gas/

	From Jie Zhang  <jie.zhang@analog.com>
	* config/bfin-parse.y (asm_1): Check AREGS in comparison
	instructions. And call yyerror () when comparing PREG with
	DREG.

gas/testsuite/:
	* gas/bfin/expected_comparison_errors.l: New test.
	* gas/bfin/expected_comparison_errors.s: New test.
	* gas/bfin/bfin.exp: Add expected_comparison_errors.

6 files changed, 51 insertions, 7 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 61996f3..1cab30a 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2008-03-26  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	From Jie Zhang  <jie.zhang@analog.com>
+	* config/bfin-parse.y (asm_1): Check AREGS in comparison
+	instructions. And call yyerror () when comparing PREG with
+	DREG.
+
 2008-03-19  Andreas Krebbel  <krebbel1@de.ibm.com>
 
 	* config/tc-s390.c (md_parse_option): z10 option added.
diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y
index df1b6f8..b320c72 100644
--- a/gas/config/bfin-parse.y
+++ b/gas/config/bfin-parse.y
@@ -1554,23 +1554,23 @@ asm_1:
 	}
 	| CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
 	{
-	  if (!REG_SAME ($3, $5))
+	  if ($3.regno == REG_A0 && $5.regno == REG_A1)
 	    {
 	      notethat ("CCflag: CC = A0 == A1\n");
 	      $$ = CCFLAG (0, 0, 5, 0, 0);
 	    }
 	  else
-	    return yyerror ("CC register expected");
+	    return yyerror ("AREGs are in bad order or same");
 	}
 	| CCREG ASSIGN REG_A LESS_THAN REG_A
 	{
-	  if (!REG_SAME ($3, $5))
+	  if ($3.regno == REG_A0 && $5.regno == REG_A1)
 	    {
 	      notethat ("CCflag: CC = A0 < A1\n");
 	      $$ = CCFLAG (0, 0, 6, 0, 0);
 	    }
 	  else
-	    return yyerror ("Register mismatch");
+	    return yyerror ("AREGs are in bad order or same");
 	}
 	| CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
 	{
@@ -1599,7 +1599,9 @@ asm_1:
 	    {
 	      notethat ("CCflag: CC = dpregs == dpregs\n");
 	      $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
-	    } 
+	    }
+	  else
+	    return yyerror ("Compare only of same register class");
 	}
 	| CCREG ASSIGN REG _ASSIGN_ASSIGN expr
 	{
@@ -1613,13 +1615,13 @@ asm_1:
 	}
 	| CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
 	{
-	  if (!REG_SAME ($3, $5))
+	  if ($3.regno == REG_A0 && $5.regno == REG_A1)
 	    {
 	      notethat ("CCflag: CC = A0 <= A1\n");
 	      $$ = CCFLAG (0, 0, 7, 0, 0);
 	    }
 	  else
-	    return yyerror ("CC register expected");
+	    return yyerror ("AREGs are in bad order or same");
 	}
 	| CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
 	{
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 8c12810..4fb1c91 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -2,6 +2,9 @@
 
 	From Jie Zhang  <jie.zhang@analog.com>
 	* gas/bfin/load.d: Update.
+	* gas/bfin/expected_comparison_errors.l: New test.
+	* gas/bfin/expected_comparison_errors.s: New test.
+	* gas/bfin/bfin.exp: Add expected_comparison_errors.
 
 2008-03-19  Andreas Krebbel  <krebbel1@de.ibm.com>
 
diff --git a/gas/testsuite/gas/bfin/bfin.exp b/gas/testsuite/gas/bfin/bfin.exp
index 9f7849b..2b8975b 100644
--- a/gas/testsuite/gas/bfin/bfin.exp
+++ b/gas/testsuite/gas/bfin/bfin.exp
@@ -12,6 +12,7 @@ if [istarget bfin*-*-*] {
 	run_dump_test "event2"
 	run_list_test "expected_errors" ""
 	run_list_test "expected_move_errors" ""
+	run_list_test "expected_comparison_errors" ""
 	run_dump_test "flow"
 	run_dump_test "flow2"
 	run_dump_test "load"
diff --git a/gas/testsuite/gas/bfin/expected_comparison_errors.l b/gas/testsuite/gas/bfin/expected_comparison_errors.l
new file mode 100644
index 0000000..12569f3
--- /dev/null
+++ b/gas/testsuite/gas/bfin/expected_comparison_errors.l
@@ -0,0 +1,16 @@
+.*: Assembler messages:
+.*:1: Error: AREGs are in bad order or same. Input text was A0.
+.*:2: Error: AREGs are in bad order or same. Input text was A1.
+.*:3: Error: AREGs are in bad order or same. Input text was A0.
+.*:4: Error: AREGs are in bad order or same. Input text was a0.
+.*:5: Error: AREGs are in bad order or same. Input text was a1.
+.*:6: Error: AREGs are in bad order or same. Input text was a0.
+.*:7: Error: AREGs are in bad order or same. Input text was a0.
+.*:8: Error: AREGs are in bad order or same. Input text was a1.
+.*:9: Error: AREGs are in bad order or same. Input text was a0.
+.*:10: Error: Compare only of same register class. Input text was P0.
+.*:11: Error: Compare only of same register class.
+.*:12: Error: Compare only of same register class.
+.*:13: Error: Compare only of same register class. Input text was R0.
+.*:14: Error: Compare only of same register class.
+.*:15: Error: Compare only of same register class.
diff --git a/gas/testsuite/gas/bfin/expected_comparison_errors.s b/gas/testsuite/gas/bfin/expected_comparison_errors.s
new file mode 100644
index 0000000..d08967b
--- /dev/null
+++ b/gas/testsuite/gas/bfin/expected_comparison_errors.s
@@ -0,0 +1,15 @@
+	CC = A0 == A0;
+	CC = A1 == A1;
+	CC = A1 == A0;
+	cc = A0 < a0;
+	cc = A1 < a1;
+	cc = A1 < a0;
+	cc = a0 <= a0;
+	cc = a1 <= a1;
+	cc = a1 <= a0;
+	CC = R0 == P0;
+	CC = R0 < P0;
+	CC = R0 <= P0;
+	CC = P0 == R0;
+	CC = P0 < R0;
+	CC = P0 <= R0;