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| author | Ian Carmichael <iancarm@cygnus> | 1998-06-16 16:02:04 +0000 |
|---|---|---|
| committer | Ian Carmichael <iancarm@cygnus> | 1998-06-16 16:02:04 +0000 |
| commit | 8ea23ea4bb5b1144540e0b00c09f710bc75ab12c (patch) | |
| tree | a4975571d41a028a9d8e84693cd2c3aeb74c5803 | |
| parent | f14defcc75432847bdbca587531734667900c7c8 (diff) | |
| download | gdb-8ea23ea4bb5b1144540e0b00c09f710bc75ab12c.zip gdb-8ea23ea4bb5b1144540e0b00c09f710bc75ab12c.tar.gz gdb-8ea23ea4bb5b1144540e0b00c09f710bc75ab12c.tar.bz2 | |
* Implement remaining bits in VPU_STAT, CMSAR0, CMSAR1, FBRST. Fix COP2 interface
* to VI registers (CFC2/CTC2).
*
* Modified Files:
* ChangeLog.sky interp.c sim-main.c sky-pke.h sky-vu.c sky-vu.h
| -rw-r--r-- | sim/mips/interp.c | 17 | ||||
| -rw-r--r-- | sim/mips/sky-pke.h | 2 |
2 files changed, 3 insertions, 16 deletions
diff --git a/sim/mips/interp.c b/sim/mips/interp.c index f0ba619..113a136 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -3440,14 +3440,7 @@ decode_coproc (SIM_DESC sd, } else /* CFC2 */ { - unsigned_4 data; - /* enum + int calculation, argh! */ - id = VU_REG_MST + 16 * id; - if (id >= VU_REG_CMSAR0) - read_vu_special_reg(&vu0_device, id, & data); - else - read_vu_misc_reg(&(vu0_device.regs), id, & data); - GPR[rt] = EXTEND32(T2H_4(data)); + GPR[rt] = vu0_read_cop2_register(id); } } else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */ @@ -3483,13 +3476,7 @@ decode_coproc (SIM_DESC sd, } else /* CTC2 */ { - unsigned_4 data = H2T_4(GPR[rt]); - /* enum + int calculation, argh! */ - id = VU_REG_VI + 16 * id; - if (id >= VU_REG_CMSAR0) - write_vu_special_reg(&vu0_device, id, & data); - else - write_vu_misc_reg(&(vu0_device.regs), id, & data); + vu0_write_cop2_register(id, GPR[rt]); } } else if(i_10_0 == 0x3bf) /* VWAITQ */ diff --git a/sim/mips/sky-pke.h b/sim/mips/sky-pke.h index 728b12b..a24e772 100644 --- a/sim/mips/sky-pke.h +++ b/sim/mips/sky-pke.h @@ -53,7 +53,7 @@ typedef unsigned_4 quadword[4]; #define GPUIF_REG_STAT_APATH_B 10 /* COP2 STAT register */ -#define COP2_REG_STAT_ADDR VPU_STAT +#define COP2_REG_STAT_ADDR VPU_STAT_ADDR #define COP2_REG_STAT_VBS1_E 8 #define COP2_REG_STAT_VBS1_B 8 #define COP2_REG_STAT_VBS0_E 0 |