* Makefile.in (ALL_MACHINES): Add v850-opc.o.

* configure: (bfd_v850v_arch) Add new case.
* configure.in: (bfd_v850_arch) Add new case.
* v850-opc.c: New file.

3 files changed, 239 insertions, 0 deletions

diff --git a/opcodes/.Sanitize b/opcodes/.Sanitize
index a48dfd8..9d1b3d9 100644
--- a/opcodes/.Sanitize
+++ b/opcodes/.Sanitize
@@ -31,6 +31,15 @@ else
 	lose_these_too="${d10v_files} ${lose_these_too}"
 fi
 
+v850_files="v850-opc.c"
+
+if ( echo $* | grep keep\-v850 > /dev/null ) ; then
+	keep_these_too="${v850_files} ${keep_these_too}"
+else
+	lose_these_too="${v850_files} ${lose_these_too}"
+fi
+
+
 # All files listed between the "Things-to-keep:" line and the
 # "Files-to-sed:" line will be kept.  All other files will be removed.
 # Directories listed in this section will have their own Sanitize
@@ -75,6 +84,7 @@ sh-dis.c
 sparc-dis.c
 sparc-opc.c
 sysdep.h
+v850-opc.c
 w65-dis.c
 w65-opc.h
 z8k-dis.c
@@ -141,6 +151,35 @@ else
 	done
 fi
 
+v850_files="ChangeLog Makefile.in configure.in configure disassemble.c"
+if ( echo $* | grep keep\-v850 > /dev/null ) ; then
+	for i in $v850_files ; do
+		if test ! -d $i && (grep sanitize-v850 $i > /dev/null) ; then
+			if [ -n "${verbose}" ] ; then
+				echo Keeping v850 stuff in $i
+			fi
+		fi
+	done
+else
+	for i in $v850_files ; do
+		if test ! -d $i && (grep sanitize-v850 $i > /dev/null) ; then
+			if [ -n "${verbose}" ] ; then
+				echo Removing traces of \"v850\" from $i...
+			fi
+			cp $i new
+			sed '/start\-sanitize\-v850/,/end-\sanitize\-v850/d' < $i > new
+			if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
+				if [ -n "${verbose}" ] ; then
+					echo Caching $i in .Recover...
+				fi
+				mv $i .Recover
+			fi
+			mv new $i
+		fi
+	done
+fi
+
+
 for i in * ; do
 	if test ! -d $i && (grep sanitize $i > /dev/null) ; then
 		echo '***' Some mentions of Sanitize are still left in $i! 1>&2
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 232fada..e6eec05 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,12 @@
+start-sanitize-v850
+Tue Aug 20 14:41:03 1996  J.T. Conklin  <jtc@hippo.cygnus.com>
+
+	* Makefile.in (ALL_MACHINES): Add v850-opc.o.
+	* configure: (bfd_v850v_arch) Add new case.
+	* configure.in: (bfd_v850_arch) Add new case.
+	* v850-opc.c: New file.
+	
+end-sanitize-v850
 Mon Aug 19 15:21:38 1996  Doug Evans  <dje@canuck.cygnus.com>
 
 	* sparc-dis.c (print_insn_sparc): Handle little endian sparcs.
diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
new file mode 100644
index 0000000..af14247
--- /dev/null
+++ b/opcodes/v850-opc.c
@@ -0,0 +1,191 @@
+#include "ansidecl.h"
+#include "opcode/v850.h"
+
+/* regular opcode */
+#define OP(x)		((x & 0x3f) << 5)
+#define OP_MASK		OP(0x3f)
+
+/* conditional branch opcode */
+#define BOP(x)		((0x0b << 7) | (x & 0x0f))
+#define BOP_MASK	((0x0b << 7) | 0x0f)
+
+/* one-word opcodes */
+#define one(x)		((unsigned int) (x))
+
+/* two-word opcodes */
+#define two(x,y)	((unsigned int) (y) | ((unsigned int) (x) << 16))
+
+
+
+const struct v850_operand v850_operands[] = {
+#define UNUSED	0
+  { 0, 0 }, 
+
+/* The R1 field in a format 1, 6, 7, or 9 insn. */
+#define R1	(UNUSED+1)
+  { 5, 0 }, 
+
+/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
+#define R2	(R1+1)
+  { 5, 11 },
+
+/* The IMM5 field in a format 2 insn. */
+#define I5	(R2+1)
+  { 5, 0 }, 
+
+#define IMM16 field in a format 6 insn. */
+#define I16	(I5+1)
+  { 16, 0 }, 
+
+/* The DISP6 field in a format 4 insn. */
+#define D6	(I16+1)
+  { 6, 1 },
+
+/* The DISP8 field in a format 3 insn. */
+#define D8	(D6+1)
+  { 9, 0 },
+
+/* The DISP16 field in a format 6 insn. */
+#define D16	(D8+1)
+  { 16, 0 }, 
+
+/* The DISP22 field in a format 4 insn. */
+#define D22	(D16+1)
+  { 16, 0 }
+} ; 
+
+
+/* reg-reg instruction format (Format I) */
+#define IF1	{R1, R2}
+
+/* imm-reg instruction format (Format II) */
+#define IF2	{I5, R2}
+
+/* conditional branch instruction format (Format III) */
+#define IF3	{D8}
+
+/* 16-bit load/store instruction (Format IV) */
+#define IF4	{D6}
+
+/* Jump instruction (Format V) */
+#define IF5	{D22}
+
+/* 3 operand instruction (Format VI) */
+#define IF6	{R1, R2, I16}
+
+/* 32-bit load/store instruction (Format VII) */
+#define IF7	{R1, R2, D16}
+
+/* Bit manipulation function 
+
+
+
+/* The opcode table.
+
+   The format of the opcode table is:
+
+   NAME		OPCODE		MASK		{ OPERANDS }
+
+   NAME is the name of the instruction.
+   OPCODE is the instruction opcode.
+   MASK is the opcode mask; this is used to tell the disassembler
+     which bits in the actual opcode must match OPCODE.
+   OPERANDS is the list of operands.
+
+   The disassembler reads the table in order and prints the first
+   instruction which matches, so this table is sorted to put more
+   specific instructions before more general instructions.  It is also
+   sorted by major opcode.  */
+
+const struct v850_opcode v850_opcodes[] = {
+/* load/store instructions */
+/* XXX */
+
+/* arithmetic operation instructions */
+{ "add",	OP(0x0e),		OP_MASK,	IF1 },
+{ "add",	OP(0x12),		OP_MASK,	IF2 },
+{ "addi",	OP(0x30),		OP_MASK,	IF6 },
+{ "sub",	OP(0x0d),		OP_MASK,	IF1 },
+{ "subr", 	OP(0x0c),		OP_MASK,	IF1 },
+{ "mulh",	OP(0x07),		OP_MASK,	IF1 },
+{ "mulh",	OP(0x17),		OP_MASK,	IF2 },
+{ "mulhi",	OP(0x37),		OP_MASK,	IF6 },
+{ "divh",	OP(0x02),		OP_MASK,	IF1 },
+{ "cmp",	OP(0x0f),		OP_MASK,	IF1 },
+{ "cmp",	OP(0x13),		OP_MASK,	IF2 },
+/* XXX missing setf */
+
+/* saturated operation instructions */
+{ "satadd",	OP(0x06),		OP_MASK,	IF1 },
+{ "satadd",	OP(0x11),		OP_MASK,	IF2 },
+{ "satsub",	OP(0x05),		OP_MASK,	IF1 },
+{ "satsubi",	OP(0x33),		OP_MASK,	IF6 },
+{ "satsubr",	OP(0x04),		OP_MASK,	IF1 },
+
+/* logical operation instructions */
+{ "tst",	OP(0x0b),		OP_MASK,	IF1 },
+{ "or",		OP(0x08),		OP_MASK,	IF1 },
+{ "ori",	OP(0x34),		OP_MASK,	IF6 },
+{ "and",	OP(0x0a),		OP_MASK,	IF1 },
+{ "andi",	OP(0x36),		OP_MASK,	IF6 },
+{ "xor",	OP(0x09),		OP_MASK,	IF1 },
+{ "xori",	OP(0x35),		OP_MASK,	IF6 },
+{ "not",	OP(0x01),		OP_MASK,	IF1 },
+{ "sar",	OP(0x15),		OP_MASK,	IF2 },
+{ "sar",	two(0x07e0,0x00a0),	two(0x07e0,0xffff),	{R1,R2} },
+{ "shl",	OP(0x16),		OP_MASK,		IF2 },
+{ "shl",	two(0x07e0,0x00c0),	two(0x07e0,0xffff),	{R1,R2} },
+{ "shr",	OP(0x14),		OP_MASK,		IF2 },
+{ "shr",	two(0x07e0,0x0080),	two(0x07e0,0xffff),	{R1,R2} },
+
+/* branch instructions */
+{ "bv",		BOP(0x0),		BOP_MASK,	IF3 },
+{ "bnv",	BOP(0x8),		BOP_MASK,	IF3 },
+{ "bc",		BOP(0x1),		BOP_MASK,	IF3 },
+{ "bl",		BOP(0x1),		BOP_MASK,	IF3 },
+{ "bnc",	BOP(0x9),		BOP_MASK,	IF3 },
+{ "bnl",	BOP(0x9),		BOP_MASK,	IF3 },
+{ "bz",		BOP(0x2),		BOP_MASK,	IF3 },
+{ "be",		BOP(0x2),		BOP_MASK,	IF3 },
+{ "bnz",	BOP(0xa),		BOP_MASK,	IF3 },
+{ "bne",	BOP(0xa),		BOP_MASK,	IF3 },
+{ "bnh",	BOP(0x3),		BOP_MASK,	IF3 },
+{ "bh",		BOP(0xb),		BOP_MASK,	IF3 },
+{ "bn",		BOP(0x4),		BOP_MASK,	IF3 },
+{ "bp",		BOP(0xc),		BOP_MASK,	IF3 },
+{ "bt",		BOP(0x5),		BOP_MASK,	IF3 },
+{ "bsa",	BOP(0xd),		BOP_MASK,	IF3 },
+{ "blt",	BOP(0x6),		BOP_MASK,	IF3 },
+{ "bge",	BOP(0xe),		BOP_MASK,	IF3 },
+{ "ble",	BOP(0x7),		BOP_MASK,	IF3 },
+{ "bgt",	BOP(0xf),		BOP_MASK,	IF3 },
+
+{ "jmp",	one(0x0060),		one(0xffe0),	IF1 },
+{ "jarl",	one(0x0780),		one(0xf83f),	{ R2,D22 } }, 
+{ "jr",		one(0x0780),		one(0xffe0),	{ D22 } },
+
+#if 0
+/* bit manipulation instructions */
+{ "set1",	one(0x07c0),		one(0xc7e0),	{B3, R1, D16} },
+{ "not1",	one(0x47c0),		one(0xc7e0),	{B3, R1, D16} },
+{ "clr1",	one(0x87c0),		one(0xc7e0),	{B3, R1, D16} },
+{ "tst1",	one(0xc7c0),		one(0xc7e0),	{B3, R1, D16} },
+#endif
+
+/* special instructions */
+{ "di",		two(0x07e0,0x0160),	two(0xffff,0xffff),	{0} },
+{ "ei",		two(0x87e0,0x0160),	two(0xffff,0xffff),	{0} },
+{ "halt",	two(0x07e0,0x0120),	two(0xffff,0xffff),	{0} },
+{ "reti",	two(0x07e0,0x0140),	two(0xffff,0xffff),	{0} },
+#if 0
+{ "trap",	two(0x07e0,0x0100),	two(0xffe0,0xffff),	{I5} },
+#endif
+{ "ldsr",	two(0x07e0,0x0020),	two(0x07e0,0xffff),	{0} },
+{ "stsr",	two(0x07e0,0x0040),	two(0x07e0,0xffff),	{0} },
+{ "nop",	one(0x00),		one(0xff),		{0} },
+
+} ;
+
+const int v850_num_opcodes =
+  sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
+