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| author | Andrew Carlotti <andrew.carlotti@arm.com> | 2024-01-19 13:01:40 +0000 |
|---|---|---|
| committer | Andrew Carlotti <andrew.carlotti@arm.com> | 2024-01-26 14:58:00 +0000 |
| commit | 0aac62aa3256719c37be9e0ce6af8b190f45c928 (patch) | |
| tree | ed18a641609d6b72bd12e9e13ae203a545b02f26 | |
| parent | c8567a87a60cf5820ebc5d98c025e91e2735f373 (diff) | |
| download | gdb-0aac62aa3256719c37be9e0ce6af8b190f45c928.zip gdb-0aac62aa3256719c37be9e0ce6af8b190f45c928.tar.gz gdb-0aac62aa3256719c37be9e0ce6af8b190f45c928.tar.bz2 | |
aarch64: move SHA512 instructions to +sha3
SHA512 instructions were added to the architecture at the same time as SHA3
instructions, but later than the SHA1 and SHA256 instructions. Furthermore,
implementations must support either both or neither of the SHA512 and SHA3
instruction sets. However, SHA512 instructions were originally (and
incorrectly) added to Binutils under the +sha2 flag.
This patch moves SHA512 instructions under the +sha3 flag, which matches the
architecture constraints and existing GCC and LLVM behaviour.
| -rw-r--r-- | opcodes/aarch64-tbl.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 66d68c0..9ea4de0 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -6047,11 +6047,11 @@ const struct aarch64_opcode aarch64_opcode_table[] = DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), DOT_INSN ("udot", 0x2f00e000, 0xbf00f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), DOT_INSN ("sdot", 0xf00e000, 0xbf00f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), -/* Crypto SHA2 (optional in ARMv8.2-a). */ - SHA2_INSN ("sha512h", 0xce608000, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0), - SHA2_INSN ("sha512h2", 0xce608400, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0), - SHA2_INSN ("sha512su0", 0xcec08000, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME2D, 0), - SHA2_INSN ("sha512su1", 0xce608800, 0xffe0fc00, cryptosha2, OP3 (Vd, Vn, Vm), QL_V3SAME2D, 0), +/* Crypto SHA512 (optional in ARMv8.2-a). */ + SHA3_INSN ("sha512h", 0xce608000, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0), + SHA3_INSN ("sha512h2", 0xce608400, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0), + SHA3_INSN ("sha512su0", 0xcec08000, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME2D, 0), + SHA3_INSN ("sha512su1", 0xce608800, 0xffe0fc00, cryptosha2, OP3 (Vd, Vn, Vm), QL_V3SAME2D, 0), /* Crypto SHA3 (optional in ARMv8.2-a). */ SHA3_INSN ("eor3", 0xce000000, 0xffe08000, cryptosha3, OP4 (Vd, Vn, Vm, Va), QL_V4SAME16B, 0), SHA3_INSN ("rax1", 0xce608c00, 0xffe0fc00, cryptosha3, OP3 (Vd, Vn, Vm), QL_V3SAME2D, 0), |