Disallow VEX/EVEX encoded instructions in 16-bit mode

gas/

	PR gas/17421
	* config/tc-i386.c (md_assemble): Disallow VEX/EVEX encoded
	instructions in 16-bit mode.

gas/testsuite/

	PR gas/17421
	* gas/i386/i386.exp: Run inval-16.

	* gas/i386/inval-16.l: New file.
	* gas/i386/inval-16.s: Likewise.

6 files changed, 57 insertions, 4 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9d512b6..7471e53 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2014-09-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/17421
+	* config/tc-i386.c (md_assemble): Disallow VEX/EVEX encoded
+	instructions in 16-bit mode.
+
 2014-09-22  Alan Modra  <amodra@gmail.com>
 
 	* config/tc-m68k.c (md_assemble): Add assert to work around
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index fa4ea11..68ca7e4 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3633,11 +3633,20 @@ md_assemble (char *line)
       as_warn (_("translating to `%sp'"), i.tm.name);
     }
 
-  if (i.tm.opcode_modifier.vex)
-    build_vex_prefix (t);
+  if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
+    {
+      if (flag_code == CODE_16BIT)
+	{
+	  as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
+		  i.tm.name);
+	  return;
+	}
 
-  if (i.tm.opcode_modifier.evex)
-    build_evex_prefix ();
+      if (i.tm.opcode_modifier.vex)
+	build_vex_prefix (t);
+      else
+	build_evex_prefix ();
+    }
 
   /* Handle conversion of 'int $3' --> special int3 insn.  XOP or FMA4
      instructions may define INT_OPCODE as well, so avoid this corner
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index f8a85bc..e740c02 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2014-09-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/17421
+	* gas/i386/i386.exp: Run inval-16.
+
+	* gas/i386/inval-16.l: New file.
+	* gas/i386/inval-16.s: Likewise.
+
 2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* gas/i386/cdr.d: New file.
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 7549a40..c55f3bf 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -42,6 +42,7 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_list_test "float" "-al -mmnemonic=att"
     run_list_test "general" "-al --listing-lhs-width=2 -mold-gcc"
     run_list_test "inval" "-al"
+    run_list_test "inval-16" "-al"
     run_list_test "segment" "-al"
     run_list_test "inval-seg" "-al"
     run_list_test "inval-reg" "-al"
diff --git a/gas/testsuite/gas/i386/inval-16.l b/gas/testsuite/gas/i386/inval-16.l
new file mode 100644
index 0000000..e1e6a43
--- /dev/null
+++ b/gas/testsuite/gas/i386/inval-16.l
@@ -0,0 +1,20 @@
+.*: Assembler messages:
+.*:3: Error: .*
+.*:4: Error: .*
+.*:5: Error: .*
+.*:6: Error: .*
+.*:7: Error: .*
+.*:8: Error: .*
+.*:9: Error: .*
+GAS LISTING .*
+
+
+[ 	]*1[ 	]+\.text
+[ 	]*2[ 	]+\.code16
+[ 	]*3[ 	]+vmovapd	%xmm0,%xmm1
+[ 	]*4[ 	]+vaddsd	%xmm4, %xmm5, %xmm6\{%k7\}
+[ 	]*5[ 	]+vfrczpd	%xmm7,%xmm7
+[ 	]*6[ 	]+andn    \(%eax\), %ecx, %ecx
+[ 	]*7[ 	]+bzhi    %ecx, \(%eax\), %ecx
+[ 	]*8[ 	]+llwpcb	%ecx
+[ 	]*9[ 	]+blcfill	%ecx, %ecx
diff --git a/gas/testsuite/gas/i386/inval-16.s b/gas/testsuite/gas/i386/inval-16.s
new file mode 100644
index 0000000..fd0f971
--- /dev/null
+++ b/gas/testsuite/gas/i386/inval-16.s
@@ -0,0 +1,9 @@
+	.text
+	.code16
+	vmovapd	%xmm0,%xmm1
+	vaddsd	%xmm4, %xmm5, %xmm6{%k7}
+	vfrczpd	%xmm7,%xmm7
+	andn    (%eax), %ecx, %ecx
+	bzhi    %ecx, (%eax), %ecx
+	llwpcb	%ecx
+	blcfill	%ecx, %ecx