diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2010-09-22 21:30:35 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-09-22 21:30:35 +0000 |
| commit | 9d2eed0673a525c8afecb5c9511ec47cd94bf769 (patch) | |
| tree | ed538920ed50cd5a5c8cc1aadf39b1cc689dcd3f | |
| parent | a2c28b80f1bc424f2b8858118634ea8428ffe985 (diff) | |
| download | gdb-9d2eed0673a525c8afecb5c9511ec47cd94bf769.zip gdb-9d2eed0673a525c8afecb5c9511ec47cd94bf769.tar.gz gdb-9d2eed0673a525c8afecb5c9511ec47cd94bf769.tar.bz2 | |
gas: blackfin: add missing register move insns
The Blackfin ISA supports moving just about anything to/from EMUDAT, so
make sure the assembler accepts these insns too.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/config/bfin-defs.h | 1 | ||||
| -rw-r--r-- | gas/config/bfin-parse.y | 6 |
3 files changed, 10 insertions, 2 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 947bfdd..102f307 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,10 @@ 2010-09-22 Robin Getz <robin.getz@analog.com> + * config/bfin-defs.h (IS_EMUDAT): New define. + * config/bfin-parse.y: Accept EMUDAT for any register move. + +2010-09-22 Robin Getz <robin.getz@analog.com> + * config/bfin-parse.y: Improve error messages. 2010-09-22 Robin Getz <robin.getz@analog.com> diff --git a/gas/config/bfin-defs.h b/gas/config/bfin-defs.h index 7dd9796..8217332 100644 --- a/gas/config/bfin-defs.h +++ b/gas/config/bfin-defs.h @@ -203,6 +203,7 @@ enum reg_class #define IS_BREG(r) (((r).regno & 0xf4) == T_REG_B) #define IS_LREG(r) (((r).regno & 0xf4) == T_REG_L) #define IS_CREG(r) ((r).regno == REG_LC0 || (r).regno == REG_LC1) +#define IS_EMUDAT(r) ((r).regno == REG_EMUDAT) #define IS_ALLREG(r) ((r).regno < T_NOGROUP) #define IS_GENREG(r) \ diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y index 4549b53..0dd729c 100644 --- a/gas/config/bfin-parse.y +++ b/gas/config/bfin-parse.y @@ -1728,10 +1728,12 @@ asm_1: || (IS_DAGREG ($1) && IS_DAGREG ($3)) || (IS_GENREG ($1) && $3.regno == REG_USP) || ($1.regno == REG_USP && IS_GENREG ($3)) + || ($1.regno == REG_USP && $3.regno == REG_USP) || (IS_DREG ($1) && IS_SYSREG ($3)) || (IS_PREG ($1) && IS_SYSREG ($3)) - || (IS_SYSREG ($1) && IS_DREG ($3)) - || (IS_SYSREG ($1) && IS_PREG ($3)) + || (IS_SYSREG ($1) && IS_GENREG ($3)) + || (IS_ALLREG ($1) && IS_EMUDAT ($3)) + || (IS_EMUDAT ($1) && IS_ALLREG ($3)) || (IS_SYSREG ($1) && $3.regno == REG_USP)) { $$ = bfin_gen_regmv (&$3, &$1); |