Remove -8 bias on PC-relative load instructions for arm-wince-pe target

8 files changed, 386 insertions, 6 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 4fb6f14..53f1294 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2003-12-16  Dmitry Semyonov  <Dmitry.Semyonov@oktet.ru>
+
+	* tc-arm.c (do_adr): Do not adjust pc by -8 if TE_WINCE is
+	defined.
+	(do_adrl): Likewise.
+
 2003-12-15  Christian Groessler  <chris@groessler.org>
 
 	* config/tc-z8k.c (struct z8k_exp): Remove, not used anywhere.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 85afdc2..e07185e 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7299,7 +7299,9 @@ do_adr (str)
   /* Frag hacking will turn this into a sub instruction if the offset turns
      out to be negative.  */
   inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
+#ifndef TE_WINCE
   inst.reloc.exp.X_add_number -= 8; /* PC relative adjust.  */
+#endif
   inst.reloc.pc_rel = 1;
 
   end_of_line (str);
@@ -7330,7 +7332,9 @@ do_adrl (str)
   /* Frag hacking will turn this into a sub instruction if the offset turns
      out to be negative.  */
   inst.reloc.type              = BFD_RELOC_ARM_ADRL_IMMEDIATE;
+#ifndef TE_WINCE  
   inst.reloc.exp.X_add_number -= 8; /* PC relative adjust  */
+#endif
   inst.reloc.pc_rel            = 1;
   inst.size                    = INSN_SIZE * 2;
 }
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 7d1253f..f888a80 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,14 @@
+2003-12-16  Nick Clifton  <nickc@redhat.com>
+
+	* gas/arm/arm.exp: Run special versions of the inst, ldconst,
+	arm7t and copro tests for the arm-wince-pe target.
+	* gas/arm/wince_inst.d: New file.  Like inst.d but for the
+	arm-wince-pe target where the -8 bias is not applied to
+	PC-relative load instructions.
+	* gas/arm/wince_ldconst.d: New file.  Similar reasons.
+	* gas/arm/wince_arm7t.d: New file.  Similar reasons.
+	* gas/arm/wince_copro.d: New file.  Similar reasons.
+	
 2003-12-15  Christian Groessler  <chris@groessler.org>
 
 	* gas/z8k/eidi.s: Add uppercase forms.  Add forms with comma
diff --git a/gas/testsuite/gas/arm/arm.exp b/gas/testsuite/gas/arm/arm.exp
index 80f9c92..9eef1b3 100644
--- a/gas/testsuite/gas/arm/arm.exp
+++ b/gas/testsuite/gas/arm/arm.exp
@@ -15,9 +15,18 @@ proc run_errors_test { name opts tname} {
 }
 
 if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
-    run_dump_test "inst"
 
-    run_dump_test "ldconst"
+    if {[istarget *-wince-*]} then {
+	run_dump_test "wince_inst"
+	run_dump_test "wince_ldconst"
+	run_dump_test "wince_arm7t"
+	run_dump_test "wince_copro"
+    } else {
+	run_dump_test "inst"
+	run_dump_test "ldconst"
+	run_dump_test "arm7t"
+	run_dump_test "copro"
+    }
 
     run_dump_test "armv1"
 
@@ -29,8 +38,6 @@ if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
 
     gas_test "arm7dm.s" "-mcpu=arm7dm" $stdoptlist "Arm 7DM instructions"
 
-    run_dump_test "arm7t"
-
     if {! [istarget arm*-*-aout] && ![istarget arm-*-pe]} then {
 	# The arm-aout port does not support Thumb mode.
 	gas_test "thumb.s" "-mcpu=arm7t" $stdoptlist "Thumb instructions"
@@ -40,8 +47,6 @@ if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
 
     run_dump_test "arch5tej"
 
-    run_dump_test "copro"
-
     gas_test "immed.s" "" $stdoptlist "immediate expressions"
 
     gas_test "float.s" "-mcpu=arm7tdmi -mfpu=fpa" $stdoptlist "Core floating point instructions"
diff --git a/gas/testsuite/gas/arm/wince_arm7t.d b/gas/testsuite/gas/arm/wince_arm7t.d
new file mode 100644
index 0000000..9d9b87f
--- /dev/null
+++ b/gas/testsuite/gas/arm/wince_arm7t.d
@@ -0,0 +1,75 @@
+#objdump: -Dr --prefix-addresses --show-raw-insn
+#name: ARM arm7t (WinCE version)
+#as: -mcpu=arm7t -EL
+#source: arm7t.s
+
+# This file is the same as arm7t.d except that the PC-relative
+# LDR[S]H instructions have not had a -8 bias inserted.
+
+
+# Test the halfword and signextend memory transfers:
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+00 <[^>]*> e1d100b0 ?	ldrh	r0, \[r1\]
+0+04 <[^>]*> e1f100b0 ?	ldrh	r0, \[r1\]!
+0+08 <[^>]*> e19100b2 ?	ldrh	r0, \[r1, r2\]
+0+0c <[^>]*> e1b100b2 ?	ldrh	r0, \[r1, r2\]!
+0+10 <[^>]*> e1d100bc ?	ldrh	r0, \[r1, #12\]
+0+14 <[^>]*> e1f100bc ?	ldrh	r0, \[r1, #12\]!
+0+18 <[^>]*> e15100bc ?	ldrh	r0, \[r1, #-12\]
+0+1c <[^>]*> e09100b2 ?	ldrh	r0, \[r1\], r2
+0+20 <[^>]*> e3a00cff ?	mov	r0, #65280	; 0xff00
+0+24 <[^>]*> e1df0abc ?	ldrh	r0, \[pc, #172\]	; 0+d8 <[^>]*>
+0+28 <[^>]*> e1df0abc ?	ldrh	r0, \[pc, #172\]	; 0+dc <[^>]*>
+0+2c <[^>]*> e1c100b0 ?	strh	r0, \[r1\]
+0+30 <[^>]*> e1e100b0 ?	strh	r0, \[r1\]!
+0+34 <[^>]*> e18100b2 ?	strh	r0, \[r1, r2\]
+0+38 <[^>]*> e1a100b2 ?	strh	r0, \[r1, r2\]!
+0+3c <[^>]*> e1c100bc ?	strh	r0, \[r1, #12\]
+0+40 <[^>]*> e1e100bc ?	strh	r0, \[r1, #12\]!
+0+44 <[^>]*> e14100bc ?	strh	r0, \[r1, #-12\]
+0+48 <[^>]*> e08100b2 ?	strh	r0, \[r1\], r2
+0+4c <[^>]*> e1cf08b8 ?	strh	r0, \[pc, #136\]	; 0+dc <[^>]*>
+0+50 <[^>]*> e1d100d0 ?	ldrsb	r0, \[r1\]
+0+54 <[^>]*> e1f100d0 ?	ldrsb	r0, \[r1\]!
+0+58 <[^>]*> e19100d2 ?	ldrsb	r0, \[r1, r2\]
+0+5c <[^>]*> e1b100d2 ?	ldrsb	r0, \[r1, r2\]!
+0+60 <[^>]*> e1d100dc ?	ldrsb	r0, \[r1, #12\]
+0+64 <[^>]*> e1f100dc ?	ldrsb	r0, \[r1, #12\]!
+0+68 <[^>]*> e15100dc ?	ldrsb	r0, \[r1, #-12\]
+0+6c <[^>]*> e09100d2 ?	ldrsb	r0, \[r1\], r2
+0+70 <[^>]*> e3a000de ?	mov	r0, #222	; 0xde
+0+74 <[^>]*> e1df06d0 ?	ldrsb	r0, \[pc, #96\]	; 0+dc <[^>]*>
+0+78 <[^>]*> e1d100f0 ?	ldrsh	r0, \[r1\]
+0+7c <[^>]*> e1f100f0 ?	ldrsh	r0, \[r1\]!
+0+80 <[^>]*> e19100f2 ?	ldrsh	r0, \[r1, r2\]
+0+84 <[^>]*> e1b100f2 ?	ldrsh	r0, \[r1, r2\]!
+0+88 <[^>]*> e1d100fc ?	ldrsh	r0, \[r1, #12\]
+0+8c <[^>]*> e1f100fc ?	ldrsh	r0, \[r1, #12\]!
+0+90 <[^>]*> e15100fc ?	ldrsh	r0, \[r1, #-12\]
+0+94 <[^>]*> e09100f2 ?	ldrsh	r0, \[r1\], r2
+0+98 <[^>]*> e3a00cff ?	mov	r0, #65280	; 0xff00
+0+9c <[^>]*> e1df03f4 ?	ldrsh	r0, \[pc, #52\]	; 0+d8 <[^>]*>
+0+a0 <[^>]*> e1df03f4 ?	ldrsh	r0, \[pc, #52\]	; 0+dc <[^>]*>
+0+a4 <[^>]*> e19100b2 ?	ldrh	r0, \[r1, r2\]
+0+a8 <[^>]*> 119100b2 ?	ldrneh	r0, \[r1, r2\]
+0+ac <[^>]*> 819100b2 ?	ldrhih	r0, \[r1, r2\]
+0+b0 <[^>]*> b19100b2 ?	ldrlth	r0, \[r1, r2\]
+0+b4 <[^>]*> e19100f2 ?	ldrsh	r0, \[r1, r2\]
+0+b8 <[^>]*> 119100f2 ?	ldrnesh	r0, \[r1, r2\]
+0+bc <[^>]*> 819100f2 ?	ldrhish	r0, \[r1, r2\]
+0+c0 <[^>]*> b19100f2 ?	ldrltsh	r0, \[r1, r2\]
+0+c4 <[^>]*> e19100d2 ?	ldrsb	r0, \[r1, r2\]
+0+c8 <[^>]*> 119100d2 ?	ldrnesb	r0, \[r1, r2\]
+0+cc <[^>]*> 819100d2 ?	ldrhisb	r0, \[r1, r2\]
+0+d0 <[^>]*> b19100d2 ?	ldrltsb	r0, \[r1, r2\]
+0+d4 <[^>]*> e15f00f4 ?	ldrsh	r0, \[pc, #-4\]	; 0+d8 <[^>]*>
+0+d8 <[^>]*> e15f00f4 ?	ldrsh	r0, \[pc, #-4\]	; 0+dc <[^>]*>
+0+dc <[^>]*> 00000000 ?	andeq	r0, r0, r0
+[		]*dc:.*fred
+0+e0 <[^>]*> 0000c0de ?	.*
+0+e4 <[^>]*> 0000dead ?	.*
+0+e8 <[^>]*> e1a00000 ?	nop[ 	]+\(mov r0,r0\)
+0+ec <[^>]*> e1a00000 ?	nop[ 	]+\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/wince_copro.d b/gas/testsuite/gas/arm/wince_copro.d
new file mode 100644
index 0000000..91097dd
--- /dev/null
+++ b/gas/testsuite/gas/arm/wince_copro.d
@@ -0,0 +1,45 @@
+#objdump: -dr --prefix-addresses --show-raw-insn --architecture=armv5te
+#name: ARM CoProcessor Instructions (WinCE version)
+#as: -march=armv5te -EL
+#source: copro.s
+
+# This file is the same as copro.d except that the PC-relative
+# LDC and STFS instructions have not had a -8 bias inserted.
+
+# Test the standard ARM co-processor instructions:
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> ee421103 	dvfs	f1, f2, f3
+0+004 <[^>]*> 0e3414a5 	cfadddeq	mvd1, mvd4, mvd5
+0+008 <[^>]*> ed939500 	cfldr32	mvfx9, \[r3\]
+0+00c <[^>]*> edd1e108 	ldfp	f6, \[r1, #32\]
+0+010 <[^>]*> 4db200ff 	ldcmi	0, cr0, \[r2, #1020\]!
+0+014 <[^>]*> 5cf31710 	ldcpll	7, cr1, \[r3\], #64
+0+018 <[^>]*> ed1f8003 	ldc	0, cr8, \[pc, #-12\]
+0+01c <[^>]*> ed830500 	cfstr32	mvfx0, \[r3\]
+0+020 <[^>]*> edc0f302 	stcl	3, cr15, \[r0, #8\]
+0+024 <[^>]*> 0da2c419 	cfstrseq	mvf12, \[r2, #100\]!
+0+028 <[^>]*> 3ca4860c 	stccc	6, cr8, \[r4\], #48
+0+02c <[^>]*> ed0f7103 	stfs	f7, \[pc, #-12\]
+0+030 <[^>]*> ee715212 	mrc	2, 3, r5, cr1, cr2, \{0\}
+0+034 <[^>]*> aeb1f4f2 	mrcge	4, 5, pc, cr1, cr2, \{7\}
+0+038 <[^>]*> ee21f711 	mcr	7, 1, pc, cr1, cr1, \{0\}
+0+03c <[^>]*> be228519 	cfsh64lt	mvdx8, mvdx2, #9
+0+040 <[^>]*> ec907300 	ldc	3, cr7, \[r0\], \{0\}
+0+044 <[^>]*> ec816e01 	stc	14, cr6, \[r1\], \{1\}
+0+048 <[^>]*> fc925502 	ldc2	5, cr5, \[r2\], \{2\}
+0+04c <[^>]*> fc834603 	stc2	6, cr4, \[r3\], \{3\}
+0+050 <[^>]*> ecd43704 	ldcl	7, cr3, \[r4\], \{4\}
+0+054 <[^>]*> ecc52805 	stcl	8, cr2, \[r5\], \{5\}
+0+058 <[^>]*> fcd61906 	ldc2l	9, cr1, \[r6\], \{6\}
+0+05c <[^>]*> fcc70a07 	stc2l	10, cr0, \[r7\], \{7\}
+0+060 <[^>]*> ecd88bff 	ldcl	11, cr8, \[r8\], \{255\}
+0+064 <[^>]*> ecc99cfe 	stcl	12, cr9, \[r9\], \{254\}
+0+068 <[^>]*> ec507d04 	mrrc	13, 0, r7, r0, cr4
+0+06c <[^>]*> ec407e05 	mcrr	14, 0, r7, r0, cr5
+0+070 <[^>]*> ec507fff 	mrrc	15, 15, r7, r0, cr15
+0+074 <[^>]*> ec407efe 	mcrr	14, 15, r7, r0, cr14
+0+078 <[^>]*> e1a00000 	nop			\(mov r0,r0\)
+0+07c <[^>]*> e1a00000 	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/wince_inst.d b/gas/testsuite/gas/arm/wince_inst.d
new file mode 100644
index 0000000..2543f0b
--- /dev/null
+++ b/gas/testsuite/gas/arm/wince_inst.d
@@ -0,0 +1,203 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: ARM basic instructions (WinCE version)
+#as: -mcpu=arm7m -EL
+#source: inst.s
+
+# This file is the same as inst.d except that the BL
+# instructions have not had a -8 bias inserted.
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> e3a00000 ?	mov	r0, #0	; 0x0
+0+004 <[^>]*> e1a01002 ?	mov	r1, r2
+0+008 <[^>]*> e1a03184 ?	mov	r3, r4, lsl #3
+0+00c <[^>]*> e1a05736 ?	mov	r5, r6, lsr r7
+0+010 <[^>]*> e1a08a59 ?	mov	r8, r9, asr sl
+0+014 <[^>]*> e1a0bd1c ?	mov	fp, ip, lsl sp
+0+018 <[^>]*> e1a0e06f ?	mov	lr, pc, rrx
+0+01c <[^>]*> e1a01002 ?	mov	r1, r2
+0+020 <[^>]*> 01a02003 ?	moveq	r2, r3
+0+024 <[^>]*> 11a04005 ?	movne	r4, r5
+0+028 <[^>]*> b1a06007 ?	movlt	r6, r7
+0+02c <[^>]*> a1a08009 ?	movge	r8, r9
+0+030 <[^>]*> d1a0a00b ?	movle	sl, fp
+0+034 <[^>]*> c1a0c00d ?	movgt	ip, sp
+0+038 <[^>]*> 31a01002 ?	movcc	r1, r2
+0+03c <[^>]*> 21a01003 ?	movcs	r1, r3
+0+040 <[^>]*> 41a03006 ?	movmi	r3, r6
+0+044 <[^>]*> 51a07009 ?	movpl	r7, r9
+0+048 <[^>]*> 61a01008 ?	movvs	r1, r8
+0+04c <[^>]*> 71a09fa1 ?	movvc	r9, r1, lsr #31
+0+050 <[^>]*> 81a0800f ?	movhi	r8, pc
+0+054 <[^>]*> 91a0f00e ?	movls	pc, lr
+0+058 <[^>]*> 21a09008 ?	movcs	r9, r8
+0+05c <[^>]*> 31a01003 ?	movcc	r1, r3
+0+060 <[^>]*> e1b00008 ?	movs	r0, r8
+0+064 <[^>]*> 31b00007 ?	movccs	r0, r7
+0+068 <[^>]*> e281000a ?	add	r0, r1, #10	; 0xa
+0+06c <[^>]*> e0832004 ?	add	r2, r3, r4
+0+070 <[^>]*> e0865287 ?	add	r5, r6, r7, lsl #5
+0+074 <[^>]*> e0821113 ?	add	r1, r2, r3, lsl r1
+0+078 <[^>]*> e201000a ?	and	r0, r1, #10	; 0xa
+0+07c <[^>]*> e0032004 ?	and	r2, r3, r4
+0+080 <[^>]*> e0065287 ?	and	r5, r6, r7, lsl #5
+0+084 <[^>]*> e0021113 ?	and	r1, r2, r3, lsl r1
+0+088 <[^>]*> e221000a ?	eor	r0, r1, #10	; 0xa
+0+08c <[^>]*> e0232004 ?	eor	r2, r3, r4
+0+090 <[^>]*> e0265287 ?	eor	r5, r6, r7, lsl #5
+0+094 <[^>]*> e0221113 ?	eor	r1, r2, r3, lsl r1
+0+098 <[^>]*> e241000a ?	sub	r0, r1, #10	; 0xa
+0+09c <[^>]*> e0432004 ?	sub	r2, r3, r4
+0+0a0 <[^>]*> e0465287 ?	sub	r5, r6, r7, lsl #5
+0+0a4 <[^>]*> e0421113 ?	sub	r1, r2, r3, lsl r1
+0+0a8 <[^>]*> e2a1000a ?	adc	r0, r1, #10	; 0xa
+0+0ac <[^>]*> e0a32004 ?	adc	r2, r3, r4
+0+0b0 <[^>]*> e0a65287 ?	adc	r5, r6, r7, lsl #5
+0+0b4 <[^>]*> e0a21113 ?	adc	r1, r2, r3, lsl r1
+0+0b8 <[^>]*> e2c1000a ?	sbc	r0, r1, #10	; 0xa
+0+0bc <[^>]*> e0c32004 ?	sbc	r2, r3, r4
+0+0c0 <[^>]*> e0c65287 ?	sbc	r5, r6, r7, lsl #5
+0+0c4 <[^>]*> e0c21113 ?	sbc	r1, r2, r3, lsl r1
+0+0c8 <[^>]*> e261000a ?	rsb	r0, r1, #10	; 0xa
+0+0cc <[^>]*> e0632004 ?	rsb	r2, r3, r4
+0+0d0 <[^>]*> e0665287 ?	rsb	r5, r6, r7, lsl #5
+0+0d4 <[^>]*> e0621113 ?	rsb	r1, r2, r3, lsl r1
+0+0d8 <[^>]*> e2e1000a ?	rsc	r0, r1, #10	; 0xa
+0+0dc <[^>]*> e0e32004 ?	rsc	r2, r3, r4
+0+0e0 <[^>]*> e0e65287 ?	rsc	r5, r6, r7, lsl #5
+0+0e4 <[^>]*> e0e21113 ?	rsc	r1, r2, r3, lsl r1
+0+0e8 <[^>]*> e381000a ?	orr	r0, r1, #10	; 0xa
+0+0ec <[^>]*> e1832004 ?	orr	r2, r3, r4
+0+0f0 <[^>]*> e1865287 ?	orr	r5, r6, r7, lsl #5
+0+0f4 <[^>]*> e1821113 ?	orr	r1, r2, r3, lsl r1
+0+0f8 <[^>]*> e3c1000a ?	bic	r0, r1, #10	; 0xa
+0+0fc <[^>]*> e1c32004 ?	bic	r2, r3, r4
+0+100 <[^>]*> e1c65287 ?	bic	r5, r6, r7, lsl #5
+0+104 <[^>]*> e1c21113 ?	bic	r1, r2, r3, lsl r1
+0+108 <[^>]*> e3e0000a ?	mvn	r0, #10	; 0xa
+0+10c <[^>]*> e1e02004 ?	mvn	r2, r4
+0+110 <[^>]*> e1e05287 ?	mvn	r5, r7, lsl #5
+0+114 <[^>]*> e1e01113 ?	mvn	r1, r3, lsl r1
+0+118 <[^>]*> e310000a ?	tst	r0, #10	; 0xa
+0+11c <[^>]*> e1120004 ?	tst	r2, r4
+0+120 <[^>]*> e1150287 ?	tst	r5, r7, lsl #5
+0+124 <[^>]*> e1110113 ?	tst	r1, r3, lsl r1
+0+128 <[^>]*> e330000a ?	teq	r0, #10	; 0xa
+0+12c <[^>]*> e1320004 ?	teq	r2, r4
+0+130 <[^>]*> e1350287 ?	teq	r5, r7, lsl #5
+0+134 <[^>]*> e1310113 ?	teq	r1, r3, lsl r1
+0+138 <[^>]*> e350000a ?	cmp	r0, #10	; 0xa
+0+13c <[^>]*> e1520004 ?	cmp	r2, r4
+0+140 <[^>]*> e1550287 ?	cmp	r5, r7, lsl #5
+0+144 <[^>]*> e1510113 ?	cmp	r1, r3, lsl r1
+0+148 <[^>]*> e370000a ?	cmn	r0, #10	; 0xa
+0+14c <[^>]*> e1720004 ?	cmn	r2, r4
+0+150 <[^>]*> e1750287 ?	cmn	r5, r7, lsl #5
+0+154 <[^>]*> e1710113 ?	cmn	r1, r3, lsl r1
+0+158 <[^>]*> e330f00a ?	teqp	r0, #10	; 0xa
+0+15c <[^>]*> e132f004 ?	teqp	r2, r4
+0+160 <[^>]*> e135f287 ?	teqp	r5, r7, lsl #5
+0+164 <[^>]*> e131f113 ?	teqp	r1, r3, lsl r1
+0+168 <[^>]*> e370f00a ?	cmnp	r0, #10	; 0xa
+0+16c <[^>]*> e172f004 ?	cmnp	r2, r4
+0+170 <[^>]*> e175f287 ?	cmnp	r5, r7, lsl #5
+0+174 <[^>]*> e171f113 ?	cmnp	r1, r3, lsl r1
+0+178 <[^>]*> e350f00a ?	cmpp	r0, #10	; 0xa
+0+17c <[^>]*> e152f004 ?	cmpp	r2, r4
+0+180 <[^>]*> e155f287 ?	cmpp	r5, r7, lsl #5
+0+184 <[^>]*> e151f113 ?	cmpp	r1, r3, lsl r1
+0+188 <[^>]*> e310f00a ?	tstp	r0, #10	; 0xa
+0+18c <[^>]*> e112f004 ?	tstp	r2, r4
+0+190 <[^>]*> e115f287 ?	tstp	r5, r7, lsl #5
+0+194 <[^>]*> e111f113 ?	tstp	r1, r3, lsl r1
+0+198 <[^>]*> e0000291 ?	mul	r0, r1, r2
+0+19c <[^>]*> e0110392 ?	muls	r1, r2, r3
+0+1a0 <[^>]*> 10000091 ?	mulne	r0, r1, r0
+0+1a4 <[^>]*> 90190798 ?	mullss	r9, r8, r7
+0+1a8 <[^>]*> e021ba99 ?	mla	r1, r9, sl, fp
+0+1ac <[^>]*> e033c994 ?	mlas	r3, r4, r9, ip
+0+1b0 <[^>]*> b029d798 ?	mlalt	r9, r8, r7, sp
+0+1b4 <[^>]*> a034e391 ?	mlages	r4, r1, r3, lr
+0+1b8 <[^>]*> e5910000 ?	ldr	r0, \[r1\]
+0+1bc <[^>]*> e7911002 ?	ldr	r1, \[r1, r2\]
+0+1c0 <[^>]*> e7b32004 ?	ldr	r2, \[r3, r4\]!
+0+1c4 <[^>]*> e5922020 ?	ldr	r2, \[r2, #32\]
+0+1c8 <[^>]*> e7932424 ?	ldr	r2, \[r3, r4, lsr #8\]
+0+1cc <[^>]*> 07b54484 ?	ldreq	r4, \[r5, r4, lsl #9\]!
+0+1d0 <[^>]*> 14954006 ?	ldrne	r4, \[r5\], #6
+0+1d4 <[^>]*> e6b21003 ?	ldrt	r1, \[r2\], r3
+0+1d8 <[^>]*> e6942425 ?	ldr	r2, \[r4\], r5, lsr #8
+0+1dc <[^>]*> e51f0008 ?	ldr	r0, \[pc, #-8\]	; 0+1dc <[^>]*>
+0+1e0 <[^>]*> e5d43000 ?	ldrb	r3, \[r4\]
+0+1e4 <[^>]*> 14f85000 ?	ldrnebt	r5, \[r8\]
+0+1e8 <[^>]*> e5810000 ?	str	r0, \[r1\]
+0+1ec <[^>]*> e7811002 ?	str	r1, \[r1, r2\]
+0+1f0 <[^>]*> e7a43003 ?	str	r3, \[r4, r3\]!
+0+1f4 <[^>]*> e5822020 ?	str	r2, \[r2, #32\]
+0+1f8 <[^>]*> e7832424 ?	str	r2, \[r3, r4, lsr #8\]
+0+1fc <[^>]*> 07a54484 ?	streq	r4, \[r5, r4, lsl #9\]!
+0+200 <[^>]*> 14854006 ?	strne	r4, \[r5\], #6
+0+204 <[^>]*> e6821003 ?	str	r1, \[r2\], r3
+0+208 <[^>]*> e6a42425 ?	strt	r2, \[r4\], r5, lsr #8
+0+20c <[^>]*> e50f1004 ?	str	r1, \[pc, #-4\]	; 0+210 <[^>]*>
+0+210 <[^>]*> e5c71000 ?	strb	r1, \[r7\]
+0+214 <[^>]*> e4e02000 ?	strbt	r2, \[r0\]
+0+218 <[^>]*> e8900002 ?	ldmia	r0, {r1}
+0+21c <[^>]*> 09920038 ?	ldmeqib	r2, {r3, r4, r5}
+0+220 <[^>]*> e853ffff ?	ldmda	r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^
+0+224 <[^>]*> e93b05ff ?	ldmdb	fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl}
+0+228 <[^>]*> e99100f7 ?	ldmib	r1, {r0, r1, r2, r4, r5, r6, r7}
+0+22c <[^>]*> e89201f8 ?	ldmia	r2, {r3, r4, r5, r6, r7, r8}
+0+230 <[^>]*> e9130003 ?	ldmdb	r3, {r0, r1}
+0+234 <[^>]*> e8540300 ?	ldmda	r4, {r8, r9}\^
+0+238 <[^>]*> e8800002 ?	stmia	r0, {r1}
+0+23c <[^>]*> 09820038 ?	stmeqib	r2, {r3, r4, r5}
+0+240 <[^>]*> e843ffff ?	stmda	r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^
+0+244 <[^>]*> e92b05ff ?	stmdb	fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl}
+0+248 <[^>]*> e8010007 ?	stmda	r1, {r0, r1, r2}
+0+24c <[^>]*> e9020018 ?	stmdb	r2, {r3, r4}
+0+250 <[^>]*> e8830003 ?	stmia	r3, {r0, r1}
+0+254 <[^>]*> e9c40300 ?	stmib	r4, {r8, r9}\^
+0+258 <[^>]*> ef123456 ?	swi	0x00123456
+0+25c <[^>]*> 2f000033 ?	swics	0x00000033
+0+260 <[^>]*> eb000000 ?	bl	0+268 <[^>]*>
+[		]*260:.*_wombat.*
+0+264 <[^>]*> 5b000000 ?	blpl	0+26c <[^>]*>
+[		]*264:.*ARM.*hohum
+0+268 <[^>]*> ea000000 ?	b	0+270 <[^>]*>
+[		]*268:.*_wibble.*
+0+26c <[^>]*> da000000 ?	ble	0+274 <[^>]*>
+[		]*26c:.*testerfunc.*
+0+270 <[^>]*> e1a01102 ?	mov	r1, r2, lsl #2
+0+274 <[^>]*> e1a01002 ?	mov	r1, r2
+0+278 <[^>]*> e1a01f82 ?	mov	r1, r2, lsl #31
+0+27c <[^>]*> e1a01312 ?	mov	r1, r2, lsl r3
+0+280 <[^>]*> e1a01122 ?	mov	r1, r2, lsr #2
+0+284 <[^>]*> e1a01fa2 ?	mov	r1, r2, lsr #31
+0+288 <[^>]*> e1a01022 ?	mov	r1, r2, lsr #32
+0+28c <[^>]*> e1a01332 ?	mov	r1, r2, lsr r3
+0+290 <[^>]*> e1a01142 ?	mov	r1, r2, asr #2
+0+294 <[^>]*> e1a01fc2 ?	mov	r1, r2, asr #31
+0+298 <[^>]*> e1a01042 ?	mov	r1, r2, asr #32
+0+29c <[^>]*> e1a01352 ?	mov	r1, r2, asr r3
+0+2a0 <[^>]*> e1a01162 ?	mov	r1, r2, ror #2
+0+2a4 <[^>]*> e1a01fe2 ?	mov	r1, r2, ror #31
+0+2a8 <[^>]*> e1a01372 ?	mov	r1, r2, ror r3
+0+2ac <[^>]*> e1a01062 ?	mov	r1, r2, rrx
+0+2b0 <[^>]*> e1a01102 ?	mov	r1, r2, lsl #2
+0+2b4 <[^>]*> e1a01002 ?	mov	r1, r2
+0+2b8 <[^>]*> e1a01f82 ?	mov	r1, r2, lsl #31
+0+2bc <[^>]*> e1a01312 ?	mov	r1, r2, lsl r3
+0+2c0 <[^>]*> e1a01122 ?	mov	r1, r2, lsr #2
+0+2c4 <[^>]*> e1a01fa2 ?	mov	r1, r2, lsr #31
+0+2c8 <[^>]*> e1a01022 ?	mov	r1, r2, lsr #32
+0+2cc <[^>]*> e1a01332 ?	mov	r1, r2, lsr r3
+0+2d0 <[^>]*> e1a01142 ?	mov	r1, r2, asr #2
+0+2d4 <[^>]*> e1a01fc2 ?	mov	r1, r2, asr #31
+0+2d8 <[^>]*> e1a01042 ?	mov	r1, r2, asr #32
+0+2dc <[^>]*> e1a01352 ?	mov	r1, r2, asr r3
+0+2e0 <[^>]*> e1a01162 ?	mov	r1, r2, ror #2
+0+2e4 <[^>]*> e1a01fe2 ?	mov	r1, r2, ror #31
+0+2e8 <[^>]*> e1a01372 ?	mov	r1, r2, ror r3
+0+2ec <[^>]*> e1a01062 ?	mov	r1, r2, rrx
diff --git a/gas/testsuite/gas/arm/wince_ldconst.d b/gas/testsuite/gas/arm/wince_ldconst.d
new file mode 100644
index 0000000..131b4b5
--- /dev/null
+++ b/gas/testsuite/gas/arm/wince_ldconst.d
@@ -0,0 +1,31 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: ARM ldr with immediate constant (WinCE version)
+#as: -mcpu=arm7m -EL
+#source: ldconst.s
+
+# This file is the same as ldconst.d except that the PC-
+# relative LDR instructions have not had a -8 bias inserted.
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+00 <[^>]*> e3a00000 ?	mov	r0, #0	; 0x0
+0+04 <[^>]*> e3a004ff ?	mov	r0, #-16777216	; 0xff000000
+0+08 <[^>]*> e3e00000 ?	mvn	r0, #0	; 0x0
+0+0c <[^>]*> e51f000c ?	ldr	r0, \[pc, #-12\]	; 0+08 <[^>]*>
+0+10 <[^>]*> 0fff0000 ?	.*
+0+14 <[^>]*> e3a0e000 ?	mov	lr, #0	; 0x0
+0+18 <[^>]*> e3a0e8ff ?	mov	lr, #16711680	; 0xff0000
+0+1c <[^>]*> e3e0e8ff ?	mvn	lr, #16711680	; 0xff0000
+0+20 <[^>]*> e51fe00c ?	ldr	lr, \[pc, #-12\]	; 0+1c <[^>]*>
+0+24 <[^>]*> 00fff000 ?	.*
+0+28 <[^>]*> 03a00000 ?	moveq	r0, #0	; 0x0
+0+2c <[^>]*> 03a00cff ?	moveq	r0, #65280	; 0xff00
+0+30 <[^>]*> 03e00cff ?	mvneq	r0, #65280	; 0xff00
+0+34 <[^>]*> 051f000c ?	ldreq	r0, \[pc, #-12\]	; 0+30 <[^>]*>
+0+38 <[^>]*> 000fff00 ?	.*
+0+3c <[^>]*> 43a0b000 ?	movmi	fp, #0	; 0x0
+0+40 <[^>]*> 43a0b0ff ?	movmi	fp, #255	; 0xff
+0+44 <[^>]*> 43e0b0ff ?	mvnmi	fp, #255	; 0xff
+0+48 <[^>]*> 451fb00c ?	ldrmi	fp, \[pc, #-12\]	; 0+44 <[^>]*>
+0+4c <[^>]*> 0000fff0 ?	.*