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authorNick Clifton <nickc@redhat.com>1998-02-19 21:52:27 +0000
committerNick Clifton <nickc@redhat.com>1998-02-19 21:52:27 +0000
commit0a2f6d93042bb83f8a19850575f256a40c7dcb8c (patch)
treeba4939968cbb4e6994002a7548e6dc3d299e3d0a
parent180d1f0b501af84bd6ba45e87cfdf1f7f2c104a6 (diff)
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test 32 bit BCL instruction.
-rw-r--r--sim/testsuite/ChangeLog17
1 files changed, 9 insertions, 8 deletions
diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index d774236..c987c3f 100644
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,13 +1,14 @@
Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
- * sim/m32r/sra.cgs: Test sra instruction.
- * sim/m32r/sra3.cgs: Test sra3 instruction.
- * sim/m32r/srai.cgs: Test srai instruction.
- * sim/m32r/srl.cgs: Test srl instruction.
- * sim/m32r/srl3.cgs: Test srl3 instruction.
- * sim/m32r/srli.cgs: Test srli instruction.
- * sim/m32r/xor3.cgs: Test xor3 instruction.
- * sim/m32r/xor.cgs: Test xor instruction.
+ * sim/m32r/bcl24.cgs: Test long version of BCL instruction
+ * sim/m32r/sra.cgs: Test SRA instruction.
+ * sim/m32r/sra3.cgs: Test SRA3 instruction.
+ * sim/m32r/srai.cgs: Test SRAI instruction.
+ * sim/m32r/srl.cgs: Test SRL instruction.
+ * sim/m32r/srl3.cgs: Test SRL3 instruction.
+ * sim/m32r/srli.cgs: Test SRLI instruction.
+ * sim/m32r/xor3.cgs: Test XOR3 instruction.
+ * sim/m32r/xor.cgs: Test XOR instruction.
Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com>