diff options
| author | Bernd Schmidt <bernds@codesourcery.com> | 2008-03-26 16:48:32 +0000 |
|---|---|---|
| committer | Bernd Schmidt <bernds@codesourcery.com> | 2008-03-26 16:48:32 +0000 |
| commit | 086134ec0edd4a54682c435552c8ae20f65fbb23 (patch) | |
| tree | 5015dbb7cf8413e68fd06ffb7359664997cc2eef | |
| parent | e2c038d34c01414b5efee68e5e3e41c3bd248193 (diff) | |
| download | gdb-086134ec0edd4a54682c435552c8ae20f65fbb23.zip gdb-086134ec0edd4a54682c435552c8ae20f65fbb23.tar.gz gdb-086134ec0edd4a54682c435552c8ae20f65fbb23.tar.bz2 | |
gas/testsuite/:
From Robin Getz <rgetz@blackfin.uclinux.org>
* gas/bfin/arithmetic.d: Update to reflect spaces/capitalization in
recent changes in opcodes/bfin-dis.c.
gas/bfin/arithmetic.s: Likewise.
gas/bfin/bit.d: Likewise.
gas/bfin/bit2.d: Likewise.
gas/bfin/control_code.d: Likewise.
gas/bfin/control_code2.d: Likewise.
gas/bfin/event.d: Likewise.
gas/bfin/event2.d: Likewise.
gas/bfin/flow.d: Likewise.
gas/bfin/flow2.d: Likewise.
gas/bfin/load.d: Likewise.
gas/bfin/logical.d: Likewise.
gas/bfin/logical2.d: Likewise.
gas/bfin/move.d: Likewise.
gas/bfin/move2.d: Likewise.
gas/bfin/parallel.d: Likewise.
gas/bfin/parallel2.d: Likewise.
gas/bfin/parallel3.d: Likewise.
gas/bfin/parallel4.d: Likewise.
gas/bfin/shift.d: Likewise.
gas/bfin/shift2.d: Likewise.
gas/bfin/stack.d: Likewise.
gas/bfin/stack2.d: Likewise.
gas/bfin/store.d: Likewise.
gas/bfin/vector.d: Likewise.
gas/bfin/vector2.d: Likewise.
gas/bfin/video.d: Likewise.
gas/bfin/video2.d: Likewise.
opcodes/:
* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
c_imm32, c_huimm32e): Define.
(constant_formats): Add flags for printing decimal, leading spaces, and
exact symbols.
(comment, parallel): Add global flags in all disassembly.
(fmtconst): Take advantage of new flags, and print default in hex.
(fmtconst_val): Likewise.
(decode_macfunc): Be consistant with spaces, tabs, comments,
capitalization in disassembly, fix minor coding style issues.
(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
_print_insn_bfin, print_insn_bfin): Likewise.
31 files changed, 3247 insertions, 3071 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index f307ee4..52d2ab6 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -25,6 +25,37 @@ for mismatched half registers in vector multipy-accumulate instructions. + From Robin Getz <rgetz@blackfin.uclinux.org> + * gas/bfin/arithmetic.d: Update to reflect spaces/capitalization in + recent changes in opcodes/bfin-dis.c. + gas/bfin/arithmetic.s: Likewise. + gas/bfin/bit.d: Likewise. + gas/bfin/bit2.d: Likewise. + gas/bfin/control_code.d: Likewise. + gas/bfin/control_code2.d: Likewise. + gas/bfin/event.d: Likewise. + gas/bfin/event2.d: Likewise. + gas/bfin/flow.d: Likewise. + gas/bfin/flow2.d: Likewise. + gas/bfin/load.d: Likewise. + gas/bfin/logical.d: Likewise. + gas/bfin/logical2.d: Likewise. + gas/bfin/move.d: Likewise. + gas/bfin/move2.d: Likewise. + gas/bfin/parallel.d: Likewise. + gas/bfin/parallel2.d: Likewise. + gas/bfin/parallel3.d: Likewise. + gas/bfin/parallel4.d: Likewise. + gas/bfin/shift.d: Likewise. + gas/bfin/shift2.d: Likewise. + gas/bfin/stack.d: Likewise. + gas/bfin/stack2.d: Likewise. + gas/bfin/store.d: Likewise. + gas/bfin/vector.d: Likewise. + gas/bfin/vector2.d: Likewise. + gas/bfin/video.d: Likewise. + gas/bfin/video2.d: Likewise. + 2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/zarch-z10.d: New file. diff --git a/gas/testsuite/gas/bfin/arithmetic.d b/gas/testsuite/gas/bfin/arithmetic.d index 471b48c..cb7c951 100644 --- a/gas/testsuite/gas/bfin/arithmetic.d +++ b/gas/testsuite/gas/bfin/arithmetic.d @@ -6,80 +6,80 @@ Disassembly of section .text: 00000000 <abs>: - 0: 10 c4 [0-3][[:xdigit:]] 00 A0= ABS A0; - 4: 10 c4 [0-3][[:xdigit:]] 40 A0= ABS A1; - 8: 30 c4 [0-3][[:xdigit:]] 00 A1= ABS A0; - c: 30 c4 [0-3][[:xdigit:]] 40 A1= ABS A1; - 10: 10 c4 [0-3][[:xdigit:]] c0 A1= ABS A0,A0= ABS A0; - 14: 07 c4 10 80 R0= ABS R2; + 0: 10 c4 [0-3][[:xdigit:]] 00 A0 = ABS A0; + 4: 10 c4 [0-3][[:xdigit:]] 40 A0 = ABS A1; + 8: 30 c4 [0-3][[:xdigit:]] 00 A1 = ABS A0; + c: 30 c4 [0-3][[:xdigit:]] 40 A1 = ABS A1; + 10: 10 c4 [0-3][[:xdigit:]] c0 A1 = ABS A0, A0 = ABS A0; + 14: 07 c4 10 80 R0 = ABS R2; 00000018 <add>: - 18: 86 5b SP=SP\+P0; - 1a: 96 5b SP=SP\+P2; - 1c: f9 5b FP=P1\+FP; - 1e: 04 c4 3a 0e R7=R7\+R2 \(NS\); - 22: 04 c4 30 2c R6=R6\+R0 \(S\); - 26: 02 c4 10 a8 R4.L=R2.H\+R0.L \(S\); - 2a: 22 c4 09 aa R5.H=R1.H\+R1.L \(S\); - 2e: 02 c4 35 0c R6.L=R6.L\+R5.L \(NS\); + 18: 86 5b SP = SP \+ P0; + 1a: 96 5b SP = SP \+ P2; + 1c: f9 5b FP = P1 \+ FP; + 1e: 04 c4 3a 0e R7 = R7 \+ R2 \(NS\); + 22: 04 c4 30 2c R6 = R6 \+ R0 \(S\); + 26: 02 c4 10 a8 R4.L = R2.H \+ R0.L \(S\); + 2a: 22 c4 09 aa R5.H = R1.H \+ R1.L \(S\); + 2e: 02 c4 35 0c R6.L = R6.L \+ R5.L \(NS\); 00000032 <add_sub_prescale_down>: - 32: 05 c4 01 98 R4.L=R0\+R1\(RND20\); - 36: 25 c4 28 96 R3.H=R5\+R0\(RND20\); - 3a: 05 c4 3d d2 R1.L=R7-R5\(RND20\); + 32: 05 c4 01 98 R4.L = R0 \+ R1 \(RND20\); + 36: 25 c4 28 96 R3.H = R5 \+ R0 \(RND20\); + 3a: 05 c4 3d d2 R1.L = R7 - R5 \(RND20\); 0000003e <add_sub_prescale_up>: - 3e: 05 c4 01 04 R2.L=R0\+R1\(RND12\); - 42: 25 c4 3e 0e R7.H=R7\+R6\(RND12\); - 46: 05 c4 1a 4a R5.L=R3-R2\(RND12\); - 4a: 25 c4 0a 44 R2.H=R1-R2\(RND12\); + 3e: 05 c4 01 04 R2.L = R0 \+ R1 \(RND12\); + 42: 25 c4 3e 0e R7.H = R7 \+ R6 \(RND12\); + 46: 05 c4 1a 4a R5.L = R3 - R2 \(RND12\); + 4a: 25 c4 0a 44 R2.H = R1 - R2 \(RND12\); 0000004e <add_immediate>: - 4e: 05 66 R5\+=-64; - 50: fa 65 R2\+=0x3f; - 52: 60 9f I0\+=2; - 54: 63 9f I3\+=2; - 56: 6a 9f I2\+=4; - 58: 69 9f I1\+=4; - 5a: 20 6c P0\+=0x4; - 5c: 86 6c SP\+=0x10; - 5e: 07 6f FP\+=-32; + 4e: 05 66 R5 \+= -0x40;.* + 50: fa 65 R2 \+= 0x3f;.* + 52: 60 9f I0 \+= 0x2;.* + 54: 63 9f I3 \+= 0x2;.* + 56: 6a 9f I2 \+= 0x4;.* + 58: 69 9f I1 \+= 0x4;.* + 5a: 20 6c P0 \+= 0x4;.* + 5c: 86 6c SP \+= 0x10;.* + 5e: 07 6f FP \+= -0x20;.* 00000060 <divide_primitive>: - 60: 6b 42 DIVS\(R3,R5\); - 62: 2b 42 DIVQ\(R3,R5\); + 60: 6b 42 DIVS \(R3, R5\); + 62: 2b 42 DIVQ \(R3, R5\); 00000064 <expadj>: - 64: 07 c6 25 0c R6.L=EXPADJ \(R5,R4.L\); - 68: 07 c6 08 ca R5.L=EXPADJ \(R0.H,R1.L\); - 6c: 07 c6 2b 48 R4.L=EXPADJ \(R3,R5.L\) \(V\); + 64: 07 c6 25 0c R6.L = EXPADJ \(R5, R4.L\); + 68: 07 c6 08 ca R5.L = EXPADJ \(R0.H, R1.L\); + 6c: 07 c6 2b 48 R4.L = EXPADJ \(R3, R5.L\) \(V\); 00000070 <max>: - 70: 07 c4 2a 0c R6=MAX\(R5,R2\); - 74: 07 c4 0b 00 R0=MAX\(R1,R3\); + 70: 07 c4 2a 0c R6 = MAX \(R5, R2\); + 74: 07 c4 0b 00 R0 = MAX \(R1, R3\); 00000078 <min>: - 78: 07 c4 13 4a R5=MIN\(R2,R3\); - 7c: 07 c4 38 48 R4=MIN\(R7,R0\); + 78: 07 c4 13 4a R5 = MIN \(R2, R3\); + 7c: 07 c4 38 48 R4 = MIN \(R7, R0\); 00000080 <modify_decrement>: - 80: 0b c4 [0-3][[:xdigit:]] c0 A0-=A1; - 84: 0b c4 [0-3][[:xdigit:]] e0 A0-=A1\(W32\); - 88: 17 44 FP-=P2; - 8a: 06 44 SP-=P0; - 8c: 73 9e I3-=M0; - 8e: 75 9e I1-=M1; + 80: 0b c4 [0-3][[:xdigit:]] c0 A0 -= A1; + 84: 0b c4 [0-3][[:xdigit:]] e0 A0 -= A1 \(W32\); + 88: 17 44 FP -= P2; + 8a: 06 44 SP -= P0; + 8c: 73 9e I3 -= M0; + 8e: 75 9e I1 -= M1; 00000090 <modify_increment>: - 90: 0b c4 [0-3][[:xdigit:]] 80 A0\+=A1; - 94: 0b c4 [0-3][[:xdigit:]] a0 A0\+=A1\(W32\); - 98: 4e 45 SP\+=P1\(BREV\); - 9a: 7d 45 P5\+=FP\(BREV\); - 9c: 6a 9e I2\+=M2; - 9e: e0 9e I0\+=M0\(BREV\); - a0: 0b c4 [0-3][[:xdigit:]] 0e R7=\(A0\+=A1\); - a4: 0b c4 [0-3][[:xdigit:]] 4c R6.L=\(A0\+=A1\); - a8: 2b c4 [0-3][[:xdigit:]] 40 R0.H=\(A0\+=A1\); + 90: 0b c4 [0-3][[:xdigit:]] 80 A0 \+= A1; + 94: 0b c4 [0-3][[:xdigit:]] a0 A0 \+= A1 \(W32\); + 98: 4e 45 SP \+= P1 \(BREV\); + 9a: 7d 45 P5 \+= FP \(BREV\); + 9c: 6a 9e I2 \+= M2; + 9e: e0 9e I0 \+= M0 \(BREV\); + a0: 0b c4 [0-3][[:xdigit:]] 0e R7 = \(A0 \+= A1\); + a4: 0b c4 [0-3][[:xdigit:]] 4c R6.L = \(A0 \+= A1\); + a8: 2b c4 [0-3][[:xdigit:]] 40 R0.H = \(A0 \+= A1\); 000000ac <multiply16>: ac: 00 c2 0a 24 R0 = R1.H \* R2.L; @@ -96,85 +96,85 @@ Disassembly of section .text: d8: 1c c2 b0 c0 R3 = R6.H \* R0.H \(M\); 000000dc <multiply32>: - dc: c4 40 R4\*=R0; - de: d7 40 R7\*=R2; + dc: c4 40 R4 \*= R0; + de: d7 40 R7 \*= R2; 000000e0 <multiply_accumulate>: - e0: 63 c0 2f 02 a0 = R5.L \* R7.H \(W32\); - e4: 03 c0 00 04 a0 = R0.H \* R0.L; - e8: 83 c0 13 0a a0 \+= R2.L \* R3.H \(FU\); - ec: 03 c0 21 0c a0 \+= R4.H \* R1.L; - f0: 03 c1 3e 12 a0 -= R7.L \* R6.H \(IS\); - f4: 03 c0 2a 16 a0 -= R5.H \* R2.H; - f8: 10 c0 08 58 a1 = R1.L \* R0.H \(M\); - fc: 00 c0 10 98 a1 = R2.H \* R0.L; - 100: 70 c0 3e 98 a1 = R7.H \* R6.L \(M, W32\); - 104: 81 c0 1a 18 a1 \+= R3.L \* R2.L \(FU\); - 108: 01 c0 31 98 a1 \+= R6.H \* R1.L; - 10c: 02 c1 03 58 a1 -= R0.L \* R3.H \(IS\); - 110: 02 c0 17 58 a1 -= R2.L \* R7.H; + e0: 63 c0 2f 02 A0 = R5.L \* R7.H \(W32\); + e4: 03 c0 00 04 A0 = R0.H \* R0.L; + e8: 83 c0 13 0a A0 \+= R2.L \* R3.H \(FU\); + ec: 03 c0 21 0c A0 \+= R4.H \* R1.L; + f0: 03 c1 3e 12 A0 -= R7.L \* R6.H \(IS\); + f4: 03 c0 2a 16 A0 -= R5.H \* R2.H; + f8: 10 c0 08 58 A1 = R1.L \* R0.H \(M\); + fc: 00 c0 10 98 A1 = R2.H \* R0.L; + 100: 70 c0 3e 98 A1 = R7.H \* R6.L \(M, W32\); + 104: 81 c0 1a 18 A1 \+= R3.L \* R2.L \(FU\); + 108: 01 c0 31 98 A1 \+= R6.H \* R1.L; + 10c: 02 c1 03 58 A1 -= R0.L \* R3.H \(IS\); + 110: 02 c0 17 58 A1 -= R2.L \* R7.H; 00000114 <multiply_accumulate_half>: - 114: 03 c0 f5 25 R7.L = \(a0 = R6.H \* R5.L\); - 118: c3 c0 0a 24 R0.L = \(a0 = R1.H \* R2.L\) \(TFU\); - 11c: 03 c0 ac 28 R2.L = \(a0 \+= R5.L \* R4.L\); - 120: 43 c0 fe 2e R3.L = \(a0 \+= R7.H \* R6.H\) \(T\); - 124: 03 c0 1a 36 R0.L = \(a0 -= R3.H \* R2.H\); - 128: 63 c1 6c 30 R1.L = \(a0 -= R5.L \* R4.L\) \(IH\); - 12c: 04 c0 48 58 R1.H = \(a1 = R1.L \* R0.H\); - 130: 34 c1 83 98 R2.H = \(a1 = R0.H \* R3.L\) \(M, ISS2\); - 134: 05 c0 bf 59 R6.H = \(a1 \+= R7.L \* R7.H\); - 138: 25 c0 d3 19 R7.H = \(a1 \+= R2.L \* R3.L\) \(S2RND\); - 13c: 06 c0 a2 d9 R6.H = \(a1 -= R4.H \* R2.H\); - 140: d6 c0 5f 99 R5.H = \(a1 -= R3.H \* R7.L\) \(M, TFU\); + 114: 03 c0 f5 25 R7.L = \(A0 = R6.H \* R5.L\); + 118: c3 c0 0a 24 R0.L = \(A0 = R1.H \* R2.L\) \(TFU\); + 11c: 03 c0 ac 28 R2.L = \(A0 \+= R5.L \* R4.L\); + 120: 43 c0 fe 2e R3.L = \(A0 \+= R7.H \* R6.H\) \(T\); + 124: 03 c0 1a 36 R0.L = \(A0 -= R3.H \* R2.H\); + 128: 63 c1 6c 30 R1.L = \(A0 -= R5.L \* R4.L\) \(IH\); + 12c: 04 c0 48 58 R1.H = \(A1 = R1.L \* R0.H\); + 130: 34 c1 83 98 R2.H = \(A1 = R0.H \* R3.L\) \(M, ISS2\); + 134: 05 c0 bf 59 R6.H = \(A1 \+= R7.L \* R7.H\); + 138: 25 c0 d3 19 R7.H = \(A1 \+= R2.L \* R3.L\) \(S2RND\); + 13c: 06 c0 a2 d9 R6.H = \(A1 -= R4.H \* R2.H\); + 140: d6 c0 5f 99 R5.H = \(A1 -= R3.H \* R7.L\) \(M, TFU\); 00000144 <multiply_accumulate_data_reg>: - 144: 0b c0 0a 20 R0 = \(a0 = R1.L \* R2.L\); - 148: 0b c1 8a 20 R2 = \(a0 = R1.L \* R2.L\) \(IS\); - 14c: 0b c0 3e 2d R4 = \(a0 \+= R7.H \* R6.L\); - 150: 2b c0 ab 2b R6 = \(a0 \+= R5.L \* R3.H\) \(S2RND\); - 154: 0b c0 97 35 R6 = \(a0 -= R2.H \* R7.L\); - 158: 8b c0 06 33 R4 = \(a0 -= R0.L \* R6.H\) \(FU\); - 15c: 0c c0 81 99 R7 = \(a1 = R0.H \* R1.L\); - 160: 9c c0 13 d9 R5 = \(a1 = R2.H \* R3.H\) \(M, FU\); - 164: 0d c0 bd 18 R3 = \(a1 \+= R7.L \* R5.L\); - 168: 2d c1 17 d8 R1 = \(a1 \+= R2.H \* R7.H\) \(ISS2\); - 16c: 0e c0 80 58 R3 = \(a1 -= R0.L \* R0.H\); - 170: 1e c1 17 59 R5 = \(a1 -= R2.L \* R7.H\) \(M, IS\); - 174: 8d c1 8b d9 R7 = \(a1 \+= R1.H \* R3.H\) \(IU\); + 144: 0b c0 0a 20 R0 = \(A0 = R1.L \* R2.L\); + 148: 0b c1 8a 20 R2 = \(A0 = R1.L \* R2.L\) \(IS\); + 14c: 0b c0 3e 2d R4 = \(A0 \+= R7.H \* R6.L\); + 150: 2b c0 ab 2b R6 = \(A0 \+= R5.L \* R3.H\) \(S2RND\); + 154: 0b c0 97 35 R6 = \(A0 -= R2.H \* R7.L\); + 158: 8b c0 06 33 R4 = \(A0 -= R0.L \* R6.H\) \(FU\); + 15c: 0c c0 81 99 R7 = \(A1 = R0.H \* R1.L\); + 160: 9c c0 13 d9 R5 = \(A1 = R2.H \* R3.H\) \(M, FU\); + 164: 0d c0 bd 18 R3 = \(A1 \+= R7.L \* R5.L\); + 168: 2d c1 17 d8 R1 = \(A1 \+= R2.H \* R7.H\) \(ISS2\); + 16c: 0e c0 80 58 R3 = \(A1 -= R0.L \* R0.H\); + 170: 1e c1 17 59 R5 = \(A1 -= R2.L \* R7.H\) \(M, IS\); + 174: 0d c0 8b d9 R7 = \(A1 \+= R1.H \* R3.H\); 00000178 <negate>: - 178: 85 43 R5=-R0; - 17a: 07 c4 10 ee R7=-R2\(S\); - 17e: 07 c4 10 ce R7=-R2\(NS\); - 182: 0e c4 [0-3][[:xdigit:]] 00 A0=-A0; - 186: 0e c4 [0-3][[:xdigit:]] 40 A0=-A1; - 18a: 2e c4 [0-3][[:xdigit:]] 00 A1=-A0; - 18e: 2e c4 [0-3][[:xdigit:]] 40 A1=-A1; - 192: 0e c4 [0-3][[:xdigit:]] c0 A1=-A1,A0=-A0; + 178: 85 43 R5 = -R0; + 17a: 07 c4 10 ee R7 = -R2 \(S\); + 17e: 07 c4 10 ce R7 = -R2 \(NS\); + 182: 0e c4 [0-3][[:xdigit:]] 00 A0 = -A0; + 186: 0e c4 [0-3][[:xdigit:]] 40 A0 = -A1; + 18a: 2e c4 [0-3][[:xdigit:]] 00 A1 = -A0; + 18e: 2e c4 [0-3][[:xdigit:]] 40 A1 = -A1; + 192: 0e c4 [0-3][[:xdigit:]] c0 A1 = -A1, A0 = -A0; 00000196 <round_half>: - 196: 0c c4 18 ca R5.L=R3\(RND\); - 19a: 2c c4 00 cc R6.H=R0\(RND\); + 196: 0c c4 18 ca R5.L = R3 \(RND\); + 19a: 2c c4 00 cc R6.H = R0 \(RND\); 0000019e <saturate>: - 19e: 08 c4 [0-3][[:xdigit:]] 20 A0=A0\(S\); - 1a2: 08 c4 [0-3][[:xdigit:]] 60 A1=A1\(S\); - 1a6: 08 c4 [0-3][[:xdigit:]] a0 A1=A1\(S\),A0=A0\(S\); + 19e: 08 c4 [0-3][[:xdigit:]] 20 A0 = A0 \(S\); + 1a2: 08 c4 [0-3][[:xdigit:]] 60 A1 = A1 \(S\); + 1a6: 08 c4 [0-3][[:xdigit:]] a0 A1 = A1 \(S\), A0 = A0 \(S\); 000001aa <signbits>: - 1aa: 05 c6 00 0a R5.L=SIGNBITS R0; - 1ae: 05 c6 07 80 R0.L=SIGNBITS R7.H; - 1b2: 06 c6 00 06 R3.L=SIGNBITS A0; - 1b6: 06 c6 00 4e R7.L=SIGNBITS A1; + 1aa: 05 c6 00 0a R5.L = SIGNBITS R0; + 1ae: 05 c6 07 80 R0.L = SIGNBITS R7.H; + 1b2: 06 c6 00 06 R3.L = SIGNBITS A0; + 1b6: 06 c6 00 4e R7.L = SIGNBITS A1; 000001ba <subtract>: - 1ba: 43 53 R5=R3-R0; - 1bc: 04 c4 38 6e R7=R7-R0 \(S\); - 1c0: 04 c4 11 46 R3=R2-R1 \(NS\); - 1c4: 03 c4 37 ea R5.L=R6.H-R7.H \(S\); - 1c8: 23 c4 1b 40 R0.H=R3.L-R3.H \(NS\); + 1ba: 43 53 R5 = R3 - R0; + 1bc: 04 c4 38 6e R7 = R7 - R0 \(S\); + 1c0: 04 c4 11 46 R3 = R2 - R1 \(NS\); + 1c4: 03 c4 37 ea R5.L = R6.H - R7.H \(S\); + 1c8: 23 c4 1b 40 R0.H = R3.L - R3.H \(NS\); 000001cc <subtract_immediate>: - 1cc: 66 9f I2-=2; - 1ce: 6c 9f I0-=4; + 1cc: 66 9f I2 -= 0x2;.* + 1ce: 6c 9f I0 -= 0x4;.* diff --git a/gas/testsuite/gas/bfin/arithmetic.s b/gas/testsuite/gas/bfin/arithmetic.s index 74ddc4e..ec6c0ae 100644 --- a/gas/testsuite/gas/bfin/arithmetic.s +++ b/gas/testsuite/gas/bfin/arithmetic.s @@ -173,7 +173,7 @@ multiply_accumulate_data_reg: r1 = (a1 += r2.h * r7.h) (iss2); r3 = (A1 -= r0.l * R0.H); R5 = (a1 -= R2.l * R7.h) (m, is); - r7 = (a1+=r1.h*r3.h) (IU); + r7 = (a1+=r1.h*r3.h); .text .global negate diff --git a/gas/testsuite/gas/bfin/bit.d b/gas/testsuite/gas/bfin/bit.d index fa334c2..29da101 100644 --- a/gas/testsuite/gas/bfin/bit.d +++ b/gas/testsuite/gas/bfin/bit.d @@ -4,39 +4,39 @@ Disassembly of section .text: 00000000 <bitclr>: - 0: fc 4c BITCLR \(R4,0x1f\); - 2: 00 4c BITCLR \(R0,0x0\); + 0: fc 4c BITCLR \(R4, 0x1f\);.* + 2: 00 4c BITCLR \(R0, 0x0\);.* 00000004 <bitset>: - 4: f2 4a BITSET \(R2,0x1e\); - 6: eb 4a BITSET \(R3,0x1d\); + 4: f2 4a BITSET \(R2, 0x1e\);.* + 6: eb 4a BITSET \(R3, 0x1d\);.* 00000008 <bittgl>: - 8: b7 4b BITTGL \(R7,0x16\); - a: 86 4b BITTGL \(R6,0x10\); + 8: b7 4b BITTGL \(R7, 0x16\);.* + a: 86 4b BITTGL \(R6, 0x10\);.* 0000000c <bittst>: - c: f8 49 CC = BITTST \(R0,0x1f\); - e: 01 49 CC = BITTST \(R1,0x0\); - 10: 7f 49 CC = BITTST \(R7,0xf\); + c: f8 49 CC = BITTST \(R0, 0x1f\);.* + e: 01 49 CC = BITTST \(R1, 0x0\);.* + 10: 7f 49 CC = BITTST \(R7, 0xf\);.* 00000012 <deposit>: - 12: 0a c6 13 8a R5=DEPOSIT\(R3,R2\); - 16: 0a c6 37 c0 R0=DEPOSIT\(R7,R6\)\(X\); + 12: 0a c6 13 8a R5 = DEPOSIT \(R3, R2\); + 16: 0a c6 37 c0 R0 = DEPOSIT \(R7, R6\) \(X\); 0000001a <extract>: - 1a: 0a c6 0a 08 R4=EXTRACT\(R2,R1.L\) \(Z\); - 1e: 0a c6 10 04 R2=EXTRACT\(R0,R2.L\) \(Z\); - 22: 0a c6 23 4e R7=EXTRACT\(R3,R4.L\)\(X\); - 26: 0a c6 0e 4a R5=EXTRACT\(R6,R1.L\)\(X\); + 1a: 0a c6 0a 08 R4 = EXTRACT \(R2, R1.L\) \(Z\); + 1e: 0a c6 10 04 R2 = EXTRACT \(R0, R2.L\) \(Z\); + 22: 0a c6 23 4e R7 = EXTRACT \(R3, R4.L\) \(X\); + 26: 0a c6 0e 4a R5 = EXTRACT \(R6, R1.L\) \(X\); 0000002a <bitmux>: - 2a: 08 c6 08 00 BITMUX \(R1,R0,A0 \)\(ASR\); - 2e: 08 c6 13 00 BITMUX \(R2,R3,A0 \)\(ASR\); - 32: 08 c6 25 40 BITMUX \(R4,R5,A0 \)\(ASL\); - 36: 08 c6 3e 40 BITMUX \(R7,R6,A0 \)\(ASL\); + 2a: 08 c6 08 00 BITMUX \(R1, R0, A0\) \(ASR\); + 2e: 08 c6 13 00 BITMUX \(R2, R3, A0\) \(ASR\); + 32: 08 c6 25 40 BITMUX \(R4, R5, A0\) \(ASL\); + 36: 08 c6 3e 40 BITMUX \(R7, R6, A0\) \(ASL\); 0000003a <ones>: - 3a: 06 c6 00 ca R5.L=ONES R0; - 3e: 06 c6 02 ce R7.L=ONES R2; + 3a: 06 c6 00 ca R5.L = ONES R0; + 3e: 06 c6 02 ce R7.L = ONES R2; ... diff --git a/gas/testsuite/gas/bfin/bit2.d b/gas/testsuite/gas/bfin/bit2.d index 77a4964..c4e14eb 100644 --- a/gas/testsuite/gas/bfin/bit2.d +++ b/gas/testsuite/gas/bfin/bit2.d @@ -5,66 +5,66 @@ Disassembly of section .text: 00000000 <.text>: - 0: 07 4c BITCLR \(R7,0x0\); - 2: ff 4c BITCLR \(R7,0x1f\); - 4: 7f 4c BITCLR \(R7,0xf\); - 6: 01 4c BITCLR \(R1,0x0\); - 8: 0a 4c BITCLR \(R2,0x1\); - a: 9b 4c BITCLR \(R3,0x13\); - c: 07 4a BITSET \(R7,0x0\); - e: ff 4a BITSET \(R7,0x1f\); - 10: 7f 4a BITSET \(R7,0xf\); - 12: 01 4a BITSET \(R1,0x0\); - 14: 0a 4a BITSET \(R2,0x1\); - 16: 9b 4a BITSET \(R3,0x13\); - 18: 07 4b BITTGL \(R7,0x0\); - 1a: ff 4b BITTGL \(R7,0x1f\); - 1c: 7f 4b BITTGL \(R7,0xf\); - 1e: 01 4b BITTGL \(R1,0x0\); - 20: 0a 4b BITTGL \(R2,0x1\); - 22: 9b 4b BITTGL \(R3,0x13\); - 24: 07 49 CC = BITTST \(R7,0x0\); - 26: ff 49 CC = BITTST \(R7,0x1f\); - 28: 7f 49 CC = BITTST \(R7,0xf\); - 2a: 01 49 CC = BITTST \(R1,0x0\); - 2c: 0a 49 CC = BITTST \(R2,0x1\); - 2e: 9b 49 CC = BITTST \(R3,0x13\); - 30: 07 48 CC = ! BITTST \(R7,0x0\); - 32: ff 48 CC = ! BITTST \(R7,0x1f\); - 34: 7f 48 CC = ! BITTST \(R7,0xf\); - 36: 01 48 CC = ! BITTST \(R1,0x0\); - 38: 0a 48 CC = ! BITTST \(R2,0x1\); - 3a: 9b 48 CC = ! BITTST \(R3,0x13\); - 3c: 0a c6 08 8e R7=DEPOSIT\(R0,R1\); - 40: 0a c6 0f 8e R7=DEPOSIT\(R7,R1\); - 44: 0a c6 3f 8e R7=DEPOSIT\(R7,R7\); - 48: 0a c6 08 82 R1=DEPOSIT\(R0,R1\); - 4c: 0a c6 0f 84 R2=DEPOSIT\(R7,R1\); - 50: 0a c6 3f 86 R3=DEPOSIT\(R7,R7\); - 54: 0a c6 08 ce R7=DEPOSIT\(R0,R1\)\(X\); - 58: 0a c6 0f ce R7=DEPOSIT\(R7,R1\)\(X\); - 5c: 0a c6 3f ce R7=DEPOSIT\(R7,R7\)\(X\); - 60: 0a c6 08 c2 R1=DEPOSIT\(R0,R1\)\(X\); - 64: 0a c6 0f c4 R2=DEPOSIT\(R7,R1\)\(X\); - 68: 0a c6 3f c6 R3=DEPOSIT\(R7,R7\)\(X\); - 6c: 0a c6 08 0e R7=EXTRACT\(R0,R1.L\) \(Z\); - 70: 0a c6 0f 0e R7=EXTRACT\(R7,R1.L\) \(Z\); - 74: 0a c6 3f 0e R7=EXTRACT\(R7,R7.L\) \(Z\); - 78: 0a c6 08 02 R1=EXTRACT\(R0,R1.L\) \(Z\); - 7c: 0a c6 0f 04 R2=EXTRACT\(R7,R1.L\) \(Z\); - 80: 0a c6 3f 06 R3=EXTRACT\(R7,R7.L\) \(Z\); - 84: 0a c6 08 4e R7=EXTRACT\(R0,R1.L\)\(X\); - 88: 0a c6 0f 4e R7=EXTRACT\(R7,R1.L\)\(X\); - 8c: 0a c6 3f 4e R7=EXTRACT\(R7,R7.L\)\(X\); - 90: 0a c6 08 42 R1=EXTRACT\(R0,R1.L\)\(X\); - 94: 0a c6 0f 44 R2=EXTRACT\(R7,R1.L\)\(X\); - 98: 0a c6 3f 46 R3=EXTRACT\(R7,R7.L\)\(X\); - 9c: 08 c6 01 00 BITMUX \(R0,R1,A0 \)\(ASR\); - a0: 08 c6 02 00 BITMUX \(R0,R2,A0 \)\(ASR\); - a4: 08 c6 0b 00 BITMUX \(R1,R3,A0 \)\(ASR\); - a8: 08 c6 01 40 BITMUX \(R0,R1,A0 \)\(ASL\); - ac: 08 c6 0a 40 BITMUX \(R1,R2,A0 \)\(ASL\); - b0: 06 c6 00 c0 R0.L=ONES R0; - b4: 06 c6 01 c0 R0.L=ONES R1; - b8: 06 c6 06 c2 R1.L=ONES R6; - bc: 06 c6 07 c4 R2.L=ONES R7; + 0: 07 4c BITCLR \(R7, 0x0\);.* + 2: ff 4c BITCLR \(R7, 0x1f\);.* + 4: 7f 4c BITCLR \(R7, 0xf\);.* + 6: 01 4c BITCLR \(R1, 0x0\);.* + 8: 0a 4c BITCLR \(R2, 0x1\);.* + a: 9b 4c BITCLR \(R3, 0x13\);.* + c: 07 4a BITSET \(R7, 0x0\);.* + e: ff 4a BITSET \(R7, 0x1f\);.* + 10: 7f 4a BITSET \(R7, 0xf\);.* + 12: 01 4a BITSET \(R1, 0x0\);.* + 14: 0a 4a BITSET \(R2, 0x1\);.* + 16: 9b 4a BITSET \(R3, 0x13\);.* + 18: 07 4b BITTGL \(R7, 0x0\);.* + 1a: ff 4b BITTGL \(R7, 0x1f\);.* + 1c: 7f 4b BITTGL \(R7, 0xf\);.* + 1e: 01 4b BITTGL \(R1, 0x0\);.* + 20: 0a 4b BITTGL \(R2, 0x1\);.* + 22: 9b 4b BITTGL \(R3, 0x13\);.* + 24: 07 49 CC = BITTST \(R7, 0x0\);.* + 26: ff 49 CC = BITTST \(R7, 0x1f\);.* + 28: 7f 49 CC = BITTST \(R7, 0xf\);.* + 2a: 01 49 CC = BITTST \(R1, 0x0\);.* + 2c: 0a 49 CC = BITTST \(R2, 0x1\);.* + 2e: 9b 49 CC = BITTST \(R3, 0x13\);.* + 30: 07 48 CC = !BITTST \(R7, 0x0\);.* + 32: ff 48 CC = !BITTST \(R7, 0x1f\);.* + 34: 7f 48 CC = !BITTST \(R7, 0xf\);.* + 36: 01 48 CC = !BITTST \(R1, 0x0\);.* + 38: 0a 48 CC = !BITTST \(R2, 0x1\);.* + 3a: 9b 48 CC = !BITTST \(R3, 0x13\);.* + 3c: 0a c6 08 8e R7 = DEPOSIT \(R0, R1\); + 40: 0a c6 0f 8e R7 = DEPOSIT \(R7, R1\); + 44: 0a c6 3f 8e R7 = DEPOSIT \(R7, R7\); + 48: 0a c6 08 82 R1 = DEPOSIT \(R0, R1\); + 4c: 0a c6 0f 84 R2 = DEPOSIT \(R7, R1\); + 50: 0a c6 3f 86 R3 = DEPOSIT \(R7, R7\); + 54: 0a c6 08 ce R7 = DEPOSIT \(R0, R1\) \(X\); + 58: 0a c6 0f ce R7 = DEPOSIT \(R7, R1\) \(X\); + 5c: 0a c6 3f ce R7 = DEPOSIT \(R7, R7\) \(X\); + 60: 0a c6 08 c2 R1 = DEPOSIT \(R0, R1\) \(X\); + 64: 0a c6 0f c4 R2 = DEPOSIT \(R7, R1\) \(X\); + 68: 0a c6 3f c6 R3 = DEPOSIT \(R7, R7\) \(X\); + 6c: 0a c6 08 0e R7 = EXTRACT \(R0, R1.L\) \(Z\); + 70: 0a c6 0f 0e R7 = EXTRACT \(R7, R1.L\) \(Z\); + 74: 0a c6 3f 0e R7 = EXTRACT \(R7, R7.L\) \(Z\); + 78: 0a c6 08 02 R1 = EXTRACT \(R0, R1.L\) \(Z\); + 7c: 0a c6 0f 04 R2 = EXTRACT \(R7, R1.L\) \(Z\); + 80: 0a c6 3f 06 R3 = EXTRACT \(R7, R7.L\) \(Z\); + 84: 0a c6 08 4e R7 = EXTRACT \(R0, R1.L\) \(X\); + 88: 0a c6 0f 4e R7 = EXTRACT \(R7, R1.L\) \(X\); + 8c: 0a c6 3f 4e R7 = EXTRACT \(R7, R7.L\) \(X\); + 90: 0a c6 08 42 R1 = EXTRACT \(R0, R1.L\) \(X\); + 94: 0a c6 0f 44 R2 = EXTRACT \(R7, R1.L\) \(X\); + 98: 0a c6 3f 46 R3 = EXTRACT \(R7, R7.L\) \(X\); + 9c: 08 c6 01 00 BITMUX \(R0, R1, A0\) \(ASR\); + a0: 08 c6 02 00 BITMUX \(R0, R2, A0\) \(ASR\); + a4: 08 c6 0b 00 BITMUX \(R1, R3, A0\) \(ASR\); + a8: 08 c6 01 40 BITMUX \(R0, R1, A0\) \(ASL\); + ac: 08 c6 0a 40 BITMUX \(R1, R2, A0\) \(ASL\); + b0: 06 c6 00 c0 R0.L = ONES R0; + b4: 06 c6 01 c0 R0.L = ONES R1; + b8: 06 c6 06 c2 R1.L = ONES R6; + bc: 06 c6 07 c4 R2.L = ONES R7; diff --git a/gas/testsuite/gas/bfin/control_code.d b/gas/testsuite/gas/bfin/control_code.d index 71a4563..f580bb5 100644 --- a/gas/testsuite/gas/bfin/control_code.d +++ b/gas/testsuite/gas/bfin/control_code.d @@ -4,59 +4,59 @@ Disassembly of section .text: 00000000 <compare_data_register>: - 0: 06 08 CC=R6==R0; - 2: 17 08 CC=R7==R2; - 4: 33 0c CC=R3==-2; - 6: 88 08 CC=R0<R1; - 8: a4 0c CC=R4<-4; - a: 2c 09 CC=R4<=R5; - c: 1d 0d CC=R5<=0x3; - e: be 09 CC=R6<R7\(IU\); - 10: a7 0d CC=R7<0x4\(IU\); - 12: 1d 0a CC=R5<=R3\(IU\); - 14: 2a 0e CC=R2<=0x5\(IU\); + 0: 06 08 CC = R6 == R0; + 2: 17 08 CC = R7 == R2; + 4: 33 0c CC = R3 == -0x2; + 6: 88 08 CC = R0 < R1; + 8: a4 0c CC = R4 < -0x4; + a: 2c 09 CC = R4 <= R5; + c: 1d 0d CC = R5 <= 0x3; + e: be 09 CC = R6 < R7 \(IU\); + 10: a7 0d CC = R7 < 0x4 \(IU\); + 12: 1d 0a CC = R5 <= R3 \(IU\); + 14: 2a 0e CC = R2 <= 0x5 \(IU\); 00000016 <compare_pointer>: - 16: 46 08 CC=SP==P0; - 18: 47 0c CC=FP==0x0; - 1a: f7 08 CC=FP<SP; - 1c: a1 0c CC=R1<-4; - 1e: 11 09 CC=R1<=R2; - 20: 1b 0d CC=R3<=0x3; - 22: b5 09 CC=R5<R6\(IU\); - 24: bf 0d CC=R7<0x7\(IU\); - 26: 08 0a CC=R0<=R1\(IU\); - 28: 02 0e CC=R2<=0x0\(IU\); + 16: 46 08 CC = SP == P0; + 18: 47 0c CC = FP == 0x0; + 1a: f7 08 CC = FP < SP; + 1c: a1 0c CC = R1 < -0x4; + 1e: 11 09 CC = R1 <= R2; + 20: 1b 0d CC = R3 <= 0x3; + 22: b5 09 CC = R5 < R6 \(IU\); + 24: bf 0d CC = R7 < 0x7 \(IU\); + 26: 08 0a CC = R0 <= R1 \(IU\); + 28: 02 0e CC = R2 <= 0x0 \(IU\); 0000002a <compare_accumulator>: - 2a: 80 0a CC=A0==A1; - 2c: 00 0b CC=A0<A1; - 2e: 80 0b CC=A0<=A1; + 2a: 80 0a CC = A0 == A1; + 2c: 00 0b CC = A0 < A1; + 2e: 80 0b CC = A0 <= A1; 00000030 <move_cc>: - 30: 00 02 R0=CC; - 32: ac 03 AC0\|=CC; - 34: 80 03 AZ=CC; - 36: 81 03 AN=CC; - 38: cd 03 AC1&=CC; - 3a: f8 03 V\^=CC; - 3c: 98 03 V=CC; - 3e: b9 03 VS\|=CC; - 40: 90 03 AV0=CC; - 42: d2 03 AV1&=CC; - 44: 93 03 AV1S=CC; - 46: a6 03 AQ\|=CC; - 48: 0c 02 CC=R4; + 30: 00 02 R0 = CC; + 32: ac 03 AC0 \|= CC; + 34: 80 03 AZ = CC; + 36: 81 03 AN = CC; + 38: cd 03 AC1 &= CC; + 3a: f8 03 V \^= CC; + 3c: 98 03 V = CC; + 3e: b9 03 VS \|= CC; + 40: 90 03 AV0 = CC; + 42: d2 03 AV1 &= CC; + 44: 93 03 AV1S = CC; + 46: a6 03 AQ \|= CC; + 48: 0c 02 CC = R4; 4a: 00 03 CC = AZ; - 4c: 21 03 CC\|=AN; - 4e: 4c 03 CC&=AC0; - 50: 6d 03 CC\^=AC1; + 4c: 21 03 CC \|= AN; + 4e: 4c 03 CC &= AC0; + 50: 6d 03 CC \^= AC1; 52: 18 03 CC = V; - 54: 39 03 CC\|=VS; - 56: 50 03 CC&=AV0; - 58: 72 03 CC\^=AV1; + 54: 39 03 CC \|= VS; + 56: 50 03 CC &= AV0; + 58: 72 03 CC \^= AV1; 5a: 13 03 CC = AV1S; - 5c: 26 03 CC\|=AQ; + 5c: 26 03 CC \|= AQ; 0000005e <negate_cc>: - 5e: 18 02 CC=!CC; + 5e: 18 02 CC = !CC; diff --git a/gas/testsuite/gas/bfin/control_code2.d b/gas/testsuite/gas/bfin/control_code2.d index 15cfdab..6a28db7 100644 --- a/gas/testsuite/gas/bfin/control_code2.d +++ b/gas/testsuite/gas/bfin/control_code2.d @@ -4,144 +4,144 @@ Disassembly of section .text: 00000000 <.text>: - 0: 07 08 CC=R7==R0; - 2: 0e 08 CC=R6==R1; - 4: 38 08 CC=R0==R7; - 6: 27 0c CC=R7==-4; - 8: 1f 0c CC=R7==0x3; - a: 20 0c CC=R0==-4; - c: 18 0c CC=R0==0x3; - e: 87 08 CC=R7<R0; - 10: 86 08 CC=R6<R0; - 12: 8f 08 CC=R7<R1; - 14: b9 08 CC=R1<R7; - 16: b0 08 CC=R0<R6; - 18: a7 0c CC=R7<-4; - 1a: a6 0c CC=R6<-4; - 1c: 9f 0c CC=R7<0x3; - 1e: 99 0c CC=R1<0x3; - 20: 07 09 CC=R7<=R0; - 22: 06 09 CC=R6<=R0; - 24: 0f 09 CC=R7<=R1; - 26: 39 09 CC=R1<=R7; - 28: 30 09 CC=R0<=R6; - 2a: 27 0d CC=R7<=-4; - 2c: 26 0d CC=R6<=-4; - 2e: 1f 0d CC=R7<=0x3; - 30: 19 0d CC=R1<=0x3; - 32: 87 09 CC=R7<R0\(IU\); - 34: 86 09 CC=R6<R0\(IU\); - 36: 8f 09 CC=R7<R1\(IU\); - 38: b9 09 CC=R1<R7\(IU\); - 3a: b0 09 CC=R0<R6\(IU\); - 3c: 87 0d CC=R7<0x0\(IU\); - 3e: 86 0d CC=R6<0x0\(IU\); - 40: bf 0d CC=R7<0x7\(IU\); - 42: b9 0d CC=R1<0x7\(IU\); - 44: 07 0a CC=R7<=R0\(IU\); - 46: 06 0a CC=R6<=R0\(IU\); - 48: 0f 0a CC=R7<=R1\(IU\); - 4a: 39 0a CC=R1<=R7\(IU\); - 4c: 30 0a CC=R0<=R6\(IU\); - 4e: 07 0e CC=R7<=0x0\(IU\); - 50: 06 0e CC=R6<=0x0\(IU\); - 52: 3f 0e CC=R7<=0x7\(IU\); - 54: 39 0e CC=R1<=0x7\(IU\); - 56: 45 08 CC=P5==P0; - 58: 4d 08 CC=P5==P1; - 5a: 50 08 CC=P0==P2; - 5c: 6b 08 CC=P3==P5; - 5e: 65 0c CC=P5==-4; - 60: 45 0c CC=P5==0x0; - 62: 5d 0c CC=P5==0x3; - 64: 62 0c CC=P2==-4; - 66: 42 0c CC=P2==0x0; - 68: 5a 0c CC=P2==0x3; - 6a: c5 08 CC=P5<P0; - 6c: cd 08 CC=P5<P1; - 6e: d0 08 CC=P0<P2; - 70: eb 08 CC=P3<P5; - 72: e5 0c CC=P5<-4; - 74: c5 0c CC=P5<0x0; - 76: dd 0c CC=P5<0x3; - 78: e2 0c CC=P2<-4; - 7a: c2 0c CC=P2<0x0; - 7c: da 0c CC=P2<0x3; - 7e: 45 09 CC=P5<=P0; - 80: 4d 09 CC=P5<=P1; - 82: 50 09 CC=P0<=P2; - 84: 6b 09 CC=P3<=P5; - 86: 65 0d CC=P5<=-4; - 88: 45 0d CC=P5<=0x0; - 8a: 5d 0d CC=P5<=0x3; - 8c: 62 0d CC=P2<=-4; - 8e: 42 0d CC=P2<=0x0; - 90: 5a 0d CC=P2<=0x3; - 92: c5 09 CC=P5<P0\(IU\); - 94: cd 09 CC=P5<P1\(IU\); - 96: d0 09 CC=P0<P2\(IU\); - 98: eb 09 CC=P3<P5\(IU\); - 9a: c5 0d CC=P5<0x0\(IU\); - 9c: fd 0d CC=P5<0x7\(IU\); - 9e: c2 0d CC=P2<0x0\(IU\); - a0: fa 0d CC=P2<0x7\(IU\); - a2: 45 0a CC=P5<=P0\(IU\); - a4: 4d 0a CC=P5<=P1\(IU\); - a6: 50 0a CC=P0<=P2\(IU\); - a8: 6b 0a CC=P3<=P5\(IU\); - aa: 45 0e CC=P5<=0x0\(IU\); - ac: 7d 0e CC=P5<=0x7\(IU\); - ae: 42 0e CC=P2<=0x0\(IU\); - b0: 7a 0e CC=P2<=0x7\(IU\); - b2: 80 0a CC=A0==A1; - b4: 00 0b CC=A0<A1; - b6: 80 0b CC=A0<=A1; - b8: 07 02 R7=CC; - ba: 00 02 R0=CC; - bc: 80 03 AZ=CC; - be: 81 03 AN=CC; - c0: 8c 03 AC0=CC; - c2: 8d 03 AC1=CC; - c4: 99 03 VS=CC; - c6: 90 03 AV0=CC; - c8: 91 03 AV0S=CC; - ca: 92 03 AV1=CC; - cc: 93 03 AV1S=CC; - ce: 86 03 AQ=CC; - d0: a0 03 AZ\|=CC; - d2: a1 03 AN\|=CC; - d4: ac 03 AC0\|=CC; - d6: ad 03 AC1\|=CC; - d8: b9 03 VS\|=CC; - da: b0 03 AV0\|=CC; - dc: b1 03 AV0S\|=CC; - de: b2 03 AV1\|=CC; - e0: b3 03 AV1S\|=CC; - e2: a6 03 AQ\|=CC; - e4: c0 03 AZ&=CC; - e6: c1 03 AN&=CC; - e8: cc 03 AC0&=CC; - ea: cd 03 AC1&=CC; - ec: d9 03 VS&=CC; - ee: d0 03 AV0&=CC; - f0: d1 03 AV0S&=CC; - f2: d2 03 AV1&=CC; - f4: d3 03 AV1S&=CC; - f6: c6 03 AQ&=CC; - f8: e0 03 AZ\^=CC; - fa: e1 03 AN\^=CC; - fc: ec 03 AC0\^=CC; - fe: ed 03 AC1\^=CC; - 100: f9 03 VS\^=CC; - 102: f0 03 AV0\^=CC; - 104: f1 03 AV0S\^=CC; - 106: f2 03 AV1\^=CC; - 108: f3 03 AV1S\^=CC; - 10a: e6 03 AQ\^=CC; - 10c: 0f 02 CC=R7; - 10e: 0e 02 CC=R6; - 110: 09 02 CC=R1; - 112: 08 02 CC=R0; + 0: 07 08 CC = R7 == R0; + 2: 0e 08 CC = R6 == R1; + 4: 38 08 CC = R0 == R7; + 6: 27 0c CC = R7 == -0x4; + 8: 1f 0c CC = R7 == 0x3; + a: 20 0c CC = R0 == -0x4; + c: 18 0c CC = R0 == 0x3; + e: 87 08 CC = R7 < R0; + 10: 86 08 CC = R6 < R0; + 12: 8f 08 CC = R7 < R1; + 14: b9 08 CC = R1 < R7; + 16: b0 08 CC = R0 < R6; + 18: a7 0c CC = R7 < -0x4; + 1a: a6 0c CC = R6 < -0x4; + 1c: 9f 0c CC = R7 < 0x3; + 1e: 99 0c CC = R1 < 0x3; + 20: 07 09 CC = R7 <= R0; + 22: 06 09 CC = R6 <= R0; + 24: 0f 09 CC = R7 <= R1; + 26: 39 09 CC = R1 <= R7; + 28: 30 09 CC = R0 <= R6; + 2a: 27 0d CC = R7 <= -0x4; + 2c: 26 0d CC = R6 <= -0x4; + 2e: 1f 0d CC = R7 <= 0x3; + 30: 19 0d CC = R1 <= 0x3; + 32: 87 09 CC = R7 < R0 \(IU\); + 34: 86 09 CC = R6 < R0 \(IU\); + 36: 8f 09 CC = R7 < R1 \(IU\); + 38: b9 09 CC = R1 < R7 \(IU\); + 3a: b0 09 CC = R0 < R6 \(IU\); + 3c: 87 0d CC = R7 < 0x0 \(IU\); + 3e: 86 0d CC = R6 < 0x0 \(IU\); + 40: bf 0d CC = R7 < 0x7 \(IU\); + 42: b9 0d CC = R1 < 0x7 \(IU\); + 44: 07 0a CC = R7 <= R0 \(IU\); + 46: 06 0a CC = R6 <= R0 \(IU\); + 48: 0f 0a CC = R7 <= R1 \(IU\); + 4a: 39 0a CC = R1 <= R7 \(IU\); + 4c: 30 0a CC = R0 <= R6 \(IU\); + 4e: 07 0e CC = R7 <= 0x0 \(IU\); + 50: 06 0e CC = R6 <= 0x0 \(IU\); + 52: 3f 0e CC = R7 <= 0x7 \(IU\); + 54: 39 0e CC = R1 <= 0x7 \(IU\); + 56: 45 08 CC = P5 == P0; + 58: 4d 08 CC = P5 == P1; + 5a: 50 08 CC = P0 == P2; + 5c: 6b 08 CC = P3 == P5; + 5e: 65 0c CC = P5 == -0x4; + 60: 45 0c CC = P5 == 0x0; + 62: 5d 0c CC = P5 == 0x3; + 64: 62 0c CC = P2 == -0x4; + 66: 42 0c CC = P2 == 0x0; + 68: 5a 0c CC = P2 == 0x3; + 6a: c5 08 CC = P5 < P0; + 6c: cd 08 CC = P5 < P1; + 6e: d0 08 CC = P0 < P2; + 70: eb 08 CC = P3 < P5; + 72: e5 0c CC = P5 < -0x4; + 74: c5 0c CC = P5 < 0x0; + 76: dd 0c CC = P5 < 0x3; + 78: e2 0c CC = P2 < -0x4; + 7a: c2 0c CC = P2 < 0x0; + 7c: da 0c CC = P2 < 0x3; + 7e: 45 09 CC = P5 <= P0; + 80: 4d 09 CC = P5 <= P1; + 82: 50 09 CC = P0 <= P2; + 84: 6b 09 CC = P3 <= P5; + 86: 65 0d CC = P5 <= -0x4; + 88: 45 0d CC = P5 <= 0x0; + 8a: 5d 0d CC = P5 <= 0x3; + 8c: 62 0d CC = P2 <= -0x4; + 8e: 42 0d CC = P2 <= 0x0; + 90: 5a 0d CC = P2 <= 0x3; + 92: c5 09 CC = P5 < P0 \(IU\); + 94: cd 09 CC = P5 < P1 \(IU\); + 96: d0 09 CC = P0 < P2 \(IU\); + 98: eb 09 CC = P3 < P5 \(IU\); + 9a: c5 0d CC = P5 < 0x0 \(IU\); + 9c: fd 0d CC = P5 < 0x7 \(IU\); + 9e: c2 0d CC = P2 < 0x0 \(IU\); + a0: fa 0d CC = P2 < 0x7 \(IU\); + a2: 45 0a CC = P5 <= P0 \(IU\); + a4: 4d 0a CC = P5 <= P1 \(IU\); + a6: 50 0a CC = P0 <= P2 \(IU\); + a8: 6b 0a CC = P3 <= P5 \(IU\); + aa: 45 0e CC = P5 <= 0x0 \(IU\); + ac: 7d 0e CC = P5 <= 0x7 \(IU\); + ae: 42 0e CC = P2 <= 0x0 \(IU\); + b0: 7a 0e CC = P2 <= 0x7 \(IU\); + b2: 80 0a CC = A0 == A1; + b4: 00 0b CC = A0 < A1; + b6: 80 0b CC = A0 <= A1; + b8: 07 02 R7 = CC; + ba: 00 02 R0 = CC; + bc: 80 03 AZ = CC; + be: 81 03 AN = CC; + c0: 8c 03 AC0 = CC; + c2: 8d 03 AC1 = CC; + c4: 99 03 VS = CC; + c6: 90 03 AV0 = CC; + c8: 91 03 AV0S = CC; + ca: 92 03 AV1 = CC; + cc: 93 03 AV1S = CC; + ce: 86 03 AQ = CC; + d0: a0 03 AZ \|= CC; + d2: a1 03 AN \|= CC; + d4: ac 03 AC0 \|= CC; + d6: ad 03 AC1 \|= CC; + d8: b9 03 VS \|= CC; + da: b0 03 AV0 \|= CC; + dc: b1 03 AV0S \|= CC; + de: b2 03 AV1 \|= CC; + e0: b3 03 AV1S \|= CC; + e2: a6 03 AQ \|= CC; + e4: c0 03 AZ &= CC; + e6: c1 03 AN &= CC; + e8: cc 03 AC0 &= CC; + ea: cd 03 AC1 &= CC; + ec: d9 03 VS &= CC; + ee: d0 03 AV0 &= CC; + f0: d1 03 AV0S &= CC; + f2: d2 03 AV1 &= CC; + f4: d3 03 AV1S &= CC; + f6: c6 03 AQ &= CC; + f8: e0 03 AZ \^= CC; + fa: e1 03 AN \^= CC; + fc: ec 03 AC0 \^= CC; + fe: ed 03 AC1 \^= CC; + 100: f9 03 VS \^= CC; + 102: f0 03 AV0 \^= CC; + 104: f1 03 AV0S \^= CC; + 106: f2 03 AV1 \^= CC; + 108: f3 03 AV1S \^= CC; + 10a: e6 03 AQ \^= CC; + 10c: 0f 02 CC = R7; + 10e: 0e 02 CC = R6; + 110: 09 02 CC = R1; + 112: 08 02 CC = R0; 114: 00 03 CC = AZ; 116: 01 03 CC = AN; 118: 0c 03 CC = AC0; @@ -152,35 +152,35 @@ Disassembly of section .text: 122: 12 03 CC = AV1; 124: 13 03 CC = AV1S; 126: 06 03 CC = AQ; - 128: 20 03 CC\|=AZ; - 12a: 21 03 CC\|=AN; - 12c: 2c 03 CC\|=AC0; - 12e: 2d 03 CC\|=AC1; - 130: 39 03 CC\|=VS; - 132: 30 03 CC\|=AV0; - 134: 31 03 CC\|=AV0S; - 136: 32 03 CC\|=AV1; - 138: 33 03 CC\|=AV1S; - 13a: 26 03 CC\|=AQ; - 13c: 40 03 CC&=AZ; - 13e: 41 03 CC&=AN; - 140: 4c 03 CC&=AC0; - 142: 4d 03 CC&=AC1; - 144: 59 03 CC&=VS; - 146: 50 03 CC&=AV0; - 148: 51 03 CC&=AV0S; - 14a: 52 03 CC&=AV1; - 14c: 53 03 CC&=AV1S; - 14e: 46 03 CC&=AQ; - 150: 60 03 CC\^=AZ; - 152: 61 03 CC\^=AN; - 154: 6c 03 CC\^=AC0; - 156: 6d 03 CC\^=AC1; - 158: 79 03 CC\^=VS; - 15a: 70 03 CC\^=AV0; - 15c: 71 03 CC\^=AV0S; - 15e: 72 03 CC\^=AV1; - 160: 73 03 CC\^=AV1S; - 162: 66 03 CC\^=AQ; - 164: 18 02 CC=!CC; + 128: 20 03 CC \|= AZ; + 12a: 21 03 CC \|= AN; + 12c: 2c 03 CC \|= AC0; + 12e: 2d 03 CC \|= AC1; + 130: 39 03 CC \|= VS; + 132: 30 03 CC \|= AV0; + 134: 31 03 CC \|= AV0S; + 136: 32 03 CC \|= AV1; + 138: 33 03 CC \|= AV1S; + 13a: 26 03 CC \|= AQ; + 13c: 40 03 CC &= AZ; + 13e: 41 03 CC &= AN; + 140: 4c 03 CC &= AC0; + 142: 4d 03 CC &= AC1; + 144: 59 03 CC &= VS; + 146: 50 03 CC &= AV0; + 148: 51 03 CC &= AV0S; + 14a: 52 03 CC &= AV1; + 14c: 53 03 CC &= AV1S; + 14e: 46 03 CC &= AQ; + 150: 60 03 CC \^= AZ; + 152: 61 03 CC \^= AN; + 154: 6c 03 CC \^= AC0; + 156: 6d 03 CC \^= AC1; + 158: 79 03 CC \^= VS; + 15a: 70 03 CC \^= AV0; + 15c: 71 03 CC \^= AV0S; + 15e: 72 03 CC \^= AV1; + 160: 73 03 CC \^= AV1S; + 162: 66 03 CC \^= AQ; + 164: 18 02 CC = !CC; ... diff --git a/gas/testsuite/gas/bfin/event.d b/gas/testsuite/gas/bfin/event.d index 13c0679..af19586 100644 --- a/gas/testsuite/gas/bfin/event.d +++ b/gas/testsuite/gas/bfin/event.d @@ -17,26 +17,26 @@ Disassembly of section .text: 6: 25 00 EMUEXCPT; 00000008 <cli>: - 8: 37 00 CLI R7; - a: 30 00 CLI R0; + 8: 37 00 CLI R7; + a: 30 00 CLI R0; 0000000c <sti>: - c: 41 00 STI R1; - e: 42 00 STI R2; + c: 41 00 STI R1; + e: 42 00 STI R2; 00000010 <raise>: - 10: 9f 00 RAISE 0xf; - 12: 90 00 RAISE 0x0; + 10: 9f 00 RAISE 0xf; + 12: 90 00 RAISE 0x0; 00000014 <excpt>: - 14: af 00 EXCPT 0xf; - 16: a0 00 EXCPT 0x0; + 14: af 00 EXCPT 0xf; + 16: a0 00 EXCPT 0x0; 00000018 <testset>: - 18: b5 00 TESTSET \(P5\); - 1a: b0 00 TESTSET \(P0\); + 18: b5 00 TESTSET \(P5\); + 1a: b0 00 TESTSET \(P0\); 0000001c <nop>: 1c: 00 00 NOP; - 1e: 03 c0 00 18 mnop; + 1e: 03 c0 00 18 MNOP; ... diff --git a/gas/testsuite/gas/bfin/event2.d b/gas/testsuite/gas/bfin/event2.d index d3975de..78b14ce 100644 --- a/gas/testsuite/gas/bfin/event2.d +++ b/gas/testsuite/gas/bfin/event2.d @@ -9,20 +9,20 @@ Disassembly of section .text: 2: 23 00 CSYNC; 4: 24 00 SSYNC; 6: 25 00 EMUEXCPT; - 8: 30 00 CLI R0; - a: 31 00 CLI R1; - c: 32 00 CLI R2; - e: 40 00 STI R0; - 10: 41 00 STI R1; - 12: 42 00 STI R2; - 14: 90 00 RAISE 0x0; - 16: 94 00 RAISE 0x4; - 18: 9f 00 RAISE 0xf; - 1a: a0 00 EXCPT 0x0; - 1c: a1 00 EXCPT 0x1; - 1e: af 00 EXCPT 0xf; - 20: b0 00 TESTSET \(P0\); - 22: b1 00 TESTSET \(P1\); - 24: b2 00 TESTSET \(P2\); + 8: 30 00 CLI R0; + a: 31 00 CLI R1; + c: 32 00 CLI R2; + e: 40 00 STI R0; + 10: 41 00 STI R1; + 12: 42 00 STI R2; + 14: 90 00 RAISE 0x0; + 16: 94 00 RAISE 0x4; + 18: 9f 00 RAISE 0xf; + 1a: a0 00 EXCPT 0x0; + 1c: a1 00 EXCPT 0x1; + 1e: af 00 EXCPT 0xf; + 20: b0 00 TESTSET \(P0\); + 22: b1 00 TESTSET \(P1\); + 24: b2 00 TESTSET \(P2\); 26: 00 00 NOP; - 28: 03 c0 00 18 mnop; + 28: 03 c0 00 18 MNOP; diff --git a/gas/testsuite/gas/bfin/flow.d b/gas/testsuite/gas/bfin/flow.d index 6a79619..29e13b0 100644 --- a/gas/testsuite/gas/bfin/flow.d +++ b/gas/testsuite/gas/bfin/flow.d @@ -5,31 +5,31 @@ Disassembly of section .text: 00000000 <jump>: - 0: 55 00 JUMP \(P5\); - 2: 83 00 JUMP \(PC\+P3\); - 4: 00 20 JUMP.S 4.* - 6: 80 e2 00 00 JUMP.L ff000006.* - a: 7f e2 ff ff JUMP.L 1000008.* - e: ff 27 JUMP.S 100c.* - 10: 7f e2 00 80 JUMP.L ff0010.* - 14: f6 2f JUMP.S 0 <jump>; + 0: 55 00 JUMP \(P5\); + 2: 83 00 JUMP \(PC \+ P3\); + 4: 00 20 JUMP.S 0x4 .* + 6: 80 e2 00 00 JUMP.L 0xff000006 .* + a: 7f e2 ff ff JUMP.L 0x1000008 .* + e: ff 27 JUMP.S 0x100c .* + 10: 7f e2 00 80 JUMP.L 0xff0010 .* + 14: f6 2f JUMP.S 0x0 <jump>; 00000016 <ccjump>: - 16: 00 1a IF CC JUMP fffffc16.* - 18: ff 1d IF CC JUMP 416.*\(BP\); - 1a: 00 16 IF ! CC JUMP fffffc1a.*\(BP\); - 1c: 89 10 IF ! CC JUMP 12e.* - 1e: f1 1b IF CC JUMP 0 <jump>; - 20: f0 1f IF CC JUMP 0 <jump>\(BP\); - 22: ef 17 IF ! CC JUMP 0 <jump>\(BP\); - 24: ee 13 IF ! CC JUMP 0 <jump>; + 16: 00 1a IF CC JUMP 0xfffffc16 .* + 18: ff 1d IF CC JUMP 0x416 .* \(BP\); + 1a: 00 16 IF !CC JUMP 0xfffffc1a .* \(BP\); + 1c: 89 10 IF !CC JUMP 0x12e .* + 1e: f1 1b IF CC JUMP 0x0 <jump>; + 20: f0 1f IF CC JUMP 0x0 <jump> \(BP\); + 22: ef 17 IF !CC JUMP 0x0 <jump> \(BP\); + 24: ee 13 IF !CC JUMP 0x0 <jump>; 00000026 <call>: - 26: 63 00 CALL \(P3\); - 28: 72 00 CALL \(PC\+P2\); - 2a: 80 e3 00 00 CALL ff00002a.* - 2e: 7f e3 ff ff CALL 100002c.* - 32: ff e3 e7 ff CALL 0 <jump>; + 26: 63 00 CALL \(P3\); + 28: 72 00 CALL \(PC \+ P2\); + 2a: 80 e3 00 00 CALL 0xff00002a .* + 2e: 7f e3 ff ff CALL 0x100002c .* + 32: ff e3 e7 ff CALL 0x0 <jump>; 00000036 <return>: 36: 10 00 RTS; @@ -39,48 +39,48 @@ Disassembly of section .text: 3e: 14 00 RTE; 00000040 <loop_lc0>: - 40: 82 e0 13 00 LSETUP\(44 <loop_lc0\+0x4>,66 <loop_lc0\+0x26>\)LC0; - 44: 38 e4 7b fc R0=\[FP\+-3604\]; - 48: 49 60 R1=0x9\(x\); - 4a: 38 e4 7b fc R0=\[FP\+-3604\]; - 4e: 00 32 P0=R0; - 50: 42 44 P2=P0<<2; - 52: ba 5a P2=P2\+FP; - 54: 20 e1 50 fb R0=-1200 \(X\); - 58: 08 32 P1=R0; - 5a: 8a 5a P2=P2\+P1; - 5c: 00 60 R0=0x0\(x\); - 5e: 10 93 \[P2\]=R0; - 60: 38 e4 7b fc R0=\[FP\+-3604\]; - 64: 08 64 R0\+=0x1; - 66: 38 e6 7b fc \[FP\+-3604\]=R0; - 6a: a2 e0 02 40 LSETUP\(6e <loop_lc0\+0x2e>,6e <loop_lc0\+0x2e>\)LC0=P4; + 40: 82 e0 13 00 LSETUP\(0x44 <loop_lc0\+0x4>, 0x66 <loop_lc0\+0x26>\) LC0; + 44: 38 e4 7b fc R0 = \[FP \+ -0xe14\]; + 48: 49 60 R1 = 0x9 \(X\);.* + 4a: 38 e4 7b fc R0 = \[FP \+ -0xe14\]; + 4e: 00 32 P0 = R0; + 50: 42 44 P2 = P0 << 0x2; + 52: ba 5a P2 = P2 \+ FP; + 54: 20 e1 50 fb R0 = -0x4b0 \(X\);.* + 58: 08 32 P1 = R0; + 5a: 8a 5a P2 = P2 \+ P1; + 5c: 00 60 R0 = 0x0 \(X\);.* + 5e: 10 93 \[P2\] = R0; + 60: 38 e4 7b fc R0 = \[FP \+ -0xe14\]; + 64: 08 64 R0 \+= 0x1;.* + 66: 38 e6 7b fc \[FP \+ -0xe14\] = R0; + 6a: a2 e0 02 40 LSETUP\(0x6e <loop_lc0\+0x2e>, 0x6e <loop_lc0\+0x2e>\) LC0 = P4; 6e: 00 00 NOP; - 70: e0 e0 00 10 LSETUP\(70 <loop_lc0\+0x30>,70 <loop_lc0\+0x30>\)LC0=P1>>1; - 74: 82 e0 ff 03 LSETUP\(78 <loop_lc0\+0x38>,72 <loop_lc0\+0x32>\)LC0; - 78: af e0 00 52 LSETUP\(76 <loop_lc0\+0x36>,fffffc78 <loop_lc1\+0xfffffbf8>\)LC0=P5; - 7c: ef e0 02 00 LSETUP\(7a <loop_lc0\+0x3a>,80 <loop_lc1>\)LC0=P0>>1; + 70: e0 e0 00 10 LSETUP\(0x70 <loop_lc0\+0x30>, 0x70 <loop_lc0\+0x30>\) LC0 = P1 >> 0x1; + 74: 82 e0 ff 03 LSETUP\(0x78 <loop_lc0\+0x38>, 0x72 <loop_lc0\+0x32>\) LC0; + 78: af e0 00 52 LSETUP\(0x76 <loop_lc0\+0x36>, 0xfffffc78 <loop_lc1\+0xfffffbf8>\) LC0 = P5; + 7c: ef e0 02 00 LSETUP\(0x7a <loop_lc0\+0x3a>, 0x80 <loop_lc1>\) LC0 = P0 >> 0x1; 00000080 <loop_lc1>: - 80: 90 e0 00 00 LSETUP\(80 <loop_lc1>,80 <loop_lc1>\)LC1; - 84: b0 e0 00 40 LSETUP\(84 <loop_lc1\+0x4>,84 <loop_lc1\+0x4>\)LC1=P4; - 88: f8 e0 1b 10 LSETUP\(78 <loop_lc0\+0x38>,be <loop_lc1\+0x3e>\)LC1=P1>>1; - 8c: 92 e0 ff 03 LSETUP\(90 <loop_lc1\+0x10>,8a <loop_lc1\+0xa>\)LC1; - 90: bf e0 00 52 LSETUP\(8e <loop_lc1\+0xe>,fffffc90 <loop_lc1\+0xfffffc10>\)LC1=P5; - 94: ff e0 02 00 LSETUP\(92 <loop_lc1\+0x12>,98 <loop_lc1\+0x18>\)LC1=P0>>1; - 98: 38 e4 7a fc R0=\[FP\+-3608\]; - 9c: 00 32 P0=R0; - 9e: 42 44 P2=P0<<2; - a0: ba 5a P2=P2\+FP; - a2: 20 e1 f0 f1 R0=-3600 \(X\); - a6: 00 32 P0=R0; - a8: 42 5a P1=P2\+P0; - aa: 38 e4 7a fc R0=\[FP\+-3608\]; - ae: 00 32 P0=R0; - b0: 42 44 P2=P0<<2; - b2: ba 5a P2=P2\+FP; - b4: 20 e1 50 fb R0=-1200 \(X\); - b8: 00 32 P0=R0; - ba: 82 5a P2=P2\+P0; - bc: 10 91 R0=\[P2\]; - be: 08 93 \[P1\]=R0; + 80: 90 e0 00 00 LSETUP\(0x80 <loop_lc1>, 0x80 <loop_lc1>\) LC1; + 84: b0 e0 00 40 LSETUP\(0x84 <loop_lc1\+0x4>, 0x84 <loop_lc1\+0x4>\) LC1 = P4; + 88: f8 e0 1b 10 LSETUP\(0x78 <loop_lc0\+0x38>, 0xbe <loop_lc1\+0x3e>\) LC1 = P1 >> 0x1; + 8c: 92 e0 ff 03 LSETUP\(0x90 <loop_lc1\+0x10>, 0x8a <loop_lc1\+0xa>\) LC1; + 90: bf e0 00 52 LSETUP\(0x8e <loop_lc1\+0xe>, 0xfffffc90 <loop_lc1\+0xfffffc10>\) LC1 = P5; + 94: ff e0 02 00 LSETUP\(0x92 <loop_lc1\+0x12>, 0x98 <loop_lc1\+0x18>\) LC1 = P0 >> 0x1; + 98: 38 e4 7a fc R0 = \[FP \+ -0xe18\]; + 9c: 00 32 P0 = R0; + 9e: 42 44 P2 = P0 << 0x2; + a0: ba 5a P2 = P2 \+ FP; + a2: 20 e1 f0 f1 R0 = -0xe10 \(X\);.* + a6: 00 32 P0 = R0; + a8: 42 5a P1 = P2 \+ P0; + aa: 38 e4 7a fc R0 = \[FP \+ -0xe18\]; + ae: 00 32 P0 = R0; + b0: 42 44 P2 = P0 << 0x2; + b2: ba 5a P2 = P2 \+ FP; + b4: 20 e1 50 fb R0 = -0x4b0 \(X\);.* + b8: 00 32 P0 = R0; + ba: 82 5a P2 = P2 \+ P0; + bc: 10 91 R0 = \[P2\]; + be: 08 93 \[P1\] = R0; diff --git a/gas/testsuite/gas/bfin/flow2.d b/gas/testsuite/gas/bfin/flow2.d index 64b782f..3eb500d 100644 --- a/gas/testsuite/gas/bfin/flow2.d +++ b/gas/testsuite/gas/bfin/flow2.d @@ -5,106 +5,106 @@ Disassembly of section .text: 00000000 <MY_LABEL1-0x2a>: - 0: 50 00 JUMP \(P0\); - 2: 51 00 JUMP \(P1\); - 4: 52 00 JUMP \(P2\); - 6: 53 00 JUMP \(P3\); - 8: 54 00 JUMP \(P4\); - a: 55 00 JUMP \(P5\); - c: 56 00 JUMP \(SP\); - e: 57 00 JUMP \(FP\); - 10: 80 00 JUMP \(PC\+P0\); - 12: 81 00 JUMP \(PC\+P1\); - 14: 82 00 JUMP \(PC\+P2\); - 16: 83 00 JUMP \(PC\+P3\); - 18: 84 00 JUMP \(PC\+P4\); - 1a: 85 00 JUMP \(PC\+P5\); - 1c: 86 00 JUMP \(PC\+SP\); - 1e: 87 00 JUMP \(PC\+FP\); - 20: 00 20 JUMP.S 20 <MY_LABEL1-0xa>; - 22: 69 22 JUMP.S 4f4.* - 24: 97 2d JUMP.S fffffb52.* - 26: 01 20 JUMP.S 28 <MY_LABEL1-0x2>; - 28: ff 2f JUMP.S 26 <MY_LABEL1-0x4>; + 0: 50 00 JUMP \(P0\); + 2: 51 00 JUMP \(P1\); + 4: 52 00 JUMP \(P2\); + 6: 53 00 JUMP \(P3\); + 8: 54 00 JUMP \(P4\); + a: 55 00 JUMP \(P5\); + c: 56 00 JUMP \(SP\); + e: 57 00 JUMP \(FP\); + 10: 80 00 JUMP \(PC \+ P0\); + 12: 81 00 JUMP \(PC \+ P1\); + 14: 82 00 JUMP \(PC \+ P2\); + 16: 83 00 JUMP \(PC \+ P3\); + 18: 84 00 JUMP \(PC \+ P4\); + 1a: 85 00 JUMP \(PC \+ P5\); + 1c: 86 00 JUMP \(PC \+ SP\); + 1e: 87 00 JUMP \(PC \+ FP\); + 20: 00 20 JUMP.S 0x20 <MY_LABEL1-0xa>; + 22: 69 22 JUMP.S 0x4f4 .* + 24: 97 2d JUMP.S 0xfffffb52 .* + 26: 01 20 JUMP.S 0x28 <MY_LABEL1-0x2>; + 28: ff 2f JUMP.S 0x26 <MY_LABEL1-0x4>; 0000002a <MY_LABEL1>: - 2a: 00 20 JUMP.S 2a <MY_LABEL1>; - 2c: 69 22 JUMP.S 4fe.* - 2e: 97 2d JUMP.S fffffb5c.* - 30: 01 20 JUMP.S 32 <MY_LABEL1\+0x8>; - 32: ff 2f JUMP.S 30 <MY_LABEL1\+0x6>; - 34: c0 e2 00 00 JUMP.L ff800034.* - 38: 3f e2 ff ff JUMP.L 800036.* - 3c: 00 e2 00 00 JUMP.L 3c <MY_LABEL1\+0x12>; - 40: 00 e2 69 02 JUMP.L 512.* - 44: ff e2 97 fd JUMP.L fffffb72.* - 48: 00 e2 01 00 JUMP.L 4a <MY_LABEL1\+0x20>; - 4c: ff e2 ff ff JUMP.L 4a <MY_LABEL1\+0x20>; - 50: ed 2f JUMP.S 2a <MY_LABEL1>; - 52: d7 2f JUMP.S 0 .* - 54: d6 2f JUMP.S 0 .* - 56: d5 2f JUMP.S 0 .* - 58: 04 1b IF CC JUMP fffffe60.* - 5a: 5a 18 IF CC JUMP 10e.* - 5c: 00 18 IF CC JUMP 5c <MY_LABEL1\+0x32>; - 5e: 04 1f IF CC JUMP fffffe66.*\(BP\); - 60: 5a 1c IF CC JUMP 114.*\(BP\); - 62: 91 13 IF ! CC JUMP ffffff84.*; - 64: 90 10 IF ! CC JUMP 184.*; - 66: 91 17 IF ! CC JUMP ffffff88.*\(BP\); - 68: 90 14 IF ! CC JUMP 188.*\(BP\); - 6a: e0 1b IF CC JUMP 2a <MY_LABEL1>; - 6c: ca 1b IF CC JUMP 0 <MY_LABEL1-0x2a>; - 6e: de 1f IF CC JUMP 2a <MY_LABEL1>\(BP\); - 70: c8 1f IF CC JUMP 0 <MY_LABEL1-0x2a>\(BP\); - 72: dc 13 IF ! CC JUMP 2a <MY_LABEL1>; - 74: c6 13 IF ! CC JUMP 0 <MY_LABEL1-0x2a>; - 76: da 17 IF ! CC JUMP 2a <MY_LABEL1>\(BP\); - 78: c4 17 IF ! CC JUMP 0 <MY_LABEL1-0x2a>\(BP\); - 7a: 60 00 CALL \(P0\); - 7c: 61 00 CALL \(P1\); - 7e: 62 00 CALL \(P2\); - 80: 63 00 CALL \(P3\); - 82: 64 00 CALL \(P4\); - 84: 65 00 CALL \(P5\); - 86: 70 00 CALL \(PC\+P0\); - 88: 71 00 CALL \(PC\+P1\); - 8a: 72 00 CALL \(PC\+P2\); - 8c: 73 00 CALL \(PC\+P3\); - 8e: 74 00 CALL \(PC\+P4\); - 90: 75 00 CALL \(PC\+P5\); - 92: 09 e3 2b 1a CALL 1234e8.*; - 96: ff e3 97 fd CALL fffffbc4.*; - 9a: ff e3 c8 ff CALL 2a <MY_LABEL1>; - 9e: ff e3 b1 ff CALL 0 <MY_LABEL1-0x2a>; + 2a: 00 20 JUMP.S 0x2a <MY_LABEL1>; + 2c: 69 22 JUMP.S 0x4fe .* + 2e: 97 2d JUMP.S 0xfffffb5c .* + 30: 01 20 JUMP.S 0x32 <MY_LABEL1\+0x8>; + 32: ff 2f JUMP.S 0x30 <MY_LABEL1\+0x6>; + 34: c0 e2 00 00 JUMP.L 0xff800034 .* + 38: 3f e2 ff ff JUMP.L 0x800036 .* + 3c: 00 e2 00 00 JUMP.L 0x3c <MY_LABEL1\+0x12>; + 40: 00 e2 69 02 JUMP.L 0x512 .* + 44: ff e2 97 fd JUMP.L 0xfffffb72 .* + 48: 00 e2 01 00 JUMP.L 0x4a <MY_LABEL1\+0x20>; + 4c: ff e2 ff ff JUMP.L 0x4a <MY_LABEL1\+0x20>; + 50: ed 2f JUMP.S 0x2a <MY_LABEL1>; + 52: d7 2f JUMP.S 0x0 .* + 54: d6 2f JUMP.S 0x0 .* + 56: d5 2f JUMP.S 0x0 .* + 58: 04 1b IF CC JUMP 0xfffffe60 .* + 5a: 5a 18 IF CC JUMP 0x10e .* + 5c: 00 18 IF CC JUMP 0x5c <MY_LABEL1\+0x32>; + 5e: 04 1f IF CC JUMP 0xfffffe66 .*\(BP\); + 60: 5a 1c IF CC JUMP 0x114 .*\(BP\); + 62: 91 13 IF !CC JUMP 0xffffff84 .*; + 64: 90 10 IF !CC JUMP 0x184 .*; + 66: 91 17 IF !CC JUMP 0xffffff88 .*\(BP\); + 68: 90 14 IF !CC JUMP 0x188 .*\(BP\); + 6a: e0 1b IF CC JUMP 0x2a <MY_LABEL1>; + 6c: ca 1b IF CC JUMP 0x0 <MY_LABEL1-0x2a>; + 6e: de 1f IF CC JUMP 0x2a <MY_LABEL1> \(BP\); + 70: c8 1f IF CC JUMP 0x0 <MY_LABEL1-0x2a> \(BP\); + 72: dc 13 IF !CC JUMP 0x2a <MY_LABEL1>; + 74: c6 13 IF !CC JUMP 0x0 <MY_LABEL1-0x2a>; + 76: da 17 IF !CC JUMP 0x2a <MY_LABEL1> \(BP\); + 78: c4 17 IF !CC JUMP 0x0 <MY_LABEL1-0x2a> \(BP\); + 7a: 60 00 CALL \(P0\); + 7c: 61 00 CALL \(P1\); + 7e: 62 00 CALL \(P2\); + 80: 63 00 CALL \(P3\); + 82: 64 00 CALL \(P4\); + 84: 65 00 CALL \(P5\); + 86: 70 00 CALL \(PC \+ P0\); + 88: 71 00 CALL \(PC \+ P1\); + 8a: 72 00 CALL \(PC \+ P2\); + 8c: 73 00 CALL \(PC \+ P3\); + 8e: 74 00 CALL \(PC \+ P4\); + 90: 75 00 CALL \(PC \+ P5\); + 92: 09 e3 2b 1a CALL 0x1234e8 .*; + 96: ff e3 97 fd CALL 0xfffffbc4 .*; + 9a: ff e3 c8 ff CALL 0x2a <MY_LABEL1>; + 9e: ff e3 b1 ff CALL 0x0 <MY_LABEL1-0x2a>; a2: 10 00 RTS; a4: 11 00 RTI; a6: 12 00 RTX; a8: 13 00 RTN; aa: 14 00 RTE; - ac: 82 e0 02 00 LSETUP\(b0 <MY_LABEL1\+0x86>,b0 <MY_LABEL1\+0x86>\)LC0; - b0: 84 e0 06 00 LSETUP\(b8 <beg_poll_bit>,bc <end_poll_bit>\)LC0; + ac: 82 e0 02 00 LSETUP\(0xb0 <MY_LABEL1\+0x86>, 0xb0 <MY_LABEL1\+0x86>\) LC0; + b0: 84 e0 06 00 LSETUP\(0xb8 <beg_poll_bit>, 0xbc <end_poll_bit>\) LC0; b4: 00 00 NOP; ... 000000b8 <beg_poll_bit>: - b8: 80 e1 01 00 R0=1 <MY_LABEL1-0x29>\(Z\); + b8: 80 e1 01 00 R0 = 0x1 \(Z\);.* 000000bc <end_poll_bit>: - bc: 81 e1 02 00 R1=2 <MY_LABEL1-0x28>\(Z\); - c0: 92 e0 03 00 LSETUP\(c4 <end_poll_bit\+0x8>,c6 <end_poll_bit\+0xa>\)LC1; - c4: 93 e0 05 00 LSETUP\(ca <FIR_filter>,ce <bottom_of_FIR_filter>\)LC1; + bc: 81 e1 02 00 R1 = 0x2 \(Z\);.* + c0: 92 e0 03 00 LSETUP\(0xc4 <end_poll_bit\+0x8>, 0xc6 <end_poll_bit\+0xa>\) LC1; + c4: 93 e0 05 00 LSETUP\(0xca <FIR_filter>, 0xce <bottom_of_FIR_filter>\) LC1; ... 000000ca <FIR_filter>: - ca: 80 e1 01 00 R0=1 <MY_LABEL1-0x29>\(Z\); + ca: 80 e1 01 00 R0 = 0x1 \(Z\);.* 000000ce <bottom_of_FIR_filter>: - ce: 81 e1 02 00 R1=2 <MY_LABEL1-0x28>\(Z\); - d2: a2 e0 04 10 LSETUP\(d6 <bottom_of_FIR_filter\+0x8>,da <bottom_of_FIR_filter\+0xc>\)LC0=P1; - d6: e2 e0 04 10 LSETUP\(da <bottom_of_FIR_filter\+0xc>,de <bottom_of_FIR_filter\+0x10>\)LC0=P1>>1; - da: 82 e0 03 00 LSETUP\(de <bottom_of_FIR_filter\+0x10>,e0 <bottom_of_FIR_filter\+0x12>\)LC0; - de: 08 60 R0=0x1\(x\); - e0: 11 60 R1=0x2\(x\); - e2: 90 e0 00 00 LSETUP\(e2 <bottom_of_FIR_filter\+0x14>,e2 <bottom_of_FIR_filter\+0x14>\)LC1; + ce: 81 e1 02 00 R1 = 0x2 \(Z\);.* + d2: a2 e0 04 10 LSETUP\(0xd6 <bottom_of_FIR_filter\+0x8>, 0xda <bottom_of_FIR_filter\+0xc>\) LC0 = P1; + d6: e2 e0 04 10 LSETUP\(0xda <bottom_of_FIR_filter\+0xc>, 0xde <bottom_of_FIR_filter\+0x10>\) LC0 = P1 >> 0x1; + da: 82 e0 03 00 LSETUP\(0xde <bottom_of_FIR_filter\+0x10>, 0xe0 <bottom_of_FIR_filter\+0x12>\) LC0; + de: 08 60 R0 = 0x1 \(X\);.* + e0: 11 60 R1 = 0x2 \(X\);.* + e2: 90 e0 00 00 LSETUP\(0xe2 <bottom_of_FIR_filter\+0x14>, 0xe2 <bottom_of_FIR_filter\+0x14>\) LC1; ... diff --git a/gas/testsuite/gas/bfin/load.d b/gas/testsuite/gas/bfin/load.d index b97142b..5d03d8c 100644 --- a/gas/testsuite/gas/bfin/load.d +++ b/gas/testsuite/gas/bfin/load.d @@ -5,112 +5,112 @@ Disassembly of section .text: 00000000 <load_immediate>: - 0: 17 e1 ff ff M3.L=0xffff.* - 4: 1a e1 fe ff B2.L=0xfffe.* - 8: 0e e1 00 00 SP.L=0.* - c: 0f e1 dc fe FP.L=0xfedc.* - 10: 40 e1 02 00 R0.H=0x2.* - 14: 4d e1 20 00 P5.H=0x20.* - 18: 52 e1 04 f2 I2.H=0xf204.* - 1c: 59 e1 40 00 B1.H=0x40.* - 20: 5c e1 ff ff L0.H=0xffff.* - 24: 45 e1 00 00 R5.H=0x0.* - 28: 5a e1 00 00 B2.H=0x0.* - 2c: 8f e1 20 ff FP=ff20.* - 30: 9e e1 20 00 L2=20.* - 34: 85 e1 00 00 R5=0 <load_immediate>\(Z\); - 38: 08 c4 [0-3][[:xdigit:]] 00 A0=0; - 3c: 08 c4 [0-3][[:xdigit:]] 40 A1=0; - 40: 08 c4 [0-3][[:xdigit:]] 80 A1=A0=0; - 44: 02 62 R2=-64\(x\); - 46: 20 e1 7f 00 R0=0x7f \(X\); - 4a: 02 68 P2=0x0; - 4c: 06 6b SP=-32; - 4e: 67 69 FP=0x2c; - 50: 3f e1 00 08 L3=0x800 \(X\); - 54: 36 e1 ff 7f M2=0x7fff \(X\); - 58: 81 60 R1=0x10\(x\); - 5a: 3c e1 00 00 L0=0x0 \(X\); - 5e: 27 e1 f3 00 R7=0xf3 \(X\); - 62: 00 e1 03 00 R0.L=0x3; - 66: 01 e1 0f 00 R1.L=0xf; + 0: 17 e1 ff ff M3.L = 0xffff;.* + 4: 1a e1 fe ff B2.L = 0xfffe;.* + 8: 0e e1 00 00 SP.L = 0x0;.* + c: 0f e1 dc fe FP.L = 0xfedc;.* + 10: 40 e1 02 00 R0.H = 0x2;.* + 14: 4d e1 20 00 P5.H = 0x20;.* + 18: 52 e1 04 f2 I2.H = 0xf204;.* + 1c: 59 e1 40 00 B1.H = 0x40;.* + 20: 5c e1 ff ff L0.H = 0xffff;.* + 24: 45 e1 00 00 R5.H = 0x0;.* + 28: 5a e1 00 00 B2.H = 0x0;.* + 2c: 8f e1 20 ff FP = 0xff20 \(Z\);.* + 30: 9e e1 20 00 L2 = 0x20 \(Z\);.* + 34: 85 e1 00 00 R5 = 0x0 \(Z\);.* + 38: 08 c4 [0-3][[:xdigit:]] 00 A0 = 0; + 3c: 08 c4 [0-3][[:xdigit:]] 40 A1 = 0; + 40: 08 c4 [0-3][[:xdigit:]] 80 A1 = A0 = 0; + 44: 02 62 R2 = -0x40 \(X\);.* + 46: 20 e1 7f 00 R0 = 0x7f \(X\);.* + 4a: 02 68 P2 = 0x0 \(X\);.* + 4c: 06 6b SP = -0x20 \(X\);.* + 4e: 67 69 FP = 0x2c \(X\);.* + 50: 3f e1 00 08 L3 = 0x800 \(X\);.* + 54: 36 e1 ff 7f M2 = 0x7fff \(X\);.* + 58: 81 60 R1 = 0x10 \(X\);.* + 5a: 3c e1 00 00 L0 = 0x0 \(X\);.* + 5e: 27 e1 f3 00 R7 = 0xf3 \(X\);.* + 62: 00 e1 03 00 R0.L = 0x3;.* + 66: 01 e1 0f 00 R1.L = 0xf;.* 0000006a <load_pointer_register>: - 6a: 7e 91 SP=\[FP\]; - 6c: 47 90 FP=\[P0\+\+\]; - 6e: f1 90 P1=\[SP--\]; - 70: 96 af SP=\[P2\+0x38\]; - 72: 3b ac P3=\[FP\+0x0\]; - 74: 3c e5 ff 7f P4=\[FP\+0x1fffc\]; - 78: 3e e5 01 80 SP=\[FP\+-131068\]; - 7c: 26 ac SP=\[P4\+0x0\]; - 7e: 0d b8 P5=\[FP-128\]; + 6a: 7e 91 SP = \[FP\]; + 6c: 47 90 FP = \[P0\+\+\]; + 6e: f1 90 P1 = \[SP--\]; + 70: 96 af SP = \[P2 \+ 0x38\]; + 72: 3b ac P3 = \[FP \+ 0x0\]; + 74: 3c e5 ff 7f P4 = \[FP \+ 0x1fffc\]; + 78: 3e e5 01 80 SP = \[FP \+ -0x1fffc\]; + 7c: 26 ac SP = \[P4 \+ 0x0\]; + 7e: 0d b8 P5 = \[FP -0x80\]; 00000080 <load_data_register>: - 80: 07 91 R7=\[P0\]; - 82: 2e 90 R6=\[P5\+\+\]; - 84: a5 90 R5=\[P4--\]; - 86: bc a2 R4=\[FP\+0x28\]; - 88: 33 e4 ff 7f R3=\[SP\+0x1fffc\]; - 8c: 32 a0 R2=\[SP\+0x0\]; - 8e: 39 e4 01 80 R1=\[FP\+-131068\]; - 92: 06 80 R0=\[SP\+\+P0\]; - 94: 05 b8 R5=\[FP-128\]; - 96: 02 9d R2=\[I0\]; - 98: 09 9c R1=\[I1\+\+\]; - 9a: 93 9c R3=\[I2--\]; - 9c: 9c 9d R4=\[I3\+\+M0\]; + 80: 07 91 R7 = \[P0\]; + 82: 2e 90 R6 = \[P5\+\+\]; + 84: a5 90 R5 = \[P4--\]; + 86: bc a2 R4 = \[FP \+ 0x28\]; + 88: 33 e4 ff 7f R3 = \[SP \+ 0x1fffc\]; + 8c: 32 a0 R2 = \[SP \+ 0x0\]; + 8e: 39 e4 01 80 R1 = \[FP \+ -0x1fffc\]; + 92: 06 80 R0 = \[SP \+\+ P0\]; + 94: 05 b8 R5 = \[FP -0x80\]; + 96: 02 9d R2 = \[I0\]; + 98: 09 9c R1 = \[I1\+\+\]; + 9a: 93 9c R3 = \[I2--\]; + 9c: 9c 9d R4 = \[I3 \+\+ M0\]; 0000009e <load_half_word_zero_extend>: - 9e: 37 95 R7=W\[SP\] \(Z\); - a0: 3e 94 R6=W\[FP\+\+\] \(Z\); - a2: 85 94 R5=W\[P0--\] \(Z\); - a4: cc a7 R4=W\[P1\+0x1e\] \(Z\); - a6: 73 e4 fe 7f R3=W\[SP\+0xfffc\] \(Z\); - aa: 7a e4 02 80 R2=W\[FP\+-65532\] \(Z\); - ae: 28 86 R0=W\[P0\+\+P5\] \(Z\); + 9e: 37 95 R7 = W\[SP\] \(Z\); + a0: 3e 94 R6 = W\[FP\+\+\] \(Z\); + a2: 85 94 R5 = W\[P0--\] \(Z\); + a4: cc a7 R4 = W\[P1 \+ 0x1e\] \(Z\); + a6: 73 e4 fe 7f R3 = W\[SP \+ 0xfffc\] \(Z\); + aa: 7a e4 02 80 R2 = W\[FP \+ -0xfffc\] \(Z\); + ae: 28 86 R0 = W\[P0 \+\+ P5\] \(Z\); 000000b0 <load_half_word_sign_extend>: - b0: 77 95 R7=W\[SP\]\(X\); - b2: 7e 94 R6=W\[FP\+\+\]\(X\); - b4: c5 94 R5=W\[P0--\]\(X\); - b6: 0d ab R5=W\[P1\+0x18\]\(X\); - b8: 73 e5 fe 7f R3=W\[SP\+0xfffc\]\(X\); - bc: 7f e5 02 80 R7=W\[FP\+-65532\]\(X\); - c0: 51 8e R1=W\[P1\+\+P2\]\(X\); + b0: 77 95 R7 = W\[SP\] \(X\); + b2: 7e 94 R6 = W\[FP\+\+\] \(X\); + b4: c5 94 R5 = W\[P0--\] \(X\); + b6: 0d ab R5 = W\[P1 \+ 0x18\] \(X\); + b8: 73 e5 fe 7f R3 = W\[SP \+ 0xfffc\] \(X\); + bc: 7f e5 02 80 R7 = W\[FP \+ -0xfffc\] \(X\); + c0: 51 8e R1 = W\[P1 \+\+ P2\] \(X\); 000000c2 <load_high_data_register_half>: - c2: 40 9d R0.H=W\[I0\]; - c4: 49 9c R1.H=W\[I1\+\+\]; - c6: d2 9c R2.H=W\[I2--\]; - c8: f6 84 R3.H=W\[SP\]; - ca: 07 85 R4.H=W\[FP\+\+P0\]; + c2: 40 9d R0.H = W\[I0\]; + c4: 49 9c R1.H = W\[I1\+\+\]; + c6: d2 9c R2.H = W\[I2--\]; + c8: f6 84 R3.H = W\[SP\]; + ca: 07 85 R4.H = W\[FP \+\+ P0\]; 000000cc <load_low_data_register_half>: - cc: 3f 9d R7.L=W\[I3\]; - ce: 36 9c R6.L=W\[I2\+\+\]; - d0: ad 9c R5.L=W\[I1--\]; - d2: 00 83 R4.L=W\[P0\]; - d4: da 82 R3.L=W\[P2\+\+P3\]; + cc: 3f 9d R7.L = W\[I3\]; + ce: 36 9c R6.L = W\[I2\+\+\]; + d0: ad 9c R5.L = W\[I1--\]; + d2: 00 83 R4.L = W\[P0\]; + d4: da 82 R3.L = W\[P2 \+\+ P3\]; 000000d6 <load_byte_zero_extend>: - d6: 05 99 R5=B\[P0\] \(Z\); - d8: 0c 98 R4=B\[P1\+\+\] \(Z\); - da: 90 98 R0=B\[P2--\] \(Z\); - dc: b3 e4 ff 7f R3=B\[SP\+0x7fff\] \(Z\); - e0: b7 e4 01 80 R7=B\[SP\+-32767\] \(Z\); + d6: 05 99 R5 = B\[P0\] \(Z\); + d8: 0c 98 R4 = B\[P1\+\+\] \(Z\); + da: 90 98 R0 = B\[P2--\] \(Z\); + dc: b3 e4 ff 7f R3 = B\[SP \+ 0x7fff\] \(Z\); + e0: b7 e4 01 80 R7 = B\[SP \+ -0x7fff\] \(Z\); 000000e4 <load_byte_sign_extend>: - e4: 45 99 R5=B\[P0\]\(X\); - e6: 4a 98 R2=B\[P1\+\+\]\(X\); - e8: fb 98 R3=B\[FP--\]\(X\); - ea: b7 e5 00 00 R7=B\[SP\+0x0\]\(X\); - ee: be e5 01 80 R6=B\[FP\+-32767\]\(X\); + e4: 45 99 R5 = B\[P0\] \(X\); + e6: 4a 98 R2 = B\[P1\+\+\] \(X\); + e8: fb 98 R3 = B\[FP--\] \(X\); + ea: b7 e5 00 00 R7 = B\[SP \+ 0x0\] \(X\); + ee: be e5 01 80 R6 = B\[FP \+ -0x7fff\] \(X\); 000000f2 <load_data1>: ... 000000f3 <load_data2>: - f3: 10 00 IF ! CC JUMP f3 <load_data2>; + f3: 10 00 IF !CC JUMP 0xf3 <load_data2>; f5: 00 00 NOP; ... diff --git a/gas/testsuite/gas/bfin/logical.d b/gas/testsuite/gas/bfin/logical.d index d35f9fd..f40c20c 100644 --- a/gas/testsuite/gas/bfin/logical.d +++ b/gas/testsuite/gas/bfin/logical.d @@ -5,35 +5,35 @@ Disassembly of section .text: 00000000 <and>: - 0: c8 55 R7=R0&R1; - 2: 9b 54 R2=R3&R3; - 4: 91 55 R6=R1&R2; + 0: c8 55 R7 = R0 & R1; + 2: 9b 54 R2 = R3 & R3; + 4: 91 55 R6 = R1 & R2; 00000006 <not>: - 6: c8 43 R0=~R1; - 8: d1 43 R1=~R2; - a: e3 43 R3=~R4; - c: ec 43 R4=~R5; + 6: c8 43 R0 =~ R1; + 8: d1 43 R1 =~ R2; + a: e3 43 R3 =~ R4; + c: ec 43 R4 =~ R5; 0000000e <or>: - e: 08 56 R0=R0\|R1; - 10: a3 56 R2=R3\|R4; - 12: 7e 57 R5=R6\|R7; + e: 08 56 R0 = R0 \| R1; + 10: a3 56 R2 = R3 \| R4; + 12: 7e 57 R5 = R6 \| R7; 00000014 <xor>: - 14: 5d 59 R5=R5\^R3; - 16: 02 59 R4=R2\^R0; - 18: 01 58 R0=R1\^R0; + 14: 5d 59 R5 = R5 \^ R3; + 16: 02 59 R4 = R2 \^ R0; + 18: 01 58 R0 = R1 \^ R0; 0000001a <bxor>: - 1a: 0b c6 00 4e R7.L=CC=BXOR\(A0,R0\); - 1e: 0b c6 08 4e R7.L=CC=BXOR\(A0,R1\); - 22: 0c c6 00 4a R5.L=CC=BXOR\( A0,A1 ,CC \); - 26: 0c c6 00 48 R4.L=CC=BXOR\( A0,A1 ,CC \); + 1a: 0b c6 00 4e R7.L = CC = BXOR \(A0, R0\); + 1e: 0b c6 08 4e R7.L = CC = BXOR \(A0, R1\); + 22: 0c c6 00 4a R5.L = CC = BXOR \(A0, A1, CC\); + 26: 0c c6 00 48 R4.L = CC = BXOR \(A0, A1, CC\); 0000002a <bxorshift>: - 2a: 0b c6 38 06 R3.L=CC=BXORSHIFT\(A0,R7\); - 2e: 0b c6 10 04 R2.L=CC=BXORSHIFT\(A0,R2\); - 32: 0c c6 00 00 A0=BXORSHIFT\(A0,A1 ,CC\); - 36: 0c c6 00 00 A0=BXORSHIFT\(A0,A1 ,CC\); + 2a: 0b c6 38 06 R3.L = CC = BXORSHIFT \(A0, R7\); + 2e: 0b c6 10 04 R2.L = CC = BXORSHIFT \(A0, R2\); + 32: 0c c6 00 00 A0 = BXORSHIFT \(A0, A1, CC\); + 36: 0c c6 00 00 A0 = BXORSHIFT \(A0, A1, CC\); ... diff --git a/gas/testsuite/gas/bfin/logical2.d b/gas/testsuite/gas/bfin/logical2.d index 0a70911..a4eb223 100644 --- a/gas/testsuite/gas/bfin/logical2.d +++ b/gas/testsuite/gas/bfin/logical2.d @@ -6,38 +6,38 @@ Disassembly of section .text: 00000000 <.text>: - 0: ff 55 R7=R7&R7; - 2: c7 55 R7=R7&R0; - 4: cf 55 R7=R7&R1; - 6: 7f 54 R1=R7&R7; - 8: 87 54 R2=R7&R0; - a: cf 54 R3=R7&R1; - c: ff 43 R7=~R7; - e: c7 43 R7=~R0; - 10: f8 43 R0=~R7; - 12: d0 43 R0=~R2; - 14: ff 57 R7=R7\|R7; - 16: cf 57 R7=R7\|R1; - 18: c7 57 R7=R7\|R0; - 1a: 7f 56 R1=R7\|R7; - 1c: 8f 56 R2=R7\|R1; - 1e: c7 56 R3=R7\|R0; - 20: ff 59 R7=R7\^R7; - 22: cf 59 R7=R7\^R1; - 24: c7 59 R7=R7\^R0; - 26: 7f 58 R1=R7\^R7; - 28: 8f 58 R2=R7\^R1; - 2a: c7 58 R3=R7\^R0; - 2c: 0b c6 00 00 R0.L=CC=BXORSHIFT\(A0,R0\); - 30: 0b c6 08 00 R0.L=CC=BXORSHIFT\(A0,R1\); - 34: 0b c6 00 06 R3.L=CC=BXORSHIFT\(A0,R0\); - 38: 0b c6 08 06 R3.L=CC=BXORSHIFT\(A0,R1\); - 3c: 0b c6 00 40 R0.L=CC=BXOR\(A0,R0\); - 40: 0b c6 08 40 R0.L=CC=BXOR\(A0,R1\); - 44: 0b c6 00 46 R3.L=CC=BXOR\(A0,R0\); - 48: 0b c6 08 46 R3.L=CC=BXOR\(A0,R1\); - 4c: 0c c6 00 40 R0.L=CC=BXOR\( A0,A1 ,CC \); - 50: 0c c6 00 40 R0.L=CC=BXOR\( A0,A1 ,CC \); - 54: 0c c6 00 46 R3.L=CC=BXOR\( A0,A1 ,CC \); - 58: 0c c6 00 46 R3.L=CC=BXOR\( A0,A1 ,CC \); - 5c: 0c c6 00 00 A0=BXORSHIFT\(A0,A1 ,CC\); + 0: ff 55 R7 = R7 & R7; + 2: c7 55 R7 = R7 & R0; + 4: cf 55 R7 = R7 & R1; + 6: 7f 54 R1 = R7 & R7; + 8: 87 54 R2 = R7 & R0; + a: cf 54 R3 = R7 & R1; + c: ff 43 R7 =~ R7; + e: c7 43 R7 =~ R0; + 10: f8 43 R0 =~ R7; + 12: d0 43 R0 =~ R2; + 14: ff 57 R7 = R7 \| R7; + 16: cf 57 R7 = R7 \| R1; + 18: c7 57 R7 = R7 \| R0; + 1a: 7f 56 R1 = R7 \| R7; + 1c: 8f 56 R2 = R7 \| R1; + 1e: c7 56 R3 = R7 \| R0; + 20: ff 59 R7 = R7 \^ R7; + 22: cf 59 R7 = R7 \^ R1; + 24: c7 59 R7 = R7 \^ R0; + 26: 7f 58 R1 = R7 \^ R7; + 28: 8f 58 R2 = R7 \^ R1; + 2a: c7 58 R3 = R7 \^ R0; + 2c: 0b c6 00 00 R0.L = CC = BXORSHIFT \(A0, R0\); + 30: 0b c6 08 00 R0.L = CC = BXORSHIFT \(A0, R1\); + 34: 0b c6 00 06 R3.L = CC = BXORSHIFT \(A0, R0\); + 38: 0b c6 08 06 R3.L = CC = BXORSHIFT \(A0, R1\); + 3c: 0b c6 00 40 R0.L = CC = BXOR \(A0, R0\); + 40: 0b c6 08 40 R0.L = CC = BXOR \(A0, R1\); + 44: 0b c6 00 46 R3.L = CC = BXOR \(A0, R0\); + 48: 0b c6 08 46 R3.L = CC = BXOR \(A0, R1\); + 4c: 0c c6 00 40 R0.L = CC = BXOR \(A0, A1, CC\); + 50: 0c c6 00 40 R0.L = CC = BXOR \(A0, A1, CC\); + 54: 0c c6 00 46 R3.L = CC = BXOR \(A0, A1, CC\); + 58: 0c c6 00 46 R3.L = CC = BXOR \(A0, A1, CC\); + 5c: 0c c6 00 00 A0 = BXORSHIFT \(A0, A1, CC\); diff --git a/gas/testsuite/gas/bfin/move.d b/gas/testsuite/gas/bfin/move.d index 62bb5e1..1a83e25 100644 --- a/gas/testsuite/gas/bfin/move.d +++ b/gas/testsuite/gas/bfin/move.d @@ -5,36 +5,36 @@ Disassembly of section .text: 00000000 <move_register>: - 0: 38 31 R7=A0.x; - 2: fb 32 FP=B3; - 4: 35 36 L2=R5; - 6: b2 34 M2=I2; - 8: d8 39 A1.w=USP; - a: 06 31 R0=ASTAT; - c: c9 31 R1=SEQSTAT; - e: d2 31 R2=SYSCFG; - 10: db 31 R3=RETI; - 12: e4 31 R4=RETX; - 14: ed 31 R5=RETN; - 16: f6 31 R6=RETE; - 18: 3f 31 R7=RETS; - 1a: a8 31 R5=LC0; - 1c: a3 31 R4=LC1; - 1e: 99 31 R3=LT0; - 20: 94 31 R2=LT1; - 22: 8a 31 R1=LB0; - 24: 85 31 R0=LB1; - 26: 96 31 R2=CYCLES; - 28: 9f 31 R3=CYCLES2; - 2a: cf 31 R1=EMUDAT; - 2c: 31 3d CYCLES=A0.w; - 2e: 7f 38 RETS=FP; - 30: e0 3d LT1=USP; - 32: 72 38 ASTAT=P2; - 34: 08 c4 [0|3][0|f] c0 A0=A1; - 38: 08 c4 [0|3][0|f] e0 A1=A0; - 3c: 09 c4 00 20 A0=R0; - 40: 09 c4 08 a0 A1=R1; + 0: 38 31 R7 = A0.X; + 2: fb 32 FP = B3; + 4: 35 36 L2 = R5; + 6: b2 34 M2 = I2; + 8: d8 39 A1.W = USP; + a: 06 31 R0 = ASTAT; + c: c9 31 R1 = SEQSTAT; + e: d2 31 R2 = SYSCFG; + 10: db 31 R3 = RETI; + 12: e4 31 R4 = RETX; + 14: ed 31 R5 = RETN; + 16: f6 31 R6 = RETE; + 18: 3f 31 R7 = RETS; + 1a: a8 31 R5 = LC0; + 1c: a3 31 R4 = LC1; + 1e: 99 31 R3 = LT0; + 20: 94 31 R2 = LT1; + 22: 8a 31 R1 = LB0; + 24: 85 31 R0 = LB1; + 26: 96 31 R2 = CYCLES; + 28: 9f 31 R3 = CYCLES2; + 2a: cf 31 R1 = EMUDAT; + 2c: 31 3d CYCLES = A0.W; + 2e: 7f 38 RETS = FP; + 30: e0 3d LT1 = USP; + 32: 72 38 ASTAT = P2; + 34: 08 c4 [0|3][0|f] c0 A0 = A1; + 38: 08 c4 [0|3][0|f] e0 A1 = A0; + 3c: 09 c4 00 20 A0 = R0; + 40: 09 c4 08 a0 A1 = R1; 44: 8b c0 00 39 R4 = A0 \(FU\); 48: 2f c1 00 19 R5 = A1 \(ISS2\); 4c: 0b c0 80 39 R6 = A0; @@ -44,25 +44,25 @@ Disassembly of section .text: 0000005c <move_conditional>: 5c: 6a 07 IF CC R5 = P2; - 5e: b0 06 IF ! CC SP = R0; + 5e: b0 06 IF !CC SP = R0; 00000060 <move_half_to_full_zero_extend>: - 60: fa 42 R2=R7.L\(Z\); - 62: c8 42 R0=R1.L\(Z\); + 60: fa 42 R2 = R7.L \(Z\); + 62: c8 42 R0 = R1.L \(Z\); 00000064 <move_half_to_full_sign_extend>: - 64: 8d 42 R5=R1.L\(X\); - 66: 93 42 R3=R2.L\(X\); + 64: 8d 42 R5 = R1.L \(X\); + 66: 93 42 R3 = R2.L \(X\); 00000068 <move_register_half>: - 68: 09 c4 28 40 A0.x=R5.L; - 6c: 09 c4 10 c0 A1.x=R2.L; - 70: 0a c4 [0|3][0|6] 00 R0.L=A0.x; - 74: 0a c4 [0|3][0|6] 4e R7.L=A1.x; - 78: 09 c4 18 00 A0.L=R3.L; - 7c: 09 c4 20 80 A1.L=R4.L; - 80: 29 c4 30 00 A0.H=R6.H; - 84: 29 c4 28 80 A1.H=R5.H; + 68: 09 c4 28 40 A0.X = R5.L; + 6c: 09 c4 10 c0 A1.X = R2.L; + 70: 0a c4 [0|3][0|6] 00 R0.L = A0.X; + 74: 0a c4 [0|3][0|6] 4e R7.L = A1.X; + 78: 09 c4 18 00 A0.L = R3.L; + 7c: 09 c4 20 80 A1.L = R4.L; + 80: 29 c4 30 00 A0.H = R6.H; + 84: 29 c4 28 80 A1.H = R5.H; 88: 83 c1 00 38 R0.L = A0 \(IU\); 8c: 27 c0 40 18 R1.H = A1 \(S2RND\); 90: 07 c0 40 18 R1.H = A1; @@ -74,9 +74,9 @@ Disassembly of section .text: a8: 07 c0 00 38 R0.H = A1, R0.L = A0; 000000ac <move_byte_zero_extend>: - ac: 57 43 R7=R2.B\(Z\); - ae: 48 43 R0=R1.B\(Z\); + ac: 57 43 R7 = R2.B \(Z\); + ae: 48 43 R0 = R1.B \(Z\); 000000b0 <move_byte_sign_extend>: - b0: 4e 43 R6=R1.B\(Z\); - b2: 65 43 R5=R4.B\(Z\); + b0: 4e 43 R6 = R1.B \(Z\); + b2: 65 43 R5 = R4.B \(Z\); diff --git a/gas/testsuite/gas/bfin/move2.d b/gas/testsuite/gas/bfin/move2.d index 722f2e1..5c64252 100644 --- a/gas/testsuite/gas/bfin/move2.d +++ b/gas/testsuite/gas/bfin/move2.d @@ -5,222 +5,222 @@ Disassembly of section .text: 00000000 <.text>: - 0: 00 30 R0=R0; - 2: 09 30 R1=R1; - 4: 12 30 R2=R2; - 6: 1b 30 R3=R3; - 8: 24 30 R4=R4; - a: 2d 30 R5=R5; - c: 36 30 R6=R6; - e: 3f 30 R7=R7; - 10: 40 32 P0=P0; - 12: 49 32 P1=P1; - 14: 52 32 P2=P2; - 16: 5b 32 P3=P3; - 18: 64 32 P4=P4; - 1a: 6d 32 P5=P5; - 1c: 76 32 SP=SP; - 1e: 7f 32 FP=FP; - 20: 00 39 A0.x=A0.x; - 22: 09 39 A0.w=A0.w; - 24: 12 39 A1.x=A1.x; - 26: 1b 39 A1.w=A1.w; - 28: 03 31 R0=A1.w; - 2a: 0a 31 R1=A1.x; - 2c: 11 31 R2=A0.w; - 2e: 18 31 R3=A0.x; - 30: 67 30 R4=FP; - 32: 6e 30 R5=SP; - 34: 75 30 R6=P5; - 36: 7c 30 R7=P4; - 38: 43 32 P0=P3; - 3a: 4a 32 P1=P2; - 3c: 51 32 P2=P1; - 3e: 58 32 P3=P0; - 40: 27 32 P4=R7; - 42: 2e 32 P5=R6; - 44: 35 32 SP=R5; - 46: 3c 32 FP=R4; - 48: 03 38 A0.x=R3; - 4a: 0a 38 A0.w=R2; - 4c: 11 38 A1.x=R1; - 4e: 18 38 A1.w=R0; - 50: 01 39 A0.x=A0.w; - 52: 03 39 A0.x=A1.w; - 54: 02 39 A0.x=A1.x; - 56: 13 39 A1.x=A1.w; - 58: 11 39 A1.x=A0.w; - 5a: 10 39 A1.x=A0.x; - 5c: 09 39 A0.w=A0.w; - 5e: 0b 39 A0.w=A1.w; - 60: 0a 39 A0.w=A1.x; - 62: 1b 39 A1.w=A1.w; - 64: 19 39 A1.w=A0.w; - 66: 18 39 A1.w=A0.x; - 68: 80 30 R0=I0; - 6a: 89 30 R1=I1; - 6c: 92 30 R2=I2; - 6e: 9b 30 R3=I3; - 70: a4 30 R4=M0; - 72: ad 30 R5=M1; - 74: b6 30 R6=M2; - 76: bf 30 R7=M3; - 78: c0 30 R0=B0; - 7a: c9 30 R1=B1; - 7c: d2 30 R2=B2; - 7e: db 30 R3=B3; - 80: e4 30 R4=L0; - 82: ed 30 R5=L1; - 84: f6 30 R6=L2; - 86: ff 30 R7=L3; - 88: 80 32 P0=I0; - 8a: 89 32 P1=I1; - 8c: 92 32 P2=I2; - 8e: 9b 32 P3=I3; - 90: a4 32 P4=M0; - 92: ad 32 P5=M1; - 94: b6 32 SP=M2; - 96: bf 32 FP=M3; - 98: c0 32 P0=B0; - 9a: c9 32 P1=B1; - 9c: d2 32 P2=B2; - 9e: db 32 P3=B3; - a0: e4 32 P4=L0; - a2: ed 32 P5=L1; - a4: f6 32 SP=L2; - a6: ff 32 FP=L3; - a8: 80 38 A0.x=I0; - aa: 89 38 A0.w=I1; - ac: 92 38 A1.x=I2; - ae: 9b 38 A1.w=I3; - b0: 84 38 A0.x=M0; - b2: 8d 38 A0.w=M1; - b4: 96 38 A1.x=M2; - b6: 9f 38 A1.w=M3; - b8: c0 38 A0.x=B0; - ba: c9 38 A0.w=B1; - bc: d2 38 A1.x=B2; - be: db 38 A1.w=B3; - c0: c4 38 A0.x=L0; - c2: cd 38 A0.w=L1; - c4: d6 38 A1.x=L2; - c6: df 38 A1.w=L3; - c8: 00 34 I0=R0; - ca: 48 34 I1=P0; - cc: 56 34 I2=SP; - ce: 5f 34 I3=FP; - d0: 00 35 I0=A0.x; - d2: 09 35 I1=A0.w; - d4: 12 35 I2=A1.x; - d6: 1b 35 I3=A1.w; - d8: 20 34 M0=R0; - da: 68 34 M1=P0; - dc: 76 34 M2=SP; - de: 7f 34 M3=FP; - e0: 20 35 M0=A0.x; - e2: 29 35 M1=A0.w; - e4: 32 35 M2=A1.x; - e6: 3b 35 M3=A1.w; - e8: 00 36 B0=R0; - ea: 48 36 B1=P0; - ec: 56 36 B2=SP; - ee: 5f 36 B3=FP; - f0: 00 37 B0=A0.x; - f2: 09 37 B1=A0.w; - f4: 12 37 B2=A1.x; - f6: 1b 37 B3=A1.w; - f8: 20 36 L0=R0; - fa: 68 36 L1=P0; - fc: 76 36 L2=SP; - fe: 7f 36 L3=FP; - 100: 20 37 L0=A0.x; - 102: 29 37 L1=A0.w; - 104: 32 37 L2=A1.x; - 106: 3b 37 L3=A1.w; - 108: 81 34 I0=I1; - 10a: 8c 34 I1=M0; - 10c: d1 34 I2=B1; - 10e: dc 34 I3=L0; - 110: a1 34 M0=I1; - 112: ac 34 M1=M0; - 114: f1 34 M2=B1; - 116: fc 34 M3=L0; - 118: 81 36 B0=I1; - 11a: 8c 36 B1=M0; - 11c: d1 36 B2=B1; - 11e: dc 36 B3=L0; - 120: a1 36 L0=I1; - 122: ac 36 L1=M0; - 124: f1 36 L2=B1; - 126: fc 36 L3=L0; - 128: c8 31 R1=USP; - 12a: d0 33 P2=USP; - 12c: f0 33 SP=USP; - 12e: f8 33 FP=USP; - 130: c0 39 A0.x=USP; - 132: d8 39 A1.w=USP; - 134: 02 3e USP=R2; - 136: 44 3e USP=P4; - 138: 46 3e USP=SP; - 13a: 47 3e USP=FP; - 13c: 00 3f USP=A0.x; - 13e: 03 3f USP=A1.w; - 140: 06 31 R0=ASTAT; - 142: c9 31 R1=SEQSTAT; - 144: d2 31 R2=SYSCFG; - 146: db 31 R3=RETI; - 148: e4 31 R4=RETX; - 14a: ed 31 R5=RETN; - 14c: f6 31 R6=RETE; - 14e: 3f 31 R7=RETS; - 150: 80 31 R0=LC0; - 152: 8b 31 R1=LC1; - 154: 91 31 R2=LT0; - 156: 9c 31 R3=LT1; - 158: a2 31 R4=LB0; - 15a: ad 31 R5=LB1; - 15c: b6 31 R6=CYCLES; - 15e: bf 31 R7=CYCLES2; - 160: 30 38 ASTAT=R0; - 162: 09 3e SEQSTAT=R1; - 164: 13 3e SYSCFG=R3; - 166: 1c 3e RETI=R4; - 168: 25 3e RETX=R5; - 16a: 2e 3e RETN=R6; - 16c: 37 3e RETE=R7; - 16e: 38 38 RETS=R0; - 170: 01 3c LC0=R1; - 172: 1a 3c LC1=R2; - 174: 0b 3c LT0=R3; - 176: 24 3c LT1=R4; - 178: 15 3c LB0=R5; - 17a: 2e 3c LB1=R6; - 17c: 37 3c CYCLES=R7; - 17e: 38 3c CYCLES2=R0; - 180: 70 38 ASTAT=P0; - 182: 49 3e SEQSTAT=P1; - 184: 53 3e SYSCFG=P3; - 186: 5c 3e RETI=P4; - 188: 65 3e RETX=P5; - 18a: 6e 3e RETN=SP; - 18c: 77 3e RETE=FP; - 18e: 78 38 RETS=P0; - 190: 41 3c LC0=P1; - 192: 5a 3c LC1=P2; - 194: 4b 3c LT0=P3; - 196: 64 3c LT1=P4; - 198: 55 3c LB0=P5; - 19a: 6e 3c LB1=SP; - 19c: 76 3c CYCLES=SP; - 19e: 78 3c CYCLES2=P0; - 1a0: 08 c4 [0|3][0|f] c0 A0=A1; - 1a4: 08 c4 [0|3][0|f] e0 A1=A0; - 1a8: 09 c4 00 20 A0=R0; - 1ac: 09 c4 08 20 A0=R1; - 1b0: 09 c4 10 20 A0=R2; - 1b4: 09 c4 00 a0 A1=R0; - 1b8: 09 c4 08 a0 A1=R1; - 1bc: 09 c4 10 a0 A1=R2; + 0: 00 30 R0 = R0; + 2: 09 30 R1 = R1; + 4: 12 30 R2 = R2; + 6: 1b 30 R3 = R3; + 8: 24 30 R4 = R4; + a: 2d 30 R5 = R5; + c: 36 30 R6 = R6; + e: 3f 30 R7 = R7; + 10: 40 32 P0 = P0; + 12: 49 32 P1 = P1; + 14: 52 32 P2 = P2; + 16: 5b 32 P3 = P3; + 18: 64 32 P4 = P4; + 1a: 6d 32 P5 = P5; + 1c: 76 32 SP = SP; + 1e: 7f 32 FP = FP; + 20: 00 39 A0.X = A0.X; + 22: 09 39 A0.W = A0.W; + 24: 12 39 A1.X = A1.X; + 26: 1b 39 A1.W = A1.W; + 28: 03 31 R0 = A1.W; + 2a: 0a 31 R1 = A1.X; + 2c: 11 31 R2 = A0.W; + 2e: 18 31 R3 = A0.X; + 30: 67 30 R4 = FP; + 32: 6e 30 R5 = SP; + 34: 75 30 R6 = P5; + 36: 7c 30 R7 = P4; + 38: 43 32 P0 = P3; + 3a: 4a 32 P1 = P2; + 3c: 51 32 P2 = P1; + 3e: 58 32 P3 = P0; + 40: 27 32 P4 = R7; + 42: 2e 32 P5 = R6; + 44: 35 32 SP = R5; + 46: 3c 32 FP = R4; + 48: 03 38 A0.X = R3; + 4a: 0a 38 A0.W = R2; + 4c: 11 38 A1.X = R1; + 4e: 18 38 A1.W = R0; + 50: 01 39 A0.X = A0.W; + 52: 03 39 A0.X = A1.W; + 54: 02 39 A0.X = A1.X; + 56: 13 39 A1.X = A1.W; + 58: 11 39 A1.X = A0.W; + 5a: 10 39 A1.X = A0.X; + 5c: 09 39 A0.W = A0.W; + 5e: 0b 39 A0.W = A1.W; + 60: 0a 39 A0.W = A1.X; + 62: 1b 39 A1.W = A1.W; + 64: 19 39 A1.W = A0.W; + 66: 18 39 A1.W = A0.X; + 68: 80 30 R0 = I0; + 6a: 89 30 R1 = I1; + 6c: 92 30 R2 = I2; + 6e: 9b 30 R3 = I3; + 70: a4 30 R4 = M0; + 72: ad 30 R5 = M1; + 74: b6 30 R6 = M2; + 76: bf 30 R7 = M3; + 78: c0 30 R0 = B0; + 7a: c9 30 R1 = B1; + 7c: d2 30 R2 = B2; + 7e: db 30 R3 = B3; + 80: e4 30 R4 = L0; + 82: ed 30 R5 = L1; + 84: f6 30 R6 = L2; + 86: ff 30 R7 = L3; + 88: 80 32 P0 = I0; + 8a: 89 32 P1 = I1; + 8c: 92 32 P2 = I2; + 8e: 9b 32 P3 = I3; + 90: a4 32 P4 = M0; + 92: ad 32 P5 = M1; + 94: b6 32 SP = M2; + 96: bf 32 FP = M3; + 98: c0 32 P0 = B0; + 9a: c9 32 P1 = B1; + 9c: d2 32 P2 = B2; + 9e: db 32 P3 = B3; + a0: e4 32 P4 = L0; + a2: ed 32 P5 = L1; + a4: f6 32 SP = L2; + a6: ff 32 FP = L3; + a8: 80 38 A0.X = I0; + aa: 89 38 A0.W = I1; + ac: 92 38 A1.X = I2; + ae: 9b 38 A1.W = I3; + b0: 84 38 A0.X = M0; + b2: 8d 38 A0.W = M1; + b4: 96 38 A1.X = M2; + b6: 9f 38 A1.W = M3; + b8: c0 38 A0.X = B0; + ba: c9 38 A0.W = B1; + bc: d2 38 A1.X = B2; + be: db 38 A1.W = B3; + c0: c4 38 A0.X = L0; + c2: cd 38 A0.W = L1; + c4: d6 38 A1.X = L2; + c6: df 38 A1.W = L3; + c8: 00 34 I0 = R0; + ca: 48 34 I1 = P0; + cc: 56 34 I2 = SP; + ce: 5f 34 I3 = FP; + d0: 00 35 I0 = A0.X; + d2: 09 35 I1 = A0.W; + d4: 12 35 I2 = A1.X; + d6: 1b 35 I3 = A1.W; + d8: 20 34 M0 = R0; + da: 68 34 M1 = P0; + dc: 76 34 M2 = SP; + de: 7f 34 M3 = FP; + e0: 20 35 M0 = A0.X; + e2: 29 35 M1 = A0.W; + e4: 32 35 M2 = A1.X; + e6: 3b 35 M3 = A1.W; + e8: 00 36 B0 = R0; + ea: 48 36 B1 = P0; + ec: 56 36 B2 = SP; + ee: 5f 36 B3 = FP; + f0: 00 37 B0 = A0.X; + f2: 09 37 B1 = A0.W; + f4: 12 37 B2 = A1.X; + f6: 1b 37 B3 = A1.W; + f8: 20 36 L0 = R0; + fa: 68 36 L1 = P0; + fc: 76 36 L2 = SP; + fe: 7f 36 L3 = FP; + 100: 20 37 L0 = A0.X; + 102: 29 37 L1 = A0.W; + 104: 32 37 L2 = A1.X; + 106: 3b 37 L3 = A1.W; + 108: 81 34 I0 = I1; + 10a: 8c 34 I1 = M0; + 10c: d1 34 I2 = B1; + 10e: dc 34 I3 = L0; + 110: a1 34 M0 = I1; + 112: ac 34 M1 = M0; + 114: f1 34 M2 = B1; + 116: fc 34 M3 = L0; + 118: 81 36 B0 = I1; + 11a: 8c 36 B1 = M0; + 11c: d1 36 B2 = B1; + 11e: dc 36 B3 = L0; + 120: a1 36 L0 = I1; + 122: ac 36 L1 = M0; + 124: f1 36 L2 = B1; + 126: fc 36 L3 = L0; + 128: c8 31 R1 = USP; + 12a: d0 33 P2 = USP; + 12c: f0 33 SP = USP; + 12e: f8 33 FP = USP; + 130: c0 39 A0.X = USP; + 132: d8 39 A1.W = USP; + 134: 02 3e USP = R2; + 136: 44 3e USP = P4; + 138: 46 3e USP = SP; + 13a: 47 3e USP = FP; + 13c: 00 3f USP = A0.X; + 13e: 03 3f USP = A1.W; + 140: 06 31 R0 = ASTAT; + 142: c9 31 R1 = SEQSTAT; + 144: d2 31 R2 = SYSCFG; + 146: db 31 R3 = RETI; + 148: e4 31 R4 = RETX; + 14a: ed 31 R5 = RETN; + 14c: f6 31 R6 = RETE; + 14e: 3f 31 R7 = RETS; + 150: 80 31 R0 = LC0; + 152: 8b 31 R1 = LC1; + 154: 91 31 R2 = LT0; + 156: 9c 31 R3 = LT1; + 158: a2 31 R4 = LB0; + 15a: ad 31 R5 = LB1; + 15c: b6 31 R6 = CYCLES; + 15e: bf 31 R7 = CYCLES2; + 160: 30 38 ASTAT = R0; + 162: 09 3e SEQSTAT = R1; + 164: 13 3e SYSCFG = R3; + 166: 1c 3e RETI = R4; + 168: 25 3e RETX = R5; + 16a: 2e 3e RETN = R6; + 16c: 37 3e RETE = R7; + 16e: 38 38 RETS = R0; + 170: 01 3c LC0 = R1; + 172: 1a 3c LC1 = R2; + 174: 0b 3c LT0 = R3; + 176: 24 3c LT1 = R4; + 178: 15 3c LB0 = R5; + 17a: 2e 3c LB1 = R6; + 17c: 37 3c CYCLES = R7; + 17e: 38 3c CYCLES2 = R0; + 180: 70 38 ASTAT = P0; + 182: 49 3e SEQSTAT = P1; + 184: 53 3e SYSCFG = P3; + 186: 5c 3e RETI = P4; + 188: 65 3e RETX = P5; + 18a: 6e 3e RETN = SP; + 18c: 77 3e RETE = FP; + 18e: 78 38 RETS = P0; + 190: 41 3c LC0 = P1; + 192: 5a 3c LC1 = P2; + 194: 4b 3c LT0 = P3; + 196: 64 3c LT1 = P4; + 198: 55 3c LB0 = P5; + 19a: 6e 3c LB1 = SP; + 19c: 76 3c CYCLES = SP; + 19e: 78 3c CYCLES2 = P0; + 1a0: 08 c4 [0|3][0|f] c0 A0 = A1; + 1a4: 08 c4 [0|3][0|f] e0 A1 = A0; + 1a8: 09 c4 00 20 A0 = R0; + 1ac: 09 c4 08 20 A0 = R1; + 1b0: 09 c4 10 20 A0 = R2; + 1b4: 09 c4 00 a0 A1 = R0; + 1b8: 09 c4 08 a0 A1 = R1; + 1bc: 09 c4 10 a0 A1 = R2; 1c0: 0b c0 00 38 R0 = A0; 1c4: 8b c0 80 38 R2 = A0 \(FU\); 1c8: 2b c1 00 39 R4 = A0 \(ISS2\); @@ -248,55 +248,55 @@ Disassembly of section .text: 208: a3 07 IF CC P4 = R3; 20a: af 07 IF CC P5 = R7; 20c: 96 07 IF CC P2 = R6; - 20e: 18 06 IF ! CC R3 = R0; - 210: 10 06 IF ! CC R2 = R0; - 212: 38 06 IF ! CC R7 = R0; - 214: 52 06 IF ! CC R2 = P2; - 216: 61 06 IF ! CC R4 = P1; - 218: 40 06 IF ! CC R0 = P0; - 21a: 7c 06 IF ! CC R7 = P4; - 21c: c2 06 IF ! CC P0 = P2; - 21e: e5 06 IF ! CC P4 = P5; - 220: cb 06 IF ! CC P1 = P3; - 222: ec 06 IF ! CC P5 = P4; - 224: 82 06 IF ! CC P0 = R2; - 226: a3 06 IF ! CC P4 = R3; - 228: af 06 IF ! CC P5 = R7; - 22a: 96 06 IF ! CC P2 = R6; - 22c: c0 42 R0=R0.L\(Z\); - 22e: ca 42 R2=R1.L\(Z\); - 230: d1 42 R1=R2.L\(Z\); - 232: f7 42 R7=R6.L\(Z\); - 234: 80 42 R0=R0.L\(X\); - 236: 8a 42 R2=R1.L\(X\); - 238: 91 42 R1=R2.L\(X\); - 23a: b7 42 R7=R6.L\(X\); - 23c: c0 42 R0=R0.L\(Z\); - 23e: ca 42 R2=R1.L\(Z\); - 240: d1 42 R1=R2.L\(Z\); - 242: f7 42 R7=R6.L\(Z\); - 244: 09 c4 00 40 A0.x=R0.L; - 248: 09 c4 08 40 A0.x=R1.L; - 24c: 09 c4 00 c0 A1.x=R0.L; - 250: 09 c4 08 c0 A1.x=R1.L; - 254: 0a c4 [0|3][0|6] 00 R0.L=A0.x; - 258: 0a c4 [0|3][0|6] 02 R1.L=A0.x; - 25c: 0a c4 [0|3][0|6] 0e R7.L=A0.x; - 260: 0a c4 [0|3][0|6] 40 R0.L=A1.x; - 264: 0a c4 [0|3][0|6] 42 R1.L=A1.x; - 268: 0a c4 [0|3][0|6] 4e R7.L=A1.x; - 26c: 09 c4 00 00 A0.L=R0.L; - 270: 09 c4 08 00 A0.L=R1.L; - 274: 09 c4 30 00 A0.L=R6.L; - 278: 09 c4 00 80 A1.L=R0.L; - 27c: 09 c4 08 80 A1.L=R1.L; - 280: 09 c4 30 80 A1.L=R6.L; - 284: 29 c4 00 00 A0.H=R0.H; - 288: 29 c4 08 00 A0.H=R1.H; - 28c: 29 c4 30 00 A0.H=R6.H; - 290: 29 c4 00 80 A1.H=R0.H; - 294: 29 c4 08 80 A1.H=R1.H; - 298: 29 c4 30 80 A1.H=R6.H; + 20e: 18 06 IF !CC R3 = R0; + 210: 10 06 IF !CC R2 = R0; + 212: 38 06 IF !CC R7 = R0; + 214: 52 06 IF !CC R2 = P2; + 216: 61 06 IF !CC R4 = P1; + 218: 40 06 IF !CC R0 = P0; + 21a: 7c 06 IF !CC R7 = P4; + 21c: c2 06 IF !CC P0 = P2; + 21e: e5 06 IF !CC P4 = P5; + 220: cb 06 IF !CC P1 = P3; + 222: ec 06 IF !CC P5 = P4; + 224: 82 06 IF !CC P0 = R2; + 226: a3 06 IF !CC P4 = R3; + 228: af 06 IF !CC P5 = R7; + 22a: 96 06 IF !CC P2 = R6; + 22c: c0 42 R0 = R0.L \(Z\); + 22e: ca 42 R2 = R1.L \(Z\); + 230: d1 42 R1 = R2.L \(Z\); + 232: f7 42 R7 = R6.L \(Z\); + 234: 80 42 R0 = R0.L \(X\); + 236: 8a 42 R2 = R1.L \(X\); + 238: 91 42 R1 = R2.L \(X\); + 23a: b7 42 R7 = R6.L \(X\); + 23c: c0 42 R0 = R0.L \(Z\); + 23e: ca 42 R2 = R1.L \(Z\); + 240: d1 42 R1 = R2.L \(Z\); + 242: f7 42 R7 = R6.L \(Z\); + 244: 09 c4 00 40 A0.X = R0.L; + 248: 09 c4 08 40 A0.X = R1.L; + 24c: 09 c4 00 c0 A1.X = R0.L; + 250: 09 c4 08 c0 A1.X = R1.L; + 254: 0a c4 [0|3][0|6] 00 R0.L = A0.X; + 258: 0a c4 [0|3][0|6] 02 R1.L = A0.X; + 25c: 0a c4 [0|3][0|6] 0e R7.L = A0.X; + 260: 0a c4 [0|3][0|6] 40 R0.L = A1.X; + 264: 0a c4 [0|3][0|6] 42 R1.L = A1.X; + 268: 0a c4 [0|3][0|6] 4e R7.L = A1.X; + 26c: 09 c4 00 00 A0.L = R0.L; + 270: 09 c4 08 00 A0.L = R1.L; + 274: 09 c4 30 00 A0.L = R6.L; + 278: 09 c4 00 80 A1.L = R0.L; + 27c: 09 c4 08 80 A1.L = R1.L; + 280: 09 c4 30 80 A1.L = R6.L; + 284: 29 c4 00 00 A0.H = R0.H; + 288: 29 c4 08 00 A0.H = R1.H; + 28c: 29 c4 30 00 A0.H = R6.H; + 290: 29 c4 00 80 A1.H = R0.H; + 294: 29 c4 08 80 A1.H = R1.H; + 298: 29 c4 30 80 A1.H = R6.H; 29c: 03 c0 00 38 R0.L = A0; 2a0: 03 c0 40 38 R1.L = A0; 2a4: 83 c0 00 38 R0.L = A0 \(FU\); @@ -361,11 +361,11 @@ Disassembly of section .text: 390: 27 c1 40 38 R1.H = A1, R1.L = A0 \(ISS2\); 394: 67 c1 00 38 R0.H = A1, R0.L = A0 \(IH\); 398: 67 c1 40 38 R1.H = A1, R1.L = A0 \(IH\); - 39c: 48 43 R0=R1.B\(Z\); - 39e: 50 43 R0=R2.B\(Z\); - 3a0: 4f 43 R7=R1.B\(Z\); - 3a2: 57 43 R7=R2.B\(Z\); - 3a4: 08 43 R0=R1.B\(X\); - 3a6: 10 43 R0=R2.B\(X\); - 3a8: 0f 43 R7=R1.B\(X\); - 3aa: 17 43 R7=R2.B\(X\); + 39c: 48 43 R0 = R1.B \(Z\); + 39e: 50 43 R0 = R2.B \(Z\); + 3a0: 4f 43 R7 = R1.B \(Z\); + 3a2: 57 43 R7 = R2.B \(Z\); + 3a4: 08 43 R0 = R1.B \(X\); + 3a6: 10 43 R0 = R2.B \(X\); + 3a8: 0f 43 R7 = R1.B \(X\); + 3aa: 17 43 R7 = R2.B \(X\); diff --git a/gas/testsuite/gas/bfin/parallel.d b/gas/testsuite/gas/bfin/parallel.d index 26aee7b..b5fec71 100644 --- a/gas/testsuite/gas/bfin/parallel.d +++ b/gas/testsuite/gas/bfin/parallel.d @@ -5,222 +5,222 @@ Disassembly of section .text: 00000000 <.text>: - 0: 0a ce 13 8a R5=DEPOSIT\(R3,R2\) \|\| I0\+=2 \|\| NOP; + 0: 0a ce 13 8a R5 = DEPOSIT \(R3, R2\) \|\| I0 \+= 0x2 \|\| NOP; 4: 60 9f 00 00 - 8: 0a ce 37 c0 R0=DEPOSIT\(R7,R6\)\(X\) \|\| I1\+=4 \|\| NOP; + 8: 0a ce 37 c0 R0 = DEPOSIT \(R7, R6\) \(X\) \|\| I1 \+= 0x4 \|\| NOP; c: 69 9f 00 00 - 10: 0a ce 0a 08 R4=EXTRACT\(R2,R1.L\) \(Z\) \|\| I2-=M0 \|\| NOP; + 10: 0a ce 0a 08 R4 = EXTRACT \(R2, R1.L\) \(Z\) \|\| I2 -= M0 \|\| NOP; 14: 72 9e 00 00 - 18: 0a ce 10 04 R2=EXTRACT\(R0,R2.L\) \(Z\) \|\| I3\+=M1 \|\| NOP; + 18: 0a ce 10 04 R2 = EXTRACT \(R0, R2.L\) \(Z\) \|\| I3 \+= M1 \|\| NOP; 1c: 67 9e 00 00 - 20: 0a ce 23 4e R7=EXTRACT\(R3,R4.L\)\(X\) \|\| I3\+=M1\(BREV\) \|\| NOP; + 20: 0a ce 23 4e R7 = EXTRACT \(R3, R4.L\) \(X\) \|\| I3 \+= M1 \(BREV\) \|\| NOP; 24: e7 9e 00 00 - 28: 0a ce 0e 4a R5=EXTRACT\(R6,R1.L\)\(X\) \|\| I0-=2 \|\| NOP; + 28: 0a ce 0e 4a R5 = EXTRACT \(R6, R1.L\) \(X\) \|\| I0 -= 0x2 \|\| NOP; 2c: 64 9f 00 00 - 30: 08 ce 08 00 BITMUX \(R1,R0,A0 \)\(ASR\) \|\| I1-=4 \|\| NOP; + 30: 08 ce 08 00 BITMUX \(R1, R0, A0\) \(ASR\) \|\| I1 -= 0x4 \|\| NOP; 34: 6d 9f 00 00 - 38: 08 ce 13 00 BITMUX \(R2,R3,A0 \)\(ASR\) \|\| I0\+=2 \|\| NOP; + 38: 08 ce 13 00 BITMUX \(R2, R3, A0\) \(ASR\) \|\| I0 \+= 0x2 \|\| NOP; 3c: 60 9f 00 00 - 40: 08 ce 25 40 BITMUX \(R4,R5,A0 \)\(ASL\) \|\| SP=\[P0\] \|\| NOP; + 40: 08 ce 25 40 BITMUX \(R4, R5, A0\) \(ASL\) \|\| SP = \[P0\] \|\| NOP; 44: 46 91 00 00 - 48: 08 ce 3e 40 BITMUX \(R7,R6,A0 \)\(ASL\) \|\| FP=\[P1\+\+\] \|\| NOP; + 48: 08 ce 3e 40 BITMUX \(R7, R6, A0\) \(ASL\) \|\| FP = \[P1\+\+\] \|\| NOP; 4c: 4f 90 00 00 - 50: 06 ce 00 ca R5.L=ONES R0 \|\| P0=\[FP--\] \|\| NOP; + 50: 06 ce 00 ca R5.L = ONES R0 \|\| P0 = \[FP--\] \|\| NOP; 54: f8 90 00 00 - 58: 06 ce 02 ce R7.L=ONES R2 \|\| P1=\[P5\+0x18\] \|\| NOP; + 58: 06 ce 02 ce R7.L = ONES R2 \|\| P1 = \[P5 \+ 0x18\] \|\| NOP; 5c: a9 ad 00 00 - 60: 10 cc 00 00 A0= ABS A0 \|\| P2=\[SP\+0x3c\] \|\| R0=\[I0\]; + 60: 10 cc 00 00 A0 = ABS A0 \|\| P2 = \[SP \+ 0x3c\] \|\| R0 = \[I0\]; 64: f2 af 00 9d - 68: 10 cc 00 40 A0= ABS A1 \|\| P3=\[FP-60\] \|\| R1=\[I1\+\+M0\]; + 68: 10 cc 00 40 A0 = ABS A1 \|\| P3 = \[FP -0x3c\] \|\| R1 = \[I1 \+\+ M0\]; 6c: 1b b9 89 9d - 70: 30 cc 00 00 A1= ABS A0 \|\| P4=\[FP-4\] \|\| R2=\[I1\+\+\]; + 70: 30 cc 00 00 A1 = ABS A0 \|\| P4 = \[FP -0x4\] \|\| R2 = \[I1\+\+\]; 74: fc b9 0a 9c - 78: 30 cc 00 40 A1= ABS A1 \|\| FP=\[SP\] \|\| R3=\[I2--\]; + 78: 30 cc 00 40 A1 = ABS A1 \|\| FP = \[SP\] \|\| R3 = \[I2--\]; 7c: 77 91 93 9c - 80: 10 cc 00 c0 A1= ABS A0,A0= ABS A0 \|\| R4=\[P5\+0x38\] \|\| R0.H=W\[I0\]; + 80: 10 cc 00 c0 A1 = ABS A0, A0 = ABS A0 \|\| R4 = \[P5 \+ 0x38\] \|\| R0.H = W\[I0\]; 84: ac a3 40 9d - 88: 07 cc 10 80 R0= ABS R2 \|\| B\[SP\]=R0 \|\| R1.H=W\[I1\+\+\]; + 88: 07 cc 10 80 R0 = ABS R2 \|\| B\[SP\] = R0 \|\| R1.H = W\[I1\+\+\]; 8c: 30 9b 49 9c - 90: 02 cc 10 a8 R4.L=R2.H\+R0.L \(S\) \|\| B\[FP\]=R0 \|\| R2.H=W\[I2--\]; + 90: 02 cc 10 a8 R4.L = R2.H \+ R0.L \(S\) \|\| B\[FP\] = R0 \|\| R2.H = W\[I2--\]; 94: 38 9b d2 9c - 98: 22 cc 09 aa R5.H=R1.H\+R1.L \(S\) \|\| B\[P0\]=R0 \|\| R3.L=W\[I3\]; + 98: 22 cc 09 aa R5.H = R1.H \+ R1.L \(S\) \|\| B\[P0\] = R0 \|\| R3.L = W\[I3\]; 9c: 00 9b 3b 9d - a0: 02 cc 35 0c R6.L=R6.L\+R5.L \(NS\) \|\| B\[P1\]=R0 \|\| R4.L=W\[I3\+\+\]; + a0: 02 cc 35 0c R6.L = R6.L \+ R5.L \(NS\) \|\| B\[P1\] = R0 \|\| R4.L = W\[I3\+\+\]; a4: 08 9b 3c 9c - a8: 05 cc 01 98 R4.L=R0\+R1\(RND20\) \|\| B\[P2\]=R0 \|\| R5.L=W\[I2--\]; + a8: 05 cc 01 98 R4.L = R0 \+ R1 \(RND20\) \|\| B\[P2\] = R0 \|\| R5.L = W\[I2--\]; ac: 10 9b b5 9c - b0: 25 cc 28 96 R3.H=R5\+R0\(RND20\) \|\| R0=B\[P0\]\(X\) \|\| \[I0\]=R6; + b0: 25 cc 28 96 R3.H = R5 \+ R0 \(RND20\) \|\| R0 = B\[P0\] \(X\) \|\| \[I0\] = R6; b4: 40 99 06 9f - b8: 05 cc 3d d2 R1.L=R7-R5\(RND20\) \|\| R0=B\[P4\] \(Z\) \|\| \[I1\+\+\]=R7; + b8: 05 cc 3d d2 R1.L = R7 - R5 \(RND20\) \|\| R0 = B\[P4\] \(Z\) \|\| \[I1\+\+\] = R7; bc: 20 99 0f 9e - c0: 05 cc 01 04 R2.L=R0\+R1\(RND12\) \|\| R1=B\[SP\]\(X\) \|\| \[I2--\]=R7; + c0: 05 cc 01 04 R2.L = R0 \+ R1 \(RND12\) \|\| R1 = B\[SP\] \(X\) \|\| \[I2--\] = R7; c4: 71 99 97 9e - c8: 25 cc 3e 0e R7.H=R7\+R6\(RND12\) \|\| R1=B\[P0\]\(X\) \|\| \[I3\+\+M1\]=R6; + c8: 25 cc 3e 0e R7.H = R7 \+ R6 \(RND12\) \|\| R1 = B\[P0\] \(X\) \|\| \[I3 \+\+ M1\] = R6; cc: 41 99 be 9f - d0: 05 cc 1a 4a R5.L=R3-R2\(RND12\) \|\| R1=B\[P1\] \(Z\) \|\| W\[I3\]=R5.H; + d0: 05 cc 1a 4a R5.L = R3 - R2 \(RND12\) \|\| R1 = B\[P1\] \(Z\) \|\| W\[I3\] = R5.H; d4: 09 99 5d 9f - d8: 25 cc 0a 44 R2.H=R1-R2\(RND12\) \|\| R1=B\[P2\] \(Z\) \|\| W\[I2\+\+\]=R4.H; + d8: 25 cc 0a 44 R2.H = R1 - R2 \(RND12\) \|\| R1 = B\[P2\] \(Z\) \|\| W\[I2\+\+\] = R4.H; dc: 11 99 54 9e - e0: 07 ce 25 0c R6.L=EXPADJ \(R5,R4.L\) \|\| R1=B\[P3\] \(Z\) \|\| W\[I1--\]=R3.H; + e0: 07 ce 25 0c R6.L = EXPADJ \(R5, R4.L\) \|\| R1 = B\[P3\] \(Z\) \|\| W\[I1--\] = R3.H; e4: 19 99 cb 9e - e8: 07 ce 08 ca R5.L=EXPADJ \(R0.H,R1.L\) \|\| R1=B\[P4\] \(Z\) \|\| W\[I0\]=R2.L; + e8: 07 ce 08 ca R5.L = EXPADJ \(R0.H, R1.L\) \|\| R1 = B\[P4\] \(Z\) \|\| W\[I0\] = R2.L; ec: 21 99 22 9f - f0: 07 ce 2b 48 R4.L=EXPADJ \(R3,R5.L\) \(V\) \|\| R1=B\[P5\] \(Z\) \|\| W\[I0\+\+\]=R1.L; + f0: 07 ce 2b 48 R4.L = EXPADJ \(R3, R5.L\) \(V\) \|\| R1 = B\[P5\] \(Z\) \|\| W\[I0\+\+\] = R1.L; f4: 29 99 21 9e - f8: 07 cc 2a 0c R6=MAX\(R5,R2\) \|\| R2=B\[P0\]\(X\) \|\| W\[I1--\]=R0.L; + f8: 07 cc 2a 0c R6 = MAX \(R5, R2\) \|\| R2 = B\[P0\] \(X\) \|\| W\[I1--\] = R0.L; fc: 42 99 a8 9e - 100: 07 cc 0b 00 R0=MAX\(R1,R3\) \|\| B\[P1\]=R2 \|\| NOP; + 100: 07 cc 0b 00 R0 = MAX \(R1, R3\) \|\| B\[P1\] = R2 \|\| NOP; 104: 0a 9b 00 00 - 108: 07 cc 13 4a R5=MIN\(R2,R3\) \|\| B\[P2\]=R2 \|\| R0=\[I1\+\+\]; + 108: 07 cc 13 4a R5 = MIN \(R2, R3\) \|\| B\[P2\] = R2 \|\| R0 = \[I1\+\+\]; 10c: 12 9b 08 9c - 110: 07 cc 38 48 R4=MIN\(R7,R0\) \|\| B\[P3\]=R2 \|\| R1=\[I1\+\+\]; + 110: 07 cc 38 48 R4 = MIN \(R7, R0\) \|\| B\[P3\] = R2 \|\| R1 = \[I1\+\+\]; 114: 1a 9b 09 9c - 118: 0b cc 00 c0 A0-=A1 \|\| B\[P4\]=R2 \|\| R2=\[I1\+\+\]; + 118: 0b cc 00 c0 A0 -= A1 \|\| B\[P4\] = R2 \|\| R2 = \[I1\+\+\]; 11c: 22 9b 0a 9c - 120: 0b cc 00 e0 A0-=A1\(W32\) \|\| B\[P5\]=R2 \|\| R3=\[I1\+\+\]; + 120: 0b cc 00 e0 A0 -= A1 \(W32\) \|\| B\[P5\] = R2 \|\| R3 = \[I1\+\+\]; 124: 2a 9b 0b 9c - 128: 0b cc 00 80 A0\+=A1 \|\| B\[SP\]=R2 \|\| R4=\[I1\+\+\]; + 128: 0b cc 00 80 A0 \+= A1 \|\| B\[SP\] = R2 \|\| R4 = \[I1\+\+\]; 12c: 32 9b 0c 9c - 130: 0b cc 00 a0 A0\+=A1\(W32\) \|\| B\[FP\]=R2 \|\| R5=\[I1\+\+\]; + 130: 0b cc 00 a0 A0 \+= A1 \(W32\) \|\| B\[FP\] = R2 \|\| R5 = \[I1\+\+\]; 134: 3a 9b 0d 9c - 138: 0b cc 00 0e R7=\(A0\+=A1\) \|\| B\[SP\]=R3 \|\| R6=\[I1\+\+\]; + 138: 0b cc 00 0e R7 = \(A0 \+= A1\) \|\| B\[SP\] = R3 \|\| R6 = \[I1\+\+\]; 13c: 33 9b 0e 9c - 140: 0b cc 00 4c R6.L=\(A0\+=A1\) \|\| B\[FP\]=R3 \|\| R7=\[I1\+\+\]; + 140: 0b cc 00 4c R6.L = \(A0 \+= A1\) \|\| B\[FP\] = R3 \|\| R7 = \[I1\+\+\]; 144: 3b 9b 0f 9c - 148: 2b cc 00 40 R0.H=\(A0\+=A1\) \|\| B\[P0\]=R3 \|\| R7=\[I0\+\+\]; + 148: 2b cc 00 40 R0.H = \(A0 \+= A1\) \|\| B\[P0\] = R3 \|\| R7 = \[I0\+\+\]; 14c: 03 9b 07 9c - 150: 00 ca 0a 24 R0 = R1.H \* R2.L \|\| B\[P1\]=R3 \|\| R1=\[I0\+\+\]; + 150: 00 ca 0a 24 R0 = R1.H \* R2.L \|\| B\[P1\] = R3 \|\| R1 = \[I0\+\+\]; 154: 0b 9b 01 9c - 158: 20 ca 68 26 R1 = R5.H \* R0.H \(S2RND\) \|\| B\[P2\]=R3 \|\| R2=\[I0\+\+\]; + 158: 20 ca 68 26 R1 = R5.H \* R0.H \(S2RND\) \|\| B\[P2\] = R3 \|\| R2 = \[I0\+\+\]; 15c: 13 9b 02 9c - 160: 80 ca db 23 R7 = R3.L \* R3.H \(FU\) \|\| B\[P3\]=R3 \|\| R3=\[I0\+\+\]; + 160: 80 ca db 23 R7 = R3.L \* R3.H \(FU\) \|\| B\[P3\] = R3 \|\| R3 = \[I0\+\+\]; 164: 1b 9b 03 9c - 168: 28 cb 15 27 R4 = R2.H \* R5.H \(ISS2\) \|\| B\[P4\]=R3 \|\| R0=\[I0\+\+\]; + 168: 28 cb 15 27 R4 = R2.H \* R5.H \(ISS2\) \|\| B\[P4\] = R3 \|\| R0 = \[I0\+\+\]; 16c: 23 9b 00 9c - 170: 08 cb 0b 20 R0 = R1.L \* R3.L \(IS\) \|\| B\[P5\]=R3 \|\| R5=\[I0\+\+\]; + 170: 08 cb 0b 20 R0 = R1.L \* R3.L \(IS\) \|\| B\[P5\] = R3 \|\| R5 = \[I0\+\+\]; 174: 2b 9b 05 9c - 178: 08 ca a8 25 R6 = R5.H \* R0.L \|\| B\[FP\]=R4 \|\| R7=\[I0\+\+\]; + 178: 08 ca a8 25 R6 = R5.H \* R0.L \|\| B\[FP\] = R4 \|\| R7 = \[I0\+\+\]; 17c: 3c 9b 07 9c - 180: 94 cb be 40 R2.H = R7.L \* R6.H \(M, IU\) \|\| B\[SP\]=R4 \|\| R6=\[I0\+\+\]; + 180: 94 cb be 40 R2.H = R7.L \* R6.H \(M, IU\) \|\| B\[SP\] = R4 \|\| R6 = \[I0\+\+\]; 184: 34 9b 06 9c - 188: 04 ca e8 80 R3.H = R5.H \* R0.L \|\| R4=B\[P0\]\(X\) \|\| \[I0\+\+M0\]=R0; + 188: 04 ca e8 80 R3.H = R5.H \* R0.L \|\| R4 = B\[P0\] \(X\) \|\| \[I0 \+\+ M0\] = R0; 18c: 44 99 80 9f - 190: 14 ca 09 40 R0.H = R1.L \* R1.H \(M\) \|\| R4=B\[P1\]\(X\) \|\| \[I0\+\+M0\]=R1; + 190: 14 ca 09 40 R0.H = R1.L \* R1.H \(M\) \|\| R4 = B\[P1\] \(X\) \|\| \[I0 \+\+ M0\] = R1; 194: 4c 99 81 9f - 198: 1c cb 3e 80 R1 = R7.H \* R6.L \(M, IS\) \|\| R4=B\[P2\]\(X\) \|\| \[I0\+\+M0\]=R2; + 198: 1c cb 3e 80 R1 = R7.H \* R6.L \(M, IS\) \|\| R4 = B\[P2\] \(X\) \|\| \[I0 \+\+ M0\] = R2; 19c: 54 99 82 9f - 1a0: 0c ca 02 41 R5 = R0.L \* R2.H \|\| R4=B\[P3\]\(X\) \|\| \[I0\+\+M0\]=R3; + 1a0: 0c ca 02 41 R5 = R0.L \* R2.H \|\| R4 = B\[P3\] \(X\) \|\| \[I0 \+\+ M0\] = R3; 1a4: 5c 99 83 9f - 1a8: 1c ca b0 c0 R3 = R6.H \* R0.H \(M\) \|\| R4=B\[P4\] \(Z\) \|\| \[I0\+\+M0\]=R4; + 1a8: 1c ca b0 c0 R3 = R6.H \* R0.H \(M\) \|\| R4 = B\[P4\] \(Z\) \|\| \[I0 \+\+ M0\] = R4; 1ac: 24 99 84 9f - 1b0: 63 c8 2f 02 a0 = R5.L \* R7.H \(W32\) \|\| R4=B\[P5\] \(Z\) \|\| \[I0\+\+M0\]=R5; + 1b0: 63 c8 2f 02 A0 = R5.L \* R7.H \(W32\) \|\| R4 = B\[P5\] \(Z\) \|\| \[I0 \+\+ M0\] = R5; 1b4: 2c 99 85 9f - 1b8: 03 c8 00 04 a0 = R0.H \* R0.L \|\| R5=B\[P0\]\(X\) \|\| \[I0\+\+M0\]=R6; + 1b8: 03 c8 00 04 A0 = R0.H \* R0.L \|\| R5 = B\[P0\] \(X\) \|\| \[I0 \+\+ M0\] = R6; 1bc: 45 99 86 9f - 1c0: 83 c8 13 0a a0 \+= R2.L \* R3.H \(FU\) \|\| R5=B\[P1\] \(Z\) \|\| \[I0\+\+M0\]=R7; + 1c0: 83 c8 13 0a A0 \+= R2.L \* R3.H \(FU\) \|\| R5 = B\[P1\] \(Z\) \|\| \[I0 \+\+ M0\] = R7; 1c4: 0d 99 87 9f - 1c8: 03 c8 21 0c a0 \+= R4.H \* R1.L \|\| R5=B\[P2\] \(Z\) \|\| \[I1\+\+M1\]=R7; + 1c8: 03 c8 21 0c A0 \+= R4.H \* R1.L \|\| R5 = B\[P2\] \(Z\) \|\| \[I1 \+\+ M1\] = R7; 1cc: 15 99 af 9f - 1d0: 03 c9 3e 12 a0 -= R7.L \* R6.H \(IS\) \|\| R5=B\[P3\]\(X\) \|\| \[I1\+\+M1\]=R6; + 1d0: 03 c9 3e 12 A0 -= R7.L \* R6.H \(IS\) \|\| R5 = B\[P3\] \(X\) \|\| \[I1 \+\+ M1\] = R6; 1d4: 5d 99 ae 9f - 1d8: 03 c8 2a 16 a0 -= R5.H \* R2.H \|\| R5=B\[P4\] \(Z\) \|\| \[I1\+\+M1\]=R5; + 1d8: 03 c8 2a 16 A0 -= R5.H \* R2.H \|\| R5 = B\[P4\] \(Z\) \|\| \[I1 \+\+ M1\] = R5; 1dc: 25 99 ad 9f - 1e0: 10 c8 08 58 a1 = R1.L \* R0.H \(M\) \|\| R5=B\[P5\]\(X\) \|\| \[I1\+\+M1\]=R4; + 1e0: 10 c8 08 58 A1 = R1.L \* R0.H \(M\) \|\| R5 = B\[P5\] \(X\) \|\| \[I1 \+\+ M1\] = R4; 1e4: 6d 99 ac 9f - 1e8: 00 c8 10 98 a1 = R2.H \* R0.L \|\| R5=B\[SP\] \(Z\) \|\| \[I1\+\+M1\]=R3; + 1e8: 00 c8 10 98 A1 = R2.H \* R0.L \|\| R5 = B\[SP\] \(Z\) \|\| \[I1 \+\+ M1\] = R3; 1ec: 35 99 ab 9f - 1f0: 70 c8 3e 98 a1 = R7.H \* R6.L \(M, W32\) \|\| R5=B\[FP\]\(X\) \|\| \[I1\+\+M1\]=R2; + 1f0: 70 c8 3e 98 A1 = R7.H \* R6.L \(M, W32\) \|\| R5 = B\[FP\] \(X\) \|\| \[I1 \+\+ M1\] = R2; 1f4: 7d 99 aa 9f - 1f8: 81 c8 1a 18 a1 \+= R3.L \* R2.L \(FU\) \|\| R0.L=W\[I0\] \|\| \[I1\+\+M1\]=R1; + 1f8: 81 c8 1a 18 A1 \+= R3.L \* R2.L \(FU\) \|\| R0.L = W\[I0\] \|\| \[I1 \+\+ M1\] = R1; 1fc: 20 9d a9 9f - 200: 01 c8 31 98 a1 \+= R6.H \* R1.L \|\| R1.L=W\[I0\] \|\| \[I1\+\+M1\]=R0; + 200: 01 c8 31 98 A1 \+= R6.H \* R1.L \|\| R1.L = W\[I0\] \|\| \[I1 \+\+ M1\] = R0; 204: 21 9d a8 9f - 208: 02 c9 03 58 a1 -= R0.L \* R3.H \(IS\) \|\| R2.L=W\[I0\] \|\| \[I2\+\+M2\]=R0; + 208: 02 c9 03 58 A1 -= R0.L \* R3.H \(IS\) \|\| R2.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R0; 20c: 22 9d d0 9f - 210: 02 c8 17 58 a1 -= R2.L \* R7.H \|\| R3.L=W\[I0\] \|\| \[I2\+\+M2\]=R1; + 210: 02 c8 17 58 A1 -= R2.L \* R7.H \|\| R3.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R1; 214: 23 9d d1 9f - 218: 03 c8 f5 25 R7.L = \(a0 = R6.H \* R5.L\) \|\| R4.L=W\[I0\] \|\| \[I2\+\+M2\]=R2; + 218: 03 c8 f5 25 R7.L = \(A0 = R6.H \* R5.L\) \|\| R4.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R2; 21c: 24 9d d2 9f - 220: c3 c8 0a 24 R0.L = \(a0 = R1.H \* R2.L\) \(TFU\) \|\| R5.L=W\[I0\] \|\| \[I2\+\+M2\]=R3; + 220: c3 c8 0a 24 R0.L = \(A0 = R1.H \* R2.L\) \(TFU\) \|\| R5.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R3; 224: 25 9d d3 9f - 228: 03 c8 ac 28 R2.L = \(a0 \+= R5.L \* R4.L\) \|\| R6.L=W\[I0\] \|\| \[I2\+\+M2\]=R4; + 228: 03 c8 ac 28 R2.L = \(A0 \+= R5.L \* R4.L\) \|\| R6.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R4; 22c: 26 9d d4 9f - 230: 43 c8 fe 2e R3.L = \(a0 \+= R7.H \* R6.H\) \(T\) \|\| R7.L=W\[I0\] \|\| \[I2\+\+M2\]=R5; + 230: 43 c8 fe 2e R3.L = \(A0 \+= R7.H \* R6.H\) \(T\) \|\| R7.L = W\[I0\] \|\| \[I2 \+\+ M2\] = R5; 234: 27 9d d5 9f - 238: 03 c8 1a 36 R0.L = \(a0 -= R3.H \* R2.H\) \|\| R7.L=W\[I1\+\+\] \|\| \[I2\+\+M2\]=R6; + 238: 03 c8 1a 36 R0.L = \(A0 -= R3.H \* R2.H\) \|\| R7.L = W\[I1\+\+\] \|\| \[I2 \+\+ M2\] = R6; 23c: 2f 9c d6 9f - 240: 63 c9 6c 30 R1.L = \(a0 -= R5.L \* R4.L\) \(IH\) \|\| R6.L=W\[I1\+\+\] \|\| \[I2\+\+M2\]=R7; + 240: 63 c9 6c 30 R1.L = \(A0 -= R5.L \* R4.L\) \(IH\) \|\| R6.L = W\[I1\+\+\] \|\| \[I2 \+\+ M2\] = R7; 244: 2e 9c d7 9f - 248: 04 c8 48 58 R1.H = \(a1 = R1.L \* R0.H\) \|\| R2.L=W\[I1\+\+\] \|\| \[I3\+\+M3\]=R7; + 248: 04 c8 48 58 R1.H = \(A1 = R1.L \* R0.H\) \|\| R2.L = W\[I1\+\+\] \|\| \[I3 \+\+ M3\] = R7; 24c: 2a 9c ff 9f - 250: 34 c9 83 98 R2.H = \(a1 = R0.H \* R3.L\) \(M, ISS2\) \|\| R3.L=W\[I1\+\+\] \|\| \[I3\+\+M3\]=R6; + 250: 34 c9 83 98 R2.H = \(A1 = R0.H \* R3.L\) \(M, ISS2\) \|\| R3.L = W\[I1\+\+\] \|\| \[I3 \+\+ M3\] = R6; 254: 2b 9c fe 9f - 258: 05 c8 bf 59 R6.H = \(a1 \+= R7.L \* R7.H\) \|\| R4.L=W\[I1\+\+\] \|\| \[I3\+\+M3\]=R5; + 258: 05 c8 bf 59 R6.H = \(A1 \+= R7.L \* R7.H\) \|\| R4.L = W\[I1\+\+\] \|\| \[I3 \+\+ M3\] = R5; 25c: 2c 9c fd 9f - 260: 25 c8 d3 19 R7.H = \(a1 \+= R2.L \* R3.L\) \(S2RND\) \|\| R5.L=W\[I1\+\+\] \|\| \[I3\+\+M3\]=R4; + 260: 25 c8 d3 19 R7.H = \(A1 \+= R2.L \* R3.L\) \(S2RND\) \|\| R5.L = W\[I1\+\+\] \|\| \[I3 \+\+ M3\] = R4; 264: 2d 9c fc 9f - 268: 06 c8 a2 d9 R6.H = \(a1 -= R4.H \* R2.H\) \|\| R6.L=W\[I1\+\+\] \|\| \[I3\+\+M3\]=R3; + 268: 06 c8 a2 d9 R6.H = \(A1 -= R4.H \* R2.H\) \|\| R6.L = W\[I1\+\+\] \|\| \[I3 \+\+ M3\] = R3; 26c: 2e 9c fb 9f - 270: d6 c8 5f 99 R5.H = \(a1 -= R3.H \* R7.L\) \(M, TFU\) \|\| R7.L=W\[I1\+\+\] \|\| \[I3\+\+M3\]=R2; + 270: d6 c8 5f 99 R5.H = \(A1 -= R3.H \* R7.L\) \(M, TFU\) \|\| R7.L = W\[I1\+\+\] \|\| \[I3 \+\+ M3\] = R2; 274: 2f 9c fa 9f - 278: 0b c8 0a 20 R0 = \(a0 = R1.L \* R2.L\) \|\| R1.L=W\[I2--\] \|\| \[I3\+\+M3\]=R1; + 278: 0b c8 0a 20 R0 = \(A0 = R1.L \* R2.L\) \|\| R1.L = W\[I2--\] \|\| \[I3 \+\+ M3\] = R1; 27c: b1 9c f9 9f - 280: 0b c9 8a 20 R2 = \(a0 = R1.L \* R2.L\) \(IS\) \|\| R1.L=W\[I2--\] \|\| \[I3\+\+M3\]=R0; + 280: 0b c9 8a 20 R2 = \(A0 = R1.L \* R2.L\) \(IS\) \|\| R1.L = W\[I2--\] \|\| \[I3 \+\+ M3\] = R0; 284: b1 9c f8 9f - 288: 0b c8 3e 2d R4 = \(a0 \+= R7.H \* R6.L\) \|\| R2.L=W\[I2--\] \|\| R0.H=W\[I0\]; + 288: 0b c8 3e 2d R4 = \(A0 \+= R7.H \* R6.L\) \|\| R2.L = W\[I2--\] \|\| R0.H = W\[I0\]; 28c: b2 9c 40 9d - 290: 2b c8 ab 2b R6 = \(a0 \+= R5.L \* R3.H\) \(S2RND\) \|\| R3.L=W\[I2--\] \|\| R1.H=W\[I1\]; + 290: 2b c8 ab 2b R6 = \(A0 \+= R5.L \* R3.H\) \(S2RND\) \|\| R3.L = W\[I2--\] \|\| R1.H = W\[I1\]; 294: b3 9c 49 9d - 298: 0b c8 97 35 R6 = \(a0 -= R2.H \* R7.L\) \|\| R4.L=W\[I2--\] \|\| R2.H=W\[I2\]; + 298: 0b c8 97 35 R6 = \(A0 -= R2.H \* R7.L\) \|\| R4.L = W\[I2--\] \|\| R2.H = W\[I2\]; 29c: b4 9c 52 9d - 2a0: 8b c8 06 33 R4 = \(a0 -= R0.L \* R6.H\) \(FU\) \|\| R5.L=W\[I2--\] \|\| R3.H=W\[I3\]; + 2a0: 8b c8 06 33 R4 = \(A0 -= R0.L \* R6.H\) \(FU\) \|\| R5.L = W\[I2--\] \|\| R3.H = W\[I3\]; 2a4: b5 9c 5b 9d - 2a8: 0c c8 81 99 R7 = \(a1 = R0.H \* R1.L\) \|\| R6.L=W\[I2--\] \|\| R4.H=W\[I3\]; + 2a8: 0c c8 81 99 R7 = \(A1 = R0.H \* R1.L\) \|\| R6.L = W\[I2--\] \|\| R4.H = W\[I3\]; 2ac: b6 9c 5c 9d - 2b0: 9c c8 13 d9 R5 = \(a1 = R2.H \* R3.H\) \(M, FU\) \|\| R7.L=W\[I2--\] \|\| R4.H=W\[I2\]; + 2b0: 9c c8 13 d9 R5 = \(A1 = R2.H \* R3.H\) \(M, FU\) \|\| R7.L = W\[I2--\] \|\| R4.H = W\[I2\]; 2b4: b7 9c 54 9d - 2b8: 0d c8 bd 18 R3 = \(a1 \+= R7.L \* R5.L\) \|\| W\[P0\]=R0.L \|\| R6.H=W\[I1\]; + 2b8: 0d c8 bd 18 R3 = \(A1 \+= R7.L \* R5.L\) \|\| W\[P0\] = R0.L \|\| R6.H = W\[I1\]; 2bc: 00 8a 4e 9d - 2c0: 2d c9 17 d8 R1 = \(a1 \+= R2.H \* R7.H\) \(ISS2\) \|\| W\[P0\]=R1.L \|\| R7.H=W\[I0\]; + 2c0: 2d c9 17 d8 R1 = \(A1 \+= R2.H \* R7.H\) \(ISS2\) \|\| W\[P0\] = R1.L \|\| R7.H = W\[I0\]; 2c4: 40 8a 47 9d - 2c8: 0e c8 80 58 R3 = \(a1 -= R0.L \* R0.H\) \|\| W\[P0\]=R2.L \|\| R7.L=W\[I0\+\+\]; + 2c8: 0e c8 80 58 R3 = \(A1 -= R0.L \* R0.H\) \|\| W\[P0\] = R2.L \|\| R7.L = W\[I0\+\+\]; 2cc: 80 8a 27 9c - 2d0: 1e c9 17 59 R5 = \(a1 -= R2.L \* R7.H\) \(M, IS\) \|\| W\[P0\]=R3.L \|\| R6.L=W\[I1\+\+\]; + 2d0: 1e c9 17 59 R5 = \(A1 -= R2.L \* R7.H\) \(M, IS\) \|\| W\[P0\] = R3.L \|\| R6.L = W\[I1\+\+\]; 2d4: c0 8a 2e 9c - 2d8: 07 cc 10 ee R7=-R2\(S\) \|\| W\[P0\]=R4.L \|\| R5.L=W\[I2\+\+\]; + 2d8: 07 cc 10 ee R7 = -R2 \(S\) \|\| W\[P0\] = R4.L \|\| R5.L = W\[I2\+\+\]; 2dc: 00 8b 35 9c - 2e0: 0e cc 00 00 A0=-A0 \|\| W\[P0\]=R5.L \|\| R4.L=W\[I3\+\+\]; + 2e0: 0e cc 00 00 A0 = -A0 \|\| W\[P0\] = R5.L \|\| R4.L = W\[I3\+\+\]; 2e4: 40 8b 3c 9c - 2e8: 0e cc 00 40 A0=-A1 \|\| W\[P0\]=R6.L \|\| R3.L=W\[I3--\]; + 2e8: 0e cc 00 40 A0 = -A1 \|\| W\[P0\] = R6.L \|\| R3.L = W\[I3--\]; 2ec: 80 8b bb 9c - 2f0: 2e cc 00 00 A1=-A0 \|\| W\[P0\]=R7.L \|\| R2.L=W\[I1\+\+\]; + 2f0: 2e cc 00 00 A1 = -A0 \|\| W\[P0\] = R7.L \|\| R2.L = W\[I1\+\+\]; 2f4: c0 8b 2a 9c - 2f8: 2e cc 00 40 A1=-A1 \|\| W\[P1\]=R0 \|\| R1.L=W\[I2--\]; + 2f8: 2e cc 00 40 A1 = -A1 \|\| W\[P1\] = R0 \|\| R1.L = W\[I2--\]; 2fc: 08 97 b1 9c - 300: 0e cc 00 c0 A1=-A1,A0=-A0 \|\| W\[P1\]=R1 \|\| R0.L=W\[I1--\]; + 300: 0e cc 00 c0 A1 = -A1, A0 = -A0 \|\| W\[P1\] = R1 \|\| R0.L = W\[I1--\]; 304: 09 97 a8 9c - 308: 0c cc 18 ca R5.L=R3\(RND\) \|\| W\[P1\]=R2 \|\| R0=\[I0\+\+M3\]; + 308: 0c cc 18 ca R5.L = R3 \(RND\) \|\| W\[P1\] = R2 \|\| R0 = \[I0 \+\+ M3\]; 30c: 0a 97 e0 9d - 310: 2c cc 00 cc R6.H=R0\(RND\) \|\| W\[P1\]=R3 \|\| R1=\[I1\+\+M2\]; + 310: 2c cc 00 cc R6.H = R0 \(RND\) \|\| W\[P1\] = R3 \|\| R1 = \[I1 \+\+ M2\]; 314: 0b 97 c9 9d - 318: 08 cc 00 20 A0=A0\(S\) \|\| W\[P1\]=R4 \|\| R2=\[I2\+\+M1\]; + 318: 08 cc 00 20 A0 = A0 \(S\) \|\| W\[P1\] = R4 \|\| R2 = \[I2 \+\+ M1\]; 31c: 0c 97 b2 9d - 320: 08 cc 00 60 A1=A1\(S\) \|\| W\[P1\]=R5 \|\| R3=\[I3\+\+M0\]; + 320: 08 cc 00 60 A1 = A1 \(S\) \|\| W\[P1\] = R5 \|\| R3 = \[I3 \+\+ M0\]; 324: 0d 97 9b 9d - 328: 08 cc 00 a0 A1=A1\(S\),A0=A0\(S\) \|\| R6=W\[P1\] \(Z\) \|\| \[I0\]=R0; + 328: 08 cc 00 a0 A1 = A1 \(S\), A0 = A0 \(S\) \|\| R6 = W\[P1\] \(Z\) \|\| \[I0\] = R0; 32c: 0e 95 00 9f - 330: 05 ce 00 0a R5.L=SIGNBITS R0 \|\| R7=W\[P1\] \(Z\) \|\| \[I1\]=R0; + 330: 05 ce 00 0a R5.L = SIGNBITS R0 \|\| R7 = W\[P1\] \(Z\) \|\| \[I1\] = R0; 334: 0f 95 08 9f - 338: 05 ce 07 80 R0.L=SIGNBITS R7.H \|\| R1=W\[P2\+\+\]\(X\) \|\| \[I2\]=R0; + 338: 05 ce 07 80 R0.L = SIGNBITS R7.H \|\| R1 = W\[P2\+\+\] \(X\) \|\| \[I2\] = R0; 33c: 51 94 10 9f - 340: 06 ce 00 06 R3.L=SIGNBITS A0 \|\| R2=W\[P2\+\+\]\(X\) \|\| \[I3\]=R0; + 340: 06 ce 00 06 R3.L = SIGNBITS A0 \|\| R2 = W\[P2\+\+\] \(X\) \|\| \[I3\] = R0; 344: 52 94 18 9f - 348: 06 ce 00 4e R7.L=SIGNBITS A1 \|\| R3=W\[P2\+\+\] \(Z\) \|\| \[I0\]=R1; + 348: 06 ce 00 4e R7.L = SIGNBITS A1 \|\| R3 = W\[P2\+\+\] \(Z\) \|\| \[I0\] = R1; 34c: 13 94 01 9f - 350: 03 cc 37 ea R5.L=R6.H-R7.H \(S\) \|\| R4=W\[P2\+\+\]\(X\) \|\| \[I1\]=R1; + 350: 03 cc 37 ea R5.L = R6.H - R7.H \(S\) \|\| R4 = W\[P2\+\+\] \(X\) \|\| \[I1\] = R1; 354: 54 94 09 9f - 358: 23 cc 1b 40 R0.H=R3.L-R3.H \(NS\) \|\| R5=W\[P2\+\+\]\(X\) \|\| \[I2\]=R2; + 358: 23 cc 1b 40 R0.H = R3.L - R3.H \(NS\) \|\| R5 = W\[P2\+\+\] \(X\) \|\| \[I2\] = R2; 35c: 55 94 12 9f - 360: 07 cc 10 84 R2= ABS R2 || R1=\[I0\+\+\] || NOP; + 360: 07 cc 10 84 R2 = ABS R2 \|\| R1 = \[I0\+\+\] \|\| NOP; 364: 01 9c 00 00 diff --git a/gas/testsuite/gas/bfin/parallel2.d b/gas/testsuite/gas/bfin/parallel2.d index cd50801..ce21097 100644 --- a/gas/testsuite/gas/bfin/parallel2.d +++ b/gas/testsuite/gas/bfin/parallel2.d @@ -5,143 +5,143 @@ Disassembly of section .text: 00000000 <.text>: - 0: 08 cc 00 c0 A0=A1 \|\| P0=\[SP\+0x14\] \|\| NOP; + 0: 08 cc 00 c0 A0 = A1 \|\| P0 = \[SP \+ 0x14\] \|\| NOP; 4: 70 ad 00 00 - 8: 08 cc 00 e0 A1=A0 \|\| P0=\[P5\+0x18\] \|\| NOP; + 8: 08 cc 00 e0 A1 = A0 \|\| P0 = \[P5 \+ 0x18\] \|\| NOP; c: a8 ad 00 00 - 10: 09 cc 00 20 A0=R0 \|\| P0=\[P4\+0x1c\] \|\| NOP; + 10: 09 cc 00 20 A0 = R0 \|\| P0 = \[P4 \+ 0x1c\] \|\| NOP; 14: e0 ad 00 00 - 18: 09 cc 08 a0 A1=R1 \|\| P0=\[P3\+0x20\] \|\| NOP; + 18: 09 cc 08 a0 A1 = R1 \|\| P0 = \[P3 \+ 0x20\] \|\| NOP; 1c: 18 ae 00 00 - 20: 8b c8 00 39 R4 = A0 \(FU\) \|\| P0=\[P3\+0x24\] \|\| NOP; + 20: 8b c8 00 39 R4 = A0 \(FU\) \|\| P0 = \[P3 \+ 0x24\] \|\| NOP; 24: 58 ae 00 00 - 28: 2f c9 00 19 R5 = A1 \(ISS2\) \|\| P0=\[P3\+0x28\] \|\| NOP; + 28: 2f c9 00 19 R5 = A1 \(ISS2\) \|\| P0 = \[P3 \+ 0x28\] \|\| NOP; 2c: 98 ae 00 00 - 30: 0b c8 80 39 R6 = A0 \|\| P0=\[P4\+0x2c\] \|\| NOP; + 30: 0b c8 80 39 R6 = A0 \|\| P0 = \[P4 \+ 0x2c\] \|\| NOP; 34: e0 ae 00 00 - 38: 0f c8 80 19 R7 = A1 \|\| P0=\[P4\+0x30\] \|\| NOP; + 38: 0f c8 80 19 R7 = A1 \|\| P0 = \[P4 \+ 0x30\] \|\| NOP; 3c: 20 af 00 00 - 40: 0f c8 80 39 R7 = A1, R6 = A0 \|\| P0=\[P4\+0x34\] \|\| NOP; + 40: 0f c8 80 39 R7 = A1, R6 = A0 \|\| P0 = \[P4 \+ 0x34\] \|\| NOP; 44: 60 af 00 00 - 48: 8f c8 00 38 R1 = A1, R0 = A0 \(FU\) \|\| P0=\[P4\+0x38\] \|\| NOP; + 48: 8f c8 00 38 R1 = A1, R0 = A0 \(FU\) \|\| P0 = \[P4 \+ 0x38\] \|\| NOP; 4c: a0 af 00 00 - 50: 09 cc 28 40 A0.x=R5.L \|\| P0=\[P4\+0x3c\] \|\| NOP; + 50: 09 cc 28 40 A0.X = R5.L \|\| P0 = \[P4 \+ 0x3c\] \|\| NOP; 54: e0 af 00 00 - 58: 09 cc 10 c0 A1.x=R2.L \|\| R0=\[I0\+\+M0\] \|\| NOP; + 58: 09 cc 10 c0 A1.X = R2.L \|\| R0 = \[I0 \+\+ M0\] \|\| NOP; 5c: 80 9d 00 00 - 60: 0a cc 00 00 R0.L=A0.x \|\| R1=\[I0\+\+M1\] \|\| NOP; + 60: 0a cc 00 00 R0.L = A0.X \|\| R1 = \[I0 \+\+ M1\] \|\| NOP; 64: a1 9d 00 00 - 68: 0a cc 00 4e R7.L=A1.x \|\| R0=\[I0\+\+M2\] \|\| NOP; + 68: 0a cc 00 4e R7.L = A1.X \|\| R0 = \[I0 \+\+ M2\] \|\| NOP; 6c: c0 9d 00 00 - 70: 09 cc 18 00 A0.L=R3.L \|\| R0=\[I0\+\+M3\] \|\| NOP; + 70: 09 cc 18 00 A0.L = R3.L \|\| R0 = \[I0 \+\+ M3\] \|\| NOP; 74: e0 9d 00 00 - 78: 09 cc 20 80 A1.L=R4.L \|\| R0=\[I1\+\+M3\] \|\| NOP; + 78: 09 cc 20 80 A1.L = R4.L \|\| R0 = \[I1 \+\+ M3\] \|\| NOP; 7c: e8 9d 00 00 - 80: 29 cc 30 00 A0.H=R6.H \|\| R0=\[I1\+\+M2\] \|\| NOP; + 80: 29 cc 30 00 A0.H = R6.H \|\| R0 = \[I1 \+\+ M2\] \|\| NOP; 84: c8 9d 00 00 - 88: 29 cc 28 80 A1.H=R5.H \|\| R0=\[I1\+\+M1\] \|\| NOP; + 88: 29 cc 28 80 A1.H = R5.H \|\| R0 = \[I1 \+\+ M1\] \|\| NOP; 8c: a8 9d 00 00 - 90: 83 c9 00 38 R0.L = A0 \(IU\) \|\| R4=\[I1\+\+M0\] \|\| NOP; + 90: 83 c9 00 38 R0.L = A0 \(IU\) \|\| R4 = \[I1 \+\+ M0\] \|\| NOP; 94: 8c 9d 00 00 - 98: 27 c8 40 18 R1.H = A1 \(S2RND\) \|\| R0=\[I2\+\+M0\] \|\| NOP; + 98: 27 c8 40 18 R1.H = A1 \(S2RND\) \|\| R0 = \[I2 \+\+ M0\] \|\| NOP; 9c: 90 9d 00 00 - a0: 07 c8 40 18 R1.H = A1 \|\| R0=\[I2\+\+M1\] \|\| NOP; + a0: 07 c8 40 18 R1.H = A1 \|\| R0 = \[I2 \+\+ M1\] \|\| NOP; a4: b0 9d 00 00 - a8: 67 c9 80 38 R2.H = A1, R2.L = A0 \(IH\) \|\| R0=\[I2\+\+M2\] \|\| NOP; + a8: 67 c9 80 38 R2.H = A1, R2.L = A0 \(IH\) \|\| R0 = \[I2 \+\+ M2\] \|\| NOP; ac: d0 9d 00 00 - b0: 07 c8 80 38 R2.H = A1, R2.L = A0 \|\| R0=\[I2\+\+M3\] \|\| NOP; + b0: 07 c8 80 38 R2.H = A1, R2.L = A0 \|\| R0 = \[I2 \+\+ M3\] \|\| NOP; b4: f0 9d 00 00 - b8: 47 c8 00 38 R0.H = A1, R0.L = A0 \(T\) \|\| R5=\[I3\+\+M0\] \|\| NOP; + b8: 47 c8 00 38 R0.H = A1, R0.L = A0 \(T\) \|\| R5 = \[I3 \+\+ M0\] \|\| NOP; bc: 9d 9d 00 00 - c0: 87 c8 00 38 R0.H = A1, R0.L = A0 \(FU\) \|\| R5=\[I3\+\+M1\] \|\| NOP; + c0: 87 c8 00 38 R0.H = A1, R0.L = A0 \(FU\) \|\| R5 = \[I3 \+\+ M1\] \|\| NOP; c4: bd 9d 00 00 - c8: 07 c9 00 38 R0.H = A1, R0.L = A0 \(IS\) \|\| R5=\[I3\+\+M2\] \|\| NOP; + c8: 07 c9 00 38 R0.H = A1, R0.L = A0 \(IS\) \|\| R5 = \[I3 \+\+ M2\] \|\| NOP; cc: dd 9d 00 00 - d0: 07 c8 00 38 R0.H = A1, R0.L = A0 \|\| R5=\[I3\+\+M3\] \|\| NOP; + d0: 07 c8 00 38 R0.H = A1, R0.L = A0 \|\| R5 = \[I3 \+\+ M3\] \|\| NOP; d4: fd 9d 00 00 - d8: 83 ce 08 41 A0=A0>>0x1f \|\| R0=\[FP-32\] \|\| NOP; + d8: 83 ce 08 41 A0 = A0 >> 0x1f \|\| R0 = \[FP -0x20\] \|\| NOP; dc: 80 b9 00 00 - e0: 83 ce f8 00 A0=A0<<0x1f \|\| R0=\[FP-28\] \|\| NOP; + e0: 83 ce f8 00 A0 = A0 << 0x1f \|\| R0 = \[FP -0x1c\] \|\| NOP; e4: 90 b9 00 00 - e8: 83 ce 00 50 A1=A1>>0x0 \|\| R0=\[FP-24\] \|\| NOP; + e8: 83 ce 00 50 A1 = A1 >> 0x0 \|\| R0 = \[FP -0x18\] \|\| NOP; ec: a0 b9 00 00 - f0: 83 ce 00 10 A1=A1<<0x0 \|\| R0=\[FP-20\] \|\| NOP; + f0: 83 ce 00 10 A1 = A1 << 0x0 \|\| R0 = \[FP -0x14\] \|\| NOP; f4: b0 b9 00 00 - f8: 82 ce fd 4e R7=R5<<0x1f\(S\) \|\| R0=\[FP-16\] \|\| NOP; + f8: 82 ce fd 4e R7 = R5 << 0x1f \(S\) \|\| R0 = \[FP -0x10\] \|\| NOP; fc: c0 b9 00 00 - 100: 82 ce 52 07 R3=R2>>>0x16 \|\| R0=\[FP-12\] \|\| NOP; + 100: 82 ce 52 07 R3 = R2 >>> 0x16 \|\| R0 = \[FP -0xc\] \|\| NOP; 104: d0 b9 00 00 - 108: 80 ce 7a 52 R1.L = R2.H << 0xf \(S\) \|\| R0=\[FP-8\] \|\| NOP; + 108: 80 ce 7a 52 R1.L = R2.H << 0xf \(S\) \|\| R0 = \[FP -0x8\] \|\| NOP; 10c: e0 b9 00 00 - 110: 80 ce f2 2b R5.H = R2.L >>> 0x2 \|\| R0=\[FP-4\] \|\| NOP; + 110: 80 ce f2 2b R5.H = R2.L >>> 0x2 \|\| R0 = \[FP -0x4\] \|\| NOP; 114: f0 b9 00 00 - 118: 00 ce 14 16 R3.L= ASHIFT R4.H BY R2.L \|\| R0=\[FP-100\] \|\| NOP; + 118: 00 ce 14 16 R3.L = ASHIFT R4.H BY R2.L \|\| R0 = \[FP -0x64\] \|\| NOP; 11c: 70 b8 00 00 - 120: 00 ce 07 6e R7.H= ASHIFT R7.L BY R0.L\(S\) \|\| R0=\[FP-104\] \|\| NOP; + 120: 00 ce 07 6e R7.H = ASHIFT R7.L BY R0.L \(S\) \|\| R0 = \[FP -0x68\] \|\| NOP; 124: 60 b8 00 00 - 128: 00 ce 07 6e R7.H= ASHIFT R7.L BY R0.L\(S\) \|\| R0=\[FP-108\] \|\| NOP; + 128: 00 ce 07 6e R7.H = ASHIFT R7.L BY R0.L \(S\) \|\| R0 = \[FP -0x6c\] \|\| NOP; 12c: 50 b8 00 00 - 130: 02 ce 15 0c R6= ASHIFT R5 BY R2.L \|\| R0=\[FP-112\] \|\| NOP; + 130: 02 ce 15 0c R6 = ASHIFT R5 BY R2.L \|\| R0 = \[FP -0x70\] \|\| NOP; 134: 40 b8 00 00 - 138: 02 ce 0c 40 R0= ASHIFT R4 BY R1.L\(S\) \|\| R3=\[FP-116\] \|\| NOP; + 138: 02 ce 0c 40 R0 = ASHIFT R4 BY R1.L \(S\) \|\| R3 = \[FP -0x74\] \|\| NOP; 13c: 33 b8 00 00 - 140: 02 ce 1e 44 R2= ASHIFT R6 BY R3.L\(S\) \|\| R0=\[FP-120\] \|\| NOP; + 140: 02 ce 1e 44 R2 = ASHIFT R6 BY R3.L \(S\) \|\| R0 = \[FP -0x78\] \|\| NOP; 144: 20 b8 00 00 - 148: 03 ce 08 00 A0= ASHIFT A0 BY R1.L \|\| R0=\[FP-124\] \|\| NOP; + 148: 03 ce 08 00 A0 = ASHIFT A0 BY R1.L \|\| R0 = \[FP -0x7c\] \|\| NOP; 14c: 10 b8 00 00 - 150: 03 ce 00 10 A1= ASHIFT A1 BY R0.L \|\| R0=\[FP-128\] \|\| NOP; + 150: 03 ce 00 10 A1 = ASHIFT A1 BY R0.L \|\| R0 = \[FP -0x80\] \|\| NOP; 154: 00 b8 00 00 - 158: 80 ce 8a a3 R1.H = R2.L >> 0xf \|\| R5=W\[P1--\] \(Z\) \|\| NOP; + 158: 80 ce 8a a3 R1.H = R2.L >> 0xf \|\| R5 = W\[P1--\] \(Z\) \|\| NOP; 15c: 8d 94 00 00 - 160: 80 ce 00 8e R7.L = R0.L << 0x0 \|\| R5=W\[P2\] \(Z\) \|\| NOP; + 160: 80 ce 00 8e R7.L = R0.L << 0x0 \|\| R5 = W\[P2\] \(Z\) \|\| NOP; 164: 15 95 00 00 - 168: 82 ce 0d 8b R5=R5>>0x1f \|\| R7=W\[P2\+\+\] \(Z\) \|\| NOP; + 168: 82 ce 0d 8b R5 = R5 >> 0x1f \|\| R7 = W\[P2\+\+\] \(Z\) \|\| NOP; 16c: 17 94 00 00 - 170: 82 ce 60 80 R0=R0<<0xc \|\| R5=W\[P2--\] \(Z\) \|\| NOP; + 170: 82 ce 60 80 R0 = R0 << 0xc \|\| R5 = W\[P2--\] \(Z\) \|\| NOP; 174: 95 94 00 00 - 178: 83 ce f8 41 A0=A0>>0x1 \|\| R5=W\[P2\+0x0\] \(Z\) \|\| NOP; + 178: 83 ce f8 41 A0 = A0 >> 0x1 \|\| R5 = W\[P2 \+ 0x0\] \(Z\) \|\| NOP; 17c: 15 a4 00 00 - 180: 83 ce 00 00 A0=A0<<0x0 \|\| R5=W\[P2\+0x2\] \(Z\) \|\| NOP; + 180: 83 ce 00 00 A0 = A0 << 0x0 \|\| R5 = W\[P2 \+ 0x2\] \(Z\) \|\| NOP; 184: 55 a4 00 00 - 188: 83 ce f8 10 A1=A1<<0x1f \|\| R5=W\[P2\+0x4\] \(Z\) \|\| NOP; + 188: 83 ce f8 10 A1 = A1 << 0x1f \|\| R5 = W\[P2 \+ 0x4\] \(Z\) \|\| NOP; 18c: 95 a4 00 00 - 190: 83 ce 80 51 A1=A1>>0x10 \|\| R5=W\[P2\+0x1e\] \(Z\) \|\| NOP; + 190: 83 ce 80 51 A1 = A1 >> 0x10 \|\| R5 = W\[P2 \+ 0x1e\] \(Z\) \|\| NOP; 194: d5 a7 00 00 - 198: 00 ce 02 b2 R1.H= LSHIFT R2.H BY R0.L \|\| R5=W\[P2\+0x18\] \(Z\) \|\| NOP; + 198: 00 ce 02 b2 R1.H = LSHIFT R2.H BY R0.L \|\| R5 = W\[P2 \+ 0x18\] \(Z\) \|\| NOP; 19c: 15 a7 00 00 - 1a0: 00 ce 08 90 R0.L= LSHIFT R0.H BY R1.L \|\| R5=W\[P2\+0x16\] \(Z\) \|\| NOP; + 1a0: 00 ce 08 90 R0.L = LSHIFT R0.H BY R1.L \|\| R5 = W\[P2 \+ 0x16\] \(Z\) \|\| NOP; 1a4: d5 a6 00 00 - 1a8: 00 ce 16 8e R7.L= LSHIFT R6.L BY R2.L \|\| R5=W\[P2\+0x14\] \(Z\) \|\| NOP; + 1a8: 00 ce 16 8e R7.L = LSHIFT R6.L BY R2.L \|\| R5 = W\[P2 \+ 0x14\] \(Z\) \|\| NOP; 1ac: 95 a6 00 00 - 1b0: 02 ce 1c 8a R5=SHIFT R4 BY R3.L \|\| R4=W\[P2\+0x12\] \(Z\) \|\| NOP; + 1b0: 02 ce 1c 8a R5 = SHIFT R4 BY R3.L \|\| R4 = W\[P2 \+ 0x12\] \(Z\) \|\| NOP; 1b4: 54 a6 00 00 - 1b8: 03 ce 30 40 A0= LSHIFT A0 BY R6.L \|\| R5=W\[P2\+0x10\] \(Z\) \|\| NOP; + 1b8: 03 ce 30 40 A0 = LSHIFT A0 BY R6.L \|\| R5 = W\[P2 \+ 0x10\] \(Z\) \|\| NOP; 1bc: 15 a6 00 00 - 1c0: 03 ce 28 50 A1= LSHIFT A1 BY R5.L \|\| R5=W\[P2\+0xe\] \(Z\) \|\| NOP; + 1c0: 03 ce 28 50 A1 = LSHIFT A1 BY R5.L \|\| R5 = W\[P2 \+ 0xe\] \(Z\) \|\| NOP; 1c4: d5 a5 00 00 - 1c8: 82 ce 07 cf R7= ROT R7 BY -32 \|\| R5=W\[P2\+0xc\] \(Z\) \|\| NOP; + 1c8: 82 ce 07 cf R7 = ROT R7 BY -0x20 \|\| R5 = W\[P2 \+ 0xc\] \(Z\) \|\| NOP; 1cc: 95 a5 00 00 - 1d0: 82 ce 0f cd R6= ROT R7 BY -31 \|\| R5=W\[P2\+0xa\] \(Z\) \|\| NOP; + 1d0: 82 ce 0f cd R6 = ROT R7 BY -0x1f \|\| R5 = W\[P2 \+ 0xa\] \(Z\) \|\| NOP; 1d4: 55 a5 00 00 - 1d8: 82 ce ff ca R5= ROT R7 BY 0x1f \|\| R6=W\[P2\+0x8\] \(Z\) \|\| NOP; + 1d8: 82 ce ff ca R5 = ROT R7 BY 0x1f \|\| R6 = W\[P2 \+ 0x8\] \(Z\) \|\| NOP; 1dc: 16 a5 00 00 - 1e0: 82 ce f7 c8 R4= ROT R7 BY 0x1e \|\| R5=W\[P2\+0x6\] \(Z\) \|\| NOP; + 1e0: 82 ce f7 c8 R4 = ROT R7 BY 0x1e \|\| R5 = W\[P2 \+ 0x6\] \(Z\) \|\| NOP; 1e4: d5 a4 00 00 - 1e8: 83 ce 00 80 A0= ROT A0 BY 0x0 \|\| R5=W\[P3\] \(Z\) \|\| NOP; + 1e8: 83 ce 00 80 A0 = ROT A0 BY 0x0 \|\| R5 = W\[P3\] \(Z\) \|\| NOP; 1ec: 1d 95 00 00 - 1f0: 83 ce 50 80 A0= ROT A0 BY 0xa \|\| R5=W\[P3\+\+\] \(Z\) \|\| NOP; + 1f0: 83 ce 50 80 A0 = ROT A0 BY 0xa \|\| R5 = W\[P3\+\+\] \(Z\) \|\| NOP; 1f4: 1d 94 00 00 - 1f8: 83 ce 60 91 A1= ROT A1 BY -20 \|\| R5=W\[P3--\] \(Z\) \|\| NOP; + 1f8: 83 ce 60 91 A1 = ROT A1 BY -0x14 \|\| R5 = W\[P3--\] \(Z\) \|\| NOP; 1fc: 9d 94 00 00 - 200: 83 ce 00 91 A1= ROT A1 BY -32 \|\| R5=W\[P4\] \(Z\) \|\| NOP; + 200: 83 ce 00 91 A1 = ROT A1 BY -0x20 \|\| R5 = W\[P4\] \(Z\) \|\| NOP; 204: 25 95 00 00 - 208: 02 ce 11 c0 R0= ROT R1 BY R2.L \|\| R5=W\[P4\+\+\] \(Z\) \|\| NOP; + 208: 02 ce 11 c0 R0 = ROT R1 BY R2.L \|\| R5 = W\[P4\+\+\] \(Z\) \|\| NOP; 20c: 25 94 00 00 - 210: 02 ce 1c c0 R0= ROT R4 BY R3.L \|\| R5=W\[P4--\] \(Z\) \|\| NOP; + 210: 02 ce 1c c0 R0 = ROT R4 BY R3.L \|\| R5 = W\[P4--\] \(Z\) \|\| NOP; 214: a5 94 00 00 - 218: 03 ce 38 80 A0= ROT A0 BY R7.L \|\| R5=W\[P5\] \(Z\) \|\| NOP; + 218: 03 ce 38 80 A0 = ROT A0 BY R7.L \|\| R5 = W\[P5\] \(Z\) \|\| NOP; 21c: 2d 95 00 00 - 220: 03 ce 30 90 A1= ROT A1 BY R6.L \|\| R5=W\[P5\+\+\] \(Z\) \|\| NOP; + 220: 03 ce 30 90 A1 = ROT A1 BY R6.L \|\| R5 = W\[P5\+\+\] \(Z\) \|\| NOP; 224: 2d 94 00 00 - 228: 03 c8 00 18 mnop \|\| R5=W\[P5--\] \(Z\) \|\| NOP; + 228: 03 c8 00 18 MNOP \|\| R5 = W\[P5--\] \(Z\) \|\| NOP; 22c: ad 94 00 00 diff --git a/gas/testsuite/gas/bfin/parallel3.d b/gas/testsuite/gas/bfin/parallel3.d index afada02..4fd9ed7 100644 --- a/gas/testsuite/gas/bfin/parallel3.d +++ b/gas/testsuite/gas/bfin/parallel3.d @@ -5,155 +5,155 @@ Disassembly of section .text: 00000000 <.text>: - 0: 0c cc 0d 08 R4.H=R4.L=SIGN\(R1.H\)\*R5.H\+SIGN\(R1.L\)\*R5.L\) \|\| \[P0\]=P0 \|\| NOP; + 0: 0c cc 0d 08 R4.H = R4.L = SIGN \(R1.H\) \* R5.H \+ SIGN \(R1.L\) \* R5.L \|\| \[P0\] = P0 \|\| NOP; 4: 40 93 00 00 - 8: 09 ce 15 8e R7=VIT_MAX\(R5,R2\)\(ASL\) \|\| \[P0\+\+\]=P0 \|\| NOP; + 8: 09 ce 15 8e R7 = VIT_MAX \(R5, R2\) \(ASL\) \|\| \[P0\+\+\] = P0 \|\| NOP; c: 40 92 00 00 - 10: 09 ce 30 c0 R0=VIT_MAX\(R0,R6\)\(ASR\) \|\| \[P0--\]=P0 \|\| NOP; + 10: 09 ce 30 c0 R0 = VIT_MAX \(R0, R6\) \(ASR\) \|\| \[P0--\] = P0 \|\| NOP; 14: c0 92 00 00 - 18: 09 ce 03 0a R5.L=VIT_MAX \(R3\) \(ASL\) \|\| \[P0\+0x4\]=P0 \|\| NOP; + 18: 09 ce 03 0a R5.L = VIT_MAX \(R3\) \(ASL\) \|\| \[P0 \+ 0x4\] = P0 \|\| NOP; 1c: 40 bc 00 00 - 20: 09 ce 02 44 R2.L=VIT_MAX \(R2\) \(ASR\) \|\| \[P0\+0x8\]=P0 \|\| NOP; + 20: 09 ce 02 44 R2.L = VIT_MAX \(R2\) \(ASR\) \|\| \[P0 \+ 0x8\] = P0 \|\| NOP; 24: 80 bc 00 00 - 28: 06 cc 28 8a R5= ABS R5\(V\) \|\| \[P0\+0x3c\]=P0 \|\| NOP; + 28: 06 cc 28 8a R5 = ABS R5 \(V\) \|\| \[P0 \+ 0x3c\] = P0 \|\| NOP; 2c: c0 bf 00 00 - 30: 06 cc 00 84 R2= ABS R0\(V\) \|\| \[P0\+0x38\]=P0 \|\| NOP; + 30: 06 cc 00 84 R2 = ABS R0 \(V\) \|\| \[P0 \+ 0x38\] = P0 \|\| NOP; 34: 80 bf 00 00 - 38: 00 cc 1a 0a R5=R3\+\|\+R2 \|\| \[P0\+0x34\]=P0 \|\| NOP; + 38: 00 cc 1a 0a R5 = R3 \+\|\+ R2 \|\| \[P0 \+ 0x34\] = P0 \|\| NOP; 3c: 40 bf 00 00 - 40: 00 cc 1a 3a R5=R3\+\|\+R2 \(SCO\) \|\| \[P1\]=P0 \|\| NOP; + 40: 00 cc 1a 3a R5 = R3 \+\|\+ R2 \(SCO\) \|\| \[P1\] = P0 \|\| NOP; 44: 48 93 00 00 - 48: 00 cc 06 8e R7=R0-\|\+R6 \|\| \[P1\+\+\]=P0 \|\| NOP; + 48: 00 cc 06 8e R7 = R0 -\|\+ R6 \|\| \[P1\+\+\] = P0 \|\| NOP; 4c: 48 92 00 00 - 50: 00 cc 0b a4 R2=R1-\|\+R3 \(S\) \|\| \[P1--\]=P0 \|\| NOP; + 50: 00 cc 0b a4 R2 = R1 -\|\+ R3 \(S\) \|\| \[P1--\] = P0 \|\| NOP; 54: c8 92 00 00 - 58: 00 cc 02 48 R4=R0\+\|-R2 \|\| \[P1\+0x30\]=P0 \|\| NOP; + 58: 00 cc 02 48 R4 = R0 \+\|- R2 \|\| \[P1 \+ 0x30\] = P0 \|\| NOP; 5c: 08 bf 00 00 - 60: 00 cc 0a 5a R5=R1\+\|-R2 \(CO\) \|\| \[P1\+0x2c\]=P0 \|\| NOP; + 60: 00 cc 0a 5a R5 = R1 \+\|- R2 \(CO\) \|\| \[P1 \+ 0x2c\] = P0 \|\| NOP; 64: c8 be 00 00 - 68: 00 cc 1c cc R6=R3-\|-R4 \|\| \[P1\+0x28\]=P0 \|\| NOP; + 68: 00 cc 1c cc R6 = R3 -\|- R4 \|\| \[P1 \+ 0x28\] = P0 \|\| NOP; 6c: 88 be 00 00 - 70: 00 cc 2e de R7=R5-\|-R6 \(CO\) \|\| \[P2\]=P0 \|\| NOP; + 70: 00 cc 2e de R7 = R5 -\|- R6 \(CO\) \|\| \[P2\] = P0 \|\| NOP; 74: 50 93 00 00 - 78: 01 cc 63 bf R5=R4\+\|\+R3,R7=R4-\|-R3\(SCO,ASR\) \|\| \[P2\+\+\]=P0 \|\| NOP; + 78: 01 cc 63 bf R5 = R4 \+\|\+ R3, R7 = R4 -\|- R3 \(SCO, ASR\) \|\| \[P2\+\+\] = P0 \|\| NOP; 7c: 50 92 00 00 - 80: 01 cc 1e c2 R0=R3\+\|\+R6,R1=R3-\|-R6\(ASL\) \|\| \[P2--\]=P0 \|\| NOP; + 80: 01 cc 1e c2 R0 = R3 \+\|\+ R6, R1 = R3 -\|- R6 \(ASL\) \|\| \[P2--\] = P0 \|\| NOP; 84: d0 92 00 00 - 88: 21 cc ca 2d R7=R1\+\|-R2,R6=R1-\|\+R2\(S\) \|\| \[P2\+0x24\]=P0 \|\| NOP; + 88: 21 cc ca 2d R7 = R1 \+\|- R2, R6 = R1 -\|\+ R2 \(S\) \|\| \[P2 \+ 0x24\] = P0 \|\| NOP; 8c: 50 be 00 00 - 90: 21 cc 53 0a R1=R2\+\|-R3,R5=R2-\|\+R3 \|\| \[P2\+0x20\]=P0 \|\| NOP; + 90: 21 cc 53 0a R1 = R2 \+\|- R3, R5 = R2 -\|\+ R3 \|\| \[P2 \+ 0x20\] = P0 \|\| NOP; 94: 10 be 00 00 - 98: 04 cc 41 8d R5=R0\+R1,R6=R0-R1 \(NS\) \|\| \[P3\]=P0 \|\| NOP; + 98: 04 cc 41 8d R5 = R0 \+ R1, R6 = R0 - R1 \(NS\) \|\| \[P3\] = P0 \|\| NOP; 9c: 58 93 00 00 - a0: 04 cc 39 a6 R0=R7\+R1,R3=R7-R1 \(S\) \|\| \[P3\+\+\]=P0 \|\| NOP; + a0: 04 cc 39 a6 R0 = R7 \+ R1, R3 = R7 - R1 \(S\) \|\| \[P3\+\+\] = P0 \|\| NOP; a4: 58 92 00 00 - a8: 11 cc c0 0b R7=A1\+A0,R5=A1-A0 \(NS\) \|\| \[P3--\]=P0 \|\| NOP; + a8: 11 cc c0 0b R7 = A1 \+ A0, R5 = A1 - A0 \(NS\) \|\| \[P3--\] = P0 \|\| NOP; ac: d8 92 00 00 - b0: 11 cc c0 6c R3=A0\+A1,R6=A0-A1 \(S\) \|\| \[P3\+0x1c\]=P0 \|\| NOP; + b0: 11 cc c0 6c R3 = A0 \+ A1, R6 = A0 - A1 \(S\) \|\| \[P3 \+ 0x1c\] = P0 \|\| NOP; b4: d8 bd 00 00 - b8: 81 ce 8b 03 R1=R3>>>0xf \(V\) \|\| \[P3\+0x18\]=P0 \|\| NOP; + b8: 81 ce 8b 03 R1 = R3 >>> 0xf \(V\) \|\| \[P3 \+ 0x18\] = P0 \|\| NOP; bc: 98 bd 00 00 - c0: 81 ce e0 09 R4=R0>>>0x4 \(V\) \|\| \[P4\]=P0 \|\| NOP; + c0: 81 ce e0 09 R4 = R0 >>> 0x4 \(V\) \|\| \[P4\] = P0 \|\| NOP; c4: 60 93 00 00 - c8: 81 ce 00 4a R5=R0<<0x0 \(V, S\) \|\| \[P4\+\+\]=P0 \|\| NOP; + c8: 81 ce 00 4a R5 = R0 << 0x0 \(V, S\) \|\| \[P4\+\+\] = P0 \|\| NOP; cc: 60 92 00 00 - d0: 81 ce 62 44 R2=R2<<0xc \(V, S\) \|\| \[P4--\]=P0 \|\| NOP; + d0: 81 ce 62 44 R2 = R2 << 0xc \(V, S\) \|\| \[P4--\] = P0 \|\| NOP; d4: e0 92 00 00 - d8: 01 ce 15 0e R7= ASHIFT R5 BY R2.L\(V\) \|\| \[P4\+0x18\]=P0 \|\| NOP; + d8: 01 ce 15 0e R7 = ASHIFT R5 BY R2.L \(V\) \|\| \[P4 \+ 0x18\] = P0 \|\| NOP; dc: a0 bd 00 00 - e0: 01 ce 02 40 R0= ASHIFT R2 BY R0.L\(V,S\) \|\| \[P4\+0x14\]=P0 \|\| NOP; + e0: 01 ce 02 40 R0 = ASHIFT R2 BY R0.L \(V, S\) \|\| \[P4 \+ 0x14\] = P0 \|\| NOP; e4: 60 bd 00 00 - e8: 81 ce 8a 8b R5=R2 >> 0xf \(V\) \|\| \[P4\+0x10\]=P0 \|\| NOP; + e8: 81 ce 8a 8b R5 = R2 >> 0xf \(V\) \|\| \[P4 \+ 0x10\] = P0 \|\| NOP; ec: 20 bd 00 00 - f0: 81 ce 11 80 R0=R1<<0x2 \(V\) \|\| \[P4\+0xc\]=P0 \|\| NOP; + f0: 81 ce 11 80 R0 = R1 << 0x2 \(V\) \|\| \[P4 \+ 0xc\] = P0 \|\| NOP; f4: e0 bc 00 00 - f8: 01 ce 11 88 R4=SHIFT R1 BY R2.L\(V\) \|\| \[P5\]=P0 \|\| NOP; + f8: 01 ce 11 88 R4 = SHIFT R1 BY R2.L \(V\) \|\| \[P5\] = P0 \|\| NOP; fc: 68 93 00 00 - 100: 06 cc 01 0c R6=MAX\(R0,R1\)\(V\) \|\| \[P5\+\+\]=P0 \|\| NOP; + 100: 06 cc 01 0c R6 = MAX \(R0, R1\) \(V\) \|\| \[P5\+\+\] = P0 \|\| NOP; 104: 68 92 00 00 - 108: 06 cc 17 40 R0=MIN\(R2,R7\)\(V\) \|\| \[P5--\]=P0 \|\| NOP; + 108: 06 cc 17 40 R0 = MIN \(R2, R7\) \(V\) \|\| \[P5--\] = P0 \|\| NOP; 10c: e8 92 00 00 - 110: 04 ca be 66 R2.H = R7.L \* R6.H, R2 = R7.H \* R6.H \|\| \[P5\+0x8\]=P0 \|\| NOP; + 110: 04 ca be 66 R2.H = R7.L \* R6.H, R2 = R7.H \* R6.H \|\| \[P5 \+ 0x8\] = P0 \|\| NOP; 114: a8 bc 00 00 - 118: 04 ca 08 e1 R4.H = R1.H \* R0.H, R4 = R1.L \* R0.L \|\| \[P5\+0x4\]=P0 \|\| NOP; + 118: 04 ca 08 e1 R4.H = R1.H \* R0.H, R4 = R1.L \* R0.L \|\| \[P5 \+ 0x4\] = P0 \|\| NOP; 11c: 68 bc 00 00 - 120: 04 ca 1a a0 R0.H = R3.H \* R2.L, R0 = R3.L \* R2.L \|\| \[P5\]=P0 \|\| NOP; + 120: 04 ca 1a a0 R0.H = R3.H \* R2.L, R0 = R3.L \* R2.L \|\| \[P5\] = P0 \|\| NOP; 124: 68 93 00 00 - 128: 94 ca 5a e1 R5.H = R3.H \* R2.H \(M\), R5 = R3.L \* R2.L \(FU\) \|\| \[SP\]=P0 \|\| NOP; + 128: 94 ca 5a e1 R5.H = R3.H \* R2.H \(M\), R5 = R3.L \* R2.L \(FU\) \|\| \[SP\] = P0 \|\| NOP; 12c: 70 93 00 00 - 130: 2c ca 27 e0 R1 = R4.H \* R7.H, R0 = R4.L \* R7.L \(S2RND\) \|\| \[SP\+\+\]=P0 \|\| NOP; + 130: 2c ca 27 e0 R1 = R4.H \* R7.H, R0 = R4.L \* R7.L \(S2RND\) \|\| \[SP\+\+\] = P0 \|\| NOP; 134: 70 92 00 00 - 138: 0c ca 95 27 R7 = R2.L \* R5.L, R6 = R2.H \* R5.H \|\| \[SP--\]=P0 \|\| NOP; + 138: 0c ca 95 27 R7 = R2.L \* R5.L, R6 = R2.H \* R5.H \|\| \[SP--\] = P0 \|\| NOP; 13c: f0 92 00 00 - 140: 24 cb 3e e0 R0.H = R7.H \* R6.H, R0 = R7.L \* R6.L \(ISS2\) \|\| \[SP\+0x3c\]=P0 \|\| NOP; + 140: 24 cb 3e e0 R0.H = R7.H \* R6.H, R0 = R7.L \* R6.L \(ISS2\) \|\| \[SP \+ 0x3c\] = P0 \|\| NOP; 144: f0 bf 00 00 - 148: 04 cb c1 e0 R3.H = R0.H \* R1.H, R3 = R0.L \* R1.L \(IS\) \|\| \[FP\]=P0 \|\| NOP; + 148: 04 cb c1 e0 R3.H = R0.H \* R1.H, R3 = R0.L \* R1.L \(IS\) \|\| \[FP\] = P0 \|\| NOP; 14c: 78 93 00 00 - 150: 00 c8 13 46 a1 = R2.L \* R3.H, a0 = R2.H \* R3.H \|\| \[FP\+\+\]=P0 \|\| NOP; + 150: 00 c8 13 46 A1 = R2.L \* R3.H, A0 = R2.H \* R3.H \|\| \[FP\+\+\] = P0 \|\| NOP; 154: 78 92 00 00 - 158: 01 c8 08 c0 a1 \+= R1.H \* R0.H, a0 = R1.L \* R0.L \|\| \[FP--\]=P0 \|\| NOP; + 158: 01 c8 08 c0 A1 \+= R1.H \* R0.H, A0 = R1.L \* R0.L \|\| \[FP--\] = P0 \|\| NOP; 15c: f8 92 00 00 - 160: 60 c8 2f c8 a1 = R5.H \* R7.H, a0 \+= R5.L \* R7.L \(W32\) \|\| \[FP\+0x0\]=P0 \|\| NOP; + 160: 60 c8 2f c8 A1 = R5.H \* R7.H, A0 \+= R5.L \* R7.L \(W32\) \|\| \[FP \+ 0x0\] = P0 \|\| NOP; 164: 38 bc 00 00 - 168: 01 c9 01 c0 a1 \+= R0.H \* R1.H, a0 = R0.L \* R1.L \(IS\) \|\| \[FP\+0x3c\]=P0 \|\| NOP; + 168: 01 c9 01 c0 A1 \+= R0.H \* R1.H, A0 = R0.L \* R1.L \(IS\) \|\| \[FP \+ 0x3c\] = P0 \|\| NOP; 16c: f8 bf 00 00 - 170: 90 c8 1c c8 a1 = R3.H \* R4.H \(M\), a0 \+= R3.L \* R4.L \(FU\) \|\| \[P0\]=P1 \|\| NOP; + 170: 90 c8 1c c8 A1 = R3.H \* R4.H \(M\), A0 \+= R3.L \* R4.L \(FU\) \|\| \[P0\] = P1 \|\| NOP; 174: 41 93 00 00 - 178: 01 c8 24 96 a1 \+= R4.H \* R4.L, a0 -= R4.H \* R4.H \|\| \[P0\]=P2 \|\| NOP; + 178: 01 c8 24 96 A1 \+= R4.H \* R4.L, A0 -= R4.H \* R4.H \|\| \[P0\] = P2 \|\| NOP; 17c: 42 93 00 00 - 180: 25 c9 3e e8 R0.H = \(a1 \+= R7.H \* R6.H\), R0.L = \(a0 \+= R7.L \* R6.L\) \(ISS2\) \|\| \[P0\]=P3 \|\| NOP; + 180: 25 c9 3e e8 R0.H = \(A1 \+= R7.H \* R6.H\), R0.L = \(A0 \+= R7.L \* R6.L\) \(ISS2\) \|\| \[P0\] = P3 \|\| NOP; 184: 43 93 00 00 - 188: 27 c8 81 28 R2.H = A1, R2.L = \(a0 \+= R0.L \* R1.L\) \(S2RND\) \|\| \[P0\]=P4 \|\| NOP; + 188: 27 c8 81 28 R2.H = A1, R2.L = \(A0 \+= R0.L \* R1.L\) \(S2RND\) \|\| \[P0\] = P4 \|\| NOP; 18c: 44 93 00 00 - 190: 04 c8 d1 c9 R7.H = \(a1 = R2.H \* R1.H\), a0 \+= R2.L \* R1.L \|\| \[P0\]=P5 \|\| NOP; + 190: 04 c8 d1 c9 R7.H = \(A1 = R2.H \* R1.H\), A0 \+= R2.L \* R1.L \|\| \[P0\] = P5 \|\| NOP; 194: 45 93 00 00 - 198: 04 c8 be 66 R2.H = \(a1 = R7.L \* R6.H\), R2.L = \(a0 = R7.H \* R6.H\) \|\| \[P0\]=FP \|\| NOP; + 198: 04 c8 be 66 R2.H = \(A1 = R7.L \* R6.H\), R2.L = \(A0 = R7.H \* R6.H\) \|\| \[P0\] = FP \|\| NOP; 19c: 47 93 00 00 - 1a0: 05 c8 9a e1 R6.H = \(a1 \+= R3.H \* R2.H\), R6.L = \(a0 = R3.L \* R2.L\) \|\| \[P0\]=SP \|\| NOP; + 1a0: 05 c8 9a e1 R6.H = \(A1 \+= R3.H \* R2.H\), R6.L = \(A0 = R3.L \* R2.L\) \|\| \[P0\] = SP \|\| NOP; 1a4: 46 93 00 00 - 1a8: 05 c8 f5 a7 R7.H = \(a1 \+= R6.H \* R5.L\), R7.L = \(a0 = R6.H \* R5.H\) \|\| \[P0\]=R1 \|\| NOP; + 1a8: 05 c8 f5 a7 R7.H = \(A1 \+= R6.H \* R5.L\), R7.L = \(A0 = R6.H \* R5.H\) \|\| \[P0\] = R1 \|\| NOP; 1ac: 01 93 00 00 - 1b0: 14 c8 3c a8 R0.H = \(a1 = R7.H \* R4.L\) \(M\), R0.L = \(a0 \+= R7.L \* R4.L\) \|\| \[P0\+\+\]=R2 \|\| NOP; + 1b0: 14 c8 3c a8 R0.H = \(A1 = R7.H \* R4.L\) \(M\), R0.L = \(A0 \+= R7.L \* R4.L\) \|\| \[P0\+\+\] = R2 \|\| NOP; 1b4: 02 92 00 00 - 1b8: 94 c8 5a e9 R5.H = \(a1 = R3.H \* R2.H\) \(M\), R5.L = \(a0 \+= R3.L \* R2.L\) \(FU\) \|\| \[P1--\]=R3 \|\| NOP; + 1b8: 94 c8 5a e9 R5.H = \(A1 = R3.H \* R2.H\) \(M\), R5.L = \(A0 \+= R3.L \* R2.L\) \(FU\) \|\| \[P1--\] = R3 \|\| NOP; 1bc: 8b 92 00 00 - 1c0: 05 c9 1a e0 R0.H = \(a1 \+= R3.H \* R2.H\), R0.L = \(a0 = R3.L \* R2.L\) \(IS\) \|\| \[I0\]=R0 \|\| NOP; + 1c0: 05 c9 1a e0 R0.H = \(A1 \+= R3.H \* R2.H\), R0.L = \(A0 = R3.L \* R2.L\) \(IS\) \|\| \[I0\] = R0 \|\| NOP; 1c4: 00 9f 00 00 - 1c8: 1c c8 b7 d0 R3 = \(a1 = R6.H \* R7.H\) \(M\), a0 -= R6.L \* R7.L \|\| \[I0\+\+\]=R1 \|\| NOP; + 1c8: 1c c8 b7 d0 R3 = \(A1 = R6.H \* R7.H\) \(M\), A0 -= R6.L \* R7.L \|\| \[I0\+\+\] = R1 \|\| NOP; 1cc: 01 9e 00 00 - 1d0: 1c c8 3c 2e R1 = \(a1 = R7.L \* R4.L\) \(M\), R0 = \(a0 \+= R7.H \* R4.H\) \|\| \[I0--\]=R2 \|\| NOP; + 1d0: 1c c8 3c 2e R1 = \(A1 = R7.L \* R4.L\) \(M\), R0 = \(A0 \+= R7.H \* R4.H\) \|\| \[I0--\] = R2 \|\| NOP; 1d4: 82 9e 00 00 - 1d8: 2d c9 3e e8 R1 = \(a1 \+= R7.H \* R6.H\), R0 = \(a0 \+= R7.L \* R6.L\) \(ISS2\) \|\| \[I1\]=R3 \|\| NOP; + 1d8: 2d c9 3e e8 R1 = \(A1 \+= R7.H \* R6.H\), R0 = \(A0 \+= R7.L \* R6.L\) \(ISS2\) \|\| \[I1\] = R3 \|\| NOP; 1dc: 0b 9f 00 00 - 1e0: 0d c8 37 e1 R5 = \(a1 \+= R6.H \* R7.H\), R4 = \(a0 = R6.L \* R7.L\) \|\| \[I1\+\+\]=R3 \|\| NOP; + 1e0: 0d c8 37 e1 R5 = \(A1 \+= R6.H \* R7.H\), R4 = \(A0 = R6.L \* R7.L\) \|\| \[I1\+\+\] = R3 \|\| NOP; 1e4: 0b 9e 00 00 - 1e8: 0d c8 9d f1 R7 = \(a1 \+= R3.H \* R5.H\), R6 = \(a0 -= R3.L \* R5.L\) \|\| \[I1--\]=R3 \|\| NOP; + 1e8: 0d c8 9d f1 R7 = \(A1 \+= R3.H \* R5.H\), R6 = \(A0 -= R3.L \* R5.L\) \|\| \[I1--\] = R3 \|\| NOP; 1ec: 8b 9e 00 00 - 1f0: 0e c8 37 c9 R5 = \(a1 -= R6.H \* R7.H\), a0 \+= R6.L \* R7.L \|\| \[I2\]=R0 \|\| NOP; + 1f0: 0e c8 37 c9 R5 = \(A1 -= R6.H \* R7.H\), A0 \+= R6.L \* R7.L \|\| \[I2\] = R0 \|\| NOP; 1f4: 10 9f 00 00 - 1f8: 0c c8 b7 e0 R3 = \(a1 = R6.H \* R7.H\), R2 = \(a0 = R6.L \* R7.L\) \|\| \[I2\+\+\]=R0 \|\| NOP; + 1f8: 0c c8 b7 e0 R3 = \(A1 = R6.H \* R7.H\), R2 = \(A0 = R6.L \* R7.L\) \|\| \[I2\+\+\] = R0 \|\| NOP; 1fc: 10 9e 00 00 - 200: 9c c8 1f e9 R5 = \(a1 = R3.H \* R7.H\) \(M\), R4 = \(a0 \+= R3.L \* R7.L\) \(FU\) \|\| \[I2--\]=R0 \|\| NOP; + 200: 9c c8 1f e9 R5 = \(A1 = R3.H \* R7.H\) \(M\), R4 = \(A0 \+= R3.L \* R7.L\) \(FU\) \|\| \[I2--\] = R0 \|\| NOP; 204: 90 9e 00 00 - 208: 2f c8 81 28 R3 = A1, R2 = \(a0 \+= R0.L \* R1.L\) \(S2RND\) \|\| \[I3\]=R7 \|\| NOP; + 208: 2f c8 81 28 R3 = A1, R2 = \(A0 \+= R0.L \* R1.L\) \(S2RND\) \|\| \[I3\] = R7 \|\| NOP; 20c: 1f 9f 00 00 - 210: 0d c9 1a e0 R1 = \(a1 \+= R3.H \* R2.H\), R0 = \(a0 = R3.L \* R2.L\) \(IS\) \|\| \[I3\+\+\]=R7 \|\| NOP; + 210: 0d c9 1a e0 R1 = \(A1 \+= R3.H \* R2.H\), R0 = \(A0 = R3.L \* R2.L\) \(IS\) \|\| \[I3\+\+\] = R7 \|\| NOP; 214: 1f 9e 00 00 - 218: 0f cc 08 c0 R0=-R1\(V\) \|\| \[I3--\]=R6 \|\| NOP; + 218: 0f cc 08 c0 R0 = -R1 \(V\) \|\| \[I3--\] = R6 \|\| NOP; 21c: 9e 9e 00 00 - 220: 0f cc 10 ce R7=-R2\(V\) \|\| \[P0\+\+P1\]=R0 \|\| NOP; + 220: 0f cc 10 ce R7 = -R2 \(V\) \|\| \[P0 \+\+ P1\] = R0 \|\| NOP; 224: 08 88 00 00 - 228: 04 ce 08 8e R7=PACK\(R0.H,R1.L\) \|\| \[P0\+\+P1\]=R3 \|\| NOP; + 228: 04 ce 08 8e R7 = PACK \(R0.H, R1.L\) \|\| \[P0 \+\+ P1\] = R3 \|\| NOP; 22c: c8 88 00 00 - 230: 04 ce 31 cc R6=PACK\(R1.H,R6.H\) \|\| \[P0\+\+P2\]=R0 \|\| NOP; + 230: 04 ce 31 cc R6 = PACK \(R1.H, R6.H\) \|\| \[P0 \+\+ P2\] = R0 \|\| NOP; 234: 10 88 00 00 - 238: 04 ce 12 4a R5=PACK\(R2.L,R2.H\) \|\| \[P0\+\+P3\]=R4 \|\| NOP; + 238: 04 ce 12 4a R5 = PACK \(R2.L, R2.H\) \|\| \[P0 \+\+ P3\] = R4 \|\| NOP; 23c: 18 89 00 00 - 240: 0d cc 10 82 \(R0,R1\) = SEARCH R2\(LT\) \|\| R2=\[P0\+0x4\] \|\| NOP; + 240: 0d cc 10 82 \(R0, R1\) = SEARCH R2 \(LT\) \|\| R2 = \[P0 \+ 0x4\] \|\| NOP; 244: 42 a0 00 00 - 248: 0d cc 80 cf \(R6,R7\) = SEARCH R0\(LE\) \|\| R5=\[P0--\] \|\| NOP; + 248: 0d cc 80 cf \(R6, R7\) = SEARCH R0 \(LE\) \|\| R5 = \[P0--\] \|\| NOP; 24c: 85 90 00 00 - 250: 0d cc c8 0c \(R3,R6\) = SEARCH R1\(GT\) \|\| R0=\[P0\+0x14\] \|\| NOP; + 250: 0d cc c8 0c \(R3, R6\) = SEARCH R1 \(GT\) \|\| R0 = \[P0 \+ 0x14\] \|\| NOP; 254: 40 a1 00 00 - 258: 0d cc 18 4b \(R4,R5\) = SEARCH R3\(GE\) \|\| R1=\[P0\+\+\] \|\| NOP; + 258: 0d cc 18 4b \(R4, R5\) = SEARCH R3 \(GE\) \|\| R1 = \[P0\+\+\] \|\| NOP; 25c: 01 90 00 00 diff --git a/gas/testsuite/gas/bfin/parallel4.d b/gas/testsuite/gas/bfin/parallel4.d index 5b5d85f..02863f9 100644 --- a/gas/testsuite/gas/bfin/parallel4.d +++ b/gas/testsuite/gas/bfin/parallel4.d @@ -5,63 +5,63 @@ Disassembly of section .text: 00000000 <.text>: - 0: 0d ce 15 0e R7=ALIGN8\(R5,R2\) \|\| \[I0\]=R0 \|\| NOP; + 0: 0d ce 15 0e R7 = ALIGN8 \(R5, R2\) \|\| \[I0\] = R0 \|\| NOP; 4: 00 9f 00 00 - 8: 0d ce 08 4a R5=ALIGN16\(R0,R1\) \|\| \[I0\+\+\]=R0 \|\| NOP; + 8: 0d ce 08 4a R5 = ALIGN16 \(R0, R1\) \|\| \[I0\+\+\] = R0 \|\| NOP; c: 00 9e 00 00 - 10: 0d ce 05 84 R2=ALIGN24\(R5,R0\) \|\| \[I0--\]=R0 \|\| NOP; + 10: 0d ce 05 84 R2 = ALIGN24 \(R5, R0\) \|\| \[I0--\] = R0 \|\| NOP; 14: 80 9e 00 00 - 18: 12 cc 00 c0 DISALGNEXCPT \|\| \[I1\]=R0 \|\| NOP; + 18: 12 cc 00 c0 DISALGNEXCPT \|\| \[I1\] = R0 \|\| NOP; 1c: 08 9f 00 00 - 20: 17 cc 02 0a R5=BYTEOP3P\(R1:0x0,R3:0x2\)\(LO\) \|\| \[I1\+\+\]=R0 \|\| NOP; + 20: 17 cc 02 0a R5 = BYTEOP3P \(R1:0, R3:2\) \(LO\) \|\| \[I1\+\+\] = R0 \|\| NOP; 24: 08 9e 00 00 - 28: 37 cc 02 00 R0=BYTEOP3P\(R1:0x0,R3:0x2\)\(HI\) \|\| \[I1--\]=R0 \|\| NOP; + 28: 37 cc 02 00 R0 = BYTEOP3P \(R1:0, R3:2\) \(HI\) \|\| \[I1--\] = R0 \|\| NOP; 2c: 88 9e 00 00 - 30: 17 cc 02 22 R1=BYTEOP3P\(R1:0x0,R3:0x2\)\(LO, R\) \|\| \[I2\]=R0 \|\| NOP; + 30: 17 cc 02 22 R1 = BYTEOP3P \(R1:0, R3:2\) \(LO, R\) \|\| \[I2\] = R0 \|\| NOP; 34: 10 9f 00 00 - 38: 37 cc 02 24 R2=BYTEOP3P\(R1:0x0,R3:0x2\)\(HI, R\) \|\| \[I2\+\+\]=R0 \|\| NOP; + 38: 37 cc 02 24 R2 = BYTEOP3P \(R1:0, R3:2\) \(HI, R\) \|\| \[I2\+\+\] = R0 \|\| NOP; 3c: 10 9e 00 00 - 40: 0c cc 40 45 R5=A1.L\+A1.H,R2=A0.L\+A0.H \|\| \[I2--\]=R0 \|\| NOP; + 40: 0c cc 40 45 R5 = A1.L \+ A1.H, R2 = A0.L \+ A0.H \|\| \[I2--\] = R0 \|\| NOP; 44: 90 9e 00 00 - 48: 15 cc 82 06 \(R2,R3\)=BYTEOP16P\(R1:0x0,R3:0x2\) \|\| \[I3\]=R0 \|\| NOP; + 48: 15 cc 82 06 \(R2, R3\) = BYTEOP16P \(R1:0, R3:2\) \|\| \[I3\] = R0 \|\| NOP; 4c: 18 9f 00 00 - 50: 15 cc 82 21 \(R6,R0\)=BYTEOP16P\(R1:0x0,R3:0x2\) \(R\) \|\| \[I3\+\+\]=R0 \|\| NOP; + 50: 15 cc 82 21 \(R6, R0\) = BYTEOP16P \(R1:0, R3:2\) \(R\) \|\| \[I3\+\+\] = R0 \|\| NOP; 54: 18 9e 00 00 - 58: 14 cc 02 4e R7=BYTEOP1P\(R1:0x0,R3:0x2\)\(T\) \|\| \[I3--\]=R0 \|\| NOP; + 58: 14 cc 02 4e R7 = BYTEOP1P \(R1:0, R3:2\) \(T\) \|\| \[I3--\] = R0 \|\| NOP; 5c: 98 9e 00 00 - 60: 14 cc 02 44 R2=BYTEOP1P\(R1:0x0,R3:0x2\)\(T\) \|\| \[P0\]=R0 \|\| NOP; + 60: 14 cc 02 44 R2 = BYTEOP1P \(R1:0, R3:2\) \(T\) \|\| \[P0\] = R0 \|\| NOP; 64: 00 93 00 00 - 68: 14 cc 02 26 R3=BYTEOP1P\(R1:0x0,R3:0x2\)\(R\) \|\| \[P0\+\+\]=R0 \|\| NOP; + 68: 14 cc 02 26 R3 = BYTEOP1P \(R1:0, R3:2\) \(R\) \|\| \[P0\+\+\] = R0 \|\| NOP; 6c: 00 92 00 00 - 70: 14 cc 02 6e R7=BYTEOP1P\(R1:0x0,R3:0x2\)\(T, R\) \|\| \[P0--\]=R0 \|\| NOP; + 70: 14 cc 02 6e R7 = BYTEOP1P \(R1:0, R3:2\) \(T, R\) \|\| \[P0--\] = R0 \|\| NOP; 74: 80 92 00 00 - 78: 16 cc 02 00 R0=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL\) \|\| \[P1\]=R0 \|\| NOP; + 78: 16 cc 02 00 R0 = BYTEOP2P \(R1:0, R3:2\) \(RNDL\) \|\| \[P1\] = R0 \|\| NOP; 7c: 08 93 00 00 - 80: 36 cc 02 02 R1=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH\) \|\| \[P1\+\+\]=R0 \|\| NOP; + 80: 36 cc 02 02 R1 = BYTEOP2P \(R1:0, R3:2\) \(RNDH\) \|\| \[P1\+\+\] = R0 \|\| NOP; 84: 08 92 00 00 - 88: 16 cc 02 44 R2=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL\) \|\| \[P1--\]=R0 \|\| NOP; + 88: 16 cc 02 44 R2 = BYTEOP2P \(R1:0, R3:2\) \(TL\) \|\| \[P1--\] = R0 \|\| NOP; 8c: 88 92 00 00 - 90: 36 cc 02 46 R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH\) \|\| \[P2\]=R0 \|\| NOP; + 90: 36 cc 02 46 R3 = BYTEOP2P \(R1:0, R3:2\) \(TH\) \|\| \[P2\] = R0 \|\| NOP; 94: 10 93 00 00 - 98: 16 cc 02 28 R4=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL, R\) \|\| \[P2\+\+\]=R0 \|\| NOP; + 98: 16 cc 02 28 R4 = BYTEOP2P \(R1:0, R3:2\) \(RNDL, R\) \|\| \[P2\+\+\] = R0 \|\| NOP; 9c: 10 92 00 00 - a0: 36 cc 02 2a R5=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH, R\) \|\| \[P2--\]=R0 \|\| NOP; + a0: 36 cc 02 2a R5 = BYTEOP2P \(R1:0, R3:2\) \(RNDH, R\) \|\| \[P2--\] = R0 \|\| NOP; a4: 90 92 00 00 - a8: 16 cc 02 6c R6=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL, R\) \|\| \[P3\]=R0 \|\| NOP; + a8: 16 cc 02 6c R6 = BYTEOP2P \(R1:0, R3:2\) \(TL, R\) \|\| \[P3\] = R0 \|\| NOP; ac: 18 93 00 00 - b0: 36 cc 02 6e R7=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH, R\) \|\| \[P3\+\+\]=R0 \|\| NOP; + b0: 36 cc 02 6e R7 = BYTEOP2P \(R1:0, R3:2\) \(TH, R\) \|\| \[P3\+\+\] = R0 \|\| NOP; b4: 18 92 00 00 - b8: 18 cc 03 0a R5=BYTEPACK\(R0,R3\) \|\| \[P3--\]=R0 \|\| NOP; + b8: 18 cc 03 0a R5 = BYTEPACK \(R0, R3\) \|\| \[P3--\] = R0 \|\| NOP; bc: 98 92 00 00 - c0: 15 cc 82 45 \(R6,R2\)=BYTEOP16M\(R1:0x0,R3:0x2\) \|\| \[P4\]=R0 \|\| NOP; + c0: 15 cc 82 45 \(R6, R2\) = BYTEOP16M \(R1:0, R3:2\) \|\| \[P4\] = R0 \|\| NOP; c4: 20 93 00 00 - c8: 15 cc 02 6a \(R0,R5\)=BYTEOP16M\(R1:0x0,R3:0x2\) \(R\) \|\| \[P4\+\+\]=R0 \|\| NOP; + c8: 15 cc 02 6a \(R0, R5\) = BYTEOP16M \(R1:0, R3:2\) \(R\) \|\| \[P4\+\+\] = R0 \|\| NOP; cc: 20 92 00 00 - d0: 12 cc 02 00 SAA\(R1:0x0,R3:0x2\) \|\| \[P4--\]=R0 \|\| NOP; + d0: 12 cc 02 00 SAA \(R1:0, R3:2\) \|\| \[P4--\] = R0 \|\| NOP; d4: a0 92 00 00 - d8: 12 cc 02 20 SAA\(R1:0x0,R3:0x2\) \(R\) \|\| \[P5\]=R0 \|\| NOP; + d8: 12 cc 02 20 SAA \(R1:0, R3:2\) \(R\) \|\| \[P5\] = R0 \|\| NOP; dc: 28 93 00 00 - e0: 18 cc c0 45 \(R7,R2\) = BYTEUNPACK R1:0x0 \|\| \[P5\+\+\]=R0 \|\| NOP; + e0: 18 cc c0 45 \(R7, R2\) = BYTEUNPACK R1:0 \|\| \[P5\+\+\] = R0 \|\| NOP; e4: 28 92 00 00 - e8: 18 cc 90 69 \(R6,R4\) = BYTEUNPACK R3:0x2 \(R\) \|\| \[P5--\]=R0 \|\| NOP; + e8: 18 cc 90 69 \(R6, R4\) = BYTEUNPACK R3:2 \(R\) \|\| \[P5--\] = R0 \|\| NOP; ec: a8 92 00 00 diff --git a/gas/testsuite/gas/bfin/shift.d b/gas/testsuite/gas/bfin/shift.d index b355f72..2b85101 100644 --- a/gas/testsuite/gas/bfin/shift.d +++ b/gas/testsuite/gas/bfin/shift.d @@ -5,71 +5,71 @@ Disassembly of section .text: 00000000 <add_with_shift>: - 0: 88 45 P0=\(P0\+P1\)<<1; - 2: ea 45 P2=\(P2\+P5\)<<2; - 4: 4f 41 R7=\(R7\+R1\)<<2; - 6: 03 41 R3=\(R3\+R0\)<<1; + 0: 88 45 P0 = \(P0 \+ P1\) << 0x1; + 2: ea 45 P2 = \(P2 \+ P5\) << 0x2; + 4: 4f 41 R7 = \(R7 \+ R1\) << 0x2; + 6: 03 41 R3 = \(R3 \+ R0\) << 0x1; 00000008 <shift_with_add>: - 8: 44 5f P5=P4\+\(P0<<2\); - a: 0a 5c P0=P2\+\(P1<<1\); + 8: 44 5f P5 = P4 \+ \(P0 << 0x2\); + a: 0a 5c P0 = P2 \+ \(P1 << 0x1\); 0000000c <arithmetic_shift>: - c: 83 c6 08 41 A0=A0>>0x1f; - 10: 83 c6 f8 00 A0=A0<<0x1f; - 14: 83 c6 00 50 A1=A1>>0x0; - 18: 83 c6 00 10 A1=A1<<0x0; - 1c: 82 c6 fd 4e R7=R5<<0x1f\(S\); - 20: 82 c6 52 07 R3=R2>>>0x16; + c: 83 c6 08 41 A0 = A0 >> 0x1f; + 10: 83 c6 f8 00 A0 = A0 << 0x1f; + 14: 83 c6 00 50 A1 = A1 >> 0x0; + 18: 83 c6 00 10 A1 = A1 << 0x0; + 1c: 82 c6 fd 4e R7 = R5 << 0x1f \(S\); + 20: 82 c6 52 07 R3 = R2 >>> 0x16; 24: 80 c6 7a 52 R1.L = R2.H << 0xf \(S\); 28: 80 c6 f2 2b R5.H = R2.L >>> 0x2; - 2c: 00 4f R0<<=0x0; - 2e: f9 4d R1>>>=0x1f; - 30: 08 40 R0>>>=R1; - 32: 8a 40 R2<<=R1; - 34: 00 c6 14 16 R3.L= ASHIFT R4.H BY R2.L; - 38: 00 c6 07 6e R7.H= ASHIFT R7.L BY R0.L\(S\); - 3c: 00 c6 07 6e R7.H= ASHIFT R7.L BY R0.L\(S\); - 40: 02 c6 15 0c R6= ASHIFT R5 BY R2.L; - 44: 02 c6 0c 40 R0= ASHIFT R4 BY R1.L\(S\); - 48: 02 c6 1e 44 R2= ASHIFT R6 BY R3.L\(S\); - 4c: 03 c6 08 00 A0= ASHIFT A0 BY R1.L; - 50: 03 c6 00 10 A1= ASHIFT A1 BY R0.L; + 2c: 00 4f R0 <<= 0x0; + 2e: f9 4d R1 >>>= 0x1f; + 30: 08 40 R0 >>>= R1; + 32: 8a 40 R2 <<= R1; + 34: 00 c6 14 16 R3.L = ASHIFT R4.H BY R2.L; + 38: 00 c6 07 6e R7.H = ASHIFT R7.L BY R0.L \(S\); + 3c: 00 c6 07 6e R7.H = ASHIFT R7.L BY R0.L \(S\); + 40: 02 c6 15 0c R6 = ASHIFT R5 BY R2.L; + 44: 02 c6 0c 40 R0 = ASHIFT R4 BY R1.L \(S\); + 48: 02 c6 1e 44 R2 = ASHIFT R6 BY R3.L \(S\); + 4c: 03 c6 08 00 A0 = ASHIFT A0 BY R1.L; + 50: 03 c6 00 10 A1 = ASHIFT A1 BY R0.L; 00000054 <logical_shift>: - 54: 00 45 P0=P0>>1; - 56: d1 44 P1=P2>>2; - 58: c9 5a P3=P1<<1; - 5a: 6c 44 P4=P5<<2; - 5c: f8 4e R0>>=0x1f; - 5e: ff 4f R7<<=0x1f; + 54: 00 45 P0 = P0 >> 0x1; + 56: d1 44 P1 = P2 >> 0x2; + 58: c9 5a P3 = P1 << 0x1; + 5a: 6c 44 P4 = P5 << 0x2; + 5c: f8 4e R0 >>= 0x1f; + 5e: ff 4f R7 <<= 0x1f; 60: 80 c6 8a a3 R1.H = R2.L >> 0xf; 64: 80 c6 00 8e R7.L = R0.L << 0x0; - 68: 82 c6 0d 8b R5=R5>>0x1f; - 6c: 82 c6 60 80 R0=R0<<0xc; - 70: 83 c6 f8 41 A0=A0>>0x1; - 74: 83 c6 00 00 A0=A0<<0x0; - 78: 83 c6 f8 10 A1=A1<<0x1f; - 7c: 83 c6 80 51 A1=A1>>0x10; - 80: 7d 40 R5>>=R7; - 82: 86 40 R6<<=R0; - 84: 00 c6 02 b2 R1.H= LSHIFT R2.H BY R0.L; - 88: 00 c6 08 90 R0.L= LSHIFT R0.H BY R1.L; - 8c: 00 c6 16 8e R7.L= LSHIFT R6.L BY R2.L; - 90: 02 c6 1c 8a R5=SHIFT R4 BY R3.L; - 94: 03 c6 30 40 A0= LSHIFT A0 BY R6.L; - 98: 03 c6 28 50 A1= LSHIFT A1 BY R5.L; + 68: 82 c6 0d 8b R5 = R5 >> 0x1f; + 6c: 82 c6 60 80 R0 = R0 << 0xc; + 70: 83 c6 f8 41 A0 = A0 >> 0x1; + 74: 83 c6 00 00 A0 = A0 << 0x0; + 78: 83 c6 f8 10 A1 = A1 << 0x1f; + 7c: 83 c6 80 51 A1 = A1 >> 0x10; + 80: 7d 40 R5 >>= R7; + 82: 86 40 R6 <<= R0; + 84: 00 c6 02 b2 R1.H = LSHIFT R2.H BY R0.L; + 88: 00 c6 08 90 R0.L = LSHIFT R0.H BY R1.L; + 8c: 00 c6 16 8e R7.L = LSHIFT R6.L BY R2.L; + 90: 02 c6 1c 8a R5 = SHIFT R4 BY R3.L; + 94: 03 c6 30 40 A0 = LSHIFT A0 BY R6.L; + 98: 03 c6 28 50 A1 = LSHIFT A1 BY R5.L; 0000009c <rotate>: - 9c: 82 c6 07 cf R7= ROT R7 BY -32; - a0: 82 c6 0f cd R6= ROT R7 BY -31; - a4: 82 c6 ff ca R5= ROT R7 BY 0x1f; - a8: 82 c6 f7 c8 R4= ROT R7 BY 0x1e; - ac: 83 c6 00 80 A0= ROT A0 BY 0x0; - b0: 83 c6 50 80 A0= ROT A0 BY 0xa; - b4: 83 c6 60 91 A1= ROT A1 BY -20; - b8: 83 c6 00 91 A1= ROT A1 BY -32; - bc: 02 c6 11 c0 R0= ROT R1 BY R2.L; - c0: 02 c6 1c c0 R0= ROT R4 BY R3.L; - c4: 03 c6 38 80 A0= ROT A0 BY R7.L; - c8: 03 c6 30 90 A1= ROT A1 BY R6.L; + 9c: 82 c6 07 cf R7 = ROT R7 BY -0x20; + a0: 82 c6 0f cd R6 = ROT R7 BY -0x1f; + a4: 82 c6 ff ca R5 = ROT R7 BY 0x1f; + a8: 82 c6 f7 c8 R4 = ROT R7 BY 0x1e; + ac: 83 c6 00 80 A0 = ROT A0 BY 0x0; + b0: 83 c6 50 80 A0 = ROT A0 BY 0xa; + b4: 83 c6 60 91 A1 = ROT A1 BY -0x14; + b8: 83 c6 00 91 A1 = ROT A1 BY -0x20; + bc: 02 c6 11 c0 R0 = ROT R1 BY R2.L; + c0: 02 c6 1c c0 R0 = ROT R4 BY R3.L; + c4: 03 c6 38 80 A0 = ROT A0 BY R7.L; + c8: 03 c6 30 90 A1 = ROT A1 BY R6.L; diff --git a/gas/testsuite/gas/bfin/shift2.d b/gas/testsuite/gas/bfin/shift2.d index 75416b1..f8c76f5 100644 --- a/gas/testsuite/gas/bfin/shift2.d +++ b/gas/testsuite/gas/bfin/shift2.d @@ -5,54 +5,54 @@ Disassembly of section .text: 00000000 <.text>: - 0: 80 45 P0=\(P0\+P0\)<<1; - 2: 88 45 P0=\(P0\+P1\)<<1; - 4: 82 45 P2=\(P2\+P0\)<<1; - 6: 91 45 P1=\(P1\+P2\)<<1; - 8: c0 45 P0=\(P0\+P0\)<<2; - a: c8 45 P0=\(P0\+P1\)<<2; - c: c2 45 P2=\(P2\+P0\)<<2; - e: d1 45 P1=\(P1\+P2\)<<2; - 10: 00 41 R0=\(R0\+R0\)<<1; - 12: 08 41 R0=\(R0\+R1\)<<1; - 14: 02 41 R2=\(R2\+R0\)<<1; - 16: 11 41 R1=\(R1\+R2\)<<1; - 18: 40 41 R0=\(R0\+R0\)<<2; - 1a: 48 41 R0=\(R0\+R1\)<<2; - 1c: 42 41 R2=\(R2\+R0\)<<2; - 1e: 51 41 R1=\(R1\+R2\)<<2; - 20: 00 5c P0=P0\+\(P0<<1\); - 22: 08 5c P0=P0\+\(P1<<1\); - 24: 10 5c P0=P0\+\(P2<<1\); - 26: 11 5c P0=P1\+\(P2<<1\); - 28: 1a 5c P0=P2\+\(P3<<1\); - 2a: 40 5c P1=P0\+\(P0<<1\); - 2c: 48 5c P1=P0\+\(P1<<1\); - 2e: 50 5c P1=P0\+\(P2<<1\); - 30: 51 5c P1=P1\+\(P2<<1\); - 32: 5a 5c P1=P2\+\(P3<<1\); - 34: 00 5e P0=P0\+\(P0<<2\); - 36: 08 5e P0=P0\+\(P1<<2\); - 38: 10 5e P0=P0\+\(P2<<2\); - 3a: 11 5e P0=P1\+\(P2<<2\); - 3c: 1a 5e P0=P2\+\(P3<<2\); - 3e: 40 5e P1=P0\+\(P0<<2\); - 40: 48 5e P1=P0\+\(P1<<2\); - 42: 50 5e P1=P0\+\(P2<<2\); - 44: 51 5e P1=P1\+\(P2<<2\); - 46: 5a 5e P1=P2\+\(P3<<2\); - 48: 00 4d R0>>>=0x0; - 4a: f8 4d R0>>>=0x1f; - 4c: 28 4d R0>>>=0x5; - 4e: 05 4d R5>>>=0x0; - 50: fd 4d R5>>>=0x1f; - 52: 2d 4d R5>>>=0x5; - 54: 00 4f R0<<=0x0; - 56: f8 4f R0<<=0x1f; - 58: 28 4f R0<<=0x5; - 5a: 05 4f R5<<=0x0; - 5c: fd 4f R5<<=0x1f; - 5e: 2d 4f R5<<=0x5; + 0: 80 45 P0 = \(P0 \+ P0\) << 0x1; + 2: 88 45 P0 = \(P0 \+ P1\) << 0x1; + 4: 82 45 P2 = \(P2 \+ P0\) << 0x1; + 6: 91 45 P1 = \(P1 \+ P2\) << 0x1; + 8: c0 45 P0 = \(P0 \+ P0\) << 0x2; + a: c8 45 P0 = \(P0 \+ P1\) << 0x2; + c: c2 45 P2 = \(P2 \+ P0\) << 0x2; + e: d1 45 P1 = \(P1 \+ P2\) << 0x2; + 10: 00 41 R0 = \(R0 \+ R0\) << 0x1; + 12: 08 41 R0 = \(R0 \+ R1\) << 0x1; + 14: 02 41 R2 = \(R2 \+ R0\) << 0x1; + 16: 11 41 R1 = \(R1 \+ R2\) << 0x1; + 18: 40 41 R0 = \(R0 \+ R0\) << 0x2; + 1a: 48 41 R0 = \(R0 \+ R1\) << 0x2; + 1c: 42 41 R2 = \(R2 \+ R0\) << 0x2; + 1e: 51 41 R1 = \(R1 \+ R2\) << 0x2; + 20: 00 5c P0 = P0 \+ \(P0 << 0x1\); + 22: 08 5c P0 = P0 \+ \(P1 << 0x1\); + 24: 10 5c P0 = P0 \+ \(P2 << 0x1\); + 26: 11 5c P0 = P1 \+ \(P2 << 0x1\); + 28: 1a 5c P0 = P2 \+ \(P3 << 0x1\); + 2a: 40 5c P1 = P0 \+ \(P0 << 0x1\); + 2c: 48 5c P1 = P0 \+ \(P1 << 0x1\); + 2e: 50 5c P1 = P0 \+ \(P2 << 0x1\); + 30: 51 5c P1 = P1 \+ \(P2 << 0x1\); + 32: 5a 5c P1 = P2 \+ \(P3 << 0x1\); + 34: 00 5e P0 = P0 \+ \(P0 << 0x2\); + 36: 08 5e P0 = P0 \+ \(P1 << 0x2\); + 38: 10 5e P0 = P0 \+ \(P2 << 0x2\); + 3a: 11 5e P0 = P1 \+ \(P2 << 0x2\); + 3c: 1a 5e P0 = P2 \+ \(P3 << 0x2\); + 3e: 40 5e P1 = P0 \+ \(P0 << 0x2\); + 40: 48 5e P1 = P0 \+ \(P1 << 0x2\); + 42: 50 5e P1 = P0 \+ \(P2 << 0x2\); + 44: 51 5e P1 = P1 \+ \(P2 << 0x2\); + 46: 5a 5e P1 = P2 \+ \(P3 << 0x2\); + 48: 00 4d R0 >>>= 0x0; + 4a: f8 4d R0 >>>= 0x1f; + 4c: 28 4d R0 >>>= 0x5; + 4e: 05 4d R5 >>>= 0x0; + 50: fd 4d R5 >>>= 0x1f; + 52: 2d 4d R5 >>>= 0x5; + 54: 00 4f R0 <<= 0x0; + 56: f8 4f R0 <<= 0x1f; + 58: 28 4f R0 <<= 0x5; + 5a: 05 4f R5 <<= 0x0; + 5c: fd 4f R5 <<= 0x1f; + 5e: 2d 4f R5 <<= 0x5; 60: 80 c6 00 00 R0.L = R0.L >>> 0x0; 64: 80 c6 88 01 R0.L = R0.L >>> 0xf; 68: 80 c6 00 10 R0.L = R0.H >>> 0x0; @@ -101,96 +101,96 @@ Disassembly of section .text: 114: 80 c6 7a 6a R5.H = R2.L << 0xf \(S\); 118: 80 c6 01 7c R6.H = R1.H << 0x0 \(S\); 11c: 80 c6 78 7e R7.H = R0.H << 0xf \(S\); - 120: 82 c6 00 00 R0=R0>>>0x0; - 124: 82 c6 08 01 R0=R0>>>0x1f; - 128: 82 c6 01 00 R0=R1>>>0x0; - 12c: 82 c6 09 01 R0=R1>>>0x1f; - 130: 82 c6 00 0e R7=R0>>>0x0; - 134: 82 c6 09 0d R6=R1>>>0x1f; - 138: 82 c6 02 0a R5=R2>>>0x0; - 13c: 82 c6 0b 09 R4=R3>>>0x1f; - 140: 82 c6 04 06 R3=R4>>>0x0; - 144: 82 c6 0d 05 R2=R5>>>0x1f; - 148: 82 c6 06 02 R1=R6>>>0x0; - 14c: 82 c6 0f 01 R0=R7>>>0x1f; - 150: 82 c6 00 40 R0=R0<<0x0\(S\); - 154: 82 c6 f8 40 R0=R0<<0x1f\(S\); - 158: 82 c6 01 40 R0=R1<<0x0\(S\); - 15c: 82 c6 f9 40 R0=R1<<0x1f\(S\); - 160: 82 c6 00 4e R7=R0<<0x0\(S\); - 164: 82 c6 f9 4c R6=R1<<0x1f\(S\); - 168: 82 c6 02 4a R5=R2<<0x0\(S\); - 16c: 82 c6 fb 48 R4=R3<<0x1f\(S\); - 170: 82 c6 04 46 R3=R4<<0x0\(S\); - 174: 82 c6 fd 44 R2=R5<<0x1f\(S\); - 178: 82 c6 06 42 R1=R6<<0x0\(S\); - 17c: 82 c6 ff 40 R0=R7<<0x1f\(S\); - 180: 83 c6 00 00 A0=A0<<0x0; - 184: 83 c6 88 01 A0=A0>>>0xf; - 188: 83 c6 08 01 A0=A0>>>0x1f; - 18c: 83 c6 00 00 A0=A0<<0x0; - 190: 83 c6 78 00 A0=A0<<0xf; - 194: 83 c6 f8 00 A0=A0<<0x1f; - 198: 83 c6 00 10 A1=A1<<0x0; - 19c: 83 c6 88 11 A1=A1>>>0xf; - 1a0: 83 c6 08 11 A1=A1>>>0x1f; - 1a4: 83 c6 00 10 A1=A1<<0x0; - 1a8: 83 c6 78 10 A1=A1<<0xf; - 1ac: 83 c6 f8 10 A1=A1<<0x1f; - 1b0: 00 40 R0>>>=R0; - 1b2: 08 40 R0>>>=R1; - 1b4: 01 40 R1>>>=R0; - 1b6: 39 40 R1>>>=R7; - 1b8: 80 40 R0<<=R0; - 1ba: 88 40 R0<<=R1; - 1bc: 81 40 R1<<=R0; - 1be: b9 40 R1<<=R7; - 1c0: 00 c6 38 16 R3.L= ASHIFT R0.H BY R7.L; - 1c4: 00 c6 38 26 R3.H= ASHIFT R0.L BY R7.L; - 1c8: 00 c6 38 36 R3.H= ASHIFT R0.H BY R7.L; - 1cc: 00 c6 38 06 R3.L= ASHIFT R0.L BY R7.L; - 1d0: 00 c6 38 56 R3.L= ASHIFT R0.H BY R7.L\(S\); - 1d4: 00 c6 38 66 R3.H= ASHIFT R0.L BY R7.L\(S\); - 1d8: 00 c6 38 76 R3.H= ASHIFT R0.H BY R7.L\(S\); - 1dc: 00 c6 38 46 R3.L= ASHIFT R0.L BY R7.L\(S\); - 1e0: 02 c6 3a 08 R4= ASHIFT R2 BY R7.L; - 1e4: 02 c6 3a 48 R4= ASHIFT R2 BY R7.L\(S\); - 1e8: 03 c6 38 00 A0= ASHIFT A0 BY R7.L; - 1ec: 03 c6 38 10 A1= ASHIFT A1 BY R7.L; - 1f0: 13 45 P3=P2>>1; - 1f2: db 44 P3=P3>>2; - 1f4: 2d 5b P4=P5<<1; - 1f6: 48 44 P0=P1<<2; - 1f8: 8b 4e R3>>=0x11; - 1fa: 8b 4f R3<<=0x11; + 120: 82 c6 00 00 R0 = R0 >>> 0x0; + 124: 82 c6 08 01 R0 = R0 >>> 0x1f; + 128: 82 c6 01 00 R0 = R1 >>> 0x0; + 12c: 82 c6 09 01 R0 = R1 >>> 0x1f; + 130: 82 c6 00 0e R7 = R0 >>> 0x0; + 134: 82 c6 09 0d R6 = R1 >>> 0x1f; + 138: 82 c6 02 0a R5 = R2 >>> 0x0; + 13c: 82 c6 0b 09 R4 = R3 >>> 0x1f; + 140: 82 c6 04 06 R3 = R4 >>> 0x0; + 144: 82 c6 0d 05 R2 = R5 >>> 0x1f; + 148: 82 c6 06 02 R1 = R6 >>> 0x0; + 14c: 82 c6 0f 01 R0 = R7 >>> 0x1f; + 150: 82 c6 00 40 R0 = R0 << 0x0 \(S\); + 154: 82 c6 f8 40 R0 = R0 << 0x1f \(S\); + 158: 82 c6 01 40 R0 = R1 << 0x0 \(S\); + 15c: 82 c6 f9 40 R0 = R1 << 0x1f \(S\); + 160: 82 c6 00 4e R7 = R0 << 0x0 \(S\); + 164: 82 c6 f9 4c R6 = R1 << 0x1f \(S\); + 168: 82 c6 02 4a R5 = R2 << 0x0 \(S\); + 16c: 82 c6 fb 48 R4 = R3 << 0x1f \(S\); + 170: 82 c6 04 46 R3 = R4 << 0x0 \(S\); + 174: 82 c6 fd 44 R2 = R5 << 0x1f \(S\); + 178: 82 c6 06 42 R1 = R6 << 0x0 \(S\); + 17c: 82 c6 ff 40 R0 = R7 << 0x1f \(S\); + 180: 83 c6 00 00 A0 = A0 << 0x0; + 184: 83 c6 88 01 A0 = A0 >>> 0xf; + 188: 83 c6 08 01 A0 = A0 >>> 0x1f; + 18c: 83 c6 00 00 A0 = A0 << 0x0; + 190: 83 c6 78 00 A0 = A0 << 0xf; + 194: 83 c6 f8 00 A0 = A0 << 0x1f; + 198: 83 c6 00 10 A1 = A1 << 0x0; + 19c: 83 c6 88 11 A1 = A1 >>> 0xf; + 1a0: 83 c6 08 11 A1 = A1 >>> 0x1f; + 1a4: 83 c6 00 10 A1 = A1 << 0x0; + 1a8: 83 c6 78 10 A1 = A1 << 0xf; + 1ac: 83 c6 f8 10 A1 = A1 << 0x1f; + 1b0: 00 40 R0 >>>= R0; + 1b2: 08 40 R0 >>>= R1; + 1b4: 01 40 R1 >>>= R0; + 1b6: 39 40 R1 >>>= R7; + 1b8: 80 40 R0 <<= R0; + 1ba: 88 40 R0 <<= R1; + 1bc: 81 40 R1 <<= R0; + 1be: b9 40 R1 <<= R7; + 1c0: 00 c6 38 16 R3.L = ASHIFT R0.H BY R7.L; + 1c4: 00 c6 38 26 R3.H = ASHIFT R0.L BY R7.L; + 1c8: 00 c6 38 36 R3.H = ASHIFT R0.H BY R7.L; + 1cc: 00 c6 38 06 R3.L = ASHIFT R0.L BY R7.L; + 1d0: 00 c6 38 56 R3.L = ASHIFT R0.H BY R7.L \(S\); + 1d4: 00 c6 38 66 R3.H = ASHIFT R0.L BY R7.L \(S\); + 1d8: 00 c6 38 76 R3.H = ASHIFT R0.H BY R7.L \(S\); + 1dc: 00 c6 38 46 R3.L = ASHIFT R0.L BY R7.L \(S\); + 1e0: 02 c6 3a 08 R4 = ASHIFT R2 BY R7.L; + 1e4: 02 c6 3a 48 R4 = ASHIFT R2 BY R7.L \(S\); + 1e8: 03 c6 38 00 A0 = ASHIFT A0 BY R7.L; + 1ec: 03 c6 38 10 A1 = ASHIFT A1 BY R7.L; + 1f0: 13 45 P3 = P2 >> 0x1; + 1f2: db 44 P3 = P3 >> 0x2; + 1f4: 2d 5b P4 = P5 << 0x1; + 1f6: 48 44 P0 = P1 << 0x2; + 1f8: 8b 4e R3 >>= 0x11; + 1fa: 8b 4f R3 <<= 0x11; 1fc: 80 c6 e0 87 R3.L = R0.L >> 0x4; 200: 80 c6 e0 97 R3.L = R0.H >> 0x4; 204: 80 c6 60 a6 R3.H = R0.L << 0xc; 208: 80 c6 70 b6 R3.H = R0.H << 0xe; - 20c: 82 c6 e6 87 R3=R6>>0x4; - 210: 82 c6 26 86 R3=R6<<0x4; - 214: 83 c6 c8 41 A0=A0>>0x7; - 218: 83 c6 38 51 A1=A1>>0x19; - 21c: 83 c6 38 00 A0=A0<<0x7; - 220: 83 c6 70 10 A1=A1<<0xe; - 224: 43 40 R3>>=R0; - 226: 8b 40 R3<<=R1; - 228: 00 c6 10 86 R3.L= LSHIFT R0.L BY R2.L; - 22c: 00 c6 10 a6 R3.H= LSHIFT R0.L BY R2.L; - 230: 03 c6 38 40 A0= LSHIFT A0 BY R7.L; - 234: 03 c6 38 50 A1= LSHIFT A1 BY R7.L; - 238: 82 c6 f9 c8 R4= ROT R1 BY 0x1f; - 23c: 82 c6 01 c9 R4= ROT R1 BY -32; - 240: 82 c6 29 c8 R4= ROT R1 BY 0x5; - 244: 83 c6 b0 80 A0= ROT A0 BY 0x16; - 248: 83 c6 00 81 A0= ROT A0 BY -32; - 24c: 83 c6 f8 80 A0= ROT A0 BY 0x1f; - 250: 83 c6 00 91 A1= ROT A1 BY -32; - 254: 83 c6 f8 90 A1= ROT A1 BY 0x1f; - 258: 83 c6 b0 90 A1= ROT A1 BY 0x16; - 25c: 02 c6 11 c8 R4= ROT R1 BY R2.L; - 260: 03 c6 18 80 A0= ROT A0 BY R3.L; - 264: 03 c6 38 90 A1= ROT A1 BY R7.L; + 20c: 82 c6 e6 87 R3 = R6 >> 0x4; + 210: 82 c6 26 86 R3 = R6 << 0x4; + 214: 83 c6 c8 41 A0 = A0 >> 0x7; + 218: 83 c6 38 51 A1 = A1 >> 0x19; + 21c: 83 c6 38 00 A0 = A0 << 0x7; + 220: 83 c6 70 10 A1 = A1 << 0xe; + 224: 43 40 R3 >>= R0; + 226: 8b 40 R3 <<= R1; + 228: 00 c6 10 86 R3.L = LSHIFT R0.L BY R2.L; + 22c: 00 c6 10 a6 R3.H = LSHIFT R0.L BY R2.L; + 230: 03 c6 38 40 A0 = LSHIFT A0 BY R7.L; + 234: 03 c6 38 50 A1 = LSHIFT A1 BY R7.L; + 238: 82 c6 f9 c8 R4 = ROT R1 BY 0x1f; + 23c: 82 c6 01 c9 R4 = ROT R1 BY -0x20; + 240: 82 c6 29 c8 R4 = ROT R1 BY 0x5; + 244: 83 c6 b0 80 A0 = ROT A0 BY 0x16; + 248: 83 c6 00 81 A0 = ROT A0 BY -0x20; + 24c: 83 c6 f8 80 A0 = ROT A0 BY 0x1f; + 250: 83 c6 00 91 A1 = ROT A1 BY -0x20; + 254: 83 c6 f8 90 A1 = ROT A1 BY 0x1f; + 258: 83 c6 b0 90 A1 = ROT A1 BY 0x16; + 25c: 02 c6 11 c8 R4 = ROT R1 BY R2.L; + 260: 03 c6 18 80 A0 = ROT A0 BY R3.L; + 264: 03 c6 38 90 A1 = ROT A1 BY R7.L; 268: 80 c6 01 80 R0.L = R1.L << 0x0; 26c: 80 c6 09 80 R0.L = R1.L << 0x1; 270: 80 c6 11 80 R0.L = R1.L << 0x2; diff --git a/gas/testsuite/gas/bfin/stack.d b/gas/testsuite/gas/bfin/stack.d index fd06754..b65d9c4 100644 --- a/gas/testsuite/gas/bfin/stack.d +++ b/gas/testsuite/gas/bfin/stack.d @@ -7,7 +7,7 @@ Disassembly of section .text: 0: 7a 01 \[--SP\] = SYSCFG; 2: 70 01 \[--SP\] = LC0; 4: 47 01 \[--SP\] = R7; - 6: 61 01 \[--SP\] = A0.w; + 6: 61 01 \[--SP\] = A0.W; 8: 76 01 \[--SP\] = CYCLES; a: 5a 01 \[--SP\] = B2; c: 55 01 \[--SP\] = M1; @@ -24,8 +24,8 @@ Disassembly of section .text: 1a: 10 01 I0 = \[SP\+\+\]; 1c: 39 01 SEQSTAT = \[SP\+\+\]; 1e: 1e 01 L2 = \[SP\+\+\]; - 20: 35 90 R5=\[SP\+\+\]; - 22: 77 90 FP=\[SP\+\+\]; + 20: 35 90 R5 = \[SP\+\+\]; + 22: 77 90 FP = \[SP\+\+\]; 00000024 <pop_multiple>: 24: a8 05 \(R7:5, P5:0\) = \[SP\+\+\]; @@ -33,9 +33,9 @@ Disassembly of section .text: 28: 84 04 \(P5:4\) = \[SP\+\+\]; 0000002a <link>: - 2a: 00 e8 02 00 LINK 0x8; - 2e: 00 e8 ff ff LINK 0x3fffc; - 32: 00 e8 01 80 LINK 0x20004; + 2a: 00 e8 02 00 LINK 0x8;.* + 2e: 00 e8 ff ff LINK 0x3fffc;.* + 32: 00 e8 01 80 LINK 0x20004;.* 00000036 <unlink>: 36: 01 e8 00 00 UNLINK; diff --git a/gas/testsuite/gas/bfin/stack2.d b/gas/testsuite/gas/bfin/stack2.d index 42a4b6d..d87b4ff 100644 --- a/gas/testsuite/gas/bfin/stack2.d +++ b/gas/testsuite/gas/bfin/stack2.d @@ -17,10 +17,10 @@ Disassembly of section .text: 12: 5d 01 \[--SP\] = L1; 14: 58 01 \[--SP\] = B0; 16: 59 01 \[--SP\] = B1; - 18: 60 01 \[--SP\] = A0.x; - 1a: 62 01 \[--SP\] = A1.x; - 1c: 61 01 \[--SP\] = A0.w; - 1e: 63 01 \[--SP\] = A1.w; + 18: 60 01 \[--SP\] = A0.X; + 1a: 62 01 \[--SP\] = A1.X; + 1c: 61 01 \[--SP\] = A0.W; + 1e: 63 01 \[--SP\] = A1.W; 20: 66 01 \[--SP\] = ASTAT; 22: 67 01 \[--SP\] = RETS; 24: 7b 01 \[--SP\] = RETI; @@ -41,10 +41,10 @@ Disassembly of section .text: 42: c0 05 \[--SP\] = \(R7:0, P5:0\); 44: 40 05 \[--SP\] = \(R7:0\); 46: c0 04 \[--SP\] = \(P5:0\); - 48: 30 90 R0=\[SP\+\+\]; - 4a: 36 90 R6=\[SP\+\+\]; - 4c: 70 90 P0=\[SP\+\+\]; - 4e: 74 90 P4=\[SP\+\+\]; + 48: 30 90 R0 = \[SP\+\+\]; + 4a: 36 90 R6 = \[SP\+\+\]; + 4c: 70 90 P0 = \[SP\+\+\]; + 4e: 74 90 P4 = \[SP\+\+\]; 50: 10 01 I0 = \[SP\+\+\]; 52: 11 01 I1 = \[SP\+\+\]; 54: 14 01 M0 = \[SP\+\+\]; @@ -53,10 +53,10 @@ Disassembly of section .text: 5a: 1d 01 L1 = \[SP\+\+\]; 5c: 18 01 B0 = \[SP\+\+\]; 5e: 19 01 B1 = \[SP\+\+\]; - 60: 20 01 A0.x = \[SP\+\+\]; - 62: 22 01 A1.x = \[SP\+\+\]; - 64: 21 01 A0.w = \[SP\+\+\]; - 66: 23 01 A1.w = \[SP\+\+\]; + 60: 20 01 A0.X = \[SP\+\+\]; + 62: 22 01 A1.X = \[SP\+\+\]; + 64: 21 01 A0.W = \[SP\+\+\]; + 66: 23 01 A1.W = \[SP\+\+\]; 68: 26 01 ASTAT = \[SP\+\+\]; 6a: 27 01 RETS = \[SP\+\+\]; 6c: 3b 01 RETI = \[SP\+\+\]; @@ -77,7 +77,7 @@ Disassembly of section .text: 8a: 80 05 \(R7:0, P5:0\) = \[SP\+\+\]; 8c: 00 05 \(R7:0\) = \[SP\+\+\]; 8e: 80 04 \(P5:0\) = \[SP\+\+\]; - 90: 00 e8 00 00 LINK 0x0; - 94: 00 e8 02 00 LINK 0x8; - 98: 00 e8 ff ff LINK 0x3fffc; + 90: 00 e8 00 00 LINK 0x0;.* + 94: 00 e8 02 00 LINK 0x8;.* + 98: 00 e8 ff ff LINK 0x3fffc;.* 9c: 01 e8 00 00 UNLINK; diff --git a/gas/testsuite/gas/bfin/store.d b/gas/testsuite/gas/bfin/store.d index 0e553c1..d65ad62 100644 --- a/gas/testsuite/gas/bfin/store.d +++ b/gas/testsuite/gas/bfin/store.d @@ -4,52 +4,52 @@ Disassembly of section .text: 00000000 <store_pointer_register>: - 0: 78 93 \[FP\]=P0; - 2: 71 92 \[SP\+\+\]=P1; - 4: fd 92 \[FP--\]=P5; - 6: d6 bf \[P2\+0x3c\]=SP; - 8: 28 e7 ff 7f \[P5\+0x1fffc\]=P0; - c: 3a bc \[FP\+0x0\]=P2; - e: f9 bb \[FP-4\]=P1; - 10: 08 ba \[FP-128\]=P0; + 0: 78 93 \[FP\] = P0; + 2: 71 92 \[SP\+\+\] = P1; + 4: fd 92 \[FP--\] = P5; + 6: d6 bf \[P2 \+ 0x3c\] = SP; + 8: 28 e7 ff 7f \[P5 \+ 0x1fffc\] = P0; + c: 3a bc \[FP \+ 0x0\] = P2; + e: f9 bb \[FP -0x4\] = P1; + 10: 08 ba \[FP -0x80\] = P0; 00000012 <store_data_register>: - 12: 10 93 \[P2\]=R0; - 14: 2a 92 \[P5\+\+\]=R2; - 16: bf 92 \[FP--\]=R7; - 18: b5 b3 \[SP\+0x38\]=R5; - 1a: 33 e6 fc 3b \[SP\+0xeff0\]=R3; - 1e: 38 e6 01 c0 \[FP\+-65532\]=R0; - 22: 4f 88 \[FP\+\+P1\]=R1; - 24: 86 ba \[FP-96\]=R6; - 26: 01 9f \[I0\]=R1; - 28: 12 9e \[I2\+\+\]=R2; - 2a: 9c 9e \[I3--\]=R4; - 2c: 8f 9f \[I1\+\+M0\]=R7; + 12: 10 93 \[P2\] = R0; + 14: 2a 92 \[P5\+\+\] = R2; + 16: bf 92 \[FP--\] = R7; + 18: b5 b3 \[SP \+ 0x38\] = R5; + 1a: 33 e6 fc 3b \[SP \+ 0xeff0\] = R3; + 1e: 38 e6 01 c0 \[FP \+ -0xfffc\] = R0; + 22: 4f 88 \[FP \+\+ P1\] = R1; + 24: 86 ba \[FP -0x60\] = R6; + 26: 01 9f \[I0\] = R1; + 28: 12 9e \[I2\+\+\] = R2; + 2a: 9c 9e \[I3--\] = R4; + 2c: 8f 9f \[I1 \+\+ M0\] = R7; 0000002e <store_data_register_half>: - 2e: 5c 9f W\[I3\]=R4.H; - 30: 40 9e W\[I0\+\+\]=R0.H; - 32: d7 9e W\[I2--\]=R7.H; - 34: b6 8d W\[SP\]=R6.H; - 36: 07 8d W\[FP\+\+P0\]=R4.H; + 2e: 5c 9f W\[I3\] = R4.H; + 30: 40 9e W\[I0\+\+\] = R0.H; + 32: d7 9e W\[I2--\] = R7.H; + 34: b6 8d W\[SP\] = R6.H; + 36: 07 8d W\[FP \+\+ P0\] = R4.H; 00000038 <store_low_data_register_half>: - 38: 20 9f W\[I0\]=R0.L; - 3a: 2f 9e W\[I1\+\+\]=R7.L; - 3c: b1 9e W\[I2--\]=R1.L; - 3e: b6 8a W\[SP\]=R2.L; - 40: 13 97 W\[P2\]=R3; - 42: 1d 96 W\[P3\+\+\]=R5; - 44: bc 96 W\[FP--\]=R4; - 46: cf b7 W\[P1\+0x1e\]=R7; - 48: 56 e6 ff 7f W\[P2\+0xfffe\]=R6; - 4c: 79 e6 98 a1 W\[FP\+-48336\]=R1; - 50: 56 8b W\[SP\+\+P2\]=R5.L; + 38: 20 9f W\[I0\] = R0.L; + 3a: 2f 9e W\[I1\+\+\] = R7.L; + 3c: b1 9e W\[I2--\] = R1.L; + 3e: b6 8a W\[SP\] = R2.L; + 40: 13 97 W\[P2\] = R3; + 42: 1d 96 W\[P3\+\+\] = R5; + 44: bc 96 W\[FP--\] = R4; + 46: cf b7 W\[P1 \+ 0x1e\] = R7; + 48: 56 e6 ff 7f W\[P2 \+ 0xfffe\] = R6; + 4c: 79 e6 98 a1 W\[FP \+ -0xbcd0\] = R1; + 50: 56 8b W\[SP \+\+ P2\] = R5.L; 00000052 <store_byte>: - 52: 39 9b B\[FP\]=R1; - 54: 00 9a B\[P0\+\+\]=R0; - 56: ba 9a B\[FP--\]=R2; - 58: 97 e6 19 00 B\[P2\+0x19\]=R7; - 5c: be e6 01 80 B\[FP\+-32767\]=R6; + 52: 39 9b B\[FP\] = R1; + 54: 00 9a B\[P0\+\+\] = R0; + 56: ba 9a B\[FP--\] = R2; + 58: 97 e6 19 00 B\[P2 \+ 0x19\] = R7; + 5c: be e6 01 80 B\[FP \+ -0x7fff\] = R6; diff --git a/gas/testsuite/gas/bfin/vector.d b/gas/testsuite/gas/bfin/vector.d index fd8bd0a..169c9da 100644 --- a/gas/testsuite/gas/bfin/vector.d +++ b/gas/testsuite/gas/bfin/vector.d @@ -5,54 +5,54 @@ Disassembly of section .text: 00000000 <add_on_sign>: - 0: 0c c4 0d 08 R4.H=R4.L=SIGN\(R1.H\)\*R5.H\+SIGN\(R1.L\)\*R5.L\); + 0: 0c c4 0d 08 R4.H = R4.L = SIGN \(R1.H\) \* R5.H \+ SIGN \(R1.L\) \* R5.L; 00000004 <vit_max>: - 4: 09 c6 15 8e R7=VIT_MAX\(R5,R2\)\(ASL\); - 8: 09 c6 30 c0 R0=VIT_MAX\(R0,R6\)\(ASR\); - c: 09 c6 03 0a R5.L=VIT_MAX \(R3\) \(ASL\); - 10: 09 c6 02 44 R2.L=VIT_MAX \(R2\) \(ASR\); + 4: 09 c6 15 8e R7 = VIT_MAX \(R5, R2\) \(ASL\); + 8: 09 c6 30 c0 R0 = VIT_MAX \(R0, R6\) \(ASR\); + c: 09 c6 03 0a R5.L = VIT_MAX \(R3\) \(ASL\); + 10: 09 c6 02 44 R2.L = VIT_MAX \(R2\) \(ASR\); 00000014 <vector_abs>: - 14: 06 c4 28 8a R5= ABS R5\(V\); - 18: 06 c4 00 84 R2= ABS R0\(V\); + 14: 06 c4 28 8a R5 = ABS R5 \(V\); + 18: 06 c4 00 84 R2 = ABS R0 \(V\); 0000001c <vector_add_sub>: - 1c: 00 c4 1a 0a R5=R3\+\|\+R2 ; - 20: 00 c4 1a 3a R5=R3\+\|\+R2 \(SCO\); - 24: 00 c4 06 8e R7=R0-\|\+R6 ; - 28: 00 c4 0b a4 R2=R1-\|\+R3 \(S\); - 2c: 00 c4 02 48 R4=R0\+\|-R2 ; - 30: 00 c4 0a 5a R5=R1\+\|-R2 \(CO\); - 34: 00 c4 1c cc R6=R3-\|-R4 ; - 38: 00 c4 2e de R7=R5-\|-R6 \(CO\); - 3c: 01 c4 63 bf R5=R4\+\|\+R3,R7=R4-\|-R3\(SCO,ASR\); - 40: 01 c4 1e c2 R0=R3\+\|\+R6,R1=R3-\|-R6\(ASL\); - 44: 21 c4 ca 2d R7=R1\+\|-R2,R6=R1-\|\+R2\(S\); - 48: 21 c4 53 0a R1=R2\+\|-R3,R5=R2-\|\+R3; - 4c: 04 c4 41 8d R5=R0\+R1,R6=R0-R1 \(NS\); - 50: 04 c4 39 a6 R0=R7\+R1,R3=R7-R1 \(S\); - 54: 11 c4 [c-f][[:xdigit:]] 0b R7=A1\+A0,R5=A1-A0 \(NS\); - 58: 11 c4 [c-f][[:xdigit:]] 6c R3=A0\+A1,R6=A0-A1 \(S\); + 1c: 00 c4 1a 0a R5 = R3 \+\|\+ R2; + 20: 00 c4 1a 3a R5 = R3 \+\|\+ R2 \(SCO\); + 24: 00 c4 06 8e R7 = R0 -\|\+ R6; + 28: 00 c4 0b a4 R2 = R1 -\|\+ R3 \(S\); + 2c: 00 c4 02 48 R4 = R0 \+\|- R2; + 30: 00 c4 0a 5a R5 = R1 \+\|- R2 \(CO\); + 34: 00 c4 1c cc R6 = R3 -\|- R4; + 38: 00 c4 2e de R7 = R5 -\|- R6 \(CO\); + 3c: 01 c4 63 bf R5 = R4 \+\|\+ R3, R7 = R4 -\|- R3 \(SCO, ASR\); + 40: 01 c4 1e c2 R0 = R3 \+\|\+ R6, R1 = R3 -\|- R6 \(ASL\); + 44: 21 c4 ca 2d R7 = R1 \+\|- R2, R6 = R1 -\|\+ R2 \(S\); + 48: 21 c4 53 0a R1 = R2 \+\|- R3, R5 = R2 -\|\+ R3; + 4c: 04 c4 41 8d R5 = R0 \+ R1, R6 = R0 - R1 \(NS\); + 50: 04 c4 39 a6 R0 = R7 \+ R1, R3 = R7 - R1 \(S\); + 54: 11 c4 [c-f][[:xdigit:]] 0b R7 = A1 \+ A0, R5 = A1 - A0 \(NS\); + 58: 11 c4 [c-f][[:xdigit:]] 6c R3 = A0 \+ A1, R6 = A0 - A1 \(S\); 0000005c <vector_ashift>: - 5c: 81 c6 8b 03 R1=R3>>>0xf \(V\); - 60: 81 c6 e0 09 R4=R0>>>0x4 \(V\); - 64: 81 c6 00 4a R5=R0<<0x0 \(V, S\); - 68: 81 c6 62 44 R2=R2<<0xc \(V, S\); - 6c: 01 c6 15 0e R7= ASHIFT R5 BY R2.L\(V\); - 70: 01 c6 02 40 R0= ASHIFT R2 BY R0.L\(V,S\); + 5c: 81 c6 8b 03 R1 = R3 >>> 0xf \(V\); + 60: 81 c6 e0 09 R4 = R0 >>> 0x4 \(V\); + 64: 81 c6 00 4a R5 = R0 << 0x0 \(V, S\); + 68: 81 c6 62 44 R2 = R2 << 0xc \(V, S\); + 6c: 01 c6 15 0e R7 = ASHIFT R5 BY R2.L \(V\); + 70: 01 c6 02 40 R0 = ASHIFT R2 BY R0.L \(V, S\); 00000074 <vector_lshift>: - 74: 81 c6 8a 8b R5=R2 >> 0xf \(V\); - 78: 81 c6 11 80 R0=R1<<0x2 \(V\); - 7c: 01 c6 11 88 R4=SHIFT R1 BY R2.L\(V\); + 74: 81 c6 8a 8b R5 = R2 >> 0xf \(V\); + 78: 81 c6 11 80 R0 = R1 << 0x2 \(V\); + 7c: 01 c6 11 88 R4 = SHIFT R1 BY R2.L \(V\); 00000080 <vector_max>: - 80: 06 c4 01 0c R6=MAX\(R0,R1\)\(V\); + 80: 06 c4 01 0c R6 = MAX \(R0, R1\) \(V\); 00000084 <vector_min>: - 84: 06 c4 17 40 R0=MIN\(R2,R7\)\(V\); + 84: 06 c4 17 40 R0 = MIN \(R2, R7\) \(V\); 00000088 <vector_mul>: 88: 04 c2 be 66 R2.H = R7.L \* R6.H, R2 = R7.H \* R6.H; @@ -63,43 +63,43 @@ Disassembly of section .text: 9c: 0c c2 95 27 R7 = R2.L \* R5.L, R6 = R2.H \* R5.H; a0: 24 c3 3e e0 R0.H = R7.H \* R6.H, R0 = R7.L \* R6.L \(ISS2\); a4: 04 c3 c1 e0 R3.H = R0.H \* R1.H, R3 = R0.L \* R1.L \(IS\); - a8: 00 c0 13 46 a1 = R2.L \* R3.H, a0 = R2.H \* R3.H; - ac: 01 c0 08 c0 a1 \+= R1.H \* R0.H, a0 = R1.L \* R0.L; - b0: 60 c0 2f c8 a1 = R5.H \* R7.H, a0 \+= R5.L \* R7.L \(W32\); - b4: 01 c1 01 c0 a1 \+= R0.H \* R1.H, a0 = R0.L \* R1.L \(IS\); - b8: 90 c0 1c c8 a1 = R3.H \* R4.H \(M\), a0 \+= R3.L \* R4.L \(FU\); - bc: 01 c0 24 96 a1 \+= R4.H \* R4.L, a0 -= R4.H \* R4.H; - c0: 25 c1 3e e8 R0.H = \(a1 \+= R7.H \* R6.H\), R0.L = \(a0 \+= R7.L \* R6.L\) \(ISS2\); - c4: 27 c0 81 28 R2.H = A1, R2.L = \(a0 \+= R0.L \* R1.L\) \(S2RND\); - c8: 04 c0 d1 c9 R7.H = \(a1 = R2.H \* R1.H\), a0 \+= R2.L \* R1.L; - cc: 04 c0 be 66 R2.H = \(a1 = R7.L \* R6.H\), R2.L = \(a0 = R7.H \* R6.H\); - d0: 05 c0 9a e1 R6.H = \(a1 \+= R3.H \* R2.H\), R6.L = \(a0 = R3.L \* R2.L\); - d4: 05 c0 f5 a7 R7.H = \(a1 \+= R6.H \* R5.L\), R7.L = \(a0 = R6.H \* R5.H\); - d8: 14 c0 3c a8 R0.H = \(a1 = R7.H \* R4.L\) \(M\), R0.L = \(a0 \+= R7.L \* R4.L\); - dc: 94 c0 5a e9 R5.H = \(a1 = R3.H \* R2.H\) \(M\), R5.L = \(a0 \+= R3.L \* R2.L\) \(FU\); - e0: 05 c1 1a e0 R0.H = \(a1 \+= R3.H \* R2.H\), R0.L = \(a0 = R3.L \* R2.L\) \(IS\); - e4: 1c c0 b7 d0 R3 = \(a1 = R6.H \* R7.H\) \(M\), a0 -= R6.L \* R7.L; - e8: 1c c0 3c 2e R1 = \(a1 = R7.L \* R4.L\) \(M\), R0 = \(a0 \+= R7.H \* R4.H\); - ec: 2d c1 3e e8 R1 = \(a1 \+= R7.H \* R6.H\), R0 = \(a0 \+= R7.L \* R6.L\) \(ISS2\); - f0: 0d c0 37 e1 R5 = \(a1 \+= R6.H \* R7.H\), R4 = \(a0 = R6.L \* R7.L\); - f4: 0d c0 9d f1 R7 = \(a1 \+= R3.H \* R5.H\), R6 = \(a0 -= R3.L \* R5.L\); - f8: 0e c0 37 c9 R5 = \(a1 -= R6.H \* R7.H\), a0 \+= R6.L \* R7.L; - fc: 0c c0 b7 e0 R3 = \(a1 = R6.H \* R7.H\), R2 = \(a0 = R6.L \* R7.L\); - 100: 9c c0 1f e9 R5 = \(a1 = R3.H \* R7.H\) \(M\), R4 = \(a0 \+= R3.L \* R7.L\) \(FU\); - 104: 2f c0 81 28 R3 = A1, R2 = \(a0 \+= R0.L \* R1.L\) \(S2RND\); - 108: 0d c1 1a e0 R1 = \(a1 \+= R3.H \* R2.H\), R0 = \(a0 = R3.L \* R2.L\) \(IS\); + a8: 00 c0 13 46 A1 = R2.L \* R3.H, A0 = R2.H \* R3.H; + ac: 01 c0 08 c0 A1 \+= R1.H \* R0.H, A0 = R1.L \* R0.L; + b0: 60 c0 2f c8 A1 = R5.H \* R7.H, A0 \+= R5.L \* R7.L \(W32\); + b4: 01 c1 01 c0 A1 \+= R0.H \* R1.H, A0 = R0.L \* R1.L \(IS\); + b8: 90 c0 1c c8 A1 = R3.H \* R4.H \(M\), A0 \+= R3.L \* R4.L \(FU\); + bc: 01 c0 24 96 A1 \+= R4.H \* R4.L, A0 -= R4.H \* R4.H; + c0: 25 c1 3e e8 R0.H = \(A1 \+= R7.H \* R6.H\), R0.L = \(A0 \+= R7.L \* R6.L\) \(ISS2\); + c4: 27 c0 81 28 R2.H = A1, R2.L = \(A0 \+= R0.L \* R1.L\) \(S2RND\); + c8: 04 c0 d1 c9 R7.H = \(A1 = R2.H \* R1.H\), A0 \+= R2.L \* R1.L; + cc: 04 c0 be 66 R2.H = \(A1 = R7.L \* R6.H\), R2.L = \(A0 = R7.H \* R6.H\); + d0: 05 c0 9a e1 R6.H = \(A1 \+= R3.H \* R2.H\), R6.L = \(A0 = R3.L \* R2.L\); + d4: 05 c0 f5 a7 R7.H = \(A1 \+= R6.H \* R5.L\), R7.L = \(A0 = R6.H \* R5.H\); + d8: 14 c0 3c a8 R0.H = \(A1 = R7.H \* R4.L\) \(M\), R0.L = \(A0 \+= R7.L \* R4.L\); + dc: 94 c0 5a e9 R5.H = \(A1 = R3.H \* R2.H\) \(M\), R5.L = \(A0 \+= R3.L \* R2.L\) \(FU\); + e0: 05 c1 1a e0 R0.H = \(A1 \+= R3.H \* R2.H\), R0.L = \(A0 = R3.L \* R2.L\) \(IS\); + e4: 1c c0 b7 d0 R3 = \(A1 = R6.H \* R7.H\) \(M\), A0 -= R6.L \* R7.L; + e8: 1c c0 3c 2e R1 = \(A1 = R7.L \* R4.L\) \(M\), R0 = \(A0 \+= R7.H \* R4.H\); + ec: 2d c1 3e e8 R1 = \(A1 \+= R7.H \* R6.H\), R0 = \(A0 \+= R7.L \* R6.L\) \(ISS2\); + f0: 0d c0 37 e1 R5 = \(A1 \+= R6.H \* R7.H\), R4 = \(A0 = R6.L \* R7.L\); + f4: 0d c0 9d f1 R7 = \(A1 \+= R3.H \* R5.H\), R6 = \(A0 -= R3.L \* R5.L\); + f8: 0e c0 37 c9 R5 = \(A1 -= R6.H \* R7.H\), A0 \+= R6.L \* R7.L; + fc: 0c c0 b7 e0 R3 = \(A1 = R6.H \* R7.H\), R2 = \(A0 = R6.L \* R7.L\); + 100: 9c c0 1f e9 R5 = \(A1 = R3.H \* R7.H\) \(M\), R4 = \(A0 \+= R3.L \* R7.L\) \(FU\); + 104: 2f c0 81 28 R3 = A1, R2 = \(A0 \+= R0.L \* R1.L\) \(S2RND\); + 108: 0d c1 1a e0 R1 = \(A1 \+= R3.H \* R2.H\), R0 = \(A0 = R3.L \* R2.L\) \(IS\); 0000010c <vector_negate>: - 10c: 0f c4 08 c0 R0=-R1\(V\); - 110: 0f c4 10 ce R7=-R2\(V\); + 10c: 0f c4 08 c0 R0 = -R1 \(V\); + 110: 0f c4 10 ce R7 = -R2 \(V\); 00000114 <vector_pack>: - 114: 04 c6 08 8e R7=PACK\(R0.H,R1.L\); - 118: 04 c6 31 cc R6=PACK\(R1.H,R6.H\); - 11c: 04 c6 12 4a R5=PACK\(R2.L,R2.H\); + 114: 04 c6 08 8e R7 = PACK \(R0.H, R1.L\); + 118: 04 c6 31 cc R6 = PACK \(R1.H, R6.H\); + 11c: 04 c6 12 4a R5 = PACK \(R2.L, R2.H\); 00000120 <vector_search>: - 120: 0d c4 10 82 \(R0,R1\) = SEARCH R2\(LT\); - 124: 0d c4 80 cf \(R6,R7\) = SEARCH R0\(LE\); - 128: 0d c4 c8 0c \(R3,R6\) = SEARCH R1\(GT\); - 12c: 0d c4 18 4b \(R4,R5\) = SEARCH R3\(GE\); + 120: 0d c4 10 82 \(R0, R1\) = SEARCH R2 \(LT\); + 124: 0d c4 80 cf \(R6, R7\) = SEARCH R0 \(LE\); + 128: 0d c4 c8 0c \(R3, R6\) = SEARCH R1 \(GT\); + 12c: 0d c4 18 4b \(R4, R5\) = SEARCH R3 \(GE\); diff --git a/gas/testsuite/gas/bfin/vector2.d b/gas/testsuite/gas/bfin/vector2.d index b71cb56..d4746ca 100644 --- a/gas/testsuite/gas/bfin/vector2.d +++ b/gas/testsuite/gas/bfin/vector2.d @@ -5,475 +5,476 @@ Disassembly of section .text: 00000000 <.text>: - 0: 0c c4 13 0e R7.H=R7.L=SIGN\(R2.H\)\*R3.H\+SIGN\(R2.L\)\*R3.L\); - 4: 0c c4 0a 00 R0.H=R0.L=SIGN\(R1.H\)\*R2.H\+SIGN\(R1.L\)\*R2.L\); - 8: 0c c4 25 06 R3.H=R3.L=SIGN\(R4.H\)\*R5.H\+SIGN\(R4.L\)\*R5.L\); - c: 0c c4 38 0c R6.H=R6.L=SIGN\(R7.H\)\*R0.H\+SIGN\(R7.L\)\*R0.L\); - 10: 0c c4 13 02 R1.H=R1.L=SIGN\(R2.H\)\*R3.H\+SIGN\(R2.L\)\*R3.L\); - 14: 0c c4 2e 08 R4.H=R4.L=SIGN\(R5.H\)\*R6.H\+SIGN\(R5.L\)\*R6.L\); - 18: 0c c4 01 0e R7.H=R7.L=SIGN\(R0.H\)\*R1.H\+SIGN\(R0.L\)\*R1.L\); - 1c: 0c c4 1c 04 R2.H=R2.L=SIGN\(R3.H\)\*R4.H\+SIGN\(R3.L\)\*R4.L\); - 20: 09 c6 13 8a R5=VIT_MAX\(R3,R2\)\(ASL\); - 24: 09 c6 01 ce R7=VIT_MAX\(R1,R0\)\(ASR\); - 28: 09 c6 11 80 R0=VIT_MAX\(R1,R2\)\(ASL\); - 2c: 09 c6 2c c6 R3=VIT_MAX\(R4,R5\)\(ASR\); - 30: 09 c6 07 8c R6=VIT_MAX\(R7,R0\)\(ASL\); - 34: 09 c6 1a c2 R1=VIT_MAX\(R2,R3\)\(ASR\); - 38: 09 c6 35 88 R4=VIT_MAX\(R5,R6\)\(ASL\); - 3c: 09 c6 08 ce R7=VIT_MAX\(R0,R1\)\(ASR\); - 40: 09 c6 23 84 R2=VIT_MAX\(R3,R4\)\(ASL\); - 44: 09 c6 3e ca R5=VIT_MAX\(R6,R7\)\(ASR\); - 48: 09 c6 01 06 R3.L=VIT_MAX \(R1\) \(ASL\); - 4c: 09 c6 01 46 R3.L=VIT_MAX \(R1\) \(ASR\); - 50: 09 c6 01 00 R0.L=VIT_MAX \(R1\) \(ASL\); - 54: 09 c6 03 44 R2.L=VIT_MAX \(R3\) \(ASR\); - 58: 09 c6 05 08 R4.L=VIT_MAX \(R5\) \(ASL\); - 5c: 09 c6 07 4c R6.L=VIT_MAX \(R7\) \(ASR\); - 60: 09 c6 02 02 R1.L=VIT_MAX \(R2\) \(ASL\); - 64: 09 c6 04 46 R3.L=VIT_MAX \(R4\) \(ASR\); - 68: 09 c6 06 0a R5.L=VIT_MAX \(R6\) \(ASL\); - 6c: 09 c6 00 4e R7.L=VIT_MAX \(R0\) \(ASR\); - 70: 06 c4 08 86 R3= ABS R1\(V\); - 74: 06 c4 00 80 R0= ABS R0\(V\); - 78: 06 c4 08 80 R0= ABS R1\(V\); - 7c: 06 c4 18 84 R2= ABS R3\(V\); - 80: 06 c4 28 88 R4= ABS R5\(V\); - 84: 06 c4 38 8c R6= ABS R7\(V\); - 88: 06 c4 00 82 R1= ABS R0\(V\); - 8c: 06 c4 10 86 R3= ABS R2\(V\); - 90: 06 c4 20 8a R5= ABS R4\(V\); - 94: 06 c4 30 8e R7= ABS R6\(V\); - 98: 00 c4 1c 0a R5=R3\+\|\+R4 ; - 9c: 00 c4 0a 00 R0=R1\+\|\+R2 ; - a0: 00 c4 25 06 R3=R4\+\|\+R5 ; - a4: 00 c4 38 0c R6=R7\+\|\+R0 ; - a8: 00 c4 13 02 R1=R2\+\|\+R3 ; - ac: 00 c4 1d 08 R4=R3\+\|\+R5 ; - b0: 00 c4 1f 0c R6=R3\+\|\+R7 ; - b4: 00 c4 0a 20 R0=R1\+\|\+R2 \(S\); - b8: 00 c4 25 26 R3=R4\+\|\+R5 \(S\); - bc: 00 c4 38 2c R6=R7\+\|\+R0 \(S\); - c0: 00 c4 13 22 R1=R2\+\|\+R3 \(S\); - c4: 00 c4 1d 28 R4=R3\+\|\+R5 \(S\); - c8: 00 c4 1f 2c R6=R3\+\|\+R7 \(S\); - cc: 00 c4 0a 10 R0=R1\+\|\+R2 \(CO\); - d0: 00 c4 25 16 R3=R4\+\|\+R5 \(CO\); - d4: 00 c4 38 1c R6=R7\+\|\+R0 \(CO\); - d8: 00 c4 13 12 R1=R2\+\|\+R3 \(CO\); - dc: 00 c4 1d 18 R4=R3\+\|\+R5 \(CO\); - e0: 00 c4 1f 1c R6=R3\+\|\+R7 \(CO\); - e4: 00 c4 0a 30 R0=R1\+\|\+R2 \(SCO\); - e8: 00 c4 25 36 R3=R4\+\|\+R5 \(SCO\); - ec: 00 c4 38 3c R6=R7\+\|\+R0 \(SCO\); - f0: 00 c4 13 32 R1=R2\+\|\+R3 \(SCO\); - f4: 00 c4 1d 38 R4=R3\+\|\+R5 \(SCO\); - f8: 00 c4 1f 3c R6=R3\+\|\+R7 \(SCO\); - fc: 00 c4 01 ac R6=R0-\|\+R1 \(S\); - 100: 00 c4 0a 80 R0=R1-\|\+R2 ; - 104: 00 c4 25 86 R3=R4-\|\+R5 ; - 108: 00 c4 38 8c R6=R7-\|\+R0 ; - 10c: 00 c4 13 82 R1=R2-\|\+R3 ; - 110: 00 c4 1d 88 R4=R3-\|\+R5 ; - 114: 00 c4 1f 8c R6=R3-\|\+R7 ; - 118: 00 c4 0a a0 R0=R1-\|\+R2 \(S\); - 11c: 00 c4 25 a6 R3=R4-\|\+R5 \(S\); - 120: 00 c4 38 ac R6=R7-\|\+R0 \(S\); - 124: 00 c4 13 a2 R1=R2-\|\+R3 \(S\); - 128: 00 c4 1d a8 R4=R3-\|\+R5 \(S\); - 12c: 00 c4 1f ac R6=R3-\|\+R7 \(S\); - 130: 00 c4 0a 90 R0=R1-\|\+R2 \(CO\); - 134: 00 c4 25 96 R3=R4-\|\+R5 \(CO\); - 138: 00 c4 38 9c R6=R7-\|\+R0 \(CO\); - 13c: 00 c4 13 92 R1=R2-\|\+R3 \(CO\); - 140: 00 c4 1d 98 R4=R3-\|\+R5 \(CO\); - 144: 00 c4 1f 9c R6=R3-\|\+R7 \(CO\); - 148: 00 c4 0a b0 R0=R1-\|\+R2 \(SCO\); - 14c: 00 c4 25 b6 R3=R4-\|\+R5 \(SCO\); - 150: 00 c4 38 bc R6=R7-\|\+R0 \(SCO\); - 154: 00 c4 13 b2 R1=R2-\|\+R3 \(SCO\); - 158: 00 c4 1d b8 R4=R3-\|\+R5 \(SCO\); - 15c: 00 c4 1f bc R6=R3-\|\+R7 \(SCO\); - 160: 00 c4 11 50 R0=R2\+\|-R1 \(CO\); - 164: 00 c4 0a 40 R0=R1\+\|-R2 ; - 168: 00 c4 25 46 R3=R4\+\|-R5 ; - 16c: 00 c4 38 4c R6=R7\+\|-R0 ; - 170: 00 c4 13 42 R1=R2\+\|-R3 ; - 174: 00 c4 1d 48 R4=R3\+\|-R5 ; - 178: 00 c4 1f 4c R6=R3\+\|-R7 ; - 17c: 00 c4 0a 60 R0=R1\+\|-R2 \(S\); - 180: 00 c4 25 66 R3=R4\+\|-R5 \(S\); - 184: 00 c4 38 6c R6=R7\+\|-R0 \(S\); - 188: 00 c4 13 62 R1=R2\+\|-R3 \(S\); - 18c: 00 c4 1d 68 R4=R3\+\|-R5 \(S\); - 190: 00 c4 1f 6c R6=R3\+\|-R7 \(S\); - 194: 00 c4 0a 50 R0=R1\+\|-R2 \(CO\); - 198: 00 c4 25 56 R3=R4\+\|-R5 \(CO\); - 19c: 00 c4 38 5c R6=R7\+\|-R0 \(CO\); - 1a0: 00 c4 13 52 R1=R2\+\|-R3 \(CO\); - 1a4: 00 c4 1d 58 R4=R3\+\|-R5 \(CO\); - 1a8: 00 c4 1f 5c R6=R3\+\|-R7 \(CO\); - 1ac: 00 c4 0a 70 R0=R1\+\|-R2 \(SCO\); - 1b0: 00 c4 25 76 R3=R4\+\|-R5 \(SCO\); - 1b4: 00 c4 38 7c R6=R7\+\|-R0 \(SCO\); - 1b8: 00 c4 13 72 R1=R2\+\|-R3 \(SCO\); - 1bc: 00 c4 1d 78 R4=R3\+\|-R5 \(SCO\); - 1c0: 00 c4 1f 7c R6=R3\+\|-R7 \(SCO\); - 1c4: 00 c4 1e fe R7=R3-\|-R6 \(SCO\); - 1c8: 00 c4 0a c0 R0=R1-\|-R2 ; - 1cc: 00 c4 25 c6 R3=R4-\|-R5 ; - 1d0: 00 c4 38 cc R6=R7-\|-R0 ; - 1d4: 00 c4 13 c2 R1=R2-\|-R3 ; - 1d8: 00 c4 1d c8 R4=R3-\|-R5 ; - 1dc: 00 c4 1f cc R6=R3-\|-R7 ; - 1e0: 00 c4 0a e0 R0=R1-\|-R2 \(S\); - 1e4: 00 c4 25 e6 R3=R4-\|-R5 \(S\); - 1e8: 00 c4 38 ec R6=R7-\|-R0 \(S\); - 1ec: 00 c4 13 e2 R1=R2-\|-R3 \(S\); - 1f0: 00 c4 1d e8 R4=R3-\|-R5 \(S\); - 1f4: 00 c4 1f ec R6=R3-\|-R7 \(S\); - 1f8: 00 c4 0a d0 R0=R1-\|-R2 \(CO\); - 1fc: 00 c4 25 d6 R3=R4-\|-R5 \(CO\); - 200: 00 c4 38 dc R6=R7-\|-R0 \(CO\); - 204: 00 c4 13 d2 R1=R2-\|-R3 \(CO\); - 208: 00 c4 1d d8 R4=R3-\|-R5 \(CO\); - 20c: 00 c4 1f dc R6=R3-\|-R7 \(CO\); - 210: 00 c4 0a f0 R0=R1-\|-R2 \(SCO\); - 214: 00 c4 25 f6 R3=R4-\|-R5 \(SCO\); - 218: 00 c4 38 fc R6=R7-\|-R0 \(SCO\); - 21c: 00 c4 13 f2 R1=R2-\|-R3 \(SCO\); - 220: 00 c4 1d f8 R4=R3-\|-R5 \(SCO\); - 224: 00 c4 1f fc R6=R3-\|-R7 \(SCO\); - 228: 01 c4 5c 0f R5=R3\+\|\+R4,R7=R3-\|-R4; - 22c: 01 c4 0a 0e R0=R1\+\|\+R2,R7=R1-\|-R2; - 230: 01 c4 e5 0c R3=R4\+\|\+R5,R6=R4-\|-R5; - 234: 01 c4 b8 0b R6=R7\+\|\+R0,R5=R7-\|-R0; - 238: 01 c4 53 08 R1=R2\+\|\+R3,R4=R2-\|-R3; - 23c: 01 c4 1d 07 R4=R3\+\|\+R5,R3=R3-\|-R5; - 240: 01 c4 9f 05 R6=R3\+\|\+R7,R2=R3-\|-R7; - 244: 01 c4 0a 2e R0=R1\+\|\+R2,R7=R1-\|-R2\(S\); - 248: 01 c4 e5 2c R3=R4\+\|\+R5,R6=R4-\|-R5\(S\); - 24c: 01 c4 b8 2b R6=R7\+\|\+R0,R5=R7-\|-R0\(S\); - 250: 01 c4 53 28 R1=R2\+\|\+R3,R4=R2-\|-R3\(S\); - 254: 01 c4 1d 27 R4=R3\+\|\+R5,R3=R3-\|-R5\(S\); - 258: 01 c4 9f 25 R6=R3\+\|\+R7,R2=R3-\|-R7\(S\); - 25c: 01 c4 0a 1e R0=R1\+\|\+R2,R7=R1-\|-R2\(CO\); - 260: 01 c4 e5 1c R3=R4\+\|\+R5,R6=R4-\|-R5\(CO\); - 264: 01 c4 b8 1b R6=R7\+\|\+R0,R5=R7-\|-R0\(CO\); - 268: 01 c4 53 18 R1=R2\+\|\+R3,R4=R2-\|-R3\(CO\); - 26c: 01 c4 1d 17 R4=R3\+\|\+R5,R3=R3-\|-R5\(CO\); - 270: 01 c4 9f 15 R6=R3\+\|\+R7,R2=R3-\|-R7\(CO\); - 274: 01 c4 0a 3e R0=R1\+\|\+R2,R7=R1-\|-R2\(SCO\); - 278: 01 c4 e5 3c R3=R4\+\|\+R5,R6=R4-\|-R5\(SCO\); - 27c: 01 c4 b8 3b R6=R7\+\|\+R0,R5=R7-\|-R0\(SCO\); - 280: 01 c4 53 38 R1=R2\+\|\+R3,R4=R2-\|-R3\(SCO\); - 284: 01 c4 1d 37 R4=R3\+\|\+R5,R3=R3-\|-R5\(SCO\); - 288: 01 c4 9f 35 R6=R3\+\|\+R7,R2=R3-\|-R7\(SCO\); - 28c: 01 c4 0a 8e R0=R1\+\|\+R2,R7=R1-\|-R2\(ASR\); - 290: 01 c4 e5 8c R3=R4\+\|\+R5,R6=R4-\|-R5\(ASR\); - 294: 01 c4 b8 8b R6=R7\+\|\+R0,R5=R7-\|-R0\(ASR\); - 298: 01 c4 53 88 R1=R2\+\|\+R3,R4=R2-\|-R3\(ASR\); - 29c: 01 c4 1d 87 R4=R3\+\|\+R5,R3=R3-\|-R5\(ASR\); - 2a0: 01 c4 9f 85 R6=R3\+\|\+R7,R2=R3-\|-R7\(ASR\); - 2a4: 01 c4 0a ce R0=R1\+\|\+R2,R7=R1-\|-R2\(ASL\); - 2a8: 01 c4 e5 cc R3=R4\+\|\+R5,R6=R4-\|-R5\(ASL\); - 2ac: 01 c4 b8 cb R6=R7\+\|\+R0,R5=R7-\|-R0\(ASL\); - 2b0: 01 c4 53 c8 R1=R2\+\|\+R3,R4=R2-\|-R3\(ASL\); - 2b4: 01 c4 1d c7 R4=R3\+\|\+R5,R3=R3-\|-R5\(ASL\); - 2b8: 01 c4 9f c5 R6=R3\+\|\+R7,R2=R3-\|-R7\(ASL\); - 2bc: 01 c4 0a ae R0=R1\+\|\+R2,R7=R1-\|-R2\(S,ASR\); - 2c0: 01 c4 e5 ac R3=R4\+\|\+R5,R6=R4-\|-R5\(S,ASR\); - 2c4: 01 c4 b8 ab R6=R7\+\|\+R0,R5=R7-\|-R0\(S,ASR\); - 2c8: 01 c4 53 a8 R1=R2\+\|\+R3,R4=R2-\|-R3\(S,ASR\); - 2cc: 01 c4 1d a7 R4=R3\+\|\+R5,R3=R3-\|-R5\(S,ASR\); - 2d0: 01 c4 9f a5 R6=R3\+\|\+R7,R2=R3-\|-R7\(S,ASR\); - 2d4: 01 c4 0a 9e R0=R1\+\|\+R2,R7=R1-\|-R2\(CO,ASR\); - 2d8: 01 c4 e5 9c R3=R4\+\|\+R5,R6=R4-\|-R5\(CO,ASR\); - 2dc: 01 c4 b8 9b R6=R7\+\|\+R0,R5=R7-\|-R0\(CO,ASR\); - 2e0: 01 c4 53 98 R1=R2\+\|\+R3,R4=R2-\|-R3\(CO,ASR\); - 2e4: 01 c4 1d 97 R4=R3\+\|\+R5,R3=R3-\|-R5\(CO,ASR\); - 2e8: 01 c4 9f 95 R6=R3\+\|\+R7,R2=R3-\|-R7\(CO,ASR\); - 2ec: 01 c4 0a be R0=R1\+\|\+R2,R7=R1-\|-R2\(SCO,ASR\); - 2f0: 01 c4 e5 bc R3=R4\+\|\+R5,R6=R4-\|-R5\(SCO,ASR\); - 2f4: 01 c4 b8 bb R6=R7\+\|\+R0,R5=R7-\|-R0\(SCO,ASR\); - 2f8: 01 c4 53 b8 R1=R2\+\|\+R3,R4=R2-\|-R3\(SCO,ASR\); - 2fc: 01 c4 1d b7 R4=R3\+\|\+R5,R3=R3-\|-R5\(SCO,ASR\); - 300: 01 c4 9f b5 R6=R3\+\|\+R7,R2=R3-\|-R7\(SCO,ASR\); - 304: 01 c4 0a ee R0=R1\+\|\+R2,R7=R1-\|-R2\(S,ASL\); - 308: 01 c4 e5 ec R3=R4\+\|\+R5,R6=R4-\|-R5\(S,ASL\); - 30c: 01 c4 b8 eb R6=R7\+\|\+R0,R5=R7-\|-R0\(S,ASL\); - 310: 01 c4 53 e8 R1=R2\+\|\+R3,R4=R2-\|-R3\(S,ASL\); - 314: 01 c4 1d e7 R4=R3\+\|\+R5,R3=R3-\|-R5\(S,ASL\); - 318: 01 c4 9f e5 R6=R3\+\|\+R7,R2=R3-\|-R7\(S,ASL\); - 31c: 01 c4 0a de R0=R1\+\|\+R2,R7=R1-\|-R2\(CO,ASL\); - 320: 01 c4 e5 dc R3=R4\+\|\+R5,R6=R4-\|-R5\(CO,ASL\); - 324: 01 c4 b8 db R6=R7\+\|\+R0,R5=R7-\|-R0\(CO,ASL\); - 328: 01 c4 53 d8 R1=R2\+\|\+R3,R4=R2-\|-R3\(CO,ASL\); - 32c: 01 c4 1d d7 R4=R3\+\|\+R5,R3=R3-\|-R5\(CO,ASL\); - 330: 01 c4 9f d5 R6=R3\+\|\+R7,R2=R3-\|-R7\(CO,ASL\); - 334: 01 c4 0a fe R0=R1\+\|\+R2,R7=R1-\|-R2\(SCO,ASL\); - 338: 01 c4 e5 fc R3=R4\+\|\+R5,R6=R4-\|-R5\(SCO,ASL\); - 33c: 01 c4 b8 fb R6=R7\+\|\+R0,R5=R7-\|-R0\(SCO,ASL\); - 340: 01 c4 53 f8 R1=R2\+\|\+R3,R4=R2-\|-R3\(SCO,ASL\); - 344: 01 c4 1d f7 R4=R3\+\|\+R5,R3=R3-\|-R5\(SCO,ASL\); - 348: 01 c4 9f f5 R6=R3\+\|\+R7,R2=R3-\|-R7\(SCO,ASL\); - 34c: 21 c4 5c 0f R5=R3\+\|-R4,R7=R3-\|\+R4; - 350: 21 c4 0a 0e R0=R1\+\|-R2,R7=R1-\|\+R2; - 354: 21 c4 e5 0c R3=R4\+\|-R5,R6=R4-\|\+R5; - 358: 21 c4 b8 0b R6=R7\+\|-R0,R5=R7-\|\+R0; - 35c: 21 c4 53 08 R1=R2\+\|-R3,R4=R2-\|\+R3; - 360: 21 c4 1d 07 R4=R3\+\|-R5,R3=R3-\|\+R5; - 364: 21 c4 9f 05 R6=R3\+\|-R7,R2=R3-\|\+R7; - 368: 21 c4 0a 2e R0=R1\+\|-R2,R7=R1-\|\+R2\(S\); - 36c: 21 c4 e5 2c R3=R4\+\|-R5,R6=R4-\|\+R5\(S\); - 370: 21 c4 b8 2b R6=R7\+\|-R0,R5=R7-\|\+R0\(S\); - 374: 21 c4 53 28 R1=R2\+\|-R3,R4=R2-\|\+R3\(S\); - 378: 21 c4 1d 27 R4=R3\+\|-R5,R3=R3-\|\+R5\(S\); - 37c: 21 c4 9f 25 R6=R3\+\|-R7,R2=R3-\|\+R7\(S\); - 380: 21 c4 0a 1e R0=R1\+\|-R2,R7=R1-\|\+R2\(CO\); - 384: 21 c4 e5 1c R3=R4\+\|-R5,R6=R4-\|\+R5\(CO\); - 388: 21 c4 b8 1b R6=R7\+\|-R0,R5=R7-\|\+R0\(CO\); - 38c: 21 c4 53 18 R1=R2\+\|-R3,R4=R2-\|\+R3\(CO\); - 390: 21 c4 1d 17 R4=R3\+\|-R5,R3=R3-\|\+R5\(CO\); - 394: 21 c4 9f 15 R6=R3\+\|-R7,R2=R3-\|\+R7\(CO\); - 398: 21 c4 0a 3e R0=R1\+\|-R2,R7=R1-\|\+R2\(SCO\); - 39c: 21 c4 e5 3c R3=R4\+\|-R5,R6=R4-\|\+R5\(SCO\); - 3a0: 21 c4 b8 3b R6=R7\+\|-R0,R5=R7-\|\+R0\(SCO\); - 3a4: 21 c4 53 38 R1=R2\+\|-R3,R4=R2-\|\+R3\(SCO\); - 3a8: 21 c4 1d 37 R4=R3\+\|-R5,R3=R3-\|\+R5\(SCO\); - 3ac: 21 c4 9f 35 R6=R3\+\|-R7,R2=R3-\|\+R7\(SCO\); - 3b0: 21 c4 0a 8e R0=R1\+\|-R2,R7=R1-\|\+R2\(ASR\); - 3b4: 21 c4 e5 8c R3=R4\+\|-R5,R6=R4-\|\+R5\(ASR\); - 3b8: 21 c4 b8 8b R6=R7\+\|-R0,R5=R7-\|\+R0\(ASR\); - 3bc: 21 c4 53 88 R1=R2\+\|-R3,R4=R2-\|\+R3\(ASR\); - 3c0: 21 c4 1d 87 R4=R3\+\|-R5,R3=R3-\|\+R5\(ASR\); - 3c4: 21 c4 9f 85 R6=R3\+\|-R7,R2=R3-\|\+R7\(ASR\); - 3c8: 21 c4 0a ce R0=R1\+\|-R2,R7=R1-\|\+R2\(ASL\); - 3cc: 21 c4 e5 cc R3=R4\+\|-R5,R6=R4-\|\+R5\(ASL\); - 3d0: 21 c4 b8 cb R6=R7\+\|-R0,R5=R7-\|\+R0\(ASL\); - 3d4: 21 c4 53 c8 R1=R2\+\|-R3,R4=R2-\|\+R3\(ASL\); - 3d8: 21 c4 1d c7 R4=R3\+\|-R5,R3=R3-\|\+R5\(ASL\); - 3dc: 21 c4 9f c5 R6=R3\+\|-R7,R2=R3-\|\+R7\(ASL\); - 3e0: 21 c4 0a ae R0=R1\+\|-R2,R7=R1-\|\+R2\(S,ASR\); - 3e4: 21 c4 e5 ac R3=R4\+\|-R5,R6=R4-\|\+R5\(S,ASR\); - 3e8: 21 c4 b8 ab R6=R7\+\|-R0,R5=R7-\|\+R0\(S,ASR\); - 3ec: 21 c4 53 a8 R1=R2\+\|-R3,R4=R2-\|\+R3\(S,ASR\); - 3f0: 21 c4 1d a7 R4=R3\+\|-R5,R3=R3-\|\+R5\(S,ASR\); - 3f4: 21 c4 9f a5 R6=R3\+\|-R7,R2=R3-\|\+R7\(S,ASR\); - 3f8: 21 c4 0a 9e R0=R1\+\|-R2,R7=R1-\|\+R2\(CO,ASR\); - 3fc: 21 c4 e5 9c R3=R4\+\|-R5,R6=R4-\|\+R5\(CO,ASR\); - 400: 21 c4 b8 9b R6=R7\+\|-R0,R5=R7-\|\+R0\(CO,ASR\); - 404: 21 c4 53 98 R1=R2\+\|-R3,R4=R2-\|\+R3\(CO,ASR\); - 408: 21 c4 1d 97 R4=R3\+\|-R5,R3=R3-\|\+R5\(CO,ASR\); - 40c: 21 c4 9f 95 R6=R3\+\|-R7,R2=R3-\|\+R7\(CO,ASR\); - 410: 21 c4 0a be R0=R1\+\|-R2,R7=R1-\|\+R2\(SCO,ASR\); - 414: 21 c4 e5 bc R3=R4\+\|-R5,R6=R4-\|\+R5\(SCO,ASR\); - 418: 21 c4 b8 bb R6=R7\+\|-R0,R5=R7-\|\+R0\(SCO,ASR\); - 41c: 21 c4 53 b8 R1=R2\+\|-R3,R4=R2-\|\+R3\(SCO,ASR\); - 420: 21 c4 1d b7 R4=R3\+\|-R5,R3=R3-\|\+R5\(SCO,ASR\); - 424: 21 c4 9f b5 R6=R3\+\|-R7,R2=R3-\|\+R7\(SCO,ASR\); - 428: 21 c4 0a ee R0=R1\+\|-R2,R7=R1-\|\+R2\(S,ASL\); - 42c: 21 c4 e5 ec R3=R4\+\|-R5,R6=R4-\|\+R5\(S,ASL\); - 430: 21 c4 b8 eb R6=R7\+\|-R0,R5=R7-\|\+R0\(S,ASL\); - 434: 21 c4 53 e8 R1=R2\+\|-R3,R4=R2-\|\+R3\(S,ASL\); - 438: 21 c4 1d e7 R4=R3\+\|-R5,R3=R3-\|\+R5\(S,ASL\); - 43c: 21 c4 9f e5 R6=R3\+\|-R7,R2=R3-\|\+R7\(S,ASL\); - 440: 21 c4 0a de R0=R1\+\|-R2,R7=R1-\|\+R2\(CO,ASL\); - 444: 21 c4 e5 dc R3=R4\+\|-R5,R6=R4-\|\+R5\(CO,ASL\); - 448: 21 c4 b8 db R6=R7\+\|-R0,R5=R7-\|\+R0\(CO,ASL\); - 44c: 21 c4 53 d8 R1=R2\+\|-R3,R4=R2-\|\+R3\(CO,ASL\); - 450: 21 c4 1d d7 R4=R3\+\|-R5,R3=R3-\|\+R5\(CO,ASL\); - 454: 21 c4 9f d5 R6=R3\+\|-R7,R2=R3-\|\+R7\(CO,ASL\); - 458: 21 c4 0a fe R0=R1\+\|-R2,R7=R1-\|\+R2\(SCO,ASL\); - 45c: 21 c4 e5 fc R3=R4\+\|-R5,R6=R4-\|\+R5\(SCO,ASL\); - 460: 21 c4 b8 fb R6=R7\+\|-R0,R5=R7-\|\+R0\(SCO,ASL\); - 464: 21 c4 53 f8 R1=R2\+\|-R3,R4=R2-\|\+R3\(SCO,ASL\); - 468: 21 c4 1d f7 R4=R3\+\|-R5,R3=R3-\|\+R5\(SCO,ASL\); - 46c: 21 c4 9f f5 R6=R3\+\|-R7,R2=R3-\|\+R7\(SCO,ASL\); - 470: 04 c4 81 86 R2=R0\+R1,R3=R0-R1 \(NS\); - 474: 04 c4 c1 81 R7=R0\+R1,R0=R0-R1 \(NS\); - 478: 04 c4 8a 83 R6=R1\+R2,R1=R1-R2 \(NS\); - 47c: 04 c4 53 85 R5=R2\+R3,R2=R2-R3 \(NS\); - 480: 04 c4 1c 87 R4=R3\+R4,R3=R3-R4 \(NS\); - 484: 04 c4 e5 88 R3=R4\+R5,R4=R4-R5 \(NS\); - 488: 04 c4 ae 8a R2=R5\+R6,R5=R5-R6 \(NS\); - 48c: 04 c4 77 8c R1=R6\+R7,R6=R6-R7 \(NS\); - 490: 04 c4 38 8e R0=R7\+R0,R7=R7-R0 \(NS\); - 494: 04 c4 81 a6 R2=R0\+R1,R3=R0-R1 \(S\); - 498: 04 c4 c1 a1 R7=R0\+R1,R0=R0-R1 \(S\); - 49c: 04 c4 8a a3 R6=R1\+R2,R1=R1-R2 \(S\); - 4a0: 04 c4 53 a5 R5=R2\+R3,R2=R2-R3 \(S\); - 4a4: 04 c4 1c a7 R4=R3\+R4,R3=R3-R4 \(S\); - 4a8: 04 c4 e5 a8 R3=R4\+R5,R4=R4-R5 \(S\); - 4ac: 04 c4 ae aa R2=R5\+R6,R5=R5-R6 \(S\); - 4b0: 04 c4 77 ac R1=R6\+R7,R6=R6-R7 \(S\); - 4b4: 04 c4 38 ae R0=R7\+R0,R7=R7-R0 \(S\); - 4b8: 11 c4 [0-3][[:xdigit:]] 02 R0=A1\+A0,R1=A1-A0 \(NS\); - 4bc: 11 c4 [8|9|a|b][[:xdigit:]] 06 R2=A1\+A0,R3=A1-A0 \(NS\); - 4c0: 11 c4 [0-3][[:xdigit:]] 0b R4=A1\+A0,R5=A1-A0 \(NS\); - 4c4: 11 c4 [8|9|a|b][[:xdigit:]] 0f R6=A1\+A0,R7=A1-A0 \(NS\); - 4c8: 11 c4 [4-7][[:xdigit:]] 00 R1=A1\+A0,R0=A1-A0 \(NS\); - 4cc: 11 c4 [c-f][[:xdigit:]] 04 R3=A1\+A0,R2=A1-A0 \(NS\); - 4d0: 11 c4 [4-7][[:xdigit:]] 09 R5=A1\+A0,R4=A1-A0 \(NS\); - 4d4: 11 c4 [0-3][[:xdigit:]] 22 R0=A1\+A0,R1=A1-A0 \(S\); - 4d8: 11 c4 [8|9|a|b][[:xdigit:]] 26 R2=A1\+A0,R3=A1-A0 \(S\); - 4dc: 11 c4 [0-3][[:xdigit:]] 2b R4=A1\+A0,R5=A1-A0 \(S\); - 4e0: 11 c4 [8|9|a|b][[:xdigit:]] 2f R6=A1\+A0,R7=A1-A0 \(S\); - 4e4: 11 c4 [4-7][[:xdigit:]] 20 R1=A1\+A0,R0=A1-A0 \(S\); - 4e8: 11 c4 [c-f][[:xdigit:]] 24 R3=A1\+A0,R2=A1-A0 \(S\); - 4ec: 11 c4 [4-7][[:xdigit:]] 29 R5=A1\+A0,R4=A1-A0 \(S\); - 4f0: 11 c4 [0-3][[:xdigit:]] 6d R4=A0\+A1,R6=A0-A1 \(S\); - 4f4: 11 c4 [0-3][[:xdigit:]] 42 R0=A0\+A1,R1=A0-A1 \(NS\); - 4f8: 11 c4 [8|9|a|b][[:xdigit:]] 46 R2=A0\+A1,R3=A0-A1 \(NS\); - 4fc: 11 c4 [0-3][[:xdigit:]] 4b R4=A0\+A1,R5=A0-A1 \(NS\); - 500: 11 c4 [8|9|a|b][[:xdigit:]] 4f R6=A0\+A1,R7=A0-A1 \(NS\); - 504: 11 c4 [4-7][[:xdigit:]] 40 R1=A0\+A1,R0=A0-A1 \(NS\); - 508: 11 c4 [c-f][[:xdigit:]] 44 R3=A0\+A1,R2=A0-A1 \(NS\); - 50c: 11 c4 [4-7][[:xdigit:]] 49 R5=A0\+A1,R4=A0-A1 \(NS\); - 510: 11 c4 [0-3][[:xdigit:]] 62 R0=A0\+A1,R1=A0-A1 \(S\); - 514: 11 c4 [8|9|a|b][[:xdigit:]] 66 R2=A0\+A1,R3=A0-A1 \(S\); - 518: 11 c4 [0-3][[:xdigit:]] 6b R4=A0\+A1,R5=A0-A1 \(S\); - 51c: 11 c4 [8|9|a|b][[:xdigit:]] 6f R6=A0\+A1,R7=A0-A1 \(S\); - 520: 11 c4 [4-7][[:xdigit:]] 60 R1=A0\+A1,R0=A0-A1 \(S\); - 524: 11 c4 [c-f][[:xdigit:]] 64 R3=A0\+A1,R2=A0-A1 \(S\); - 528: 11 c4 [4-7][[:xdigit:]] 69 R5=A0\+A1,R4=A0-A1 \(S\); - 52c: 81 c6 d8 01 R0=R0>>>0x5 \(V\); - 530: 81 c6 d9 01 R0=R1>>>0x5 \(V\); - 534: 81 c6 db 05 R2=R3>>>0x5 \(V\); - 538: 81 c6 dd 09 R4=R5>>>0x5 \(V\); - 53c: 81 c6 df 0d R6=R7>>>0x5 \(V\); - 540: 81 c6 d8 03 R1=R0>>>0x5 \(V\); - 544: 81 c6 da 07 R3=R2>>>0x5 \(V\); - 548: 81 c6 dc 0b R5=R4>>>0x5 \(V\); - 54c: 81 c6 de 0f R7=R6>>>0x5 \(V\); - 550: 81 c6 29 40 R0=R1<<0x5 \(V, S\); - 554: 81 c6 2b 44 R2=R3<<0x5 \(V, S\); - 558: 81 c6 2d 48 R4=R5<<0x5 \(V, S\); - 55c: 81 c6 2f 4c R6=R7<<0x5 \(V, S\); - 560: 81 c6 28 42 R1=R0<<0x5 \(V, S\); - 564: 81 c6 2a 46 R3=R2<<0x5 \(V, S\); - 568: 81 c6 2c 4a R5=R4<<0x5 \(V, S\); - 56c: 81 c6 2e 4e R7=R6<<0x5 \(V, S\); - 570: 01 c6 2f 04 R2= ASHIFT R7 BY R5.L\(V\); - 574: 01 c6 11 00 R0= ASHIFT R1 BY R2.L\(V\); - 578: 01 c6 2c 06 R3= ASHIFT R4 BY R5.L\(V\); - 57c: 01 c6 07 0c R6= ASHIFT R7 BY R0.L\(V\); - 580: 01 c6 1a 02 R1= ASHIFT R2 BY R3.L\(V\); - 584: 01 c6 35 08 R4= ASHIFT R5 BY R6.L\(V\); - 588: 01 c6 08 0e R7= ASHIFT R0 BY R1.L\(V\); - 58c: 01 c6 23 04 R2= ASHIFT R3 BY R4.L\(V\); - 590: 01 c6 3e 0a R5= ASHIFT R6 BY R7.L\(V\); - 594: 01 c6 11 40 R0= ASHIFT R1 BY R2.L\(V,S\); - 598: 01 c6 2c 46 R3= ASHIFT R4 BY R5.L\(V,S\); - 59c: 01 c6 07 4c R6= ASHIFT R7 BY R0.L\(V,S\); - 5a0: 01 c6 1a 42 R1= ASHIFT R2 BY R3.L\(V,S\); - 5a4: 01 c6 35 48 R4= ASHIFT R5 BY R6.L\(V,S\); - 5a8: 01 c6 08 4e R7= ASHIFT R0 BY R1.L\(V,S\); - 5ac: 01 c6 23 44 R2= ASHIFT R3 BY R4.L\(V,S\); - 5b0: 01 c6 3e 4a R5= ASHIFT R6 BY R7.L\(V,S\); - 5b4: 81 c6 d9 81 R0=R1 >> 0x5 \(V\); - 5b8: 81 c6 db 85 R2=R3 >> 0x5 \(V\); - 5bc: 81 c6 dd 89 R4=R5 >> 0x5 \(V\); - 5c0: 81 c6 df 8d R6=R7 >> 0x5 \(V\); - 5c4: 81 c6 d8 83 R1=R0 >> 0x5 \(V\); - 5c8: 81 c6 da 87 R3=R2 >> 0x5 \(V\); - 5cc: 81 c6 dc 8b R5=R4 >> 0x5 \(V\); - 5d0: 81 c6 de 8f R7=R6 >> 0x5 \(V\); - 5d4: 81 c6 29 80 R0=R1<<0x5 \(V\); - 5d8: 81 c6 2b 84 R2=R3<<0x5 \(V\); - 5dc: 81 c6 2d 88 R4=R5<<0x5 \(V\); - 5e0: 81 c6 2f 8c R6=R7<<0x5 \(V\); - 5e4: 81 c6 28 82 R1=R0<<0x5 \(V\); - 5e8: 81 c6 2a 86 R3=R2<<0x5 \(V\); - 5ec: 81 c6 2c 8a R5=R4<<0x5 \(V\); - 5f0: 81 c6 2e 8e R7=R6<<0x5 \(V\); - 5f4: 01 c6 11 80 R0=SHIFT R1 BY R2.L\(V\); - 5f8: 01 c6 2c 86 R3=SHIFT R4 BY R5.L\(V\); - 5fc: 01 c6 07 8c R6=SHIFT R7 BY R0.L\(V\); - 600: 01 c6 1a 82 R1=SHIFT R2 BY R3.L\(V\); - 604: 01 c6 35 88 R4=SHIFT R5 BY R6.L\(V\); - 608: 01 c6 08 8e R7=SHIFT R0 BY R1.L\(V\); - 60c: 01 c6 23 84 R2=SHIFT R3 BY R4.L\(V\); - 610: 01 c6 3e 8a R5=SHIFT R6 BY R7.L\(V\); - 614: 06 c4 08 0e R7=MAX\(R1,R0\)\(V\); - 618: 06 c4 0a 00 R0=MAX\(R1,R2\)\(V\); - 61c: 06 c4 25 06 R3=MAX\(R4,R5\)\(V\); - 620: 06 c4 38 0c R6=MAX\(R7,R0\)\(V\); - 624: 06 c4 13 02 R1=MAX\(R2,R3\)\(V\); - 628: 06 c4 2e 08 R4=MAX\(R5,R6\)\(V\); - 62c: 06 c4 01 0e R7=MAX\(R0,R1\)\(V\); - 630: 06 c4 1c 04 R2=MAX\(R3,R4\)\(V\); - 634: 06 c4 37 0a R5=MAX\(R6,R7\)\(V\); - 638: 06 c4 0a 40 R0=MIN\(R1,R2\)\(V\); - 63c: 06 c4 25 46 R3=MIN\(R4,R5\)\(V\); - 640: 06 c4 38 4c R6=MIN\(R7,R0\)\(V\); - 644: 06 c4 13 42 R1=MIN\(R2,R3\)\(V\); - 648: 06 c4 2e 48 R4=MIN\(R5,R6\)\(V\); - 64c: 06 c4 01 4e R7=MIN\(R0,R1\)\(V\); - 650: 06 c4 1c 44 R2=MIN\(R3,R4\)\(V\); - 654: 06 c4 37 4a R5=MIN\(R6,R7\)\(V\); + 0: 0c c4 13 0e R7.H = R7.L = SIGN \(R2.H\) \* R3.H \+ SIGN \(R2.L\) \* R3.L; + 4: 0c c4 0a 00 R0.H = R0.L = SIGN \(R1.H\) \* R2.H \+ SIGN \(R1.L\) \* R2.L; + 8: 0c c4 25 06 R3.H = R3.L = SIGN \(R4.H\) \* R5.H \+ SIGN \(R4.L\) \* R5.L; + c: 0c c4 38 0c R6.H = R6.L = SIGN \(R7.H\) \* R0.H \+ SIGN \(R7.L\) \* R0.L; + 10: 0c c4 13 02 R1.H = R1.L = SIGN \(R2.H\) \* R3.H \+ SIGN \(R2.L\) \* R3.L; + 14: 0c c4 2e 08 R4.H = R4.L = SIGN \(R5.H\) \* R6.H \+ SIGN \(R5.L\) \* R6.L; + 18: 0c c4 01 0e R7.H = R7.L = SIGN \(R0.H\) \* R1.H \+ SIGN \(R0.L\) \* R1.L; + 1c: 0c c4 1c 04 R2.H = R2.L = SIGN \(R3.H\) \* R4.H \+ SIGN \(R3.L\) \* R4.L; + 20: 09 c6 13 8a R5 = VIT_MAX \(R3, R2\) \(ASL\); + 24: 09 c6 01 ce R7 = VIT_MAX \(R1, R0\) \(ASR\); + 28: 09 c6 11 80 R0 = VIT_MAX \(R1, R2\) \(ASL\); + 2c: 09 c6 2c c6 R3 = VIT_MAX \(R4, R5\) \(ASR\); + 30: 09 c6 07 8c R6 = VIT_MAX \(R7, R0\) \(ASL\); + 34: 09 c6 1a c2 R1 = VIT_MAX \(R2, R3\) \(ASR\); + 38: 09 c6 35 88 R4 = VIT_MAX \(R5, R6\) \(ASL\); + 3c: 09 c6 08 ce R7 = VIT_MAX \(R0, R1\) \(ASR\); + 40: 09 c6 23 84 R2 = VIT_MAX \(R3, R4\) \(ASL\); + 44: 09 c6 3e ca R5 = VIT_MAX \(R6, R7\) \(ASR\); + 48: 09 c6 01 06 R3.L = VIT_MAX \(R1\) \(ASL\); + 4c: 09 c6 01 46 R3.L = VIT_MAX \(R1\) \(ASR\); + 50: 09 c6 01 00 R0.L = VIT_MAX \(R1\) \(ASL\); + 54: 09 c6 03 44 R2.L = VIT_MAX \(R3\) \(ASR\); + 58: 09 c6 05 08 R4.L = VIT_MAX \(R5\) \(ASL\); + 5c: 09 c6 07 4c R6.L = VIT_MAX \(R7\) \(ASR\); + 60: 09 c6 02 02 R1.L = VIT_MAX \(R2\) \(ASL\); + 64: 09 c6 04 46 R3.L = VIT_MAX \(R4\) \(ASR\); + 68: 09 c6 06 0a R5.L = VIT_MAX \(R6\) \(ASL\); + 6c: 09 c6 00 4e R7.L = VIT_MAX \(R0\) \(ASR\); + 70: 06 c4 08 86 R3 = ABS R1 \(V\); + 74: 06 c4 00 80 R0 = ABS R0 \(V\); + 78: 06 c4 08 80 R0 = ABS R1 \(V\); + 7c: 06 c4 18 84 R2 = ABS R3 \(V\); + 80: 06 c4 28 88 R4 = ABS R5 \(V\); + 84: 06 c4 38 8c R6 = ABS R7 \(V\); + 88: 06 c4 00 82 R1 = ABS R0 \(V\); + 8c: 06 c4 10 86 R3 = ABS R2 \(V\); + 90: 06 c4 20 8a R5 = ABS R4 \(V\); + 94: 06 c4 30 8e R7 = ABS R6 \(V\); + 98: 00 c4 1c 0a R5 = R3 \+\|\+ R4; + 9c: 00 c4 0a 00 R0 = R1 \+\|\+ R2; + a0: 00 c4 25 06 R3 = R4 \+\|\+ R5; + a4: 00 c4 38 0c R6 = R7 \+\|\+ R0; + a8: 00 c4 13 02 R1 = R2 \+\|\+ R3; + ac: 00 c4 1d 08 R4 = R3 \+\|\+ R5; + b0: 00 c4 1f 0c R6 = R3 \+\|\+ R7; + b4: 00 c4 0a 20 R0 = R1 \+\|\+ R2 \(S\); + b8: 00 c4 25 26 R3 = R4 \+\|\+ R5 \(S\); + bc: 00 c4 38 2c R6 = R7 \+\|\+ R0 \(S\); + c0: 00 c4 13 22 R1 = R2 \+\|\+ R3 \(S\); + c4: 00 c4 1d 28 R4 = R3 \+\|\+ R5 \(S\); + c8: 00 c4 1f 2c R6 = R3 \+\|\+ R7 \(S\); + cc: 00 c4 0a 10 R0 = R1 \+\|\+ R2 \(CO\); + d0: 00 c4 25 16 R3 = R4 \+\|\+ R5 \(CO\); + d4: 00 c4 38 1c R6 = R7 \+\|\+ R0 \(CO\); + d8: 00 c4 13 12 R1 = R2 \+\|\+ R3 \(CO\); + dc: 00 c4 1d 18 R4 = R3 \+\|\+ R5 \(CO\); + e0: 00 c4 1f 1c R6 = R3 \+\|\+ R7 \(CO\); + e4: 00 c4 0a 30 R0 = R1 \+\|\+ R2 \(SCO\); + e8: 00 c4 25 36 R3 = R4 \+\|\+ R5 \(SCO\); + ec: 00 c4 38 3c R6 = R7 \+\|\+ R0 \(SCO\); + f0: 00 c4 13 32 R1 = R2 \+\|\+ R3 \(SCO\); + f4: 00 c4 1d 38 R4 = R3 \+\|\+ R5 \(SCO\); + f8: 00 c4 1f 3c R6 = R3 \+\|\+ R7 \(SCO\); + fc: 00 c4 01 ac R6 = R0 -\|\+ R1 \(S\); + 100: 00 c4 0a 80 R0 = R1 -\|\+ R2; + 104: 00 c4 25 86 R3 = R4 -\|\+ R5; + 108: 00 c4 38 8c R6 = R7 -\|\+ R0; + 10c: 00 c4 13 82 R1 = R2 -\|\+ R3; + 110: 00 c4 1d 88 R4 = R3 -\|\+ R5; + 114: 00 c4 1f 8c R6 = R3 -\|\+ R7; + 118: 00 c4 0a a0 R0 = R1 -\|\+ R2 \(S\); + 11c: 00 c4 25 a6 R3 = R4 -\|\+ R5 \(S\); + 120: 00 c4 38 ac R6 = R7 -\|\+ R0 \(S\); + 124: 00 c4 13 a2 R1 = R2 -\|\+ R3 \(S\); + 128: 00 c4 1d a8 R4 = R3 -\|\+ R5 \(S\); + 12c: 00 c4 1f ac R6 = R3 -\|\+ R7 \(S\); + 130: 00 c4 0a 90 R0 = R1 -\|\+ R2 \(CO\); + 134: 00 c4 25 96 R3 = R4 -\|\+ R5 \(CO\); + 138: 00 c4 38 9c R6 = R7 -\|\+ R0 \(CO\); + 13c: 00 c4 13 92 R1 = R2 -\|\+ R3 \(CO\); + 140: 00 c4 1d 98 R4 = R3 -\|\+ R5 \(CO\); + 144: 00 c4 1f 9c R6 = R3 -\|\+ R7 \(CO\); + 148: 00 c4 0a b0 R0 = R1 -\|\+ R2 \(SCO\); + 14c: 00 c4 25 b6 R3 = R4 -\|\+ R5 \(SCO\); + 150: 00 c4 38 bc R6 = R7 -\|\+ R0 \(SCO\); + 154: 00 c4 13 b2 R1 = R2 -\|\+ R3 \(SCO\); + 158: 00 c4 1d b8 R4 = R3 -\|\+ R5 \(SCO\); + 15c: 00 c4 1f bc R6 = R3 -\|\+ R7 \(SCO\); + 160: 00 c4 11 50 R0 = R2 \+\|- R1 \(CO\); + 164: 00 c4 0a 40 R0 = R1 \+\|- R2; + 168: 00 c4 25 46 R3 = R4 \+\|- R5; + 16c: 00 c4 38 4c R6 = R7 \+\|- R0; + 170: 00 c4 13 42 R1 = R2 \+\|- R3; + 174: 00 c4 1d 48 R4 = R3 \+\|- R5; + 178: 00 c4 1f 4c R6 = R3 \+\|- R7; + 17c: 00 c4 0a 60 R0 = R1 \+\|- R2 \(S\); + 180: 00 c4 25 66 R3 = R4 \+\|- R5 \(S\); + 184: 00 c4 38 6c R6 = R7 \+\|- R0 \(S\); + 188: 00 c4 13 62 R1 = R2 \+\|- R3 \(S\); + 18c: 00 c4 1d 68 R4 = R3 \+\|- R5 \(S\); + 190: 00 c4 1f 6c R6 = R3 \+\|- R7 \(S\); + 194: 00 c4 0a 50 R0 = R1 \+\|- R2 \(CO\); + 198: 00 c4 25 56 R3 = R4 \+\|- R5 \(CO\); + 19c: 00 c4 38 5c R6 = R7 \+\|- R0 \(CO\); + 1a0: 00 c4 13 52 R1 = R2 \+\|- R3 \(CO\); + 1a4: 00 c4 1d 58 R4 = R3 \+\|- R5 \(CO\); + 1a8: 00 c4 1f 5c R6 = R3 \+\|- R7 \(CO\); + 1ac: 00 c4 0a 70 R0 = R1 \+\|- R2 \(SCO\); + 1b0: 00 c4 25 76 R3 = R4 \+\|- R5 \(SCO\); + 1b4: 00 c4 38 7c R6 = R7 \+\|- R0 \(SCO\); + 1b8: 00 c4 13 72 R1 = R2 \+\|- R3 \(SCO\); + 1bc: 00 c4 1d 78 R4 = R3 \+\|- R5 \(SCO\); + 1c0: 00 c4 1f 7c R6 = R3 \+\|- R7 \(SCO\); + 1c4: 00 c4 1e fe R7 = R3 -\|- R6 \(SCO\); + 1c8: 00 c4 0a c0 R0 = R1 -\|- R2; + 1cc: 00 c4 25 c6 R3 = R4 -\|- R5; + 1d0: 00 c4 38 cc R6 = R7 -\|- R0; + 1d4: 00 c4 13 c2 R1 = R2 -\|- R3; + 1d8: 00 c4 1d c8 R4 = R3 -\|- R5; + 1dc: 00 c4 1f cc R6 = R3 -\|- R7; + 1e0: 00 c4 0a e0 R0 = R1 -\|- R2 \(S\); + 1e4: 00 c4 25 e6 R3 = R4 -\|- R5 \(S\); + 1e8: 00 c4 38 ec R6 = R7 -\|- R0 \(S\); + 1ec: 00 c4 13 e2 R1 = R2 -\|- R3 \(S\); + 1f0: 00 c4 1d e8 R4 = R3 -\|- R5 \(S\); + 1f4: 00 c4 1f ec R6 = R3 -\|- R7 \(S\); + 1f8: 00 c4 0a d0 R0 = R1 -\|- R2 \(CO\); + 1fc: 00 c4 25 d6 R3 = R4 -\|- R5 \(CO\); + 200: 00 c4 38 dc R6 = R7 -\|- R0 \(CO\); + 204: 00 c4 13 d2 R1 = R2 -\|- R3 \(CO\); + 208: 00 c4 1d d8 R4 = R3 -\|- R5 \(CO\); + 20c: 00 c4 1f dc R6 = R3 -\|- R7 \(CO\); + 210: 00 c4 0a f0 R0 = R1 -\|- R2 \(SCO\); + 214: 00 c4 25 f6 R3 = R4 -\|- R5 \(SCO\); + 218: 00 c4 38 fc R6 = R7 -\|- R0 \(SCO\); + 21c: 00 c4 13 f2 R1 = R2 -\|- R3 \(SCO\); + 220: 00 c4 1d f8 R4 = R3 -\|- R5 \(SCO\); + 224: 00 c4 1f fc R6 = R3 -\|- R7 \(SCO\); + 228: 01 c4 5c 0f R5 = R3 \+\|\+ R4, R7 = R3 -\|- R4; + 22c: 01 c4 0a 0e R0 = R1 \+\|\+ R2, R7 = R1 -\|- R2; + 230: 01 c4 e5 0c R3 = R4 \+\|\+ R5, R6 = R4 -\|- R5; + 234: 01 c4 b8 0b R6 = R7 \+\|\+ R0, R5 = R7 -\|- R0; + 238: 01 c4 53 08 R1 = R2 \+\|\+ R3, R4 = R2 -\|- R3; + 23c: 01 c4 1d 07 R4 = R3 \+\|\+ R5, R3 = R3 -\|- R5; + 240: 01 c4 9f 05 R6 = R3 \+\|\+ R7, R2 = R3 -\|- R7; + 244: 01 c4 0a 2e R0 = R1 \+\|\+ R2, R7 = R1 -\|- R2 \(S\); + 248: 01 c4 e5 2c R3 = R4 \+\|\+ R5, R6 = R4 -\|- R5 \(S\); + 24c: 01 c4 b8 2b R6 = R7 \+\|\+ R0, R5 = R7 -\|- R0 \(S\); + 250: 01 c4 53 28 R1 = R2 \+\|\+ R3, R4 = R2 -\|- R3 \(S\); + 254: 01 c4 1d 27 R4 = R3 \+\|\+ R5, R3 = R3 -\|- R5 \(S\); + 258: 01 c4 9f 25 R6 = R3 \+\|\+ R7, R2 = R3 -\|- R7 \(S\); + 25c: 01 c4 0a 1e R0 = R1 \+\|\+ R2, R7 = R1 -\|- R2 \(CO\); + 260: 01 c4 e5 1c R3 = R4 \+\|\+ R5, R6 = R4 -\|- R5 \(CO\); + 264: 01 c4 b8 1b R6 = R7 \+\|\+ R0, R5 = R7 -\|- R0 \(CO\); + 268: 01 c4 53 18 R1 = R2 \+\|\+ R3, R4 = R2 -\|- R3 \(CO\); + 26c: 01 c4 1d 17 R4 = R3 \+\|\+ R5, R3 = R3 -\|- R5 \(CO\); + 270: 01 c4 9f 15 R6 = R3 \+\|\+ R7, R2 = R3 -\|- R7 \(CO\); + 274: 01 c4 0a 3e R0 = R1 \+\|\+ R2, R7 = R1 -\|- R2 \(SCO\); + 278: 01 c4 e5 3c R3 = R4 \+\|\+ R5, R6 = R4 -\|- R5 \(SCO\); + 27c: 01 c4 b8 3b R6 = R7 \+\|\+ R0, R5 = R7 -\|- R0 \(SCO\); + 280: 01 c4 53 38 R1 = R2 \+\|\+ R3, R4 = R2 -\|- R3 \(SCO\); + 284: 01 c4 1d 37 R4 = R3 \+\|\+ R5, R3 = R3 -\|- R5 \(SCO\); + 288: 01 c4 9f 35 R6 = R3 \+\|\+ R7, R2 = R3 -\|- R7 \(SCO\); + 28c: 01 c4 0a 8e R0 = R1 \+\|\+ R2, R7 = R1 -\|- R2 \(ASR\); + 290: 01 c4 e5 8c R3 = R4 \+\|\+ R5, R6 = R4 -\|- R5 \(ASR\); + 294: 01 c4 b8 8b R6 = R7 \+\|\+ R0, R5 = R7 -\|- R0 \(ASR\); + 298: 01 c4 53 88 R1 = R2 \+\|\+ R3, R4 = R2 -\|- R3 \(ASR\); + 29c: 01 c4 1d 87 R4 = R3 \+\|\+ R5, R3 = R3 -\|- R5 \(ASR\); + 2a0: 01 c4 9f 85 R6 = R3 \+\|\+ R7, R2 = R3 -\|- R7 \(ASR\); + 2a4: 01 c4 0a ce R0 = R1 \+\|\+ R2, R7 = R1 -\|- R2 \(ASL\); + 2a8: 01 c4 e5 cc R3 = R4 \+\|\+ R5, R6 = R4 -\|- R5 \(ASL\); + 2ac: 01 c4 b8 cb R6 = R7 \+\|\+ R0, R5 = R7 -\|- R0 \(ASL\); + 2b0: 01 c4 53 c8 R1 = R2 \+\|\+ R3, R4 = R2 -\|- R3 \(ASL\); + 2b4: 01 c4 1d c7 R4 = R3 \+\|\+ R5, R3 = R3 -\|- R5 \(ASL\); + 2b8: 01 c4 9f c5 R6 = R3 \+\|\+ R7, R2 = R3 -\|- R7 \(ASL\); + 2bc: 01 c4 0a ae R0 = R1 \+\|\+ R2, R7 = R1 -\|- R2 \(S, ASR\); + 2c0: 01 c4 e5 ac R3 = R4 \+\|\+ R5, R6 = R4 -\|- R5 \(S, ASR\); + 2c4: 01 c4 b8 ab R6 = R7 \+\|\+ R0, R5 = R7 -\|- R0 \(S, ASR\); + 2c8: 01 c4 53 a8 R1 = R2 \+\|\+ R3, R4 = R2 -\|- R3 \(S, ASR\); + 2cc: 01 c4 1d a7 R4 = R3 \+\|\+ R5, R3 = R3 -\|- R5 \(S, ASR\); + 2d0: 01 c4 9f a5 R6 = R3 \+\|\+ R7, R2 = R3 -\|- R7 \(S, ASR\); + 2d4: 01 c4 0a 9e R0 = R1 \+\|\+ R2, R7 = R1 -\|- R2 \(CO, ASR\); + 2d8: 01 c4 e5 9c R3 = R4 \+\|\+ R5, R6 = R4 -\|- R5 \(CO, ASR\); + 2dc: 01 c4 b8 9b R6 = R7 \+\|\+ R0, R5 = R7 -\|- R0 \(CO, ASR\); + 2e0: 01 c4 53 98 R1 = R2 \+\|\+ R3, R4 = R2 -\|- R3 \(CO, ASR\); + 2e4: 01 c4 1d 97 R4 = R3 \+\|\+ R5, R3 = R3 -\|- R5 \(CO, ASR\); + 2e8: 01 c4 9f 95 R6 = R3 \+\|\+ R7, R2 = R3 -\|- R7 \(CO, ASR\); + 2ec: 01 c4 0a be R0 = R1 \+\|\+ R2, R7 = R1 -\|- R2 \(SCO, ASR\); + 2f0: 01 c4 e5 bc R3 = R4 \+\|\+ R5, R6 = R4 -\|- R5 \(SCO, ASR\); + 2f4: 01 c4 b8 bb R6 = R7 \+\|\+ R0, R5 = R7 -\|- R0 \(SCO, ASR\); + 2f8: 01 c4 53 b8 R1 = R2 \+\|\+ R3, R4 = R2 -\|- R3 \(SCO, ASR\); + 2fc: 01 c4 1d b7 R4 = R3 \+\|\+ R5, R3 = R3 -\|- R5 \(SCO, ASR\); + 300: 01 c4 9f b5 R6 = R3 \+\|\+ R7, R2 = R3 -\|- R7 \(SCO, ASR\); + 304: 01 c4 0a ee R0 = R1 \+\|\+ R2, R7 = R1 -\|- R2 \(S, ASL\); + 308: 01 c4 e5 ec R3 = R4 \+\|\+ R5, R6 = R4 -\|- R5 \(S, ASL\); + 30c: 01 c4 b8 eb R6 = R7 \+\|\+ R0, R5 = R7 -\|- R0 \(S, ASL\); + 310: 01 c4 53 e8 R1 = R2 \+\|\+ R3, R4 = R2 -\|- R3 \(S, ASL\); + 314: 01 c4 1d e7 R4 = R3 \+\|\+ R5, R3 = R3 -\|- R5 \(S, ASL\); + 318: 01 c4 9f e5 R6 = R3 \+\|\+ R7, R2 = R3 -\|- R7 \(S, ASL\); + 31c: 01 c4 0a de R0 = R1 \+\|\+ R2, R7 = R1 -\|- R2 \(CO, ASL\); + 320: 01 c4 e5 dc R3 = R4 \+\|\+ R5, R6 = R4 -\|- R5 \(CO, ASL\); + 324: 01 c4 b8 db R6 = R7 \+\|\+ R0, R5 = R7 -\|- R0 \(CO, ASL\); + 328: 01 c4 53 d8 R1 = R2 \+\|\+ R3, R4 = R2 -\|- R3 \(CO, ASL\); + 32c: 01 c4 1d d7 R4 = R3 \+\|\+ R5, R3 = R3 -\|- R5 \(CO, ASL\); + 330: 01 c4 9f d5 R6 = R3 \+\|\+ R7, R2 = R3 -\|- R7 \(CO, ASL\); + 334: 01 c4 0a fe R0 = R1 \+\|\+ R2, R7 = R1 -\|- R2 \(SCO, ASL\); + 338: 01 c4 e5 fc R3 = R4 \+\|\+ R5, R6 = R4 -\|- R5 \(SCO, ASL\); + 33c: 01 c4 b8 fb R6 = R7 \+\|\+ R0, R5 = R7 -\|- R0 \(SCO, ASL\); + 340: 01 c4 53 f8 R1 = R2 \+\|\+ R3, R4 = R2 -\|- R3 \(SCO, ASL\); + 344: 01 c4 1d f7 R4 = R3 \+\|\+ R5, R3 = R3 -\|- R5 \(SCO, ASL\); + 348: 01 c4 9f f5 R6 = R3 \+\|\+ R7, R2 = R3 -\|- R7 \(SCO, ASL\); + 34c: 21 c4 5c 0f R5 = R3 \+\|- R4, R7 = R3 -\|\+ R4; + 350: 21 c4 0a 0e R0 = R1 \+\|- R2, R7 = R1 -\|\+ R2; + 354: 21 c4 e5 0c R3 = R4 \+\|- R5, R6 = R4 -\|\+ R5; + 358: 21 c4 b8 0b R6 = R7 \+\|- R0, R5 = R7 -\|\+ R0; + 35c: 21 c4 53 08 R1 = R2 \+\|- R3, R4 = R2 -\|\+ R3; + 360: 21 c4 1d 07 R4 = R3 \+\|- R5, R3 = R3 -\|\+ R5; + 364: 21 c4 9f 05 R6 = R3 \+\|- R7, R2 = R3 -\|\+ R7; + 368: 21 c4 0a 2e R0 = R1 \+\|- R2, R7 = R1 -\|\+ R2 \(S\); + 36c: 21 c4 e5 2c R3 = R4 \+\|- R5, R6 = R4 -\|\+ R5 \(S\); + 370: 21 c4 b8 2b R6 = R7 \+\|- R0, R5 = R7 -\|\+ R0 \(S\); + 374: 21 c4 53 28 R1 = R2 \+\|- R3, R4 = R2 -\|\+ R3 \(S\); + 378: 21 c4 1d 27 R4 = R3 \+\|- R5, R3 = R3 -\|\+ R5 \(S\); + 37c: 21 c4 9f 25 R6 = R3 \+\|- R7, R2 = R3 -\|\+ R7 \(S\); + 380: 21 c4 0a 1e R0 = R1 \+\|- R2, R7 = R1 -\|\+ R2 \(CO\); + 384: 21 c4 e5 1c R3 = R4 \+\|- R5, R6 = R4 -\|\+ R5 \(CO\); + 388: 21 c4 b8 1b R6 = R7 \+\|- R0, R5 = R7 -\|\+ R0 \(CO\); + 38c: 21 c4 53 18 R1 = R2 \+\|- R3, R4 = R2 -\|\+ R3 \(CO\); + 390: 21 c4 1d 17 R4 = R3 \+\|- R5, R3 = R3 -\|\+ R5 \(CO\); + 394: 21 c4 9f 15 R6 = R3 \+\|- R7, R2 = R3 -\|\+ R7 \(CO\); + 398: 21 c4 0a 3e R0 = R1 \+\|- R2, R7 = R1 -\|\+ R2 \(SCO\); + 39c: 21 c4 e5 3c R3 = R4 \+\|- R5, R6 = R4 -\|\+ R5 \(SCO\); + 3a0: 21 c4 b8 3b R6 = R7 \+\|- R0, R5 = R7 -\|\+ R0 \(SCO\); + 3a4: 21 c4 53 38 R1 = R2 \+\|- R3, R4 = R2 -\|\+ R3 \(SCO\); + 3a8: 21 c4 1d 37 R4 = R3 \+\|- R5, R3 = R3 -\|\+ R5 \(SCO\); + 3ac: 21 c4 9f 35 R6 = R3 \+\|- R7, R2 = R3 -\|\+ R7 \(SCO\); + 3b0: 21 c4 0a 8e R0 = R1 \+\|- R2, R7 = R1 -\|\+ R2 \(ASR\); + 3b4: 21 c4 e5 8c R3 = R4 \+\|- R5, R6 = R4 -\|\+ R5 \(ASR\); + 3b8: 21 c4 b8 8b R6 = R7 \+\|- R0, R5 = R7 -\|\+ R0 \(ASR\); + 3bc: 21 c4 53 88 R1 = R2 \+\|- R3, R4 = R2 -\|\+ R3 \(ASR\); + 3c0: 21 c4 1d 87 R4 = R3 \+\|- R5, R3 = R3 -\|\+ R5 \(ASR\); + 3c4: 21 c4 9f 85 R6 = R3 \+\|- R7, R2 = R3 -\|\+ R7 \(ASR\); + 3c8: 21 c4 0a ce R0 = R1 \+\|- R2, R7 = R1 -\|\+ R2 \(ASL\); + 3cc: 21 c4 e5 cc R3 = R4 \+\|- R5, R6 = R4 -\|\+ R5 \(ASL\); + 3d0: 21 c4 b8 cb R6 = R7 \+\|- R0, R5 = R7 -\|\+ R0 \(ASL\); + 3d4: 21 c4 53 c8 R1 = R2 \+\|- R3, R4 = R2 -\|\+ R3 \(ASL\); + 3d8: 21 c4 1d c7 R4 = R3 \+\|- R5, R3 = R3 -\|\+ R5 \(ASL\); + 3dc: 21 c4 9f c5 R6 = R3 \+\|- R7, R2 = R3 -\|\+ R7 \(ASL\); + 3e0: 21 c4 0a ae R0 = R1 \+\|- R2, R7 = R1 -\|\+ R2 \(S, ASR\); + 3e4: 21 c4 e5 ac R3 = R4 \+\|- R5, R6 = R4 -\|\+ R5 \(S, ASR\); + 3e8: 21 c4 b8 ab R6 = R7 \+\|- R0, R5 = R7 -\|\+ R0 \(S, ASR\); + 3ec: 21 c4 53 a8 R1 = R2 \+\|- R3, R4 = R2 -\|\+ R3 \(S, ASR\); + 3f0: 21 c4 1d a7 R4 = R3 \+\|- R5, R3 = R3 -\|\+ R5 \(S, ASR\); + 3f4: 21 c4 9f a5 R6 = R3 \+\|- R7, R2 = R3 -\|\+ R7 \(S, ASR\); + 3f8: 21 c4 0a 9e R0 = R1 \+\|- R2, R7 = R1 -\|\+ R2 \(CO, ASR\); + 3fc: 21 c4 e5 9c R3 = R4 \+\|- R5, R6 = R4 -\|\+ R5 \(CO, ASR\); + 400: 21 c4 b8 9b R6 = R7 \+\|- R0, R5 = R7 -\|\+ R0 \(CO, ASR\); + 404: 21 c4 53 98 R1 = R2 \+\|- R3, R4 = R2 -\|\+ R3 \(CO, ASR\); + 408: 21 c4 1d 97 R4 = R3 \+\|- R5, R3 = R3 -\|\+ R5 \(CO, ASR\); + 40c: 21 c4 9f 95 R6 = R3 \+\|- R7, R2 = R3 -\|\+ R7 \(CO, ASR\); + 410: 21 c4 0a be R0 = R1 \+\|- R2, R7 = R1 -\|\+ R2 \(SCO, ASR\); + 414: 21 c4 e5 bc R3 = R4 \+\|- R5, R6 = R4 -\|\+ R5 \(SCO, ASR\); + 418: 21 c4 b8 bb R6 = R7 \+\|- R0, R5 = R7 -\|\+ R0 \(SCO, ASR\); + 41c: 21 c4 53 b8 R1 = R2 \+\|- R3, R4 = R2 -\|\+ R3 \(SCO, ASR\); + 420: 21 c4 1d b7 R4 = R3 \+\|- R5, R3 = R3 -\|\+ R5 \(SCO, ASR\); + 424: 21 c4 9f b5 R6 = R3 \+\|- R7, R2 = R3 -\|\+ R7 \(SCO, ASR\); + 428: 21 c4 0a ee R0 = R1 \+\|- R2, R7 = R1 -\|\+ R2 \(S, ASL\); + 42c: 21 c4 e5 ec R3 = R4 \+\|- R5, R6 = R4 -\|\+ R5 \(S, ASL\); + 430: 21 c4 b8 eb R6 = R7 \+\|- R0, R5 = R7 -\|\+ R0 \(S, ASL\); + 434: 21 c4 53 e8 R1 = R2 \+\|- R3, R4 = R2 -\|\+ R3 \(S, ASL\); + 438: 21 c4 1d e7 R4 = R3 \+\|- R5, R3 = R3 -\|\+ R5 \(S, ASL\); + 43c: 21 c4 9f e5 R6 = R3 \+\|- R7, R2 = R3 -\|\+ R7 \(S, ASL\); + 440: 21 c4 0a de R0 = R1 \+\|- R2, R7 = R1 -\|\+ R2 \(CO, ASL\); + 444: 21 c4 e5 dc R3 = R4 \+\|- R5, R6 = R4 -\|\+ R5 \(CO, ASL\); + 448: 21 c4 b8 db R6 = R7 \+\|- R0, R5 = R7 -\|\+ R0 \(CO, ASL\); + 44c: 21 c4 53 d8 R1 = R2 \+\|- R3, R4 = R2 -\|\+ R3 \(CO, ASL\); + 450: 21 c4 1d d7 R4 = R3 \+\|- R5, R3 = R3 -\|\+ R5 \(CO, ASL\); + 454: 21 c4 9f d5 R6 = R3 \+\|- R7, R2 = R3 -\|\+ R7 \(CO, ASL\); + 458: 21 c4 0a fe R0 = R1 \+\|- R2, R7 = R1 -\|\+ R2 \(SCO, ASL\); + 45c: 21 c4 e5 fc R3 = R4 \+\|- R5, R6 = R4 -\|\+ R5 \(SCO, ASL\); + 460: 21 c4 b8 fb R6 = R7 \+\|- R0, R5 = R7 -\|\+ R0 \(SCO, ASL\); + 464: 21 c4 53 f8 R1 = R2 \+\|- R3, R4 = R2 -\|\+ R3 \(SCO, ASL\); + 468: 21 c4 1d f7 R4 = R3 \+\|- R5, R3 = R3 -\|\+ R5 \(SCO, ASL\); + 46c: 21 c4 9f f5 R6 = R3 \+\|- R7, R2 = R3 -\|\+ R7 \(SCO, ASL\); + 470: 04 c4 81 86 R2 = R0 \+ R1, R3 = R0 - R1 \(NS\); + 474: 04 c4 c1 81 R7 = R0 \+ R1, R0 = R0 - R1 \(NS\); + 478: 04 c4 8a 83 R6 = R1 \+ R2, R1 = R1 - R2 \(NS\); + 47c: 04 c4 53 85 R5 = R2 \+ R3, R2 = R2 - R3 \(NS\); + 480: 04 c4 1c 87 R4 = R3 \+ R4, R3 = R3 - R4 \(NS\); + 484: 04 c4 e5 88 R3 = R4 \+ R5, R4 = R4 - R5 \(NS\); + 488: 04 c4 ae 8a R2 = R5 \+ R6, R5 = R5 - R6 \(NS\); + 48c: 04 c4 77 8c R1 = R6 \+ R7, R6 = R6 - R7 \(NS\); + 490: 04 c4 38 8e R0 = R7 \+ R0, R7 = R7 - R0 \(NS\); + 494: 04 c4 81 a6 R2 = R0 \+ R1, R3 = R0 - R1 \(S\); + 498: 04 c4 c1 a1 R7 = R0 \+ R1, R0 = R0 - R1 \(S\); + 49c: 04 c4 8a a3 R6 = R1 \+ R2, R1 = R1 - R2 \(S\); + 4a0: 04 c4 53 a5 R5 = R2 \+ R3, R2 = R2 - R3 \(S\); + 4a4: 04 c4 1c a7 R4 = R3 \+ R4, R3 = R3 - R4 \(S\); + 4a8: 04 c4 e5 a8 R3 = R4 \+ R5, R4 = R4 - R5 \(S\); + 4ac: 04 c4 ae aa R2 = R5 \+ R6, R5 = R5 - R6 \(S\); + 4b0: 04 c4 77 ac R1 = R6 \+ R7, R6 = R6 - R7 \(S\); + 4b4: 04 c4 38 ae R0 = R7 \+ R0, R7 = R7 - R0 \(S\); + 4b8: 11 c4 [0-3][[:xdigit:]] 02 R0 = A1 \+ A0, R1 = A1 - A0 \(NS\); + 4bc: 11 c4 [8|9|a|b][[:xdigit:]] 06 R2 = A1 \+ A0, R3 = A1 - A0 \(NS\); + 4c0: 11 c4 [0-3][[:xdigit:]] 0b R4 = A1 \+ A0, R5 = A1 - A0 \(NS\); + 4c4: 11 c4 [8|9|a|b][[:xdigit:]] 0f R6 = A1 \+ A0, R7 = A1 - A0 \(NS\); + 4c8: 11 c4 [4-7][[:xdigit:]] 00 R1 = A1 \+ A0, R0 = A1 - A0 \(NS\); + 4cc: 11 c4 [c-f][[:xdigit:]] 04 R3 = A1 \+ A0, R2 = A1 - A0 \(NS\); + 4d0: 11 c4 [4-7][[:xdigit:]] 09 R5 = A1 \+ A0, R4 = A1 - A0 \(NS\); + 4d4: 11 c4 [0-3][[:xdigit:]] 22 R0 = A1 \+ A0, R1 = A1 - A0 \(S\); + 4d8: 11 c4 [8|9|a|b][[:xdigit:]] 26 R2 = A1 \+ A0, R3 = A1 - A0 \(S\); + 4dc: 11 c4 [0-3][[:xdigit:]] 2b R4 = A1 \+ A0, R5 = A1 - A0 \(S\); + 4e0: 11 c4 [8|9|a|b][[:xdigit:]] 2f R6 = A1 \+ A0, R7 = A1 - A0 \(S\); + 4e4: 11 c4 [4-7][[:xdigit:]] 20 R1 = A1 \+ A0, R0 = A1 - A0 \(S\); + 4e8: 11 c4 [c-f][[:xdigit:]] 24 R3 = A1 \+ A0, R2 = A1 - A0 \(S\); + 4ec: 11 c4 [4-7][[:xdigit:]] 29 R5 = A1 \+ A0, R4 = A1 - A0 \(S\); + 4f0: 11 c4 [0-3][[:xdigit:]] 6d R4 = A0 \+ A1, R6 = A0 - A1 \(S\); + 4f4: 11 c4 [0-3][[:xdigit:]] 42 R0 = A0 \+ A1, R1 = A0 - A1 \(NS\); + 4f8: 11 c4 [8|9|a|b][[:xdigit:]] 46 R2 = A0 \+ A1, R3 = A0 - A1 \(NS\); + 4fc: 11 c4 [0-3][[:xdigit:]] 4b R4 = A0 \+ A1, R5 = A0 - A1 \(NS\); + 500: 11 c4 [8|9|a|b][[:xdigit:]] 4f R6 = A0 \+ A1, R7 = A0 - A1 \(NS\); + 504: 11 c4 [4-7][[:xdigit:]] 40 R1 = A0 \+ A1, R0 = A0 - A1 \(NS\); + 508: 11 c4 [c-f][[:xdigit:]] 44 R3 = A0 \+ A1, R2 = A0 - A1 \(NS\); + 50c: 11 c4 [4-7][[:xdigit:]] 49 R5 = A0 \+ A1, R4 = A0 - A1 \(NS\); + 510: 11 c4 [0-3][[:xdigit:]] 62 R0 = A0 \+ A1, R1 = A0 - A1 \(S\); + 514: 11 c4 [8|9|a|b][[:xdigit:]] 66 R2 = A0 \+ A1, R3 = A0 - A1 \(S\); + 518: 11 c4 [0-3][[:xdigit:]] 6b R4 = A0 \+ A1, R5 = A0 - A1 \(S\); + 51c: 11 c4 [8|9|a|b][[:xdigit:]] 6f R6 = A0 \+ A1, R7 = A0 - A1 \(S\); + 520: 11 c4 [4-7][[:xdigit:]] 60 R1 = A0 \+ A1, R0 = A0 - A1 \(S\); + 524: 11 c4 [c-f][[:xdigit:]] 64 R3 = A0 \+ A1, R2 = A0 - A1 \(S\); + 528: 11 c4 [4-7][[:xdigit:]] 69 R5 = A0 \+ A1, R4 = A0 - A1 \(S\); + 52c: 81 c6 d8 01 R0 = R0 >>> 0x5 \(V\); + 530: 81 c6 d9 01 R0 = R1 >>> 0x5 \(V\); + 534: 81 c6 db 05 R2 = R3 >>> 0x5 \(V\); + 538: 81 c6 dd 09 R4 = R5 >>> 0x5 \(V\); + 53c: 81 c6 df 0d R6 = R7 >>> 0x5 \(V\); + 540: 81 c6 d8 03 R1 = R0 >>> 0x5 \(V\); + 544: 81 c6 da 07 R3 = R2 >>> 0x5 \(V\); + 548: 81 c6 dc 0b R5 = R4 >>> 0x5 \(V\); + 54c: 81 c6 de 0f R7 = R6 >>> 0x5 \(V\); + 550: 81 c6 29 40 R0 = R1 << 0x5 \(V, S\); + 554: 81 c6 2b 44 R2 = R3 << 0x5 \(V, S\); + 558: 81 c6 2d 48 R4 = R5 << 0x5 \(V, S\); + 55c: 81 c6 2f 4c R6 = R7 << 0x5 \(V, S\); + 560: 81 c6 28 42 R1 = R0 << 0x5 \(V, S\); + 564: 81 c6 2a 46 R3 = R2 << 0x5 \(V, S\); + 568: 81 c6 2c 4a R5 = R4 << 0x5 \(V, S\); + 56c: 81 c6 2e 4e R7 = R6 << 0x5 \(V, S\); + 570: 01 c6 2f 04 R2 = ASHIFT R7 BY R5.L \(V\); + 574: 01 c6 11 00 R0 = ASHIFT R1 BY R2.L \(V\); + 578: 01 c6 2c 06 R3 = ASHIFT R4 BY R5.L \(V\); + 57c: 01 c6 07 0c R6 = ASHIFT R7 BY R0.L \(V\); + 580: 01 c6 1a 02 R1 = ASHIFT R2 BY R3.L \(V\); + 584: 01 c6 35 08 R4 = ASHIFT R5 BY R6.L \(V\); + 588: 01 c6 08 0e R7 = ASHIFT R0 BY R1.L \(V\); + 58c: 01 c6 23 04 R2 = ASHIFT R3 BY R4.L \(V\); + 590: 01 c6 3e 0a R5 = ASHIFT R6 BY R7.L \(V\); + 594: 01 c6 11 40 R0 = ASHIFT R1 BY R2.L \(V, S\); + 598: 01 c6 2c 46 R3 = ASHIFT R4 BY R5.L \(V, S\); + 59c: 01 c6 07 4c R6 = ASHIFT R7 BY R0.L \(V, S\); + 5a0: 01 c6 1a 42 R1 = ASHIFT R2 BY R3.L \(V, S\); + 5a4: 01 c6 35 48 R4 = ASHIFT R5 BY R6.L \(V, S\); + 5a8: 01 c6 08 4e R7 = ASHIFT R0 BY R1.L \(V, S\); + 5ac: 01 c6 23 44 R2 = ASHIFT R3 BY R4.L \(V, S\); + 5b0: 01 c6 3e 4a R5 = ASHIFT R6 BY R7.L \(V, S\); + 5b4: 81 c6 d9 81 R0 = R1 >> 0x5 \(V\); + 5b8: 81 c6 db 85 R2 = R3 >> 0x5 \(V\); + 5bc: 81 c6 dd 89 R4 = R5 >> 0x5 \(V\); + 5c0: 81 c6 df 8d R6 = R7 >> 0x5 \(V\); + 5c4: 81 c6 d8 83 R1 = R0 >> 0x5 \(V\); + 5c8: 81 c6 da 87 R3 = R2 >> 0x5 \(V\); + 5cc: 81 c6 dc 8b R5 = R4 >> 0x5 \(V\); + 5d0: 81 c6 de 8f R7 = R6 >> 0x5 \(V\); + 5d4: 81 c6 29 80 R0 = R1 << 0x5 \(V\); + 5d8: 81 c6 2b 84 R2 = R3 << 0x5 \(V\); + 5dc: 81 c6 2d 88 R4 = R5 << 0x5 \(V\); + 5e0: 81 c6 2f 8c R6 = R7 << 0x5 \(V\); + 5e4: 81 c6 28 82 R1 = R0 << 0x5 \(V\); + 5e8: 81 c6 2a 86 R3 = R2 << 0x5 \(V\); + 5ec: 81 c6 2c 8a R5 = R4 << 0x5 \(V\); + 5f0: 81 c6 2e 8e R7 = R6 << 0x5 \(V\); + 5f4: 01 c6 11 80 R0 = SHIFT R1 BY R2.L \(V\); + 5f8: 01 c6 2c 86 R3 = SHIFT R4 BY R5.L \(V\); + 5fc: 01 c6 07 8c R6 = SHIFT R7 BY R0.L \(V\); + 600: 01 c6 1a 82 R1 = SHIFT R2 BY R3.L \(V\); + 604: 01 c6 35 88 R4 = SHIFT R5 BY R6.L \(V\); + 608: 01 c6 08 8e R7 = SHIFT R0 BY R1.L \(V\); + 60c: 01 c6 23 84 R2 = SHIFT R3 BY R4.L \(V\); + 610: 01 c6 3e 8a R5 = SHIFT R6 BY R7.L \(V\); + 614: 06 c4 08 0e R7 = MAX \(R1, R0\) \(V\); + 618: 06 c4 0a 00 R0 = MAX \(R1, R2\) \(V\); + 61c: 06 c4 25 06 R3 = MAX \(R4, R5\) \(V\); + 620: 06 c4 38 0c R6 = MAX \(R7, R0\) \(V\); + 624: 06 c4 13 02 R1 = MAX \(R2, R3\) \(V\); + 628: 06 c4 2e 08 R4 = MAX \(R5, R6\) \(V\); + 62c: 06 c4 01 0e R7 = MAX \(R0, R1\) \(V\); + 630: 06 c4 1c 04 R2 = MAX \(R3, R4\) \(V\); + 634: 06 c4 37 0a R5 = MAX \(R6, R7\) \(V\); + 638: 06 c4 0a 40 R0 = MIN \(R1, R2\) \(V\); + 63c: 06 c4 25 46 R3 = MIN \(R4, R5\) \(V\); + 640: 06 c4 38 4c R6 = MIN \(R7, R0\) \(V\); + 644: 06 c4 13 42 R1 = MIN \(R2, R3\) \(V\); + 648: 06 c4 2e 48 R4 = MIN \(R5, R6\) \(V\); + 64c: 06 c4 01 4e R7 = MIN \(R0, R1\) \(V\); + 650: 06 c4 1c 44 R2 = MIN \(R3, R4\) \(V\); + 654: 06 c4 37 4a R5 = MIN \(R6, R7\) \(V\); 658: 04 c2 be 66 R2.H = R7.L \* R6.H, R2 = R7.H \* R6.H; 65c: 04 c2 08 e1 R4.H = R1.H \* R0.H, R4 = R1.L \* R0.L; 660: 14 c2 1a a0 R0.H = R3.H \* R2.L \(M\), R0 = R3.L \* R2.L; - 664: 00 c0 13 46 a1 = R2.L \* R3.H, a0 = R2.H \* R3.H; - 668: 01 c0 08 c0 a1 \+= R1.H \* R0.H, a0 = R1.L \* R0.L; - 66c: 01 c0 1b 96 a1 \+= R3.H \* R3.L, a0 -= R3.H \* R3.H; - 670: 10 c0 1a 88 a1 = R3.H \* R2.L \(M\), a0 \+= R3.L \* R2.L; - 674: 90 c0 3c c8 a1 = R7.H \* R4.H \(M\), a0 \+= R7.L \* R4.L \(FU\); - 678: 01 c1 1a c0 a1 \+= R3.H \* R2.H, a0 = R3.L \* R2.L \(IS\); - 67c: 60 c0 37 c8 a1 = R6.H \* R7.H, a0 \+= R6.L \* R7.L \(W32\); - 680: 04 c0 be 66 R2.H = \(a1 = R7.L \* R6.H\), R2.L = \(a0 = R7.H \* R6.H\); - 684: 05 c0 08 e1 R4.H = \(a1 \+= R1.H \* R0.H\), R4.L = \(a0 = R1.L \* R0.L\); - 688: 05 c0 f5 a7 R7.H = \(a1 \+= R6.H \* R5.L\), R7.L = \(a0 = R6.H \* R5.H\); - 68c: 14 c0 3c a8 R0.H = \(a1 = R7.H \* R4.L\) \(M\), R0.L = \(a0 \+= R7.L \* R4.L\); - 690: 94 c0 5a e9 R5.H = \(a1 = R3.H \* R2.H\) \(M\), R5.L = \(a0 \+= R3.L \* R2.L\) \(FU\); - 694: 05 c1 1a e0 R0.H = \(a1 \+= R3.H \* R2.H\), R0.L = \(a0 = R3.L \* R2.L\) \(IS\); - 698: 04 c0 51 c9 R5.H = \(a1 = R2.H \* R1.H\), a0 \+= R2.L \* R1.L; - 69c: 14 c0 d1 c0 R3.H = \(a1 = R2.H \* R1.H\) \(M\), a0 = R2.L \* R1.L; - 6a0: 27 c0 c1 28 R3.H = A1, R3.L = \(a0 \+= R0.L \* R1.L\) \(S2RND\); - 6a4: 25 c1 3e e8 R0.H = \(a1 \+= R7.H \* R6.H\), R0.L = \(a0 \+= R7.L \* R6.L\) \(ISS2\); - 6a8: 0c c0 b7 e0 R3 = \(a1 = R6.H \* R7.H\), R2 = \(a0 = R6.L \* R7.L\); - 6ac: 0d c0 37 e1 R5 = \(a1 \+= R6.H \* R7.H\), R4 = \(a0 = R6.L \* R7.L\); - 6b0: 0d c0 9d f1 R7 = \(a1 \+= R3.H \* R5.H\), R6 = \(a0 -= R3.L \* R5.L\); - 6b4: 1c c0 3c 2e R1 = \(a1 = R7.L \* R4.L\) \(M\), R0 = \(a0 \+= R7.H \* R4.H\); - 6b8: 9c c0 1f e9 R5 = \(a1 = R3.H \* R7.H\) \(M\), R4 = \(a0 \+= R3.L \* R7.L\) \(FU\); - 6bc: 0d c1 1a e0 R1 = \(a1 \+= R3.H \* R2.H\), R0 = \(a0 = R3.L \* R2.L\) \(IS\); - 6c0: 0e c0 37 c9 R5 = \(a1 -= R6.H \* R7.H\), a0 \+= R6.L \* R7.L; - 6c4: 1c c0 b7 d0 R3 = \(a1 = R6.H \* R7.H\) \(M\), a0 -= R6.L \* R7.L; - 6c8: 2f c0 81 28 R3 = A1, R2 = \(a0 \+= R0.L \* R1.L\) \(S2RND\); - 6cc: 2d c1 3e e8 R1 = \(a1 \+= R7.H \* R6.H\), R0 = \(a0 \+= R7.L \* R6.L\) \(ISS2\); - 6d0: 0f c4 18 ca R5=-R3\(V\); - 6d4: 04 c6 2c 06 R3=PACK\(R4.L,R5.L\); - 6d8: 04 c6 26 42 R1=PACK\(R6.L,R4.H\); - 6dc: 04 c6 22 80 R0=PACK\(R2.H,R4.L\); - 6e0: 04 c6 17 ca R5=PACK\(R7.H,R2.H\); - 6e4: 0d cc 50 c0 \(R1,R0\) = SEARCH R2\(LE\) \|\| R2=\[P0\+\+\] \|\| NOP; + 664: 00 c0 13 46 A1 = R2.L \* R3.H, A0 = R2.H \* R3.H; + 668: 01 c0 08 c0 A1 \+= R1.H \* R0.H, A0 = R1.L \* R0.L; + 66c: 01 c0 1b 96 A1 \+= R3.H \* R3.L, A0 -= R3.H \* R3.H; + 670: 10 c0 1a 88 A1 = R3.H \* R2.L \(M\), A0 \+= R3.L \* R2.L; + 674: 90 c0 3c c8 A1 = R7.H \* R4.H \(M\), A0 \+= R7.L \* R4.L \(FU\); + 678: 01 c1 1a c0 A1 \+= R3.H \* R2.H, A0 = R3.L \* R2.L \(IS\); + 67c: 60 c0 37 c8 A1 = R6.H \* R7.H, A0 \+= R6.L \* R7.L \(W32\); + 680: 04 c0 be 66 R2.H = \(A1 = R7.L \* R6.H\), R2.L = \(A0 = R7.H \* R6.H\); + 684: 05 c0 08 e1 R4.H = \(A1 \+= R1.H \* R0.H\), R4.L = \(A0 = R1.L \* R0.L\); + 688: 05 c0 f5 a7 R7.H = \(A1 \+= R6.H \* R5.L\), R7.L = \(A0 = R6.H \* R5.H\); + 68c: 14 c0 3c a8 R0.H = \(A1 = R7.H \* R4.L\) \(M\), R0.L = \(A0 \+= R7.L \* R4.L\); + 690: 94 c0 5a e9 R5.H = \(A1 = R3.H \* R2.H\) \(M\), R5.L = \(A0 \+= R3.L \* R2.L\) \(FU\); + 694: 05 c1 1a e0 R0.H = \(A1 \+= R3.H \* R2.H\), R0.L = \(A0 = R3.L \* R2.L\) \(IS\); + 698: 04 c0 51 c9 R5.H = \(A1 = R2.H \* R1.H\), A0 \+= R2.L \* R1.L; + 69c: 14 c0 d1 c0 R3.H = \(A1 = R2.H \* R1.H\) \(M\), A0 = R2.L \* R1.L; + 6a0: 27 c0 c1 28 R3.H = A1, R3.L = \(A0 \+= R0.L \* R1.L\) \(S2RND\); + 6a4: 25 c1 3e e8 R0.H = \(A1 \+= R7.H \* R6.H\), R0.L = \(A0 \+= R7.L \* R6.L\) \(ISS2\); + 6a8: 0c c0 b7 e0 R3 = \(A1 = R6.H \* R7.H\), R2 = \(A0 = R6.L \* R7.L\); + 6ac: 0d c0 37 e1 R5 = \(A1 \+= R6.H \* R7.H\), R4 = \(A0 = R6.L \* R7.L\); + 6b0: 0d c0 9d f1 R7 = \(A1 \+= R3.H \* R5.H\), R6 = \(A0 -= R3.L \* R5.L\); + 6b4: 1c c0 3c 2e R1 = \(A1 = R7.L \* R4.L\) \(M\), R0 = \(A0 \+= R7.H \* R4.H\); + 6b8: 9c c0 1f e9 R5 = \(A1 = R3.H \* R7.H\) \(M\), R4 = \(A0 \+= R3.L \* R7.L\) \(FU\); + 6bc: 0d c1 1a e0 R1 = \(A1 \+= R3.H \* R2.H\), R0 = \(A0 = R3.L \* R2.L\) \(IS\); + 6c0: 0e c0 37 c9 R5 = \(A1 -= R6.H \* R7.H\), A0 \+= R6.L \* R7.L; + 6c4: 1c c0 b7 d0 R3 = \(A1 = R6.H \* R7.H\) \(M\), A0 -= R6.L \* R7.L; + 6c8: 2f c0 81 28 R3 = A1, R2 = \(A0 \+= R0.L \* R1.L\) \(S2RND\); + 6cc: 2d c1 3e e8 R1 = \(A1 \+= R7.H \* R6.H\), R0 = \(A0 \+= R7.L \* R6.L\) \(ISS2\); + 6d0: 0f c4 18 ca R5 = -R3 \(V\); + 6d4: 04 c6 2c 06 R3 = PACK \(R4.L, R5.L\); + 6d8: 04 c6 26 42 R1 = PACK \(R6.L, R4.H\); + 6dc: 04 c6 22 80 R0 = PACK \(R2.H, R4.L\); + 6e0: 04 c6 17 ca R5 = PACK \(R7.H, R2.H\); + 6e4: 0d cc 50 c0 \(R1, R0\) = SEARCH R2 \(LE\) \|\| R2 = \[P0\+\+\] \|\| NOP; 6e8: 02 90 00 00 - 6ec: 0d c4 50 c0 \(R1,R0\) = SEARCH R2\(LE\); - 6f0: 12 cc 02 00 SAA\(R1:0x0,R3:0x2\) \|\| R0=\[I0\+\+\] \|\| R2=\[I1\+\+\]; + 6ec: 0d c4 50 c0 \(R1, R0\) = SEARCH R2 \(LE\); + 6f0: 12 cc 02 00 SAA \(R1:0, R3:2\) \|\| R0 = \[I0\+\+\] \|\| R2 = \[I1\+\+\]; 6f4: 00 9c 0a 9c - 6f8: 12 cc 02 20 SAA\(R1:0x0,R3:0x2\) \(R\) \|\| R1=\[I0\+\+\] \|\| R3=\[I1\+\+\]; + 6f8: 12 cc 02 20 SAA \(R1:0, R3:2\) \(R\) \|\| R1 = \[I0\+\+\] \|\| R3 = \[I1\+\+\]; 6fc: 01 9c 0b 9c - 700: 03 c8 00 18 mnop \|\| R1=\[I0\+\+\] \|\| R3=\[I1\+\+\]; + 700: 03 c8 00 18 MNOP \|\| R1 = \[I0\+\+\] \|\| R3 = \[I1\+\+\]; 704: 01 9c 0b 9c - 708: 0c cc 13 0e R7.H=R7.L=SIGN\(R2.H\)\*R3.H\+SIGN\(R2.L\)\*R3.L\) \|\| I0\+=M3 \|\| R0=\[I0\]; + 708: 0c cc 13 0e R7.H = R7.L = SIGN \(R2.H\) \* R3.H \+ SIGN \(R2.L\) \* R3.L \|\| I0 \+= M3 \|\| R0 = \[I0\]; 70c: 6c 9e 00 9d - 710: 01 cc 94 88 R2=R2\+\|\+R4,R4=R2-\|-R4\(ASR\) \|\| I0\+=M0\(BREV\) \|\| R1=\[I0\]; + 710: 01 cc 94 88 R2 = R2 \+\|\+ R4, R4 = R2 -\|- R4 \(ASR\) \|\| I0 \+= M0 \(BREV\) \|\| R1 = \[I0\]; 714: e0 9e 01 9d - 718: 00 c8 11 06 a1 = R2.L \* R1.L, a0 = R2.H \* R1.H \|\| R2.H=W\[I2\+\+\] \|\| \[I3\+\+\]=R3; + 718: 00 c8 11 06 A1 = R2.L \* R1.L, A0 = R2.H \* R1.H \|\| R2.H = W\[I2\+\+\] \|\| \[I3\+\+\] = R3; 71c: 52 9c 1b 9e - 720: 01 c8 02 48 a1 \+= R0.L \* R2.H, a0 \+= R0.L \* R2.L \|\| R2.L=W\[I2\+\+\] \|\| R0=\[I1--\]; + 720: 01 c8 02 48 A1 \+= R0.L \* R2.H, A0 \+= R0.L \* R2.L \|\| R2.L = W\[I2\+\+\] \|\| R0 = \[I1--\]; 724: 32 9c 88 9c - 728: 05 c8 c1 68 R3.H = \(a1 \+= R0.L \* R1.H\), R3.L = \(a0 \+= R0.L \* R1.L\) \|\| R0=\[P0\+\+\] \|\| R1=\[I0\]; + 728: 05 c8 c1 68 R3.H = \(A1 \+= R0.L \* R1.H\), R3.L = \(A0 \+= R0.L \* R1.L\) \|\| R0 = \[P0\+\+\] \|\| R1 = \[I0\]; 72c: 00 90 01 9d - 730: 04 ce 01 c2 R1=PACK\(R1.H,R0.H\) \|\| \[I0\+\+\]=R0 \|\| R2.L=W\[I2\+\+\]; + 730: 04 ce 01 c2 R1 = PACK \(R1.H, R0.H\) \|\| \[I0\+\+\] = R0 \|\| R2.L = W\[I2\+\+\]; 734: 00 9e 32 9c - 738: 8b c8 9a 2f R6 = \(a0 \+= R3.H \* R2.H\) \(FU\) \|\| I2-=M0 \|\| NOP; + 738: 8b c8 9a 2f R6 = \(A0 \+= R3.H \* R2.H\) \(FU\) \|\| I2 -= M0 \|\| NOP; 73c: 72 9e 00 00 740: 14 c2 1a a0 R0.H = R3.H \* R2.L \(M\), R0 = R3.L \* R2.L; 744: 1c c2 b8 60 R3 = R7.L \* R0.H \(M\), R2 = R7.L \* R0.L; - 748: 1c c0 b8 60 R3 = \(a1 = R7.L \* R0.H\) \(M\), R2 = \(a0 = R7.L \* R0.L\); - 74c: 44 c0 23 04 R0.H = \(a1 = R4.L \* R3.L\), a0 = R4.H \* R3.L \(T\); - 750: 54 c0 23 04 R0.H = \(a1 = R4.L \* R3.L\) \(M\), a0 = R4.H \* R3.L \(T\); - 754: 44 c0 23 04 R0.H = \(a1 = R4.L \* R3.L\), a0 = R4.H \* R3.L \(T\); - 758: 54 c0 23 04 R0.H = \(a1 = R4.L \* R3.L\) \(M\), a0 = R4.H \* R3.L \(T\); - 75c: 41 c0 3c e2 a1 \+= R7.H \* R4.H, R0.L = \(a0 = R7.L \* R4.H\) \(T\); + 748: 1c c0 b8 60 R3 = \(A1 = R7.L \* R0.H\) \(M\), R2 = \(A0 = R7.L \* R0.L\); + 74c: 44 c0 23 04 R0.H = \(A1 = R4.L \* R3.L\), A0 = R4.H \* R3.L \(T\); + 750: 54 c0 23 04 R0.H = \(A1 = R4.L \* R3.L\) \(M\), A0 = R4.H \* R3.L \(T\); + 754: 44 c0 23 04 R0.H = \(A1 = R4.L \* R3.L\), A0 = R4.H \* R3.L \(T\); + 758: 54 c0 23 04 R0.H = \(A1 = R4.L \* R3.L\) \(M\), A0 = R4.H \* R3.L \(T\); + 75c: 41 c0 3c e2 A1 \+= R7.H \* R4.H, R0.L = \(A0 = R7.L \* R4.H\) \(T\); + diff --git a/gas/testsuite/gas/bfin/video.d b/gas/testsuite/gas/bfin/video.d index 7f911d1..e84714f 100644 --- a/gas/testsuite/gas/bfin/video.d +++ b/gas/testsuite/gas/bfin/video.d @@ -4,53 +4,53 @@ Disassembly of section .text: 00000000 <align>: - 0: 0d c6 15 0e R7=ALIGN8\(R5,R2\); - 4: 0d c6 08 4a R5=ALIGN16\(R0,R1\); - 8: 0d c6 05 84 R2=ALIGN24\(R5,R0\); + 0: 0d c6 15 0e R7 = ALIGN8 \(R5, R2\); + 4: 0d c6 08 4a R5 = ALIGN16 \(R0, R1\); + 8: 0d c6 05 84 R2 = ALIGN24 \(R5, R0\); 0000000c <disalgnexcpt>: c: 12 c4 00 c0 DISALGNEXCPT; 00000010 <byteop3p>: - 10: 17 c4 02 0a R5=BYTEOP3P\(R1:0x0,R3:0x2\)\(LO\); - 14: 37 c4 02 00 R0=BYTEOP3P\(R1:0x0,R3:0x2\)\(HI\); - 18: 17 c4 02 22 R1=BYTEOP3P\(R1:0x0,R3:0x2\)\(LO, R\); - 1c: 37 c4 02 24 R2=BYTEOP3P\(R1:0x0,R3:0x2\)\(HI, R\); + 10: 17 c4 02 0a R5 = BYTEOP3P \(R1:0, R3:2\) \(LO\); + 14: 37 c4 02 00 R0 = BYTEOP3P \(R1:0, R3:2\) \(HI\); + 18: 17 c4 02 22 R1 = BYTEOP3P \(R1:0, R3:2\) \(LO, R\); + 1c: 37 c4 02 24 R2 = BYTEOP3P \(R1:0, R3:2\) \(HI, R\); 00000020 <dual16>: - 20: 0c c4 [4-7][[:xdigit:]] 45 R5=A1.L\+A1.H,R2=A0.L\+A0.H; + 20: 0c c4 [4-7][[:xdigit:]] 45 R5 = A1.L \+ A1.H, R2 = A0.L \+ A0.H; 00000024 <byteop16p>: - 24: 15 c4 82 06 \(R2,R3\)=BYTEOP16P\(R1:0x0,R3:0x2\) ; - 28: 15 c4 82 21 \(R6,R0\)=BYTEOP16P\(R1:0x0,R3:0x2\) \(R\); + 24: 15 c4 82 06 \(R2, R3\) = BYTEOP16P \(R1:0, R3:2\); + 28: 15 c4 82 21 \(R6, R0\) = BYTEOP16P \(R1:0, R3:2\) \(R\); 0000002c <byteop1p>: - 2c: 14 c4 02 0e R7=BYTEOP1P\(R1:0x0,R3:0x2\); - 30: 14 c4 02 44 R2=BYTEOP1P\(R1:0x0,R3:0x2\)\(T\); - 34: 14 c4 02 26 R3=BYTEOP1P\(R1:0x0,R3:0x2\)\(R\); - 38: 14 c4 02 6e R7=BYTEOP1P\(R1:0x0,R3:0x2\)\(T, R\); + 2c: 14 c4 02 0e R7 = BYTEOP1P \(R1:0, R3:2\); + 30: 14 c4 02 44 R2 = BYTEOP1P \(R1:0, R3:2\) \(T\); + 34: 14 c4 02 26 R3 = BYTEOP1P \(R1:0, R3:2\) \(R\); + 38: 14 c4 02 6e R7 = BYTEOP1P \(R1:0, R3:2\) \(T, R\); 0000003c <byteop2p>: - 3c: 16 c4 02 00 R0=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL\); - 40: 36 c4 02 02 R1=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH\); - 44: 16 c4 02 44 R2=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL\); - 48: 36 c4 02 46 R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH\); - 4c: 16 c4 02 28 R4=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL, R\); - 50: 36 c4 02 2a R5=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH, R\); - 54: 16 c4 02 6c R6=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL, R\); - 58: 36 c4 02 6e R7=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH, R\); + 3c: 16 c4 02 00 R0 = BYTEOP2P \(R1:0, R3:2\) \(RNDL\); + 40: 36 c4 02 02 R1 = BYTEOP2P \(R1:0, R3:2\) \(RNDH\); + 44: 16 c4 02 44 R2 = BYTEOP2P \(R1:0, R3:2\) \(TL\); + 48: 36 c4 02 46 R3 = BYTEOP2P \(R1:0, R3:2\) \(TH\); + 4c: 16 c4 02 28 R4 = BYTEOP2P \(R1:0, R3:2\) \(RNDL, R\); + 50: 36 c4 02 2a R5 = BYTEOP2P \(R1:0, R3:2\) \(RNDH, R\); + 54: 16 c4 02 6c R6 = BYTEOP2P \(R1:0, R3:2\) \(TL, R\); + 58: 36 c4 02 6e R7 = BYTEOP2P \(R1:0, R3:2\) \(TH, R\); 0000005c <bytepack>: - 5c: 18 c4 03 0a R5=BYTEPACK\(R0,R3\); + 5c: 18 c4 03 0a R5 = BYTEPACK \(R0, R3\); 00000060 <byteop16m>: - 60: 15 c4 82 45 \(R6,R2\)=BYTEOP16M\(R1:0x0,R3:0x2\) ; - 64: 15 c4 02 6a \(R0,R5\)=BYTEOP16M\(R1:0x0,R3:0x2\) \(R\); + 60: 15 c4 82 45 \(R6, R2\) = BYTEOP16M \(R1:0, R3:2\); + 64: 15 c4 02 6a \(R0, R5\) = BYTEOP16M \(R1:0, R3:2\) \(R\); 00000068 <saa>: - 68: 12 c4 02 00 SAA\(R1:0x0,R3:0x2\) ; - 6c: 12 c4 02 20 SAA\(R1:0x0,R3:0x2\) \(R\); + 68: 12 c4 02 00 SAA \(R1:0, R3:2\); + 6c: 12 c4 02 20 SAA \(R1:0, R3:2\) \(R\); 00000070 <byteunpack>: - 70: 18 c4 c0 45 \(R7,R2\) = BYTEUNPACK R1:0x0 ; - 74: 18 c4 90 69 \(R6,R4\) = BYTEUNPACK R3:0x2 \(R\); + 70: 18 c4 c0 45 \(R7, R2\) = BYTEUNPACK R1:0; + 74: 18 c4 90 69 \(R6, R4\) = BYTEUNPACK R3:2 \(R\); diff --git a/gas/testsuite/gas/bfin/video2.d b/gas/testsuite/gas/bfin/video2.d index 90be24b..19760ec 100644 --- a/gas/testsuite/gas/bfin/video2.d +++ b/gas/testsuite/gas/bfin/video2.d @@ -5,144 +5,144 @@ Disassembly of section .text: 00000000 <.text>: - 0: 0d c6 00 00 R0=ALIGN8\(R0,R0\); - 4: 0d c6 08 00 R0=ALIGN8\(R0,R1\); - 8: 0d c6 01 00 R0=ALIGN8\(R1,R0\); - c: 0d c6 09 00 R0=ALIGN8\(R1,R1\); - 10: 0d c6 11 00 R0=ALIGN8\(R1,R2\); - 14: 0d c6 2c 06 R3=ALIGN8\(R4,R5\); - 18: 0d c6 07 0c R6=ALIGN8\(R7,R0\); - 1c: 0d c6 1a 02 R1=ALIGN8\(R2,R3\); - 20: 0d c6 35 08 R4=ALIGN8\(R5,R6\); - 24: 0d c6 08 0e R7=ALIGN8\(R0,R1\); - 28: 0d c6 23 04 R2=ALIGN8\(R3,R4\); - 2c: 0d c6 3e 0a R5=ALIGN8\(R6,R7\); - 30: 0d c6 00 40 R0=ALIGN16\(R0,R0\); - 34: 0d c6 08 40 R0=ALIGN16\(R0,R1\); - 38: 0d c6 01 40 R0=ALIGN16\(R1,R0\); - 3c: 0d c6 09 40 R0=ALIGN16\(R1,R1\); - 40: 0d c6 11 40 R0=ALIGN16\(R1,R2\); - 44: 0d c6 2c 46 R3=ALIGN16\(R4,R5\); - 48: 0d c6 07 4c R6=ALIGN16\(R7,R0\); - 4c: 0d c6 1a 42 R1=ALIGN16\(R2,R3\); - 50: 0d c6 35 48 R4=ALIGN16\(R5,R6\); - 54: 0d c6 08 4e R7=ALIGN16\(R0,R1\); - 58: 0d c6 23 44 R2=ALIGN16\(R3,R4\); - 5c: 0d c6 3e 4a R5=ALIGN16\(R6,R7\); - 60: 0d c6 00 80 R0=ALIGN24\(R0,R0\); - 64: 0d c6 08 80 R0=ALIGN24\(R0,R1\); - 68: 0d c6 01 80 R0=ALIGN24\(R1,R0\); - 6c: 0d c6 09 80 R0=ALIGN24\(R1,R1\); - 70: 0d c6 11 80 R0=ALIGN24\(R1,R2\); - 74: 0d c6 2c 86 R3=ALIGN24\(R4,R5\); - 78: 0d c6 07 8c R6=ALIGN24\(R7,R0\); - 7c: 0d c6 1a 82 R1=ALIGN24\(R2,R3\); - 80: 0d c6 35 88 R4=ALIGN24\(R5,R6\); - 84: 0d c6 08 8e R7=ALIGN24\(R0,R1\); - 88: 0d c6 23 84 R2=ALIGN24\(R3,R4\); - 8c: 0d c6 3e 8a R5=ALIGN24\(R6,R7\); + 0: 0d c6 00 00 R0 = ALIGN8 \(R0, R0\); + 4: 0d c6 08 00 R0 = ALIGN8 \(R0, R1\); + 8: 0d c6 01 00 R0 = ALIGN8 \(R1, R0\); + c: 0d c6 09 00 R0 = ALIGN8 \(R1, R1\); + 10: 0d c6 11 00 R0 = ALIGN8 \(R1, R2\); + 14: 0d c6 2c 06 R3 = ALIGN8 \(R4, R5\); + 18: 0d c6 07 0c R6 = ALIGN8 \(R7, R0\); + 1c: 0d c6 1a 02 R1 = ALIGN8 \(R2, R3\); + 20: 0d c6 35 08 R4 = ALIGN8 \(R5, R6\); + 24: 0d c6 08 0e R7 = ALIGN8 \(R0, R1\); + 28: 0d c6 23 04 R2 = ALIGN8 \(R3, R4\); + 2c: 0d c6 3e 0a R5 = ALIGN8 \(R6, R7\); + 30: 0d c6 00 40 R0 = ALIGN16 \(R0, R0\); + 34: 0d c6 08 40 R0 = ALIGN16 \(R0, R1\); + 38: 0d c6 01 40 R0 = ALIGN16 \(R1, R0\); + 3c: 0d c6 09 40 R0 = ALIGN16 \(R1, R1\); + 40: 0d c6 11 40 R0 = ALIGN16 \(R1, R2\); + 44: 0d c6 2c 46 R3 = ALIGN16 \(R4, R5\); + 48: 0d c6 07 4c R6 = ALIGN16 \(R7, R0\); + 4c: 0d c6 1a 42 R1 = ALIGN16 \(R2, R3\); + 50: 0d c6 35 48 R4 = ALIGN16 \(R5, R6\); + 54: 0d c6 08 4e R7 = ALIGN16 \(R0, R1\); + 58: 0d c6 23 44 R2 = ALIGN16 \(R3, R4\); + 5c: 0d c6 3e 4a R5 = ALIGN16 \(R6, R7\); + 60: 0d c6 00 80 R0 = ALIGN24 \(R0, R0\); + 64: 0d c6 08 80 R0 = ALIGN24 \(R0, R1\); + 68: 0d c6 01 80 R0 = ALIGN24 \(R1, R0\); + 6c: 0d c6 09 80 R0 = ALIGN24 \(R1, R1\); + 70: 0d c6 11 80 R0 = ALIGN24 \(R1, R2\); + 74: 0d c6 2c 86 R3 = ALIGN24 \(R4, R5\); + 78: 0d c6 07 8c R6 = ALIGN24 \(R7, R0\); + 7c: 0d c6 1a 82 R1 = ALIGN24 \(R2, R3\); + 80: 0d c6 35 88 R4 = ALIGN24 \(R5, R6\); + 84: 0d c6 08 8e R7 = ALIGN24 \(R0, R1\); + 88: 0d c6 23 84 R2 = ALIGN24 \(R3, R4\); + 8c: 0d c6 3e 8a R5 = ALIGN24 \(R6, R7\); 90: 12 c4 00 c0 DISALGNEXCPT; - 94: 17 c4 02 00 R0=BYTEOP3P\(R1:0x0,R3:0x2\)\(LO\); - 98: 37 c4 02 02 R1=BYTEOP3P\(R1:0x0,R3:0x2\)\(HI\); - 9c: 17 c4 02 24 R2=BYTEOP3P\(R1:0x0,R3:0x2\)\(LO, R\); - a0: 37 c4 02 26 R3=BYTEOP3P\(R1:0x0,R3:0x2\)\(HI, R\); - a4: 17 c4 10 08 R4=BYTEOP3P\(R3:0x2,R1:0x0\)\(LO\); - a8: 37 c4 10 0a R5=BYTEOP3P\(R3:0x2,R1:0x0\)\(HI\); - ac: 17 c4 10 2c R6=BYTEOP3P\(R3:0x2,R1:0x0\)\(LO, R\); - b0: 37 c4 10 2e R7=BYTEOP3P\(R3:0x2,R1:0x0\)\(HI, R\); - b4: 0c c4 [0-3][[:xdigit:]] 40 R0=A1.L\+A1.H,R0=A0.L\+A0.H; - b8: 0c c4 [0-3][[:xdigit:]] 42 R0=A1.L\+A1.H,R1=A0.L\+A0.H; - bc: 0c c4 [8|9|a|b][[:xdigit:]] 46 R2=A1.L\+A1.H,R3=A0.L\+A0.H; - c0: 0c c4 [0-3][[:xdigit:]] 4b R4=A1.L\+A1.H,R5=A0.L\+A0.H; - c4: 0c c4 [8|9|a|b][[:xdigit:]] 4f R6=A1.L\+A1.H,R7=A0.L\+A0.H; - c8: 15 c4 d0 01 \(R7,R0\)=BYTEOP16P\(R3:0x2,R1:0x0\) ; - cc: 15 c4 50 04 \(R1,R2\)=BYTEOP16P\(R3:0x2,R1:0x0\) ; - d0: 15 c4 10 02 \(R0,R1\)=BYTEOP16P\(R3:0x2,R1:0x0\) ; - d4: 15 c4 90 06 \(R2,R3\)=BYTEOP16P\(R3:0x2,R1:0x0\) ; - d8: 15 c4 c2 01 \(R7,R0\)=BYTEOP16P\(R1:0x0,R3:0x2\) ; - dc: 15 c4 42 04 \(R1,R2\)=BYTEOP16P\(R1:0x0,R3:0x2\) ; - e0: 15 c4 02 02 \(R0,R1\)=BYTEOP16P\(R1:0x0,R3:0x2\) ; - e4: 15 c4 82 06 \(R2,R3\)=BYTEOP16P\(R1:0x0,R3:0x2\) ; - e8: 15 c4 d0 21 \(R7,R0\)=BYTEOP16P\(R3:0x2,R1:0x0\) \(R\); - ec: 15 c4 50 24 \(R1,R2\)=BYTEOP16P\(R3:0x2,R1:0x0\) \(R\); - f0: 15 c4 10 22 \(R0,R1\)=BYTEOP16P\(R3:0x2,R1:0x0\) \(R\); - f4: 15 c4 90 26 \(R2,R3\)=BYTEOP16P\(R3:0x2,R1:0x0\) \(R\); - f8: 15 c4 c2 21 \(R7,R0\)=BYTEOP16P\(R1:0x0,R3:0x2\) \(R\); - fc: 15 c4 42 24 \(R1,R2\)=BYTEOP16P\(R1:0x0,R3:0x2\) \(R\); - 100: 15 c4 02 22 \(R0,R1\)=BYTEOP16P\(R1:0x0,R3:0x2\) \(R\); - 104: 15 c4 82 26 \(R2,R3\)=BYTEOP16P\(R1:0x0,R3:0x2\) \(R\); - 108: 14 c4 02 06 R3=BYTEOP1P\(R1:0x0,R3:0x2\); - 10c: 14 c4 02 26 R3=BYTEOP1P\(R1:0x0,R3:0x2\)\(R\); - 110: 14 c4 02 46 R3=BYTEOP1P\(R1:0x0,R3:0x2\)\(T\); - 114: 14 c4 02 66 R3=BYTEOP1P\(R1:0x0,R3:0x2\)\(T, R\); - 118: 14 c4 10 00 R0=BYTEOP1P\(R3:0x2,R1:0x0\); - 11c: 14 c4 10 22 R1=BYTEOP1P\(R3:0x2,R1:0x0\)\(R\); - 120: 14 c4 10 44 R2=BYTEOP1P\(R3:0x2,R1:0x0\)\(T\); - 124: 14 c4 10 66 R3=BYTEOP1P\(R3:0x2,R1:0x0\)\(T, R\); - 128: 16 c4 02 06 R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL\); - 12c: 36 c4 02 06 R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH\); - 130: 16 c4 02 46 R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL\); - 134: 36 c4 02 46 R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH\); - 138: 16 c4 02 26 R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL, R\); - 13c: 36 c4 02 26 R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH, R\); - 140: 16 c4 02 66 R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL, R\); - 144: 36 c4 02 66 R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH, R\); - 148: 16 c4 02 00 R0=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL\); - 14c: 36 c4 02 02 R1=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH\); - 150: 16 c4 02 44 R2=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL\); - 154: 36 c4 02 46 R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH\); - 158: 16 c4 02 28 R4=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL, R\); - 15c: 36 c4 02 2a R5=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH, R\); - 160: 16 c4 02 6c R6=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL, R\); - 164: 36 c4 02 6e R7=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH, R\); - 168: 16 c4 12 00 R0=BYTEOP2P\(R3:0x2,R3:0x2\)\(RNDL\); - 16c: 36 c4 12 02 R1=BYTEOP2P\(R3:0x2,R3:0x2\)\(RNDH\); - 170: 16 c4 12 44 R2=BYTEOP2P\(R3:0x2,R3:0x2\)\(TL\); - 174: 36 c4 12 46 R3=BYTEOP2P\(R3:0x2,R3:0x2\)\(TH\); - 178: 16 c4 12 28 R4=BYTEOP2P\(R3:0x2,R3:0x2\)\(RNDL, R\); - 17c: 36 c4 12 2a R5=BYTEOP2P\(R3:0x2,R3:0x2\)\(RNDH, R\); - 180: 16 c4 12 6c R6=BYTEOP2P\(R3:0x2,R3:0x2\)\(TL, R\); - 184: 36 c4 12 6e R7=BYTEOP2P\(R3:0x2,R3:0x2\)\(TH, R\); - 188: 18 c4 00 00 R0=BYTEPACK\(R0,R0\); - 18c: 18 c4 13 02 R1=BYTEPACK\(R2,R3\); - 190: 18 c4 2e 08 R4=BYTEPACK\(R5,R6\); - 194: 18 c4 01 0e R7=BYTEPACK\(R0,R1\); - 198: 18 c4 1c 04 R2=BYTEPACK\(R3,R4\); - 19c: 18 c4 37 0a R5=BYTEPACK\(R6,R7\); - 1a0: 15 c4 50 44 \(R1,R2\)=BYTEOP16M\(R3:0x2,R1:0x0\) ; - 1a4: 15 c4 50 64 \(R1,R2\)=BYTEOP16M\(R3:0x2,R1:0x0\) \(R\); - 1a8: 15 c4 10 42 \(R0,R1\)=BYTEOP16M\(R3:0x2,R1:0x0\) ; - 1ac: 15 c4 90 66 \(R2,R3\)=BYTEOP16M\(R3:0x2,R1:0x0\) \(R\); - 1b0: 15 c4 d0 4a \(R3,R5\)=BYTEOP16M\(R3:0x2,R1:0x0\) ; - 1b4: 15 c4 90 6f \(R6,R7\)=BYTEOP16M\(R3:0x2,R1:0x0\) \(R\); - 1b8: 15 c4 40 44 \(R1,R2\)=BYTEOP16M\(R1:0x0,R1:0x0\) ; - 1bc: 15 c4 40 64 \(R1,R2\)=BYTEOP16M\(R1:0x0,R1:0x0\) \(R\); - 1c0: 15 c4 00 42 \(R0,R1\)=BYTEOP16M\(R1:0x0,R1:0x0\) ; - 1c4: 15 c4 80 66 \(R2,R3\)=BYTEOP16M\(R1:0x0,R1:0x0\) \(R\); - 1c8: 15 c4 c0 4a \(R3,R5\)=BYTEOP16M\(R1:0x0,R1:0x0\) ; - 1cc: 15 c4 80 6f \(R6,R7\)=BYTEOP16M\(R1:0x0,R1:0x0\) \(R\); - 1d0: 15 c4 42 44 \(R1,R2\)=BYTEOP16M\(R1:0x0,R3:0x2\) ; - 1d4: 15 c4 42 64 \(R1,R2\)=BYTEOP16M\(R1:0x0,R3:0x2\) \(R\); - 1d8: 15 c4 02 42 \(R0,R1\)=BYTEOP16M\(R1:0x0,R3:0x2\) ; - 1dc: 15 c4 82 66 \(R2,R3\)=BYTEOP16M\(R1:0x0,R3:0x2\) \(R\); - 1e0: 15 c4 c2 4a \(R3,R5\)=BYTEOP16M\(R1:0x0,R3:0x2\) ; - 1e4: 15 c4 82 6f \(R6,R7\)=BYTEOP16M\(R1:0x0,R3:0x2\) \(R\); - 1e8: 15 c4 52 44 \(R1,R2\)=BYTEOP16M\(R3:0x2,R3:0x2\) ; - 1ec: 15 c4 52 64 \(R1,R2\)=BYTEOP16M\(R3:0x2,R3:0x2\) \(R\); - 1f0: 15 c4 12 42 \(R0,R1\)=BYTEOP16M\(R3:0x2,R3:0x2\) ; - 1f4: 15 c4 92 66 \(R2,R3\)=BYTEOP16M\(R3:0x2,R3:0x2\) \(R\); - 1f8: 15 c4 d2 4a \(R3,R5\)=BYTEOP16M\(R3:0x2,R3:0x2\) ; - 1fc: 15 c4 92 6f \(R6,R7\)=BYTEOP16M\(R3:0x2,R3:0x2\) \(R\); - 200: 12 cc 02 00 SAA\(R1:0x0,R3:0x2\) \|\| R0=\[I0\+\+\] \|\| R2=\[I1\+\+\]; + 94: 17 c4 02 00 R0 = BYTEOP3P \(R1:0, R3:2\) \(LO\); + 98: 37 c4 02 02 R1 = BYTEOP3P \(R1:0, R3:2\) \(HI\); + 9c: 17 c4 02 24 R2 = BYTEOP3P \(R1:0, R3:2\) \(LO, R\); + a0: 37 c4 02 26 R3 = BYTEOP3P \(R1:0, R3:2\) \(HI, R\); + a4: 17 c4 10 08 R4 = BYTEOP3P \(R3:2, R1:0\) \(LO\); + a8: 37 c4 10 0a R5 = BYTEOP3P \(R3:2, R1:0\) \(HI\); + ac: 17 c4 10 2c R6 = BYTEOP3P \(R3:2, R1:0\) \(LO, R\); + b0: 37 c4 10 2e R7 = BYTEOP3P \(R3:2, R1:0\) \(HI, R\); + b4: 0c c4 [0-3][[:xdigit:]] 40 R0 = A1.L \+ A1.H, R0 = A0.L \+ A0.H; + b8: 0c c4 [0-3][[:xdigit:]] 42 R0 = A1.L \+ A1.H, R1 = A0.L \+ A0.H; + bc: 0c c4 [8|9|a|b][[:xdigit:]] 46 R2 = A1.L \+ A1.H, R3 = A0.L \+ A0.H; + c0: 0c c4 [0-3][[:xdigit:]] 4b R4 = A1.L \+ A1.H, R5 = A0.L \+ A0.H; + c4: 0c c4 [8|9|a|b][[:xdigit:]] 4f R6 = A1.L \+ A1.H, R7 = A0.L \+ A0.H; + c8: 15 c4 d0 01 \(R7, R0\) = BYTEOP16P \(R3:2, R1:0\); + cc: 15 c4 50 04 \(R1, R2\) = BYTEOP16P \(R3:2, R1:0\); + d0: 15 c4 10 02 \(R0, R1\) = BYTEOP16P \(R3:2, R1:0\); + d4: 15 c4 90 06 \(R2, R3\) = BYTEOP16P \(R3:2, R1:0\); + d8: 15 c4 c2 01 \(R7, R0\) = BYTEOP16P \(R1:0, R3:2\); + dc: 15 c4 42 04 \(R1, R2\) = BYTEOP16P \(R1:0, R3:2\); + e0: 15 c4 02 02 \(R0, R1\) = BYTEOP16P \(R1:0, R3:2\); + e4: 15 c4 82 06 \(R2, R3\) = BYTEOP16P \(R1:0, R3:2\); + e8: 15 c4 d0 21 \(R7, R0\) = BYTEOP16P \(R3:2, R1:0\) \(R\); + ec: 15 c4 50 24 \(R1, R2\) = BYTEOP16P \(R3:2, R1:0\) \(R\); + f0: 15 c4 10 22 \(R0, R1\) = BYTEOP16P \(R3:2, R1:0\) \(R\); + f4: 15 c4 90 26 \(R2, R3\) = BYTEOP16P \(R3:2, R1:0\) \(R\); + f8: 15 c4 c2 21 \(R7, R0\) = BYTEOP16P \(R1:0, R3:2\) \(R\); + fc: 15 c4 42 24 \(R1, R2\) = BYTEOP16P \(R1:0, R3:2\) \(R\); + 100: 15 c4 02 22 \(R0, R1\) = BYTEOP16P \(R1:0, R3:2\) \(R\); + 104: 15 c4 82 26 \(R2, R3\) = BYTEOP16P \(R1:0, R3:2\) \(R\); + 108: 14 c4 02 06 R3 = BYTEOP1P \(R1:0, R3:2\); + 10c: 14 c4 02 26 R3 = BYTEOP1P \(R1:0, R3:2\) \(R\); + 110: 14 c4 02 46 R3 = BYTEOP1P \(R1:0, R3:2\) \(T\); + 114: 14 c4 02 66 R3 = BYTEOP1P \(R1:0, R3:2\) \(T, R\); + 118: 14 c4 10 00 R0 = BYTEOP1P \(R3:2, R1:0\); + 11c: 14 c4 10 22 R1 = BYTEOP1P \(R3:2, R1:0\) \(R\); + 120: 14 c4 10 44 R2 = BYTEOP1P \(R3:2, R1:0\) \(T\); + 124: 14 c4 10 66 R3 = BYTEOP1P \(R3:2, R1:0\) \(T, R\); + 128: 16 c4 02 06 R3 = BYTEOP2P \(R1:0, R3:2\) \(RNDL\); + 12c: 36 c4 02 06 R3 = BYTEOP2P \(R1:0, R3:2\) \(RNDH\); + 130: 16 c4 02 46 R3 = BYTEOP2P \(R1:0, R3:2\) \(TL\); + 134: 36 c4 02 46 R3 = BYTEOP2P \(R1:0, R3:2\) \(TH\); + 138: 16 c4 02 26 R3 = BYTEOP2P \(R1:0, R3:2\) \(RNDL, R\); + 13c: 36 c4 02 26 R3 = BYTEOP2P \(R1:0, R3:2\) \(RNDH, R\); + 140: 16 c4 02 66 R3 = BYTEOP2P \(R1:0, R3:2\) \(TL, R\); + 144: 36 c4 02 66 R3 = BYTEOP2P \(R1:0, R3:2\) \(TH, R\); + 148: 16 c4 02 00 R0 = BYTEOP2P \(R1:0, R3:2\) \(RNDL\); + 14c: 36 c4 02 02 R1 = BYTEOP2P \(R1:0, R3:2\) \(RNDH\); + 150: 16 c4 02 44 R2 = BYTEOP2P \(R1:0, R3:2\) \(TL\); + 154: 36 c4 02 46 R3 = BYTEOP2P \(R1:0, R3:2\) \(TH\); + 158: 16 c4 02 28 R4 = BYTEOP2P \(R1:0, R3:2\) \(RNDL, R\); + 15c: 36 c4 02 2a R5 = BYTEOP2P \(R1:0, R3:2\) \(RNDH, R\); + 160: 16 c4 02 6c R6 = BYTEOP2P \(R1:0, R3:2\) \(TL, R\); + 164: 36 c4 02 6e R7 = BYTEOP2P \(R1:0, R3:2\) \(TH, R\); + 168: 16 c4 12 00 R0 = BYTEOP2P \(R3:2, R3:2\) \(RNDL\); + 16c: 36 c4 12 02 R1 = BYTEOP2P \(R3:2, R3:2\) \(RNDH\); + 170: 16 c4 12 44 R2 = BYTEOP2P \(R3:2, R3:2\) \(TL\); + 174: 36 c4 12 46 R3 = BYTEOP2P \(R3:2, R3:2\) \(TH\); + 178: 16 c4 12 28 R4 = BYTEOP2P \(R3:2, R3:2\) \(RNDL, R\); + 17c: 36 c4 12 2a R5 = BYTEOP2P \(R3:2, R3:2\) \(RNDH, R\); + 180: 16 c4 12 6c R6 = BYTEOP2P \(R3:2, R3:2\) \(TL, R\); + 184: 36 c4 12 6e R7 = BYTEOP2P \(R3:2, R3:2\) \(TH, R\); + 188: 18 c4 00 00 R0 = BYTEPACK \(R0, R0\); + 18c: 18 c4 13 02 R1 = BYTEPACK \(R2, R3\); + 190: 18 c4 2e 08 R4 = BYTEPACK \(R5, R6\); + 194: 18 c4 01 0e R7 = BYTEPACK \(R0, R1\); + 198: 18 c4 1c 04 R2 = BYTEPACK \(R3, R4\); + 19c: 18 c4 37 0a R5 = BYTEPACK \(R6, R7\); + 1a0: 15 c4 50 44 \(R1, R2\) = BYTEOP16M \(R3:2, R1:0\); + 1a4: 15 c4 50 64 \(R1, R2\) = BYTEOP16M \(R3:2, R1:0\) \(R\); + 1a8: 15 c4 10 42 \(R0, R1\) = BYTEOP16M \(R3:2, R1:0\); + 1ac: 15 c4 90 66 \(R2, R3\) = BYTEOP16M \(R3:2, R1:0\) \(R\); + 1b0: 15 c4 d0 4a \(R3, R5\) = BYTEOP16M \(R3:2, R1:0\); + 1b4: 15 c4 90 6f \(R6, R7\) = BYTEOP16M \(R3:2, R1:0\) \(R\); + 1b8: 15 c4 40 44 \(R1, R2\) = BYTEOP16M \(R1:0, R1:0\); + 1bc: 15 c4 40 64 \(R1, R2\) = BYTEOP16M \(R1:0, R1:0\) \(R\); + 1c0: 15 c4 00 42 \(R0, R1\) = BYTEOP16M \(R1:0, R1:0\); + 1c4: 15 c4 80 66 \(R2, R3\) = BYTEOP16M \(R1:0, R1:0\) \(R\); + 1c8: 15 c4 c0 4a \(R3, R5\) = BYTEOP16M \(R1:0, R1:0\); + 1cc: 15 c4 80 6f \(R6, R7\) = BYTEOP16M \(R1:0, R1:0\) \(R\); + 1d0: 15 c4 42 44 \(R1, R2\) = BYTEOP16M \(R1:0, R3:2\); + 1d4: 15 c4 42 64 \(R1, R2\) = BYTEOP16M \(R1:0, R3:2\) \(R\); + 1d8: 15 c4 02 42 \(R0, R1\) = BYTEOP16M \(R1:0, R3:2\); + 1dc: 15 c4 82 66 \(R2, R3\) = BYTEOP16M \(R1:0, R3:2\) \(R\); + 1e0: 15 c4 c2 4a \(R3, R5\) = BYTEOP16M \(R1:0, R3:2\); + 1e4: 15 c4 82 6f \(R6, R7\) = BYTEOP16M \(R1:0, R3:2\) \(R\); + 1e8: 15 c4 52 44 \(R1, R2\) = BYTEOP16M \(R3:2, R3:2\); + 1ec: 15 c4 52 64 \(R1, R2\) = BYTEOP16M \(R3:2, R3:2\) \(R\); + 1f0: 15 c4 12 42 \(R0, R1\) = BYTEOP16M \(R3:2, R3:2\); + 1f4: 15 c4 92 66 \(R2, R3\) = BYTEOP16M \(R3:2, R3:2\) \(R\); + 1f8: 15 c4 d2 4a \(R3, R5\) = BYTEOP16M \(R3:2, R3:2\); + 1fc: 15 c4 92 6f \(R6, R7\) = BYTEOP16M \(R3:2, R3:2\) \(R\); + 200: 12 cc 02 00 SAA \(R1:0, R3:2\) \|\| R0 = \[I0\+\+\] \|\| R2 = \[I1\+\+\]; 204: 00 9c 0a 9c - 208: 12 cc 02 20 SAA\(R1:0x0,R3:0x2\) \(R\) \|\| R1=\[I0\+\+\] \|\| R3=\[I1\+\+\]; + 208: 12 cc 02 20 SAA \(R1:0, R3:2\) \(R\) \|\| R1 = \[I0\+\+\] \|\| R3 = \[I1\+\+\]; 20c: 01 9c 0b 9c - 210: 12 c4 02 00 SAA\(R1:0x0,R3:0x2\) ; - 214: 18 c4 80 4b \(R6,R5\) = BYTEUNPACK R1:0x0 ; - 218: 18 c4 80 6b \(R6,R5\) = BYTEUNPACK R1:0x0 \(R\); - 21c: 18 c4 90 4b \(R6,R5\) = BYTEUNPACK R3:0x2 ; - 220: 18 c4 90 6b \(R6,R5\) = BYTEUNPACK R3:0x2 \(R\); - 224: 18 c4 00 42 \(R0,R1\) = BYTEUNPACK R1:0x0 ; - 228: 18 c4 80 66 \(R2,R3\) = BYTEUNPACK R1:0x0 \(R\); - 22c: 18 c4 10 4b \(R4,R5\) = BYTEUNPACK R3:0x2 ; - 230: 18 c4 90 6f \(R6,R7\) = BYTEUNPACK R3:0x2 \(R\); + 210: 12 c4 02 00 SAA \(R1:0, R3:2\); + 214: 18 c4 80 4b \(R6, R5\) = BYTEUNPACK R1:0; + 218: 18 c4 80 6b \(R6, R5\) = BYTEUNPACK R1:0 \(R\); + 21c: 18 c4 90 4b \(R6, R5\) = BYTEUNPACK R3:2; + 220: 18 c4 90 6b \(R6, R5\) = BYTEUNPACK R3:2 \(R\); + 224: 18 c4 00 42 \(R0, R1\) = BYTEUNPACK R1:0; + 228: 18 c4 80 66 \(R2, R3\) = BYTEUNPACK R1:0 \(R\); + 22c: 18 c4 10 4b \(R4, R5\) = BYTEUNPACK R3:2; + 230: 18 c4 90 6f \(R6, R7\) = BYTEUNPACK R3:2 \(R\); diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8360494..fdbaedb 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -20,6 +20,27 @@ * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for multiply and multiply-accumulate to data register instruction. + * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d, + c_imm32, c_huimm32e): Define. + (constant_formats): Add flags for printing decimal, leading spaces, and + exact symbols. + (comment, parallel): Add global flags in all disassembly. + (fmtconst): Take advantage of new flags, and print default in hex. + (fmtconst_val): Likewise. + (decode_macfunc): Be consistant with spaces, tabs, comments, + capitalization in disassembly, fix minor coding style issues. + (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise. + (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0, + decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0, + decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0, + decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0, + decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0, + decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0, + decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0, + decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0, + decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0, + _print_insn_bfin, print_insn_bfin): Likewise. + 2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> * aclocal.m4: Regenerate. diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c index 046027e..d74fa58 100644 --- a/opcodes/bfin-dis.c +++ b/opcodes/bfin-dis.c @@ -56,10 +56,10 @@ typedef unsigned int bu32; typedef enum { c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4, - c_imm4, c_uimm4s4, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_uimm5, c_imm6, - c_imm7, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10, - c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4, - c_uimm16, c_pcrel24, c_uimm32, c_huimm32, + c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6, + c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10, + c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4, + c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e, } const_forms_t; static struct @@ -73,49 +73,62 @@ static struct char offset; char negative; char positive; + char decimal; + char leading; + char exact; } constant_formats[] = { - { "0", 0, 0, 1, 0, 0, 0, 0, 0}, - { "1", 0, 0, 1, 0, 0, 0, 0, 0}, - { "4", 0, 0, 1, 0, 0, 0, 0, 0}, - { "2", 0, 0, 1, 0, 0, 0, 0, 0}, - { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0}, - { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0}, - { "imm3", 3, 0, 1, 0, 0, 0, 0, 0}, - { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0}, - { "imm4", 4, 0, 1, 0, 0, 0, 0, 0}, - { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1}, - { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0}, - { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1}, - { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0}, - { "imm5", 5, 0, 1, 0, 0, 0, 0, 0}, - { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0}, - { "imm6", 6, 0, 1, 0, 0, 0, 0, 0}, - { "imm7", 7, 0, 1, 0, 0, 0, 0, 0}, - { "imm8", 8, 0, 1, 0, 0, 0, 0, 0}, - { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0}, - { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0}, - { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0}, - { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0}, - { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0}, - { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0}, - { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0}, - { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0}, - { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0}, - { "imm16", 16, 0, 1, 0, 0, 0, 0, 0}, - { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0}, - { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0}, - { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0}, - { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0}, - { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0}, - { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0}, - { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0}, - { "huimm16", 32, 1, 0, 0, 0, 0, 0, 0} + { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0}, + { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0}, + { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0}, + { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0}, + { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0}, + { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0}, + { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0}, + { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0}, + { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0}, + { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0}, + { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0}, + { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, + { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, + { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0}, + { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0}, + { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0}, + { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0}, + { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0}, + { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, + { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0}, + { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1}, }; int _print_insn_bfin (bfd_vma pc, disassemble_info * outf); int print_insn_bfin (bfd_vma pc, disassemble_info * outf); +static char comment = 0; +static char parallel = 0; + static char * fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info * outf) { @@ -128,8 +141,16 @@ fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info * outf) if (constant_formats[cf].pcrel) ea += pc; - outf->print_address_func (ea, outf); - return ""; + if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact) + { + outf->print_address_func (ea, outf); + return ""; + } + else + { + sprintf (buf, "%lx", x); + return buf; + } } /* Negative constants have an implied sign bit. */ @@ -149,10 +170,24 @@ fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info * outf) if (constant_formats[cf].scale) x <<= constant_formats[cf].scale; - if (constant_formats[cf].issigned && x < 0) - sprintf (buf, "%ld", x); + if (constant_formats[cf].decimal) + { + if (constant_formats[cf].leading) + { + char ps[10]; + sprintf (ps, "%%%ii", constant_formats[cf].leading); + sprintf (buf, ps, x); + } + else + sprintf (buf, "%li", x); + } else - sprintf (buf, "0x%lx", x); + { + if (constant_formats[cf].issigned && x < 0) + sprintf (buf, "-0x%x", abs (x)); + else + sprintf (buf, "0x%lx", x); + } return buf; } @@ -163,11 +198,11 @@ fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc) if (0 && constant_formats[cf].reloc) { bu32 ea = (((constant_formats[cf].pcrel - ? SIGNEXTEND (x, constant_formats[cf].nbits) - : x) + constant_formats[cf].offset) - << constant_formats[cf].scale); + ? SIGNEXTEND (x, constant_formats[cf].nbits) + : x) + constant_formats[cf].offset) + << constant_formats[cf].scale); if (constant_formats[cf].pcrel) - ea += pc; + ea += pc; return ea; } @@ -228,7 +263,7 @@ static char *reg_names[] = "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3", - "P4", "P5", "SP", "FP", "A0.x", "A1.x", "A0.w", "A1.w", + "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W", "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1", "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3", @@ -402,6 +437,7 @@ static enum machine_registers decode_allregs[] = #define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x]) #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf) +#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf) #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf) #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf) #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf) @@ -411,6 +447,7 @@ static enum machine_registers decode_allregs[] = #define rimm16(x) fmtconst (c_rimm16, x, 0, outf) #define huimm16(x) fmtconst (c_huimm16, x, 0, outf) #define imm16(x) fmtconst (c_imm16, x, 0, outf) +#define imm16d(x) fmtconst (c_imm16d, x, 0, outf) #define uimm2(x) fmtconst (c_uimm2, x, 0, outf) #define uimm3(x) fmtconst (c_uimm3, x, 0, outf) #define luimm16(x) fmtconst (c_luimm16, x, 0, outf) @@ -421,18 +458,24 @@ static enum machine_registers decode_allregs[] = #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf) #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf) #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf) +#define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf) #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf) #define imm3(x) fmtconst (c_imm3, x, 0, outf) #define imm4(x) fmtconst (c_imm4, x, 0, outf) #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf) #define imm5(x) fmtconst (c_imm5, x, 0, outf) +#define imm5d(x) fmtconst (c_imm5d, x, 0, outf) #define imm6(x) fmtconst (c_imm6, x, 0, outf) #define imm7(x) fmtconst (c_imm7, x, 0, outf) +#define imm7d(x) fmtconst (c_imm7d, x, 0, outf) #define imm8(x) fmtconst (c_imm8, x, 0, outf) #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf) #define uimm16(x) fmtconst (c_uimm16, x, 0, outf) #define uimm32(x) fmtconst (c_uimm32, x, 0, outf) +#define imm32(x) fmtconst (c_imm32, x, 0, outf) #define huimm32(x) fmtconst (c_huimm32, x, 0, outf) +#define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf) +#define imm7_val(x) fmtconst_val (c_imm7, x, 0) #define imm16_val(x) fmtconst_val (c_uimm16, x, 0) #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0) @@ -445,47 +488,47 @@ static void amod0 (int s0, int x0, disassemble_info *outf) { if (s0 == 1 && x0 == 0) - OUTS (outf, "(S)"); + OUTS (outf, " (S)"); else if (s0 == 0 && x0 == 1) - OUTS (outf, "(CO)"); + OUTS (outf, " (CO)"); else if (s0 == 1 && x0 == 1) - OUTS (outf, "(SCO)"); + OUTS (outf, " (SCO)"); } static void amod1 (int s0, int x0, disassemble_info *outf) { if (s0 == 0 && x0 == 0) - OUTS (outf, "(NS)"); + OUTS (outf, " (NS)"); else if (s0 == 1 && x0 == 0) - OUTS (outf, "(S)"); + OUTS (outf, " (S)"); } static void amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf) { if (s0 == 1 && x0 == 0 && aop0 == 0) - OUTS (outf, "(S)"); + OUTS (outf, " (S)"); else if (s0 == 0 && x0 == 1 && aop0 == 0) - OUTS (outf, "(CO)"); + OUTS (outf, " (CO)"); else if (s0 == 1 && x0 == 1 && aop0 == 0) - OUTS (outf, "(SCO)"); + OUTS (outf, " (SCO)"); else if (s0 == 0 && x0 == 0 && aop0 == 2) - OUTS (outf, "(ASR)"); + OUTS (outf, " (ASR)"); else if (s0 == 1 && x0 == 0 && aop0 == 2) - OUTS (outf, "(S,ASR)"); + OUTS (outf, " (S, ASR)"); else if (s0 == 0 && x0 == 1 && aop0 == 2) - OUTS (outf, "(CO,ASR)"); + OUTS (outf, " (CO, ASR)"); else if (s0 == 1 && x0 == 1 && aop0 == 2) - OUTS (outf, "(SCO,ASR)"); + OUTS (outf, " (SCO, ASR)"); else if (s0 == 0 && x0 == 0 && aop0 == 3) - OUTS (outf, "(ASL)"); + OUTS (outf, " (ASL)"); else if (s0 == 1 && x0 == 0 && aop0 == 3) - OUTS (outf, "(S,ASL)"); + OUTS (outf, " (S, ASL)"); else if (s0 == 0 && x0 == 1 && aop0 == 3) - OUTS (outf, "(CO,ASL)"); + OUTS (outf, " (CO, ASL)"); else if (s0 == 1 && x0 == 1 && aop0 == 3) - OUTS (outf, "(SCO,ASL)"); + OUTS (outf, " (SCO, ASL)"); } static void @@ -505,7 +548,7 @@ static void aligndir (int r0, disassemble_info *outf) { if (r0 == 1) - OUTS (outf, "(R)"); + OUTS (outf, " (R)"); } static int @@ -536,9 +579,9 @@ decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemb char *sop = "<unknown op>"; if (which) - a = "a1"; + a = "A1"; else - a = "a0"; + a = "A0"; if (op == 3) { @@ -548,16 +591,14 @@ decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemb switch (op) { - case 0: sop = "="; break; - case 1: sop = "+="; break; - case 2: sop = "-="; break; + case 0: sop = " = "; break; + case 1: sop = " += "; break; + case 2: sop = " -= "; break; default: break; } OUTS (outf, a); - OUTS (outf, " "); OUTS (outf, sop); - OUTS (outf, " "); decode_multfunc (h0, h1, src0, src1, outf); return 0; @@ -676,19 +717,19 @@ get_allreg (int grp, int reg) case 7: return &LREG (reg & 3); break; default: switch (fullreg) - { - case 32: return &saved_state.a0x; - case 33: return &saved_state.a0w; - case 34: return &saved_state.a1x; - case 35: return &saved_state.a1w; - case 39: return &saved_state.rets; - case 48: return &LC0REG; - case 49: return <0REG; - case 50: return &LB0REG; - case 51: return &LC1REG; - case 52: return <1REG; - case 53: return &LB1REG; - } + { + case 32: return &saved_state.a0x; + case 33: return &saved_state.a0w; + case 34: return &saved_state.a1x; + case 35: return &saved_state.a1w; + case 39: return &saved_state.rets; + case 48: return &LC0REG; + case 49: return <0REG; + case 50: return &LB0REG; + case 51: return &LC1REG; + case 52: return <1REG; + case 53: return &LB1REG; + } return 0; } } @@ -725,51 +766,51 @@ decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf) OUTS (outf, "EMUEXCPT"); else if (prgfunc == 3) { - OUTS (outf, "CLI "); + OUTS (outf, "CLI "); OUTS (outf, dregs (poprnd)); } else if (prgfunc == 4) { - OUTS (outf, "STI "); + OUTS (outf, "STI "); OUTS (outf, dregs (poprnd)); } else if (prgfunc == 5) { - OUTS (outf, "JUMP ("); + OUTS (outf, "JUMP ("); OUTS (outf, pregs (poprnd)); OUTS (outf, ")"); } else if (prgfunc == 6) { - OUTS (outf, "CALL ("); + OUTS (outf, "CALL ("); OUTS (outf, pregs (poprnd)); OUTS (outf, ")"); } else if (prgfunc == 7) { - OUTS (outf, "CALL (PC+"); + OUTS (outf, "CALL (PC + "); OUTS (outf, pregs (poprnd)); OUTS (outf, ")"); } else if (prgfunc == 8) { - OUTS (outf, "JUMP (PC+"); + OUTS (outf, "JUMP (PC + "); OUTS (outf, pregs (poprnd)); OUTS (outf, ")"); } else if (prgfunc == 9) { - OUTS (outf, "RAISE "); + OUTS (outf, "RAISE "); OUTS (outf, uimm4 (poprnd)); } else if (prgfunc == 10) { - OUTS (outf, "EXCPT "); + OUTS (outf, "EXCPT "); OUTS (outf, uimm4 (poprnd)); } else if (prgfunc == 11) { - OUTS (outf, "TESTSET ("); + OUTS (outf, "TESTSET ("); OUTS (outf, pregs (poprnd)); OUTS (outf, ")"); } @@ -880,49 +921,45 @@ decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf) int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask); int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask); int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask); - char ps[5], ds[5]; - - sprintf (ps, "%d", pr); - sprintf (ds, "%d", dr); if (W == 1 && d == 1 && p == 1) { OUTS (outf, "[--SP] = (R7:"); - OUTS (outf, ds); + OUTS (outf, imm5d (dr)); OUTS (outf, ", P5:"); - OUTS (outf, ps); + OUTS (outf, imm5d (pr)); OUTS (outf, ")"); } else if (W == 1 && d == 1 && p == 0) { OUTS (outf, "[--SP] = (R7:"); - OUTS (outf, ds); + OUTS (outf, imm5d (dr)); OUTS (outf, ")"); } else if (W == 1 && d == 0 && p == 1) { OUTS (outf, "[--SP] = (P5:"); - OUTS (outf, ps); + OUTS (outf, imm5d (pr)); OUTS (outf, ")"); } else if (W == 0 && d == 1 && p == 1) { OUTS (outf, "(R7:"); - OUTS (outf, ds); + OUTS (outf, imm5d (dr)); OUTS (outf, ", P5:"); - OUTS (outf, ps); + OUTS (outf, imm5d (pr)); OUTS (outf, ") = [SP++]"); } else if (W == 0 && d == 1 && p == 0) { OUTS (outf, "(R7:"); - OUTS (outf, ds); + OUTS (outf, imm5d (dr)); OUTS (outf, ") = [SP++]"); } else if (W == 0 && d == 0 && p == 1) { OUTS (outf, "(P5:"); - OUTS (outf, ps); + OUTS (outf, imm5d (pr)); OUTS (outf, ") = [SP++]"); } else @@ -952,7 +989,7 @@ decode_ccMV_0 (TIword iw0, disassemble_info *outf) } else if (T == 0) { - OUTS (outf, "IF ! CC "); + OUTS (outf, "IF !CC "); OUTS (outf, gregs (dst, d)); OUTS (outf, " = "); OUTS (outf, gregs (src, s)); @@ -977,160 +1014,160 @@ decode_CCflag_0 (TIword iw0, disassemble_info *outf) if (opc == 0 && I == 0 && G == 0) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, dregs (x)); - OUTS (outf, "=="); + OUTS (outf, " == "); OUTS (outf, dregs (y)); } else if (opc == 1 && I == 0 && G == 0) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, dregs (x)); - OUTS (outf, "<"); + OUTS (outf, " < "); OUTS (outf, dregs (y)); } else if (opc == 2 && I == 0 && G == 0) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, dregs (x)); - OUTS (outf, "<="); + OUTS (outf, " <= "); OUTS (outf, dregs (y)); } else if (opc == 3 && I == 0 && G == 0) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, dregs (x)); - OUTS (outf, "<"); + OUTS (outf, " < "); OUTS (outf, dregs (y)); - OUTS (outf, "(IU)"); + OUTS (outf, " (IU)"); } else if (opc == 4 && I == 0 && G == 0) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, dregs (x)); - OUTS (outf, "<="); + OUTS (outf, " <= "); OUTS (outf, dregs (y)); - OUTS (outf, "(IU)"); + OUTS (outf, " (IU)"); } else if (opc == 0 && I == 1 && G == 0) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, dregs (x)); - OUTS (outf, "=="); + OUTS (outf, " == "); OUTS (outf, imm3 (y)); } else if (opc == 1 && I == 1 && G == 0) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, dregs (x)); - OUTS (outf, "<"); + OUTS (outf, " < "); OUTS (outf, imm3 (y)); } else if (opc == 2 && I == 1 && G == 0) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, dregs (x)); - OUTS (outf, "<="); + OUTS (outf, " <= "); OUTS (outf, imm3 (y)); } else if (opc == 3 && I == 1 && G == 0) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, dregs (x)); - OUTS (outf, "<"); + OUTS (outf, " < "); OUTS (outf, uimm3 (y)); - OUTS (outf, "(IU)"); + OUTS (outf, " (IU)"); } else if (opc == 4 && I == 1 && G == 0) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, dregs (x)); - OUTS (outf, "<="); + OUTS (outf, " <= "); OUTS (outf, uimm3 (y)); - OUTS (outf, "(IU)"); + OUTS (outf, " (IU)"); } else if (opc == 0 && I == 0 && G == 1) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, pregs (x)); - OUTS (outf, "=="); + OUTS (outf, " == "); OUTS (outf, pregs (y)); } else if (opc == 1 && I == 0 && G == 1) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, pregs (x)); - OUTS (outf, "<"); + OUTS (outf, " < "); OUTS (outf, pregs (y)); } else if (opc == 2 && I == 0 && G == 1) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, pregs (x)); - OUTS (outf, "<="); + OUTS (outf, " <= "); OUTS (outf, pregs (y)); } else if (opc == 3 && I == 0 && G == 1) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, pregs (x)); - OUTS (outf, "<"); + OUTS (outf, " < "); OUTS (outf, pregs (y)); - OUTS (outf, "(IU)"); + OUTS (outf, " (IU)"); } else if (opc == 4 && I == 0 && G == 1) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, pregs (x)); - OUTS (outf, "<="); + OUTS (outf, " <= "); OUTS (outf, pregs (y)); - OUTS (outf, "(IU)"); + OUTS (outf, " (IU)"); } else if (opc == 0 && I == 1 && G == 1) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, pregs (x)); - OUTS (outf, "=="); + OUTS (outf, " == "); OUTS (outf, imm3 (y)); } else if (opc == 1 && I == 1 && G == 1) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, pregs (x)); - OUTS (outf, "<"); + OUTS (outf, " < "); OUTS (outf, imm3 (y)); } else if (opc == 2 && I == 1 && G == 1) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, pregs (x)); - OUTS (outf, "<="); + OUTS (outf, " <= "); OUTS (outf, imm3 (y)); } else if (opc == 3 && I == 1 && G == 1) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, pregs (x)); - OUTS (outf, "<"); + OUTS (outf, " < "); OUTS (outf, uimm3 (y)); - OUTS (outf, "(IU)"); + OUTS (outf, " (IU)"); } else if (opc == 4 && I == 1 && G == 1) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, pregs (x)); - OUTS (outf, "<="); + OUTS (outf, " <= "); OUTS (outf, uimm3 (y)); - OUTS (outf, "(IU)"); + OUTS (outf, " (IU)"); } else if (opc == 5 && I == 0 && G == 0) - OUTS (outf, "CC=A0==A1"); + OUTS (outf, "CC = A0 == A1"); else if (opc == 6 && I == 0 && G == 0) - OUTS (outf, "CC=A0<A1"); + OUTS (outf, "CC = A0 < A1"); else if (opc == 7 && I == 0 && G == 0) - OUTS (outf, "CC=A0<=A1"); + OUTS (outf, "CC = A0 <= A1"); else return 0; @@ -1150,15 +1187,15 @@ decode_CC2dreg_0 (TIword iw0, disassemble_info *outf) if (op == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=CC"); + OUTS (outf, " = CC"); } else if (op == 1) { - OUTS (outf, "CC="); + OUTS (outf, "CC = "); OUTS (outf, dregs (reg)); } else if (op == 3) - OUTS (outf, "CC=!CC"); + OUTS (outf, "CC = !CC"); else return 0; @@ -1183,38 +1220,38 @@ decode_CC2stat_0 (TIword iw0, disassemble_info *outf) } else if (op == 1 && D == 0) { - OUTS (outf, "CC|="); + OUTS (outf, "CC |= "); OUTS (outf, statbits (cbit)); } else if (op == 2 && D == 0) { - OUTS (outf, "CC&="); + OUTS (outf, "CC &= "); OUTS (outf, statbits (cbit)); } else if (op == 3 && D == 0) { - OUTS (outf, "CC^="); + OUTS (outf, "CC ^= "); OUTS (outf, statbits (cbit)); } else if (op == 0 && D == 1) { OUTS (outf, statbits (cbit)); - OUTS (outf, "=CC"); + OUTS (outf, " = CC"); } else if (op == 1 && D == 1) { OUTS (outf, statbits (cbit)); - OUTS (outf, "|=CC"); + OUTS (outf, " |= CC"); } else if (op == 2 && D == 1) { OUTS (outf, statbits (cbit)); - OUTS (outf, "&=CC"); + OUTS (outf, " &= CC"); } else if (op == 3 && D == 1) { OUTS (outf, statbits (cbit)); - OUTS (outf, "^=CC"); + OUTS (outf, " ^= CC"); } else return 0; @@ -1235,24 +1272,24 @@ decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf) if (T == 1 && B == 1) { - OUTS (outf, "IF CC JUMP "); + OUTS (outf, "IF CC JUMP 0x"); OUTS (outf, pcrel10 (offset)); - OUTS (outf, "(BP)"); + OUTS (outf, " (BP)"); } else if (T == 0 && B == 1) { - OUTS (outf, "IF ! CC JUMP "); + OUTS (outf, "IF !CC JUMP 0x"); OUTS (outf, pcrel10 (offset)); - OUTS (outf, "(BP)"); + OUTS (outf, " (BP)"); } else if (T == 1) { - OUTS (outf, "IF CC JUMP "); + OUTS (outf, "IF CC JUMP 0x"); OUTS (outf, pcrel10 (offset)); } else if (T == 0) { - OUTS (outf, "IF ! CC JUMP "); + OUTS (outf, "IF !CC JUMP 0x"); OUTS (outf, pcrel10 (offset)); } else @@ -1270,7 +1307,7 @@ decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf) +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask); - OUTS (outf, "JUMP.S "); + OUTS (outf, "JUMP.S 0x"); OUTS (outf, pcrel12 (offset)); return 2; } @@ -1288,7 +1325,7 @@ decode_REGMV_0 (TIword iw0, disassemble_info *outf) int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask); OUTS (outf, allregs (dst, gd)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, allregs (src, gs)); return 2; } @@ -1307,99 +1344,99 @@ decode_ALU2op_0 (TIword iw0, disassemble_info *outf) if (opc == 0) { OUTS (outf, dregs (dst)); - OUTS (outf, ">>>="); + OUTS (outf, " >>>= "); OUTS (outf, dregs (src)); } else if (opc == 1) { OUTS (outf, dregs (dst)); - OUTS (outf, ">>="); + OUTS (outf, " >>= "); OUTS (outf, dregs (src)); } else if (opc == 2) { OUTS (outf, dregs (dst)); - OUTS (outf, "<<="); + OUTS (outf, " <<= "); OUTS (outf, dregs (src)); } else if (opc == 3) { OUTS (outf, dregs (dst)); - OUTS (outf, "*="); + OUTS (outf, " *= "); OUTS (outf, dregs (src)); } else if (opc == 4) { OUTS (outf, dregs (dst)); - OUTS (outf, "=("); + OUTS (outf, " = ("); OUTS (outf, dregs (dst)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs (src)); - OUTS (outf, ")<<1"); + OUTS (outf, ") << 0x1"); } else if (opc == 5) { OUTS (outf, dregs (dst)); - OUTS (outf, "=("); + OUTS (outf, " = ("); OUTS (outf, dregs (dst)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs (src)); - OUTS (outf, ")<<2"); + OUTS (outf, ") << 0x2"); } else if (opc == 8) { - OUTS (outf, "DIVQ("); + OUTS (outf, "DIVQ ("); OUTS (outf, dregs (dst)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src)); OUTS (outf, ")"); } else if (opc == 9) { - OUTS (outf, "DIVS("); + OUTS (outf, "DIVS ("); OUTS (outf, dregs (dst)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src)); OUTS (outf, ")"); } else if (opc == 10) { OUTS (outf, dregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_lo (src)); - OUTS (outf, "(X)"); + OUTS (outf, " (X)"); } else if (opc == 11) { OUTS (outf, dregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_lo (src)); - OUTS (outf, "(Z)"); + OUTS (outf, " (Z)"); } else if (opc == 12) { OUTS (outf, dregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_byte (src)); - OUTS (outf, "(X)"); + OUTS (outf, " (X)"); } else if (opc == 13) { OUTS (outf, dregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_byte (src)); - OUTS (outf, "(Z)"); + OUTS (outf, " (Z)"); } else if (opc == 14) { OUTS (outf, dregs (dst)); - OUTS (outf, "=-"); + OUTS (outf, " = -"); OUTS (outf, dregs (src)); } else if (opc == 15) { OUTS (outf, dregs (dst)); - OUTS (outf, "=~"); + OUTS (outf, " =~ "); OUTS (outf, dregs (src)); } else @@ -1422,54 +1459,54 @@ decode_PTR2op_0 (TIword iw0, disassemble_info *outf) if (opc == 0) { OUTS (outf, pregs (dst)); - OUTS (outf, "-="); + OUTS (outf, " -= "); OUTS (outf, pregs (src)); } else if (opc == 1) { OUTS (outf, pregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, pregs (src)); - OUTS (outf, "<<2"); + OUTS (outf, " << 0x2"); } else if (opc == 3) { OUTS (outf, pregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, pregs (src)); - OUTS (outf, ">>2"); + OUTS (outf, " >> 0x2"); } else if (opc == 4) { OUTS (outf, pregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, pregs (src)); - OUTS (outf, ">>1"); + OUTS (outf, " >> 0x1"); } else if (opc == 5) { OUTS (outf, pregs (dst)); - OUTS (outf, "+="); + OUTS (outf, " += "); OUTS (outf, pregs (src)); - OUTS (outf, "(BREV)"); + OUTS (outf, " (BREV)"); } else if (opc == 6) { OUTS (outf, pregs (dst)); - OUTS (outf, "=("); + OUTS (outf, " = ("); OUTS (outf, pregs (dst)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, pregs (src)); - OUTS (outf, ")<<1"); + OUTS (outf, ") << 0x1"); } else if (opc == 7) { OUTS (outf, pregs (dst)); - OUTS (outf, "=("); + OUTS (outf, " = ("); OUTS (outf, pregs (dst)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, pregs (src)); - OUTS (outf, ")<<2"); + OUTS (outf, ") << 0x2"); } else return 0; @@ -1490,60 +1527,75 @@ decode_LOGI2op_0 (TIword iw0, disassemble_info *outf) if (opc == 0) { - OUTS (outf, "CC = ! BITTST ("); + OUTS (outf, "CC = !BITTST ("); OUTS (outf, dregs (dst)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, uimm5 (src)); - OUTS (outf, ")"); + OUTS (outf, ");\t\t/* bit"); + OUTS (outf, imm7d (src)); + OUTS (outf, " */"); + comment = 1; } else if (opc == 1) { OUTS (outf, "CC = BITTST ("); OUTS (outf, dregs (dst)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, uimm5 (src)); - OUTS (outf, ")"); + OUTS (outf, ");\t\t/* bit"); + OUTS (outf, imm7d (src)); + OUTS (outf, " */"); + comment = 1; } else if (opc == 2) { OUTS (outf, "BITSET ("); OUTS (outf, dregs (dst)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, uimm5 (src)); - OUTS (outf, ")"); + OUTS (outf, ");\t\t/* bit"); + OUTS (outf, imm7d (src)); + OUTS (outf, " */"); + comment = 1; } else if (opc == 3) { OUTS (outf, "BITTGL ("); OUTS (outf, dregs (dst)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, uimm5 (src)); - OUTS (outf, ")"); + OUTS (outf, ");\t\t/* bit"); + OUTS (outf, imm7d (src)); + OUTS (outf, " */"); + comment = 1; } else if (opc == 4) { OUTS (outf, "BITCLR ("); OUTS (outf, dregs (dst)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, uimm5 (src)); - OUTS (outf, ")"); + OUTS (outf, ");\t\t/* bit"); + OUTS (outf, imm7d (src)); + OUTS (outf, " */"); + comment = 1; } else if (opc == 5) { OUTS (outf, dregs (dst)); - OUTS (outf, ">>>="); + OUTS (outf, " >>>= "); OUTS (outf, uimm5 (src)); } else if (opc == 6) { OUTS (outf, dregs (dst)); - OUTS (outf, ">>="); + OUTS (outf, " >>= "); OUTS (outf, uimm5 (src)); } else if (opc == 7) { OUTS (outf, dregs (dst)); - OUTS (outf, "<<="); + OUTS (outf, " <<= "); OUTS (outf, uimm5 (src)); } else @@ -1567,74 +1619,74 @@ decode_COMP3op_0 (TIword iw0, disassemble_info *outf) if (opc == 5 && src1 == src0) { OUTS (outf, pregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, pregs (src0)); - OUTS (outf, "<<1"); + OUTS (outf, " << 0x1"); } else if (opc == 1) { OUTS (outf, dregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "-"); + OUTS (outf, " - "); OUTS (outf, dregs (src1)); } else if (opc == 2) { OUTS (outf, dregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "&"); + OUTS (outf, " & "); OUTS (outf, dregs (src1)); } else if (opc == 3) { OUTS (outf, dregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "|"); + OUTS (outf, " | "); OUTS (outf, dregs (src1)); } else if (opc == 4) { OUTS (outf, dregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "^"); + OUTS (outf, " ^ "); OUTS (outf, dregs (src1)); } else if (opc == 5) { OUTS (outf, pregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, pregs (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, pregs (src1)); } else if (opc == 6) { OUTS (outf, pregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, pregs (src0)); - OUTS (outf, "+("); + OUTS (outf, " + ("); OUTS (outf, pregs (src1)); - OUTS (outf, "<<1)"); + OUTS (outf, " << 0x1)"); } else if (opc == 7) { OUTS (outf, pregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, pregs (src0)); - OUTS (outf, "+("); + OUTS (outf, " + ("); OUTS (outf, pregs (src1)); - OUTS (outf, "<<2)"); + OUTS (outf, " << 0x2)"); } else if (opc == 0) { OUTS (outf, dregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs (src1)); } else @@ -1654,18 +1706,43 @@ decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf) int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask); int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask); + bu32 *pval = get_allreg (0, dst); + + /* Since we don't have 32-bit immediate loads, we allow the disassembler + to combine them, so it prints out the right values. + Here we keep track of the registers. */ + if (op == 0) + { + *pval = imm7_val (src); + if (src & 0x40) + *pval |= 0xFFFFFF80; + else + *pval &= 0x7F; + } + if (op == 0) { OUTS (outf, dregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, imm7 (src)); - OUTS (outf, "(x)"); + OUTS (outf, " (X);\t\t/*\t\t"); + OUTS (outf, dregs (dst)); + OUTS (outf, "="); + OUTS (outf, uimm32 (*pval)); + OUTS (outf, "("); + OUTS (outf, imm32 (*pval)); + OUTS (outf, ") */"); + comment = 1; } else if (op == 1) { OUTS (outf, dregs (dst)); - OUTS (outf, "+="); + OUTS (outf, " += "); OUTS (outf, imm7 (src)); + OUTS (outf, ";\t\t/* ("); + OUTS (outf, imm7d (src)); + OUTS (outf, ") */"); + comment = 1; } else return 0; @@ -1684,17 +1761,40 @@ decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf) int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask); int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask); + bu32 *pval = get_allreg (1, dst); + + if (op == 0) + { + *pval = imm7_val (src); + if (src & 0x40) + *pval |= 0xFFFFFF80; + else + *pval &= 0x7F; + } + if (op == 0) { OUTS (outf, pregs (dst)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, imm7 (src)); + OUTS (outf, " (X);\t\t/*\t\t"); + OUTS (outf, pregs (dst)); + OUTS (outf, "="); + OUTS (outf, uimm32 (*pval)); + OUTS (outf, "("); + OUTS (outf, imm32 (*pval)); + OUTS (outf, ") */"); + comment = 1; } else if (op == 1) { OUTS (outf, pregs (dst)); - OUTS (outf, "+="); + OUTS (outf, " += "); OUTS (outf, imm7 (src)); + OUTS (outf, ";\t\t/* ("); + OUTS (outf, imm7d (src)); + OUTS (outf, ") */"); + comment = 1; } else return 0; @@ -1718,14 +1818,14 @@ decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf) if (aop == 1 && W == 0 && idx == ptr) { OUTS (outf, dregs_lo (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); OUTS (outf, "]"); } else if (aop == 2 && W == 0 && idx == ptr) { OUTS (outf, dregs_hi (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); OUTS (outf, "]"); } @@ -1733,86 +1833,86 @@ decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf) { OUTS (outf, "W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs_lo (reg)); } else if (aop == 2 && W == 1 && idx == ptr) { OUTS (outf, "W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs_hi (reg)); } else if (aop == 0 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=["); + OUTS (outf, " = ["); OUTS (outf, pregs (ptr)); - OUTS (outf, "++"); + OUTS (outf, " ++ "); OUTS (outf, pregs (idx)); OUTS (outf, "]"); } else if (aop == 1 && W == 0) { OUTS (outf, dregs_lo (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "++"); + OUTS (outf, " ++ "); OUTS (outf, pregs (idx)); OUTS (outf, "]"); } else if (aop == 2 && W == 0) { OUTS (outf, dregs_hi (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "++"); + OUTS (outf, " ++ "); OUTS (outf, pregs (idx)); OUTS (outf, "]"); } else if (aop == 3 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "++"); + OUTS (outf, " ++ "); OUTS (outf, pregs (idx)); OUTS (outf, "] (Z)"); } else if (aop == 3 && W == 1) { OUTS (outf, dregs (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "++"); + OUTS (outf, " ++ "); OUTS (outf, pregs (idx)); - OUTS (outf, "](X)"); + OUTS (outf, "] (X)"); } else if (aop == 0 && W == 1) { OUTS (outf, "["); OUTS (outf, pregs (ptr)); - OUTS (outf, "++"); + OUTS (outf, " ++ "); OUTS (outf, pregs (idx)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs (reg)); } else if (aop == 1 && W == 1) { OUTS (outf, "W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "++"); + OUTS (outf, " ++ "); OUTS (outf, pregs (idx)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs_lo (reg)); } else if (aop == 2 && W == 1) { OUTS (outf, "W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "++"); + OUTS (outf, " ++ "); OUTS (outf, pregs (idx)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs_hi (reg)); } else @@ -1836,20 +1936,20 @@ decode_dagMODim_0 (TIword iw0, disassemble_info *outf) if (op == 0 && br == 1) { OUTS (outf, iregs (i)); - OUTS (outf, "+="); + OUTS (outf, " += "); OUTS (outf, mregs (m)); - OUTS (outf, "(BREV)"); + OUTS (outf, " (BREV)"); } else if (op == 0) { OUTS (outf, iregs (i)); - OUTS (outf, "+="); + OUTS (outf, " += "); OUTS (outf, mregs (m)); } else if (op == 1) { OUTS (outf, iregs (i)); - OUTS (outf, "-="); + OUTS (outf, " -= "); OUTS (outf, mregs (m)); } else @@ -1871,26 +1971,37 @@ decode_dagMODik_0 (TIword iw0, disassemble_info *outf) if (op == 0) { OUTS (outf, iregs (i)); - OUTS (outf, "+=2"); + OUTS (outf, " += 0x2"); } else if (op == 1) { OUTS (outf, iregs (i)); - OUTS (outf, "-=2"); + OUTS (outf, " -= 0x2"); } else if (op == 2) { OUTS (outf, iregs (i)); - OUTS (outf, "+=4"); + OUTS (outf, " += 0x4"); } else if (op == 3) { OUTS (outf, iregs (i)); - OUTS (outf, "-=4"); + OUTS (outf, " -= 0x4"); } else return 0; + if (! parallel ) + { + OUTS (outf, ";\t\t/* ( "); + if (op == 0 || op == 1) + OUTS (outf, "2"); + else if (op == 2 || op == 3) + OUTS (outf, "4"); + OUTS (outf, ") */"); + comment = 1; + } + return 2; } @@ -1910,63 +2021,63 @@ decode_dspLDST_0 (TIword iw0, disassemble_info *outf) if (aop == 0 && W == 0 && m == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=["); + OUTS (outf, " = ["); OUTS (outf, iregs (i)); OUTS (outf, "++]"); } else if (aop == 0 && W == 0 && m == 1) { OUTS (outf, dregs_lo (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, iregs (i)); OUTS (outf, "++]"); } else if (aop == 0 && W == 0 && m == 2) { OUTS (outf, dregs_hi (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, iregs (i)); OUTS (outf, "++]"); } else if (aop == 1 && W == 0 && m == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=["); + OUTS (outf, " = ["); OUTS (outf, iregs (i)); OUTS (outf, "--]"); } else if (aop == 1 && W == 0 && m == 1) { OUTS (outf, dregs_lo (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, iregs (i)); OUTS (outf, "--]"); } else if (aop == 1 && W == 0 && m == 2) { OUTS (outf, dregs_hi (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, iregs (i)); OUTS (outf, "--]"); } else if (aop == 2 && W == 0 && m == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=["); + OUTS (outf, " = ["); OUTS (outf, iregs (i)); OUTS (outf, "]"); } else if (aop == 2 && W == 0 && m == 1) { OUTS (outf, dregs_lo (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, iregs (i)); OUTS (outf, "]"); } else if (aop == 2 && W == 0 && m == 2) { OUTS (outf, dregs_hi (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, iregs (i)); OUTS (outf, "]"); } @@ -1974,71 +2085,71 @@ decode_dspLDST_0 (TIword iw0, disassemble_info *outf) { OUTS (outf, "["); OUTS (outf, iregs (i)); - OUTS (outf, "++]="); + OUTS (outf, "++] = "); OUTS (outf, dregs (reg)); } else if (aop == 0 && W == 1 && m == 1) { OUTS (outf, "W["); OUTS (outf, iregs (i)); - OUTS (outf, "++]="); + OUTS (outf, "++] = "); OUTS (outf, dregs_lo (reg)); } else if (aop == 0 && W == 1 && m == 2) { OUTS (outf, "W["); OUTS (outf, iregs (i)); - OUTS (outf, "++]="); + OUTS (outf, "++] = "); OUTS (outf, dregs_hi (reg)); } else if (aop == 1 && W == 1 && m == 0) { OUTS (outf, "["); OUTS (outf, iregs (i)); - OUTS (outf, "--]="); + OUTS (outf, "--] = "); OUTS (outf, dregs (reg)); } else if (aop == 1 && W == 1 && m == 1) { OUTS (outf, "W["); OUTS (outf, iregs (i)); - OUTS (outf, "--]="); + OUTS (outf, "--] = "); OUTS (outf, dregs_lo (reg)); } else if (aop == 1 && W == 1 && m == 2) { OUTS (outf, "W["); OUTS (outf, iregs (i)); - OUTS (outf, "--]="); + OUTS (outf, "--] = "); OUTS (outf, dregs_hi (reg)); } else if (aop == 2 && W == 1 && m == 0) { OUTS (outf, "["); OUTS (outf, iregs (i)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs (reg)); } else if (aop == 2 && W == 1 && m == 1) { OUTS (outf, "W["); OUTS (outf, iregs (i)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs_lo (reg)); } else if (aop == 2 && W == 1 && m == 2) { OUTS (outf, "W["); OUTS (outf, iregs (i)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs_hi (reg)); } else if (aop == 3 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=["); + OUTS (outf, " = ["); OUTS (outf, iregs (i)); - OUTS (outf, "++"); + OUTS (outf, " ++ "); OUTS (outf, mregs (m)); OUTS (outf, "]"); } @@ -2046,9 +2157,9 @@ decode_dspLDST_0 (TIword iw0, disassemble_info *outf) { OUTS (outf, "["); OUTS (outf, iregs (i)); - OUTS (outf, "++"); + OUTS (outf, " ++ "); OUTS (outf, mregs (m)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs (reg)); } else @@ -2074,211 +2185,211 @@ decode_LDST_0 (TIword iw0, disassemble_info *outf) if (aop == 0 && sz == 0 && Z == 0 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=["); + OUTS (outf, " = ["); OUTS (outf, pregs (ptr)); OUTS (outf, "++]"); } else if (aop == 0 && sz == 0 && Z == 1 && W == 0) { OUTS (outf, pregs (reg)); - OUTS (outf, "=["); + OUTS (outf, " = ["); OUTS (outf, pregs (ptr)); OUTS (outf, "++]"); } else if (aop == 0 && sz == 1 && Z == 0 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); OUTS (outf, "++] (Z)"); } else if (aop == 0 && sz == 1 && Z == 1 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "++](X)"); + OUTS (outf, "++] (X)"); } else if (aop == 0 && sz == 2 && Z == 0 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=B["); + OUTS (outf, " = B["); OUTS (outf, pregs (ptr)); OUTS (outf, "++] (Z)"); } else if (aop == 0 && sz == 2 && Z == 1 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=B["); + OUTS (outf, " = B["); OUTS (outf, pregs (ptr)); - OUTS (outf, "++](X)"); + OUTS (outf, "++] (X)"); } else if (aop == 1 && sz == 0 && Z == 0 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=["); + OUTS (outf, " = ["); OUTS (outf, pregs (ptr)); OUTS (outf, "--]"); } else if (aop == 1 && sz == 0 && Z == 1 && W == 0) { OUTS (outf, pregs (reg)); - OUTS (outf, "=["); + OUTS (outf, " = ["); OUTS (outf, pregs (ptr)); OUTS (outf, "--]"); } else if (aop == 1 && sz == 1 && Z == 0 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); OUTS (outf, "--] (Z)"); } else if (aop == 1 && sz == 1 && Z == 1 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "--](X)"); + OUTS (outf, "--] (X)"); } else if (aop == 1 && sz == 2 && Z == 0 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=B["); + OUTS (outf, " = B["); OUTS (outf, pregs (ptr)); OUTS (outf, "--] (Z)"); } else if (aop == 1 && sz == 2 && Z == 1 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=B["); + OUTS (outf, " = B["); OUTS (outf, pregs (ptr)); - OUTS (outf, "--](X)"); + OUTS (outf, "--] (X)"); } else if (aop == 2 && sz == 0 && Z == 0 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=["); + OUTS (outf, " = ["); OUTS (outf, pregs (ptr)); OUTS (outf, "]"); } else if (aop == 2 && sz == 0 && Z == 1 && W == 0) { OUTS (outf, pregs (reg)); - OUTS (outf, "=["); + OUTS (outf, " = ["); OUTS (outf, pregs (ptr)); OUTS (outf, "]"); } else if (aop == 2 && sz == 1 && Z == 0 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); OUTS (outf, "] (Z)"); } else if (aop == 2 && sz == 1 && Z == 1 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "](X)"); + OUTS (outf, "] (X)"); } else if (aop == 2 && sz == 2 && Z == 0 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=B["); + OUTS (outf, " = B["); OUTS (outf, pregs (ptr)); OUTS (outf, "] (Z)"); } else if (aop == 2 && sz == 2 && Z == 1 && W == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=B["); + OUTS (outf, " = B["); OUTS (outf, pregs (ptr)); - OUTS (outf, "](X)"); + OUTS (outf, "] (X)"); } else if (aop == 0 && sz == 0 && Z == 0 && W == 1) { OUTS (outf, "["); OUTS (outf, pregs (ptr)); - OUTS (outf, "++]="); + OUTS (outf, "++] = "); OUTS (outf, dregs (reg)); } else if (aop == 0 && sz == 0 && Z == 1 && W == 1) { OUTS (outf, "["); OUTS (outf, pregs (ptr)); - OUTS (outf, "++]="); + OUTS (outf, "++] = "); OUTS (outf, pregs (reg)); } else if (aop == 0 && sz == 1 && Z == 0 && W == 1) { OUTS (outf, "W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "++]="); + OUTS (outf, "++] = "); OUTS (outf, dregs (reg)); } else if (aop == 0 && sz == 2 && Z == 0 && W == 1) { OUTS (outf, "B["); OUTS (outf, pregs (ptr)); - OUTS (outf, "++]="); + OUTS (outf, "++] = "); OUTS (outf, dregs (reg)); } else if (aop == 1 && sz == 0 && Z == 0 && W == 1) { OUTS (outf, "["); OUTS (outf, pregs (ptr)); - OUTS (outf, "--]="); + OUTS (outf, "--] = "); OUTS (outf, dregs (reg)); } else if (aop == 1 && sz == 0 && Z == 1 && W == 1) { OUTS (outf, "["); OUTS (outf, pregs (ptr)); - OUTS (outf, "--]="); + OUTS (outf, "--] = "); OUTS (outf, pregs (reg)); } else if (aop == 1 && sz == 1 && Z == 0 && W == 1) { OUTS (outf, "W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "--]="); + OUTS (outf, "--] = "); OUTS (outf, dregs (reg)); } else if (aop == 1 && sz == 2 && Z == 0 && W == 1) { OUTS (outf, "B["); OUTS (outf, pregs (ptr)); - OUTS (outf, "--]="); + OUTS (outf, "--] = "); OUTS (outf, dregs (reg)); } else if (aop == 2 && sz == 0 && Z == 0 && W == 1) { OUTS (outf, "["); OUTS (outf, pregs (ptr)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs (reg)); } else if (aop == 2 && sz == 0 && Z == 1 && W == 1) { OUTS (outf, "["); OUTS (outf, pregs (ptr)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, pregs (reg)); } else if (aop == 2 && sz == 1 && Z == 0 && W == 1) { OUTS (outf, "W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs (reg)); } else if (aop == 2 && sz == 2 && Z == 0 && W == 1) { OUTS (outf, "B["); OUTS (outf, pregs (ptr)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs (reg)); } else @@ -2301,15 +2412,15 @@ decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf) if (W == 0) { OUTS (outf, dpregs (reg)); - OUTS (outf, "=[FP"); + OUTS (outf, " = [FP "); OUTS (outf, negimm5s4 (offset)); OUTS (outf, "]"); } else if (W == 1) { - OUTS (outf, "[FP"); + OUTS (outf, "[FP "); OUTS (outf, negimm5s4 (offset)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dpregs (reg)); } else @@ -2334,36 +2445,36 @@ decode_LDSTii_0 (TIword iw0, disassemble_info *outf) if (W == 0 && op == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=["); + OUTS (outf, " = ["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, uimm4s4 (offset)); OUTS (outf, "]"); } else if (W == 0 && op == 1) { OUTS (outf, dregs (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, uimm4s2 (offset)); OUTS (outf, "] (Z)"); } else if (W == 0 && op == 2) { OUTS (outf, dregs (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, uimm4s2 (offset)); - OUTS (outf, "](X)"); + OUTS (outf, "] (X)"); } else if (W == 0 && op == 3) { OUTS (outf, pregs (reg)); - OUTS (outf, "=["); + OUTS (outf, " = ["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, uimm4s4 (offset)); OUTS (outf, "]"); } @@ -2371,29 +2482,27 @@ decode_LDSTii_0 (TIword iw0, disassemble_info *outf) { OUTS (outf, "["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, uimm4s4 (offset)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs (reg)); } else if (W == 1 && op == 1) { - OUTS (outf, "W"); - OUTS (outf, "["); + OUTS (outf, "W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, uimm4s2 (offset)); - OUTS (outf, "]"); - OUTS (outf, "="); + OUTS (outf, "] = "); OUTS (outf, dregs (reg)); } else if (W == 1 && op == 3) { OUTS (outf, "["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, uimm4s4 (offset)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, pregs (reg)); } else @@ -2419,37 +2528,37 @@ decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf) if (rop == 0) { OUTS (outf, "LSETUP"); - OUTS (outf, "("); + OUTS (outf, "(0x"); OUTS (outf, pcrel4 (soffset)); - OUTS (outf, ","); + OUTS (outf, ", 0x"); OUTS (outf, lppcrel10 (eoffset)); - OUTS (outf, ")"); + OUTS (outf, ") "); OUTS (outf, counters (c)); } else if (rop == 1) { OUTS (outf, "LSETUP"); - OUTS (outf, "("); + OUTS (outf, "(0x"); OUTS (outf, pcrel4 (soffset)); - OUTS (outf, ","); + OUTS (outf, ", 0x"); OUTS (outf, lppcrel10 (eoffset)); - OUTS (outf, ")"); + OUTS (outf, ") "); OUTS (outf, counters (c)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, pregs (reg)); } else if (rop == 3) { OUTS (outf, "LSETUP"); - OUTS (outf, "("); + OUTS (outf, "(0x"); OUTS (outf, pcrel4 (soffset)); - OUTS (outf, ","); + OUTS (outf, ", 0x"); OUTS (outf, lppcrel10 (eoffset)); - OUTS (outf, ")"); + OUTS (outf, ") "); OUTS (outf, counters (c)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, pregs (reg)); - OUTS (outf, ">>1"); + OUTS (outf, " >> 0x1"); } else return 0; @@ -2481,11 +2590,16 @@ decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf) { /* regs = imm16 (x) */ *pval = imm16_val (hword); + if (hword & 0x8000) + *pval |= 0xFFFF0000; + else + *pval &= 0xFFFF; } else if (H == 0 && S == 0 && Z == 1) { /* regs = luimm16 (Z) */ *pval = luimm16_val (hword); + *pval &= 0xFFFF; } else if (H == 0 && S == 0 && Z == 0) { @@ -2504,64 +2618,89 @@ decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf) if (grp == 0 && H == 0 && S == 0 && Z == 0) { OUTS (outf, dregs_lo (reg)); - OUTS (outf, "="); - OUTS (outf, imm16 (hword)); + OUTS (outf, " = "); + OUTS (outf, uimm16 (hword)); } else if (grp == 0 && H == 1 && S == 0 && Z == 0) { OUTS (outf, dregs_hi (reg)); - OUTS (outf, "="); - OUTS (outf, imm16 (hword)); + OUTS (outf, " = "); + OUTS (outf, uimm16 (hword)); } else if (grp == 0 && H == 0 && S == 1 && Z == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, imm16 (hword)); OUTS (outf, " (X)"); } else if (H == 0 && S == 1 && Z == 0) - { + { OUTS (outf, regs (reg, grp)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, imm16 (hword)); OUTS (outf, " (X)"); } else if (H == 0 && S == 0 && Z == 1) { OUTS (outf, regs (reg, grp)); - OUTS (outf, "="); - OUTS (outf, luimm16 (hword)); - OUTS (outf, "(Z)"); + OUTS (outf, " = "); + OUTS (outf, uimm16 (hword)); + OUTS (outf, " (Z)"); } else if (H == 0 && S == 0 && Z == 0) { OUTS (outf, regs_lo (reg, grp)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, uimm16 (hword)); } else if (H == 1 && S == 0 && Z == 0) { OUTS (outf, regs_hi (reg, grp)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, uimm16 (hword)); } else return 0; /* And we print out the 32-bit value if it is a pointer. */ - if ( S == 0 && Z == 0 && grp != 0 ) + if (S == 0 && Z == 0) { - OUTS (outf, "\t/* "); + OUTS (outf, ";\t\t/* ("); + OUTS (outf, imm16d (hword)); + OUTS (outf, ")\t"); + /* If it is an MMR, don't print the symbol. */ - if ( *pval < 0xFFC00000 ) - OUTS (outf, huimm32(*pval)); + if (*pval < 0xFFC00000 && grp == 1) + { + OUTS (outf, regs (reg, grp)); + OUTS (outf, "=0x"); + OUTS (outf, huimm32e (*pval)); + } else - OUTS (outf, uimm32(*pval)); + { + OUTS (outf, regs (reg, grp)); + OUTS (outf, "=0x"); + OUTS (outf, huimm32e (*pval)); + OUTS (outf, "("); + OUTS (outf, imm32 (*pval)); + OUTS (outf, ")"); + } OUTS (outf, " */"); + comment = 1; + } + if (S == 1 || Z == 1) + { + OUTS (outf, ";\t\t/*\t\t"); + OUTS (outf, regs (reg, grp)); + OUTS (outf, "=0x"); + OUTS (outf, huimm32e (*pval)); + OUTS (outf, "("); + OUTS (outf, imm32 (*pval)); + OUTS (outf, ") */"); + comment = 1; } - return 4; } @@ -2578,9 +2717,9 @@ decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf) int msw = ((iw0 >> 0) & 0xff); if (S == 1) - OUTS (outf, "CALL "); + OUTS (outf, "CALL 0x"); else if (S == 0) - OUTS (outf, "JUMP.L "); + OUTS (outf, "JUMP.L 0x"); else return 0; @@ -2606,91 +2745,91 @@ decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf) if (W == 0 && sz == 0 && Z == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=["); + OUTS (outf, " = ["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, imm16s4 (offset)); OUTS (outf, "]"); } else if (W == 0 && sz == 0 && Z == 1) { OUTS (outf, pregs (reg)); - OUTS (outf, "=["); + OUTS (outf, " = ["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, imm16s4 (offset)); OUTS (outf, "]"); } else if (W == 0 && sz == 1 && Z == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, imm16s2 (offset)); OUTS (outf, "] (Z)"); } else if (W == 0 && sz == 1 && Z == 1) { OUTS (outf, dregs (reg)); - OUTS (outf, "=W["); + OUTS (outf, " = W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, imm16s2 (offset)); - OUTS (outf, "](X)"); + OUTS (outf, "] (X)"); } else if (W == 0 && sz == 2 && Z == 0) { OUTS (outf, dregs (reg)); - OUTS (outf, "=B["); + OUTS (outf, " = B["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, imm16 (offset)); OUTS (outf, "] (Z)"); } else if (W == 0 && sz == 2 && Z == 1) { OUTS (outf, dregs (reg)); - OUTS (outf, "=B["); + OUTS (outf, " = B["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, imm16 (offset)); - OUTS (outf, "](X)"); + OUTS (outf, "] (X)"); } else if (W == 1 && sz == 0 && Z == 0) { OUTS (outf, "["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, imm16s4 (offset)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs (reg)); } else if (W == 1 && sz == 0 && Z == 1) { OUTS (outf, "["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, imm16s4 (offset)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, pregs (reg)); } else if (W == 1 && sz == 1 && Z == 0) { OUTS (outf, "W["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, imm16s2 (offset)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs (reg)); } else if (W == 1 && sz == 2 && Z == 0) { OUTS (outf, "B["); OUTS (outf, pregs (ptr)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, imm16 (offset)); - OUTS (outf, "]="); + OUTS (outf, "] = "); OUTS (outf, dregs (reg)); } else @@ -2714,6 +2853,10 @@ decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf) { OUTS (outf, "LINK "); OUTS (outf, uimm16s4 (framesize)); + OUTS (outf, ";\t\t/* ("); + OUTS (outf, uimm16s4d (framesize)); + OUTS (outf, ") */"); + comment = 1; } else if (R == 1) OUTS (outf, "UNLINK"); @@ -2878,279 +3021,263 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) if (aop == 0 && aopcde == 9 && HL == 0 && s == 0) { - OUTS (outf, "A0.L="); + OUTS (outf, "A0.L = "); OUTS (outf, dregs_lo (src0)); } else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0) { - OUTS (outf, "A1.H="); + OUTS (outf, "A1.H = "); OUTS (outf, dregs_hi (src0)); } else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0) { - OUTS (outf, "A1.L="); + OUTS (outf, "A1.L = "); OUTS (outf, dregs_lo (src0)); } else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0) { - OUTS (outf, "A0.H="); + OUTS (outf, "A0.H = "); OUTS (outf, dregs_hi (src0)); } else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "-"); + OUTS (outf, " - "); OUTS (outf, dregs (src1)); - OUTS (outf, "(RND20)"); + OUTS (outf, " (RND20)"); } else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs (src1)); - OUTS (outf, "(RND20)"); + OUTS (outf, " (RND20)"); } else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "-"); + OUTS (outf, " - "); OUTS (outf, dregs (src1)); - OUTS (outf, "(RND12)"); + OUTS (outf, " (RND12)"); } else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs (src1)); - OUTS (outf, "(RND12)"); + OUTS (outf, " (RND12)"); } else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "-"); + OUTS (outf, " - "); OUTS (outf, dregs (src1)); - OUTS (outf, "(RND20)"); + OUTS (outf, " (RND20)"); } else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs (src1)); - OUTS (outf, "(RND12)"); + OUTS (outf, " (RND12)"); } else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs (src1)); - OUTS (outf, "(RND20)"); + OUTS (outf, " (RND20)"); } else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "-"); + OUTS (outf, " - "); OUTS (outf, dregs (src1)); - OUTS (outf, "(RND12)"); + OUTS (outf, " (RND12)"); } else if (HL == 1 && aop == 0 && aopcde == 2) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs_lo (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 1 && aop == 1 && aopcde == 2) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs_hi (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 1 && aop == 2 && aopcde == 2) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_hi (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs_lo (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 1 && aop == 3 && aopcde == 2) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_hi (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs_hi (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 0 && aop == 0 && aopcde == 3) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "-"); + OUTS (outf, " - "); OUTS (outf, dregs_lo (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 0 && aop == 1 && aopcde == 3) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "-"); + OUTS (outf, " - "); OUTS (outf, dregs_hi (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 0 && aop == 3 && aopcde == 2) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_hi (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs_hi (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 1 && aop == 0 && aopcde == 3) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "-"); + OUTS (outf, " - "); OUTS (outf, dregs_lo (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 1 && aop == 1 && aopcde == 3) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "-"); + OUTS (outf, " - "); OUTS (outf, dregs_hi (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 1 && aop == 2 && aopcde == 3) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_hi (src0)); - OUTS (outf, "-"); + OUTS (outf, " - "); OUTS (outf, dregs_lo (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 1 && aop == 3 && aopcde == 3) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_hi (src0)); - OUTS (outf, "-"); + OUTS (outf, " - "); OUTS (outf, dregs_hi (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 0 && aop == 2 && aopcde == 2) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_hi (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs_lo (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 0 && aop == 1 && aopcde == 2) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs_hi (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 0 && aop == 2 && aopcde == 3) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_hi (src0)); - OUTS (outf, "-"); + OUTS (outf, " - "); OUTS (outf, dregs_lo (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 0 && aop == 3 && aopcde == 3) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_hi (src0)); - OUTS (outf, "-"); + OUTS (outf, " - "); OUTS (outf, dregs_hi (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 0 && aop == 0 && aopcde == 2) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs_lo (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (aop == 0 && aopcde == 9 && s == 1) { - OUTS (outf, "A0="); + OUTS (outf, "A0 = "); OUTS (outf, dregs (src0)); } else if (aop == 3 && aopcde == 11 && s == 0) - OUTS (outf, "A0-=A1"); + OUTS (outf, "A0 -= A1"); else if (aop == 3 && aopcde == 11 && s == 1) - OUTS (outf, "A0-=A1(W32)"); + OUTS (outf, "A0 -= A1 (W32)"); else if (aop == 3 && aopcde == 22 && HL == 1) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=BYTEOP2M("); + OUTS (outf, " = BYTEOP2M ("); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); OUTS (outf, imm5 (src0)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src1 + 1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1)); - OUTS (outf, ")(TH"); + OUTS (outf, ") (TH"); if (s == 1) OUTS (outf, ", R)"); else @@ -3159,15 +3286,15 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (aop == 3 && aopcde == 22 && HL == 0) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=BYTEOP2M("); + OUTS (outf, " = BYTEOP2M ("); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); OUTS (outf, imm5 (src0)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src1 + 1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1)); - OUTS (outf, ")(TL"); + OUTS (outf, ") (TL"); if (s == 1) OUTS (outf, ", R)"); else @@ -3176,15 +3303,15 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (aop == 2 && aopcde == 22 && HL == 1) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=BYTEOP2M("); + OUTS (outf, " = BYTEOP2M ("); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); OUTS (outf, imm5 (src0)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src1 + 1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1)); - OUTS (outf, ")(RNDH"); + OUTS (outf, ") (RNDH"); if (s == 1) OUTS (outf, ", R)"); else @@ -3193,15 +3320,15 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (aop == 2 && aopcde == 22 && HL == 0) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=BYTEOP2M("); + OUTS (outf, " = BYTEOP2M ("); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); OUTS (outf, imm5 (src0)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src1 + 1)); OUTS (outf, ":"); OUTS (outf, imm5 (src1)); - OUTS (outf, ")(RNDL"); + OUTS (outf, ") (RNDL"); if (s == 1) OUTS (outf, ", R)"); else @@ -3210,15 +3337,15 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (aop == 1 && aopcde == 22 && HL == 1) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=BYTEOP2P("); + OUTS (outf, " = BYTEOP2P ("); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src0)); - OUTS (outf, ","); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); OUTS (outf, dregs (src1 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src1)); - OUTS (outf, ")(TH"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (TH"); if (s == 1) OUTS (outf, ", R)"); else @@ -3227,15 +3354,15 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (aop == 1 && aopcde == 22 && HL == 0) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=BYTEOP2P("); + OUTS (outf, " = BYTEOP2P ("); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src0)); - OUTS (outf, ","); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); OUTS (outf, dregs (src1 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src1)); - OUTS (outf, ")(TL"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (TL"); if (s == 1) OUTS (outf, ", R)"); else @@ -3244,15 +3371,15 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (aop == 0 && aopcde == 22 && HL == 1) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=BYTEOP2P("); + OUTS (outf, " = BYTEOP2P ("); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src0)); - OUTS (outf, ","); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); OUTS (outf, dregs (src1 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src1)); - OUTS (outf, ")(RNDH"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (RNDH"); if (s == 1) OUTS (outf, ", R)"); else @@ -3261,69 +3388,69 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (aop == 0 && aopcde == 22 && HL == 0) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=BYTEOP2P("); + OUTS (outf, " = BYTEOP2P ("); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src0)); - OUTS (outf, ","); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); OUTS (outf, dregs (src1 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src1)); - OUTS (outf, ")(RNDL"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (RNDL"); if (s == 1) OUTS (outf, ", R)"); else OUTS (outf, ")"); } else if (aop == 0 && s == 0 && aopcde == 8) - OUTS (outf, "A0=0"); + OUTS (outf, "A0 = 0"); else if (aop == 0 && s == 1 && aopcde == 8) - OUTS (outf, "A0=A0(S)"); + OUTS (outf, "A0 = A0 (S)"); else if (aop == 1 && s == 0 && aopcde == 8) - OUTS (outf, "A1=0"); + OUTS (outf, "A1 = 0"); else if (aop == 1 && s == 1 && aopcde == 8) - OUTS (outf, "A1=A1(S)"); + OUTS (outf, "A1 = A1 (S)"); else if (aop == 2 && s == 0 && aopcde == 8) - OUTS (outf, "A1=A0=0"); + OUTS (outf, "A1 = A0 = 0"); else if (aop == 2 && s == 1 && aopcde == 8) - OUTS (outf, "A1=A1(S),A0=A0(S)"); + OUTS (outf, "A1 = A1 (S), A0 = A0 (S)"); else if (aop == 3 && s == 0 && aopcde == 8) - OUTS (outf, "A0=A1"); + OUTS (outf, "A0 = A1"); else if (aop == 3 && s == 1 && aopcde == 8) - OUTS (outf, "A1=A0"); + OUTS (outf, "A1 = A0"); else if (aop == 1 && aopcde == 9 && s == 0) { - OUTS (outf, "A0.x="); + OUTS (outf, "A0.X = "); OUTS (outf, dregs_lo (src0)); } else if (aop == 1 && HL == 0 && aopcde == 11) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=(A0+=A1)"); + OUTS (outf, " = (A0 += A1)"); } else if (aop == 3 && HL == 0 && aopcde == 16) - OUTS (outf, "A1= ABS A0,A0= ABS A0"); + OUTS (outf, "A1 = ABS A0, A0 = ABS A0"); else if (aop == 0 && aopcde == 23 && HL == 1) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=BYTEOP3P("); + OUTS (outf, " = BYTEOP3P ("); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src0)); - OUTS (outf, ","); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); OUTS (outf, dregs (src1 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src1)); - OUTS (outf, ")(HI"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (HI"); if (s == 1) OUTS (outf, ", R)"); else @@ -3331,239 +3458,233 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) } else if (aop == 3 && aopcde == 9 && s == 0) { - OUTS (outf, "A1.x="); + OUTS (outf, "A1.X = "); OUTS (outf, dregs_lo (src0)); } else if (aop == 1 && HL == 1 && aopcde == 16) - OUTS (outf, "A1= ABS A1"); + OUTS (outf, "A1 = ABS A1"); else if (aop == 0 && HL == 1 && aopcde == 16) - OUTS (outf, "A1= ABS A0"); + OUTS (outf, "A1 = ABS A0"); else if (aop == 2 && aopcde == 9 && s == 1) { - OUTS (outf, "A1="); + OUTS (outf, "A1 = "); OUTS (outf, dregs (src0)); } else if (HL == 0 && aop == 3 && aopcde == 12) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "(RND)"); + OUTS (outf, " (RND)"); } else if (aop == 1 && HL == 0 && aopcde == 16) - OUTS (outf, "A0= ABS A1"); + OUTS (outf, "A0 = ABS A1"); else if (aop == 0 && HL == 0 && aopcde == 16) - OUTS (outf, "A0= ABS A0"); + OUTS (outf, "A0 = ABS A0"); else if (aop == 3 && HL == 0 && aopcde == 15) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=-"); + OUTS (outf, " = -"); OUTS (outf, dregs (src0)); - OUTS (outf, "(V)"); + OUTS (outf, " (V)"); } else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=-"); + OUTS (outf, " = -"); OUTS (outf, dregs (src0)); - OUTS (outf, "(S)"); + OUTS (outf, " (S)"); } else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=-"); + OUTS (outf, " = -"); OUTS (outf, dregs (src0)); - OUTS (outf, "(NS)"); + OUTS (outf, " (NS)"); } else if (aop == 1 && HL == 1 && aopcde == 11) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "=(A0+=A1)"); + OUTS (outf, " = (A0 += A1)"); } else if (aop == 2 && aopcde == 11 && s == 0) - OUTS (outf, "A0+=A1"); + OUTS (outf, "A0 += A1"); else if (aop == 2 && aopcde == 11 && s == 1) - OUTS (outf, "A0+=A1(W32)"); + OUTS (outf, "A0 += A1 (W32)"); else if (aop == 3 && HL == 0 && aopcde == 14) - OUTS (outf, "A1=-A1,A0=-A0"); + OUTS (outf, "A1 = -A1, A0 = -A0"); else if (HL == 1 && aop == 3 && aopcde == 12) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "(RND)"); + OUTS (outf, " (RND)"); } else if (aop == 0 && aopcde == 23 && HL == 0) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=BYTEOP3P("); + OUTS (outf, " = BYTEOP3P ("); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src0)); - OUTS (outf, ","); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); OUTS (outf, dregs (src1 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src1)); - OUTS (outf, ")(LO"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (LO"); if (s == 1) OUTS (outf, ", R)"); else OUTS (outf, ")"); } else if (aop == 0 && HL == 0 && aopcde == 14) - OUTS (outf, "A0=-A0"); + OUTS (outf, "A0 = -A0"); else if (aop == 1 && HL == 0 && aopcde == 14) - OUTS (outf, "A0=-A1"); + OUTS (outf, "A0 = -A1"); else if (aop == 0 && HL == 1 && aopcde == 14) - OUTS (outf, "A1=-A0"); + OUTS (outf, "A1 = -A0"); else if (aop == 1 && HL == 1 && aopcde == 14) - OUTS (outf, "A1=-A1"); + OUTS (outf, "A1 = -A1"); else if (aop == 0 && aopcde == 12) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=SIGN("); + OUTS (outf, " = SIGN ("); OUTS (outf, dregs_hi (src0)); - OUTS (outf, ")*"); + OUTS (outf, ") * "); OUTS (outf, dregs_hi (src1)); - OUTS (outf, "+SIGN("); + OUTS (outf, " + SIGN ("); OUTS (outf, dregs_lo (src0)); - OUTS (outf, ")*"); + OUTS (outf, ") * "); OUTS (outf, dregs_lo (src1)); - OUTS (outf, ")"); } else if (aop == 2 && aopcde == 0) { OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "-|+"); + OUTS (outf, " -|+ "); OUTS (outf, dregs (src1)); - OUTS (outf, " "); amod0 (s, x, outf); } else if (aop == 1 && aopcde == 12) { OUTS (outf, dregs (dst1)); - OUTS (outf, "=A1.L+A1.H,"); + OUTS (outf, " = A1.L + A1.H, "); OUTS (outf, dregs (dst0)); - OUTS (outf, "=A0.L+A0.H"); + OUTS (outf, " = A0.L + A0.H"); } else if (aop == 2 && aopcde == 4) { OUTS (outf, dregs (dst1)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "-"); + OUTS (outf, " - "); OUTS (outf, dregs (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (HL == 0 && aopcde == 1) { OUTS (outf, dregs (dst1)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "+|+"); + OUTS (outf, " +|+ "); OUTS (outf, dregs (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "-|-"); + OUTS (outf, " -|- "); OUTS (outf, dregs (src1)); amod0amod2 (s, x, aop, outf); } else if (aop == 0 && aopcde == 11) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=(A0+=A1)"); + OUTS (outf, " = (A0 += A1)"); } else if (aop == 0 && aopcde == 10) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=A0.x"); + OUTS (outf, " = A0.X"); } else if (aop == 1 && aopcde == 10) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=A1.x"); + OUTS (outf, " = A1.X"); } else if (aop == 1 && aopcde == 0) { OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "+|-"); + OUTS (outf, " +|- "); OUTS (outf, dregs (src1)); - OUTS (outf, " "); amod0 (s, x, outf); } else if (aop == 3 && aopcde == 0) { OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "-|-"); + OUTS (outf, " -|- "); OUTS (outf, dregs (src1)); - OUTS (outf, " "); amod0 (s, x, outf); } else if (aop == 1 && aopcde == 4) { OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "-"); + OUTS (outf, " - "); OUTS (outf, dregs (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (aop == 0 && aopcde == 17) { OUTS (outf, dregs (dst1)); - OUTS (outf, "=A1+A0,"); + OUTS (outf, " = A1 + A0, "); OUTS (outf, dregs (dst0)); - OUTS (outf, "=A1-A0 "); + OUTS (outf, " = A1 - A0"); amod1 (s, x, outf); } else if (aop == 1 && aopcde == 17) { OUTS (outf, dregs (dst1)); - OUTS (outf, "=A0+A1,"); + OUTS (outf, " = A0 + A1, "); OUTS (outf, dregs (dst0)); - OUTS (outf, "=A0-A1 "); + OUTS (outf, " = A0 - A1"); amod1 (s, x, outf); } else if (aop == 0 && aopcde == 18) { - OUTS (outf, "SAA("); + OUTS (outf, "SAA ("); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src0)); - OUTS (outf, ","); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); OUTS (outf, dregs (src1 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src1)); - OUTS (outf, ") "); + OUTS (outf, imm5d (src1)); + OUTS (outf, ")"); aligndir (s, outf); } else if (aop == 3 && aopcde == 18) @@ -3572,29 +3693,29 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (aop == 0 && aopcde == 20) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=BYTEOP1P("); + OUTS (outf, " = BYTEOP1P ("); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src0)); - OUTS (outf, ","); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); OUTS (outf, dregs (src1 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src1)); + OUTS (outf, imm5d (src1)); OUTS (outf, ")"); aligndir (s, outf); } else if (aop == 1 && aopcde == 20) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=BYTEOP1P("); + OUTS (outf, " = BYTEOP1P ("); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src0)); - OUTS (outf, ","); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); OUTS (outf, dregs (src1 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src1)); - OUTS (outf, ")(T"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (T"); if (s == 1) OUTS (outf, ", R)"); else @@ -3604,126 +3725,124 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) { OUTS (outf, "("); OUTS (outf, dregs (dst1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (dst0)); - OUTS (outf, ")=BYTEOP16P("); + OUTS (outf, ") = BYTEOP16P ("); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src0)); - OUTS (outf, ","); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); OUTS (outf, dregs (src1 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src1)); - OUTS (outf, ") "); + OUTS (outf, imm5d (src1)); + OUTS (outf, ")"); aligndir (s, outf); } else if (aop == 1 && aopcde == 21) { OUTS (outf, "("); OUTS (outf, dregs (dst1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (dst0)); - OUTS (outf, ")=BYTEOP16M("); + OUTS (outf, ") = BYTEOP16M ("); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src0)); - OUTS (outf, ","); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); OUTS (outf, dregs (src1 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src1)); - OUTS (outf, ") "); + OUTS (outf, imm5d (src1)); + OUTS (outf, ")"); aligndir (s, outf); } else if (aop == 2 && aopcde == 7) { OUTS (outf, dregs (dst0)); - OUTS (outf, "= ABS "); + OUTS (outf, " = ABS "); OUTS (outf, dregs (src0)); } else if (aop == 1 && aopcde == 7) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=MIN("); + OUTS (outf, " = MIN ("); OUTS (outf, dregs (src0)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src1)); OUTS (outf, ")"); } else if (aop == 0 && aopcde == 7) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=MAX("); + OUTS (outf, " = MAX ("); OUTS (outf, dregs (src0)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src1)); OUTS (outf, ")"); } else if (aop == 2 && aopcde == 6) { OUTS (outf, dregs (dst0)); - OUTS (outf, "= ABS "); + OUTS (outf, " = ABS "); OUTS (outf, dregs (src0)); - OUTS (outf, "(V)"); + OUTS (outf, " (V)"); } else if (aop == 1 && aopcde == 6) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=MIN("); + OUTS (outf, " = MIN ("); OUTS (outf, dregs (src0)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src1)); - OUTS (outf, ")(V)"); + OUTS (outf, ") (V)"); } else if (aop == 0 && aopcde == 6) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=MAX("); + OUTS (outf, " = MAX ("); OUTS (outf, dregs (src0)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src1)); - OUTS (outf, ")(V)"); + OUTS (outf, ") (V)"); } else if (HL == 1 && aopcde == 1) { OUTS (outf, dregs (dst1)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "+|-"); + OUTS (outf, " +|- "); OUTS (outf, dregs (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "-|+"); + OUTS (outf, " -|+ "); OUTS (outf, dregs (src1)); amod0amod2 (s, x, aop, outf); } else if (aop == 0 && aopcde == 4) { OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "+"); + OUTS (outf, " + "); OUTS (outf, dregs (src1)); - OUTS (outf, " "); amod1 (s, x, outf); } else if (aop == 0 && aopcde == 0) { OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src0)); - OUTS (outf, "+|+"); + OUTS (outf, " +|+ "); OUTS (outf, dregs (src1)); - OUTS (outf, " "); amod0 (s, x, outf); } else if (aop == 0 && aopcde == 24) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=BYTEPACK("); + OUTS (outf, " = BYTEPACK ("); OUTS (outf, dregs (src0)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src1)); OUTS (outf, ")"); } @@ -3731,24 +3850,23 @@ decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) { OUTS (outf, "("); OUTS (outf, dregs (dst1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (dst0)); OUTS (outf, ") = BYTEUNPACK "); OUTS (outf, dregs (src0 + 1)); OUTS (outf, ":"); - OUTS (outf, imm5 (src0)); - OUTS (outf, " "); + OUTS (outf, imm5d (src0)); aligndir (s, outf); } else if (aopcde == 13) { OUTS (outf, "("); OUTS (outf, dregs (dst1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (dst0)); OUTS (outf, ") = SEARCH "); OUTS (outf, dregs (src0)); - OUTS (outf, "("); + OUTS (outf, " ("); searchmod (aop, outf); OUTS (outf, ")"); } @@ -3777,7 +3895,7 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) if (HLs == 0 && sop == 0 && sopcde == 0) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "= ASHIFT "); + OUTS (outf, " = ASHIFT "); OUTS (outf, dregs_lo (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); @@ -3785,7 +3903,7 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (HLs == 1 && sop == 0 && sopcde == 0) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "= ASHIFT "); + OUTS (outf, " = ASHIFT "); OUTS (outf, dregs_hi (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); @@ -3793,7 +3911,7 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (HLs == 2 && sop == 0 && sopcde == 0) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "= ASHIFT "); + OUTS (outf, " = ASHIFT "); OUTS (outf, dregs_lo (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); @@ -3801,7 +3919,7 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (HLs == 3 && sop == 0 && sopcde == 0) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "= ASHIFT "); + OUTS (outf, " = ASHIFT "); OUTS (outf, dregs_hi (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); @@ -3809,43 +3927,43 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (HLs == 0 && sop == 1 && sopcde == 0) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "= ASHIFT "); + OUTS (outf, " = ASHIFT "); OUTS (outf, dregs_lo (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "(S)"); + OUTS (outf, " (S)"); } else if (HLs == 1 && sop == 1 && sopcde == 0) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "= ASHIFT "); + OUTS (outf, " = ASHIFT "); OUTS (outf, dregs_hi (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "(S)"); + OUTS (outf, " (S)"); } else if (HLs == 2 && sop == 1 && sopcde == 0) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "= ASHIFT "); + OUTS (outf, " = ASHIFT "); OUTS (outf, dregs_lo (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "(S)"); + OUTS (outf, " (S)"); } else if (HLs == 3 && sop == 1 && sopcde == 0) { OUTS (outf, dregs_hi (dst0)); - OUTS (outf, "= ASHIFT "); + OUTS (outf, " = ASHIFT "); OUTS (outf, dregs_hi (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "(S)"); + OUTS (outf, " (S)"); } else if (sop == 2 && sopcde == 0) { OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0)); - OUTS (outf, "= LSHIFT "); + OUTS (outf, " = LSHIFT "); OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); @@ -3853,7 +3971,7 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (sop == 0 && sopcde == 3) { OUTS (outf, acc01); - OUTS (outf, "= ASHIFT "); + OUTS (outf, " = ASHIFT "); OUTS (outf, acc01); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); @@ -3861,7 +3979,7 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (sop == 1 && sopcde == 3) { OUTS (outf, acc01); - OUTS (outf, "= LSHIFT "); + OUTS (outf, " = LSHIFT "); OUTS (outf, acc01); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); @@ -3869,7 +3987,7 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (sop == 2 && sopcde == 3) { OUTS (outf, acc01); - OUTS (outf, "= ROT "); + OUTS (outf, " = ROT "); OUTS (outf, acc01); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); @@ -3877,7 +3995,7 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (sop == 3 && sopcde == 3) { OUTS (outf, dregs (dst0)); - OUTS (outf, "= ROT "); + OUTS (outf, " = ROT "); OUTS (outf, dregs (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); @@ -3885,25 +4003,25 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (sop == 1 && sopcde == 1) { OUTS (outf, dregs (dst0)); - OUTS (outf, "= ASHIFT "); + OUTS (outf, " = ASHIFT "); OUTS (outf, dregs (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "(V,S)"); + OUTS (outf, " (V, S)"); } else if (sop == 0 && sopcde == 1) { OUTS (outf, dregs (dst0)); - OUTS (outf, "= ASHIFT "); + OUTS (outf, " = ASHIFT "); OUTS (outf, dregs (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "(V)"); + OUTS (outf, " (V)"); } else if (sop == 0 && sopcde == 2) { OUTS (outf, dregs (dst0)); - OUTS (outf, "= ASHIFT "); + OUTS (outf, " = ASHIFT "); OUTS (outf, dregs (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); @@ -3911,16 +4029,16 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (sop == 1 && sopcde == 2) { OUTS (outf, dregs (dst0)); - OUTS (outf, "= ASHIFT "); + OUTS (outf, " = ASHIFT "); OUTS (outf, dregs (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "(S)"); + OUTS (outf, " (S)"); } else if (sop == 2 && sopcde == 2) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=SHIFT "); + OUTS (outf, " = SHIFT "); OUTS (outf, dregs (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); @@ -3928,7 +4046,7 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (sop == 3 && sopcde == 2) { OUTS (outf, dregs (dst0)); - OUTS (outf, "= ROT "); + OUTS (outf, " = ROT "); OUTS (outf, dregs (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); @@ -3936,116 +4054,115 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (sop == 2 && sopcde == 1) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=SHIFT "); + OUTS (outf, " = SHIFT "); OUTS (outf, dregs (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, "(V)"); + OUTS (outf, " (V)"); } else if (sop == 0 && sopcde == 4) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=PACK"); - OUTS (outf, "("); + OUTS (outf, " = PACK ("); OUTS (outf, dregs_lo (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs_lo (src0)); OUTS (outf, ")"); } else if (sop == 1 && sopcde == 4) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=PACK("); + OUTS (outf, " = PACK ("); OUTS (outf, dregs_lo (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs_hi (src0)); OUTS (outf, ")"); } else if (sop == 2 && sopcde == 4) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=PACK("); + OUTS (outf, " = PACK ("); OUTS (outf, dregs_hi (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs_lo (src0)); OUTS (outf, ")"); } else if (sop == 3 && sopcde == 4) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=PACK("); + OUTS (outf, " = PACK ("); OUTS (outf, dregs_hi (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs_hi (src0)); OUTS (outf, ")"); } else if (sop == 0 && sopcde == 5) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=SIGNBITS "); + OUTS (outf, " = SIGNBITS "); OUTS (outf, dregs (src1)); } else if (sop == 1 && sopcde == 5) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=SIGNBITS "); + OUTS (outf, " = SIGNBITS "); OUTS (outf, dregs_lo (src1)); } else if (sop == 2 && sopcde == 5) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=SIGNBITS "); + OUTS (outf, " = SIGNBITS "); OUTS (outf, dregs_hi (src1)); } else if (sop == 0 && sopcde == 6) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=SIGNBITS A0"); + OUTS (outf, " = SIGNBITS A0"); } else if (sop == 1 && sopcde == 6) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=SIGNBITS A1"); + OUTS (outf, " = SIGNBITS A1"); } else if (sop == 3 && sopcde == 6) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=ONES "); + OUTS (outf, " = ONES "); OUTS (outf, dregs (src1)); } else if (sop == 0 && sopcde == 7) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=EXPADJ ("); + OUTS (outf, " = EXPADJ ("); OUTS (outf, dregs (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs_lo (src0)); OUTS (outf, ")"); } else if (sop == 1 && sopcde == 7) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=EXPADJ ("); + OUTS (outf, " = EXPADJ ("); OUTS (outf, dregs (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs_lo (src0)); OUTS (outf, ") (V)"); } else if (sop == 2 && sopcde == 7) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=EXPADJ ("); + OUTS (outf, " = EXPADJ ("); OUTS (outf, dregs_lo (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs_lo (src0)); OUTS (outf, ")"); } else if (sop == 3 && sopcde == 7) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=EXPADJ ("); + OUTS (outf, " = EXPADJ ("); OUTS (outf, dregs_hi (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs_lo (src0)); OUTS (outf, ")"); } @@ -4053,132 +4170,132 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) { OUTS (outf, "BITMUX ("); OUTS (outf, dregs (src0)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src1)); - OUTS (outf, ",A0 )(ASR)"); + OUTS (outf, ", A0) (ASR)"); } else if (sop == 1 && sopcde == 8) { OUTS (outf, "BITMUX ("); OUTS (outf, dregs (src0)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src1)); - OUTS (outf, ",A0 )(ASL)"); + OUTS (outf, ", A0) (ASL)"); } else if (sop == 0 && sopcde == 9) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=VIT_MAX ("); + OUTS (outf, " = VIT_MAX ("); OUTS (outf, dregs (src1)); OUTS (outf, ") (ASL)"); } else if (sop == 1 && sopcde == 9) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=VIT_MAX ("); + OUTS (outf, " = VIT_MAX ("); OUTS (outf, dregs (src1)); OUTS (outf, ") (ASR)"); } else if (sop == 2 && sopcde == 9) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=VIT_MAX("); + OUTS (outf, " = VIT_MAX ("); OUTS (outf, dregs (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src0)); - OUTS (outf, ")(ASL)"); + OUTS (outf, ") (ASL)"); } else if (sop == 3 && sopcde == 9) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=VIT_MAX("); + OUTS (outf, " = VIT_MAX ("); OUTS (outf, dregs (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src0)); - OUTS (outf, ")(ASR)"); + OUTS (outf, ") (ASR)"); } else if (sop == 0 && sopcde == 10) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=EXTRACT("); + OUTS (outf, " = EXTRACT ("); OUTS (outf, dregs (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs_lo (src0)); OUTS (outf, ") (Z)"); } else if (sop == 1 && sopcde == 10) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=EXTRACT("); + OUTS (outf, " = EXTRACT ("); OUTS (outf, dregs (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs_lo (src0)); - OUTS (outf, ")(X)"); + OUTS (outf, ") (X)"); } else if (sop == 2 && sopcde == 10) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=DEPOSIT("); + OUTS (outf, " = DEPOSIT ("); OUTS (outf, dregs (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src0)); OUTS (outf, ")"); } else if (sop == 3 && sopcde == 10) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=DEPOSIT("); + OUTS (outf, " = DEPOSIT ("); OUTS (outf, dregs (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src0)); - OUTS (outf, ")(X)"); + OUTS (outf, ") (X)"); } else if (sop == 0 && sopcde == 11) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=CC=BXORSHIFT(A0,"); + OUTS (outf, " = CC = BXORSHIFT (A0, "); OUTS (outf, dregs (src0)); OUTS (outf, ")"); } else if (sop == 1 && sopcde == 11) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=CC=BXOR(A0,"); + OUTS (outf, " = CC = BXOR (A0, "); OUTS (outf, dregs (src0)); OUTS (outf, ")"); } else if (sop == 0 && sopcde == 12) - OUTS (outf, "A0=BXORSHIFT(A0,A1 ,CC)"); + OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)"); else if (sop == 1 && sopcde == 12) { OUTS (outf, dregs_lo (dst0)); - OUTS (outf, "=CC=BXOR( A0,A1 ,CC )"); + OUTS (outf, " = CC = BXOR (A0, A1, CC)"); } else if (sop == 0 && sopcde == 13) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=ALIGN8("); + OUTS (outf, " = ALIGN8 ("); OUTS (outf, dregs (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src0)); OUTS (outf, ")"); } else if (sop == 1 && sopcde == 13) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=ALIGN16("); + OUTS (outf, " = ALIGN16 ("); OUTS (outf, dregs (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src0)); OUTS (outf, ")"); } else if (sop == 2 && sopcde == 13) { OUTS (outf, dregs (dst0)); - OUTS (outf, "=ALIGN24("); + OUTS (outf, " = ALIGN24 ("); OUTS (outf, dregs (src1)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, dregs (src0)); OUTS (outf, ")"); } @@ -4250,66 +4367,66 @@ decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf) } else if (sop == 2 && sopcde == 3 && HLs == 1) { - OUTS (outf, "A1= ROT A1 BY "); + OUTS (outf, "A1 = ROT A1 BY "); OUTS (outf, imm6 (immag)); } else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0) { - OUTS (outf, "A0=A0<<"); + OUTS (outf, "A0 = A0 << "); OUTS (outf, uimm5 (immag)); } else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1) { - OUTS (outf, "A0=A0>>>"); + OUTS (outf, "A0 = A0 >>> "); OUTS (outf, uimm5 (newimmag)); } else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0) { - OUTS (outf, "A1=A1<<"); + OUTS (outf, "A1 = A1 << "); OUTS (outf, uimm5 (immag)); } else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1) { - OUTS (outf, "A1=A1>>>"); + OUTS (outf, "A1 = A1 >>> "); OUTS (outf, uimm5 (newimmag)); } else if (sop == 1 && sopcde == 3 && HLs == 0) { - OUTS (outf, "A0=A0>>"); + OUTS (outf, "A0 = A0 >> "); OUTS (outf, uimm5 (newimmag)); } else if (sop == 1 && sopcde == 3 && HLs == 1) { - OUTS (outf, "A1=A1>>"); + OUTS (outf, "A1 = A1 >> "); OUTS (outf, uimm5 (newimmag)); } else if (sop == 2 && sopcde == 3 && HLs == 0) { - OUTS (outf, "A0= ROT A0 BY "); + OUTS (outf, "A0 = ROT A0 BY "); OUTS (outf, imm6 (immag)); } else if (sop == 1 && sopcde == 1 && bit8 == 0) { OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src1)); - OUTS (outf, "<<"); + OUTS (outf, " << "); OUTS (outf, uimm5 (immag)); OUTS (outf, " (V, S)"); } else if (sop == 1 && sopcde == 1 && bit8 == 1) { OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src1)); - OUTS (outf, ">>>"); + OUTS (outf, " >>> "); OUTS (outf, imm5 (-immag)); OUTS (outf, " (V)"); } else if (sop == 2 && sopcde == 1 && bit8 == 1) { OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src1)); OUTS (outf, " >> "); OUTS (outf, uimm5 (newimmag)); @@ -4318,50 +4435,50 @@ decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (sop == 2 && sopcde == 1 && bit8 == 0) { OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src1)); - OUTS (outf, "<<"); + OUTS (outf, " << "); OUTS (outf, imm5 (immag)); OUTS (outf, " (V)"); } else if (sop == 0 && sopcde == 1) { OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src1)); - OUTS (outf, ">>>"); + OUTS (outf, " >>> "); OUTS (outf, uimm5 (newimmag)); OUTS (outf, " (V)"); } else if (sop == 1 && sopcde == 2) { OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src1)); - OUTS (outf, "<<"); + OUTS (outf, " << "); OUTS (outf, uimm5 (immag)); - OUTS (outf, "(S)"); + OUTS (outf, " (S)"); } else if (sop == 2 && sopcde == 2 && bit8 == 1) { OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src1)); - OUTS (outf, ">>"); + OUTS (outf, " >> "); OUTS (outf, uimm5 (newimmag)); } else if (sop == 2 && sopcde == 2 && bit8 == 0) { OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src1)); - OUTS (outf, "<<"); + OUTS (outf, " << "); OUTS (outf, uimm5 (immag)); } else if (sop == 3 && sopcde == 2) { OUTS (outf, dregs (dst0)); - OUTS (outf, "= ROT "); + OUTS (outf, " = ROT "); OUTS (outf, dregs (src1)); OUTS (outf, " BY "); OUTS (outf, imm6 (immag)); @@ -4369,9 +4486,9 @@ decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (sop == 0 && sopcde == 2) { OUTS (outf, dregs (dst0)); - OUTS (outf, "="); + OUTS (outf, " = "); OUTS (outf, dregs (src1)); - OUTS (outf, ">>>"); + OUTS (outf, " >>> "); OUTS (outf, uimm5 (newimmag)); } else @@ -4408,7 +4525,7 @@ decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf) else if (reg == 6 && fn == 3) { - OUTS (outf, "DBGCMPLX("); + OUTS (outf, "DBGCMPLX ("); OUTS (outf, dregs (grp)); OUTS (outf, ")"); } @@ -4450,33 +4567,33 @@ decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf) if (dbgop == 0) { - OUTS (outf, "DBGA("); + OUTS (outf, "DBGA ("); OUTS (outf, dregs_lo (regtest)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, uimm16 (expected)); OUTS (outf, ")"); } else if (dbgop == 1) { - OUTS (outf, "DBGA("); + OUTS (outf, "DBGA ("); OUTS (outf, dregs_hi (regtest)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, uimm16 (expected)); OUTS (outf, ")"); } else if (dbgop == 2) { - OUTS (outf, "DBGAL("); + OUTS (outf, "DBGAL ("); OUTS (outf, dregs (regtest)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, uimm16 (expected)); OUTS (outf, ")"); } else if (dbgop == 3) { - OUTS (outf, "DBGAH("); + OUTS (outf, "DBGAH ("); OUTS (outf, dregs (regtest)); - OUTS (outf, ","); + OUTS (outf, ", "); OUTS (outf, uimm16 (expected)); OUTS (outf, ")"); } @@ -4502,7 +4619,7 @@ _print_insn_bfin (bfd_vma pc, disassemble_info *outf) if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800) { - OUTS (outf, "mnop"); + OUTS (outf, "MNOP"); return 4; } else if ((iw0 & 0xff00) == 0x0000) @@ -4604,16 +4721,22 @@ print_insn_bfin (bfd_vma pc, disassemble_info *outf) if ((iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS) && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ )) { + parallel = 1; outf->fprintf_func (outf->stream, " || "); count += _print_insn_bfin (pc + 4, outf); outf->fprintf_func (outf->stream, " || "); count += _print_insn_bfin (pc + 6, outf); + parallel = 0; } if (count == 0) { outf->fprintf_func (outf->stream, "ILLEGAL"); return 2; } - outf->fprintf_func (outf->stream, ";"); + if (!comment) + outf->fprintf_func (outf->stream, ";"); + + comment = 0; + return count; } |