diff options
| author | Luis Machado <luisgpm@br.ibm.com> | 2008-08-15 15:18:34 +0000 |
|---|---|---|
| committer | Luis Machado <luisgpm@br.ibm.com> | 2008-08-15 15:18:34 +0000 |
| commit | 604c2f837ca75dbfd0331a7d8a7f9504ca1d9b53 (patch) | |
| tree | 4fabd1fa23ecde79e1eb19aa6b9185e7099cc1e2 | |
| parent | 7dc6076f0ce4ca5d95e4a564677a3af3a253ea3c (diff) | |
| download | gdb-604c2f837ca75dbfd0331a7d8a7f9504ca1d9b53.zip gdb-604c2f837ca75dbfd0331a7d8a7f9504ca1d9b53.tar.gz gdb-604c2f837ca75dbfd0331a7d8a7f9504ca1d9b53.tar.bz2 | |
* rs6000-tdep: Include "features/rs6000/powerpc-vsx32.c".
Include "features/rs6000/powerpc-vsx64.c".
(ppc_supply_vsxregset): New function.
(ppc_collect_vsxregset): New function.
(IS_VSX_PSEUDOREG): New macro.
(IS_EFP_PSEUDOREG): New macro.
(vsx_register_p): New function.
(ppc_vsx_support_p): New function.
(rs6000_builtin_type_vec128): New function.
(rs6000_register_name): Hide upper halves of vs0~vs31. Return
correct names for VSX registers and EFPR registers.
(rs6000_pseudo_register_type): Return correct types for VSX
and EFPR registers.
(rs6000_pseudo_register_reggroup_p): Return correct group for
VSX and EFPR registers.
(ppc_pseudo_register_read): Rename to dfp_pseudo_register_read.
(ppc_pseudo_register_write): Rename to dfp_pseudo_register_write.
(vsx_pseudo_register_read): New function.
(vsx_pseudo_register_write): New function.
(efpr_pseudo_register_read): New function.
(efpr_pseudo_register_write): New function.
(rs6000_pseudo_register_read): Call new VSX and EFPR read functions.
(rs6000_pseudo_register_write): Call new VSX and EFPR write functions.
(rs6000_gdbarch_init): Declare have_vsx.
Initialize new upper half VSX registers.
Initialize VSX-related and EFPR-related pseudo-registers variables.
Adjust the number of pseudo registers accordingly.
* ppc-linux-nat.c: Define PTRACE_GETVSXREGS, PTRACE_SETVSXREGS
and SIZEOF_VSRREGS.
(gdb_vsxregset_t): New type.
(have_ptrace_getsetvsxregs): New variable.
(fetch_vsx_register): New function.
(fetch_register): Handle VSX registers.
(fetch_vsx_registers): New function.
(fetch_ppc_registers): Handle VSX registers.
(store_ppc_registers): Handle VSX registers.
(store_vsx_register): New function.
(store_register): Handle VSX registers.
(store_vsx_registers): New function.
(ppc_linux_read_description): Handle VSX-enabled inferiors.
(gdb_vsxregset_t): New type.
(supply_vsxregset): New function.
(fill_vsxregset): New function.
* ppc-tdep.h (vsx_register_p): New prototype.
(vsx_support_p): New prototype.
(ppc_vsr0_regnum): New variable.
(ppc_vsr0_upper_regnum): Likewise.
(ppc_efpr0_regnum): Likewise.
(ppc_builtin_type_vec128): New type.
(ppc_num_vsrs): New constant.
(ppc_num_vshrs): New constant.
(ppc_num_efprs): Likewise.
Define POWERPC_VEC_VSX PPC_VSR0_UPPER_REGNUM and PPC_VSR31_UPPER_REGNUM.
(ppc_supply_vsxregset): New prototype.
(ppc_collect_vsxregset): New prototype.
* ppc-linux-tdep.c: Include "features/rs6000/powerpc-vsx32l.c"
Include "features/rs6000/powerpc-vsx64l.c".
(_initialize_ppc_linux_tdep): Initialize VSX-enabled targets.
(ppc_linux_regset_sections): Add new ".reg-ppc-vsx" field.
(ppc32_linux_vsxregset): New 32-bit VSX-enabled regset.
(ppc_linux_regset_from_core_section): Handle VSX core section.
(ppc_linux_core_read_description): Support VSX-enabled core files.
* ppc-linux-tdep.h: Declare *tdesc_powerpc_vsx32l
Declare tdesc_powerpc_vsx64l
* corelow.c (get_core_register_section): Support VSX-enabled
core files.
* features/rs6000/power-vsx.xml: New VSX descriptions.
* features/rs6000/powerpc-vsx32.xml: New file.
* features/rs6000/powerpc-vsx32l.xml: New file.
* features/rs6000/powerpc-vsx64.xml: New file.
* features/rs6000/powerpc-vsx64l.xml: New file.
* features/rs6000/powerpc-vsx32.c: New file (generated).
* features/rs6000/powerpc-vsx32l.c: New file (generated).
* features/rs6000/powerpc-vsx64.c: New file (generated).
* features/rs6000/powerpc-vsx64l.c: New file (generated).
* features/Makefile: Updated with new descriptions.
* regformats/rs6000/powerpc-vsx32l.dat: New file (generated).
* regformats/rs6000/powerpc-vsx64l.dat: New file (generated).
* testsuite/gdb.arch/vsx-regs.c: New source file.
* testsuite/gdb.arch/vsx-regs.exp: New testcase.
* testsuite/lib/gdb.exp (skip_vsx_tests): New function.
| -rw-r--r-- | gdb/ChangeLog | 87 | ||||
| -rw-r--r-- | gdb/corelow.c | 2 | ||||
| -rw-r--r-- | gdb/features/Makefile | 6 | ||||
| -rw-r--r-- | gdb/features/rs6000/power-vsx.xml | 44 | ||||
| -rw-r--r-- | gdb/features/rs6000/powerpc-vsx32.c | 198 | ||||
| -rw-r--r-- | gdb/features/rs6000/powerpc-vsx32.xml | 18 | ||||
| -rw-r--r-- | gdb/features/rs6000/powerpc-vsx32l.c | 202 | ||||
| -rw-r--r-- | gdb/features/rs6000/powerpc-vsx32l.xml | 20 | ||||
| -rw-r--r-- | gdb/features/rs6000/powerpc-vsx64.c | 198 | ||||
| -rw-r--r-- | gdb/features/rs6000/powerpc-vsx64.xml | 18 | ||||
| -rw-r--r-- | gdb/features/rs6000/powerpc-vsx64l.c | 202 | ||||
| -rw-r--r-- | gdb/features/rs6000/powerpc-vsx64l.xml | 20 | ||||
| -rw-r--r-- | gdb/ppc-linux-nat.c | 222 | ||||
| -rw-r--r-- | gdb/ppc-linux-tdep.c | 29 | ||||
| -rw-r--r-- | gdb/ppc-linux-tdep.h | 2 | ||||
| -rw-r--r-- | gdb/ppc-tdep.h | 40 | ||||
| -rw-r--r-- | gdb/regformats/rs6000/powerpc-vsx32l.dat | 143 | ||||
| -rw-r--r-- | gdb/regformats/rs6000/powerpc-vsx64l.dat | 143 | ||||
| -rw-r--r-- | gdb/rs6000-tdep.c | 385 | ||||
| -rw-r--r-- | gdb/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gdb/testsuite/gdb.arch/vsx-regs.c | 41 | ||||
| -rw-r--r-- | gdb/testsuite/gdb.arch/vsx-regs.exp | 193 | ||||
| -rw-r--r-- | gdb/testsuite/lib/gdb.exp | 86 |
23 files changed, 2272 insertions, 33 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 417fed9..4cc052a 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,90 @@ +2008-08-15 Luis Machado <luisgpm@br.ibm.com> + + * rs6000-tdep: Include "features/rs6000/powerpc-vsx32.c". + Include "features/rs6000/powerpc-vsx64.c". + (ppc_supply_vsxregset): New function. + (ppc_collect_vsxregset): New function. + (IS_VSX_PSEUDOREG): New macro. + (IS_EFP_PSEUDOREG): New macro. + (vsx_register_p): New function. + (ppc_vsx_support_p): New function. + (rs6000_builtin_type_vec128): New function. + (rs6000_register_name): Hide upper halves of vs0~vs31. Return + correct names for VSX registers and EFPR registers. + (rs6000_pseudo_register_type): Return correct types for VSX + and EFPR registers. + (rs6000_pseudo_register_reggroup_p): Return correct group for + VSX and EFPR registers. + (ppc_pseudo_register_read): Rename to dfp_pseudo_register_read. + (ppc_pseudo_register_write): Rename to dfp_pseudo_register_write. + (vsx_pseudo_register_read): New function. + (vsx_pseudo_register_write): New function. + (efpr_pseudo_register_read): New function. + (efpr_pseudo_register_write): New function. + (rs6000_pseudo_register_read): Call new VSX and EFPR read functions. + (rs6000_pseudo_register_write): Call new VSX and EFPR write functions. + (rs6000_gdbarch_init): Declare have_vsx. + Initialize new upper half VSX registers. + Initialize VSX-related and EFPR-related pseudo-registers variables. + Adjust the number of pseudo registers accordingly. + + * ppc-linux-nat.c: Define PTRACE_GETVSXREGS, PTRACE_SETVSXREGS + and SIZEOF_VSRREGS. + (gdb_vsxregset_t): New type. + (have_ptrace_getsetvsxregs): New variable. + (fetch_vsx_register): New function. + (fetch_register): Handle VSX registers. + (fetch_vsx_registers): New function. + (fetch_ppc_registers): Handle VSX registers. + (store_ppc_registers): Handle VSX registers. + (store_vsx_register): New function. + (store_register): Handle VSX registers. + (store_vsx_registers): New function. + (ppc_linux_read_description): Handle VSX-enabled inferiors. + (gdb_vsxregset_t): New type. + (supply_vsxregset): New function. + (fill_vsxregset): New function. + + * ppc-tdep.h (vsx_register_p): New prototype. + (vsx_support_p): New prototype. + (ppc_vsr0_regnum): New variable. + (ppc_vsr0_upper_regnum): Likewise. + (ppc_efpr0_regnum): Likewise. + (ppc_builtin_type_vec128): New type. + (ppc_num_vsrs): New constant. + (ppc_num_vshrs): New constant. + (ppc_num_efprs): Likewise. + Define POWERPC_VEC_VSX PPC_VSR0_UPPER_REGNUM and PPC_VSR31_UPPER_REGNUM. + (ppc_supply_vsxregset): New prototype. + (ppc_collect_vsxregset): New prototype. + + * ppc-linux-tdep.c: Include "features/rs6000/powerpc-vsx32l.c" + Include "features/rs6000/powerpc-vsx64l.c". + (_initialize_ppc_linux_tdep): Initialize VSX-enabled targets. + (ppc_linux_regset_sections): Add new ".reg-ppc-vsx" field. + (ppc32_linux_vsxregset): New 32-bit VSX-enabled regset. + (ppc_linux_regset_from_core_section): Handle VSX core section. + (ppc_linux_core_read_description): Support VSX-enabled core files. + + * ppc-linux-tdep.h: Declare *tdesc_powerpc_vsx32l + Declare tdesc_powerpc_vsx64l + + * corelow.c (get_core_register_section): Support VSX-enabled + core files. + + * features/rs6000/power-vsx.xml: New VSX descriptions. + * features/rs6000/powerpc-vsx32.xml: New file. + * features/rs6000/powerpc-vsx32l.xml: New file. + * features/rs6000/powerpc-vsx64.xml: New file. + * features/rs6000/powerpc-vsx64l.xml: New file. + * features/rs6000/powerpc-vsx32.c: New file (generated). + * features/rs6000/powerpc-vsx32l.c: New file (generated). + * features/rs6000/powerpc-vsx64.c: New file (generated). + * features/rs6000/powerpc-vsx64l.c: New file (generated). + * features/Makefile: Updated with new descriptions. + * regformats/rs6000/powerpc-vsx32l.dat: New file (generated). + * regformats/rs6000/powerpc-vsx64l.dat: New file (generated). + 2008-08-15 Vladimir Prus <vladimir@codesourcery.com> * ia64-linux.nat (_initialize_ia64_linux_nat): Don't diff --git a/gdb/corelow.c b/gdb/corelow.c index 28b61e5..7c3a398 100644 --- a/gdb/corelow.c +++ b/gdb/corelow.c @@ -499,6 +499,8 @@ get_core_registers (struct regcache *regcache, int regno) ".reg-xfp", 3, "extended floating-point", 0); get_core_register_section (regcache, ".reg-ppc-vmx", 3, "ppc Altivec", 0); + get_core_register_section (regcache, + ".reg-ppc-vsx", 4, "POWER7 VSX", 0); /* Supply dummy value for all registers not found in the core. */ for (i = 0; i < gdbarch_num_regs (get_regcache_arch (regcache)); i++) diff --git a/gdb/features/Makefile b/gdb/features/Makefile index 378f764..9241e2a 100644 --- a/gdb/features/Makefile +++ b/gdb/features/Makefile @@ -33,7 +33,8 @@ WHICH = arm-with-iwmmxt mips-linux mips64-linux \ rs6000/powerpc-32l rs6000/powerpc-altivec32l rs6000/powerpc-e500l \ - rs6000/powerpc-64l rs6000/powerpc-altivec64l + rs6000/powerpc-64l rs6000/powerpc-altivec64l rs6000/powerpc-vsx32l \ + rs6000/powerpc-vsx64l # Record which registers should be sent to GDB by default after stop. arm-with-iwmmxt-expedite = r11,sp,pc @@ -41,9 +42,12 @@ mips-linux-expedite = r29,pc mips64-linux-expedite = r29,pc rs6000/powerpc-32l-expedite = r1,pc rs6000/powerpc-altivec32l-expedite = r1,pc +rs6000/powerpc-vsx32l-expedite = r1,pc rs6000/powerpc-e500l-expedite = r1,pc rs6000/powerpc-64l-expedite = r1,pc rs6000/powerpc-altivec64l-expedite = r1,pc +rs6000/powerpc-vsx64l-expedite = r1,pc + XSLTPROC = xsltproc outdir = ../regformats diff --git a/gdb/features/rs6000/power-vsx.xml b/gdb/features/rs6000/power-vsx.xml new file mode 100644 index 0000000..fa8121a --- /dev/null +++ b/gdb/features/rs6000/power-vsx.xml @@ -0,0 +1,44 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2008 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!-- POWER7 VSX registers that do not overlap existing FP and VMX + registers. --> +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.power.vsx"> + <reg name="vs0h" bitsize="64" type="uint64"/> + <reg name="vs1h" bitsize="64" type="uint64"/> + <reg name="vs2h" bitsize="64" type="uint64"/> + <reg name="vs3h" bitsize="64" type="uint64"/> + <reg name="vs4h" bitsize="64" type="uint64"/> + <reg name="vs5h" bitsize="64" type="uint64"/> + <reg name="vs6h" bitsize="64" type="uint64"/> + <reg name="vs7h" bitsize="64" type="uint64"/> + <reg name="vs8h" bitsize="64" type="uint64"/> + <reg name="vs9h" bitsize="64" type="uint64"/> + <reg name="vs10h" bitsize="64" type="uint64"/> + <reg name="vs11h" bitsize="64" type="uint64"/> + <reg name="vs12h" bitsize="64" type="uint64"/> + <reg name="vs13h" bitsize="64" type="uint64"/> + <reg name="vs14h" bitsize="64" type="uint64"/> + <reg name="vs15h" bitsize="64" type="uint64"/> + <reg name="vs16h" bitsize="64" type="uint64"/> + <reg name="vs17h" bitsize="64" type="uint64"/> + <reg name="vs18h" bitsize="64" type="uint64"/> + <reg name="vs19h" bitsize="64" type="uint64"/> + <reg name="vs20h" bitsize="64" type="uint64"/> + <reg name="vs21h" bitsize="64" type="uint64"/> + <reg name="vs22h" bitsize="64" type="uint64"/> + <reg name="vs23h" bitsize="64" type="uint64"/> + <reg name="vs24h" bitsize="64" type="uint64"/> + <reg name="vs25h" bitsize="64" type="uint64"/> + <reg name="vs26h" bitsize="64" type="uint64"/> + <reg name="vs27h" bitsize="64" type="uint64"/> + <reg name="vs28h" bitsize="64" type="uint64"/> + <reg name="vs29h" bitsize="64" type="uint64"/> + <reg name="vs30h" bitsize="64" type="uint64"/> + <reg name="vs31h" bitsize="64" type="uint64"/> +</feature> diff --git a/gdb/features/rs6000/powerpc-vsx32.c b/gdb/features/rs6000/powerpc-vsx32.c new file mode 100644 index 0000000..560b48f --- /dev/null +++ b/gdb/features/rs6000/powerpc-vsx32.c @@ -0,0 +1,198 @@ +/* THIS FILE IS GENERATED. Original: powerpc-vsx32.xml */ + +#include "defs.h" +#include "gdbtypes.h" +#include "target-descriptions.h" + +struct target_desc *tdesc_powerpc_vsx32; +static void +initialize_tdesc_powerpc_vsx32 (void) +{ + struct target_desc *result = allocate_target_description (); + struct tdesc_feature *feature; + struct type *field_type, *type; + + set_tdesc_architecture (result, bfd_scan_arch ("powerpc:common")); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.core"); + tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r13", 13, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r14", 14, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r15", 15, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r16", 16, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r17", 17, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r18", 18, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r19", 19, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r20", 20, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r21", 21, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r22", 22, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r23", 23, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r24", 24, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r25", 25, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r26", 26, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r27", 27, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r28", 28, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "pc", 64, 1, NULL, 32, "code_ptr"); + tdesc_create_reg (feature, "msr", 65, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "cr", 66, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "lr", 67, 1, NULL, 32, "code_ptr"); + tdesc_create_reg (feature, "ctr", 68, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "xer", 69, 1, NULL, 32, "uint32"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.fpu"); + tdesc_create_reg (feature, "f0", 32, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f1", 33, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f2", 34, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f3", 35, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f4", 36, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f5", 37, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f6", 38, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f7", 39, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f8", 40, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f9", 41, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f10", 42, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f11", 43, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f12", 44, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f13", 45, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f14", 46, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f15", 47, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f16", 48, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f17", 49, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f18", 50, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f19", 51, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f20", 52, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f21", 53, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f22", 54, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f23", 55, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f24", 56, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f25", 57, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f26", 58, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f27", 59, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f28", 60, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f29", 61, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f30", 62, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f31", 63, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "fpscr", 70, 1, "float", 32, "int"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.altivec"); + field_type = tdesc_named_type (feature, "ieee_single"); + type = init_vector_type (field_type, 4); + TYPE_NAME (type) = xstrdup ("v4f"); + tdesc_record_type (feature, type); + + field_type = tdesc_named_type (feature, "int32"); + type = init_vector_type (field_type, 4); + TYPE_NAME (type) = xstrdup ("v4i32"); + tdesc_record_type (feature, type); + + field_type = tdesc_named_type (feature, "int16"); + type = init_vector_type (field_type, 8); + TYPE_NAME (type) = xstrdup ("v8i16"); + tdesc_record_type (feature, type); + + field_type = tdesc_named_type (feature, "int8"); + type = init_vector_type (field_type, 16); + TYPE_NAME (type) = xstrdup ("v16i8"); + tdesc_record_type (feature, type); + + type = init_composite_type (NULL, TYPE_CODE_UNION); + TYPE_NAME (type) = xstrdup ("vec128"); + field_type = tdesc_named_type (feature, "uint128"); + append_composite_type_field (type, xstrdup ("uint128"), field_type); + field_type = tdesc_named_type (feature, "v4f"); + append_composite_type_field (type, xstrdup ("v4_float"), field_type); + field_type = tdesc_named_type (feature, "v4i32"); + append_composite_type_field (type, xstrdup ("v4_int32"), field_type); + field_type = tdesc_named_type (feature, "v8i16"); + append_composite_type_field (type, xstrdup ("v8_int16"), field_type); + field_type = tdesc_named_type (feature, "v16i8"); + append_composite_type_field (type, xstrdup ("v16_int8"), field_type); + TYPE_FLAGS (type) |= TYPE_FLAG_VECTOR; + tdesc_record_type (feature, type); + + tdesc_create_reg (feature, "vr0", 71, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr1", 72, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr2", 73, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr3", 74, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr4", 75, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr5", 76, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr6", 77, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr7", 78, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr8", 79, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr9", 80, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr10", 81, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr11", 82, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr12", 83, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr13", 84, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr14", 85, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr15", 86, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr16", 87, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr17", 88, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr18", 89, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr19", 90, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr20", 91, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr21", 92, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr22", 93, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr23", 94, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr24", 95, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr25", 96, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr26", 97, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr27", 98, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr28", 99, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr29", 100, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr30", 101, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr31", 102, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vscr", 103, 1, "vector", 32, "int"); + tdesc_create_reg (feature, "vrsave", 104, 1, "vector", 32, "int"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.vsx"); + tdesc_create_reg (feature, "vs0h", 105, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs1h", 106, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs2h", 107, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs3h", 108, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs4h", 109, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs5h", 110, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs6h", 111, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs7h", 112, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs8h", 113, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs9h", 114, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs10h", 115, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs11h", 116, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs12h", 117, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs13h", 118, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs14h", 119, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs15h", 120, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs16h", 121, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs17h", 122, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs18h", 123, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs19h", 124, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs20h", 125, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs21h", 126, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs22h", 127, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs23h", 128, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs24h", 129, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs25h", 130, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs26h", 131, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs27h", 132, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs28h", 133, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs29h", 134, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs30h", 135, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs31h", 136, 1, NULL, 64, "uint64"); + + tdesc_powerpc_vsx32 = result; +} diff --git a/gdb/features/rs6000/powerpc-vsx32.xml b/gdb/features/rs6000/powerpc-vsx32.xml new file mode 100644 index 0000000..c216c94 --- /dev/null +++ b/gdb/features/rs6000/powerpc-vsx32.xml @@ -0,0 +1,18 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2008 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!-- PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only + view of the PowerPC. Includes AltiVec and VSX vector registers. --> + +<!DOCTYPE target SYSTEM "gdb-target.dtd"> +<target> + <architecture>powerpc:common</architecture> + <xi:include href="power-core.xml"/> + <xi:include href="power-fpu.xml"/> + <xi:include href="power-altivec.xml"/> + <xi:include href="power-vsx.xml"/> +</target> diff --git a/gdb/features/rs6000/powerpc-vsx32l.c b/gdb/features/rs6000/powerpc-vsx32l.c new file mode 100644 index 0000000..bedf039 --- /dev/null +++ b/gdb/features/rs6000/powerpc-vsx32l.c @@ -0,0 +1,202 @@ +/* THIS FILE IS GENERATED. Original: powerpc-vsx32l.xml */ + +#include "defs.h" +#include "gdbtypes.h" +#include "target-descriptions.h" + +struct target_desc *tdesc_powerpc_vsx32l; +static void +initialize_tdesc_powerpc_vsx32l (void) +{ + struct target_desc *result = allocate_target_description (); + struct tdesc_feature *feature; + struct type *field_type, *type; + + set_tdesc_architecture (result, bfd_scan_arch ("powerpc:common")); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.core"); + tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r13", 13, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r14", 14, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r15", 15, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r16", 16, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r17", 17, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r18", 18, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r19", 19, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r20", 20, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r21", 21, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r22", 22, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r23", 23, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r24", 24, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r25", 25, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r26", 26, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r27", 27, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r28", 28, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "pc", 64, 1, NULL, 32, "code_ptr"); + tdesc_create_reg (feature, "msr", 65, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "cr", 66, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "lr", 67, 1, NULL, 32, "code_ptr"); + tdesc_create_reg (feature, "ctr", 68, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "xer", 69, 1, NULL, 32, "uint32"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.fpu"); + tdesc_create_reg (feature, "f0", 32, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f1", 33, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f2", 34, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f3", 35, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f4", 36, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f5", 37, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f6", 38, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f7", 39, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f8", 40, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f9", 41, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f10", 42, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f11", 43, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f12", 44, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f13", 45, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f14", 46, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f15", 47, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f16", 48, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f17", 49, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f18", 50, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f19", 51, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f20", 52, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f21", 53, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f22", 54, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f23", 55, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f24", 56, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f25", 57, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f26", 58, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f27", 59, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f28", 60, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f29", 61, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f30", 62, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f31", 63, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "fpscr", 70, 1, "float", 32, "int"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.linux"); + tdesc_create_reg (feature, "orig_r3", 71, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "trap", 72, 1, NULL, 32, "int"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.altivec"); + field_type = tdesc_named_type (feature, "ieee_single"); + type = init_vector_type (field_type, 4); + TYPE_NAME (type) = xstrdup ("v4f"); + tdesc_record_type (feature, type); + + field_type = tdesc_named_type (feature, "int32"); + type = init_vector_type (field_type, 4); + TYPE_NAME (type) = xstrdup ("v4i32"); + tdesc_record_type (feature, type); + + field_type = tdesc_named_type (feature, "int16"); + type = init_vector_type (field_type, 8); + TYPE_NAME (type) = xstrdup ("v8i16"); + tdesc_record_type (feature, type); + + field_type = tdesc_named_type (feature, "int8"); + type = init_vector_type (field_type, 16); + TYPE_NAME (type) = xstrdup ("v16i8"); + tdesc_record_type (feature, type); + + type = init_composite_type (NULL, TYPE_CODE_UNION); + TYPE_NAME (type) = xstrdup ("vec128"); + field_type = tdesc_named_type (feature, "uint128"); + append_composite_type_field (type, xstrdup ("uint128"), field_type); + field_type = tdesc_named_type (feature, "v4f"); + append_composite_type_field (type, xstrdup ("v4_float"), field_type); + field_type = tdesc_named_type (feature, "v4i32"); + append_composite_type_field (type, xstrdup ("v4_int32"), field_type); + field_type = tdesc_named_type (feature, "v8i16"); + append_composite_type_field (type, xstrdup ("v8_int16"), field_type); + field_type = tdesc_named_type (feature, "v16i8"); + append_composite_type_field (type, xstrdup ("v16_int8"), field_type); + TYPE_FLAGS (type) |= TYPE_FLAG_VECTOR; + tdesc_record_type (feature, type); + + tdesc_create_reg (feature, "vr0", 73, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr1", 74, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr2", 75, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr3", 76, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr4", 77, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr5", 78, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr6", 79, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr7", 80, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr8", 81, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr9", 82, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr10", 83, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr11", 84, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr12", 85, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr13", 86, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr14", 87, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr15", 88, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr16", 89, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr17", 90, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr18", 91, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr19", 92, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr20", 93, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr21", 94, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr22", 95, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr23", 96, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr24", 97, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr25", 98, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr26", 99, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr27", 100, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr28", 101, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr29", 102, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr30", 103, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr31", 104, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vscr", 105, 1, "vector", 32, "int"); + tdesc_create_reg (feature, "vrsave", 106, 1, "vector", 32, "int"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.vsx"); + tdesc_create_reg (feature, "vs0h", 107, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs1h", 108, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs2h", 109, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs3h", 110, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs4h", 111, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs5h", 112, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs6h", 113, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs7h", 114, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs8h", 115, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs9h", 116, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs10h", 117, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs11h", 118, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs12h", 119, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs13h", 120, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs14h", 121, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs15h", 122, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs16h", 123, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs17h", 124, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs18h", 125, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs19h", 126, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs20h", 127, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs21h", 128, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs22h", 129, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs23h", 130, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs24h", 131, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs25h", 132, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs26h", 133, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs27h", 134, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs28h", 135, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs29h", 136, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs30h", 137, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs31h", 138, 1, NULL, 64, "uint64"); + + tdesc_powerpc_vsx32l = result; +} diff --git a/gdb/features/rs6000/powerpc-vsx32l.xml b/gdb/features/rs6000/powerpc-vsx32l.xml new file mode 100644 index 0000000..671141d --- /dev/null +++ b/gdb/features/rs6000/powerpc-vsx32l.xml @@ -0,0 +1,20 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2008 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!-- PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only + view of the PowerPC. Includes Linux-only special "registers", AltiVec + and VSX vector registers. --> + +<!DOCTYPE target SYSTEM "gdb-target.dtd"> +<target> + <architecture>powerpc:common</architecture> + <xi:include href="power-core.xml"/> + <xi:include href="power-fpu.xml"/> + <xi:include href="power-linux.xml"/> + <xi:include href="power-altivec.xml"/> + <xi:include href="power-vsx.xml"/> +</target> diff --git a/gdb/features/rs6000/powerpc-vsx64.c b/gdb/features/rs6000/powerpc-vsx64.c new file mode 100644 index 0000000..da6b0fc --- /dev/null +++ b/gdb/features/rs6000/powerpc-vsx64.c @@ -0,0 +1,198 @@ +/* THIS FILE IS GENERATED. Original: powerpc-vsx64.xml */ + +#include "defs.h" +#include "gdbtypes.h" +#include "target-descriptions.h" + +struct target_desc *tdesc_powerpc_vsx64; +static void +initialize_tdesc_powerpc_vsx64 (void) +{ + struct target_desc *result = allocate_target_description (); + struct tdesc_feature *feature; + struct type *field_type, *type; + + set_tdesc_architecture (result, bfd_scan_arch ("powerpc:common64")); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.core"); + tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "pc", 64, 1, NULL, 64, "code_ptr"); + tdesc_create_reg (feature, "msr", 65, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "cr", 66, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "lr", 67, 1, NULL, 64, "code_ptr"); + tdesc_create_reg (feature, "ctr", 68, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "xer", 69, 1, NULL, 32, "uint32"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.fpu"); + tdesc_create_reg (feature, "f0", 32, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f1", 33, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f2", 34, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f3", 35, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f4", 36, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f5", 37, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f6", 38, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f7", 39, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f8", 40, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f9", 41, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f10", 42, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f11", 43, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f12", 44, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f13", 45, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f14", 46, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f15", 47, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f16", 48, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f17", 49, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f18", 50, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f19", 51, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f20", 52, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f21", 53, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f22", 54, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f23", 55, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f24", 56, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f25", 57, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f26", 58, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f27", 59, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f28", 60, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f29", 61, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f30", 62, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f31", 63, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "fpscr", 70, 1, "float", 32, "int"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.altivec"); + field_type = tdesc_named_type (feature, "ieee_single"); + type = init_vector_type (field_type, 4); + TYPE_NAME (type) = xstrdup ("v4f"); + tdesc_record_type (feature, type); + + field_type = tdesc_named_type (feature, "int32"); + type = init_vector_type (field_type, 4); + TYPE_NAME (type) = xstrdup ("v4i32"); + tdesc_record_type (feature, type); + + field_type = tdesc_named_type (feature, "int16"); + type = init_vector_type (field_type, 8); + TYPE_NAME (type) = xstrdup ("v8i16"); + tdesc_record_type (feature, type); + + field_type = tdesc_named_type (feature, "int8"); + type = init_vector_type (field_type, 16); + TYPE_NAME (type) = xstrdup ("v16i8"); + tdesc_record_type (feature, type); + + type = init_composite_type (NULL, TYPE_CODE_UNION); + TYPE_NAME (type) = xstrdup ("vec128"); + field_type = tdesc_named_type (feature, "uint128"); + append_composite_type_field (type, xstrdup ("uint128"), field_type); + field_type = tdesc_named_type (feature, "v4f"); + append_composite_type_field (type, xstrdup ("v4_float"), field_type); + field_type = tdesc_named_type (feature, "v4i32"); + append_composite_type_field (type, xstrdup ("v4_int32"), field_type); + field_type = tdesc_named_type (feature, "v8i16"); + append_composite_type_field (type, xstrdup ("v8_int16"), field_type); + field_type = tdesc_named_type (feature, "v16i8"); + append_composite_type_field (type, xstrdup ("v16_int8"), field_type); + TYPE_FLAGS (type) |= TYPE_FLAG_VECTOR; + tdesc_record_type (feature, type); + + tdesc_create_reg (feature, "vr0", 71, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr1", 72, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr2", 73, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr3", 74, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr4", 75, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr5", 76, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr6", 77, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr7", 78, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr8", 79, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr9", 80, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr10", 81, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr11", 82, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr12", 83, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr13", 84, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr14", 85, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr15", 86, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr16", 87, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr17", 88, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr18", 89, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr19", 90, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr20", 91, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr21", 92, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr22", 93, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr23", 94, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr24", 95, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr25", 96, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr26", 97, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr27", 98, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr28", 99, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr29", 100, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr30", 101, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr31", 102, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vscr", 103, 1, "vector", 32, "int"); + tdesc_create_reg (feature, "vrsave", 104, 1, "vector", 32, "int"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.vsx"); + tdesc_create_reg (feature, "vs0h", 105, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs1h", 106, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs2h", 107, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs3h", 108, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs4h", 109, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs5h", 110, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs6h", 111, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs7h", 112, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs8h", 113, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs9h", 114, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs10h", 115, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs11h", 116, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs12h", 117, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs13h", 118, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs14h", 119, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs15h", 120, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs16h", 121, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs17h", 122, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs18h", 123, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs19h", 124, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs20h", 125, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs21h", 126, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs22h", 127, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs23h", 128, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs24h", 129, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs25h", 130, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs26h", 131, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs27h", 132, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs28h", 133, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs29h", 134, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs30h", 135, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs31h", 136, 1, NULL, 64, "uint64"); + + tdesc_powerpc_vsx64 = result; +} diff --git a/gdb/features/rs6000/powerpc-vsx64.xml b/gdb/features/rs6000/powerpc-vsx64.xml new file mode 100644 index 0000000..322850e --- /dev/null +++ b/gdb/features/rs6000/powerpc-vsx64.xml @@ -0,0 +1,18 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2008 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!-- PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only + view of the PowerPC. Includes AltiVec and VSX vector registers. --> + +<!DOCTYPE target SYSTEM "gdb-target.dtd"> +<target> + <architecture>powerpc:common64</architecture> + <xi:include href="power64-core.xml"/> + <xi:include href="power-fpu.xml"/> + <xi:include href="power-altivec.xml"/> + <xi:include href="power-vsx.xml"/> +</target> diff --git a/gdb/features/rs6000/powerpc-vsx64l.c b/gdb/features/rs6000/powerpc-vsx64l.c new file mode 100644 index 0000000..689ca67 --- /dev/null +++ b/gdb/features/rs6000/powerpc-vsx64l.c @@ -0,0 +1,202 @@ +/* THIS FILE IS GENERATED. Original: powerpc-vsx64l.xml */ + +#include "defs.h" +#include "gdbtypes.h" +#include "target-descriptions.h" + +struct target_desc *tdesc_powerpc_vsx64l; +static void +initialize_tdesc_powerpc_vsx64l (void) +{ + struct target_desc *result = allocate_target_description (); + struct tdesc_feature *feature; + struct type *field_type, *type; + + set_tdesc_architecture (result, bfd_scan_arch ("powerpc:common64")); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.core"); + tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "pc", 64, 1, NULL, 64, "code_ptr"); + tdesc_create_reg (feature, "msr", 65, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "cr", 66, 1, NULL, 32, "uint32"); + tdesc_create_reg (feature, "lr", 67, 1, NULL, 64, "code_ptr"); + tdesc_create_reg (feature, "ctr", 68, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "xer", 69, 1, NULL, 32, "uint32"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.fpu"); + tdesc_create_reg (feature, "f0", 32, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f1", 33, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f2", 34, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f3", 35, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f4", 36, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f5", 37, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f6", 38, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f7", 39, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f8", 40, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f9", 41, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f10", 42, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f11", 43, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f12", 44, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f13", 45, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f14", 46, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f15", 47, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f16", 48, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f17", 49, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f18", 50, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f19", 51, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f20", 52, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f21", 53, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f22", 54, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f23", 55, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f24", 56, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f25", 57, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f26", 58, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f27", 59, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f28", 60, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f29", 61, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f30", 62, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "f31", 63, 1, NULL, 64, "ieee_double"); + tdesc_create_reg (feature, "fpscr", 70, 1, "float", 32, "int"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.linux"); + tdesc_create_reg (feature, "orig_r3", 71, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "trap", 72, 1, NULL, 64, "int"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.altivec"); + field_type = tdesc_named_type (feature, "ieee_single"); + type = init_vector_type (field_type, 4); + TYPE_NAME (type) = xstrdup ("v4f"); + tdesc_record_type (feature, type); + + field_type = tdesc_named_type (feature, "int32"); + type = init_vector_type (field_type, 4); + TYPE_NAME (type) = xstrdup ("v4i32"); + tdesc_record_type (feature, type); + + field_type = tdesc_named_type (feature, "int16"); + type = init_vector_type (field_type, 8); + TYPE_NAME (type) = xstrdup ("v8i16"); + tdesc_record_type (feature, type); + + field_type = tdesc_named_type (feature, "int8"); + type = init_vector_type (field_type, 16); + TYPE_NAME (type) = xstrdup ("v16i8"); + tdesc_record_type (feature, type); + + type = init_composite_type (NULL, TYPE_CODE_UNION); + TYPE_NAME (type) = xstrdup ("vec128"); + field_type = tdesc_named_type (feature, "uint128"); + append_composite_type_field (type, xstrdup ("uint128"), field_type); + field_type = tdesc_named_type (feature, "v4f"); + append_composite_type_field (type, xstrdup ("v4_float"), field_type); + field_type = tdesc_named_type (feature, "v4i32"); + append_composite_type_field (type, xstrdup ("v4_int32"), field_type); + field_type = tdesc_named_type (feature, "v8i16"); + append_composite_type_field (type, xstrdup ("v8_int16"), field_type); + field_type = tdesc_named_type (feature, "v16i8"); + append_composite_type_field (type, xstrdup ("v16_int8"), field_type); + TYPE_FLAGS (type) |= TYPE_FLAG_VECTOR; + tdesc_record_type (feature, type); + + tdesc_create_reg (feature, "vr0", 73, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr1", 74, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr2", 75, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr3", 76, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr4", 77, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr5", 78, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr6", 79, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr7", 80, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr8", 81, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr9", 82, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr10", 83, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr11", 84, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr12", 85, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr13", 86, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr14", 87, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr15", 88, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr16", 89, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr17", 90, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr18", 91, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr19", 92, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr20", 93, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr21", 94, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr22", 95, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr23", 96, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr24", 97, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr25", 98, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr26", 99, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr27", 100, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr28", 101, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr29", 102, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr30", 103, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vr31", 104, 1, NULL, 128, "vec128"); + tdesc_create_reg (feature, "vscr", 105, 1, "vector", 32, "int"); + tdesc_create_reg (feature, "vrsave", 106, 1, "vector", 32, "int"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.vsx"); + tdesc_create_reg (feature, "vs0h", 107, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs1h", 108, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs2h", 109, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs3h", 110, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs4h", 111, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs5h", 112, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs6h", 113, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs7h", 114, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs8h", 115, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs9h", 116, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs10h", 117, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs11h", 118, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs12h", 119, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs13h", 120, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs14h", 121, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs15h", 122, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs16h", 123, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs17h", 124, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs18h", 125, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs19h", 126, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs20h", 127, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs21h", 128, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs22h", 129, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs23h", 130, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs24h", 131, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs25h", 132, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs26h", 133, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs27h", 134, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs28h", 135, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs29h", 136, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs30h", 137, 1, NULL, 64, "uint64"); + tdesc_create_reg (feature, "vs31h", 138, 1, NULL, 64, "uint64"); + + tdesc_powerpc_vsx64l = result; +} diff --git a/gdb/features/rs6000/powerpc-vsx64l.xml b/gdb/features/rs6000/powerpc-vsx64l.xml new file mode 100644 index 0000000..655ae5c --- /dev/null +++ b/gdb/features/rs6000/powerpc-vsx64l.xml @@ -0,0 +1,20 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2008 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!-- PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only + view of the PowerPC. Includes Linux-only special "registers", AltiVec + and VSX vector registers. --> + +<!DOCTYPE target SYSTEM "gdb-target.dtd"> +<target> + <architecture>powerpc:common64</architecture> + <xi:include href="power64-core.xml"/> + <xi:include href="power-fpu.xml"/> + <xi:include href="power64-linux.xml"/> + <xi:include href="power-altivec.xml"/> + <xi:include href="power-vsx.xml"/> +</target> diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c index db070b9..ed197f1 100644 --- a/gdb/ppc-linux-nat.c +++ b/gdb/ppc-linux-nat.c @@ -76,6 +76,11 @@ #define PTRACE_SETVRREGS 19 #endif +/* PTRACE requests for POWER7 VSX registers. */ +#ifndef PTRACE_GETVSXREGS +#define PTRACE_GETVSXREGS 27 +#define PTRACE_SETVSXREGS 28 +#endif /* Similarly for the ptrace requests for getting / setting the SPE registers (ev0 -- ev31, acc, and spefscr). See the description of @@ -127,6 +132,41 @@ typedef char gdb_vrregset_t[SIZEOF_VRREGS]; +/* This is the layout of the POWER7 VSX registers and the way they overlap + with the existing FPR and VMX registers. + + VSR doubleword 0 VSR doubleword 1 + ---------------------------------------------------------------- + VSR[0] | FPR[0] | | + ---------------------------------------------------------------- + VSR[1] | FPR[1] | | + ---------------------------------------------------------------- + | ... | | + | ... | | + ---------------------------------------------------------------- + VSR[30] | FPR[30] | | + ---------------------------------------------------------------- + VSR[31] | FPR[31] | | + ---------------------------------------------------------------- + VSR[32] | VR[0] | + ---------------------------------------------------------------- + VSR[33] | VR[1] | + ---------------------------------------------------------------- + | ... | + | ... | + ---------------------------------------------------------------- + VSR[62] | VR[30] | + ---------------------------------------------------------------- + VSR[63] | VR[31] | + ---------------------------------------------------------------- + + VSX has 64 128bit registers. The first 32 registers overlap with + the FP registers (doubleword 0) and hence extend them with additional + 64 bits (doubleword 1). The other 32 regs overlap with the VMX + registers. */ +#define SIZEOF_VSXREGS 32*8 + +typedef char gdb_vsxregset_t[SIZEOF_VSXREGS]; /* On PPC processors that support the the Signal Processing Extension (SPE) APU, the general-purpose registers are 64 bits long. @@ -152,6 +192,12 @@ struct gdb_evrregset_t unsigned long spefscr; }; +/* Non-zero if our kernel may support the PTRACE_GETVSXREGS and + PTRACE_SETVSXREGS requests, for reading and writing the VSX + POWER7 registers 0 through 31. Zero if we've tried one of them and + gotten an error. Note that VSX registers 32 through 63 overlap + with VR registers 0 through 31. */ +int have_ptrace_getsetvsxregs = 1; /* Non-zero if our kernel may support the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests, for reading and writing the Altivec @@ -239,6 +285,34 @@ ppc_register_u_addr (struct gdbarch *gdbarch, int regno) return u_addr; } +/* The Linux kernel ptrace interface for POWER7 VSX registers uses the + registers set mechanism, as opposed to the interface for all the + other registers, that stores/fetches each register individually. */ +static void +fetch_vsx_register (struct regcache *regcache, int tid, int regno) +{ + int ret; + gdb_vsxregset_t regs; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); + + ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); + if (ret < 0) + { + if (errno == EIO) + { + have_ptrace_getsetvsxregs = 0; + return; + } + perror_with_name (_("Unable to fetch VSX register")); + } + + regcache_raw_supply (regcache, regno, + regs + (regno - tdep->ppc_vsr0_upper_regnum) + * vsxregsize); +} + /* The Linux kernel ptrace interface for AltiVec registers uses the registers set mechanism, as opposed to the interface for all the other registers, that stores/fetches each register individually. */ @@ -373,6 +447,14 @@ fetch_register (struct regcache *regcache, int tid, int regno) AltiVec registers, fall through and return zeroes, because regaddr will be -1 in this case. */ } + if (vsx_register_p (gdbarch, regno)) + { + if (have_ptrace_getsetvsxregs) + { + fetch_vsx_register (regcache, tid, regno); + return; + } + } else if (spe_register_p (gdbarch, regno)) { fetch_spe_register (regcache, tid, regno); @@ -429,6 +511,21 @@ fetch_register (struct regcache *regcache, int tid, int regno) } static void +supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) +{ + int i; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); + + for (i = 0; i < ppc_num_vshrs; i++) + { + regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i, + *vsxregsetp + i * vsxregsize); + } +} + +static void supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) { int i; @@ -454,6 +551,25 @@ supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) } static void +fetch_vsx_registers (struct regcache *regcache, int tid) +{ + int ret; + gdb_vsxregset_t regs; + + ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); + if (ret < 0) + { + if (errno == EIO) + { + have_ptrace_getsetvsxregs = 0; + return; + } + perror_with_name (_("Unable to fetch VSX registers")); + } + supply_vsxregset (regcache, ®s); +} + +static void fetch_altivec_registers (struct regcache *regcache, int tid) { int ret; @@ -507,6 +623,9 @@ fetch_ppc_registers (struct regcache *regcache, int tid) if (have_ptrace_getvrregs) if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) fetch_altivec_registers (regcache, tid); + if (have_ptrace_getsetvsxregs) + if (tdep->ppc_vsr0_upper_regnum != -1) + fetch_vsx_registers (regcache, tid); if (tdep->ppc_ev0_upper_regnum >= 0) fetch_spe_register (regcache, tid, -1); } @@ -530,6 +649,35 @@ ppc_linux_fetch_inferior_registers (struct regcache *regcache, int regno) fetch_register (regcache, tid, regno); } +/* Store one VSX register. */ +static void +store_vsx_register (const struct regcache *regcache, int tid, int regno) +{ + int ret; + gdb_vsxregset_t regs; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); + + ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); + if (ret < 0) + { + if (errno == EIO) + { + have_ptrace_getsetvsxregs = 0; + return; + } + perror_with_name (_("Unable to fetch VSX register")); + } + + regcache_raw_collect (regcache, regno, regs + + (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize); + + ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); + if (ret < 0) + perror_with_name (_("Unable to store VSX register")); +} + /* Store one register. */ static void store_altivec_register (const struct regcache *regcache, int tid, int regno) @@ -668,6 +816,11 @@ store_register (const struct regcache *regcache, int tid, int regno) store_altivec_register (regcache, tid, regno); return; } + if (vsx_register_p (gdbarch, regno)) + { + store_vsx_register (regcache, tid, regno); + return; + } else if (spe_register_p (gdbarch, regno)) { store_spe_register (regcache, tid, regno); @@ -722,6 +875,19 @@ store_register (const struct regcache *regcache, int tid, int regno) } static void +fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) +{ + int i; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); + + for (i = 0; i < ppc_num_vshrs; i++) + regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i, + *vsxregsetp + i * vsxregsize); +} + +static void fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) { int i; @@ -745,6 +911,29 @@ fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) } static void +store_vsx_registers (const struct regcache *regcache, int tid) +{ + int ret; + gdb_vsxregset_t regs; + + ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); + if (ret < 0) + { + if (errno == EIO) + { + have_ptrace_getsetvsxregs = 0; + return; + } + perror_with_name (_("Couldn't get VSX registers")); + } + + fill_vsxregset (regcache, ®s); + + if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0) + perror_with_name (_("Couldn't write VSX registers")); +} + +static void store_altivec_registers (const struct regcache *regcache, int tid) { int ret; @@ -802,6 +991,9 @@ store_ppc_registers (const struct regcache *regcache, int tid) if (have_ptrace_getvrregs) if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) store_altivec_registers (regcache, tid); + if (have_ptrace_getsetvsxregs) + if (tdep->ppc_vsr0_upper_regnum != -1) + store_vsx_registers (regcache, tid); if (tdep->ppc_ev0_upper_regnum >= 0) store_spe_register (regcache, tid, -1); } @@ -1037,6 +1229,7 @@ static const struct target_desc * ppc_linux_read_description (struct target_ops *ops) { int altivec = 0; + int vsx = 0; int tid = TIDGET (inferior_ptid); if (tid == 0) @@ -1055,6 +1248,19 @@ ppc_linux_read_description (struct target_ops *ops) perror_with_name (_("Unable to fetch SPE registers")); } + if (have_ptrace_getsetvsxregs) + { + gdb_vsxregset_t vsxregset; + + if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) + vsx = 1; + + /* EIO means that the PTRACE_GETVSXREGS request isn't supported. + Anything else needs to be reported. */ + else if (errno != EIO) + perror_with_name (_("Unable to fetch VSX registers")); + } + if (have_ptrace_getvrregs) { gdb_vrregset_t vrregset; @@ -1076,11 +1282,23 @@ ppc_linux_read_description (struct target_ops *ops) errno = 0; msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0); if (errno == 0 && msr < 0) - return altivec? tdesc_powerpc_altivec64l : tdesc_powerpc_64l; + { + if (vsx) + return tdesc_powerpc_vsx64l; + else if (altivec) + return tdesc_powerpc_altivec64l; + + return tdesc_powerpc_64l; + } } #endif - return altivec? tdesc_powerpc_altivec32l : tdesc_powerpc_32l; + if (vsx) + return tdesc_powerpc_vsx32l; + else if (altivec) + return tdesc_powerpc_altivec32l; + + return tdesc_powerpc_32l; } void _initialize_ppc_linux_nat (void); diff --git a/gdb/ppc-linux-tdep.c b/gdb/ppc-linux-tdep.c index 5051cbf..ccf4085 100644 --- a/gdb/ppc-linux-tdep.c +++ b/gdb/ppc-linux-tdep.c @@ -41,8 +41,10 @@ #include "features/rs6000/powerpc-32l.c" #include "features/rs6000/powerpc-altivec32l.c" +#include "features/rs6000/powerpc-vsx32l.c" #include "features/rs6000/powerpc-64l.c" #include "features/rs6000/powerpc-altivec64l.c" +#include "features/rs6000/powerpc-vsx64l.c" #include "features/rs6000/powerpc-e500l.c" @@ -494,6 +496,7 @@ static struct core_regset_section ppc_linux_regset_sections[] = { ".reg", 268 }, { ".reg2", 264 }, { ".reg-ppc-vmx", 544 }, + { ".reg-ppc-vsx", 256 }, { NULL, 0} }; @@ -741,6 +744,13 @@ static const struct regset ppc32_linux_vrregset = { NULL }; +static const struct regset ppc32_linux_vsxregset = { + &ppc32_linux_reg_offsets, + ppc_supply_vsxregset, + ppc_collect_vsxregset, + NULL +}; + const struct regset * ppc_linux_gregset (int wordsize) { @@ -769,6 +779,8 @@ ppc_linux_regset_from_core_section (struct gdbarch *core_arch, return &ppc32_linux_fpregset; if (strcmp (sect_name, ".reg-ppc-vmx") == 0) return &ppc32_linux_vrregset; + if (strcmp (sect_name, ".reg-ppc-vsx") == 0) + return &ppc32_linux_vsxregset; return NULL; } @@ -972,6 +984,7 @@ ppc_linux_core_read_description (struct gdbarch *gdbarch, bfd *abfd) { asection *altivec = bfd_get_section_by_name (abfd, ".reg-ppc-vmx"); + asection *vsx = bfd_get_section_by_name (abfd, ".reg-ppc-vsx"); asection *section = bfd_get_section_by_name (abfd, ".reg"); if (! section) return NULL; @@ -979,10 +992,20 @@ ppc_linux_core_read_description (struct gdbarch *gdbarch, switch (bfd_section_size (abfd, section)) { case 48 * 4: - return altivec? tdesc_powerpc_altivec32l : tdesc_powerpc_32l; + if (vsx) + return tdesc_powerpc_vsx32l; + else if (altivec) + return tdesc_powerpc_altivec32l; + else + return tdesc_powerpc_32l; case 48 * 8: - return altivec? tdesc_powerpc_altivec64l : tdesc_powerpc_64l; + if (vsx) + return tdesc_powerpc_vsx64l; + else if (altivec) + return tdesc_powerpc_altivec64l; + else + return tdesc_powerpc_64l; default: return NULL; @@ -1095,7 +1118,9 @@ _initialize_ppc_linux_tdep (void) /* Initialize the Linux target descriptions. */ initialize_tdesc_powerpc_32l (); initialize_tdesc_powerpc_altivec32l (); + initialize_tdesc_powerpc_vsx32l (); initialize_tdesc_powerpc_64l (); initialize_tdesc_powerpc_altivec64l (); + initialize_tdesc_powerpc_vsx64l (); initialize_tdesc_powerpc_e500l (); } diff --git a/gdb/ppc-linux-tdep.h b/gdb/ppc-linux-tdep.h index 0ac76d3..ccfb902 100644 --- a/gdb/ppc-linux-tdep.h +++ b/gdb/ppc-linux-tdep.h @@ -41,8 +41,10 @@ int ppc_linux_trap_reg_p (struct gdbarch *gdbarch); /* Linux target descriptions. */ extern struct target_desc *tdesc_powerpc_32l; extern struct target_desc *tdesc_powerpc_altivec32l; +extern struct target_desc *tdesc_powerpc_vsx32l; extern struct target_desc *tdesc_powerpc_e500l; extern struct target_desc *tdesc_powerpc_64l; extern struct target_desc *tdesc_powerpc_altivec64l; +extern struct target_desc *tdesc_powerpc_vsx64l; #endif /* PPC_LINUX_TDEP_H */ diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h index 766ddd6..01c3850 100644 --- a/gdb/ppc-tdep.h +++ b/gdb/ppc-tdep.h @@ -63,6 +63,7 @@ enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarc /* From rs6000-tdep.c... */ int altivec_register_p (struct gdbarch *gdbarch, int regno); +int vsx_register_p (struct gdbarch *gdbarch, int regno); int spe_register_p (struct gdbarch *gdbarch, int regno); /* Return non-zero if the architecture described by GDBARCH has @@ -73,6 +74,9 @@ int ppc_floating_point_unit_p (struct gdbarch *gdbarch); Altivec registers (vr0 --- vr31, vrsave and vscr). */ int ppc_altivec_support_p (struct gdbarch *gdbarch); +/* Return non-zero if the architecture described by GDBARCH has + VSX registers (vsr0 --- vsr63). */ +int vsx_support_p (struct gdbarch *gdbarch); int ppc_deal_with_atomic_sequence (struct frame_info *frame); @@ -133,6 +137,14 @@ extern void ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache, int regnum, const void *vrregs, size_t len); +/* Supply register REGNUM in the VSX register set REGSET + from the buffer specified by VSXREGS and LEN to register cache + REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ + +extern void ppc_supply_vsxregset (const struct regset *regset, + struct regcache *regcache, + int regnum, const void *vsxregs, size_t len); + /* Collect register REGNUM in the general-purpose register set REGSET. from register cache REGCACHE into the buffer specified by GREGS and LEN. If REGNUM is -1, do this for all registers in @@ -160,6 +172,15 @@ extern void ppc_collect_vrregset (const struct regset *regset, const struct regcache *regcache, int regnum, void *vrregs, size_t len); +/* Collect register REGNUM in the VSX register set + REGSET from register cache REGCACHE into the buffer specified by + VSXREGS and LEN. If REGNUM is -1, do this for all registers in + REGSET. */ + +extern void ppc_collect_vsxregset (const struct regset *regset, + const struct regcache *regcache, + int regnum, void *vsxregs, size_t len); + /* Private data that this module attaches to struct gdbarch. */ /* Vector ABI used by the inferior. */ @@ -199,6 +220,11 @@ struct gdbarch_tdep /* Multiplier-Quotient Register (older POWER architectures only). */ int ppc_mq_regnum; + /* POWER7 VSX registers. */ + int ppc_vsr0_regnum; /* First VSX register. */ + int ppc_vsr0_upper_regnum; /* First right most dword vsx register. */ + int ppc_efpr0_regnum; /* First Extended FP register. */ + /* Altivec registers. */ int ppc_vr0_regnum; /* First AltiVec register */ int ppc_vrsave_regnum; /* Last AltiVec register */ @@ -222,16 +248,20 @@ struct gdbarch_tdep /* ISA-specific types. */ struct type *ppc_builtin_type_vec64; + struct type *ppc_builtin_type_vec128; }; /* Constants for register set sizes. */ enum { - ppc_num_gprs = 32, /* 32 general-purpose registers */ - ppc_num_fprs = 32, /* 32 floating-point registers */ - ppc_num_srs = 16, /* 16 segment registers */ - ppc_num_vrs = 32 /* 32 Altivec vector registers */ + ppc_num_gprs = 32, /* 32 general-purpose registers. */ + ppc_num_fprs = 32, /* 32 floating-point registers. */ + ppc_num_srs = 16, /* 16 segment registers. */ + ppc_num_vrs = 32, /* 32 Altivec vector registers. */ + ppc_num_vshrs = 32, /* 32 doublewords (dword 1 of vs0~vs31). */ + ppc_num_vsrs = 64, /* 64 VSX vector registers. */ + ppc_num_efprs = 32 /* 32 Extended FP registers. */ }; @@ -257,6 +287,8 @@ enum { PPC_VR0_REGNUM = 106, PPC_VSCR_REGNUM = 138, PPC_VRSAVE_REGNUM = 139, + PPC_VSR0_UPPER_REGNUM = 140, + PPC_VSR31_UPPER_REGNUM = 171, PPC_NUM_REGS }; diff --git a/gdb/regformats/rs6000/powerpc-vsx32l.dat b/gdb/regformats/rs6000/powerpc-vsx32l.dat new file mode 100644 index 0000000..3fc1ef3 --- /dev/null +++ b/gdb/regformats/rs6000/powerpc-vsx32l.dat @@ -0,0 +1,143 @@ +# DO NOT EDIT: generated from rs6000/powerpc-vsx32l.xml +name:powerpc_vsx32l +xmltarget:powerpc-vsx32l.xml +expedite:r1,pc +32:r0 +32:r1 +32:r2 +32:r3 +32:r4 +32:r5 +32:r6 +32:r7 +32:r8 +32:r9 +32:r10 +32:r11 +32:r12 +32:r13 +32:r14 +32:r15 +32:r16 +32:r17 +32:r18 +32:r19 +32:r20 +32:r21 +32:r22 +32:r23 +32:r24 +32:r25 +32:r26 +32:r27 +32:r28 +32:r29 +32:r30 +32:r31 +64:f0 +64:f1 +64:f2 +64:f3 +64:f4 +64:f5 +64:f6 +64:f7 +64:f8 +64:f9 +64:f10 +64:f11 +64:f12 +64:f13 +64:f14 +64:f15 +64:f16 +64:f17 +64:f18 +64:f19 +64:f20 +64:f21 +64:f22 +64:f23 +64:f24 +64:f25 +64:f26 +64:f27 +64:f28 +64:f29 +64:f30 +64:f31 +32:pc +32:msr +32:cr +32:lr +32:ctr +32:xer +32:fpscr +32:orig_r3 +32:trap +128:vr0 +128:vr1 +128:vr2 +128:vr3 +128:vr4 +128:vr5 +128:vr6 +128:vr7 +128:vr8 +128:vr9 +128:vr10 +128:vr11 +128:vr12 +128:vr13 +128:vr14 +128:vr15 +128:vr16 +128:vr17 +128:vr18 +128:vr19 +128:vr20 +128:vr21 +128:vr22 +128:vr23 +128:vr24 +128:vr25 +128:vr26 +128:vr27 +128:vr28 +128:vr29 +128:vr30 +128:vr31 +32:vscr +32:vrsave +64:vs0h +64:vs1h +64:vs2h +64:vs3h +64:vs4h +64:vs5h +64:vs6h +64:vs7h +64:vs8h +64:vs9h +64:vs10h +64:vs11h +64:vs12h +64:vs13h +64:vs14h +64:vs15h +64:vs16h +64:vs17h +64:vs18h +64:vs19h +64:vs20h +64:vs21h +64:vs22h +64:vs23h +64:vs24h +64:vs25h +64:vs26h +64:vs27h +64:vs28h +64:vs29h +64:vs30h +64:vs31h diff --git a/gdb/regformats/rs6000/powerpc-vsx64l.dat b/gdb/regformats/rs6000/powerpc-vsx64l.dat new file mode 100644 index 0000000..af070f0 --- /dev/null +++ b/gdb/regformats/rs6000/powerpc-vsx64l.dat @@ -0,0 +1,143 @@ +# DO NOT EDIT: generated from rs6000/powerpc-vsx64l.xml +name:powerpc_vsx64l +xmltarget:powerpc-vsx64l.xml +expedite:r1,pc +64:r0 +64:r1 +64:r2 +64:r3 +64:r4 +64:r5 +64:r6 +64:r7 +64:r8 +64:r9 +64:r10 +64:r11 +64:r12 +64:r13 +64:r14 +64:r15 +64:r16 +64:r17 +64:r18 +64:r19 +64:r20 +64:r21 +64:r22 +64:r23 +64:r24 +64:r25 +64:r26 +64:r27 +64:r28 +64:r29 +64:r30 +64:r31 +64:f0 +64:f1 +64:f2 +64:f3 +64:f4 +64:f5 +64:f6 +64:f7 +64:f8 +64:f9 +64:f10 +64:f11 +64:f12 +64:f13 +64:f14 +64:f15 +64:f16 +64:f17 +64:f18 +64:f19 +64:f20 +64:f21 +64:f22 +64:f23 +64:f24 +64:f25 +64:f26 +64:f27 +64:f28 +64:f29 +64:f30 +64:f31 +64:pc +64:msr +32:cr +64:lr +64:ctr +32:xer +32:fpscr +64:orig_r3 +64:trap +128:vr0 +128:vr1 +128:vr2 +128:vr3 +128:vr4 +128:vr5 +128:vr6 +128:vr7 +128:vr8 +128:vr9 +128:vr10 +128:vr11 +128:vr12 +128:vr13 +128:vr14 +128:vr15 +128:vr16 +128:vr17 +128:vr18 +128:vr19 +128:vr20 +128:vr21 +128:vr22 +128:vr23 +128:vr24 +128:vr25 +128:vr26 +128:vr27 +128:vr28 +128:vr29 +128:vr30 +128:vr31 +32:vscr +32:vrsave +64:vs0h +64:vs1h +64:vs2h +64:vs3h +64:vs4h +64:vs5h +64:vs6h +64:vs7h +64:vs8h +64:vs9h +64:vs10h +64:vs11h +64:vs12h +64:vs13h +64:vs14h +64:vs15h +64:vs16h +64:vs17h +64:vs18h +64:vs19h +64:vs20h +64:vs21h +64:vs22h +64:vs23h +64:vs24h +64:vs25h +64:vs26h +64:vs27h +64:vs28h +64:vs29h +64:vs30h +64:vs31h diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c index fcf4355..f1d9799 100644 --- a/gdb/rs6000-tdep.c +++ b/gdb/rs6000-tdep.c @@ -63,6 +63,7 @@ #include "features/rs6000/powerpc-32.c" #include "features/rs6000/powerpc-altivec32.c" +#include "features/rs6000/powerpc-vsx32.c" #include "features/rs6000/powerpc-403.c" #include "features/rs6000/powerpc-403gc.c" #include "features/rs6000/powerpc-505.c" @@ -72,6 +73,7 @@ #include "features/rs6000/powerpc-604.c" #include "features/rs6000/powerpc-64.c" #include "features/rs6000/powerpc-altivec64.c" +#include "features/rs6000/powerpc-vsx64.c" #include "features/rs6000/powerpc-7400.c" #include "features/rs6000/powerpc-750.c" #include "features/rs6000/powerpc-860.c" @@ -88,6 +90,16 @@ && (regnum) >= (tdep)->ppc_dl0_regnum \ && (regnum) < (tdep)->ppc_dl0_regnum + 16) +/* Determine if regnum is a POWER7 VSX register. */ +#define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \ + && (regnum) >= (tdep)->ppc_vsr0_regnum \ + && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs) + +/* Determine if regnum is a POWER7 Extended FP register. */ +#define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \ + && (regnum) >= (tdep)->ppc_efpr0_regnum \ + && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_fprs) + /* The list of available "set powerpc ..." and "show powerpc ..." commands. */ static struct cmd_list_element *setpowerpccmdlist = NULL; @@ -133,6 +145,18 @@ struct rs6000_framedata }; +/* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */ +int +vsx_register_p (struct gdbarch *gdbarch, int regno) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + if (tdep->ppc_vsr0_regnum < 0) + return 0; + else + return (regno >= tdep->ppc_vsr0_upper_regnum && regno + <= tdep->ppc_vsr0_upper_regnum + 31); +} + /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ int altivec_register_p (struct gdbarch *gdbarch, int regno) @@ -188,6 +212,16 @@ ppc_floating_point_unit_p (struct gdbarch *gdbarch) } /* Return non-zero if the architecture described by GDBARCH has + VSX registers (vsr0 --- vsr63). */ +int +ppc_vsx_support_p (struct gdbarch *gdbarch) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + return tdep->ppc_vsr0_regnum >= 0; +} + +/* Return non-zero if the architecture described by GDBARCH has Altivec registers (vr0 --- vr31, vrsave and vscr). */ int ppc_altivec_support_p (struct gdbarch *gdbarch) @@ -539,6 +573,37 @@ ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); } +/* Supply register REGNUM in the VSX register set REGSET + from the buffer specified by VSXREGS and LEN to register cache + REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ + +void +ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache, + int regnum, const void *vsxregs, size_t len) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep; + + if (!ppc_vsx_support_p (gdbarch)) + return; + + tdep = gdbarch_tdep (gdbarch); + + if (regnum == -1) + { + int i; + + for (i = tdep->ppc_vsr0_upper_regnum; + i < tdep->ppc_vsr0_upper_regnum + 32; + i++) + ppc_supply_reg (regcache, i, vsxregs, 0, 8); + + return; + } + else + ppc_supply_reg (regcache, regnum, vsxregs, 0, 8); +} + /* Supply register REGNUM in the Altivec register set REGSET from the buffer specified by VRREGS and LEN to register cache REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ @@ -669,6 +734,40 @@ ppc_collect_fpregset (const struct regset *regset, regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); } +/* Collect register REGNUM in the VSX register set + REGSET from register cache REGCACHE into the buffer specified by + VSXREGS and LEN. If REGNUM is -1, do this for all registers in + REGSET. */ + +void +ppc_collect_vsxregset (const struct regset *regset, + const struct regcache *regcache, + int regnum, void *vsxregs, size_t len) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep; + + if (!ppc_vsx_support_p (gdbarch)) + return; + + tdep = gdbarch_tdep (gdbarch); + + if (regnum == -1) + { + int i; + + for (i = tdep->ppc_vsr0_upper_regnum; + i < tdep->ppc_vsr0_upper_regnum + 32; + i++) + ppc_collect_reg (regcache, i, vsxregs, 0, 8); + + return; + } + else + ppc_collect_reg (regcache, regnum, vsxregs, 0, 8); +} + + /* Collect register REGNUM in the Altivec register set REGSET from register cache REGCACHE into the buffer specified by VRREGS and LEN. If REGNUM is -1, do this for all registers in @@ -1964,6 +2063,47 @@ rs6000_builtin_type_vec64 (struct gdbarch *gdbarch) return tdep->ppc_builtin_type_vec64; } +/* Vector 128 type. */ + +static struct type * +rs6000_builtin_type_vec128 (struct gdbarch *gdbarch) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + if (!tdep->ppc_builtin_type_vec128) + { + /* The type we're building is this + + type = union __ppc_builtin_type_vec128 { + uint128_t uint128; + float v4_float[4]; + int32_t v4_int32[4]; + int16_t v8_int16[8]; + int8_t v16_int8[16]; + } + */ + + struct type *t; + + t = init_composite_type ("__ppc_builtin_type_vec128", TYPE_CODE_UNION); + append_composite_type_field (t, "uint128", builtin_type_uint128); + append_composite_type_field (t, "v4_float", + init_vector_type (builtin_type (gdbarch)->builtin_float, 4)); + append_composite_type_field (t, "v4_int32", + init_vector_type (builtin_type_int32, 4)); + append_composite_type_field (t, "v8_int16", + init_vector_type (builtin_type_int16, 8)); + append_composite_type_field (t, "v16_int8", + init_vector_type (builtin_type_int8, 16)); + + TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR; + TYPE_NAME (t) = "ppc_builtin_type_vec128"; + tdep->ppc_builtin_type_vec128 = t; + } + + return tdep->ppc_builtin_type_vec128; +} + /* Return the name of register number REGNO, or the empty string if it is an anonymous register. */ @@ -1980,6 +2120,12 @@ rs6000_register_name (struct gdbarch *gdbarch, int regno) && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) return ""; + /* Hide the upper halves of the vs0~vs31 registers. */ + if (tdep->ppc_vsr0_regnum >= 0 + && tdep->ppc_vsr0_upper_regnum <= regno + && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs) + return ""; + /* Check if the SPE pseudo registers are available. */ if (IS_SPE_PSEUDOREG (tdep, regno)) { @@ -2004,6 +2150,36 @@ rs6000_register_name (struct gdbarch *gdbarch, int regno) return dfp128_regnames[regno - tdep->ppc_dl0_regnum]; } + /* Check if this is a VSX pseudo-register. */ + if (IS_VSX_PSEUDOREG (tdep, regno)) + { + static const char *const vsx_regnames[] = { + "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7", + "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14", + "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21", + "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28", + "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35", + "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42", + "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49", + "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56", + "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63" + }; + return vsx_regnames[regno - tdep->ppc_vsr0_regnum]; + } + + /* Check if the this is a Extended FP pseudo-register. */ + if (IS_EFP_PSEUDOREG (tdep, regno)) + { + static const char *const efpr_regnames[] = { + "f32", "f33", "f34", "f35", "f36", "f37", "f38", + "f39", "f40", "f41", "f42", "f43", "f44", "f45", + "f46", "f47", "f48", "f49", "f50", "f51", + "f52", "f53", "f54", "f55", "f56", "f57", + "f58", "f59", "f60", "f61", "f62", "f63" + }; + return efpr_regnames[regno - tdep->ppc_efpr0_regnum]; + } + return tdesc_register_name (gdbarch, regno); } @@ -2017,14 +2193,22 @@ rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum) /* These are the only pseudo-registers we support. */ gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum) - || IS_DFP_PSEUDOREG (tdep, regnum)); + || IS_DFP_PSEUDOREG (tdep, regnum) + || IS_VSX_PSEUDOREG (tdep, regnum) + || IS_EFP_PSEUDOREG (tdep, regnum)); /* These are the e500 pseudo-registers. */ if (IS_SPE_PSEUDOREG (tdep, regnum)) return rs6000_builtin_type_vec64 (gdbarch); - else - /* Could only be the ppc decimal128 pseudo-registers. */ + else if (IS_DFP_PSEUDOREG (tdep, regnum)) + /* PPC decimal128 pseudo-registers. */ return builtin_type (gdbarch)->builtin_declong; + else if (IS_VSX_PSEUDOREG (tdep, regnum)) + /* POWER7 VSX pseudo-registers. */ + return rs6000_builtin_type_vec128 (gdbarch); + else + /* POWER7 Extended FP pseudo-registers. */ + return builtin_type (gdbarch)->builtin_double; } /* Is REGNUM a member of REGGROUP? */ @@ -2036,13 +2220,15 @@ rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, /* These are the only pseudo-registers we support. */ gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum) - || IS_DFP_PSEUDOREG (tdep, regnum)); + || IS_DFP_PSEUDOREG (tdep, regnum) + || IS_VSX_PSEUDOREG (tdep, regnum) + || IS_EFP_PSEUDOREG (tdep, regnum)); - /* These are the e500 pseudo-registers. */ - if (IS_SPE_PSEUDOREG (tdep, regnum)) + /* These are the e500 pseudo-registers or the POWER7 VSX registers. */ + if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum)) return group == all_reggroup || group == vector_reggroup; else - /* Could only be the ppc decimal128 pseudo-registers. */ + /* PPC decimal128 or Extended FP pseudo-registers. */ return group == all_reggroup || group == float_reggroup; } @@ -2156,10 +2342,9 @@ e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, regcache, reg_nr, (gdb_byte *) buffer); } -/* Read method for PPC pseudo-registers. Currently this is handling the - 16 decimal128 registers that map into 16 pairs of FP registers. */ +/* Read method for DFP pseudo-registers. */ static void -ppc_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, +dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, int reg_nr, gdb_byte *buffer) { struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); @@ -2182,10 +2367,9 @@ ppc_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, } } -/* Write method for PPC pseudo-registers. Currently this is handling the - 16 decimal128 registers that map into 16 pairs of FP registers. */ +/* Write method for DFP pseudo-registers. */ static void -ppc_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, +dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, int reg_nr, const gdb_byte *buffer) { struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); @@ -2209,6 +2393,92 @@ ppc_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, } } +/* Read method for POWER7 VSX pseudo-registers. */ +static void +vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, + int reg_nr, gdb_byte *buffer) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int reg_index = reg_nr - tdep->ppc_vsr0_regnum; + + /* Read the portion that overlaps the VMX registers. */ + if (reg_index > 31) + regcache_raw_read (regcache, tdep->ppc_vr0_regnum + + reg_index - 32, buffer); + else + /* Read the portion that overlaps the FPR registers. */ + if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) + { + regcache_raw_read (regcache, tdep->ppc_fp0_regnum + + reg_index, buffer); + regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum + + reg_index, buffer + 8); + } + else + { + regcache_raw_read (regcache, tdep->ppc_fp0_regnum + + reg_index, buffer + 8); + regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum + + reg_index, buffer); + } +} + +/* Write method for POWER7 VSX pseudo-registers. */ +static void +vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, + int reg_nr, const gdb_byte *buffer) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int reg_index = reg_nr - tdep->ppc_vsr0_regnum; + + /* Write the portion that overlaps the VMX registers. */ + if (reg_index > 31) + regcache_raw_write (regcache, tdep->ppc_vr0_regnum + + reg_index - 32, buffer); + else + /* Write the portion that overlaps the FPR registers. */ + if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) + { + regcache_raw_write (regcache, tdep->ppc_fp0_regnum + + reg_index, buffer); + regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum + + reg_index, buffer + 8); + } + else + { + regcache_raw_write (regcache, tdep->ppc_fp0_regnum + + reg_index, buffer + 8); + regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum + + reg_index, buffer); + } +} + +/* Read method for POWER7 Extended FP pseudo-registers. */ +static void +efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, + int reg_nr, gdb_byte *buffer) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int reg_index = reg_nr - tdep->ppc_efpr0_regnum; + + /* Read the portion that overlaps the VMX registers. */ + regcache_raw_read (regcache, tdep->ppc_vr0_regnum + + reg_index, buffer); +} + +/* Write method for POWER7 Extended FP pseudo-registers. */ +static void +efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, + int reg_nr, const gdb_byte *buffer) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int reg_index = reg_nr - tdep->ppc_efpr0_regnum; + + /* Write the portion that overlaps the VMX registers. */ + regcache_raw_write (regcache, tdep->ppc_vr0_regnum + + reg_index, buffer); +} + static void rs6000_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, int reg_nr, gdb_byte *buffer) @@ -2221,7 +2491,11 @@ rs6000_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, if (IS_SPE_PSEUDOREG (tdep, reg_nr)) e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); else if (IS_DFP_PSEUDOREG (tdep, reg_nr)) - ppc_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); + dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); + else if (IS_VSX_PSEUDOREG (tdep, reg_nr)) + vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); + else if (IS_EFP_PSEUDOREG (tdep, reg_nr)) + efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); else internal_error (__FILE__, __LINE__, _("rs6000_pseudo_register_read: " @@ -2242,7 +2516,11 @@ rs6000_pseudo_register_write (struct gdbarch *gdbarch, if (IS_SPE_PSEUDOREG (tdep, reg_nr)) e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); else if (IS_DFP_PSEUDOREG (tdep, reg_nr)) - ppc_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); + dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); + else if (IS_VSX_PSEUDOREG (tdep, reg_nr)) + vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); + else if (IS_EFP_PSEUDOREG (tdep, reg_nr)) + efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); else internal_error (__FILE__, __LINE__, _("rs6000_pseudo_register_write: " @@ -2825,11 +3103,13 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) enum auto_boolean soft_float_flag = powerpc_soft_float_global; int soft_float; enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global; - int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0; + int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0, + have_vsx = 0; int tdesc_wordsize = -1; const struct target_desc *tdesc = info.target_desc; struct tdesc_arch_data *tdesc_data = NULL; int num_pseudoregs = 0; + int cur_reg; from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; @@ -3024,6 +3304,38 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) else have_altivec = 0; + /* Check for POWER7 VSX registers support. */ + feature = tdesc_find_feature (tdesc, + "org.gnu.gdb.power.vsx"); + + if (feature != NULL) + { + static const char *const vsx_regs[] = { + "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h", + "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h", + "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h", + "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h", + "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h", + "vs30h", "vs31h" + }; + + valid_p = 1; + + for (i = 0; i < ppc_num_vshrs; i++) + valid_p &= tdesc_numbered_register (feature, tdesc_data, + PPC_VSR0_UPPER_REGNUM + i, + vsx_regs[i]); + if (!valid_p) + { + tdesc_data_cleanup (tdesc_data); + return NULL; + } + + have_vsx = 1; + } + else + have_vsx = 0; + /* On machines supporting the SPE APU, the general-purpose registers are 64 bits long. There are SIMD vector instructions to treat them as pairs of floats, but the rest of the instruction set treats them @@ -3207,6 +3519,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1; tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1; + tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1; tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1; tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1; tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1; @@ -3235,7 +3548,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) else tdep->lr_frame_offset = 4; - if (have_spe || have_dfp) + if (have_spe || have_dfp || have_vsx) { set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read); set_gdbarch_pseudo_register_write (gdbarch, rs6000_pseudo_register_write); @@ -3255,6 +3568,9 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) num_pseudoregs += 32; if (have_dfp) num_pseudoregs += 16; + if (have_vsx) + /* Include both VSX and Extended FP registers. */ + num_pseudoregs += 96; set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs); @@ -3351,15 +3667,34 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) halves anonymous. */ set_gdbarch_register_name (gdbarch, rs6000_register_name); - /* Recording the numbering of pseudo registers. */ - tdep->ppc_ev0_regnum = have_spe ? gdbarch_num_regs (gdbarch) : -1; + /* Choose register numbers for all supported pseudo-registers. */ + tdep->ppc_ev0_regnum = -1; + tdep->ppc_dl0_regnum = -1; + tdep->ppc_vsr0_regnum = -1; + tdep->ppc_efpr0_regnum = -1; - /* Set the register number for _Decimal128 pseudo-registers. */ - tdep->ppc_dl0_regnum = have_dfp? gdbarch_num_regs (gdbarch) : -1; + cur_reg = gdbarch_num_regs (gdbarch); + + if (have_spe) + { + tdep->ppc_ev0_regnum = cur_reg; + cur_reg += 32; + } + if (have_dfp) + { + tdep->ppc_dl0_regnum = cur_reg; + cur_reg += 16; + } + if (have_vsx) + { + tdep->ppc_vsr0_regnum = cur_reg; + cur_reg += 64; + tdep->ppc_efpr0_regnum = cur_reg; + cur_reg += 32; + } - if (have_dfp && have_spe) - /* Put the _Decimal128 pseudo-registers after the SPE registers. */ - tdep->ppc_dl0_regnum += 32; + gdb_assert (gdbarch_num_regs (gdbarch) + + gdbarch_num_pseudo_regs (gdbarch) == cur_reg); /* Setup displaced stepping. */ set_gdbarch_displaced_step_copy_insn (gdbarch, @@ -3454,6 +3789,7 @@ _initialize_rs6000_tdep (void) /* Initialize the standard target descriptions. */ initialize_tdesc_powerpc_32 (); initialize_tdesc_powerpc_altivec32 (); + initialize_tdesc_powerpc_vsx32 (); initialize_tdesc_powerpc_403 (); initialize_tdesc_powerpc_403gc (); initialize_tdesc_powerpc_505 (); @@ -3463,6 +3799,7 @@ _initialize_rs6000_tdep (void) initialize_tdesc_powerpc_604 (); initialize_tdesc_powerpc_64 (); initialize_tdesc_powerpc_altivec64 (); + initialize_tdesc_powerpc_vsx64 (); initialize_tdesc_powerpc_7400 (); initialize_tdesc_powerpc_750 (); initialize_tdesc_powerpc_860 (); diff --git a/gdb/testsuite/ChangeLog b/gdb/testsuite/ChangeLog index 577d0eb..92dd07a 100644 --- a/gdb/testsuite/ChangeLog +++ b/gdb/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2008-08-15 Luis Machado <luisgpm@br.ibm.com> + + * testsuite/gdb.arch/vsx-regs.c: New source file. + * testsuite/gdb.arch/vsx-regs.exp: New testcase. + * testsuite/lib/gdb.exp (skip_vsx_tests): New function. + 2008-08-14 Tom Tromey <tromey@redhat.com> * gdb.base/macscp.exp: Add regression test for "macro define" or diff --git a/gdb/testsuite/gdb.arch/vsx-regs.c b/gdb/testsuite/gdb.arch/vsx-regs.c new file mode 100644 index 0000000..24a6fa6 --- /dev/null +++ b/gdb/testsuite/gdb.arch/vsx-regs.c @@ -0,0 +1,41 @@ +#include <altivec.h> +#include <stdio.h> + +vector unsigned int +vector_fun (vector unsigned int a, vector unsigned int b) +{ + vector unsigned int c; + a = ((vector unsigned int) vec_splat_u8(2)); + b = ((vector unsigned int) vec_splat_u8(3)); + + c = vec_add (a, b); + return c; +} + +int +main () +{ + vector unsigned int y; + vector unsigned int x; + vector unsigned int z; + int a; + + /* This line may look unnecessary but we do need it, because we want to + have a line to do a next over (so that gdb refetches the registers) + and we don't want the code to change any vector registers. + The splat operations below modify the VRs,i + so we don't want to execute them yet. */ + a = 9; + x = ((vector unsigned int) vec_splat_u8 (-2)); + y = ((vector unsigned int) vec_splat_u8 (1)); + + z = vector_fun (x, y); + x = vec_sld (x,y,2); + + x = vec_add (x, ((vector unsigned int){5,6,7,8})); + z = (vector unsigned int) vec_splat_u8 ( -2); + y = vec_add (x, z); + z = (vector unsigned int) vec_cmpeq (x,y); + + return 0; +} diff --git a/gdb/testsuite/gdb.arch/vsx-regs.exp b/gdb/testsuite/gdb.arch/vsx-regs.exp new file mode 100644 index 0000000..006eb6d --- /dev/null +++ b/gdb/testsuite/gdb.arch/vsx-regs.exp @@ -0,0 +1,193 @@ +# Copyright (C) 2008 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +# Please email any bugs, comments, and/or additions to this file to: +# bug-gdb@prep.ai.mit.edu +# + +# Tests for Powerpc AltiVec register setting and fetching + +if $tracelevel then { + strace $tracelevel +} + +# +# Test the use of VSX registers, for Powerpc. +# + +set prms_id 0 +set bug_id 0 + +if {![istarget "powerpc*"] || [skip_vsx_tests]} then { + verbose "Skipping vsx register tests." + verbose -log "Skipping vsx register tests." + return +} + +set testfile "vsx-regs" +set binfile ${objdir}/${subdir}/${testfile} +set srcfile ${testfile}.c + +set compile_flags {debug nowarnings quiet} +if [get_compiler_info $binfile] { + warning "get_compiler failed" + return -1 +} + +if [test_compiler_info gcc*] { + set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec" +} elseif [test_compiler_info xlc*] { + set compile_flags "$compile_flags additional_flags=-qaltivec" +} else { + warning "unknown compiler" + return -1 +} + +if { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } { + untested vsx-regs.exp + return -1 +} + +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +# Run to `main' where we begin our tests. + +if ![runto_main] then { + gdb_suppress_tests +} + +# Data sets used throughout the test + +set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.." + +set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." + +set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." + +set float_register ".raw 0xdeadbeefdeadbeef." + +# First run the F0~F31/VS0~VS31 tests + +# 1: Set F0~F31 registers and check if it reflects on VS0~VS31. +for {set i 0} {$i < 32} {incr i 1} { + send_gdb "set \$f$i = 1\.3" +} + +for {set i 0} {$i < 32} {incr i 1} { + gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)" +} + +# 2: Set VS0~VS31 registers and check if it reflects on F0~F31. +for {set i 0} {$i < 32} {incr i 1} { + for {set j 0} {$j < 4} {incr j 1} { + send_gdb "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef" + } +} + +for {set i 0} {$i < 32} {incr i 1} { + gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i" +} + +for {set i 0} {$i < 32} {incr i 1} { + gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)" +} + +# Now run the VR0~VR31/VS32~VS63 tests + +# 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63. +for {set i 0} {$i < 32} {incr i 1} { + for {set j 0} {$j < 4} {incr j 1} { + send_gdb "set \$vr$i.v4_int32\[$j\] = 1" + } +} + +for {set i 32} {$i < 64} {incr i 1} { + gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i" +} +# 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31. +for {set i 32} {$i < 64} {incr i 1} { + for {set j 0} {$j < 4} {incr j 1} { + send_gdb "set \$vs$i.v4_int32\[$j\] = 1" + } +} + +for {set i 0} {$i < 32} {incr i 1} { + gdb_test "info reg vr$i" "vr$i.*$vector_register3" "info reg vr$i" +} + +set escapedfilename [string_to_regexp ${objdir}/${subdir}/vsx-core.test] + +set core_supported 0 + +gdb_test_multiple "gcore ${objdir}/${subdir}/vsx-core.test" \ + "Save a VSX-enabled corefile" \ +{ + -re "Saved corefile ${escapedfilename}\[\r\n\]+$gdb_prompt $" { + pass "Save a VSX-enabled corefile" + global core_supported + set core_supported 1 + } + -re "Can't create a corefile\[\r\n\]+$gdb_prompt $" { + unsupported "Save a VSX-enabled corefile" + global core_supported + set core_supported 0 + } +} + +if {!$core_supported} { + return -1 +} + +gdb_exit +gdb_start +gdb_reinitialize_dir $srcdir/$subdir +gdb_load ${binfile} + +gdb_test_multiple "core ${objdir}/${subdir}/vsx-core.test" \ + "re-load generated corefile" \ +{ + -re ".* is not a core dump:.*$gdb_prompt $" { + fail "re-load generated corefile (bad file format)" + # No use proceeding from here. + return; + } + -re ".*: No such file or directory.*$gdb_prompt $" { + fail "re-load generated corefile (file not found)" + # No use proceeding from here. + return; + } + -re ".*Couldn't find .* registers in core file.*$gdb_prompt $" { + fail "re-load generated corefile (incomplete note section)" + } + -re "Core was generated by .*$gdb_prompt $" { + pass "re-load generated corefile" + } + -re ".*$gdb_prompt $" { + fail "re-load generated corefile" + } + timeout { + fail "re-load generated corefile (timeout)" + } +} + +for {set i 0} {$i < 32} {incr i 1} { + gdb_test "info reg vs$i" "vs$i.*$vector_register2" "Restore vs$i from core file" +} + +for {set i 32} {$i < 64} {incr i 1} { + gdb_test "info reg vs$i" "vs$i.*$vector_register3" "Restore vs$i from core file" +} diff --git a/gdb/testsuite/lib/gdb.exp b/gdb/testsuite/lib/gdb.exp index 72081a8..3761d7a 100644 --- a/gdb/testsuite/lib/gdb.exp +++ b/gdb/testsuite/lib/gdb.exp @@ -1349,6 +1349,92 @@ proc skip_altivec_tests {} { return $skip_vmx_tests_saved } +# Run a test on the target to see if it supports vmx hardware. Return 0 if so, +# 1 if it does not. Based on 'check_vmx_hw_available' from the GCC testsuite. + +proc skip_vsx_tests {} { + global skip_vsx_tests_saved + global srcdir subdir gdb_prompt + + # Use the cached value, if it exists. + set me "skip_vsx_tests" + if [info exists skip_vsx_tests_saved] { + verbose "$me: returning saved $skip_vsx_tests_saved" 2 + return $skip_vsx_tests_saved + } + + # Some simulators are known to not support Altivec instructions, so + # they won't support VSX instructions as well. + if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] } { + verbose "$me: target known to not support VSX, returning 1" 2 + return [set skip_vsx_tests_saved 1] + } + + # Make sure we have a compiler that understands altivec. + set compile_flags {debug nowarnings quiet} + if [get_compiler_info not-used] { + warning "Could not get compiler info" + return 1 + } + if [test_compiler_info gcc*] { + set compile_flags "$compile_flags additional_flags=-mvsx" + } elseif [test_compiler_info xlc*] { + set compile_flags "$compile_flags additional_flags=-qvsx" + } else { + verbose "Could not compile with vsx support, returning 1" 2 + return 1 + } + + set src vsx[pid].c + set exe vsx[pid].x + + set f [open $src "w"] + puts $f "int main() {" + puts $f "#ifdef __MACH__" + puts $f " asm volatile (\"lxvd2x v0,v0,v0\");" + puts $f "#else" + puts $f " asm volatile (\"lxvd2x 0,0,0\");" + puts $f "#endif" + puts $f " return 0; }" + close $f + + verbose "$me: compiling testfile $src" 2 + set lines [gdb_compile $src $exe executable $compile_flags] + file delete $src + + if ![string match "" $lines] then { + verbose "$me: testfile compilation failed, returning 1" 2 + return [set skip_vsx_tests_saved 1] + } + + # No error message, compilation succeeded so now run it via gdb. + + gdb_exit + gdb_start + gdb_reinitialize_dir $srcdir/$subdir + gdb_load "$exe" + gdb_run_cmd + gdb_expect { + -re ".*Illegal instruction.*${gdb_prompt} $" { + verbose -log "\n$me VSX hardware not detected" + set skip_vsx_tests_saved 1 + } + -re ".*Program exited normally.*${gdb_prompt} $" { + verbose -log "\n$me: VSX hardware detected" + set skip_vsx_tests_saved 0 + } + default { + warning "\n$me: default case taken" + set skip_vsx_tests_saved 1 + } + } + gdb_exit + remote_file build delete $exe + + verbose "$me: returning $skip_vsx_tests_saved" 2 + return $skip_vsx_tests_saved +} + # Skip all the tests in the file if you are not on an hppa running # hpux target. |