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authorJoseph Myers <joseph@codesourcery.com>2008-06-12 12:44:01 +0000
committerJoseph Myers <joseph@codesourcery.com>2008-06-12 12:44:01 +0000
commit3c9a78e063e11129d5684ddc2994f71c050b46ed (patch)
tree989cbadc57c1b869684718c6f30934785e550706
parentb922d5904f4a0ac69d5abfc8e24826b17012f334 (diff)
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* common.h: Update e_machine table.
-rw-r--r--include/elf/ChangeLog4
-rw-r--r--include/elf/common.h54
2 files changed, 56 insertions, 2 deletions
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index f003a83..507fd72 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,7 @@
+2008-06-12 Joseph Myers <joseph@codesourcery.com>
+
+ * common.h: Update e_machine table.
+
2008-06-09 Takashi Yoshii <yoshii.takashi@renesas.com>
* sh.h (EF_SH_BFD_TABLE): Set bfd_mach_sh for EF_SH_UNKNOWN.
diff --git a/include/elf/common.h b/include/elf/common.h
index c3d7d01..53d57ac 100644
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -148,7 +148,7 @@
#define EM_ST100 60 /* STMicroelectronics ST100 processor */
#define EM_TINYJ 61 /* Advanced Logic Corp. TinyJ embedded processor */
#define EM_X86_64 62 /* Advanced Micro Devices X86-64 processor */
-
+#define EM_PDSP 63 /* Sony DSP Processor */
#define EM_PDP10 64 /* Digital Equipment Corp. PDP-10 */
#define EM_PDP11 65 /* Digital Equipment Corp. PDP-11 */
#define EM_FX66 66 /* Siemens FX66 microcontroller */
@@ -180,14 +180,61 @@
#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */
#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */
#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */
+#define EM_VIDEOCORE 95 /* Alphamosaic VideoCore processor */
+#define EM_TMM_GPP 96 /* Thompson Multimedia General Purpose Processor */
+#define EM_NS32K 97 /* National Semiconductor 32000 series */
+#define EM_TPC 98 /* Tenor Network TPC processor */
+#define EM_SNP1K 99 /* Trebia SNP 1000 processor */
+#define EM_ST200 100 /* STMicroelectronics ST200 microcontroller */
#define EM_IP2K 101 /* Ubicom IP2022 micro controller */
+#define EM_MAX 102 /* MAX Processor */
#define EM_CR 103 /* National Semiconductor CompactRISC */
+#define EM_F2MC16 104 /* Fujitsu F2MC16 */
#define EM_MSP430 105 /* TI msp430 micro controller */
#define EM_BLACKFIN 106 /* ADI Blackfin */
+#define EM_SE_C33 107 /* S1C33 Family of Seiko Epson processors */
+#define EM_SEP 108 /* Sharp embedded microprocessor */
+#define EM_ARCA 109 /* Arca RISC Microprocessor */
+#define EM_UNICORE 110 /* Microprocessor series from PKU-Unity Ltd. and MPRC of Peking University */
+#define EM_EXCESS 111 /* eXcess: 16/32/64-bit configurable embedded CPU */
+#define EM_DXP 112 /* Icera Semiconductor Inc. Deep Execution Processor */
#define EM_ALTERA_NIOS2 113 /* Altera Nios II soft-core processor */
#define EM_CRX 114 /* National Semiconductor CRX */
-#define EM_CR16 115 /* National Semiconductor CompactRISC - CR16 */
+#define EM_XGATE 115 /* Motorola XGATE embedded processor */
+#define EM_C166 116 /* Infineon C16x/XC16x processor */
+#define EM_M16C 117 /* Renesas M16C series microprocessors */
+#define EM_DSPIC30F 118 /* Microchip Technology dsPIC30F Digital Signal Controller */
+#define EM_CE 119 /* Freescale Communication Engine RISC core */
+#define EM_M32C_NEW 120 /* Renesas M32C series microprocessors */
+
+#define EM_TSK3000 131 /* Altium TSK3000 core */
+#define EM_RS08 132 /* Freescale RS08 embedded processor */
+
+#define EM_ECOG2 134 /* Cyan Technology eCOG2 microprocessor */
#define EM_SCORE 135 /* Sunplus Score */
+#define EM_DSP24 136 /* New Japan Radio (NJR) 24-bit DSP Processor */
+#define EM_VIDEOCORE3 137 /* Broadcom VideoCore III processor */
+#define EM_LATTICEMICO32 138 /* RISC processor for Lattice FPGA architecture */
+#define EM_SE_C17 139 /* Seiko Epson C17 family */
+
+#define EM_MMDSP_PLUS 160 /* STMicroelectronics 64bit VLIW Data Signal Processor */
+#define EM_CYPRESS_M8C 161 /* Cypress M8C microprocessor */
+#define EM_R32C 162 /* Renesas R32C series microprocessors */
+#define EM_TRIMEDIA 163 /* NXP Semiconductors TriMedia architecture family */
+#define EM_QDSP6 164 /* QUALCOMM DSP6 Processor */
+#define EM_8051 165 /* Intel 8051 and variants */
+#define EM_STXP7X 166 /* STMicroelectronics STxP7x family */
+#define EM_NDS32 167 /* Andes Technology compact code size embedded RISC processor family */
+#define EM_ECOG1 168 /* Cyan Technology eCOG1X family */
+#define EM_ECOG1X 168 /* Cyan Technology eCOG1X family */
+#define EM_MAXQ30 169 /* Dallas Semiconductor MAXQ30 Core Micro-controllers */
+#define EM_XIMO16 170 /* New Japan Radio (NJR) 16-bit DSP Processor */
+#define EM_MANIK 171 /* M2000 Reconfigurable RISC Microprocessor */
+#define EM_CRAYNV2 172 /* Cray Inc. NV2 vector architecture */
+#define EM_RX 173 /* Renesas RX family */
+#define EM_METAG 174 /* Imagination Technologies META processor architecture */
+#define EM_MCST_ELBRUS 175 /* MCST Elbrus general purpose hardware architecture */
+#define EM_ECOG16 176 /* Cyan Technology eCOG16 family */
/* If it is necessary to assign new unofficial EM_* values, please pick large
random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision
@@ -211,6 +258,9 @@
/* picoJava */
#define EM_PJ_OLD 99
+/* National Semiconductor CompactRISC - CR16 */
+#define EM_CR16 115
+
/* AVR magic number. Written in the absense of an ABI. */
#define EM_AVR_OLD 0x1057