gas/

* config/tc-mips.c (mips_set_options): Add ase_mcu. (mips_opts): Initialise ase_mcu to -1. (ISA_SUPPORTS_MCU_ASE): New macro. (MIPS_CPU_ASE_MCU): Likewise. (is_opcode_valid): Handle MCU. (macro_build, macro): Likewise. (validate_mips_insn, validate_micromips_insn): Likewise. (mips_ip): Likewise. (options): Add OPTION_MCU and OPTION_NO_MCU. (md_longopts): Add mmcu and mno-mcu. (md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU. (mips_after_parse_args): Handle MCU. (s_mipsset): Likewise. (md_show_usage): Handle MCU options. * doc/as.texinfo: Document -mmcu and -mno-mcu options. * doc/c-mips.texi: Likewise, and document ".set mcu" and ".set nomcu" directives. gas/testsuite/ * gas/mips/micromips@mcu.d: New test. * gas/mips/mcu.d: Likewise. * gas/mips/mcu.s: New test source. * gas/mips/mips.exp: Run the new tests. include/opcode/ * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. (INSN_ASE_MASK): Add the MCU bit. (INSN_MCU): New macro. (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values. (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros. opcodes/ * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2" and "mips64r2". (print_insn_args, print_insn_micromips): Handle MCU. * micromips-opc.c (MC): New macro. (micromips_opcodes): Add "aclr", "aset" and "iret". * mips-opc.c (MC): New macro. (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
author: Maciej W. Rozycki <macro@linux-mips.org> 2011-08-09 15:20:03 +0000
committer: Maciej W. Rozycki <macro@linux-mips.org> 2011-08-09 15:20:03 +0000
commit: dec0624dcd4590d55fad203497fcdcef4ce292e3 (patch)
tree: 0b51906dbdefe2193c68282fd68a1652b1f998f4
parent: 2b0c8b40edb06c073ce8bb358239cc1a5c6653a5 (diff)
download: gdb-dec0624dcd4590d55fad203497fcdcef4ce292e3.zip
gdb-dec0624dcd4590d55fad203497fcdcef4ce292e3.tar.gz
gdb-dec0624dcd4590d55fad203497fcdcef4ce292e3.tar.bz2
15 files changed, 532 insertions, 13 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index c6c5ee1..c2304df 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,25 @@
+2011-08-09  Chao-ying Fu  <fu@mips.com>
+            Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* config/tc-mips.c (mips_set_options): Add ase_mcu.
+	(mips_opts): Initialise ase_mcu to -1.
+	(ISA_SUPPORTS_MCU_ASE): New macro.
+	(MIPS_CPU_ASE_MCU): Likewise.
+	(is_opcode_valid): Handle MCU.
+	(macro_build, macro): Likewise.
+	(validate_mips_insn, validate_micromips_insn): Likewise.
+	(mips_ip): Likewise.
+	(options): Add OPTION_MCU and OPTION_NO_MCU.
+	(md_longopts): Add mmcu and mno-mcu.
+	(md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU.
+	(mips_after_parse_args): Handle MCU.
+	(s_mipsset): Likewise.
+	(md_show_usage): Handle MCU options.
+
+	* doc/as.texinfo: Document -mmcu and -mno-mcu options.
+	* doc/c-mips.texi: Likewise, and document ".set mcu" and
+	".set nomcu" directives.
+
 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 
 	* config/tc-mips.c (gpr_mod_mask): Remove INSN2_MOD_GPR_MB,
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 08c1c02..c9b653c 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -218,6 +218,7 @@ struct mips_set_options
   int ase_dsp;
   int ase_dspr2;
   int ase_mt;
+  int ase_mcu;
   /* Whether we are assembling for the mips16 processor.  0 if we are
      not, 1 if we are, and -1 if the value has not been initialized.
      Changed by `.set mips16' and `.set nomips16', and the -mips16 and
@@ -292,8 +293,8 @@ static struct mips_set_options mips_opts =
 {
   /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
   /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
-  /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, /* at */ ATREG,
-  /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
+  /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
+  /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
   /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
   /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
 };
@@ -368,6 +369,9 @@ static int file_ase_mt;
 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2		\
 			     || mips_opts.isa == ISA_MIPS64R2)
 
+#define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2		\
+			      || mips_opts.isa == ISA_MIPS64R2)
+
 /* The argument of the -march= flag.  The architecture we are assembling.  */
 static int file_mips_arch = CPU_UNKNOWN;
 static const char *mips_arch_string;
@@ -1388,6 +1392,7 @@ struct mips_cpu_info
 #define MIPS_CPU_ASE_MIPS3D	0x0010	/* CPU implements MIPS-3D ASE */
 #define MIPS_CPU_ASE_MDMX	0x0020	/* CPU implements MDMX ASE */
 #define MIPS_CPU_ASE_DSPR2	0x0040	/* CPU implements DSP R2 ASE */
+#define MIPS_CPU_ASE_MCU	0x0080	/* CPU implements MCU ASE */
 
 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
@@ -2203,6 +2208,8 @@ is_opcode_valid (const struct mips_opcode *mo)
     isa |= INSN_MIPS3D;
   if (mips_opts.ase_smartmips)
     isa |= INSN_SMARTMIPS;
+  if (mips_opts.ase_mcu)
+    isa |= INSN_MCU;
 
   /* Don't accept instructions based on the ISA if the CPU does not implement
      all the coprocessor insns. */
@@ -5044,9 +5051,14 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 	  INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
 	  continue;
 
+	case '\\':
+	  INSERT_OPERAND (mips_opts.micromips,
+			  3BITPOS, insn, va_arg (args, unsigned int));
+	  continue;
+
 	case '~':
-	  gas_assert (mips_opts.micromips);
-	  INSERT_OPERAND (1, OFFSET12, insn, va_arg (args, unsigned long));
+	  INSERT_OPERAND (mips_opts.micromips,
+			  OFFSET12, insn, va_arg (args, unsigned long));
 	  continue;
 
 	case 'N':
@@ -7881,6 +7893,22 @@ macro (struct mips_cl_insn *ip)
 
       break;
 
+    case M_ACLR_AB:
+      ab = 1;
+    case M_ACLR_OB:
+      s = "aclr";
+      treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
+      fmt = "\\,~(b)";
+      off12 = 1;
+      goto ld_st;
+    case M_ASET_AB:
+      ab = 1;
+    case M_ASET_OB:
+      s = "aset";
+      treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
+      fmt = "\\,~(b)";
+      off12 = 1;
+      goto ld_st;
     case M_LB_AB:
       ab = 1;
       s = "lb";
@@ -10270,6 +10298,8 @@ validate_mips_insn (const struct mips_opcode *opc)
       case '$': USE_BITS (OP_MASK_MT_H,		OP_SH_MT_H);	break;
       case '*': USE_BITS (OP_MASK_MTACC_T,	OP_SH_MTACC_T);	break;
       case '&': USE_BITS (OP_MASK_MTACC_D,	OP_SH_MTACC_D);	break;
+      case '\\': USE_BITS (OP_MASK_3BITPOS,	OP_SH_3BITPOS);	break;
+      case '~': USE_BITS (OP_MASK_OFFSET12,	OP_SH_OFFSET12); break;
       case 'g': USE_BITS (OP_MASK_RD,		OP_SH_RD);	break;
       default:
 	as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
@@ -10427,6 +10457,7 @@ validate_micromips_insn (const struct mips_opcode *opc)
       case 'S': USE_BITS (FS);		break;
       case 'T': USE_BITS (FT);		break;
       case 'V': USE_BITS (FS);		break;
+      case '\\': USE_BITS (3BITPOS);	break;
       case 'a': USE_BITS (TARGET);	break;
       case 'b': USE_BITS (RS);		break;
       case 'c': USE_BITS (CODE);	break;
@@ -10933,6 +10964,25 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 		as_bad (_("Invalid dsp/smartmips acc register"));
 	      break;
 
+	    case '\\':		/* 3-bit bit position.  */
+	      {
+		unsigned long mask = (!mips_opts.micromips
+				      ? OP_MASK_3BITPOS
+				      : MICROMIPSOP_MASK_3BITPOS);
+
+		my_getExpression (&imm_expr, s);
+		check_absolute_expr (ip, &imm_expr);
+		if ((unsigned long) imm_expr.X_add_number > mask)
+		  as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
+			   ip->insn_mo->name,
+			   mask, (unsigned long) imm_expr.X_add_number);
+		INSERT_OPERAND (mips_opts.micromips,
+				3BITPOS, *ip, imm_expr.X_add_number);
+		imm_expr.X_op = O_absent;
+		s = expr_end;
+	      }
+	      continue;
+
 	    case ',':
 	      ++argnum;
 	      if (*s++ == *args)
@@ -11371,8 +11421,8 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      break;
 
 	    case '.':		/* 10-bit offset.  */
-	    case '~':		/* 12-bit offset.  */
 	      gas_assert (mips_opts.micromips);
+	    case '~':		/* 12-bit offset.  */
 	      {
 		int shift = *args == '.' ? 9 : 11;
 		size_t i;
@@ -11398,7 +11448,8 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 		if (shift == 9)
 		  INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
 		else
-		  INSERT_OPERAND (1, OFFSET12, *ip, imm_expr.X_add_number);
+		  INSERT_OPERAND (mips_opts.micromips,
+				  OFFSET12, *ip, imm_expr.X_add_number);
 		imm_expr.X_op = O_absent;
 		s = expr_end;
 	      }
@@ -14176,6 +14227,8 @@ enum options
     OPTION_NO_DSPR2,
     OPTION_MICROMIPS,
     OPTION_NO_MICROMIPS,
+    OPTION_MCU,
+    OPTION_NO_MCU,
     OPTION_COMPAT_ARCH_BASE,
     OPTION_M4650,
     OPTION_NO_M4650,
@@ -14270,6 +14323,8 @@ struct option md_longopts[] =
   {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
   {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
   {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
+  {"mmcu", no_argument, NULL, OPTION_MCU},
+  {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
 
   /* Old-style architecture options.  Don't add more of these.  */
   {"m4650", no_argument, NULL, OPTION_M4650},
@@ -14524,6 +14579,14 @@ md_parse_option (int c, char *arg)
       mips_opts.ase_mt = 0;
       break;
 
+    case OPTION_MCU:
+      mips_opts.ase_mcu = 1;
+      break;
+
+    case OPTION_NO_MCU:
+      mips_opts.ase_mcu = 0;
+      break;
+
     case OPTION_MICROMIPS:
       if (mips_opts.mips16 == 1)
 	{
@@ -15023,6 +15086,12 @@ mips_after_parse_args (void)
     as_warn (_("%s ISA does not support MT ASE"),
 	     mips_cpu_info_from_isa (mips_opts.isa)->name);
 
+  if (mips_opts.ase_mcu == -1)
+    mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0;
+  if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE)
+      as_warn (_("%s ISA does not support MCU ASE"),
+	       mips_cpu_info_from_isa (mips_opts.isa)->name);
+
   file_mips_isa = mips_opts.isa;
   file_ase_mips3d = mips_opts.ase_mips3d;
   file_ase_mdmx = mips_opts.ase_mdmx;
@@ -16069,6 +16138,10 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
     }
   else if (strcmp (name, "nomt") == 0)
     mips_opts.ase_mt = 0;
+  else if (strcmp (name, "mcu") == 0)
+    mips_opts.ase_mcu = 1;
+  else if (strcmp (name, "nomcu") == 0)
+    mips_opts.ase_mcu = 0;
   else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
     {
       int reset = 0;
@@ -19190,6 +19263,9 @@ MIPS options:\n\
 -mmt			generate MT instructions\n\
 -mno-mt			do not generate MT instructions\n"));
   fprintf (stream, _("\
+-mmcu			generate MCU instructions\n\
+-mno-mcu		do not generate MCU instructions\n"));
+  fprintf (stream, _("\
 -mfix-loongson2f-jump	work around Loongson2F JUMP instructions\n\
 -mfix-loongson2f-nop	work around Loongson2F NOP errata\n\
 -mfix-vr4120		work around certain VR4120 errata\n\
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index a2be539..069efa0 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -401,6 +401,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-mdsp}] [@b{-mno-dsp}]
    [@b{-mdspr2}] [@b{-mno-dspr2}]
    [@b{-mmt}] [@b{-mno-mt}]
+   [@b{-mmcu}] [@b{-mno-mcu}]
    [@b{-mfix7000}] [@b{-mno-fix7000}]
    [@b{-mfix-vr4120}] [@b{-mno-fix-vr4120}]
    [@b{-mfix-vr4130}] [@b{-mno-fix-vr4130}]
@@ -1223,6 +1224,12 @@ Generate code for the MT Application Specific Extension.
 This tells the assembler to accept MT instructions.
 @samp{-mno-mt} turns off this option.
 
+@item -mmcu
+@itemx -mno-mcu
+Generate code for the MCU Application Specific Extension.
+This tells the assembler to accept MCU instructions.
+@samp{-mno-mcu} turns off this option.
+
 @item --construct-floats
 @itemx --no-construct-floats
 The @samp{--no-construct-floats} option disables the construction of
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index b6e2ae6..28f31d0 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -175,6 +175,12 @@ Generate code for the MT Application Specific Extension.
 This tells the assembler to accept MT instructions.
 @samp{-mno-mt} turns off this option.
 
+@item -mmcu
+@itemx -mno-mcu
+Generate code for the MCU Application Specific Extension.
+This tells the assembler to accept MCU instructions.
+@samp{-mno-mcu} turns off this option.
+
 @item -mfix7000
 @itemx -mno-fix7000
 Cause nops to be inserted if the read of the destination register
@@ -662,6 +668,14 @@ from the MT Application Specific Extension from that point on
 in the assembly.  The @code{.set nomt} directive prevents MT
 instructions from being accepted.
 
+@cindex MIPS MCU instruction generation override
+@kindex @code{.set mcu}
+@kindex @code{.set nomcu}
+The directive @code{.set mcu} makes the assembler accept instructions
+from the MCU Application Specific Extension from that point on
+in the assembly.  The @code{.set nomcu} directive prevents MCU
+instructions from being accepted.
+
 Traditional @sc{mips} assemblers do not support these directives.
 
 @node MIPS floating-point
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 5e81c90..4526e2f 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,4 +1,12 @@
 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
+            Chao-ying Fu  <fu@mips.com>
+
+	* gas/mips/micromips@mcu.d: New test.
+	* gas/mips/mcu.d: Likewise.
+	* gas/mips/mcu.s: New test source.
+	* gas/mips/mips.exp: Run the new tests.
+
+2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 
 	* gas/mips/micromips.d: Update according to changes to enable
 	microMIPS branch swapping.
diff --git a/gas/testsuite/gas/mips/mcu.d b/gas/testsuite/gas/mips/mcu.d
new file mode 100644
index 0000000..06e5bae
--- /dev/null
+++ b/gas/testsuite/gas/mips/mcu.d
@@ -0,0 +1,122 @@
+#objdump: -dr --show-raw-insn
+#name: MCU for MIPS32r2
+#as: -32
+#source: mcu.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <foo>:
+[ 0-9a-f]+:	42000038 	iret
+[ 0-9a-f]+:	04070000 	aclr	0x0,0\(zero\)
+[ 0-9a-f]+:	04070000 	aclr	0x0,0\(zero\)
+[ 0-9a-f]+:	04070000 	aclr	0x0,0\(zero\)
+[ 0-9a-f]+:	04071000 	aclr	0x1,0\(zero\)
+[ 0-9a-f]+:	04072000 	aclr	0x2,0\(zero\)
+[ 0-9a-f]+:	04073000 	aclr	0x3,0\(zero\)
+[ 0-9a-f]+:	04074000 	aclr	0x4,0\(zero\)
+[ 0-9a-f]+:	04075000 	aclr	0x5,0\(zero\)
+[ 0-9a-f]+:	04076000 	aclr	0x6,0\(zero\)
+[ 0-9a-f]+:	04077000 	aclr	0x7,0\(zero\)
+[ 0-9a-f]+:	04477000 	aclr	0x7,0\(v0\)
+[ 0-9a-f]+:	07e77000 	aclr	0x7,0\(ra\)
+[ 0-9a-f]+:	07e777ff 	aclr	0x7,2047\(ra\)
+[ 0-9a-f]+:	07e77800 	aclr	0x7,-2048\(ra\)
+[ 0-9a-f]+:	24011000 	li	at,4096
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	04277800 	aclr	0x7,-2048\(at\)
+[ 0-9a-f]+:	2401f000 	li	at,-4096
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	042777ff 	aclr	0x7,2047\(at\)
+[ 0-9a-f]+:	34018000 	li	at,0x8000
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	04277fff 	aclr	0x7,-1\(at\)
+[ 0-9a-f]+:	24018000 	li	at,-32768
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	04277000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	3c010001 	lui	at,0x1
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277fff 	aclr	0x7,-1\(at\)
+[ 0-9a-f]+:	3c010001 	lui	at,0x1
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	3c01ffff 	lui	at,0xffff
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	24018000 	li	at,-32768
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	3c01ffff 	lui	at,0xffff
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277001 	aclr	0x7,1\(at\)
+[ 0-9a-f]+:	24018000 	li	at,-32768
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277001 	aclr	0x7,1\(at\)
+[ 0-9a-f]+:	3c01f000 	lui	at,0xf000
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	04877fff 	aclr	0x7,-1\(a0\)
+[ 0-9a-f]+:	3c011234 	lui	at,0x1234
+[ 0-9a-f]+:	34215000 	ori	at,at,0x5000
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	04277678 	aclr	0x7,1656\(at\)
+[ 0-9a-f]+:	24610000 	addiu	at,v1,0
+[ 	]*[0-9a-f]+: R_MIPS_LO16	foo
+[ 0-9a-f]+:	04271000 	aclr	0x1,0\(at\)
+[ 0-9a-f]+:	24610000 	addiu	at,v1,0
+[ 	]*[0-9a-f]+: R_MIPS_LO16	foo
+[ 0-9a-f]+:	04279000 	aset	0x1,0\(at\)
+[ 0-9a-f]+:	04078000 	aset	0x0,0\(zero\)
+[ 0-9a-f]+:	04078000 	aset	0x0,0\(zero\)
+[ 0-9a-f]+:	04078000 	aset	0x0,0\(zero\)
+[ 0-9a-f]+:	04079000 	aset	0x1,0\(zero\)
+[ 0-9a-f]+:	0407a000 	aset	0x2,0\(zero\)
+[ 0-9a-f]+:	0407b000 	aset	0x3,0\(zero\)
+[ 0-9a-f]+:	0407c000 	aset	0x4,0\(zero\)
+[ 0-9a-f]+:	0407d000 	aset	0x5,0\(zero\)
+[ 0-9a-f]+:	0407e000 	aset	0x6,0\(zero\)
+[ 0-9a-f]+:	0407f000 	aset	0x7,0\(zero\)
+[ 0-9a-f]+:	0447f000 	aset	0x7,0\(v0\)
+[ 0-9a-f]+:	07e7f000 	aset	0x7,0\(ra\)
+[ 0-9a-f]+:	07e7f7ff 	aset	0x7,2047\(ra\)
+[ 0-9a-f]+:	07e7f800 	aset	0x7,-2048\(ra\)
+[ 0-9a-f]+:	24011000 	li	at,4096
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	0427f800 	aset	0x7,-2048\(at\)
+[ 0-9a-f]+:	2401f000 	li	at,-4096
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	0427f7ff 	aset	0x7,2047\(at\)
+[ 0-9a-f]+:	34018000 	li	at,0x8000
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	0427ffff 	aset	0x7,-1\(at\)
+[ 0-9a-f]+:	24018000 	li	at,-32768
+[ 0-9a-f]+:	003f0821 	addu	at,at,ra
+[ 0-9a-f]+:	0427f000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	3c010001 	lui	at,0x1
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427ffff 	aset	0x7,-1\(at\)
+[ 0-9a-f]+:	3c010001 	lui	at,0x1
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427f000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	3c01ffff 	lui	at,0xffff
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427f000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	24018000 	li	at,-32768
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427f000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	3c01ffff 	lui	at,0xffff
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427f001 	aset	0x7,1\(at\)
+[ 0-9a-f]+:	24018000 	li	at,-32768
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427f001 	aset	0x7,1\(at\)
+[ 0-9a-f]+:	3c01f000 	lui	at,0xf000
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427f000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	0487ffff 	aset	0x7,-1\(a0\)
+[ 0-9a-f]+:	3c011234 	lui	at,0x1234
+[ 0-9a-f]+:	34215000 	ori	at,at,0x5000
+[ 0-9a-f]+:	00240821 	addu	at,at,a0
+[ 0-9a-f]+:	0427f678 	aset	0x7,1656\(at\)
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mcu.s b/gas/testsuite/gas/mips/mcu.s
new file mode 100644
index 0000000..182008a
--- /dev/null
+++ b/gas/testsuite/gas/mips/mcu.s
@@ -0,0 +1,70 @@
+	.text
+	.set	mcu
+	.ent	foo
+	.globl	foo
+foo:
+	iret
+
+	aclr	0, 0
+	aclr	0, ($0)
+	aclr	0, 0($0)
+	aclr	1, 0($0)
+	aclr	2, 0($0)
+	aclr	3, 0($0)
+	aclr	4, 0($0)
+	aclr	5, 0($0)
+	aclr	6, 0($0)
+	aclr	7, 0($0)
+	aclr	7, 0($2)
+	aclr	7, 0($31)
+	aclr	7, 2047($31)
+	aclr	7, -2048($31)
+	aclr	7, 2048($31)
+	aclr	7, -2049($31)
+	aclr	7, 32767($31)
+	aclr	7, -32768($31)
+	aclr	7, 65535($4)
+	aclr	7, 65536($4)
+	aclr	7, 0xffff0000($4)
+	aclr	7, 0xffff8000($4)
+	aclr	7, 0xffff0001($4)
+	aclr	7, 0xffff8001($4)
+	aclr	7, 0xf0000000($4)
+	aclr	7, 0xffffffff($4)
+	aclr	7, 0x12345678($4)
+
+	aclr	1, %lo(foo)($3)
+	aset	1, %lo(foo)($3)
+
+	aset	0, 0
+	aset	0, ($0)
+	aset	0, 0($0)
+	aset	1, 0($0)
+	aset	2, 0($0)
+	aset	3, 0($0)
+	aset	4, 0($0)
+	aset	5, 0($0)
+	aset	6, 0($0)
+	aset	7, 0($0)
+	aset	7, 0($2)
+	aset	7, 0($31)
+	aset	7, 2047($31)
+	aset	7, -2048($31)
+	aset	7, 2048($31)
+	aset	7, -2049($31)
+	aset	7, 32767($31)
+	aset	7, -32768($31)
+	aset	7, 65535($4)
+	aset	7, 65536($4)
+	aset	7, 0xffff0000($4)
+	aset	7, 0xffff8000($4)
+	aset	7, 0xffff0001($4)
+	aset	7, 0xffff8001($4)
+	aset	7, 0xf0000000($4)
+	aset	7, 0xffffffff($4)
+	aset	7, 0x12345678($4)
+	.end	foo
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.align	2
+	.space	8
diff --git a/gas/testsuite/gas/mips/micromips@mcu.d b/gas/testsuite/gas/mips/micromips@mcu.d
new file mode 100644
index 0000000..eec0ed7
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromips@mcu.d
@@ -0,0 +1,122 @@
+#objdump: -dr --show-raw-insn
+#name: MCU for MIPS32r2
+#as: -32
+#source: mcu.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <foo>:
+[ 0-9a-f]+:	0000 d37c 	iret
+[ 0-9a-f]+:	2000 b000 	aclr	0x0,0\(zero\)
+[ 0-9a-f]+:	2000 b000 	aclr	0x0,0\(zero\)
+[ 0-9a-f]+:	2000 b000 	aclr	0x0,0\(zero\)
+[ 0-9a-f]+:	2020 b000 	aclr	0x1,0\(zero\)
+[ 0-9a-f]+:	2040 b000 	aclr	0x2,0\(zero\)
+[ 0-9a-f]+:	2060 b000 	aclr	0x3,0\(zero\)
+[ 0-9a-f]+:	2080 b000 	aclr	0x4,0\(zero\)
+[ 0-9a-f]+:	20a0 b000 	aclr	0x5,0\(zero\)
+[ 0-9a-f]+:	20c0 b000 	aclr	0x6,0\(zero\)
+[ 0-9a-f]+:	20e0 b000 	aclr	0x7,0\(zero\)
+[ 0-9a-f]+:	20e2 b000 	aclr	0x7,0\(v0\)
+[ 0-9a-f]+:	20ff b000 	aclr	0x7,0\(ra\)
+[ 0-9a-f]+:	20ff b7ff 	aclr	0x7,2047\(ra\)
+[ 0-9a-f]+:	20ff b800 	aclr	0x7,-2048\(ra\)
+[ 0-9a-f]+:	3020 1000 	li	at,4096
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 b800 	aclr	0x7,-2048\(at\)
+[ 0-9a-f]+:	3020 f000 	li	at,-4096
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 b7ff 	aclr	0x7,2047\(at\)
+[ 0-9a-f]+:	5020 8000 	li	at,0x8000
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 bfff 	aclr	0x7,-1\(at\)
+[ 0-9a-f]+:	3020 8000 	li	at,-32768
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 b000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	41a1 0001 	lui	at,0x1
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 bfff 	aclr	0x7,-1\(at\)
+[ 0-9a-f]+:	41a1 0001 	lui	at,0x1
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 b000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	41a1 ffff 	lui	at,0xffff
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 b000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	3020 8000 	li	at,-32768
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 b000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	41a1 ffff 	lui	at,0xffff
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 b001 	aclr	0x7,1\(at\)
+[ 0-9a-f]+:	3020 8000 	li	at,-32768
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 b001 	aclr	0x7,1\(at\)
+[ 0-9a-f]+:	41a1 f000 	lui	at,0xf000
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 b000 	aclr	0x7,0\(at\)
+[ 0-9a-f]+:	20e4 bfff 	aclr	0x7,-1\(a0\)
+[ 0-9a-f]+:	41a1 1234 	lui	at,0x1234
+[ 0-9a-f]+:	5021 5000 	ori	at,at,0x5000
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 b678 	aclr	0x7,1656\(at\)
+[ 0-9a-f]+:	3023 0000 	addiu	at,v1,0
+[ 	]*[0-9a-f]+: R_MICROMIPS_LO16	foo
+[ 0-9a-f]+:	2021 b000 	aclr	0x1,0\(at\)
+[ 0-9a-f]+:	3023 0000 	addiu	at,v1,0
+[ 	]*[0-9a-f]+: R_MICROMIPS_LO16	foo
+[ 0-9a-f]+:	2021 3000 	aset	0x1,0\(at\)
+[ 0-9a-f]+:	2000 3000 	aset	0x0,0\(zero\)
+[ 0-9a-f]+:	2000 3000 	aset	0x0,0\(zero\)
+[ 0-9a-f]+:	2000 3000 	aset	0x0,0\(zero\)
+[ 0-9a-f]+:	2020 3000 	aset	0x1,0\(zero\)
+[ 0-9a-f]+:	2040 3000 	aset	0x2,0\(zero\)
+[ 0-9a-f]+:	2060 3000 	aset	0x3,0\(zero\)
+[ 0-9a-f]+:	2080 3000 	aset	0x4,0\(zero\)
+[ 0-9a-f]+:	20a0 3000 	aset	0x5,0\(zero\)
+[ 0-9a-f]+:	20c0 3000 	aset	0x6,0\(zero\)
+[ 0-9a-f]+:	20e0 3000 	aset	0x7,0\(zero\)
+[ 0-9a-f]+:	20e2 3000 	aset	0x7,0\(v0\)
+[ 0-9a-f]+:	20ff 3000 	aset	0x7,0\(ra\)
+[ 0-9a-f]+:	20ff 37ff 	aset	0x7,2047\(ra\)
+[ 0-9a-f]+:	20ff 3800 	aset	0x7,-2048\(ra\)
+[ 0-9a-f]+:	3020 1000 	li	at,4096
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 3800 	aset	0x7,-2048\(at\)
+[ 0-9a-f]+:	3020 f000 	li	at,-4096
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 37ff 	aset	0x7,2047\(at\)
+[ 0-9a-f]+:	5020 8000 	li	at,0x8000
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 3fff 	aset	0x7,-1\(at\)
+[ 0-9a-f]+:	3020 8000 	li	at,-32768
+[ 0-9a-f]+:	03e1 0950 	addu	at,at,ra
+[ 0-9a-f]+:	20e1 3000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	41a1 0001 	lui	at,0x1
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3fff 	aset	0x7,-1\(at\)
+[ 0-9a-f]+:	41a1 0001 	lui	at,0x1
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	41a1 ffff 	lui	at,0xffff
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	3020 8000 	li	at,-32768
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	41a1 ffff 	lui	at,0xffff
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3001 	aset	0x7,1\(at\)
+[ 0-9a-f]+:	3020 8000 	li	at,-32768
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3001 	aset	0x7,1\(at\)
+[ 0-9a-f]+:	41a1 f000 	lui	at,0xf000
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3000 	aset	0x7,0\(at\)
+[ 0-9a-f]+:	20e4 3fff 	aset	0x7,-1\(a0\)
+[ 0-9a-f]+:	41a1 1234 	lui	at,0x1234
+[ 0-9a-f]+:	5021 5000 	ori	at,at,0x5000
+[ 0-9a-f]+:	0081 0950 	addu	at,at,a0
+[ 0-9a-f]+:	20e1 3678 	aset	0x7,1656\(at\)
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index a66c711..63c2666 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1053,4 +1053,7 @@ if { [istarget mips*-*-vxworks*] } {
 	run_dump_test "micromips-branch-relax-pic"
 	run_dump_test "micromips-branch-delay"
     }
+
+    run_dump_test_arches "mcu"		[mips_arch_list_matching mips32r2 \
+					    !octeon]
 }
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 4d88f24..a69f746 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,13 @@
+2011-08-09  Chao-ying Fu  <fu@mips.com>
+            Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
+	(OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
+	(INSN_ASE_MASK): Add the MCU bit.
+	(INSN_MCU): New macro.
+	(M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
+	(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
+
 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 
 	* mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 1db4aed..e6703f8 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -187,6 +187,12 @@
 #define OP_SH_MTACC_D		13
 #define OP_MASK_MTACC_D		0x3
 
+/* MIPS MCU ASE */
+#define OP_MASK_3BITPOS		0x7
+#define OP_SH_3BITPOS		12
+#define OP_MASK_OFFSET12	0xfff
+#define OP_SH_OFFSET12		0
+
 #define	OP_OP_COP0		0x10
 #define	OP_OP_COP1		0x11
 #define	OP_OP_COP2		0x12
@@ -251,8 +257,6 @@
 #define OP_SH_CODE10		0
 #define OP_MASK_TRAP		0
 #define OP_SH_TRAP		0
-#define OP_MASK_OFFSET12	0
-#define OP_SH_OFFSET12		0
 #define OP_MASK_OFFSET10	0
 #define OP_SH_OFFSET10		0
 #define OP_MASK_RS3		0
@@ -473,6 +477,10 @@ struct mips_opcode
    "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
    "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
 
+   MCU ASE usage:
+   "~" 12 bit offset (OP_*_OFFSET12)
+   "\" 3 bit position for aset and aclr (OP_*_3BITPOS)
+
    UDI immediates:
    "+1" UDI immediate bits 6-10
    "+2" UDI immediate bits 6-15
@@ -508,7 +516,7 @@ struct mips_opcode
 
    Characters used so far, for quick reference when adding more:
    "1234567890"
-   "%[]<>(),+:'@!$*&"
+   "%[]<>(),+:'@!$*&\~"
    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
    "abcdefghijklopqrstuvwxz"
 
@@ -711,7 +719,7 @@ static const unsigned int mips_isa_table[] =
 #define INSN_OCTEON		  0x00000800
 
 /* Masks used for MIPS-defined ASEs.  */
-#define INSN_ASE_MASK		  0x3c00f000
+#define INSN_ASE_MASK		  0x3c00f010
 
 /* DSP ASE */ 
 #define INSN_DSP                  0x00001000
@@ -760,6 +768,9 @@ static const unsigned int mips_isa_table[] =
 /* RMI Xlr instruction */
 #define INSN_XLR              	  0x00000020
 
+/* MCU (MicroController) ASE */
+#define INSN_MCU		  0x00000010
+
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
@@ -862,9 +873,13 @@ static const unsigned int mips_isa_table[] =
 enum
 {
   M_ABS,
+  M_ACLR_AB,
+  M_ACLR_OB,
   M_ADD_I,
   M_ADDU_I,
   M_AND_I,
+  M_ASET_AB,
+  M_ASET_OB,
   M_BALIGN,
   M_BC1FL,
   M_BC1TL,
@@ -1366,6 +1381,8 @@ extern const int bfd_mips16_num_opcodes;
 #define MICROMIPSOP_SH_SEL		11
 #define MICROMIPSOP_MASK_OFFSET12	0xfff
 #define MICROMIPSOP_SH_OFFSET12		0
+#define MICROMIPSOP_MASK_3BITPOS	0x7
+#define MICROMIPSOP_SH_3BITPOS		21
 #define MICROMIPSOP_MASK_STYPE		0x1f
 #define MICROMIPSOP_SH_STYPE		16
 #define MICROMIPSOP_MASK_OFFSET10	0x3ff
@@ -1591,6 +1608,7 @@ extern const int bfd_mips16_num_opcodes;
    "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
    ">" shift amount between 32 and 63, stored after subtracting 32
        (MICROMIPSOP_*_SHAMT)
+   "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS)
    "|" 4-bit trap code (MICROMIPSOP_*_TRAP)
    "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
    "a" 26-bit target address (MICROMIPSOP_*_TARGET)
@@ -1680,7 +1698,7 @@ extern const int bfd_mips16_num_opcodes;
 
    Characters used so far, for quick reference when adding more:
    "1234567890"
-   "<>(),+.|~"
+   "<>(),+.\|~"
    "ABCDEFGHI KLMN   RST V    "
    "abcd f hijklmnopqrstuvw yz"
 
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0a59fab..7c603f1 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,14 @@
+2011-08-09  Chao-ying Fu  <fu@mips.com>
+            Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
+	and "mips64r2".
+	(print_insn_args, print_insn_micromips): Handle MCU.
+	* micromips-opc.c (MC): New macro.
+	(micromips_opcodes): Add "aclr", "aset" and "iret".
+	* mips-opc.c (MC): New macro.
+	(mips_builtin_opcodes): Add "aclr", "aset" and "iret".
+
 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 
 	* micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 0d5b11d..852081e 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -99,6 +99,9 @@
 #define I1	INSN_ISA1
 #define I3	INSN_ISA3
 
+/* MIPS MCU (MicroController) ASE support.  */
+#define MC	INSN_MCU
+
 const struct mips_opcode micromips_opcodes[] =
 {
 /* These instructions appear first so that the disassembler will find
@@ -138,6 +141,9 @@ const struct mips_opcode micromips_opcodes[] =
 {"abs.d",   "T,V",	0x5400237b, 0xfc00ffff,	WR_T|RD_S|FP_D,		0,		I1	},
 {"abs.s",   "T,V",	0x5400037b, 0xfc00ffff,	WR_T|RD_S|FP_S,		0,		I1	},
 {"abs.ps",  "T,V",	0x5400437b, 0xfc00ffff,	WR_T|RD_S|FP_D,		0,		I1	},
+{"aclr",    "\\,~(b)",	0x2000b000, 0xff00f000,	SM|RD_b|NODS,		0,		MC	},
+{"aclr",    "\\,o(b)",	0,    (int) M_ACLR_OB,	INSN_MACRO,		0,		MC	},
+{"aclr",    "\\,A(b)",	0,    (int) M_ACLR_AB,	INSN_MACRO,		0,		MC	},
 {"add",     "d,v,t",	0x00000110, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
 {"add",     "t,r,I",	0,    (int) M_ADD_I,	INSN_MACRO,		0,		I1	},
 {"add.d",   "D,V,T",	0x54000130, 0xfc0007ff,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
@@ -170,6 +176,9 @@ const struct mips_opcode micromips_opcodes[] =
 {"and",     "t,r,I",	0,    (int) M_AND_I,	INSN_MACRO,		0,		I1	},
 {"andi",    "md,mc,mC",	    0x2c00,     0xfc00,	0,			WR_md|RD_mc,	I1	},
 {"andi",    "t,r,i",	0xd0000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
+{"aset",    "\\,~(b)",	0x20003000, 0xff00f000,	SM|RD_b|NODS,		0,		MC	},
+{"aset",    "\\,o(b)",	0,    (int) M_ASET_OB,	INSN_MACRO,		0,		MC	},
+{"aset",    "\\,A(b)",	0,    (int) M_ASET_AB,	INSN_MACRO,		0,		MC	},
 /* b is at the top of the table.  */
 /* bal is at the top of the table.  */
 {"bc1f",    "p",	0x43800000, 0xffff0000,	CBD|RD_CC|FP_S,		0,		I1	},
@@ -508,6 +517,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"floor.w.d", "T,V",	0x54004b3b, 0xfc00ffff,	WR_T|RD_S|FP_S|FP_D,	0,		I1	},
 {"floor.w.s", "T,V",	0x54000b3b, 0xfc00ffff,	WR_T|RD_S|FP_S,		0,		I1	},
 {"ins",     "t,r,+A,+B", 0x0000000c, 0xfc00003f, WR_t|RD_s,		0,		I1	},
+{"iret",    "",		0x0000d37c, 0xffffffff,	NODS,			0,		MC	},
 {"jr",      "mj",	    0x4580,     0xffe0,	UBD,			RD_mj,		I1	},
 {"jr",      "s",	0x00000f3c, 0xffe0ffff,	UBD|RD_s,		BD32,		I1	}, /* jalr */
 {"jrs",     "s",	0x00004f3c, 0xffe0ffff,	UBD|RD_s,		BD16,		I1	}, /* jalrs */
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 75f9bb7..4e18d8a 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -564,7 +564,7 @@ const struct mips_arch_choice mips_arch_choices[] =
 
   { "mips32r2",	1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
     (ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
-     | INSN_MIPS3D | INSN_MT),
+     | INSN_MIPS3D | INSN_MT | INSN_MCU),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_hwr_names_mips3264r2 },
@@ -578,7 +578,7 @@ const struct mips_arch_choice mips_arch_choices[] =
 
   { "mips64r2",	1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
     (ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
-     | INSN_DSP64 | INSN_MT | INSN_MDMX),
+     | INSN_DSP64 | INSN_MT | INSN_MDMX | INSN_MCU),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_hwr_names_mips3264r2 },
@@ -1170,6 +1170,18 @@ print_insn_args (const char *d,
 	  (*info->fprintf_func) (info->stream, "%d", delta);
 	  break;
 
+	case '~':
+	  delta = (l >> OP_SH_OFFSET12) & OP_MASK_OFFSET12;
+	  if (delta & 0x800)
+	    delta |= ~0x7ff;
+	  (*info->fprintf_func) (info->stream, "%d", delta);
+	  break;
+
+	case '\\':
+	  (*info->fprintf_func) (info->stream, "0x%lx",
+				 (l >> OP_SH_3BITPOS) & OP_MASK_3BITPOS);
+	  break;
+
 	case '\'':
 	  (*info->fprintf_func) (info->stream, "0x%lx",
 				 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
@@ -2388,6 +2400,10 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
 		  iprintf (is, "0x%lx", GET_OP (insn, SHAMT));
 		  break;
 
+		case '\\':
+		  iprintf (is, "0x%lx", GET_OP (insn, 3BITPOS));
+		  break;
+
 		case '|':
 		  iprintf (is, "0x%lx", GET_OP (insn, TRAP));
 		  break;
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index f8770a4..7adf337 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -173,6 +173,9 @@
 #define RD_Z	INSN2_READ_FPR_Z
 #define RD_d	INSN2_READ_GPR_D
 
+/* MIPS MCU (MicroController) ASE support.  */
+#define MC	INSN_MCU
+
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -272,6 +275,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"abs.d",   "D,V",	0x46200005, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I1	},
 {"abs.ps",  "D,V",	0x46c00005, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I5_33|IL2F	},
 {"abs.ps",  "D,V",	0x45600005, 0xffff003f,	WR_D|RD_S|FP_D,		0,		IL2E	},
+{"aclr",    "\\,~(b)",	0x04070000, 0xfc1f8000,	SM|RD_b|NODS,		0,		MC	},
+{"aclr",    "\\,o(b)",	0,    (int) M_ACLR_OB,	INSN_MACRO,		0,		MC	},
+{"aclr",    "\\,A(b)",	0,    (int) M_ACLR_AB,	INSN_MACRO,		0,		MC	},
 {"add",     "d,v,t",	0x00000020, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
 {"add",     "t,r,I",	0,    (int) M_ADD_I,	INSN_MACRO,		0,		I1	},
 {"add",	"D,S,T",	0x45c00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
@@ -312,6 +318,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"and.ob",  "D,S,k",	0x4bc0000c, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"and.qh",  "X,Y,Q",	0x7820000c, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
 {"andi",    "t,r,i",	0x30000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
+{"aset",    "\\,~(b)",	0x04078000, 0xfc1f8000,	SM|RD_b|NODS,		0,		MC	},
+{"aset",    "\\,o(b)",	0,    (int) M_ASET_OB,	INSN_MACRO,		0,		MC	},
+{"aset",    "\\,A(b)",	0,    (int) M_ASET_AB,	INSN_MACRO,		0,		MC	},
 {"baddu",   "d,v,t",	0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		IOCT	},
 /* b is at the top of the table.  */
 /* bal is at the top of the table.  */
@@ -778,6 +787,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"floor.w.s", "D,S",	0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2	},
 {"hibernate","",        0x42000023, 0xffffffff,	0, 			0,		V1	},
 {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,    		0,		I33	},
+{"iret",    "",		0x42000038, 0xffffffff,	NODS,			0,		MC	},
 {"jr",      "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		0,		I1	},
 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
    the same hazard barrier effect.  */
author	Maciej W. Rozycki <macro@linux-mips.org>	2011-08-09 15:20:03 +0000
committer	Maciej W. Rozycki <macro@linux-mips.org>	2011-08-09 15:20:03 +0000
commit	dec0624dcd4590d55fad203497fcdcef4ce292e3 (patch)
tree	0b51906dbdefe2193c68282fd68a1652b1f998f4
parent	2b0c8b40edb06c073ce8bb358239cc1a5c6653a5 (diff)
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