[ gas/ChangeLog ]

2002-12-31  Chris Demetriou  <cgd@broadcom.com>

	* config/tc-mips.c (validate_mips_insn, mips_ip): Recognize
	the "+D" operand, which will be used only by the disassembler.

[ gas/testsuite/ChangeLog ]
2002-12-31  Chris Demetriou  <cgd@broadcom.com>

	* gas/mips/cp0sel-names-mips32.d: New test.
	* gas/mips/cp0sel-names-mips32r2.d: New test.
	* gas/mips/cp0sel-names-mips64.d: New test.
	* gas/mips/cp0sel-names-numeric.d: New test.
	* gas/mips/cp0sel-names-sb1.d: New test.
	* gas/mips/cp0sel-names.s: New test source file.
	* gas/mips/mips.exp: Run new tests.

[ include/opcode/ChangeLog ]
2002-12-31  Chris Demetriou  <cgd@broadcom.com>

	* mips.h: Note that the "+D" operand type name is now used.

[ opcodes/ChangeLog ]
2002-12-31  Chris Demetriou  <cgd@broadcom.com>

	* mips-dis.c (mips_cp0sel_name): New structure.
	(mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2)
	(mips_cp0sel_names_sb1): New arrays.
	(mips_arch_choice): New structure members "cp0sel_names" and
	"cp0sel_names_len".
	(mips_arch_choices): Add references to new cp0sel_names arrays
	as appropriate, and make all existing entries reference
	appropriate mips_XXX_names_numeric arrays rather than simply
	using NULL.
	(mips_cp0sel_names, mips_cp0sel_names_len): New variables.
	(lookup_mips_cp0sel_name): New function.
	(set_default_mips_dis_options): Set mips_cp0sel_names and
	mips_cp0sel_names_len as appropriate.  Remove now-unnecessary
	checks for NULL register name arrays.
	(parse_mips_dis_option): Likewise.
	(print_insn_arg): Handle "+D" operand type.
	* mips-opc.c (mips_builtin_opcodes): Add new "+D" variants
	of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register
	names symbolically.

15 files changed, 1688 insertions, 44 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 19d6a60..833e3e0 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2002-12-31  Chris Demetriou  <cgd@broadcom.com>
+
+	* config/tc-mips.c (validate_mips_insn, mips_ip): Recognize
+	the "+D" operand, which will be used only by the disassembler.
+
 2002-12-30  Chris Demetriou  <cgd@broadcom.com>
 
 	* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index b501c19..2c46fec 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -8022,6 +8022,8 @@ validate_mips_insn (opc)
 	  case 'A': USE_BITS (OP_MASK_SHAMT,	OP_SH_SHAMT);	break;
 	  case 'B': USE_BITS (OP_MASK_INSMSB,	OP_SH_INSMSB);	break;
 	  case 'C': USE_BITS (OP_MASK_EXTMSBD,	OP_SH_EXTMSBD);	break;
+	  case 'D': USE_BITS (OP_MASK_RD,	OP_SH_RD);
+		    USE_BITS (OP_MASK_SEL,	OP_SH_SEL);	break;
 	  default:
 	    as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
 		    c, opc->name, opc->args);
@@ -8337,6 +8339,10 @@ mips_ip (str, ip)
 		    s = expr_end;
 		    continue;
 
+		case 'D':
+		  /* +D is for disassembly only; never match.  */
+		  break;
+
 		default:
 		  as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
 		    *args, insn->name, insn->args);
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 48b0149..a9c16c9 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2002-12-31  Chris Demetriou  <cgd@broadcom.com>
+
+	* gas/mips/cp0sel-names-mips32.d: New test.
+	* gas/mips/cp0sel-names-mips32r2.d: New test.
+	* gas/mips/cp0sel-names-mips64.d: New test.
+	* gas/mips/cp0sel-names-numeric.d: New test.
+	* gas/mips/cp0sel-names-sb1.d: New test.
+	* gas/mips/cp0sel-names.s: New test source file.
+	* gas/mips/mips.exp: Run new tests.
+
 2002-12-30  Chris Demetriou  <cgd@broadcom.com>
 
 	* gas/mips/elf_arch_mips1.d: New test.
diff --git a/gas/testsuite/gas/mips/cp0sel-names-mips32.d b/gas/testsuite/gas/mips/cp0sel-names-mips32.d
new file mode 100644
index 0000000..8cefcb6
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp0sel-names-mips32.d
@@ -0,0 +1,235 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa32 -M gpr-names=numeric,cp0-names=mips32
+#name: MIPS CP0 with sel register disassembly (mips32)
+#as: -march=mips32
+#source: cp0sel-names.s
+
+# Check objdump's handling of -M cp0-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 40800001 	mtc0	\$0,\$0,1
+0+0004 <[^>]*> 40800002 	mtc0	\$0,\$0,2
+0+0008 <[^>]*> 40800003 	mtc0	\$0,\$0,3
+0+000c <[^>]*> 40800004 	mtc0	\$0,\$0,4
+0+0010 <[^>]*> 40800005 	mtc0	\$0,\$0,5
+0+0014 <[^>]*> 40800006 	mtc0	\$0,\$0,6
+0+0018 <[^>]*> 40800007 	mtc0	\$0,\$0,7
+0+001c <[^>]*> 40800801 	mtc0	\$0,\$1,1
+0+0020 <[^>]*> 40800802 	mtc0	\$0,\$1,2
+0+0024 <[^>]*> 40800803 	mtc0	\$0,\$1,3
+0+0028 <[^>]*> 40800804 	mtc0	\$0,\$1,4
+0+002c <[^>]*> 40800805 	mtc0	\$0,\$1,5
+0+0030 <[^>]*> 40800806 	mtc0	\$0,\$1,6
+0+0034 <[^>]*> 40800807 	mtc0	\$0,\$1,7
+0+0038 <[^>]*> 40801001 	mtc0	\$0,\$2,1
+0+003c <[^>]*> 40801002 	mtc0	\$0,\$2,2
+0+0040 <[^>]*> 40801003 	mtc0	\$0,\$2,3
+0+0044 <[^>]*> 40801004 	mtc0	\$0,\$2,4
+0+0048 <[^>]*> 40801005 	mtc0	\$0,\$2,5
+0+004c <[^>]*> 40801006 	mtc0	\$0,\$2,6
+0+0050 <[^>]*> 40801007 	mtc0	\$0,\$2,7
+0+0054 <[^>]*> 40801801 	mtc0	\$0,\$3,1
+0+0058 <[^>]*> 40801802 	mtc0	\$0,\$3,2
+0+005c <[^>]*> 40801803 	mtc0	\$0,\$3,3
+0+0060 <[^>]*> 40801804 	mtc0	\$0,\$3,4
+0+0064 <[^>]*> 40801805 	mtc0	\$0,\$3,5
+0+0068 <[^>]*> 40801806 	mtc0	\$0,\$3,6
+0+006c <[^>]*> 40801807 	mtc0	\$0,\$3,7
+0+0070 <[^>]*> 40802001 	mtc0	\$0,\$4,1
+0+0074 <[^>]*> 40802002 	mtc0	\$0,\$4,2
+0+0078 <[^>]*> 40802003 	mtc0	\$0,\$4,3
+0+007c <[^>]*> 40802004 	mtc0	\$0,\$4,4
+0+0080 <[^>]*> 40802005 	mtc0	\$0,\$4,5
+0+0084 <[^>]*> 40802006 	mtc0	\$0,\$4,6
+0+0088 <[^>]*> 40802007 	mtc0	\$0,\$4,7
+0+008c <[^>]*> 40802801 	mtc0	\$0,\$5,1
+0+0090 <[^>]*> 40802802 	mtc0	\$0,\$5,2
+0+0094 <[^>]*> 40802803 	mtc0	\$0,\$5,3
+0+0098 <[^>]*> 40802804 	mtc0	\$0,\$5,4
+0+009c <[^>]*> 40802805 	mtc0	\$0,\$5,5
+0+00a0 <[^>]*> 40802806 	mtc0	\$0,\$5,6
+0+00a4 <[^>]*> 40802807 	mtc0	\$0,\$5,7
+0+00a8 <[^>]*> 40803001 	mtc0	\$0,\$6,1
+0+00ac <[^>]*> 40803002 	mtc0	\$0,\$6,2
+0+00b0 <[^>]*> 40803003 	mtc0	\$0,\$6,3
+0+00b4 <[^>]*> 40803004 	mtc0	\$0,\$6,4
+0+00b8 <[^>]*> 40803005 	mtc0	\$0,\$6,5
+0+00bc <[^>]*> 40803006 	mtc0	\$0,\$6,6
+0+00c0 <[^>]*> 40803007 	mtc0	\$0,\$6,7
+0+00c4 <[^>]*> 40803801 	mtc0	\$0,\$7,1
+0+00c8 <[^>]*> 40803802 	mtc0	\$0,\$7,2
+0+00cc <[^>]*> 40803803 	mtc0	\$0,\$7,3
+0+00d0 <[^>]*> 40803804 	mtc0	\$0,\$7,4
+0+00d4 <[^>]*> 40803805 	mtc0	\$0,\$7,5
+0+00d8 <[^>]*> 40803806 	mtc0	\$0,\$7,6
+0+00dc <[^>]*> 40803807 	mtc0	\$0,\$7,7
+0+00e0 <[^>]*> 40804001 	mtc0	\$0,\$8,1
+0+00e4 <[^>]*> 40804002 	mtc0	\$0,\$8,2
+0+00e8 <[^>]*> 40804003 	mtc0	\$0,\$8,3
+0+00ec <[^>]*> 40804004 	mtc0	\$0,\$8,4
+0+00f0 <[^>]*> 40804005 	mtc0	\$0,\$8,5
+0+00f4 <[^>]*> 40804006 	mtc0	\$0,\$8,6
+0+00f8 <[^>]*> 40804007 	mtc0	\$0,\$8,7
+0+00fc <[^>]*> 40804801 	mtc0	\$0,\$9,1
+0+0100 <[^>]*> 40804802 	mtc0	\$0,\$9,2
+0+0104 <[^>]*> 40804803 	mtc0	\$0,\$9,3
+0+0108 <[^>]*> 40804804 	mtc0	\$0,\$9,4
+0+010c <[^>]*> 40804805 	mtc0	\$0,\$9,5
+0+0110 <[^>]*> 40804806 	mtc0	\$0,\$9,6
+0+0114 <[^>]*> 40804807 	mtc0	\$0,\$9,7
+0+0118 <[^>]*> 40805001 	mtc0	\$0,\$10,1
+0+011c <[^>]*> 40805002 	mtc0	\$0,\$10,2
+0+0120 <[^>]*> 40805003 	mtc0	\$0,\$10,3
+0+0124 <[^>]*> 40805004 	mtc0	\$0,\$10,4
+0+0128 <[^>]*> 40805005 	mtc0	\$0,\$10,5
+0+012c <[^>]*> 40805006 	mtc0	\$0,\$10,6
+0+0130 <[^>]*> 40805007 	mtc0	\$0,\$10,7
+0+0134 <[^>]*> 40805801 	mtc0	\$0,\$11,1
+0+0138 <[^>]*> 40805802 	mtc0	\$0,\$11,2
+0+013c <[^>]*> 40805803 	mtc0	\$0,\$11,3
+0+0140 <[^>]*> 40805804 	mtc0	\$0,\$11,4
+0+0144 <[^>]*> 40805805 	mtc0	\$0,\$11,5
+0+0148 <[^>]*> 40805806 	mtc0	\$0,\$11,6
+0+014c <[^>]*> 40805807 	mtc0	\$0,\$11,7
+0+0150 <[^>]*> 40806001 	mtc0	\$0,\$12,1
+0+0154 <[^>]*> 40806002 	mtc0	\$0,\$12,2
+0+0158 <[^>]*> 40806003 	mtc0	\$0,\$12,3
+0+015c <[^>]*> 40806004 	mtc0	\$0,\$12,4
+0+0160 <[^>]*> 40806005 	mtc0	\$0,\$12,5
+0+0164 <[^>]*> 40806006 	mtc0	\$0,\$12,6
+0+0168 <[^>]*> 40806007 	mtc0	\$0,\$12,7
+0+016c <[^>]*> 40806801 	mtc0	\$0,\$13,1
+0+0170 <[^>]*> 40806802 	mtc0	\$0,\$13,2
+0+0174 <[^>]*> 40806803 	mtc0	\$0,\$13,3
+0+0178 <[^>]*> 40806804 	mtc0	\$0,\$13,4
+0+017c <[^>]*> 40806805 	mtc0	\$0,\$13,5
+0+0180 <[^>]*> 40806806 	mtc0	\$0,\$13,6
+0+0184 <[^>]*> 40806807 	mtc0	\$0,\$13,7
+0+0188 <[^>]*> 40807001 	mtc0	\$0,\$14,1
+0+018c <[^>]*> 40807002 	mtc0	\$0,\$14,2
+0+0190 <[^>]*> 40807003 	mtc0	\$0,\$14,3
+0+0194 <[^>]*> 40807004 	mtc0	\$0,\$14,4
+0+0198 <[^>]*> 40807005 	mtc0	\$0,\$14,5
+0+019c <[^>]*> 40807006 	mtc0	\$0,\$14,6
+0+01a0 <[^>]*> 40807007 	mtc0	\$0,\$14,7
+0+01a4 <[^>]*> 40807801 	mtc0	\$0,\$15,1
+0+01a8 <[^>]*> 40807802 	mtc0	\$0,\$15,2
+0+01ac <[^>]*> 40807803 	mtc0	\$0,\$15,3
+0+01b0 <[^>]*> 40807804 	mtc0	\$0,\$15,4
+0+01b4 <[^>]*> 40807805 	mtc0	\$0,\$15,5
+0+01b8 <[^>]*> 40807806 	mtc0	\$0,\$15,6
+0+01bc <[^>]*> 40807807 	mtc0	\$0,\$15,7
+0+01c0 <[^>]*> 40808001 	mtc0	\$0,c0_config1
+0+01c4 <[^>]*> 40808002 	mtc0	\$0,c0_config2
+0+01c8 <[^>]*> 40808003 	mtc0	\$0,c0_config3
+0+01cc <[^>]*> 40808004 	mtc0	\$0,\$16,4
+0+01d0 <[^>]*> 40808005 	mtc0	\$0,\$16,5
+0+01d4 <[^>]*> 40808006 	mtc0	\$0,\$16,6
+0+01d8 <[^>]*> 40808007 	mtc0	\$0,\$16,7
+0+01dc <[^>]*> 40808801 	mtc0	\$0,\$17,1
+0+01e0 <[^>]*> 40808802 	mtc0	\$0,\$17,2
+0+01e4 <[^>]*> 40808803 	mtc0	\$0,\$17,3
+0+01e8 <[^>]*> 40808804 	mtc0	\$0,\$17,4
+0+01ec <[^>]*> 40808805 	mtc0	\$0,\$17,5
+0+01f0 <[^>]*> 40808806 	mtc0	\$0,\$17,6
+0+01f4 <[^>]*> 40808807 	mtc0	\$0,\$17,7
+0+01f8 <[^>]*> 40809001 	mtc0	\$0,c0_watchlo,1
+0+01fc <[^>]*> 40809002 	mtc0	\$0,c0_watchlo,2
+0+0200 <[^>]*> 40809003 	mtc0	\$0,c0_watchlo,3
+0+0204 <[^>]*> 40809004 	mtc0	\$0,c0_watchlo,4
+0+0208 <[^>]*> 40809005 	mtc0	\$0,c0_watchlo,5
+0+020c <[^>]*> 40809006 	mtc0	\$0,c0_watchlo,6
+0+0210 <[^>]*> 40809007 	mtc0	\$0,c0_watchlo,7
+0+0214 <[^>]*> 40809801 	mtc0	\$0,c0_watchhi,1
+0+0218 <[^>]*> 40809802 	mtc0	\$0,c0_watchhi,2
+0+021c <[^>]*> 40809803 	mtc0	\$0,c0_watchhi,3
+0+0220 <[^>]*> 40809804 	mtc0	\$0,c0_watchhi,4
+0+0224 <[^>]*> 40809805 	mtc0	\$0,c0_watchhi,5
+0+0228 <[^>]*> 40809806 	mtc0	\$0,c0_watchhi,6
+0+022c <[^>]*> 40809807 	mtc0	\$0,c0_watchhi,7
+0+0230 <[^>]*> 4080a001 	mtc0	\$0,\$20,1
+0+0234 <[^>]*> 4080a002 	mtc0	\$0,\$20,2
+0+0238 <[^>]*> 4080a003 	mtc0	\$0,\$20,3
+0+023c <[^>]*> 4080a004 	mtc0	\$0,\$20,4
+0+0240 <[^>]*> 4080a005 	mtc0	\$0,\$20,5
+0+0244 <[^>]*> 4080a006 	mtc0	\$0,\$20,6
+0+0248 <[^>]*> 4080a007 	mtc0	\$0,\$20,7
+0+024c <[^>]*> 4080a801 	mtc0	\$0,\$21,1
+0+0250 <[^>]*> 4080a802 	mtc0	\$0,\$21,2
+0+0254 <[^>]*> 4080a803 	mtc0	\$0,\$21,3
+0+0258 <[^>]*> 4080a804 	mtc0	\$0,\$21,4
+0+025c <[^>]*> 4080a805 	mtc0	\$0,\$21,5
+0+0260 <[^>]*> 4080a806 	mtc0	\$0,\$21,6
+0+0264 <[^>]*> 4080a807 	mtc0	\$0,\$21,7
+0+0268 <[^>]*> 4080b001 	mtc0	\$0,\$22,1
+0+026c <[^>]*> 4080b002 	mtc0	\$0,\$22,2
+0+0270 <[^>]*> 4080b003 	mtc0	\$0,\$22,3
+0+0274 <[^>]*> 4080b004 	mtc0	\$0,\$22,4
+0+0278 <[^>]*> 4080b005 	mtc0	\$0,\$22,5
+0+027c <[^>]*> 4080b006 	mtc0	\$0,\$22,6
+0+0280 <[^>]*> 4080b007 	mtc0	\$0,\$22,7
+0+0284 <[^>]*> 4080b801 	mtc0	\$0,\$23,1
+0+0288 <[^>]*> 4080b802 	mtc0	\$0,\$23,2
+0+028c <[^>]*> 4080b803 	mtc0	\$0,\$23,3
+0+0290 <[^>]*> 4080b804 	mtc0	\$0,\$23,4
+0+0294 <[^>]*> 4080b805 	mtc0	\$0,\$23,5
+0+0298 <[^>]*> 4080b806 	mtc0	\$0,\$23,6
+0+029c <[^>]*> 4080b807 	mtc0	\$0,\$23,7
+0+02a0 <[^>]*> 4080c001 	mtc0	\$0,\$24,1
+0+02a4 <[^>]*> 4080c002 	mtc0	\$0,\$24,2
+0+02a8 <[^>]*> 4080c003 	mtc0	\$0,\$24,3
+0+02ac <[^>]*> 4080c004 	mtc0	\$0,\$24,4
+0+02b0 <[^>]*> 4080c005 	mtc0	\$0,\$24,5
+0+02b4 <[^>]*> 4080c006 	mtc0	\$0,\$24,6
+0+02b8 <[^>]*> 4080c007 	mtc0	\$0,\$24,7
+0+02bc <[^>]*> 4080c801 	mtc0	\$0,c0_perfcnt,1
+0+02c0 <[^>]*> 4080c802 	mtc0	\$0,c0_perfcnt,2
+0+02c4 <[^>]*> 4080c803 	mtc0	\$0,c0_perfcnt,3
+0+02c8 <[^>]*> 4080c804 	mtc0	\$0,c0_perfcnt,4
+0+02cc <[^>]*> 4080c805 	mtc0	\$0,c0_perfcnt,5
+0+02d0 <[^>]*> 4080c806 	mtc0	\$0,c0_perfcnt,6
+0+02d4 <[^>]*> 4080c807 	mtc0	\$0,c0_perfcnt,7
+0+02d8 <[^>]*> 4080d001 	mtc0	\$0,\$26,1
+0+02dc <[^>]*> 4080d002 	mtc0	\$0,\$26,2
+0+02e0 <[^>]*> 4080d003 	mtc0	\$0,\$26,3
+0+02e4 <[^>]*> 4080d004 	mtc0	\$0,\$26,4
+0+02e8 <[^>]*> 4080d005 	mtc0	\$0,\$26,5
+0+02ec <[^>]*> 4080d006 	mtc0	\$0,\$26,6
+0+02f0 <[^>]*> 4080d007 	mtc0	\$0,\$26,7
+0+02f4 <[^>]*> 4080d801 	mtc0	\$0,c0_cacheerr,1
+0+02f8 <[^>]*> 4080d802 	mtc0	\$0,c0_cacheerr,2
+0+02fc <[^>]*> 4080d803 	mtc0	\$0,c0_cacheerr,3
+0+0300 <[^>]*> 4080d804 	mtc0	\$0,\$27,4
+0+0304 <[^>]*> 4080d805 	mtc0	\$0,\$27,5
+0+0308 <[^>]*> 4080d806 	mtc0	\$0,\$27,6
+0+030c <[^>]*> 4080d807 	mtc0	\$0,\$27,7
+0+0310 <[^>]*> 4080e001 	mtc0	\$0,c0_datalo
+0+0314 <[^>]*> 4080e002 	mtc0	\$0,\$28,2
+0+0318 <[^>]*> 4080e003 	mtc0	\$0,\$28,3
+0+031c <[^>]*> 4080e004 	mtc0	\$0,\$28,4
+0+0320 <[^>]*> 4080e005 	mtc0	\$0,\$28,5
+0+0324 <[^>]*> 4080e006 	mtc0	\$0,\$28,6
+0+0328 <[^>]*> 4080e007 	mtc0	\$0,\$28,7
+0+032c <[^>]*> 4080e801 	mtc0	\$0,c0_datahi
+0+0330 <[^>]*> 4080e802 	mtc0	\$0,\$29,2
+0+0334 <[^>]*> 4080e803 	mtc0	\$0,\$29,3
+0+0338 <[^>]*> 4080e804 	mtc0	\$0,\$29,4
+0+033c <[^>]*> 4080e805 	mtc0	\$0,\$29,5
+0+0340 <[^>]*> 4080e806 	mtc0	\$0,\$29,6
+0+0344 <[^>]*> 4080e807 	mtc0	\$0,\$29,7
+0+0348 <[^>]*> 4080f001 	mtc0	\$0,\$30,1
+0+034c <[^>]*> 4080f002 	mtc0	\$0,\$30,2
+0+0350 <[^>]*> 4080f003 	mtc0	\$0,\$30,3
+0+0354 <[^>]*> 4080f004 	mtc0	\$0,\$30,4
+0+0358 <[^>]*> 4080f005 	mtc0	\$0,\$30,5
+0+035c <[^>]*> 4080f006 	mtc0	\$0,\$30,6
+0+0360 <[^>]*> 4080f007 	mtc0	\$0,\$30,7
+0+0364 <[^>]*> 4080f801 	mtc0	\$0,\$31,1
+0+0368 <[^>]*> 4080f802 	mtc0	\$0,\$31,2
+0+036c <[^>]*> 4080f803 	mtc0	\$0,\$31,3
+0+0370 <[^>]*> 4080f804 	mtc0	\$0,\$31,4
+0+0374 <[^>]*> 4080f805 	mtc0	\$0,\$31,5
+0+0378 <[^>]*> 4080f806 	mtc0	\$0,\$31,6
+0+037c <[^>]*> 4080f807 	mtc0	\$0,\$31,7
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/cp0sel-names-mips32r2.d b/gas/testsuite/gas/mips/cp0sel-names-mips32r2.d
new file mode 100644
index 0000000..f61ee8a
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp0sel-names-mips32r2.d
@@ -0,0 +1,235 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa32 -M gpr-names=numeric,cp0-names=mips32r2
+#name: MIPS CP0 with sel register disassembly (mips32r2)
+#as: -march=mips32
+#source: cp0sel-names.s
+
+# Check objdump's handling of -M cp0-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 40800001 	mtc0	\$0,\$0,1
+0+0004 <[^>]*> 40800002 	mtc0	\$0,\$0,2
+0+0008 <[^>]*> 40800003 	mtc0	\$0,\$0,3
+0+000c <[^>]*> 40800004 	mtc0	\$0,\$0,4
+0+0010 <[^>]*> 40800005 	mtc0	\$0,\$0,5
+0+0014 <[^>]*> 40800006 	mtc0	\$0,\$0,6
+0+0018 <[^>]*> 40800007 	mtc0	\$0,\$0,7
+0+001c <[^>]*> 40800801 	mtc0	\$0,\$1,1
+0+0020 <[^>]*> 40800802 	mtc0	\$0,\$1,2
+0+0024 <[^>]*> 40800803 	mtc0	\$0,\$1,3
+0+0028 <[^>]*> 40800804 	mtc0	\$0,\$1,4
+0+002c <[^>]*> 40800805 	mtc0	\$0,\$1,5
+0+0030 <[^>]*> 40800806 	mtc0	\$0,\$1,6
+0+0034 <[^>]*> 40800807 	mtc0	\$0,\$1,7
+0+0038 <[^>]*> 40801001 	mtc0	\$0,\$2,1
+0+003c <[^>]*> 40801002 	mtc0	\$0,\$2,2
+0+0040 <[^>]*> 40801003 	mtc0	\$0,\$2,3
+0+0044 <[^>]*> 40801004 	mtc0	\$0,\$2,4
+0+0048 <[^>]*> 40801005 	mtc0	\$0,\$2,5
+0+004c <[^>]*> 40801006 	mtc0	\$0,\$2,6
+0+0050 <[^>]*> 40801007 	mtc0	\$0,\$2,7
+0+0054 <[^>]*> 40801801 	mtc0	\$0,\$3,1
+0+0058 <[^>]*> 40801802 	mtc0	\$0,\$3,2
+0+005c <[^>]*> 40801803 	mtc0	\$0,\$3,3
+0+0060 <[^>]*> 40801804 	mtc0	\$0,\$3,4
+0+0064 <[^>]*> 40801805 	mtc0	\$0,\$3,5
+0+0068 <[^>]*> 40801806 	mtc0	\$0,\$3,6
+0+006c <[^>]*> 40801807 	mtc0	\$0,\$3,7
+0+0070 <[^>]*> 40802001 	mtc0	\$0,c0_contextconfig
+0+0074 <[^>]*> 40802002 	mtc0	\$0,\$4,2
+0+0078 <[^>]*> 40802003 	mtc0	\$0,\$4,3
+0+007c <[^>]*> 40802004 	mtc0	\$0,\$4,4
+0+0080 <[^>]*> 40802005 	mtc0	\$0,\$4,5
+0+0084 <[^>]*> 40802006 	mtc0	\$0,\$4,6
+0+0088 <[^>]*> 40802007 	mtc0	\$0,\$4,7
+0+008c <[^>]*> 40802801 	mtc0	\$0,c0_pagegrain
+0+0090 <[^>]*> 40802802 	mtc0	\$0,\$5,2
+0+0094 <[^>]*> 40802803 	mtc0	\$0,\$5,3
+0+0098 <[^>]*> 40802804 	mtc0	\$0,\$5,4
+0+009c <[^>]*> 40802805 	mtc0	\$0,\$5,5
+0+00a0 <[^>]*> 40802806 	mtc0	\$0,\$5,6
+0+00a4 <[^>]*> 40802807 	mtc0	\$0,\$5,7
+0+00a8 <[^>]*> 40803001 	mtc0	\$0,\$6,1
+0+00ac <[^>]*> 40803002 	mtc0	\$0,\$6,2
+0+00b0 <[^>]*> 40803003 	mtc0	\$0,\$6,3
+0+00b4 <[^>]*> 40803004 	mtc0	\$0,\$6,4
+0+00b8 <[^>]*> 40803005 	mtc0	\$0,\$6,5
+0+00bc <[^>]*> 40803006 	mtc0	\$0,\$6,6
+0+00c0 <[^>]*> 40803007 	mtc0	\$0,\$6,7
+0+00c4 <[^>]*> 40803801 	mtc0	\$0,\$7,1
+0+00c8 <[^>]*> 40803802 	mtc0	\$0,\$7,2
+0+00cc <[^>]*> 40803803 	mtc0	\$0,\$7,3
+0+00d0 <[^>]*> 40803804 	mtc0	\$0,\$7,4
+0+00d4 <[^>]*> 40803805 	mtc0	\$0,\$7,5
+0+00d8 <[^>]*> 40803806 	mtc0	\$0,\$7,6
+0+00dc <[^>]*> 40803807 	mtc0	\$0,\$7,7
+0+00e0 <[^>]*> 40804001 	mtc0	\$0,\$8,1
+0+00e4 <[^>]*> 40804002 	mtc0	\$0,\$8,2
+0+00e8 <[^>]*> 40804003 	mtc0	\$0,\$8,3
+0+00ec <[^>]*> 40804004 	mtc0	\$0,\$8,4
+0+00f0 <[^>]*> 40804005 	mtc0	\$0,\$8,5
+0+00f4 <[^>]*> 40804006 	mtc0	\$0,\$8,6
+0+00f8 <[^>]*> 40804007 	mtc0	\$0,\$8,7
+0+00fc <[^>]*> 40804801 	mtc0	\$0,\$9,1
+0+0100 <[^>]*> 40804802 	mtc0	\$0,\$9,2
+0+0104 <[^>]*> 40804803 	mtc0	\$0,\$9,3
+0+0108 <[^>]*> 40804804 	mtc0	\$0,\$9,4
+0+010c <[^>]*> 40804805 	mtc0	\$0,\$9,5
+0+0110 <[^>]*> 40804806 	mtc0	\$0,\$9,6
+0+0114 <[^>]*> 40804807 	mtc0	\$0,\$9,7
+0+0118 <[^>]*> 40805001 	mtc0	\$0,\$10,1
+0+011c <[^>]*> 40805002 	mtc0	\$0,\$10,2
+0+0120 <[^>]*> 40805003 	mtc0	\$0,\$10,3
+0+0124 <[^>]*> 40805004 	mtc0	\$0,\$10,4
+0+0128 <[^>]*> 40805005 	mtc0	\$0,\$10,5
+0+012c <[^>]*> 40805006 	mtc0	\$0,\$10,6
+0+0130 <[^>]*> 40805007 	mtc0	\$0,\$10,7
+0+0134 <[^>]*> 40805801 	mtc0	\$0,\$11,1
+0+0138 <[^>]*> 40805802 	mtc0	\$0,\$11,2
+0+013c <[^>]*> 40805803 	mtc0	\$0,\$11,3
+0+0140 <[^>]*> 40805804 	mtc0	\$0,\$11,4
+0+0144 <[^>]*> 40805805 	mtc0	\$0,\$11,5
+0+0148 <[^>]*> 40805806 	mtc0	\$0,\$11,6
+0+014c <[^>]*> 40805807 	mtc0	\$0,\$11,7
+0+0150 <[^>]*> 40806001 	mtc0	\$0,c0_intctl
+0+0154 <[^>]*> 40806002 	mtc0	\$0,c0_srsctl
+0+0158 <[^>]*> 40806003 	mtc0	\$0,c0_srsmap
+0+015c <[^>]*> 40806004 	mtc0	\$0,\$12,4
+0+0160 <[^>]*> 40806005 	mtc0	\$0,\$12,5
+0+0164 <[^>]*> 40806006 	mtc0	\$0,\$12,6
+0+0168 <[^>]*> 40806007 	mtc0	\$0,\$12,7
+0+016c <[^>]*> 40806801 	mtc0	\$0,\$13,1
+0+0170 <[^>]*> 40806802 	mtc0	\$0,\$13,2
+0+0174 <[^>]*> 40806803 	mtc0	\$0,\$13,3
+0+0178 <[^>]*> 40806804 	mtc0	\$0,\$13,4
+0+017c <[^>]*> 40806805 	mtc0	\$0,\$13,5
+0+0180 <[^>]*> 40806806 	mtc0	\$0,\$13,6
+0+0184 <[^>]*> 40806807 	mtc0	\$0,\$13,7
+0+0188 <[^>]*> 40807001 	mtc0	\$0,\$14,1
+0+018c <[^>]*> 40807002 	mtc0	\$0,\$14,2
+0+0190 <[^>]*> 40807003 	mtc0	\$0,\$14,3
+0+0194 <[^>]*> 40807004 	mtc0	\$0,\$14,4
+0+0198 <[^>]*> 40807005 	mtc0	\$0,\$14,5
+0+019c <[^>]*> 40807006 	mtc0	\$0,\$14,6
+0+01a0 <[^>]*> 40807007 	mtc0	\$0,\$14,7
+0+01a4 <[^>]*> 40807801 	mtc0	\$0,c0_ebase
+0+01a8 <[^>]*> 40807802 	mtc0	\$0,\$15,2
+0+01ac <[^>]*> 40807803 	mtc0	\$0,\$15,3
+0+01b0 <[^>]*> 40807804 	mtc0	\$0,\$15,4
+0+01b4 <[^>]*> 40807805 	mtc0	\$0,\$15,5
+0+01b8 <[^>]*> 40807806 	mtc0	\$0,\$15,6
+0+01bc <[^>]*> 40807807 	mtc0	\$0,\$15,7
+0+01c0 <[^>]*> 40808001 	mtc0	\$0,c0_config1
+0+01c4 <[^>]*> 40808002 	mtc0	\$0,c0_config2
+0+01c8 <[^>]*> 40808003 	mtc0	\$0,c0_config3
+0+01cc <[^>]*> 40808004 	mtc0	\$0,\$16,4
+0+01d0 <[^>]*> 40808005 	mtc0	\$0,\$16,5
+0+01d4 <[^>]*> 40808006 	mtc0	\$0,\$16,6
+0+01d8 <[^>]*> 40808007 	mtc0	\$0,\$16,7
+0+01dc <[^>]*> 40808801 	mtc0	\$0,\$17,1
+0+01e0 <[^>]*> 40808802 	mtc0	\$0,\$17,2
+0+01e4 <[^>]*> 40808803 	mtc0	\$0,\$17,3
+0+01e8 <[^>]*> 40808804 	mtc0	\$0,\$17,4
+0+01ec <[^>]*> 40808805 	mtc0	\$0,\$17,5
+0+01f0 <[^>]*> 40808806 	mtc0	\$0,\$17,6
+0+01f4 <[^>]*> 40808807 	mtc0	\$0,\$17,7
+0+01f8 <[^>]*> 40809001 	mtc0	\$0,c0_watchlo,1
+0+01fc <[^>]*> 40809002 	mtc0	\$0,c0_watchlo,2
+0+0200 <[^>]*> 40809003 	mtc0	\$0,c0_watchlo,3
+0+0204 <[^>]*> 40809004 	mtc0	\$0,c0_watchlo,4
+0+0208 <[^>]*> 40809005 	mtc0	\$0,c0_watchlo,5
+0+020c <[^>]*> 40809006 	mtc0	\$0,c0_watchlo,6
+0+0210 <[^>]*> 40809007 	mtc0	\$0,c0_watchlo,7
+0+0214 <[^>]*> 40809801 	mtc0	\$0,c0_watchhi,1
+0+0218 <[^>]*> 40809802 	mtc0	\$0,c0_watchhi,2
+0+021c <[^>]*> 40809803 	mtc0	\$0,c0_watchhi,3
+0+0220 <[^>]*> 40809804 	mtc0	\$0,c0_watchhi,4
+0+0224 <[^>]*> 40809805 	mtc0	\$0,c0_watchhi,5
+0+0228 <[^>]*> 40809806 	mtc0	\$0,c0_watchhi,6
+0+022c <[^>]*> 40809807 	mtc0	\$0,c0_watchhi,7
+0+0230 <[^>]*> 4080a001 	mtc0	\$0,\$20,1
+0+0234 <[^>]*> 4080a002 	mtc0	\$0,\$20,2
+0+0238 <[^>]*> 4080a003 	mtc0	\$0,\$20,3
+0+023c <[^>]*> 4080a004 	mtc0	\$0,\$20,4
+0+0240 <[^>]*> 4080a005 	mtc0	\$0,\$20,5
+0+0244 <[^>]*> 4080a006 	mtc0	\$0,\$20,6
+0+0248 <[^>]*> 4080a007 	mtc0	\$0,\$20,7
+0+024c <[^>]*> 4080a801 	mtc0	\$0,\$21,1
+0+0250 <[^>]*> 4080a802 	mtc0	\$0,\$21,2
+0+0254 <[^>]*> 4080a803 	mtc0	\$0,\$21,3
+0+0258 <[^>]*> 4080a804 	mtc0	\$0,\$21,4
+0+025c <[^>]*> 4080a805 	mtc0	\$0,\$21,5
+0+0260 <[^>]*> 4080a806 	mtc0	\$0,\$21,6
+0+0264 <[^>]*> 4080a807 	mtc0	\$0,\$21,7
+0+0268 <[^>]*> 4080b001 	mtc0	\$0,\$22,1
+0+026c <[^>]*> 4080b002 	mtc0	\$0,\$22,2
+0+0270 <[^>]*> 4080b003 	mtc0	\$0,\$22,3
+0+0274 <[^>]*> 4080b004 	mtc0	\$0,\$22,4
+0+0278 <[^>]*> 4080b005 	mtc0	\$0,\$22,5
+0+027c <[^>]*> 4080b006 	mtc0	\$0,\$22,6
+0+0280 <[^>]*> 4080b007 	mtc0	\$0,\$22,7
+0+0284 <[^>]*> 4080b801 	mtc0	\$0,c0_tracecontrol
+0+0288 <[^>]*> 4080b802 	mtc0	\$0,c0_tracecontrol2
+0+028c <[^>]*> 4080b803 	mtc0	\$0,c0_usertracedata
+0+0290 <[^>]*> 4080b804 	mtc0	\$0,c0_tracebpc
+0+0294 <[^>]*> 4080b805 	mtc0	\$0,\$23,5
+0+0298 <[^>]*> 4080b806 	mtc0	\$0,\$23,6
+0+029c <[^>]*> 4080b807 	mtc0	\$0,\$23,7
+0+02a0 <[^>]*> 4080c001 	mtc0	\$0,\$24,1
+0+02a4 <[^>]*> 4080c002 	mtc0	\$0,\$24,2
+0+02a8 <[^>]*> 4080c003 	mtc0	\$0,\$24,3
+0+02ac <[^>]*> 4080c004 	mtc0	\$0,\$24,4
+0+02b0 <[^>]*> 4080c005 	mtc0	\$0,\$24,5
+0+02b4 <[^>]*> 4080c006 	mtc0	\$0,\$24,6
+0+02b8 <[^>]*> 4080c007 	mtc0	\$0,\$24,7
+0+02bc <[^>]*> 4080c801 	mtc0	\$0,c0_perfcnt,1
+0+02c0 <[^>]*> 4080c802 	mtc0	\$0,c0_perfcnt,2
+0+02c4 <[^>]*> 4080c803 	mtc0	\$0,c0_perfcnt,3
+0+02c8 <[^>]*> 4080c804 	mtc0	\$0,c0_perfcnt,4
+0+02cc <[^>]*> 4080c805 	mtc0	\$0,c0_perfcnt,5
+0+02d0 <[^>]*> 4080c806 	mtc0	\$0,c0_perfcnt,6
+0+02d4 <[^>]*> 4080c807 	mtc0	\$0,c0_perfcnt,7
+0+02d8 <[^>]*> 4080d001 	mtc0	\$0,\$26,1
+0+02dc <[^>]*> 4080d002 	mtc0	\$0,\$26,2
+0+02e0 <[^>]*> 4080d003 	mtc0	\$0,\$26,3
+0+02e4 <[^>]*> 4080d004 	mtc0	\$0,\$26,4
+0+02e8 <[^>]*> 4080d005 	mtc0	\$0,\$26,5
+0+02ec <[^>]*> 4080d006 	mtc0	\$0,\$26,6
+0+02f0 <[^>]*> 4080d007 	mtc0	\$0,\$26,7
+0+02f4 <[^>]*> 4080d801 	mtc0	\$0,c0_cacheerr,1
+0+02f8 <[^>]*> 4080d802 	mtc0	\$0,c0_cacheerr,2
+0+02fc <[^>]*> 4080d803 	mtc0	\$0,c0_cacheerr,3
+0+0300 <[^>]*> 4080d804 	mtc0	\$0,\$27,4
+0+0304 <[^>]*> 4080d805 	mtc0	\$0,\$27,5
+0+0308 <[^>]*> 4080d806 	mtc0	\$0,\$27,6
+0+030c <[^>]*> 4080d807 	mtc0	\$0,\$27,7
+0+0310 <[^>]*> 4080e001 	mtc0	\$0,c0_datalo
+0+0314 <[^>]*> 4080e002 	mtc0	\$0,c0_taglo1
+0+0318 <[^>]*> 4080e003 	mtc0	\$0,c0_datalo1
+0+031c <[^>]*> 4080e004 	mtc0	\$0,c0_taglo2
+0+0320 <[^>]*> 4080e005 	mtc0	\$0,c0_datalo2
+0+0324 <[^>]*> 4080e006 	mtc0	\$0,c0_taglo3
+0+0328 <[^>]*> 4080e007 	mtc0	\$0,c0_datalo3
+0+032c <[^>]*> 4080e801 	mtc0	\$0,c0_datahi
+0+0330 <[^>]*> 4080e802 	mtc0	\$0,c0_taghi1
+0+0334 <[^>]*> 4080e803 	mtc0	\$0,c0_datahi1
+0+0338 <[^>]*> 4080e804 	mtc0	\$0,c0_taghi2
+0+033c <[^>]*> 4080e805 	mtc0	\$0,c0_datahi2
+0+0340 <[^>]*> 4080e806 	mtc0	\$0,c0_taghi3
+0+0344 <[^>]*> 4080e807 	mtc0	\$0,c0_datahi3
+0+0348 <[^>]*> 4080f001 	mtc0	\$0,\$30,1
+0+034c <[^>]*> 4080f002 	mtc0	\$0,\$30,2
+0+0350 <[^>]*> 4080f003 	mtc0	\$0,\$30,3
+0+0354 <[^>]*> 4080f004 	mtc0	\$0,\$30,4
+0+0358 <[^>]*> 4080f005 	mtc0	\$0,\$30,5
+0+035c <[^>]*> 4080f006 	mtc0	\$0,\$30,6
+0+0360 <[^>]*> 4080f007 	mtc0	\$0,\$30,7
+0+0364 <[^>]*> 4080f801 	mtc0	\$0,\$31,1
+0+0368 <[^>]*> 4080f802 	mtc0	\$0,\$31,2
+0+036c <[^>]*> 4080f803 	mtc0	\$0,\$31,3
+0+0370 <[^>]*> 4080f804 	mtc0	\$0,\$31,4
+0+0374 <[^>]*> 4080f805 	mtc0	\$0,\$31,5
+0+0378 <[^>]*> 4080f806 	mtc0	\$0,\$31,6
+0+037c <[^>]*> 4080f807 	mtc0	\$0,\$31,7
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/cp0sel-names-mips64.d b/gas/testsuite/gas/mips/cp0sel-names-mips64.d
new file mode 100644
index 0000000..6073344
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp0sel-names-mips64.d
@@ -0,0 +1,235 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa32 -M gpr-names=numeric,cp0-names=mips64
+#name: MIPS CP0 with sel register disassembly (mips64)
+#as: -march=mips32
+#source: cp0sel-names.s
+
+# Check objdump's handling of -M cp0-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 40800001 	mtc0	\$0,\$0,1
+0+0004 <[^>]*> 40800002 	mtc0	\$0,\$0,2
+0+0008 <[^>]*> 40800003 	mtc0	\$0,\$0,3
+0+000c <[^>]*> 40800004 	mtc0	\$0,\$0,4
+0+0010 <[^>]*> 40800005 	mtc0	\$0,\$0,5
+0+0014 <[^>]*> 40800006 	mtc0	\$0,\$0,6
+0+0018 <[^>]*> 40800007 	mtc0	\$0,\$0,7
+0+001c <[^>]*> 40800801 	mtc0	\$0,\$1,1
+0+0020 <[^>]*> 40800802 	mtc0	\$0,\$1,2
+0+0024 <[^>]*> 40800803 	mtc0	\$0,\$1,3
+0+0028 <[^>]*> 40800804 	mtc0	\$0,\$1,4
+0+002c <[^>]*> 40800805 	mtc0	\$0,\$1,5
+0+0030 <[^>]*> 40800806 	mtc0	\$0,\$1,6
+0+0034 <[^>]*> 40800807 	mtc0	\$0,\$1,7
+0+0038 <[^>]*> 40801001 	mtc0	\$0,\$2,1
+0+003c <[^>]*> 40801002 	mtc0	\$0,\$2,2
+0+0040 <[^>]*> 40801003 	mtc0	\$0,\$2,3
+0+0044 <[^>]*> 40801004 	mtc0	\$0,\$2,4
+0+0048 <[^>]*> 40801005 	mtc0	\$0,\$2,5
+0+004c <[^>]*> 40801006 	mtc0	\$0,\$2,6
+0+0050 <[^>]*> 40801007 	mtc0	\$0,\$2,7
+0+0054 <[^>]*> 40801801 	mtc0	\$0,\$3,1
+0+0058 <[^>]*> 40801802 	mtc0	\$0,\$3,2
+0+005c <[^>]*> 40801803 	mtc0	\$0,\$3,3
+0+0060 <[^>]*> 40801804 	mtc0	\$0,\$3,4
+0+0064 <[^>]*> 40801805 	mtc0	\$0,\$3,5
+0+0068 <[^>]*> 40801806 	mtc0	\$0,\$3,6
+0+006c <[^>]*> 40801807 	mtc0	\$0,\$3,7
+0+0070 <[^>]*> 40802001 	mtc0	\$0,\$4,1
+0+0074 <[^>]*> 40802002 	mtc0	\$0,\$4,2
+0+0078 <[^>]*> 40802003 	mtc0	\$0,\$4,3
+0+007c <[^>]*> 40802004 	mtc0	\$0,\$4,4
+0+0080 <[^>]*> 40802005 	mtc0	\$0,\$4,5
+0+0084 <[^>]*> 40802006 	mtc0	\$0,\$4,6
+0+0088 <[^>]*> 40802007 	mtc0	\$0,\$4,7
+0+008c <[^>]*> 40802801 	mtc0	\$0,\$5,1
+0+0090 <[^>]*> 40802802 	mtc0	\$0,\$5,2
+0+0094 <[^>]*> 40802803 	mtc0	\$0,\$5,3
+0+0098 <[^>]*> 40802804 	mtc0	\$0,\$5,4
+0+009c <[^>]*> 40802805 	mtc0	\$0,\$5,5
+0+00a0 <[^>]*> 40802806 	mtc0	\$0,\$5,6
+0+00a4 <[^>]*> 40802807 	mtc0	\$0,\$5,7
+0+00a8 <[^>]*> 40803001 	mtc0	\$0,\$6,1
+0+00ac <[^>]*> 40803002 	mtc0	\$0,\$6,2
+0+00b0 <[^>]*> 40803003 	mtc0	\$0,\$6,3
+0+00b4 <[^>]*> 40803004 	mtc0	\$0,\$6,4
+0+00b8 <[^>]*> 40803005 	mtc0	\$0,\$6,5
+0+00bc <[^>]*> 40803006 	mtc0	\$0,\$6,6
+0+00c0 <[^>]*> 40803007 	mtc0	\$0,\$6,7
+0+00c4 <[^>]*> 40803801 	mtc0	\$0,\$7,1
+0+00c8 <[^>]*> 40803802 	mtc0	\$0,\$7,2
+0+00cc <[^>]*> 40803803 	mtc0	\$0,\$7,3
+0+00d0 <[^>]*> 40803804 	mtc0	\$0,\$7,4
+0+00d4 <[^>]*> 40803805 	mtc0	\$0,\$7,5
+0+00d8 <[^>]*> 40803806 	mtc0	\$0,\$7,6
+0+00dc <[^>]*> 40803807 	mtc0	\$0,\$7,7
+0+00e0 <[^>]*> 40804001 	mtc0	\$0,\$8,1
+0+00e4 <[^>]*> 40804002 	mtc0	\$0,\$8,2
+0+00e8 <[^>]*> 40804003 	mtc0	\$0,\$8,3
+0+00ec <[^>]*> 40804004 	mtc0	\$0,\$8,4
+0+00f0 <[^>]*> 40804005 	mtc0	\$0,\$8,5
+0+00f4 <[^>]*> 40804006 	mtc0	\$0,\$8,6
+0+00f8 <[^>]*> 40804007 	mtc0	\$0,\$8,7
+0+00fc <[^>]*> 40804801 	mtc0	\$0,\$9,1
+0+0100 <[^>]*> 40804802 	mtc0	\$0,\$9,2
+0+0104 <[^>]*> 40804803 	mtc0	\$0,\$9,3
+0+0108 <[^>]*> 40804804 	mtc0	\$0,\$9,4
+0+010c <[^>]*> 40804805 	mtc0	\$0,\$9,5
+0+0110 <[^>]*> 40804806 	mtc0	\$0,\$9,6
+0+0114 <[^>]*> 40804807 	mtc0	\$0,\$9,7
+0+0118 <[^>]*> 40805001 	mtc0	\$0,\$10,1
+0+011c <[^>]*> 40805002 	mtc0	\$0,\$10,2
+0+0120 <[^>]*> 40805003 	mtc0	\$0,\$10,3
+0+0124 <[^>]*> 40805004 	mtc0	\$0,\$10,4
+0+0128 <[^>]*> 40805005 	mtc0	\$0,\$10,5
+0+012c <[^>]*> 40805006 	mtc0	\$0,\$10,6
+0+0130 <[^>]*> 40805007 	mtc0	\$0,\$10,7
+0+0134 <[^>]*> 40805801 	mtc0	\$0,\$11,1
+0+0138 <[^>]*> 40805802 	mtc0	\$0,\$11,2
+0+013c <[^>]*> 40805803 	mtc0	\$0,\$11,3
+0+0140 <[^>]*> 40805804 	mtc0	\$0,\$11,4
+0+0144 <[^>]*> 40805805 	mtc0	\$0,\$11,5
+0+0148 <[^>]*> 40805806 	mtc0	\$0,\$11,6
+0+014c <[^>]*> 40805807 	mtc0	\$0,\$11,7
+0+0150 <[^>]*> 40806001 	mtc0	\$0,\$12,1
+0+0154 <[^>]*> 40806002 	mtc0	\$0,\$12,2
+0+0158 <[^>]*> 40806003 	mtc0	\$0,\$12,3
+0+015c <[^>]*> 40806004 	mtc0	\$0,\$12,4
+0+0160 <[^>]*> 40806005 	mtc0	\$0,\$12,5
+0+0164 <[^>]*> 40806006 	mtc0	\$0,\$12,6
+0+0168 <[^>]*> 40806007 	mtc0	\$0,\$12,7
+0+016c <[^>]*> 40806801 	mtc0	\$0,\$13,1
+0+0170 <[^>]*> 40806802 	mtc0	\$0,\$13,2
+0+0174 <[^>]*> 40806803 	mtc0	\$0,\$13,3
+0+0178 <[^>]*> 40806804 	mtc0	\$0,\$13,4
+0+017c <[^>]*> 40806805 	mtc0	\$0,\$13,5
+0+0180 <[^>]*> 40806806 	mtc0	\$0,\$13,6
+0+0184 <[^>]*> 40806807 	mtc0	\$0,\$13,7
+0+0188 <[^>]*> 40807001 	mtc0	\$0,\$14,1
+0+018c <[^>]*> 40807002 	mtc0	\$0,\$14,2
+0+0190 <[^>]*> 40807003 	mtc0	\$0,\$14,3
+0+0194 <[^>]*> 40807004 	mtc0	\$0,\$14,4
+0+0198 <[^>]*> 40807005 	mtc0	\$0,\$14,5
+0+019c <[^>]*> 40807006 	mtc0	\$0,\$14,6
+0+01a0 <[^>]*> 40807007 	mtc0	\$0,\$14,7
+0+01a4 <[^>]*> 40807801 	mtc0	\$0,\$15,1
+0+01a8 <[^>]*> 40807802 	mtc0	\$0,\$15,2
+0+01ac <[^>]*> 40807803 	mtc0	\$0,\$15,3
+0+01b0 <[^>]*> 40807804 	mtc0	\$0,\$15,4
+0+01b4 <[^>]*> 40807805 	mtc0	\$0,\$15,5
+0+01b8 <[^>]*> 40807806 	mtc0	\$0,\$15,6
+0+01bc <[^>]*> 40807807 	mtc0	\$0,\$15,7
+0+01c0 <[^>]*> 40808001 	mtc0	\$0,c0_config1
+0+01c4 <[^>]*> 40808002 	mtc0	\$0,c0_config2
+0+01c8 <[^>]*> 40808003 	mtc0	\$0,c0_config3
+0+01cc <[^>]*> 40808004 	mtc0	\$0,\$16,4
+0+01d0 <[^>]*> 40808005 	mtc0	\$0,\$16,5
+0+01d4 <[^>]*> 40808006 	mtc0	\$0,\$16,6
+0+01d8 <[^>]*> 40808007 	mtc0	\$0,\$16,7
+0+01dc <[^>]*> 40808801 	mtc0	\$0,\$17,1
+0+01e0 <[^>]*> 40808802 	mtc0	\$0,\$17,2
+0+01e4 <[^>]*> 40808803 	mtc0	\$0,\$17,3
+0+01e8 <[^>]*> 40808804 	mtc0	\$0,\$17,4
+0+01ec <[^>]*> 40808805 	mtc0	\$0,\$17,5
+0+01f0 <[^>]*> 40808806 	mtc0	\$0,\$17,6
+0+01f4 <[^>]*> 40808807 	mtc0	\$0,\$17,7
+0+01f8 <[^>]*> 40809001 	mtc0	\$0,c0_watchlo,1
+0+01fc <[^>]*> 40809002 	mtc0	\$0,c0_watchlo,2
+0+0200 <[^>]*> 40809003 	mtc0	\$0,c0_watchlo,3
+0+0204 <[^>]*> 40809004 	mtc0	\$0,c0_watchlo,4
+0+0208 <[^>]*> 40809005 	mtc0	\$0,c0_watchlo,5
+0+020c <[^>]*> 40809006 	mtc0	\$0,c0_watchlo,6
+0+0210 <[^>]*> 40809007 	mtc0	\$0,c0_watchlo,7
+0+0214 <[^>]*> 40809801 	mtc0	\$0,c0_watchhi,1
+0+0218 <[^>]*> 40809802 	mtc0	\$0,c0_watchhi,2
+0+021c <[^>]*> 40809803 	mtc0	\$0,c0_watchhi,3
+0+0220 <[^>]*> 40809804 	mtc0	\$0,c0_watchhi,4
+0+0224 <[^>]*> 40809805 	mtc0	\$0,c0_watchhi,5
+0+0228 <[^>]*> 40809806 	mtc0	\$0,c0_watchhi,6
+0+022c <[^>]*> 40809807 	mtc0	\$0,c0_watchhi,7
+0+0230 <[^>]*> 4080a001 	mtc0	\$0,\$20,1
+0+0234 <[^>]*> 4080a002 	mtc0	\$0,\$20,2
+0+0238 <[^>]*> 4080a003 	mtc0	\$0,\$20,3
+0+023c <[^>]*> 4080a004 	mtc0	\$0,\$20,4
+0+0240 <[^>]*> 4080a005 	mtc0	\$0,\$20,5
+0+0244 <[^>]*> 4080a006 	mtc0	\$0,\$20,6
+0+0248 <[^>]*> 4080a007 	mtc0	\$0,\$20,7
+0+024c <[^>]*> 4080a801 	mtc0	\$0,\$21,1
+0+0250 <[^>]*> 4080a802 	mtc0	\$0,\$21,2
+0+0254 <[^>]*> 4080a803 	mtc0	\$0,\$21,3
+0+0258 <[^>]*> 4080a804 	mtc0	\$0,\$21,4
+0+025c <[^>]*> 4080a805 	mtc0	\$0,\$21,5
+0+0260 <[^>]*> 4080a806 	mtc0	\$0,\$21,6
+0+0264 <[^>]*> 4080a807 	mtc0	\$0,\$21,7
+0+0268 <[^>]*> 4080b001 	mtc0	\$0,\$22,1
+0+026c <[^>]*> 4080b002 	mtc0	\$0,\$22,2
+0+0270 <[^>]*> 4080b003 	mtc0	\$0,\$22,3
+0+0274 <[^>]*> 4080b004 	mtc0	\$0,\$22,4
+0+0278 <[^>]*> 4080b005 	mtc0	\$0,\$22,5
+0+027c <[^>]*> 4080b006 	mtc0	\$0,\$22,6
+0+0280 <[^>]*> 4080b007 	mtc0	\$0,\$22,7
+0+0284 <[^>]*> 4080b801 	mtc0	\$0,\$23,1
+0+0288 <[^>]*> 4080b802 	mtc0	\$0,\$23,2
+0+028c <[^>]*> 4080b803 	mtc0	\$0,\$23,3
+0+0290 <[^>]*> 4080b804 	mtc0	\$0,\$23,4
+0+0294 <[^>]*> 4080b805 	mtc0	\$0,\$23,5
+0+0298 <[^>]*> 4080b806 	mtc0	\$0,\$23,6
+0+029c <[^>]*> 4080b807 	mtc0	\$0,\$23,7
+0+02a0 <[^>]*> 4080c001 	mtc0	\$0,\$24,1
+0+02a4 <[^>]*> 4080c002 	mtc0	\$0,\$24,2
+0+02a8 <[^>]*> 4080c003 	mtc0	\$0,\$24,3
+0+02ac <[^>]*> 4080c004 	mtc0	\$0,\$24,4
+0+02b0 <[^>]*> 4080c005 	mtc0	\$0,\$24,5
+0+02b4 <[^>]*> 4080c006 	mtc0	\$0,\$24,6
+0+02b8 <[^>]*> 4080c007 	mtc0	\$0,\$24,7
+0+02bc <[^>]*> 4080c801 	mtc0	\$0,c0_perfcnt,1
+0+02c0 <[^>]*> 4080c802 	mtc0	\$0,c0_perfcnt,2
+0+02c4 <[^>]*> 4080c803 	mtc0	\$0,c0_perfcnt,3
+0+02c8 <[^>]*> 4080c804 	mtc0	\$0,c0_perfcnt,4
+0+02cc <[^>]*> 4080c805 	mtc0	\$0,c0_perfcnt,5
+0+02d0 <[^>]*> 4080c806 	mtc0	\$0,c0_perfcnt,6
+0+02d4 <[^>]*> 4080c807 	mtc0	\$0,c0_perfcnt,7
+0+02d8 <[^>]*> 4080d001 	mtc0	\$0,\$26,1
+0+02dc <[^>]*> 4080d002 	mtc0	\$0,\$26,2
+0+02e0 <[^>]*> 4080d003 	mtc0	\$0,\$26,3
+0+02e4 <[^>]*> 4080d004 	mtc0	\$0,\$26,4
+0+02e8 <[^>]*> 4080d005 	mtc0	\$0,\$26,5
+0+02ec <[^>]*> 4080d006 	mtc0	\$0,\$26,6
+0+02f0 <[^>]*> 4080d007 	mtc0	\$0,\$26,7
+0+02f4 <[^>]*> 4080d801 	mtc0	\$0,c0_cacheerr,1
+0+02f8 <[^>]*> 4080d802 	mtc0	\$0,c0_cacheerr,2
+0+02fc <[^>]*> 4080d803 	mtc0	\$0,c0_cacheerr,3
+0+0300 <[^>]*> 4080d804 	mtc0	\$0,\$27,4
+0+0304 <[^>]*> 4080d805 	mtc0	\$0,\$27,5
+0+0308 <[^>]*> 4080d806 	mtc0	\$0,\$27,6
+0+030c <[^>]*> 4080d807 	mtc0	\$0,\$27,7
+0+0310 <[^>]*> 4080e001 	mtc0	\$0,c0_datalo
+0+0314 <[^>]*> 4080e002 	mtc0	\$0,\$28,2
+0+0318 <[^>]*> 4080e003 	mtc0	\$0,\$28,3
+0+031c <[^>]*> 4080e004 	mtc0	\$0,\$28,4
+0+0320 <[^>]*> 4080e005 	mtc0	\$0,\$28,5
+0+0324 <[^>]*> 4080e006 	mtc0	\$0,\$28,6
+0+0328 <[^>]*> 4080e007 	mtc0	\$0,\$28,7
+0+032c <[^>]*> 4080e801 	mtc0	\$0,c0_datahi
+0+0330 <[^>]*> 4080e802 	mtc0	\$0,\$29,2
+0+0334 <[^>]*> 4080e803 	mtc0	\$0,\$29,3
+0+0338 <[^>]*> 4080e804 	mtc0	\$0,\$29,4
+0+033c <[^>]*> 4080e805 	mtc0	\$0,\$29,5
+0+0340 <[^>]*> 4080e806 	mtc0	\$0,\$29,6
+0+0344 <[^>]*> 4080e807 	mtc0	\$0,\$29,7
+0+0348 <[^>]*> 4080f001 	mtc0	\$0,\$30,1
+0+034c <[^>]*> 4080f002 	mtc0	\$0,\$30,2
+0+0350 <[^>]*> 4080f003 	mtc0	\$0,\$30,3
+0+0354 <[^>]*> 4080f004 	mtc0	\$0,\$30,4
+0+0358 <[^>]*> 4080f005 	mtc0	\$0,\$30,5
+0+035c <[^>]*> 4080f006 	mtc0	\$0,\$30,6
+0+0360 <[^>]*> 4080f007 	mtc0	\$0,\$30,7
+0+0364 <[^>]*> 4080f801 	mtc0	\$0,\$31,1
+0+0368 <[^>]*> 4080f802 	mtc0	\$0,\$31,2
+0+036c <[^>]*> 4080f803 	mtc0	\$0,\$31,3
+0+0370 <[^>]*> 4080f804 	mtc0	\$0,\$31,4
+0+0374 <[^>]*> 4080f805 	mtc0	\$0,\$31,5
+0+0378 <[^>]*> 4080f806 	mtc0	\$0,\$31,6
+0+037c <[^>]*> 4080f807 	mtc0	\$0,\$31,7
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/cp0sel-names-numeric.d b/gas/testsuite/gas/mips/cp0sel-names-numeric.d
new file mode 100644
index 0000000..0886cff
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp0sel-names-numeric.d
@@ -0,0 +1,235 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa32 -M gpr-names=numeric,cp0-names=numeric
+#name: MIPS CP0 with sel register disassembly (numeric)
+#as: -march=mips32
+#source: cp0sel-names.s
+
+# Check objdump's handling of -M cp0-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 40800001 	mtc0	\$0,\$0,1
+0+0004 <[^>]*> 40800002 	mtc0	\$0,\$0,2
+0+0008 <[^>]*> 40800003 	mtc0	\$0,\$0,3
+0+000c <[^>]*> 40800004 	mtc0	\$0,\$0,4
+0+0010 <[^>]*> 40800005 	mtc0	\$0,\$0,5
+0+0014 <[^>]*> 40800006 	mtc0	\$0,\$0,6
+0+0018 <[^>]*> 40800007 	mtc0	\$0,\$0,7
+0+001c <[^>]*> 40800801 	mtc0	\$0,\$1,1
+0+0020 <[^>]*> 40800802 	mtc0	\$0,\$1,2
+0+0024 <[^>]*> 40800803 	mtc0	\$0,\$1,3
+0+0028 <[^>]*> 40800804 	mtc0	\$0,\$1,4
+0+002c <[^>]*> 40800805 	mtc0	\$0,\$1,5
+0+0030 <[^>]*> 40800806 	mtc0	\$0,\$1,6
+0+0034 <[^>]*> 40800807 	mtc0	\$0,\$1,7
+0+0038 <[^>]*> 40801001 	mtc0	\$0,\$2,1
+0+003c <[^>]*> 40801002 	mtc0	\$0,\$2,2
+0+0040 <[^>]*> 40801003 	mtc0	\$0,\$2,3
+0+0044 <[^>]*> 40801004 	mtc0	\$0,\$2,4
+0+0048 <[^>]*> 40801005 	mtc0	\$0,\$2,5
+0+004c <[^>]*> 40801006 	mtc0	\$0,\$2,6
+0+0050 <[^>]*> 40801007 	mtc0	\$0,\$2,7
+0+0054 <[^>]*> 40801801 	mtc0	\$0,\$3,1
+0+0058 <[^>]*> 40801802 	mtc0	\$0,\$3,2
+0+005c <[^>]*> 40801803 	mtc0	\$0,\$3,3
+0+0060 <[^>]*> 40801804 	mtc0	\$0,\$3,4
+0+0064 <[^>]*> 40801805 	mtc0	\$0,\$3,5
+0+0068 <[^>]*> 40801806 	mtc0	\$0,\$3,6
+0+006c <[^>]*> 40801807 	mtc0	\$0,\$3,7
+0+0070 <[^>]*> 40802001 	mtc0	\$0,\$4,1
+0+0074 <[^>]*> 40802002 	mtc0	\$0,\$4,2
+0+0078 <[^>]*> 40802003 	mtc0	\$0,\$4,3
+0+007c <[^>]*> 40802004 	mtc0	\$0,\$4,4
+0+0080 <[^>]*> 40802005 	mtc0	\$0,\$4,5
+0+0084 <[^>]*> 40802006 	mtc0	\$0,\$4,6
+0+0088 <[^>]*> 40802007 	mtc0	\$0,\$4,7
+0+008c <[^>]*> 40802801 	mtc0	\$0,\$5,1
+0+0090 <[^>]*> 40802802 	mtc0	\$0,\$5,2
+0+0094 <[^>]*> 40802803 	mtc0	\$0,\$5,3
+0+0098 <[^>]*> 40802804 	mtc0	\$0,\$5,4
+0+009c <[^>]*> 40802805 	mtc0	\$0,\$5,5
+0+00a0 <[^>]*> 40802806 	mtc0	\$0,\$5,6
+0+00a4 <[^>]*> 40802807 	mtc0	\$0,\$5,7
+0+00a8 <[^>]*> 40803001 	mtc0	\$0,\$6,1
+0+00ac <[^>]*> 40803002 	mtc0	\$0,\$6,2
+0+00b0 <[^>]*> 40803003 	mtc0	\$0,\$6,3
+0+00b4 <[^>]*> 40803004 	mtc0	\$0,\$6,4
+0+00b8 <[^>]*> 40803005 	mtc0	\$0,\$6,5
+0+00bc <[^>]*> 40803006 	mtc0	\$0,\$6,6
+0+00c0 <[^>]*> 40803007 	mtc0	\$0,\$6,7
+0+00c4 <[^>]*> 40803801 	mtc0	\$0,\$7,1
+0+00c8 <[^>]*> 40803802 	mtc0	\$0,\$7,2
+0+00cc <[^>]*> 40803803 	mtc0	\$0,\$7,3
+0+00d0 <[^>]*> 40803804 	mtc0	\$0,\$7,4
+0+00d4 <[^>]*> 40803805 	mtc0	\$0,\$7,5
+0+00d8 <[^>]*> 40803806 	mtc0	\$0,\$7,6
+0+00dc <[^>]*> 40803807 	mtc0	\$0,\$7,7
+0+00e0 <[^>]*> 40804001 	mtc0	\$0,\$8,1
+0+00e4 <[^>]*> 40804002 	mtc0	\$0,\$8,2
+0+00e8 <[^>]*> 40804003 	mtc0	\$0,\$8,3
+0+00ec <[^>]*> 40804004 	mtc0	\$0,\$8,4
+0+00f0 <[^>]*> 40804005 	mtc0	\$0,\$8,5
+0+00f4 <[^>]*> 40804006 	mtc0	\$0,\$8,6
+0+00f8 <[^>]*> 40804007 	mtc0	\$0,\$8,7
+0+00fc <[^>]*> 40804801 	mtc0	\$0,\$9,1
+0+0100 <[^>]*> 40804802 	mtc0	\$0,\$9,2
+0+0104 <[^>]*> 40804803 	mtc0	\$0,\$9,3
+0+0108 <[^>]*> 40804804 	mtc0	\$0,\$9,4
+0+010c <[^>]*> 40804805 	mtc0	\$0,\$9,5
+0+0110 <[^>]*> 40804806 	mtc0	\$0,\$9,6
+0+0114 <[^>]*> 40804807 	mtc0	\$0,\$9,7
+0+0118 <[^>]*> 40805001 	mtc0	\$0,\$10,1
+0+011c <[^>]*> 40805002 	mtc0	\$0,\$10,2
+0+0120 <[^>]*> 40805003 	mtc0	\$0,\$10,3
+0+0124 <[^>]*> 40805004 	mtc0	\$0,\$10,4
+0+0128 <[^>]*> 40805005 	mtc0	\$0,\$10,5
+0+012c <[^>]*> 40805006 	mtc0	\$0,\$10,6
+0+0130 <[^>]*> 40805007 	mtc0	\$0,\$10,7
+0+0134 <[^>]*> 40805801 	mtc0	\$0,\$11,1
+0+0138 <[^>]*> 40805802 	mtc0	\$0,\$11,2
+0+013c <[^>]*> 40805803 	mtc0	\$0,\$11,3
+0+0140 <[^>]*> 40805804 	mtc0	\$0,\$11,4
+0+0144 <[^>]*> 40805805 	mtc0	\$0,\$11,5
+0+0148 <[^>]*> 40805806 	mtc0	\$0,\$11,6
+0+014c <[^>]*> 40805807 	mtc0	\$0,\$11,7
+0+0150 <[^>]*> 40806001 	mtc0	\$0,\$12,1
+0+0154 <[^>]*> 40806002 	mtc0	\$0,\$12,2
+0+0158 <[^>]*> 40806003 	mtc0	\$0,\$12,3
+0+015c <[^>]*> 40806004 	mtc0	\$0,\$12,4
+0+0160 <[^>]*> 40806005 	mtc0	\$0,\$12,5
+0+0164 <[^>]*> 40806006 	mtc0	\$0,\$12,6
+0+0168 <[^>]*> 40806007 	mtc0	\$0,\$12,7
+0+016c <[^>]*> 40806801 	mtc0	\$0,\$13,1
+0+0170 <[^>]*> 40806802 	mtc0	\$0,\$13,2
+0+0174 <[^>]*> 40806803 	mtc0	\$0,\$13,3
+0+0178 <[^>]*> 40806804 	mtc0	\$0,\$13,4
+0+017c <[^>]*> 40806805 	mtc0	\$0,\$13,5
+0+0180 <[^>]*> 40806806 	mtc0	\$0,\$13,6
+0+0184 <[^>]*> 40806807 	mtc0	\$0,\$13,7
+0+0188 <[^>]*> 40807001 	mtc0	\$0,\$14,1
+0+018c <[^>]*> 40807002 	mtc0	\$0,\$14,2
+0+0190 <[^>]*> 40807003 	mtc0	\$0,\$14,3
+0+0194 <[^>]*> 40807004 	mtc0	\$0,\$14,4
+0+0198 <[^>]*> 40807005 	mtc0	\$0,\$14,5
+0+019c <[^>]*> 40807006 	mtc0	\$0,\$14,6
+0+01a0 <[^>]*> 40807007 	mtc0	\$0,\$14,7
+0+01a4 <[^>]*> 40807801 	mtc0	\$0,\$15,1
+0+01a8 <[^>]*> 40807802 	mtc0	\$0,\$15,2
+0+01ac <[^>]*> 40807803 	mtc0	\$0,\$15,3
+0+01b0 <[^>]*> 40807804 	mtc0	\$0,\$15,4
+0+01b4 <[^>]*> 40807805 	mtc0	\$0,\$15,5
+0+01b8 <[^>]*> 40807806 	mtc0	\$0,\$15,6
+0+01bc <[^>]*> 40807807 	mtc0	\$0,\$15,7
+0+01c0 <[^>]*> 40808001 	mtc0	\$0,\$16,1
+0+01c4 <[^>]*> 40808002 	mtc0	\$0,\$16,2
+0+01c8 <[^>]*> 40808003 	mtc0	\$0,\$16,3
+0+01cc <[^>]*> 40808004 	mtc0	\$0,\$16,4
+0+01d0 <[^>]*> 40808005 	mtc0	\$0,\$16,5
+0+01d4 <[^>]*> 40808006 	mtc0	\$0,\$16,6
+0+01d8 <[^>]*> 40808007 	mtc0	\$0,\$16,7
+0+01dc <[^>]*> 40808801 	mtc0	\$0,\$17,1
+0+01e0 <[^>]*> 40808802 	mtc0	\$0,\$17,2
+0+01e4 <[^>]*> 40808803 	mtc0	\$0,\$17,3
+0+01e8 <[^>]*> 40808804 	mtc0	\$0,\$17,4
+0+01ec <[^>]*> 40808805 	mtc0	\$0,\$17,5
+0+01f0 <[^>]*> 40808806 	mtc0	\$0,\$17,6
+0+01f4 <[^>]*> 40808807 	mtc0	\$0,\$17,7
+0+01f8 <[^>]*> 40809001 	mtc0	\$0,\$18,1
+0+01fc <[^>]*> 40809002 	mtc0	\$0,\$18,2
+0+0200 <[^>]*> 40809003 	mtc0	\$0,\$18,3
+0+0204 <[^>]*> 40809004 	mtc0	\$0,\$18,4
+0+0208 <[^>]*> 40809005 	mtc0	\$0,\$18,5
+0+020c <[^>]*> 40809006 	mtc0	\$0,\$18,6
+0+0210 <[^>]*> 40809007 	mtc0	\$0,\$18,7
+0+0214 <[^>]*> 40809801 	mtc0	\$0,\$19,1
+0+0218 <[^>]*> 40809802 	mtc0	\$0,\$19,2
+0+021c <[^>]*> 40809803 	mtc0	\$0,\$19,3
+0+0220 <[^>]*> 40809804 	mtc0	\$0,\$19,4
+0+0224 <[^>]*> 40809805 	mtc0	\$0,\$19,5
+0+0228 <[^>]*> 40809806 	mtc0	\$0,\$19,6
+0+022c <[^>]*> 40809807 	mtc0	\$0,\$19,7
+0+0230 <[^>]*> 4080a001 	mtc0	\$0,\$20,1
+0+0234 <[^>]*> 4080a002 	mtc0	\$0,\$20,2
+0+0238 <[^>]*> 4080a003 	mtc0	\$0,\$20,3
+0+023c <[^>]*> 4080a004 	mtc0	\$0,\$20,4
+0+0240 <[^>]*> 4080a005 	mtc0	\$0,\$20,5
+0+0244 <[^>]*> 4080a006 	mtc0	\$0,\$20,6
+0+0248 <[^>]*> 4080a007 	mtc0	\$0,\$20,7
+0+024c <[^>]*> 4080a801 	mtc0	\$0,\$21,1
+0+0250 <[^>]*> 4080a802 	mtc0	\$0,\$21,2
+0+0254 <[^>]*> 4080a803 	mtc0	\$0,\$21,3
+0+0258 <[^>]*> 4080a804 	mtc0	\$0,\$21,4
+0+025c <[^>]*> 4080a805 	mtc0	\$0,\$21,5
+0+0260 <[^>]*> 4080a806 	mtc0	\$0,\$21,6
+0+0264 <[^>]*> 4080a807 	mtc0	\$0,\$21,7
+0+0268 <[^>]*> 4080b001 	mtc0	\$0,\$22,1
+0+026c <[^>]*> 4080b002 	mtc0	\$0,\$22,2
+0+0270 <[^>]*> 4080b003 	mtc0	\$0,\$22,3
+0+0274 <[^>]*> 4080b004 	mtc0	\$0,\$22,4
+0+0278 <[^>]*> 4080b005 	mtc0	\$0,\$22,5
+0+027c <[^>]*> 4080b006 	mtc0	\$0,\$22,6
+0+0280 <[^>]*> 4080b007 	mtc0	\$0,\$22,7
+0+0284 <[^>]*> 4080b801 	mtc0	\$0,\$23,1
+0+0288 <[^>]*> 4080b802 	mtc0	\$0,\$23,2
+0+028c <[^>]*> 4080b803 	mtc0	\$0,\$23,3
+0+0290 <[^>]*> 4080b804 	mtc0	\$0,\$23,4
+0+0294 <[^>]*> 4080b805 	mtc0	\$0,\$23,5
+0+0298 <[^>]*> 4080b806 	mtc0	\$0,\$23,6
+0+029c <[^>]*> 4080b807 	mtc0	\$0,\$23,7
+0+02a0 <[^>]*> 4080c001 	mtc0	\$0,\$24,1
+0+02a4 <[^>]*> 4080c002 	mtc0	\$0,\$24,2
+0+02a8 <[^>]*> 4080c003 	mtc0	\$0,\$24,3
+0+02ac <[^>]*> 4080c004 	mtc0	\$0,\$24,4
+0+02b0 <[^>]*> 4080c005 	mtc0	\$0,\$24,5
+0+02b4 <[^>]*> 4080c006 	mtc0	\$0,\$24,6
+0+02b8 <[^>]*> 4080c007 	mtc0	\$0,\$24,7
+0+02bc <[^>]*> 4080c801 	mtc0	\$0,\$25,1
+0+02c0 <[^>]*> 4080c802 	mtc0	\$0,\$25,2
+0+02c4 <[^>]*> 4080c803 	mtc0	\$0,\$25,3
+0+02c8 <[^>]*> 4080c804 	mtc0	\$0,\$25,4
+0+02cc <[^>]*> 4080c805 	mtc0	\$0,\$25,5
+0+02d0 <[^>]*> 4080c806 	mtc0	\$0,\$25,6
+0+02d4 <[^>]*> 4080c807 	mtc0	\$0,\$25,7
+0+02d8 <[^>]*> 4080d001 	mtc0	\$0,\$26,1
+0+02dc <[^>]*> 4080d002 	mtc0	\$0,\$26,2
+0+02e0 <[^>]*> 4080d003 	mtc0	\$0,\$26,3
+0+02e4 <[^>]*> 4080d004 	mtc0	\$0,\$26,4
+0+02e8 <[^>]*> 4080d005 	mtc0	\$0,\$26,5
+0+02ec <[^>]*> 4080d006 	mtc0	\$0,\$26,6
+0+02f0 <[^>]*> 4080d007 	mtc0	\$0,\$26,7
+0+02f4 <[^>]*> 4080d801 	mtc0	\$0,\$27,1
+0+02f8 <[^>]*> 4080d802 	mtc0	\$0,\$27,2
+0+02fc <[^>]*> 4080d803 	mtc0	\$0,\$27,3
+0+0300 <[^>]*> 4080d804 	mtc0	\$0,\$27,4
+0+0304 <[^>]*> 4080d805 	mtc0	\$0,\$27,5
+0+0308 <[^>]*> 4080d806 	mtc0	\$0,\$27,6
+0+030c <[^>]*> 4080d807 	mtc0	\$0,\$27,7
+0+0310 <[^>]*> 4080e001 	mtc0	\$0,\$28,1
+0+0314 <[^>]*> 4080e002 	mtc0	\$0,\$28,2
+0+0318 <[^>]*> 4080e003 	mtc0	\$0,\$28,3
+0+031c <[^>]*> 4080e004 	mtc0	\$0,\$28,4
+0+0320 <[^>]*> 4080e005 	mtc0	\$0,\$28,5
+0+0324 <[^>]*> 4080e006 	mtc0	\$0,\$28,6
+0+0328 <[^>]*> 4080e007 	mtc0	\$0,\$28,7
+0+032c <[^>]*> 4080e801 	mtc0	\$0,\$29,1
+0+0330 <[^>]*> 4080e802 	mtc0	\$0,\$29,2
+0+0334 <[^>]*> 4080e803 	mtc0	\$0,\$29,3
+0+0338 <[^>]*> 4080e804 	mtc0	\$0,\$29,4
+0+033c <[^>]*> 4080e805 	mtc0	\$0,\$29,5
+0+0340 <[^>]*> 4080e806 	mtc0	\$0,\$29,6
+0+0344 <[^>]*> 4080e807 	mtc0	\$0,\$29,7
+0+0348 <[^>]*> 4080f001 	mtc0	\$0,\$30,1
+0+034c <[^>]*> 4080f002 	mtc0	\$0,\$30,2
+0+0350 <[^>]*> 4080f003 	mtc0	\$0,\$30,3
+0+0354 <[^>]*> 4080f004 	mtc0	\$0,\$30,4
+0+0358 <[^>]*> 4080f005 	mtc0	\$0,\$30,5
+0+035c <[^>]*> 4080f006 	mtc0	\$0,\$30,6
+0+0360 <[^>]*> 4080f007 	mtc0	\$0,\$30,7
+0+0364 <[^>]*> 4080f801 	mtc0	\$0,\$31,1
+0+0368 <[^>]*> 4080f802 	mtc0	\$0,\$31,2
+0+036c <[^>]*> 4080f803 	mtc0	\$0,\$31,3
+0+0370 <[^>]*> 4080f804 	mtc0	\$0,\$31,4
+0+0374 <[^>]*> 4080f805 	mtc0	\$0,\$31,5
+0+0378 <[^>]*> 4080f806 	mtc0	\$0,\$31,6
+0+037c <[^>]*> 4080f807 	mtc0	\$0,\$31,7
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/cp0sel-names-sb1.d b/gas/testsuite/gas/mips/cp0sel-names-sb1.d
new file mode 100644
index 0000000..6263eed
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp0sel-names-sb1.d
@@ -0,0 +1,235 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa32 -M gpr-names=numeric,cp0-names=sb1
+#name: MIPS CP0 with sel register disassembly (sb1)
+#as: -march=mips32
+#source: cp0sel-names.s
+
+# Check objdump's handling of -M cp0-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 40800001 	mtc0	\$0,\$0,1
+0+0004 <[^>]*> 40800002 	mtc0	\$0,\$0,2
+0+0008 <[^>]*> 40800003 	mtc0	\$0,\$0,3
+0+000c <[^>]*> 40800004 	mtc0	\$0,\$0,4
+0+0010 <[^>]*> 40800005 	mtc0	\$0,\$0,5
+0+0014 <[^>]*> 40800006 	mtc0	\$0,\$0,6
+0+0018 <[^>]*> 40800007 	mtc0	\$0,\$0,7
+0+001c <[^>]*> 40800801 	mtc0	\$0,\$1,1
+0+0020 <[^>]*> 40800802 	mtc0	\$0,\$1,2
+0+0024 <[^>]*> 40800803 	mtc0	\$0,\$1,3
+0+0028 <[^>]*> 40800804 	mtc0	\$0,\$1,4
+0+002c <[^>]*> 40800805 	mtc0	\$0,\$1,5
+0+0030 <[^>]*> 40800806 	mtc0	\$0,\$1,6
+0+0034 <[^>]*> 40800807 	mtc0	\$0,\$1,7
+0+0038 <[^>]*> 40801001 	mtc0	\$0,\$2,1
+0+003c <[^>]*> 40801002 	mtc0	\$0,\$2,2
+0+0040 <[^>]*> 40801003 	mtc0	\$0,\$2,3
+0+0044 <[^>]*> 40801004 	mtc0	\$0,\$2,4
+0+0048 <[^>]*> 40801005 	mtc0	\$0,\$2,5
+0+004c <[^>]*> 40801006 	mtc0	\$0,\$2,6
+0+0050 <[^>]*> 40801007 	mtc0	\$0,\$2,7
+0+0054 <[^>]*> 40801801 	mtc0	\$0,\$3,1
+0+0058 <[^>]*> 40801802 	mtc0	\$0,\$3,2
+0+005c <[^>]*> 40801803 	mtc0	\$0,\$3,3
+0+0060 <[^>]*> 40801804 	mtc0	\$0,\$3,4
+0+0064 <[^>]*> 40801805 	mtc0	\$0,\$3,5
+0+0068 <[^>]*> 40801806 	mtc0	\$0,\$3,6
+0+006c <[^>]*> 40801807 	mtc0	\$0,\$3,7
+0+0070 <[^>]*> 40802001 	mtc0	\$0,\$4,1
+0+0074 <[^>]*> 40802002 	mtc0	\$0,\$4,2
+0+0078 <[^>]*> 40802003 	mtc0	\$0,\$4,3
+0+007c <[^>]*> 40802004 	mtc0	\$0,\$4,4
+0+0080 <[^>]*> 40802005 	mtc0	\$0,\$4,5
+0+0084 <[^>]*> 40802006 	mtc0	\$0,\$4,6
+0+0088 <[^>]*> 40802007 	mtc0	\$0,\$4,7
+0+008c <[^>]*> 40802801 	mtc0	\$0,\$5,1
+0+0090 <[^>]*> 40802802 	mtc0	\$0,\$5,2
+0+0094 <[^>]*> 40802803 	mtc0	\$0,\$5,3
+0+0098 <[^>]*> 40802804 	mtc0	\$0,\$5,4
+0+009c <[^>]*> 40802805 	mtc0	\$0,\$5,5
+0+00a0 <[^>]*> 40802806 	mtc0	\$0,\$5,6
+0+00a4 <[^>]*> 40802807 	mtc0	\$0,\$5,7
+0+00a8 <[^>]*> 40803001 	mtc0	\$0,\$6,1
+0+00ac <[^>]*> 40803002 	mtc0	\$0,\$6,2
+0+00b0 <[^>]*> 40803003 	mtc0	\$0,\$6,3
+0+00b4 <[^>]*> 40803004 	mtc0	\$0,\$6,4
+0+00b8 <[^>]*> 40803005 	mtc0	\$0,\$6,5
+0+00bc <[^>]*> 40803006 	mtc0	\$0,\$6,6
+0+00c0 <[^>]*> 40803007 	mtc0	\$0,\$6,7
+0+00c4 <[^>]*> 40803801 	mtc0	\$0,\$7,1
+0+00c8 <[^>]*> 40803802 	mtc0	\$0,\$7,2
+0+00cc <[^>]*> 40803803 	mtc0	\$0,\$7,3
+0+00d0 <[^>]*> 40803804 	mtc0	\$0,\$7,4
+0+00d4 <[^>]*> 40803805 	mtc0	\$0,\$7,5
+0+00d8 <[^>]*> 40803806 	mtc0	\$0,\$7,6
+0+00dc <[^>]*> 40803807 	mtc0	\$0,\$7,7
+0+00e0 <[^>]*> 40804001 	mtc0	\$0,\$8,1
+0+00e4 <[^>]*> 40804002 	mtc0	\$0,\$8,2
+0+00e8 <[^>]*> 40804003 	mtc0	\$0,\$8,3
+0+00ec <[^>]*> 40804004 	mtc0	\$0,\$8,4
+0+00f0 <[^>]*> 40804005 	mtc0	\$0,\$8,5
+0+00f4 <[^>]*> 40804006 	mtc0	\$0,\$8,6
+0+00f8 <[^>]*> 40804007 	mtc0	\$0,\$8,7
+0+00fc <[^>]*> 40804801 	mtc0	\$0,\$9,1
+0+0100 <[^>]*> 40804802 	mtc0	\$0,\$9,2
+0+0104 <[^>]*> 40804803 	mtc0	\$0,\$9,3
+0+0108 <[^>]*> 40804804 	mtc0	\$0,\$9,4
+0+010c <[^>]*> 40804805 	mtc0	\$0,\$9,5
+0+0110 <[^>]*> 40804806 	mtc0	\$0,\$9,6
+0+0114 <[^>]*> 40804807 	mtc0	\$0,\$9,7
+0+0118 <[^>]*> 40805001 	mtc0	\$0,\$10,1
+0+011c <[^>]*> 40805002 	mtc0	\$0,\$10,2
+0+0120 <[^>]*> 40805003 	mtc0	\$0,\$10,3
+0+0124 <[^>]*> 40805004 	mtc0	\$0,\$10,4
+0+0128 <[^>]*> 40805005 	mtc0	\$0,\$10,5
+0+012c <[^>]*> 40805006 	mtc0	\$0,\$10,6
+0+0130 <[^>]*> 40805007 	mtc0	\$0,\$10,7
+0+0134 <[^>]*> 40805801 	mtc0	\$0,\$11,1
+0+0138 <[^>]*> 40805802 	mtc0	\$0,\$11,2
+0+013c <[^>]*> 40805803 	mtc0	\$0,\$11,3
+0+0140 <[^>]*> 40805804 	mtc0	\$0,\$11,4
+0+0144 <[^>]*> 40805805 	mtc0	\$0,\$11,5
+0+0148 <[^>]*> 40805806 	mtc0	\$0,\$11,6
+0+014c <[^>]*> 40805807 	mtc0	\$0,\$11,7
+0+0150 <[^>]*> 40806001 	mtc0	\$0,\$12,1
+0+0154 <[^>]*> 40806002 	mtc0	\$0,\$12,2
+0+0158 <[^>]*> 40806003 	mtc0	\$0,\$12,3
+0+015c <[^>]*> 40806004 	mtc0	\$0,\$12,4
+0+0160 <[^>]*> 40806005 	mtc0	\$0,\$12,5
+0+0164 <[^>]*> 40806006 	mtc0	\$0,\$12,6
+0+0168 <[^>]*> 40806007 	mtc0	\$0,\$12,7
+0+016c <[^>]*> 40806801 	mtc0	\$0,\$13,1
+0+0170 <[^>]*> 40806802 	mtc0	\$0,\$13,2
+0+0174 <[^>]*> 40806803 	mtc0	\$0,\$13,3
+0+0178 <[^>]*> 40806804 	mtc0	\$0,\$13,4
+0+017c <[^>]*> 40806805 	mtc0	\$0,\$13,5
+0+0180 <[^>]*> 40806806 	mtc0	\$0,\$13,6
+0+0184 <[^>]*> 40806807 	mtc0	\$0,\$13,7
+0+0188 <[^>]*> 40807001 	mtc0	\$0,\$14,1
+0+018c <[^>]*> 40807002 	mtc0	\$0,\$14,2
+0+0190 <[^>]*> 40807003 	mtc0	\$0,\$14,3
+0+0194 <[^>]*> 40807004 	mtc0	\$0,\$14,4
+0+0198 <[^>]*> 40807005 	mtc0	\$0,\$14,5
+0+019c <[^>]*> 40807006 	mtc0	\$0,\$14,6
+0+01a0 <[^>]*> 40807007 	mtc0	\$0,\$14,7
+0+01a4 <[^>]*> 40807801 	mtc0	\$0,\$15,1
+0+01a8 <[^>]*> 40807802 	mtc0	\$0,\$15,2
+0+01ac <[^>]*> 40807803 	mtc0	\$0,\$15,3
+0+01b0 <[^>]*> 40807804 	mtc0	\$0,\$15,4
+0+01b4 <[^>]*> 40807805 	mtc0	\$0,\$15,5
+0+01b8 <[^>]*> 40807806 	mtc0	\$0,\$15,6
+0+01bc <[^>]*> 40807807 	mtc0	\$0,\$15,7
+0+01c0 <[^>]*> 40808001 	mtc0	\$0,c0_config1
+0+01c4 <[^>]*> 40808002 	mtc0	\$0,\$16,2
+0+01c8 <[^>]*> 40808003 	mtc0	\$0,\$16,3
+0+01cc <[^>]*> 40808004 	mtc0	\$0,\$16,4
+0+01d0 <[^>]*> 40808005 	mtc0	\$0,\$16,5
+0+01d4 <[^>]*> 40808006 	mtc0	\$0,\$16,6
+0+01d8 <[^>]*> 40808007 	mtc0	\$0,\$16,7
+0+01dc <[^>]*> 40808801 	mtc0	\$0,\$17,1
+0+01e0 <[^>]*> 40808802 	mtc0	\$0,\$17,2
+0+01e4 <[^>]*> 40808803 	mtc0	\$0,\$17,3
+0+01e8 <[^>]*> 40808804 	mtc0	\$0,\$17,4
+0+01ec <[^>]*> 40808805 	mtc0	\$0,\$17,5
+0+01f0 <[^>]*> 40808806 	mtc0	\$0,\$17,6
+0+01f4 <[^>]*> 40808807 	mtc0	\$0,\$17,7
+0+01f8 <[^>]*> 40809001 	mtc0	\$0,c0_watchlo,1
+0+01fc <[^>]*> 40809002 	mtc0	\$0,\$18,2
+0+0200 <[^>]*> 40809003 	mtc0	\$0,\$18,3
+0+0204 <[^>]*> 40809004 	mtc0	\$0,\$18,4
+0+0208 <[^>]*> 40809005 	mtc0	\$0,\$18,5
+0+020c <[^>]*> 40809006 	mtc0	\$0,\$18,6
+0+0210 <[^>]*> 40809007 	mtc0	\$0,\$18,7
+0+0214 <[^>]*> 40809801 	mtc0	\$0,c0_watchhi,1
+0+0218 <[^>]*> 40809802 	mtc0	\$0,\$19,2
+0+021c <[^>]*> 40809803 	mtc0	\$0,\$19,3
+0+0220 <[^>]*> 40809804 	mtc0	\$0,\$19,4
+0+0224 <[^>]*> 40809805 	mtc0	\$0,\$19,5
+0+0228 <[^>]*> 40809806 	mtc0	\$0,\$19,6
+0+022c <[^>]*> 40809807 	mtc0	\$0,\$19,7
+0+0230 <[^>]*> 4080a001 	mtc0	\$0,\$20,1
+0+0234 <[^>]*> 4080a002 	mtc0	\$0,\$20,2
+0+0238 <[^>]*> 4080a003 	mtc0	\$0,\$20,3
+0+023c <[^>]*> 4080a004 	mtc0	\$0,\$20,4
+0+0240 <[^>]*> 4080a005 	mtc0	\$0,\$20,5
+0+0244 <[^>]*> 4080a006 	mtc0	\$0,\$20,6
+0+0248 <[^>]*> 4080a007 	mtc0	\$0,\$20,7
+0+024c <[^>]*> 4080a801 	mtc0	\$0,\$21,1
+0+0250 <[^>]*> 4080a802 	mtc0	\$0,\$21,2
+0+0254 <[^>]*> 4080a803 	mtc0	\$0,\$21,3
+0+0258 <[^>]*> 4080a804 	mtc0	\$0,\$21,4
+0+025c <[^>]*> 4080a805 	mtc0	\$0,\$21,5
+0+0260 <[^>]*> 4080a806 	mtc0	\$0,\$21,6
+0+0264 <[^>]*> 4080a807 	mtc0	\$0,\$21,7
+0+0268 <[^>]*> 4080b001 	mtc0	\$0,\$22,1
+0+026c <[^>]*> 4080b002 	mtc0	\$0,\$22,2
+0+0270 <[^>]*> 4080b003 	mtc0	\$0,\$22,3
+0+0274 <[^>]*> 4080b004 	mtc0	\$0,\$22,4
+0+0278 <[^>]*> 4080b005 	mtc0	\$0,\$22,5
+0+027c <[^>]*> 4080b006 	mtc0	\$0,\$22,6
+0+0280 <[^>]*> 4080b007 	mtc0	\$0,\$22,7
+0+0284 <[^>]*> 4080b801 	mtc0	\$0,\$23,1
+0+0288 <[^>]*> 4080b802 	mtc0	\$0,\$23,2
+0+028c <[^>]*> 4080b803 	mtc0	\$0,c0_edebug
+0+0290 <[^>]*> 4080b804 	mtc0	\$0,\$23,4
+0+0294 <[^>]*> 4080b805 	mtc0	\$0,\$23,5
+0+0298 <[^>]*> 4080b806 	mtc0	\$0,\$23,6
+0+029c <[^>]*> 4080b807 	mtc0	\$0,\$23,7
+0+02a0 <[^>]*> 4080c001 	mtc0	\$0,\$24,1
+0+02a4 <[^>]*> 4080c002 	mtc0	\$0,\$24,2
+0+02a8 <[^>]*> 4080c003 	mtc0	\$0,\$24,3
+0+02ac <[^>]*> 4080c004 	mtc0	\$0,\$24,4
+0+02b0 <[^>]*> 4080c005 	mtc0	\$0,\$24,5
+0+02b4 <[^>]*> 4080c006 	mtc0	\$0,\$24,6
+0+02b8 <[^>]*> 4080c007 	mtc0	\$0,\$24,7
+0+02bc <[^>]*> 4080c801 	mtc0	\$0,c0_perfcnt,1
+0+02c0 <[^>]*> 4080c802 	mtc0	\$0,c0_perfcnt,2
+0+02c4 <[^>]*> 4080c803 	mtc0	\$0,c0_perfcnt,3
+0+02c8 <[^>]*> 4080c804 	mtc0	\$0,c0_perfcnt,4
+0+02cc <[^>]*> 4080c805 	mtc0	\$0,c0_perfcnt,5
+0+02d0 <[^>]*> 4080c806 	mtc0	\$0,c0_perfcnt,6
+0+02d4 <[^>]*> 4080c807 	mtc0	\$0,c0_perfcnt,7
+0+02d8 <[^>]*> 4080d001 	mtc0	\$0,c0_buserr_pa
+0+02dc <[^>]*> 4080d002 	mtc0	\$0,\$26,2
+0+02e0 <[^>]*> 4080d003 	mtc0	\$0,\$26,3
+0+02e4 <[^>]*> 4080d004 	mtc0	\$0,\$26,4
+0+02e8 <[^>]*> 4080d005 	mtc0	\$0,\$26,5
+0+02ec <[^>]*> 4080d006 	mtc0	\$0,\$26,6
+0+02f0 <[^>]*> 4080d007 	mtc0	\$0,\$26,7
+0+02f4 <[^>]*> 4080d801 	mtc0	\$0,c0_cacheerr_d
+0+02f8 <[^>]*> 4080d802 	mtc0	\$0,\$27,2
+0+02fc <[^>]*> 4080d803 	mtc0	\$0,c0_cacheerr_d_pa
+0+0300 <[^>]*> 4080d804 	mtc0	\$0,\$27,4
+0+0304 <[^>]*> 4080d805 	mtc0	\$0,\$27,5
+0+0308 <[^>]*> 4080d806 	mtc0	\$0,\$27,6
+0+030c <[^>]*> 4080d807 	mtc0	\$0,\$27,7
+0+0310 <[^>]*> 4080e001 	mtc0	\$0,c0_datalo_i
+0+0314 <[^>]*> 4080e002 	mtc0	\$0,c0_taglo_d
+0+0318 <[^>]*> 4080e003 	mtc0	\$0,c0_datalo_d
+0+031c <[^>]*> 4080e004 	mtc0	\$0,\$28,4
+0+0320 <[^>]*> 4080e005 	mtc0	\$0,\$28,5
+0+0324 <[^>]*> 4080e006 	mtc0	\$0,\$28,6
+0+0328 <[^>]*> 4080e007 	mtc0	\$0,\$28,7
+0+032c <[^>]*> 4080e801 	mtc0	\$0,c0_datahi_i
+0+0330 <[^>]*> 4080e802 	mtc0	\$0,c0_taghi_d
+0+0334 <[^>]*> 4080e803 	mtc0	\$0,c0_datahi_d
+0+0338 <[^>]*> 4080e804 	mtc0	\$0,\$29,4
+0+033c <[^>]*> 4080e805 	mtc0	\$0,\$29,5
+0+0340 <[^>]*> 4080e806 	mtc0	\$0,\$29,6
+0+0344 <[^>]*> 4080e807 	mtc0	\$0,\$29,7
+0+0348 <[^>]*> 4080f001 	mtc0	\$0,\$30,1
+0+034c <[^>]*> 4080f002 	mtc0	\$0,\$30,2
+0+0350 <[^>]*> 4080f003 	mtc0	\$0,\$30,3
+0+0354 <[^>]*> 4080f004 	mtc0	\$0,\$30,4
+0+0358 <[^>]*> 4080f005 	mtc0	\$0,\$30,5
+0+035c <[^>]*> 4080f006 	mtc0	\$0,\$30,6
+0+0360 <[^>]*> 4080f007 	mtc0	\$0,\$30,7
+0+0364 <[^>]*> 4080f801 	mtc0	\$0,\$31,1
+0+0368 <[^>]*> 4080f802 	mtc0	\$0,\$31,2
+0+036c <[^>]*> 4080f803 	mtc0	\$0,\$31,3
+0+0370 <[^>]*> 4080f804 	mtc0	\$0,\$31,4
+0+0374 <[^>]*> 4080f805 	mtc0	\$0,\$31,5
+0+0378 <[^>]*> 4080f806 	mtc0	\$0,\$31,6
+0+037c <[^>]*> 4080f807 	mtc0	\$0,\$31,7
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/cp0sel-names.s b/gas/testsuite/gas/mips/cp0sel-names.s
new file mode 100644
index 0000000..e9ae9c1
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp0sel-names.s
@@ -0,0 +1,236 @@
+# source file to test objdump's disassembly using various styles of
+# CP0 (w/ non-zero select code) register names.
+
+	.set noreorder
+	.set noat
+
+	.globl text_label .text
+text_label:
+
+	mtc0	$0, $0, 1
+	mtc0	$0, $0, 2
+	mtc0	$0, $0, 3
+	mtc0	$0, $0, 4
+	mtc0	$0, $0, 5
+	mtc0	$0, $0, 6
+	mtc0	$0, $0, 7
+	mtc0	$0, $1, 1
+	mtc0	$0, $1, 2
+	mtc0	$0, $1, 3
+	mtc0	$0, $1, 4
+	mtc0	$0, $1, 5
+	mtc0	$0, $1, 6
+	mtc0	$0, $1, 7
+	mtc0	$0, $2, 1
+	mtc0	$0, $2, 2
+	mtc0	$0, $2, 3
+	mtc0	$0, $2, 4
+	mtc0	$0, $2, 5
+	mtc0	$0, $2, 6
+	mtc0	$0, $2, 7
+	mtc0	$0, $3, 1
+	mtc0	$0, $3, 2
+	mtc0	$0, $3, 3
+	mtc0	$0, $3, 4
+	mtc0	$0, $3, 5
+	mtc0	$0, $3, 6
+	mtc0	$0, $3, 7
+	mtc0	$0, $4, 1
+	mtc0	$0, $4, 2
+	mtc0	$0, $4, 3
+	mtc0	$0, $4, 4
+	mtc0	$0, $4, 5
+	mtc0	$0, $4, 6
+	mtc0	$0, $4, 7
+	mtc0	$0, $5, 1
+	mtc0	$0, $5, 2
+	mtc0	$0, $5, 3
+	mtc0	$0, $5, 4
+	mtc0	$0, $5, 5
+	mtc0	$0, $5, 6
+	mtc0	$0, $5, 7
+	mtc0	$0, $6, 1
+	mtc0	$0, $6, 2
+	mtc0	$0, $6, 3
+	mtc0	$0, $6, 4
+	mtc0	$0, $6, 5
+	mtc0	$0, $6, 6
+	mtc0	$0, $6, 7
+	mtc0	$0, $7, 1
+	mtc0	$0, $7, 2
+	mtc0	$0, $7, 3
+	mtc0	$0, $7, 4
+	mtc0	$0, $7, 5
+	mtc0	$0, $7, 6
+	mtc0	$0, $7, 7
+	mtc0	$0, $8, 1
+	mtc0	$0, $8, 2
+	mtc0	$0, $8, 3
+	mtc0	$0, $8, 4
+	mtc0	$0, $8, 5
+	mtc0	$0, $8, 6
+	mtc0	$0, $8, 7
+	mtc0	$0, $9, 1
+	mtc0	$0, $9, 2
+	mtc0	$0, $9, 3
+	mtc0	$0, $9, 4
+	mtc0	$0, $9, 5
+	mtc0	$0, $9, 6
+	mtc0	$0, $9, 7
+	mtc0	$0, $10, 1
+	mtc0	$0, $10, 2
+	mtc0	$0, $10, 3
+	mtc0	$0, $10, 4
+	mtc0	$0, $10, 5
+	mtc0	$0, $10, 6
+	mtc0	$0, $10, 7
+	mtc0	$0, $11, 1
+	mtc0	$0, $11, 2
+	mtc0	$0, $11, 3
+	mtc0	$0, $11, 4
+	mtc0	$0, $11, 5
+	mtc0	$0, $11, 6
+	mtc0	$0, $11, 7
+	mtc0	$0, $12, 1
+	mtc0	$0, $12, 2
+	mtc0	$0, $12, 3
+	mtc0	$0, $12, 4
+	mtc0	$0, $12, 5
+	mtc0	$0, $12, 6
+	mtc0	$0, $12, 7
+	mtc0	$0, $13, 1
+	mtc0	$0, $13, 2
+	mtc0	$0, $13, 3
+	mtc0	$0, $13, 4
+	mtc0	$0, $13, 5
+	mtc0	$0, $13, 6
+	mtc0	$0, $13, 7
+	mtc0	$0, $14, 1
+	mtc0	$0, $14, 2
+	mtc0	$0, $14, 3
+	mtc0	$0, $14, 4
+	mtc0	$0, $14, 5
+	mtc0	$0, $14, 6
+	mtc0	$0, $14, 7
+	mtc0	$0, $15, 1
+	mtc0	$0, $15, 2
+	mtc0	$0, $15, 3
+	mtc0	$0, $15, 4
+	mtc0	$0, $15, 5
+	mtc0	$0, $15, 6
+	mtc0	$0, $15, 7
+	mtc0	$0, $16, 1
+	mtc0	$0, $16, 2
+	mtc0	$0, $16, 3
+	mtc0	$0, $16, 4
+	mtc0	$0, $16, 5
+	mtc0	$0, $16, 6
+	mtc0	$0, $16, 7
+	mtc0	$0, $17, 1
+	mtc0	$0, $17, 2
+	mtc0	$0, $17, 3
+	mtc0	$0, $17, 4
+	mtc0	$0, $17, 5
+	mtc0	$0, $17, 6
+	mtc0	$0, $17, 7
+	mtc0	$0, $18, 1
+	mtc0	$0, $18, 2
+	mtc0	$0, $18, 3
+	mtc0	$0, $18, 4
+	mtc0	$0, $18, 5
+	mtc0	$0, $18, 6
+	mtc0	$0, $18, 7
+	mtc0	$0, $19, 1
+	mtc0	$0, $19, 2
+	mtc0	$0, $19, 3
+	mtc0	$0, $19, 4
+	mtc0	$0, $19, 5
+	mtc0	$0, $19, 6
+	mtc0	$0, $19, 7
+	mtc0	$0, $20, 1
+	mtc0	$0, $20, 2
+	mtc0	$0, $20, 3
+	mtc0	$0, $20, 4
+	mtc0	$0, $20, 5
+	mtc0	$0, $20, 6
+	mtc0	$0, $20, 7
+	mtc0	$0, $21, 1
+	mtc0	$0, $21, 2
+	mtc0	$0, $21, 3
+	mtc0	$0, $21, 4
+	mtc0	$0, $21, 5
+	mtc0	$0, $21, 6
+	mtc0	$0, $21, 7
+	mtc0	$0, $22, 1
+	mtc0	$0, $22, 2
+	mtc0	$0, $22, 3
+	mtc0	$0, $22, 4
+	mtc0	$0, $22, 5
+	mtc0	$0, $22, 6
+	mtc0	$0, $22, 7
+	mtc0	$0, $23, 1
+	mtc0	$0, $23, 2
+	mtc0	$0, $23, 3
+	mtc0	$0, $23, 4
+	mtc0	$0, $23, 5
+	mtc0	$0, $23, 6
+	mtc0	$0, $23, 7
+	mtc0	$0, $24, 1
+	mtc0	$0, $24, 2
+	mtc0	$0, $24, 3
+	mtc0	$0, $24, 4
+	mtc0	$0, $24, 5
+	mtc0	$0, $24, 6
+	mtc0	$0, $24, 7
+	mtc0	$0, $25, 1
+	mtc0	$0, $25, 2
+	mtc0	$0, $25, 3
+	mtc0	$0, $25, 4
+	mtc0	$0, $25, 5
+	mtc0	$0, $25, 6
+	mtc0	$0, $25, 7
+	mtc0	$0, $26, 1
+	mtc0	$0, $26, 2
+	mtc0	$0, $26, 3
+	mtc0	$0, $26, 4
+	mtc0	$0, $26, 5
+	mtc0	$0, $26, 6
+	mtc0	$0, $26, 7
+	mtc0	$0, $27, 1
+	mtc0	$0, $27, 2
+	mtc0	$0, $27, 3
+	mtc0	$0, $27, 4
+	mtc0	$0, $27, 5
+	mtc0	$0, $27, 6
+	mtc0	$0, $27, 7
+	mtc0	$0, $28, 1
+	mtc0	$0, $28, 2
+	mtc0	$0, $28, 3
+	mtc0	$0, $28, 4
+	mtc0	$0, $28, 5
+	mtc0	$0, $28, 6
+	mtc0	$0, $28, 7
+	mtc0	$0, $29, 1
+	mtc0	$0, $29, 2
+	mtc0	$0, $29, 3
+	mtc0	$0, $29, 4
+	mtc0	$0, $29, 5
+	mtc0	$0, $29, 6
+	mtc0	$0, $29, 7
+	mtc0	$0, $30, 1
+	mtc0	$0, $30, 2
+	mtc0	$0, $30, 3
+	mtc0	$0, $30, 4
+	mtc0	$0, $30, 5
+	mtc0	$0, $30, 6
+	mtc0	$0, $30, 7
+	mtc0	$0, $31, 1
+	mtc0	$0, $31, 2
+	mtc0	$0, $31, 3
+	mtc0	$0, $31, 4
+	mtc0	$0, $31, 5
+	mtc0	$0, $31, 6
+	mtc0	$0, $31, 7
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+      .space  8
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 256d6cb..c43b126 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -631,6 +631,12 @@ if { [istarget mips*-*-*] } then {
     run_dump_test "cp0-names-mips64"
     run_dump_test "cp0-names-sb1"
 
+    run_dump_test "cp0sel-names-numeric"
+    run_dump_test "cp0sel-names-mips32"
+    run_dump_test "cp0sel-names-mips32r2"
+    run_dump_test "cp0sel-names-mips64"
+    run_dump_test "cp0sel-names-sb1"
+
     run_dump_test "hwr-names-numeric"
     run_dump_test "hwr-names-mips32r2"
 }
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 6f68432..89a231b 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2002-12-31  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h: Note that the "+D" operand type name is now used.
+
 2002-12-30  Chris Demetriou  <cgd@broadcom.com>
 
 	* mips.h: Document "+" as the start of two-character operand
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index ce6ce08..19f3e21 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -257,6 +257,8 @@ struct mips_opcode
    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
    see also "k" above
+   "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
+	for pretty-printing in disassembly only.
 
    Macro instructions:
    "A" General 32 bit expression
@@ -287,7 +289,7 @@ struct mips_opcode
 
    Extension character sequences used so far ("+" followed by the
    following), for quick reference when adding more:
-   "ABC"
+   "ABCD"
 */
 
 /* These are the bits which may be set in the pinfo field of an
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 98a4b3c..f33f75d 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,25 @@
+2002-12-31  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c (mips_cp0sel_name): New structure.
+	(mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2)
+	(mips_cp0sel_names_sb1): New arrays.
+	(mips_arch_choice): New structure members "cp0sel_names" and
+	"cp0sel_names_len".
+	(mips_arch_choices): Add references to new cp0sel_names arrays
+	as appropriate, and make all existing entries reference
+	appropriate mips_XXX_names_numeric arrays rather than simply
+	using NULL.
+	(mips_cp0sel_names, mips_cp0sel_names_len): New variables.
+	(lookup_mips_cp0sel_name): New function.
+	(set_default_mips_dis_options): Set mips_cp0sel_names and
+	mips_cp0sel_names_len as appropriate.  Remove now-unnecessary
+	checks for NULL register name arrays.
+	(parse_mips_dis_option): Likewise.
+	(print_insn_arg): Handle "+D" operand type.
+	* mips-opc.c (mips_builtin_opcodes): Add new "+D" variants
+	of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register
+	names symbolically.
+
 2002-12-30  Chris Demetriou  <cgd@broadcom.com>
 
 	* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 71cf6be..a2f68e9 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -62,6 +62,12 @@ static void print_mips16_insn_arg
 
 /* FIXME: These should be shared with gdb somehow.  */
 
+struct mips_cp0sel_name {
+	unsigned int cp0reg;
+	unsigned int sel;
+	const char * const name;
+};
+
 /* The mips16 register names.  */
 static const char * const mips16_reg_names[] = {
   "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
@@ -134,6 +140,38 @@ static const char * const mips_cp0_names_mips3264[32] = {
   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
 };
 
+static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = {
+  { 16, 1, "c0_config1"		},
+  { 16, 2, "c0_config2"		},
+  { 16, 3, "c0_config3"		},
+  { 18, 1, "c0_watchlo,1"	},
+  { 18, 2, "c0_watchlo,2"	},
+  { 18, 3, "c0_watchlo,3"	},
+  { 18, 4, "c0_watchlo,4"	},
+  { 18, 5, "c0_watchlo,5"	},
+  { 18, 6, "c0_watchlo,6"	},
+  { 18, 7, "c0_watchlo,7"	},
+  { 19, 1, "c0_watchhi,1"	},
+  { 19, 2, "c0_watchhi,2"	},
+  { 19, 3, "c0_watchhi,3"	},
+  { 19, 4, "c0_watchhi,4"	},
+  { 19, 5, "c0_watchhi,5"	},
+  { 19, 6, "c0_watchhi,6"	},
+  { 19, 7, "c0_watchhi,7"	},
+  { 25, 1, "c0_perfcnt,1"	},
+  { 25, 2, "c0_perfcnt,2"	},
+  { 25, 3, "c0_perfcnt,3"	},
+  { 25, 4, "c0_perfcnt,4"	},
+  { 25, 5, "c0_perfcnt,5"	},
+  { 25, 6, "c0_perfcnt,6"	},
+  { 25, 7, "c0_perfcnt,7"	},
+  { 27, 1, "c0_cacheerr,1"	},
+  { 27, 2, "c0_cacheerr,2"	},
+  { 27, 3, "c0_cacheerr,3"	},
+  { 28, 1, "c0_datalo"		},
+  { 29, 1, "c0_datahi"		}
+};
+
 static const char * const mips_cp0_names_mips3264r2[32] = {
   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
   "c0_context",   "c0_pagemask",  "c0_wired",     "c0_hwrena",
@@ -145,6 +183,60 @@ static const char * const mips_cp0_names_mips3264r2[32] = {
   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
 };
 
+static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = {
+  {  4, 1, "c0_contextconfig"	},
+  {  5, 1, "c0_pagegrain"	},
+  { 12, 1, "c0_intctl"		},
+  { 12, 2, "c0_srsctl"		},
+  { 12, 3, "c0_srsmap"		},
+  { 15, 1, "c0_ebase"		},
+  { 16, 1, "c0_config1"		},
+  { 16, 2, "c0_config2"		},
+  { 16, 3, "c0_config3"		},
+  { 18, 1, "c0_watchlo,1"	},
+  { 18, 2, "c0_watchlo,2"	},
+  { 18, 3, "c0_watchlo,3"	},
+  { 18, 4, "c0_watchlo,4"	},
+  { 18, 5, "c0_watchlo,5"	},
+  { 18, 6, "c0_watchlo,6"	},
+  { 18, 7, "c0_watchlo,7"	},
+  { 19, 1, "c0_watchhi,1"	},
+  { 19, 2, "c0_watchhi,2"	},
+  { 19, 3, "c0_watchhi,3"	},
+  { 19, 4, "c0_watchhi,4"	},
+  { 19, 5, "c0_watchhi,5"	},
+  { 19, 6, "c0_watchhi,6"	},
+  { 19, 7, "c0_watchhi,7"	},
+  { 23, 1, "c0_tracecontrol"	},
+  { 23, 2, "c0_tracecontrol2"	},
+  { 23, 3, "c0_usertracedata"	},
+  { 23, 4, "c0_tracebpc"	},
+  { 25, 1, "c0_perfcnt,1"	},
+  { 25, 2, "c0_perfcnt,2"	},
+  { 25, 3, "c0_perfcnt,3"	},
+  { 25, 4, "c0_perfcnt,4"	},
+  { 25, 5, "c0_perfcnt,5"	},
+  { 25, 6, "c0_perfcnt,6"	},
+  { 25, 7, "c0_perfcnt,7"	},
+  { 27, 1, "c0_cacheerr,1"	},
+  { 27, 2, "c0_cacheerr,2"	},
+  { 27, 3, "c0_cacheerr,3"	},
+  { 28, 1, "c0_datalo"		},
+  { 28, 2, "c0_taglo1"		},
+  { 28, 3, "c0_datalo1"		},
+  { 28, 4, "c0_taglo2"		},
+  { 28, 5, "c0_datalo2"		},
+  { 28, 6, "c0_taglo3"		},
+  { 28, 7, "c0_datalo3"		},
+  { 29, 1, "c0_datahi"		},
+  { 29, 2, "c0_taghi1"		},
+  { 29, 3, "c0_datahi1"		},
+  { 29, 4, "c0_taghi2"		},
+  { 29, 5, "c0_datahi2"		},
+  { 29, 6, "c0_taghi3"		},
+  { 29, 7, "c0_datahi3"		},
+};
+
 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods.  */
 static const char * const mips_cp0_names_sb1[32] = {
   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
@@ -157,6 +249,30 @@ static const char * const mips_cp0_names_sb1[32] = {
   "c0_taglo_i",   "c0_taghi_i",   "c0_errorepc",  "c0_desave",
 };
 
+static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = {
+  { 16, 1, "c0_config1"		},
+  { 18, 1, "c0_watchlo,1"	},
+  { 19, 1, "c0_watchhi,1"	},
+  { 22, 0, "c0_perftrace"	},
+  { 23, 3, "c0_edebug"		},
+  { 25, 1, "c0_perfcnt,1"	},
+  { 25, 2, "c0_perfcnt,2"	},
+  { 25, 3, "c0_perfcnt,3"	},
+  { 25, 4, "c0_perfcnt,4"	},
+  { 25, 5, "c0_perfcnt,5"	},
+  { 25, 6, "c0_perfcnt,6"	},
+  { 25, 7, "c0_perfcnt,7"	},
+  { 26, 1, "c0_buserr_pa"	},
+  { 27, 1, "c0_cacheerr_d"	},
+  { 27, 3, "c0_cacheerr_d_pa"	},
+  { 28, 1, "c0_datalo_i"	},
+  { 28, 2, "c0_taglo_d"		},
+  { 28, 3, "c0_datalo_d"	},
+  { 29, 1, "c0_datahi_i"	},
+  { 29, 2, "c0_taghi_d"		},
+  { 29, 3, "c0_datahi_d"	},
+};
+
 static const char * const mips_hwr_names_numeric[32] = {
   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
@@ -192,50 +308,54 @@ struct mips_arch_choice {
   int processor;
   int isa;
   const char * const *cp0_names;
+  const struct mips_cp0sel_name *cp0sel_names;
+  unsigned int cp0sel_names_len;
   const char * const *hwr_names;
 };
 
-struct mips_arch_choice mips_arch_choices[] = {
+const struct mips_arch_choice mips_arch_choices[] = {
   { "numeric",	0, 0, 0, 0,
-    mips_cp0_names_numeric, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+
   { "r3000",	1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "r3900",	1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "r4000",	1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "r4010",	1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "vr4100",	1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "vr4111",	1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "vr4120",	1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "r4300",	1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "r4400",	1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "r4600",	1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "r4650",	1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "r5000",	1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "vr5400",	1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "vr5500",	1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "r6000",	1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "r8000",	1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "r10000",	1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "r12000",	1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "mips5",	1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+
   /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
      Note that MIPS-3D and MDMX are not applicable to MIPS32.  (See
      _MIPS32 Architecture For Programmers Volume I: Introduction to the
@@ -243,22 +363,33 @@ struct mips_arch_choice mips_arch_choices[] = {
      page 1.  */
   { "mips32",	1, bfd_mach_mipsisa32, CPU_MIPS32,
     ISA_MIPS32 | INSN_MIPS16,
-    mips_cp0_names_mips3264, NULL },
+    mips_cp0_names_mips3264,
+    mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
+    mips_hwr_names_numeric },
+
   { "mips32r2",	1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
     ISA_MIPS32R2 | INSN_MIPS16,
-    mips_cp0_names_mips3264r2, mips_hwr_names_mips3264r2 },
+    mips_cp0_names_mips3264r2,
+    mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+    mips_hwr_names_mips3264r2 },
+
   /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
   { "mips64",	1, bfd_mach_mipsisa64, CPU_MIPS64,
     ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
-    mips_cp0_names_mips3264, NULL },
+    mips_cp0_names_mips3264,
+    mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
+    mips_hwr_names_numeric },
+
   { "sb1",	1, bfd_mach_mips_sb1, CPU_SB1,
     ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
-    mips_cp0_names_sb1, NULL },
+    mips_cp0_names_sb1,
+    mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
+    mips_hwr_names_numeric },
 
   /* This entry, mips16, is here only for ISA/processor selection; do
      not print its name.  */
   { "",		1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
-    NULL, NULL },
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
 };
 
 /* ISA and processor type to disassemble for, and register names to use.
@@ -269,6 +400,8 @@ static int mips_isa;
 static const char * const *mips_gpr_names;
 static const char * const *mips_fpr_names;
 static const char * const *mips_cp0_names;
+static const struct mips_cp0sel_name *mips_cp0sel_names;
+static int mips_cp0sel_names_len;
 static const char * const *mips_hwr_names;
 
 static const struct mips_abi_choice *choose_abi_by_name
@@ -277,6 +410,9 @@ static const struct mips_arch_choice *choose_arch_by_name
   PARAMS ((const char *, unsigned int));
 static const struct mips_arch_choice *choose_arch_by_number
   PARAMS ((unsigned long));
+static const struct mips_cp0sel_name *lookup_mips_cp0sel_name
+  PARAMS ((const struct mips_cp0sel_name *, unsigned int, unsigned int,
+	   unsigned int));
 
 static const struct mips_abi_choice *
 choose_abi_by_name (name, namelen)
@@ -354,6 +490,8 @@ set_default_mips_dis_options (info)
   mips_gpr_names = mips_gpr_names_oldabi;
   mips_fpr_names = mips_fpr_names_numeric;
   mips_cp0_names = mips_cp0_names_numeric;
+  mips_cp0sel_names = NULL;
+  mips_cp0sel_names_len = 0;
   mips_hwr_names = mips_hwr_names_numeric;
 
   /* If an ELF "newabi" binary, use the n32/(n)64 GPR names.  */
@@ -378,10 +516,10 @@ set_default_mips_dis_options (info)
     {
       mips_processor = chosen_arch->processor;
       mips_isa = chosen_arch->isa;
-      if (chosen_arch->cp0_names != NULL)
-	mips_cp0_names = chosen_arch->cp0_names;
-      if (chosen_arch->hwr_names != NULL)
-	mips_hwr_names = chosen_arch->hwr_names;
+      mips_cp0_names = chosen_arch->cp0_names;
+      mips_cp0sel_names = chosen_arch->cp0sel_names;
+      mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
+      mips_hwr_names = chosen_arch->hwr_names;
     }
 #endif
 }
@@ -417,7 +555,7 @@ parse_mips_dis_option (option, len)
       && strlen("gpr-names") == optionlen)
     {
       chosen_abi = choose_abi_by_name (val, vallen);
-      if (chosen_abi != NULL && chosen_abi->gpr_names != NULL)
+      if (chosen_abi != NULL)
 	mips_gpr_names = chosen_abi->gpr_names;
       return;
     }
@@ -426,7 +564,7 @@ parse_mips_dis_option (option, len)
       && strlen("fpr-names") == optionlen)
     {
       chosen_abi = choose_abi_by_name (val, vallen);
-      if (chosen_abi != NULL && chosen_abi->fpr_names != NULL)
+      if (chosen_abi != NULL)
 	mips_fpr_names = chosen_abi->fpr_names;
       return;
     }
@@ -435,8 +573,12 @@ parse_mips_dis_option (option, len)
       && strlen("cp0-names") == optionlen)
     {
       chosen_arch = choose_arch_by_name (val, vallen);
-      if (chosen_arch != NULL && chosen_arch->cp0_names != NULL)
-	mips_cp0_names = chosen_arch->cp0_names;
+      if (chosen_arch != NULL)
+	{
+	  mips_cp0_names = chosen_arch->cp0_names;
+	  mips_cp0sel_names = chosen_arch->cp0sel_names;
+	  mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
+	}
       return;
     }
 
@@ -444,7 +586,7 @@ parse_mips_dis_option (option, len)
       && strlen("hwr-names") == optionlen)
     {
       chosen_arch = choose_arch_by_name (val, vallen);
-      if (chosen_arch != NULL && chosen_arch->hwr_names != NULL)
+      if (chosen_arch != NULL)
 	mips_hwr_names = chosen_arch->hwr_names;
       return;
     }
@@ -459,18 +601,16 @@ parse_mips_dis_option (option, len)
       chosen_abi = choose_abi_by_name (val, vallen);
       if (chosen_abi != NULL)
 	{
-	  if (chosen_abi->gpr_names != NULL)
-	    mips_gpr_names = chosen_abi->gpr_names;
-	  if (chosen_abi->fpr_names != NULL)
-	    mips_fpr_names = chosen_abi->fpr_names;
+	  mips_gpr_names = chosen_abi->gpr_names;
+	  mips_fpr_names = chosen_abi->fpr_names;
 	}
       chosen_arch = choose_arch_by_name (val, vallen);
       if (chosen_arch != NULL)
 	{
-	  if (chosen_arch->cp0_names != NULL)
-	    mips_cp0_names = chosen_arch->cp0_names;
-	  if (chosen_arch->hwr_names != NULL)
-	    mips_hwr_names = chosen_arch->hwr_names;
+	  mips_cp0_names = chosen_arch->cp0_names;
+	  mips_cp0sel_names = chosen_arch->cp0sel_names;
+	  mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
+	  mips_hwr_names = chosen_arch->hwr_names;
 	}
       return;
     }
@@ -509,6 +649,18 @@ parse_mips_dis_options (options)
     }
 }
 
+static const struct mips_cp0sel_name *
+lookup_mips_cp0sel_name(names, len, cp0reg, sel)
+	const struct mips_cp0sel_name *names;
+	unsigned int len, cp0reg, sel;
+{
+  unsigned int i;
+
+  for (i = 0; i < len; i++)
+    if (names[i].cp0reg == cp0reg && names[i].sel == sel)
+      return &names[i];
+  return NULL;
+}
 
 /* Print insn arguments for 32/64-bit code.  */
 
@@ -556,6 +708,28 @@ print_insn_arg (d, l, pc, info)
 				  + 1));
 	  break;
 
+	case 'D':
+	  {
+	    const struct mips_cp0sel_name *n;
+	    unsigned int cp0reg, sel;
+
+	    cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
+	    sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
+
+	    /* CP0 register including 'sel' code for mtcN (et al.), to be
+	       printed textually if known.  If not known, print both
+	       CP0 register name and sel numerically since CP0 register
+	       with sel 0 may have a name unrelated to register being
+	       printed.  */
+	    n = lookup_mips_cp0sel_name(mips_cp0sel_names,
+					mips_cp0sel_names_len, cp0reg, sel);
+	    if (n != NULL)
+	      (*info->fprintf_func) (info->stream, "%s", n->name);
+	    else
+	      (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
+	    break;
+	  }
+
 	default:
 	  /* xgettext:c-format */
 	  (*info->fprintf_func) (info->stream,
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index c35aa06..436420e 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -521,8 +521,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmaccus", "d,s,t",	0x00000469, 0xfc0007ff,	RD_s|RD_t|WR_LO|WR_d,	N412	},
 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       N411    },
 {"dmfc0",   "t,G",	0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,		I3	},
+{"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 	I64     },
 {"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 	I64     },
 {"dmtc0",   "t,G",	0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,	I3	},
+{"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I64     },
 {"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I64     },
 {"dmfc1",   "t,S",	0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,	I3	},
 {"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I3      },
@@ -714,6 +716,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mfpc",    "t,P",	0x4000c801, 0xffe0ffc1,	LCD|WR_t|RD_C0,		M1|N5	},
 {"mfps",    "t,P",	0x4000c800, 0xffe0ffc1,	LCD|WR_t|RD_C0,		M1|N5	},
 {"mfc0",    "t,G",	0x40000000, 0xffe007ff,	LCD|WR_t|RD_C0,		I1	},
+{"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 	I32     },
 {"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 	I32     },
 {"mfc1",    "t,S",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1	},
 {"mfc1",    "t,G",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1	},
@@ -777,6 +780,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtpc",    "t,P",	0x4080c801, 0xffe0ffc1,	COD|RD_t|WR_C0,		M1|N5	},
 {"mtps",    "t,P",	0x4080c800, 0xffe0ffc1,	COD|RD_t|WR_C0,		M1|N5	},
 {"mtc0",    "t,G",	0x40800000, 0xffe007ff,	COD|RD_t|WR_C0|WR_CC,	I1	},
+{"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I32     },
 {"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I32     },
 {"mtc1",    "t,S",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I1	},
 {"mtc1",    "t,G",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I1	},