RISC-V: Add T-Head Bitmanip vendor extension

T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XThead{Ba,Bb,Bs} extensions, a collection of
T-Head-specific bitmanipulation instructions.
The 'th' prefix and the "XThead{Ba,Bb,Bs}" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

20 files changed, 215 insertions, 0 deletions

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index ed516c2..febb84e 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1224,6 +1224,9 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
 
 static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
 {
+  {"xtheadba",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xtheadbb",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xtheadbs",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadcmo",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadsync",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {NULL, 0, 0, 0, 0}
@@ -2388,6 +2391,12 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
       return riscv_subset_supports (rps, "h");
+    case INSN_CLASS_XTHEADBA:
+      return riscv_subset_supports (rps, "xtheadba");
+    case INSN_CLASS_XTHEADBB:
+      return riscv_subset_supports (rps, "xtheadbb");
+    case INSN_CLASS_XTHEADBS:
+      return riscv_subset_supports (rps, "xtheadbs");
     case INSN_CLASS_XTHEADCMO:
       return riscv_subset_supports (rps, "xtheadcmo");
     case INSN_CLASS_XTHEADSYNC:
@@ -2519,6 +2528,12 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "svinval";
     case INSN_CLASS_H:
       return _("h");
+    case INSN_CLASS_XTHEADBA:
+      return "xtheadba";
+    case INSN_CLASS_XTHEADBB:
+      return "xtheadbb";
+    case INSN_CLASS_XTHEADBS:
+      return "xtheadbs";
     case INSN_CLASS_XTHEADCMO:
       return "xtheadcmo";
     case INSN_CLASS_XTHEADSYNC:
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index c55dd0b..570a4f4 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -704,6 +704,21 @@ extensions supported and provides the location of their
 publicly-released documentation:
 
 @table @r
+@item XTheadBa
+The XTheadBa extension provides instructions for address calculations.
+
+It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
+
+@item XTheadBb
+The XTheadBb extension provides instructions for basic bit-manipulation
+
+It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
+
+@item XTheadBs
+The XTheadBs extension provides single-bit instructions.
+
+It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
+
 @item XTheadCmo
 The XTheadCmo extension provides instructions for cache management.
 
diff --git a/gas/testsuite/gas/riscv/x-thead-ba-fail.d b/gas/testsuite/gas/riscv/x-thead-ba-fail.d
new file mode 100644
index 0000000..9fbb935
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-ba-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64i_xtheadba
+#source: x-thead-ba-fail.s
+#error_output: x-thead-ba-fail.l
diff --git a/gas/testsuite/gas/riscv/x-thead-ba-fail.l b/gas/testsuite/gas/riscv/x-thead-ba-fail.l
new file mode 100644
index 0000000..4bb12e7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-ba-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: improper immediate value \(18446744073709551615\)
+.*: Error: improper immediate value \(4\)
diff --git a/gas/testsuite/gas/riscv/x-thead-ba-fail.s b/gas/testsuite/gas/riscv/x-thead-ba-fail.s
new file mode 100644
index 0000000..9a3b27d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-ba-fail.s
@@ -0,0 +1,3 @@
+target:
+	th.addsl	a0, a1, a2, -1
+	th.addsl	a0, a1, a2, 4
diff --git a/gas/testsuite/gas/riscv/x-thead-ba.d b/gas/testsuite/gas/riscv/x-thead-ba.d
new file mode 100644
index 0000000..bf4f8a5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-ba.d
@@ -0,0 +1,13 @@
+#as: -march=rv64i_xtheadba
+#source: x-thead-ba.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+00c5950b[ 	]+th.addsl[ 	]+a0,a1,a2,0
+[ 	]+[0-9a-f]+:[ 	]+02c5950b[ 	]+th.addsl[ 	]+a0,a1,a2,1
+[ 	]+[0-9a-f]+:[ 	]+04c5950b[ 	]+th.addsl[ 	]+a0,a1,a2,2
+[ 	]+[0-9a-f]+:[ 	]+06c5950b[ 	]+th.addsl[ 	]+a0,a1,a2,3
diff --git a/gas/testsuite/gas/riscv/x-thead-ba.s b/gas/testsuite/gas/riscv/x-thead-ba.s
new file mode 100644
index 0000000..5081c06
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-ba.s
@@ -0,0 +1,6 @@
+target:
+	th.addsl	a0, a1, a2, 0
+	th.addsl	a0, a1, a2, 1
+	th.addsl	a0, a1, a2, 2
+	th.addsl	a0, a1, a2, 3
+
diff --git a/gas/testsuite/gas/riscv/x-thead-bb-fail.d b/gas/testsuite/gas/riscv/x-thead-bb-fail.d
new file mode 100644
index 0000000..1dc4c06
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-bb-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64i_xtheadbb
+#source: x-thead-bb-fail.s
+#error_output: x-thead-bb-fail.l
diff --git a/gas/testsuite/gas/riscv/x-thead-bb-fail.l b/gas/testsuite/gas/riscv/x-thead-bb-fail.l
new file mode 100644
index 0000000..dd4a0df
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-bb-fail.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*: Error: improper immediate value \(18446744073709551615\)
+.*: Error: improper immediate value \(64\)
+.*: Error: improper immediate value \(18446744073709551615\)
+.*: Error: improper immediate value \(32\)
+.*: Error: illegal operands `th.ext a0,64,62'
+.*: Error: illegal operands `th.extu a0,-1,0'
diff --git a/gas/testsuite/gas/riscv/x-thead-bb-fail.s b/gas/testsuite/gas/riscv/x-thead-bb-fail.s
new file mode 100644
index 0000000..5b91f50
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-bb-fail.s
@@ -0,0 +1,7 @@
+target:
+	th.srri		a0, a1, -1
+	th.srri		a0, a1, 64
+	th.srriw	a0, a1, -1
+	th.srriw	a0, a1, 32
+	th.ext		a0, 64, 62
+	th.extu		a0, -1, 0
diff --git a/gas/testsuite/gas/riscv/x-thead-bb.d b/gas/testsuite/gas/riscv/x-thead-bb.d
new file mode 100644
index 0000000..3e5547a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-bb.d
@@ -0,0 +1,30 @@
+#as: -march=rv64i_xtheadbb
+#source: x-thead-bb.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+1005950b[ 	]+th.srri[ 	]+a0,a1,0
+[ 	]+[0-9a-f]+:[ 	]+1015950b[ 	]+th.srri[ 	]+a0,a1,1
+[ 	]+[0-9a-f]+:[ 	]+13e5950b[ 	]+th.srri[ 	]+a0,a1,62
+[ 	]+[0-9a-f]+:[ 	]+13f5950b[ 	]+th.srri[ 	]+a0,a1,63
+[ 	]+[0-9a-f]+:[ 	]+1405950b[ 	]+th.srriw[ 	]+a0,a1,0
+[ 	]+[0-9a-f]+:[ 	]+1415950b[ 	]+th.srriw[ 	]+a0,a1,1
+[ 	]+[0-9a-f]+:[ 	]+15e5950b[ 	]+th.srriw[ 	]+a0,a1,30
+[ 	]+[0-9a-f]+:[ 	]+15f5950b[ 	]+th.srriw[ 	]+a0,a1,31
+[ 	]+[0-9a-f]+:[ 	]+0405a50b[ 	]+th.ext[ 	]+a0,a1,1,0
+[ 	]+[0-9a-f]+:[ 	]+7c05a50b[ 	]+th.ext[ 	]+a0,a1,31,0
+[ 	]+[0-9a-f]+:[ 	]+fdf5a50b[ 	]+th.ext[ 	]+a0,a1,63,31
+[ 	]+[0-9a-f]+:[ 	]+ffe5a50b[ 	]+th.ext[ 	]+a0,a1,63,62
+[ 	]+[0-9a-f]+:[ 	]+0405b50b[ 	]+th.extu[ 	]+a0,a1,1,0
+[ 	]+[0-9a-f]+:[ 	]+7c05b50b[ 	]+th.extu[ 	]+a0,a1,31,0
+[ 	]+[0-9a-f]+:[ 	]+fdf5b50b[ 	]+th.extu[ 	]+a0,a1,63,31
+[ 	]+[0-9a-f]+:[ 	]+ffe5b50b[ 	]+th.extu[ 	]+a0,a1,63,62
+[ 	]+[0-9a-f]+:[ 	]+8405950b[ 	]+th.ff0[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+8605950b[ 	]+th.ff1[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+8205950b[ 	]+th.rev[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+9005950b[ 	]+th.revw[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+8005950b[ 	]+th.tstnbz[ 	]+a0,a1
diff --git a/gas/testsuite/gas/riscv/x-thead-bb.s b/gas/testsuite/gas/riscv/x-thead-bb.s
new file mode 100644
index 0000000..e31b3b6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-bb.s
@@ -0,0 +1,22 @@
+target:
+	th.srri		a0, a1, 0
+	th.srri		a0, a1, 1
+	th.srri		a0, a1, 62
+	th.srri		a0, a1, 63
+	th.srriw	a0, a1, 0
+	th.srriw	a0, a1, 1
+	th.srriw	a0, a1, 30
+	th.srriw	a0, a1, 31
+	th.ext		a0, a1, 1, 0
+	th.ext		a0, a1, 31, 0
+	th.ext		a0, a1, 63, 31
+	th.ext		a0, a1, 63, 62
+	th.extu		a0, a1, 1, 0
+	th.extu		a0, a1, 31, 0
+	th.extu		a0, a1, 63, 31
+	th.extu		a0, a1, 63, 62
+	th.ff0		a0, a1
+	th.ff1		a0, a1
+	th.rev		a0, a1
+	th.revw		a0, a1
+	th.tstnbz	a0, a1
diff --git a/gas/testsuite/gas/riscv/x-thead-bs-fail.d b/gas/testsuite/gas/riscv/x-thead-bs-fail.d
new file mode 100644
index 0000000..9326552
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-bs-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64i_xtheadbs
+#source: x-thead-bs-fail.s
+#error_output: x-thead-bs-fail.l
diff --git a/gas/testsuite/gas/riscv/x-thead-bs-fail.l b/gas/testsuite/gas/riscv/x-thead-bs-fail.l
new file mode 100644
index 0000000..c8a7ff4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-bs-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: improper immediate value \(18446744073709551615\)
+.*: Error: improper immediate value \(64\)
diff --git a/gas/testsuite/gas/riscv/x-thead-bs-fail.s b/gas/testsuite/gas/riscv/x-thead-bs-fail.s
new file mode 100644
index 0000000..fbb296e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-bs-fail.s
@@ -0,0 +1,3 @@
+target:
+	th.tst	a0, a1, -1
+	th.tst	a0, a1, 64
diff --git a/gas/testsuite/gas/riscv/x-thead-bs.d b/gas/testsuite/gas/riscv/x-thead-bs.d
new file mode 100644
index 0000000..18cfd28
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-bs.d
@@ -0,0 +1,14 @@
+#as: -march=rv64i_xtheadbs
+#source: x-thead-bs.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+8805950b[ 	]+th.tst[ 	]+a0,a1,0
+[ 	]+[0-9a-f]+:[ 	]+8815950b[ 	]+th.tst[ 	]+a0,a1,1
+[ 	]+[0-9a-f]+:[ 	]+89f5950b[ 	]+th.tst[ 	]+a0,a1,31
+[ 	]+[0-9a-f]+:[ 	]+8a05950b[ 	]+th.tst[ 	]+a0,a1,32
+[ 	]+[0-9a-f]+:[ 	]+8bf5950b[ 	]+th.tst[ 	]+a0,a1,63
diff --git a/gas/testsuite/gas/riscv/x-thead-bs.s b/gas/testsuite/gas/riscv/x-thead-bs.s
new file mode 100644
index 0000000..39db01c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-bs.s
@@ -0,0 +1,6 @@
+target:
+	th.tst	a0, a1, 0
+	th.tst	a0, a1, 1
+	th.tst	a0, a1, 31
+	th.tst	a0, a1, 32
+	th.tst	a0, a1, 63
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 970cdf2..9ed5cb4 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2113,6 +2113,31 @@
 #define MASK_CBO_INVAL 0xfff07fff
 #define MATCH_CBO_ZERO 0x40200f
 #define MASK_CBO_ZERO 0xfff07fff
+/* Vendor-specific (T-Head) XTheadBa instructions.  */
+#define MATCH_TH_ADDSL 0x0000100b
+#define MASK_TH_ADDSL 0xf800707f
+/* Vendor-specific (T-Head) XTheadBb instructions.  */
+#define MATCH_TH_SRRI 0x1000100b
+#define MASK_TH_SRRI 0xfc00707f
+#define MATCH_TH_SRRIW 0x1400100b
+#define MASK_TH_SRRIW 0xfe00707f
+#define MATCH_TH_EXT 0x0000200b
+#define MASK_TH_EXT 0x0000707f
+#define MATCH_TH_EXTU 0x0000300b
+#define MASK_TH_EXTU 0x0000707f
+#define MATCH_TH_FF0 0x8400100b
+#define MASK_TH_FF0 0xfff0707f
+#define MATCH_TH_FF1 0x8600100b
+#define MASK_TH_FF1 0xfff0707f
+#define MATCH_TH_REV 0x8200100b
+#define MASK_TH_REV 0xfff0707f
+#define MATCH_TH_REVW 0x9000100b
+#define MASK_TH_REVW 0xfff0707f
+#define MATCH_TH_TSTNBZ 0x8000100b
+#define MASK_TH_TSTNBZ 0xfff0707f
+/* Vendor-specific (T-Head) XTheadBs instructions.  */
+#define MATCH_TH_TST 0x8800100b
+#define MASK_TH_TST 0xfc00707f
 /* Vendor-specific (T-Head) XTheadCmo instructions.  */
 #define MATCH_TH_DCACHE_CALL 0x0010000b
 #define MASK_TH_DCACHE_CALL 0xffffffff
@@ -2906,6 +2931,20 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN);
 DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
 DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
 DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
+/* Vendor-specific (T-Head) XTheadBa instructions.  */
+DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
+/* Vendor-specific (T-Head) XTheadBb instructions.  */
+DECLARE_INSN(th_srri, MATCH_TH_SRRI, MASK_TH_SRRI)
+DECLARE_INSN(th_srriw, MATCH_TH_SRRIW, MASK_TH_SRRIW)
+DECLARE_INSN(th_ext, MATCH_TH_EXT, MASK_TH_EXT)
+DECLARE_INSN(th_extu, MATCH_TH_EXTU, MASK_TH_EXTU)
+DECLARE_INSN(th_ff0, MATCH_TH_FF0, MASK_TH_FF0)
+DECLARE_INSN(th_ff1, MATCH_TH_FF1, MASK_TH_FF1)
+DECLARE_INSN(th_rev, MATCH_TH_REV, MASK_TH_REV)
+DECLARE_INSN(th_revw, MATCH_TH_REVW, MASK_TH_REVW)
+DECLARE_INSN(th_tstbnz, MATCH_TH_TSTNBZ, MASK_TH_TSTNBZ)
+/* Vendor-specific (T-Head) XTheadBs instructions.  */
+DECLARE_INSN(th_tst, MATCH_TH_TST, MASK_TH_TST)
 /* Vendor-specific (T-Head) XTheadCmo instructions.  */
 DECLARE_INSN(th_dcache_call, MATCH_TH_DCACHE_CALL, MASK_TH_DCACHE_CALL)
 DECLARE_INSN(th_dcache_ciall, MATCH_TH_DCACHE_CIALL, MASK_TH_DCACHE_CIALL)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index faef28a..53b5b3c 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -415,6 +415,9 @@ enum riscv_insn_class
   INSN_CLASS_ZICBOP,
   INSN_CLASS_ZICBOZ,
   INSN_CLASS_H,
+  INSN_CLASS_XTHEADBA,
+  INSN_CLASS_XTHEADBB,
+  INSN_CLASS_XTHEADBS,
   INSN_CLASS_XTHEADCMO,
   INSN_CLASS_XTHEADSYNC,
 };
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 8bba648..6f4a3f8 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1825,6 +1825,23 @@ const struct riscv_opcode riscv_opcodes[] =
 {"hsv.w",       0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
 {"hsv.d",      64, INSN_CLASS_H, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
 
+/* Vendor-specific (T-Head) XTheadBa instructions.  */
+{"th.addsl",    0, INSN_CLASS_XTHEADBA,    "d,s,t,Xu2@25",   MATCH_TH_ADDSL,    MASK_TH_ADDSL,    match_opcode, 0},
+
+/* Vendor-specific (T-Head) XTheadBb instructions.  */
+{"th.srri",     0, INSN_CLASS_XTHEADBB,    "d,s,Xu6@20",   MATCH_TH_SRRI,    MASK_TH_SRRI,     match_opcode, 0},
+{"th.srriw",   64, INSN_CLASS_XTHEADBB,    "d,s,Xu5@20",   MATCH_TH_SRRIW,   MASK_TH_SRRIW,    match_opcode, 0},
+{"th.ext",      0, INSN_CLASS_XTHEADBB,    "d,s,Xu6@26,Xu6@20",   MATCH_TH_EXT,     MASK_TH_EXT,      match_opcode, 0},
+{"th.extu",     0, INSN_CLASS_XTHEADBB,    "d,s,Xu6@26,Xu6@20",   MATCH_TH_EXTU,    MASK_TH_EXTU,     match_opcode, 0},
+{"th.ff0",      0, INSN_CLASS_XTHEADBB,    "d,s",   MATCH_TH_FF0,     MASK_TH_FF0,      match_opcode, 0},
+{"th.ff1",      0, INSN_CLASS_XTHEADBB,    "d,s",   MATCH_TH_FF1,     MASK_TH_FF1,      match_opcode, 0},
+{"th.rev",      0, INSN_CLASS_XTHEADBB,    "d,s",   MATCH_TH_REV,     MASK_TH_REV,      match_opcode, 0},
+{"th.revw",    64, INSN_CLASS_XTHEADBB,    "d,s",   MATCH_TH_REVW,    MASK_TH_REVW,     match_opcode, 0},
+{"th.tstnbz",   0, INSN_CLASS_XTHEADBB,    "d,s",   MATCH_TH_TSTNBZ,  MASK_TH_TSTNBZ,   match_opcode, 0},
+
+/* Vendor-specific (T-Head) XTheadBs instructions.  */
+{"th.tst",      0, INSN_CLASS_XTHEADBS,    "d,s,Xu6@20",   MATCH_TH_TST,     MASK_TH_TST,      match_opcode, 0},
+
 /* Vendor-specific (T-Head) XTheadCmo instructions.  */
 {"th.dcache.call",   0, INSN_CLASS_XTHEADCMO,   "",   MATCH_TH_DCACHE_CALL,   MASK_TH_DCACHE_CALL,   match_opcode, 0},
 {"th.dcache.ciall",  0, INSN_CLASS_XTHEADCMO,   "",   MATCH_TH_DCACHE_CIALL,  MASK_TH_DCACHE_CIALL,  match_opcode, 0},