diff options
| author | Jan Beulich <jbeulich@suse.com> | 2022-12-19 09:22:33 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2022-12-19 09:22:33 +0100 |
| commit | 4fdeb2a3799c0e04ef03b2128c33d756205f7d7d (patch) | |
| tree | 80694148da431e76a780b32317a97466f1021336 | |
| parent | 2a517ca94d30ee7ea34818105a46648432e02fee (diff) | |
| download | gdb-4fdeb2a3799c0e04ef03b2128c33d756205f7d7d.zip gdb-4fdeb2a3799c0e04ef03b2128c33d756205f7d7d.tar.gz gdb-4fdeb2a3799c0e04ef03b2128c33d756205f7d7d.tar.bz2 | |
x86: omit Cpu prefixes from opcode table
These enumerators can be used in only one specific field, and hence the
Cpu prefix isn't needed ther for disambiguation / name space separation.
| -rw-r--r-- | opcodes/i386-gen.c | 695 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 3763 |
2 files changed, 2238 insertions, 2220 deletions
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 101f686..f616318 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -46,435 +46,435 @@ typedef struct initializer static initializer cpu_flag_init[] = { { "CPU_UNKNOWN_FLAGS", - "~CpuIAMCU" }, + "~IAMCU" }, { "CPU_GENERIC32_FLAGS", - "Cpu186|Cpu286|Cpu386" }, + "186|286|386" }, { "CPU_GENERIC64_FLAGS", - "CPU_PENTIUMPRO_FLAGS|CpuClflush|CpuSYSCALL|CPU_MMX_FLAGS|CPU_SSE2_FLAGS|CpuLM" }, + "CPU_PENTIUMPRO_FLAGS|Clflush|SYSCALL|CPU_MMX_FLAGS|CPU_SSE2_FLAGS|LM" }, { "CPU_NONE_FLAGS", "0" }, { "CPU_I186_FLAGS", - "Cpu186" }, + "186" }, { "CPU_I286_FLAGS", - "CPU_I186_FLAGS|Cpu286" }, + "CPU_I186_FLAGS|286" }, { "CPU_I386_FLAGS", - "CPU_I286_FLAGS|Cpu386" }, + "CPU_I286_FLAGS|386" }, { "CPU_I486_FLAGS", - "CPU_I386_FLAGS|Cpu486" }, + "CPU_I386_FLAGS|486" }, { "CPU_I586_FLAGS", - "CPU_I486_FLAGS|Cpu387|Cpu586" }, + "CPU_I486_FLAGS|387|586" }, { "CPU_I686_FLAGS", - "CPU_I586_FLAGS|Cpu686|Cpu687|CpuCMOV|CpuFXSR" }, + "CPU_I586_FLAGS|686|687|CMOV|FXSR" }, { "CPU_PENTIUMPRO_FLAGS", - "CPU_I686_FLAGS|CpuNop" }, + "CPU_I686_FLAGS|Nop" }, { "CPU_P2_FLAGS", "CPU_PENTIUMPRO_FLAGS|CPU_MMX_FLAGS" }, { "CPU_P3_FLAGS", "CPU_P2_FLAGS|CPU_SSE_FLAGS" }, { "CPU_P4_FLAGS", - "CPU_P3_FLAGS|CpuClflush|CPU_SSE2_FLAGS" }, + "CPU_P3_FLAGS|Clflush|CPU_SSE2_FLAGS" }, { "CPU_NOCONA_FLAGS", - "CPU_GENERIC64_FLAGS|CpuFISTTP|CPU_SSE3_FLAGS|CpuCX16" }, + "CPU_GENERIC64_FLAGS|FISTTP|CPU_SSE3_FLAGS|CX16" }, { "CPU_CORE_FLAGS", - "CPU_P4_FLAGS|CpuFISTTP|CPU_SSE3_FLAGS|CpuCX16" }, + "CPU_P4_FLAGS|FISTTP|CPU_SSE3_FLAGS|CX16" }, { "CPU_CORE2_FLAGS", "CPU_NOCONA_FLAGS|CPU_SSSE3_FLAGS" }, { "CPU_COREI7_FLAGS", - "CPU_CORE2_FLAGS|CPU_SSE4_2_FLAGS|CpuRdtscp" }, + "CPU_CORE2_FLAGS|CPU_SSE4_2_FLAGS|Rdtscp" }, { "CPU_K6_FLAGS", - "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuSYSCALL|Cpu387|CPU_MMX_FLAGS" }, + "186|286|386|486|586|SYSCALL|387|CPU_MMX_FLAGS" }, { "CPU_K6_2_FLAGS", - "CPU_K6_FLAGS|Cpu3dnow" }, + "CPU_K6_FLAGS|3dnow" }, { "CPU_ATHLON_FLAGS", - "CPU_K6_2_FLAGS|Cpu686|Cpu687|CpuNop|Cpu3dnowA" }, + "CPU_K6_2_FLAGS|686|687|Nop|3dnowA" }, { "CPU_K8_FLAGS", - "CPU_ATHLON_FLAGS|CpuRdtscp|CPU_SSE2_FLAGS|CpuLM" }, + "CPU_ATHLON_FLAGS|Rdtscp|CPU_SSE2_FLAGS|LM" }, { "CPU_AMDFAM10_FLAGS", - "CPU_K8_FLAGS|CpuFISTTP|CPU_SSE4A_FLAGS|CpuLZCNT|CpuPOPCNT" }, + "CPU_K8_FLAGS|FISTTP|CPU_SSE4A_FLAGS|LZCNT|POPCNT" }, { "CPU_BDVER1_FLAGS", - "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuRdtscp|CpuCX16|CPU_XOP_FLAGS|CpuLZCNT|CpuPOPCNT|CpuLWP|CpuSVME|CpuAES|CpuPCLMUL|CpuPRFCHW" }, + "CPU_GENERIC64_FLAGS|FISTTP|Rdtscp|CX16|CPU_XOP_FLAGS|LZCNT|POPCNT|LWP|SVME|AES|PCLMUL|PRFCHW" }, { "CPU_BDVER2_FLAGS", - "CPU_BDVER1_FLAGS|CpuFMA|CpuBMI|CpuTBM|CpuF16C" }, + "CPU_BDVER1_FLAGS|FMA|BMI|TBM|F16C" }, { "CPU_BDVER3_FLAGS", - "CPU_BDVER2_FLAGS|CpuXsaveopt|CpuFSGSBase" }, + "CPU_BDVER2_FLAGS|Xsaveopt|FSGSBase" }, { "CPU_BDVER4_FLAGS", - "CPU_BDVER3_FLAGS|CpuAVX2|CpuMovbe|CpuBMI2|CpuRdRnd|CpuMWAITX" }, + "CPU_BDVER3_FLAGS|AVX2|Movbe|BMI2|RdRnd|MWAITX" }, { "CPU_ZNVER1_FLAGS", - "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuRdtscp|CpuCX16|CPU_AVX2_FLAGS|CpuSSE4A|CpuLZCNT|CpuPOPCNT|CpuSVME|CpuAES|CpuPCLMUL|CpuPRFCHW|CpuFMA|CpuBMI|CpuF16C|CpuXsaveopt|CpuFSGSBase|CpuMovbe|CpuBMI2|CpuRdRnd|CpuADX|CpuRdSeed|CpuSMAP|CpuSHA|CpuXSAVEC|CpuXSAVES|CpuClflushOpt|CpuCLZERO|CpuMWAITX" }, + "CPU_GENERIC64_FLAGS|FISTTP|Rdtscp|CX16|CPU_AVX2_FLAGS|SSE4A|LZCNT|POPCNT|SVME|AES|PCLMUL|PRFCHW|FMA|BMI|F16C|Xsaveopt|FSGSBase|Movbe|BMI2|RdRnd|ADX|RdSeed|SMAP|SHA|XSAVEC|XSAVES|ClflushOpt|CLZERO|MWAITX" }, { "CPU_ZNVER2_FLAGS", - "CPU_ZNVER1_FLAGS|CpuCLWB|CpuRDPID|CpuRDPRU|CpuMCOMMIT|CpuWBNOINVD" }, + "CPU_ZNVER1_FLAGS|CLWB|RDPID|RDPRU|MCOMMIT|WBNOINVD" }, { "CPU_ZNVER3_FLAGS", - "CPU_ZNVER2_FLAGS|CpuINVLPGB|CpuTLBSYNC|CpuVAES|CpuVPCLMULQDQ|CpuINVPCID|CpuSNP|CpuOSPKE" }, + "CPU_ZNVER2_FLAGS|INVLPGB|TLBSYNC|VAES|VPCLMULQDQ|INVPCID|SNP|OSPKE" }, { "CPU_ZNVER4_FLAGS", - "CPU_ZNVER3_FLAGS|CpuAVX512F|CpuAVX512DQ|CpuAVX512IFMA|CpuAVX512CD|CpuAVX512BW|CpuAVX512VL|CpuAVX512_BF16|CpuAVX512VBMI|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_VPOPCNTDQ|CpuGFNI|CpuRMPQUERY" }, + "CPU_ZNVER3_FLAGS|AVX512F|AVX512DQ|AVX512IFMA|AVX512CD|AVX512BW|AVX512VL|AVX512_BF16|AVX512VBMI|AVX512_VBMI2|AVX512_VNNI|AVX512_BITALG|AVX512_VPOPCNTDQ|GFNI|RMPQUERY" }, { "CPU_BTVER1_FLAGS", - "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuCX16|CpuRdtscp|CPU_SSSE3_FLAGS|CpuSSE4A|CpuLZCNT|CpuPOPCNT|CpuPRFCHW|CpuCX16|CpuClflush|CpuFISTTP|CpuSVME" }, + "CPU_GENERIC64_FLAGS|FISTTP|CX16|Rdtscp|CPU_SSSE3_FLAGS|SSE4A|LZCNT|POPCNT|PRFCHW|CX16|Clflush|FISTTP|SVME" }, { "CPU_BTVER2_FLAGS", - "CPU_BTVER1_FLAGS|CPU_AVX_FLAGS|CpuBMI|CpuF16C|CpuAES|CpuPCLMUL|CpuMovbe|CpuXsaveopt|CpuPRFCHW" }, + "CPU_BTVER1_FLAGS|CPU_AVX_FLAGS|BMI|F16C|AES|PCLMUL|Movbe|Xsaveopt|PRFCHW" }, { "CPU_8087_FLAGS", - "Cpu8087" }, + "8087" }, { "CPU_287_FLAGS", - "Cpu287" }, + "287" }, { "CPU_387_FLAGS", - "Cpu387" }, + "387" }, { "CPU_687_FLAGS", - "CPU_387_FLAGS|Cpu687" }, + "CPU_387_FLAGS|687" }, { "CPU_CMOV_FLAGS", - "CpuCMOV" }, + "CMOV" }, { "CPU_FXSR_FLAGS", - "CpuFXSR" }, + "FXSR" }, { "CPU_CLFLUSH_FLAGS", - "CpuClflush" }, + "Clflush" }, { "CPU_NOP_FLAGS", - "CpuNop" }, + "Nop" }, { "CPU_SYSCALL_FLAGS", - "CpuSYSCALL" }, + "SYSCALL" }, { "CPU_MMX_FLAGS", - "CpuMMX" }, + "MMX" }, { "CPU_SSE_FLAGS", - "CpuSSE" }, + "SSE" }, { "CPU_SSE2_FLAGS", - "CPU_SSE_FLAGS|CpuSSE2" }, + "CPU_SSE_FLAGS|SSE2" }, { "CPU_SSE3_FLAGS", - "CPU_SSE2_FLAGS|CpuSSE3" }, + "CPU_SSE2_FLAGS|SSE3" }, { "CPU_SSSE3_FLAGS", - "CPU_SSE3_FLAGS|CpuSSSE3" }, + "CPU_SSE3_FLAGS|SSSE3" }, { "CPU_SSE4_1_FLAGS", - "CPU_SSSE3_FLAGS|CpuSSE4_1" }, + "CPU_SSSE3_FLAGS|SSE4_1" }, { "CPU_SSE4_2_FLAGS", - "CPU_SSE4_1_FLAGS|CpuSSE4_2|CpuPOPCNT" }, + "CPU_SSE4_1_FLAGS|SSE4_2|POPCNT" }, { "CPU_VMX_FLAGS", - "CpuVMX" }, + "VMX" }, { "CPU_SMX_FLAGS", - "CpuSMX" }, + "SMX" }, { "CPU_XSAVE_FLAGS", - "CpuXsave" }, + "Xsave" }, { "CPU_XSAVEOPT_FLAGS", - "CPU_XSAVE_FLAGS|CpuXsaveopt" }, + "CPU_XSAVE_FLAGS|Xsaveopt" }, { "CPU_AES_FLAGS", - "CPU_SSE2_FLAGS|CpuAES" }, + "CPU_SSE2_FLAGS|AES" }, { "CPU_PCLMUL_FLAGS", - "CPU_SSE2_FLAGS|CpuPCLMUL" }, + "CPU_SSE2_FLAGS|PCLMUL" }, { "CPU_FMA_FLAGS", - "CPU_AVX_FLAGS|CpuFMA" }, + "CPU_AVX_FLAGS|FMA" }, { "CPU_FMA4_FLAGS", - "CPU_AVX_FLAGS|CpuFMA4" }, + "CPU_AVX_FLAGS|FMA4" }, { "CPU_XOP_FLAGS", - "CPU_SSE4A_FLAGS|CPU_FMA4_FLAGS|CpuXOP" }, + "CPU_SSE4A_FLAGS|CPU_FMA4_FLAGS|XOP" }, { "CPU_LWP_FLAGS", - "CPU_XSAVE_FLAGS|CpuLWP" }, + "CPU_XSAVE_FLAGS|LWP" }, { "CPU_BMI_FLAGS", - "CpuBMI" }, + "BMI" }, { "CPU_TBM_FLAGS", - "CpuTBM" }, + "TBM" }, { "CPU_MOVBE_FLAGS", - "CpuMovbe" }, + "Movbe" }, { "CPU_CX16_FLAGS", - "CpuCX16" }, + "CX16" }, { "CPU_RDTSCP_FLAGS", - "CpuRdtscp" }, + "Rdtscp" }, { "CPU_EPT_FLAGS", - "CpuEPT" }, + "EPT" }, { "CPU_FSGSBASE_FLAGS", - "CpuFSGSBase" }, + "FSGSBase" }, { "CPU_RDRND_FLAGS", - "CpuRdRnd" }, + "RdRnd" }, { "CPU_F16C_FLAGS", - "CPU_AVX_FLAGS|CpuF16C" }, + "CPU_AVX_FLAGS|F16C" }, { "CPU_BMI2_FLAGS", - "CpuBMI2" }, + "BMI2" }, { "CPU_LZCNT_FLAGS", - "CpuLZCNT" }, + "LZCNT" }, { "CPU_POPCNT_FLAGS", - "CpuPOPCNT" }, + "POPCNT" }, { "CPU_HLE_FLAGS", - "CpuHLE" }, + "HLE" }, { "CPU_RTM_FLAGS", - "CpuRTM" }, + "RTM" }, { "CPU_INVPCID_FLAGS", - "CpuINVPCID" }, + "INVPCID" }, { "CPU_VMFUNC_FLAGS", - "CpuVMFUNC" }, + "VMFUNC" }, { "CPU_3DNOW_FLAGS", - "CPU_MMX_FLAGS|Cpu3dnow" }, + "CPU_MMX_FLAGS|3dnow" }, { "CPU_3DNOWA_FLAGS", - "CPU_3DNOW_FLAGS|Cpu3dnowA" }, + "CPU_3DNOW_FLAGS|3dnowA" }, { "CPU_PADLOCK_FLAGS", - "CpuPadLock" }, + "PadLock" }, { "CPU_SVME_FLAGS", - "CpuSVME" }, + "SVME" }, { "CPU_SSE4A_FLAGS", - "CPU_SSE3_FLAGS|CpuSSE4a" }, + "CPU_SSE3_FLAGS|SSE4a" }, { "CPU_ABM_FLAGS", - "CpuLZCNT|CpuPOPCNT" }, + "LZCNT|POPCNT" }, { "CPU_AVX_FLAGS", - "CPU_SSE4_2_FLAGS|CPU_XSAVE_FLAGS|CpuAVX" }, + "CPU_SSE4_2_FLAGS|CPU_XSAVE_FLAGS|AVX" }, { "CPU_AVX2_FLAGS", - "CPU_AVX_FLAGS|CpuAVX2" }, + "CPU_AVX_FLAGS|AVX2" }, { "CPU_AVX_VNNI_FLAGS", - "CPU_AVX2_FLAGS|CpuAVX_VNNI" }, + "CPU_AVX2_FLAGS|AVX_VNNI" }, { "CPU_AVX512F_FLAGS", - "CPU_AVX2_FLAGS|CpuAVX512F" }, + "CPU_AVX2_FLAGS|AVX512F" }, { "CPU_AVX512CD_FLAGS", - "CPU_AVX512F_FLAGS|CpuAVX512CD" }, + "CPU_AVX512F_FLAGS|AVX512CD" }, { "CPU_AVX512ER_FLAGS", - "CPU_AVX512F_FLAGS|CpuAVX512ER" }, + "CPU_AVX512F_FLAGS|AVX512ER" }, { "CPU_AVX512PF_FLAGS", - "CPU_AVX512F_FLAGS|CpuAVX512PF" }, + "CPU_AVX512F_FLAGS|AVX512PF" }, { "CPU_AVX512DQ_FLAGS", - "CPU_AVX512F_FLAGS|CpuAVX512DQ" }, + "CPU_AVX512F_FLAGS|AVX512DQ" }, { "CPU_AVX512BW_FLAGS", - "CPU_AVX512F_FLAGS|CpuAVX512BW" }, + "CPU_AVX512F_FLAGS|AVX512BW" }, { "CPU_AVX512VL_FLAGS", - "CPU_AVX512F_FLAGS|CpuAVX512VL" }, + "CPU_AVX512F_FLAGS|AVX512VL" }, { "CPU_AVX512IFMA_FLAGS", - "CPU_AVX512F_FLAGS|CpuAVX512IFMA" }, + "CPU_AVX512F_FLAGS|AVX512IFMA" }, { "CPU_AVX512VBMI_FLAGS", - "CPU_AVX512F_FLAGS|CpuAVX512VBMI" }, + "CPU_AVX512F_FLAGS|AVX512VBMI" }, { "CPU_AVX512_4FMAPS_FLAGS", - "CPU_AVX512F_FLAGS|CpuAVX512_4FMAPS" }, + "CPU_AVX512F_FLAGS|AVX512_4FMAPS" }, { "CPU_AVX512_4VNNIW_FLAGS", - "CPU_AVX512F_FLAGS|CpuAVX512_4VNNIW" }, + "CPU_AVX512F_FLAGS|AVX512_4VNNIW" }, { "CPU_AVX512_VPOPCNTDQ_FLAGS", - "CPU_AVX512F_FLAGS|CpuAVX512_VPOPCNTDQ" }, + "CPU_AVX512F_FLAGS|AVX512_VPOPCNTDQ" }, { "CPU_AVX512_VBMI2_FLAGS", - "CPU_AVX512F_FLAGS|CpuAVX512_VBMI2" }, + "CPU_AVX512F_FLAGS|AVX512_VBMI2" }, { "CPU_AVX512_VNNI_FLAGS", - "CPU_AVX512F_FLAGS|CpuAVX512_VNNI" }, + "CPU_AVX512F_FLAGS|AVX512_VNNI" }, { "CPU_AVX512_BITALG_FLAGS", - "CPU_AVX512F_FLAGS|CpuAVX512_BITALG" }, + "CPU_AVX512F_FLAGS|AVX512_BITALG" }, { "CPU_AVX512_BF16_FLAGS", - "CPU_AVX512F_FLAGS|CpuAVX512_BF16" }, + "CPU_AVX512F_FLAGS|AVX512_BF16" }, { "CPU_AVX512_FP16_FLAGS", - "CPU_AVX512BW_FLAGS|CpuAVX512_FP16" }, + "CPU_AVX512BW_FLAGS|AVX512_FP16" }, { "CPU_PREFETCHI_FLAGS", - "CpuPREFETCHI"}, + "PREFETCHI"}, { "CPU_AVX_IFMA_FLAGS", - "CPU_AVX2_FLAGS|CpuAVX_IFMA" }, + "CPU_AVX2_FLAGS|AVX_IFMA" }, { "CPU_AVX_VNNI_INT8_FLAGS", - "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" }, + "CPU_AVX2_FLAGS|AVX_VNNI_INT8" }, { "CPU_CMPCCXADD_FLAGS", - "CpuCMPCCXADD" }, + "CMPCCXADD" }, { "CPU_WRMSRNS_FLAGS", - "CpuWRMSRNS" }, + "WRMSRNS" }, { "CPU_MSRLIST_FLAGS", - "CpuMSRLIST" }, + "MSRLIST" }, { "CPU_AVX_NE_CONVERT_FLAGS", - "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" }, + "CPU_AVX2_FLAGS|AVX_NE_CONVERT" }, { "CPU_RAO_INT_FLAGS", - "CpuRAO_INT" }, + "RAO_INT" }, { "CPU_IAMCU_FLAGS", - "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, + "186|286|386|486|586|IAMCU" }, { "CPU_ADX_FLAGS", - "CpuADX" }, + "ADX" }, { "CPU_RDSEED_FLAGS", - "CpuRdSeed" }, + "RdSeed" }, { "CPU_PRFCHW_FLAGS", - "CpuPRFCHW" }, + "PRFCHW" }, { "CPU_SMAP_FLAGS", - "CpuSMAP" }, + "SMAP" }, { "CPU_MPX_FLAGS", - "CPU_XSAVE_FLAGS|CpuMPX" }, + "CPU_XSAVE_FLAGS|MPX" }, { "CPU_SHA_FLAGS", - "CPU_SSE2_FLAGS|CpuSHA" }, + "CPU_SSE2_FLAGS|SHA" }, { "CPU_CLFLUSHOPT_FLAGS", - "CpuClflushOpt" }, + "ClflushOpt" }, { "CPU_XSAVES_FLAGS", - "CPU_XSAVE_FLAGS|CpuXSAVES" }, + "CPU_XSAVE_FLAGS|XSAVES" }, { "CPU_XSAVEC_FLAGS", - "CPU_XSAVE_FLAGS|CpuXSAVEC" }, + "CPU_XSAVE_FLAGS|XSAVEC" }, { "CPU_PREFETCHWT1_FLAGS", - "CpuPREFETCHWT1" }, + "PREFETCHWT1" }, { "CPU_SE1_FLAGS", - "CpuSE1" }, + "SE1" }, { "CPU_CLWB_FLAGS", - "CpuCLWB" }, + "CLWB" }, { "CPU_CLZERO_FLAGS", - "CpuCLZERO" }, + "CLZERO" }, { "CPU_MWAITX_FLAGS", - "CpuMWAITX" }, + "MWAITX" }, { "CPU_OSPKE_FLAGS", - "CPU_XSAVE_FLAGS|CpuOSPKE" }, + "CPU_XSAVE_FLAGS|OSPKE" }, { "CPU_RDPID_FLAGS", - "CpuRDPID" }, + "RDPID" }, { "CPU_PTWRITE_FLAGS", - "CpuPTWRITE" }, + "PTWRITE" }, { "CPU_IBT_FLAGS", - "CpuIBT" }, + "IBT" }, { "CPU_SHSTK_FLAGS", - "CpuSHSTK" }, + "SHSTK" }, { "CPU_GFNI_FLAGS", - "CpuGFNI" }, + "GFNI" }, { "CPU_VAES_FLAGS", - "CpuVAES" }, + "VAES" }, { "CPU_VPCLMULQDQ_FLAGS", - "CpuVPCLMULQDQ" }, + "VPCLMULQDQ" }, { "CPU_WBNOINVD_FLAGS", - "CpuWBNOINVD" }, + "WBNOINVD" }, { "CPU_PCONFIG_FLAGS", - "CpuPCONFIG" }, + "PCONFIG" }, { "CPU_WAITPKG_FLAGS", - "CpuWAITPKG" }, + "WAITPKG" }, { "CPU_UINTR_FLAGS", - "CpuUINTR" }, + "UINTR" }, { "CPU_CLDEMOTE_FLAGS", - "CpuCLDEMOTE" }, + "CLDEMOTE" }, { "CPU_AMX_INT8_FLAGS", - "CPU_AMX_TILE_FLAGS|CpuAMX_INT8" }, + "CPU_AMX_TILE_FLAGS|AMX_INT8" }, { "CPU_AMX_BF16_FLAGS", - "CPU_AMX_TILE_FLAGS|CpuAMX_BF16" }, + "CPU_AMX_TILE_FLAGS|AMX_BF16" }, { "CPU_AMX_FP16_FLAGS", - "CPU_AMX_TILE_FLAGS|CpuAMX_FP16" }, + "CPU_AMX_TILE_FLAGS|AMX_FP16" }, { "CPU_AMX_TILE_FLAGS", - "CpuAMX_TILE" }, + "AMX_TILE" }, { "CPU_MOVDIRI_FLAGS", - "CpuMOVDIRI" }, + "MOVDIRI" }, { "CPU_MOVDIR64B_FLAGS", - "CpuMOVDIR64B" }, + "MOVDIR64B" }, { "CPU_ENQCMD_FLAGS", - "CpuENQCMD" }, + "ENQCMD" }, { "CPU_SERIALIZE_FLAGS", - "CpuSERIALIZE" }, + "SERIALIZE" }, { "CPU_AVX512_VP2INTERSECT_FLAGS", - "CpuAVX512_VP2INTERSECT" }, + "AVX512_VP2INTERSECT" }, { "CPU_TDX_FLAGS", - "CpuTDX" }, + "TDX" }, { "CPU_RDPRU_FLAGS", - "CpuRDPRU" }, + "RDPRU" }, { "CPU_MCOMMIT_FLAGS", - "CpuMCOMMIT" }, + "MCOMMIT" }, { "CPU_SEV_ES_FLAGS", - "CpuSEV_ES" }, + "SEV_ES" }, { "CPU_TSXLDTRK_FLAGS", - "CpuTSXLDTRK"}, + "TSXLDTRK"}, { "CPU_KL_FLAGS", - "CpuKL" }, + "KL" }, { "CPU_WIDEKL_FLAGS", - "CpuWideKL" }, + "WideKL" }, { "CPU_HRESET_FLAGS", - "CpuHRESET"}, + "HRESET"}, { "CPU_INVLPGB_FLAGS", - "CpuINVLPGB" }, + "INVLPGB" }, { "CPU_TLBSYNC_FLAGS", - "CpuTLBSYNC" }, + "TLBSYNC" }, { "CPU_SNP_FLAGS", - "CpuSNP" }, + "SNP" }, { "CPU_RMPQUERY_FLAGS", - "CpuRMPQUERY" }, + "RMPQUERY" }, { "CPU_ANY_X87_FLAGS", - "CPU_ANY_287_FLAGS|Cpu8087" }, + "CPU_ANY_287_FLAGS|8087" }, { "CPU_ANY_287_FLAGS", - "CPU_ANY_387_FLAGS|Cpu287" }, + "CPU_ANY_387_FLAGS|287" }, { "CPU_ANY_387_FLAGS", - "CPU_ANY_687_FLAGS|Cpu387" }, + "CPU_ANY_687_FLAGS|387" }, { "CPU_ANY_687_FLAGS", - "Cpu687|CpuFISTTP" }, + "687|FISTTP" }, { "CPU_ANY_CMOV_FLAGS", - "CpuCMOV" }, + "CMOV" }, { "CPU_ANY_FXSR_FLAGS", - "CpuFXSR" }, + "FXSR" }, { "CPU_ANY_MMX_FLAGS", "CPU_3DNOWA_FLAGS" }, { "CPU_ANY_SSE_FLAGS", - "CPU_ANY_SSE2_FLAGS|CpuSSE" }, + "CPU_ANY_SSE2_FLAGS|SSE" }, { "CPU_ANY_SSE2_FLAGS", - "CPU_ANY_SSE3_FLAGS|CpuSSE2" }, + "CPU_ANY_SSE3_FLAGS|SSE2" }, { "CPU_ANY_SSE3_FLAGS", - "CPU_ANY_SSSE3_FLAGS|CpuSSE3|CpuSSE4a" }, + "CPU_ANY_SSSE3_FLAGS|SSE3|SSE4a" }, { "CPU_ANY_SSSE3_FLAGS", - "CPU_ANY_SSE4_1_FLAGS|CpuSSSE3" }, + "CPU_ANY_SSE4_1_FLAGS|SSSE3" }, { "CPU_ANY_SSE4_1_FLAGS", - "CPU_ANY_SSE4_2_FLAGS|CpuSSE4_1" }, + "CPU_ANY_SSE4_2_FLAGS|SSE4_1" }, { "CPU_ANY_SSE4_2_FLAGS", - "CpuSSE4_2" }, + "SSE4_2" }, { "CPU_ANY_SSE4A_FLAGS", - "CpuSSE4a" }, + "SSE4a" }, { "CPU_ANY_AVX_FLAGS", - "CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" }, + "CPU_ANY_AVX2_FLAGS|F16C|FMA|FMA4|XOP|AVX" }, { "CPU_ANY_AVX2_FLAGS", - "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA|CpuAVX_VNNI_INT8|CpuAVX_NE_CONVERT" }, + "CPU_ANY_AVX512F_FLAGS|AVX2|AVX_VNNI|AVX_IFMA|AVX_VNNI_INT8|AVX_NE_CONVERT" }, { "CPU_ANY_AVX512F_FLAGS", - "CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CPU_ANY_AVX512BW_FLAGS|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_BF16|CpuAVX512_VP2INTERSECT" }, + "AVX512F|AVX512CD|AVX512ER|AVX512PF|AVX512DQ|CPU_ANY_AVX512BW_FLAGS|AVX512VL|AVX512IFMA|AVX512VBMI|AVX512_4FMAPS|AVX512_4VNNIW|AVX512_VPOPCNTDQ|AVX512_VBMI2|AVX512_VNNI|AVX512_BITALG|AVX512_BF16|AVX512_VP2INTERSECT" }, { "CPU_ANY_AVX512CD_FLAGS", - "CpuAVX512CD" }, + "AVX512CD" }, { "CPU_ANY_AVX512ER_FLAGS", - "CpuAVX512ER" }, + "AVX512ER" }, { "CPU_ANY_AVX512PF_FLAGS", - "CpuAVX512PF" }, + "AVX512PF" }, { "CPU_ANY_AVX512DQ_FLAGS", - "CpuAVX512DQ" }, + "AVX512DQ" }, { "CPU_ANY_AVX512BW_FLAGS", - "CpuAVX512BW|CPU_ANY_AVX512_FP16_FLAGS" }, + "AVX512BW|CPU_ANY_AVX512_FP16_FLAGS" }, { "CPU_ANY_AVX512VL_FLAGS", - "CpuAVX512VL" }, + "AVX512VL" }, { "CPU_ANY_AVX512IFMA_FLAGS", - "CpuAVX512IFMA" }, + "AVX512IFMA" }, { "CPU_ANY_AVX512VBMI_FLAGS", - "CpuAVX512VBMI" }, + "AVX512VBMI" }, { "CPU_ANY_AVX512_4FMAPS_FLAGS", - "CpuAVX512_4FMAPS" }, + "AVX512_4FMAPS" }, { "CPU_ANY_AVX512_4VNNIW_FLAGS", - "CpuAVX512_4VNNIW" }, + "AVX512_4VNNIW" }, { "CPU_ANY_AVX512_VPOPCNTDQ_FLAGS", - "CpuAVX512_VPOPCNTDQ" }, + "AVX512_VPOPCNTDQ" }, { "CPU_ANY_IBT_FLAGS", - "CpuIBT" }, + "IBT" }, { "CPU_ANY_SHSTK_FLAGS", - "CpuSHSTK" }, + "SHSTK" }, { "CPU_ANY_AVX512_VBMI2_FLAGS", - "CpuAVX512_VBMI2" }, + "AVX512_VBMI2" }, { "CPU_ANY_AVX512_VNNI_FLAGS", - "CpuAVX512_VNNI" }, + "AVX512_VNNI" }, { "CPU_ANY_AVX512_BITALG_FLAGS", - "CpuAVX512_BITALG" }, + "AVX512_BITALG" }, { "CPU_ANY_AVX512_BF16_FLAGS", - "CpuAVX512_BF16" }, + "AVX512_BF16" }, { "CPU_ANY_AMX_INT8_FLAGS", - "CpuAMX_INT8" }, + "AMX_INT8" }, { "CPU_ANY_AMX_BF16_FLAGS", - "CpuAMX_BF16" }, + "AMX_BF16" }, { "CPU_ANY_AMX_TILE_FLAGS", - "CpuAMX_TILE|CpuAMX_INT8|CpuAMX_BF16|CpuAMX_FP16" }, + "AMX_TILE|AMX_INT8|AMX_BF16|AMX_FP16" }, { "CPU_ANY_AVX_VNNI_FLAGS", - "CpuAVX_VNNI" }, + "AVX_VNNI" }, { "CPU_ANY_MOVDIRI_FLAGS", - "CpuMOVDIRI" }, + "MOVDIRI" }, { "CPU_ANY_UINTR_FLAGS", - "CpuUINTR" }, + "UINTR" }, { "CPU_ANY_MOVDIR64B_FLAGS", - "CpuMOVDIR64B" }, + "MOVDIR64B" }, { "CPU_ANY_ENQCMD_FLAGS", - "CpuENQCMD" }, + "ENQCMD" }, { "CPU_ANY_SERIALIZE_FLAGS", - "CpuSERIALIZE" }, + "SERIALIZE" }, { "CPU_ANY_AVX512_VP2INTERSECT_FLAGS", - "CpuAVX512_VP2INTERSECT" }, + "AVX512_VP2INTERSECT" }, { "CPU_ANY_TDX_FLAGS", - "CpuTDX" }, + "TDX" }, { "CPU_ANY_TSXLDTRK_FLAGS", - "CpuTSXLDTRK" }, + "TSXLDTRK" }, { "CPU_ANY_KL_FLAGS", - "CpuKL|CpuWideKL" }, + "KL|WideKL" }, { "CPU_ANY_WIDEKL_FLAGS", - "CpuWideKL" }, + "WideKL" }, { "CPU_ANY_HRESET_FLAGS", - "CpuHRESET" }, + "HRESET" }, { "CPU_ANY_AVX512_FP16_FLAGS", - "CpuAVX512_FP16" }, + "AVX512_FP16" }, { "CPU_ANY_AVX_IFMA_FLAGS", - "CpuAVX_IFMA" }, + "AVX_IFMA" }, { "CPU_ANY_AVX_VNNI_INT8_FLAGS", - "CpuAVX_VNNI_INT8" }, + "AVX_VNNI_INT8" }, { "CPU_ANY_CMPCCXADD_FLAGS", - "CpuCMPCCXADD" }, + "CMPCCXADD" }, { "CPU_ANY_WRMSRNS_FLAGS", - "CpuWRMSRNS" }, + "WRMSRNS" }, { "CPU_ANY_MSRLIST_FLAGS", - "CpuMSRLIST" }, + "MSRLIST" }, { "CPU_ANY_AVX_NE_CONVERT_FLAGS", - "CpuAVX_NE_CONVERT" }, + "AVX_NE_CONVERT" }, { "CPU_ANY_RAO_INT_FLAGS", - "CpuRAO_INT"}, + "RAO_INT"}, }; typedef struct bitfield @@ -484,149 +484,152 @@ typedef struct bitfield const char *name; } bitfield; -#define BITFIELD(n) { n, 0, #n } +#define BITFIELD(n) { Cpu##n, 0, #n } static bitfield cpu_flags[] = { - BITFIELD (Cpu186), - BITFIELD (Cpu286), - BITFIELD (Cpu386), - BITFIELD (Cpu486), - BITFIELD (Cpu586), - BITFIELD (Cpu686), - BITFIELD (CpuCMOV), - BITFIELD (CpuFXSR), - BITFIELD (CpuClflush), - BITFIELD (CpuNop), - BITFIELD (CpuSYSCALL), - BITFIELD (Cpu8087), - BITFIELD (Cpu287), - BITFIELD (Cpu387), - BITFIELD (Cpu687), - BITFIELD (CpuFISTTP), - BITFIELD (CpuMMX), - BITFIELD (CpuSSE), - BITFIELD (CpuSSE2), - BITFIELD (CpuSSE3), - BITFIELD (CpuSSSE3), - BITFIELD (CpuSSE4_1), - BITFIELD (CpuSSE4_2), - BITFIELD (CpuAVX), - BITFIELD (CpuAVX2), - BITFIELD (CpuAVX512F), - BITFIELD (CpuAVX512CD), - BITFIELD (CpuAVX512ER), - BITFIELD (CpuAVX512PF), - BITFIELD (CpuAVX512VL), - BITFIELD (CpuAVX512DQ), - BITFIELD (CpuAVX512BW), - BITFIELD (CpuIAMCU), - BITFIELD (CpuSSE4a), - BITFIELD (Cpu3dnow), - BITFIELD (Cpu3dnowA), - BITFIELD (CpuPadLock), - BITFIELD (CpuSVME), - BITFIELD (CpuVMX), - BITFIELD (CpuSMX), - BITFIELD (CpuXsave), - BITFIELD (CpuXsaveopt), - BITFIELD (CpuAES), - BITFIELD (CpuPCLMUL), - BITFIELD (CpuFMA), - BITFIELD (CpuFMA4), - BITFIELD (CpuXOP), - BITFIELD (CpuLWP), - BITFIELD (CpuBMI), - BITFIELD (CpuTBM), - BITFIELD (CpuLM), - BITFIELD (CpuMovbe), - BITFIELD (CpuCX16), - BITFIELD (CpuEPT), - BITFIELD (CpuRdtscp), - BITFIELD (CpuFSGSBase), - BITFIELD (CpuRdRnd), - BITFIELD (CpuF16C), - BITFIELD (CpuBMI2), - BITFIELD (CpuLZCNT), - BITFIELD (CpuPOPCNT), - BITFIELD (CpuHLE), - BITFIELD (CpuRTM), - BITFIELD (CpuINVPCID), - BITFIELD (CpuVMFUNC), - BITFIELD (CpuRDSEED), - BITFIELD (CpuADX), - BITFIELD (CpuPRFCHW), - BITFIELD (CpuSMAP), - BITFIELD (CpuSHA), - BITFIELD (CpuClflushOpt), - BITFIELD (CpuXSAVES), - BITFIELD (CpuXSAVEC), - BITFIELD (CpuPREFETCHWT1), - BITFIELD (CpuSE1), - BITFIELD (CpuCLWB), - BITFIELD (CpuMPX), - BITFIELD (CpuAVX512IFMA), - BITFIELD (CpuAVX512VBMI), - BITFIELD (CpuAVX512_4FMAPS), - BITFIELD (CpuAVX512_4VNNIW), - BITFIELD (CpuAVX512_VPOPCNTDQ), - BITFIELD (CpuAVX512_VBMI2), - BITFIELD (CpuAVX512_VNNI), - BITFIELD (CpuAVX512_BITALG), - BITFIELD (CpuAVX512_BF16), - BITFIELD (CpuAVX512_VP2INTERSECT), - BITFIELD (CpuTDX), - BITFIELD (CpuAVX_VNNI), - BITFIELD (CpuAVX512_FP16), - BITFIELD (CpuPREFETCHI), - BITFIELD (CpuAVX_IFMA), - BITFIELD (CpuAVX_VNNI_INT8), - BITFIELD (CpuCMPCCXADD), - BITFIELD (CpuWRMSRNS), - BITFIELD (CpuMSRLIST), - BITFIELD (CpuAVX_NE_CONVERT), - BITFIELD (CpuRAO_INT), - BITFIELD (CpuMWAITX), - BITFIELD (CpuCLZERO), - BITFIELD (CpuOSPKE), - BITFIELD (CpuRDPID), - BITFIELD (CpuPTWRITE), - BITFIELD (CpuIBT), - BITFIELD (CpuSHSTK), - BITFIELD (CpuGFNI), - BITFIELD (CpuVAES), - BITFIELD (CpuVPCLMULQDQ), - BITFIELD (CpuWBNOINVD), - BITFIELD (CpuPCONFIG), - BITFIELD (CpuWAITPKG), - BITFIELD (CpuUINTR), - BITFIELD (CpuCLDEMOTE), - BITFIELD (CpuAMX_INT8), - BITFIELD (CpuAMX_BF16), - BITFIELD (CpuAMX_FP16), - BITFIELD (CpuAMX_TILE), - BITFIELD (CpuMOVDIRI), - BITFIELD (CpuMOVDIR64B), - BITFIELD (CpuENQCMD), - BITFIELD (CpuSERIALIZE), - BITFIELD (CpuRDPRU), - BITFIELD (CpuMCOMMIT), - BITFIELD (CpuSEV_ES), - BITFIELD (CpuTSXLDTRK), - BITFIELD (CpuKL), - BITFIELD (CpuWideKL), - BITFIELD (CpuHRESET), - BITFIELD (CpuINVLPGB), - BITFIELD (CpuTLBSYNC), - BITFIELD (CpuSNP), - BITFIELD (CpuRMPQUERY), - BITFIELD (Cpu64), - BITFIELD (CpuNo64), + BITFIELD (186), + BITFIELD (286), + BITFIELD (386), + BITFIELD (486), + BITFIELD (586), + BITFIELD (686), + BITFIELD (CMOV), + BITFIELD (FXSR), + BITFIELD (Clflush), + BITFIELD (Nop), + BITFIELD (SYSCALL), + BITFIELD (8087), + BITFIELD (287), + BITFIELD (387), + BITFIELD (687), + BITFIELD (FISTTP), + BITFIELD (MMX), + BITFIELD (SSE), + BITFIELD (SSE2), + BITFIELD (SSE3), + BITFIELD (SSSE3), + BITFIELD (SSE4_1), + BITFIELD (SSE4_2), + BITFIELD (AVX), + BITFIELD (AVX2), + BITFIELD (AVX512F), + BITFIELD (AVX512CD), + BITFIELD (AVX512ER), + BITFIELD (AVX512PF), + BITFIELD (AVX512VL), + BITFIELD (AVX512DQ), + BITFIELD (AVX512BW), + BITFIELD (IAMCU), + BITFIELD (SSE4a), + BITFIELD (3dnow), + BITFIELD (3dnowA), + BITFIELD (PadLock), + BITFIELD (SVME), + BITFIELD (VMX), + BITFIELD (SMX), + BITFIELD (Xsave), + BITFIELD (Xsaveopt), + BITFIELD (AES), + BITFIELD (PCLMUL), + BITFIELD (FMA), + BITFIELD (FMA4), + BITFIELD (XOP), + BITFIELD (LWP), + BITFIELD (BMI), + BITFIELD (TBM), + BITFIELD (LM), + BITFIELD (Movbe), + BITFIELD (CX16), + BITFIELD (EPT), + BITFIELD (Rdtscp), + BITFIELD (FSGSBase), + BITFIELD (RdRnd), + BITFIELD (F16C), + BITFIELD (BMI2), + BITFIELD (LZCNT), + BITFIELD (POPCNT), + BITFIELD (HLE), + BITFIELD (RTM), + BITFIELD (INVPCID), + BITFIELD (VMFUNC), + BITFIELD (RDSEED), + BITFIELD (ADX), + BITFIELD (PRFCHW), + BITFIELD (SMAP), + BITFIELD (SHA), + BITFIELD (ClflushOpt), + BITFIELD (XSAVES), + BITFIELD (XSAVEC), + BITFIELD (PREFETCHWT1), + BITFIELD (SE1), + BITFIELD (CLWB), + BITFIELD (MPX), + BITFIELD (AVX512IFMA), + BITFIELD (AVX512VBMI), + BITFIELD (AVX512_4FMAPS), + BITFIELD (AVX512_4VNNIW), + BITFIELD (AVX512_VPOPCNTDQ), + BITFIELD (AVX512_VBMI2), + BITFIELD (AVX512_VNNI), + BITFIELD (AVX512_BITALG), + BITFIELD (AVX512_BF16), + BITFIELD (AVX512_VP2INTERSECT), + BITFIELD (TDX), + BITFIELD (AVX_VNNI), + BITFIELD (AVX512_FP16), + BITFIELD (PREFETCHI), + BITFIELD (AVX_IFMA), + BITFIELD (AVX_VNNI_INT8), + BITFIELD (CMPCCXADD), + BITFIELD (WRMSRNS), + BITFIELD (MSRLIST), + BITFIELD (AVX_NE_CONVERT), + BITFIELD (RAO_INT), + BITFIELD (MWAITX), + BITFIELD (CLZERO), + BITFIELD (OSPKE), + BITFIELD (RDPID), + BITFIELD (PTWRITE), + BITFIELD (IBT), + BITFIELD (SHSTK), + BITFIELD (GFNI), + BITFIELD (VAES), + BITFIELD (VPCLMULQDQ), + BITFIELD (WBNOINVD), + BITFIELD (PCONFIG), + BITFIELD (WAITPKG), + BITFIELD (UINTR), + BITFIELD (CLDEMOTE), + BITFIELD (AMX_INT8), + BITFIELD (AMX_BF16), + BITFIELD (AMX_FP16), + BITFIELD (AMX_TILE), + BITFIELD (MOVDIRI), + BITFIELD (MOVDIR64B), + BITFIELD (ENQCMD), + BITFIELD (SERIALIZE), + BITFIELD (RDPRU), + BITFIELD (MCOMMIT), + BITFIELD (SEV_ES), + BITFIELD (TSXLDTRK), + BITFIELD (KL), + BITFIELD (WideKL), + BITFIELD (HRESET), + BITFIELD (INVLPGB), + BITFIELD (TLBSYNC), + BITFIELD (SNP), + BITFIELD (RMPQUERY), + BITFIELD (64), + BITFIELD (No64), #ifdef CpuUnused - BITFIELD (CpuUnused), + BITFIELD (Unused), #endif }; +#undef BITFIELD +#define BITFIELD(n) { n, 0, #n } + static bitfield opcode_modifiers[] = { BITFIELD (D), diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 44a8ca3..a477d5b 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -136,21 +136,36 @@ // operands may allow to switch from 3-byte to 2-byte VEX encoding. #define C StaticRounding -#define CpuFP Cpu387|Cpu287|Cpu8087 +#define FP 387|287|8087 + +// To avoid CPU specifiers to look like plain number tokens in the table, +// introduce some aliases. +#define i186 186 +#define i286 286 +#undef i386 +#define i386 386 +#define i486 486 +#define i586 586 +#define i686 686 +#define i8087 8087 +#define i287 287 +#define i387 387 +#define i687 687 +#define x64 64 ### MARKER ### // Move instructions. -mov, 0xa0, CpuNo64, D|W|CheckRegSize|No_sSuf|No_qSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword } -mov, 0xa0, Cpu64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } -movabs, 0xa0, Cpu64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } +mov, 0xa0, No64, D|W|CheckRegSize|No_sSuf|No_qSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword } +mov, 0xa0, x64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } +movabs, 0xa0, x64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } mov, 0x88, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixRelease, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } // In the 64bit mode the short form mov immediate is redefined to have // 64bit value. mov, 0xb0, 0, W|No_sSuf|No_qSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32 } mov, 0xc6/0, 0, W|Modrm|No_sSuf|HLEPrefixRelease|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -mov, 0xb8, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|Optimize, { Imm64, Reg64 } -movabs, 0xb8, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Imm64, Reg64 } +mov, 0xb8, x64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|Optimize, { Imm64, Reg64 } +movabs, 0xb8, x64, No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Imm64, Reg64 } // The segment register moves accept WordReg so that a segment register // can be copied to a 32 bit register, and vice versa, without using a // size prefix. When moving to a 32 bit register, the upper 16 bits @@ -161,57 +176,57 @@ mov, 0x8c, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { SReg, Word|U mov, 0x8e, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, SReg } // Move to/from control debug registers. In the 16 or 32bit modes // they are 32bit. In the 64bit mode they are 64bit. -mov, 0xf20, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Control, Reg32 } -mov, 0xf20, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Control, Reg64 } -mov, 0xf21, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Debug, Reg32 } -mov, 0xf21, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Debug, Reg64 } -mov, 0xf24, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Test, Reg32 } +mov, 0xf20, i386|No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Control, Reg32 } +mov, 0xf20, x64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Control, Reg64 } +mov, 0xf21, i386|No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Debug, Reg32 } +mov, 0xf21, x64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Debug, Reg64 } +mov, 0xf24, i386|No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Test, Reg32 } // Move after swapping the bytes -movbe, 0x0f38f0, CpuMovbe, D|Modrm|CheckRegSize|No_bSuf|No_sSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movbe, 0x0f38f0, Movbe, D|Modrm|CheckRegSize|No_bSuf|No_sSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // Move with sign extend. -movsb, 0xfbe, Cpu386, Modrm|No_bSuf|No_sSuf, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -movsw, 0xfbf, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } -movsl, 0x63, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg32|Unspecified|BaseIndex, Reg64 } -movsx, 0xfbe, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -movsx, 0x63, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } -movsxd, 0x63, Cpu64, Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } -movsxd, 0x63, Cpu64, Amd64|Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg16 } -movsxd, 0x63, Cpu64, Intel64|Modrm|NoSuf, { Reg16|Unspecified|BaseIndex, Reg16 } +movsb, 0xfbe, i386, Modrm|No_bSuf|No_sSuf, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movsw, 0xfbf, i386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 } +movsl, 0x63, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg32|Unspecified|BaseIndex, Reg64 } +movsx, 0xfbe, i386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movsx, 0x63, x64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } +movsxd, 0x63, x64, Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } +movsxd, 0x63, x64, Amd64|Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg16 } +movsxd, 0x63, x64, Intel64|Modrm|NoSuf, { Reg16|Unspecified|BaseIndex, Reg16 } // Move with zero extend. -movzb, 0xfb6, Cpu386, Modrm|No_bSuf|No_sSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -movzw, 0xfb7, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 } +movzb, 0xfb6, i386, Modrm|No_bSuf|No_sSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movzw, 0xfb7, i386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 } // The 64-bit variant is not particularly useful since the zero extend // 32->64 is implicit, but we can encode them. -movzx, 0xfb6, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movzx, 0xfb6, i386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // Push instructions. -push, 0x50, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } -push, 0xff/6, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex } -push, 0x6a, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm8S } -push, 0x68, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16|Imm32 } -push, 0x6, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } +push, 0x50, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } +push, 0xff/6, No64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex } +push, 0x6a, i186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm8S } +push, 0x68, i186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16|Imm32 } +push, 0x6, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } // In 64bit mode, the operand size is implicitly 64bit. -push, 0x50, Cpu64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } -push, 0xff/6, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } -push, 0x6a, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm8S } -push, 0x68, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16|Imm32S } -push, 0xfa0, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg } +push, 0x50, x64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } +push, 0xff/6, x64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } +push, 0x6a, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm8S } +push, 0x68, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16|Imm32S } +push, 0xfa0, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg } -pusha, 0x60, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} +pusha, 0x60, i186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} // Pop instructions. -pop, 0x58, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } -pop, 0x8f/0, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex } -pop, 0x7, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } +pop, 0x58, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } +pop, 0x8f/0, No64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex } +pop, 0x7, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } // In 64bit mode, the operand size is implicitly 64bit. -pop, 0x58, Cpu64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } -pop, 0x8f/0, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } -pop, 0xfa1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg } +pop, 0x58, x64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } +pop, 0x8f/0, x64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } +pop, 0xfa1, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg } -popa, 0x61, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} +popa, 0x61, i186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} // Exchange instructions. // xchg commutes: we allow both operand orders. @@ -234,27 +249,27 @@ out, 0xee, 0, W|No_sSuf|No_qSuf, { InOutPortReg } lea, 0x8d, 0, Modrm|Anysize|No_bSuf|No_sSuf|Optimize, { BaseIndex, Reg16|Reg32|Reg64 } // Load segment registers from memory. -lds, 0xc5, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 } -les, 0xc4, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 } -lfs, 0xfb4, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } -lfs, 0xfb4, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -lgs, 0xfb5, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } -lgs, 0xfb5, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -lss, 0xfb2, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } -lss, 0xfb2, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lds, 0xc5, No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 } +les, 0xc4, No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 } +lfs, 0xfb4, i386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } +lfs, 0xfb4, x64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lgs, 0xfb5, i386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } +lgs, 0xfb5, x64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lss, 0xfb2, i386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } +lss, 0xfb2, x64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // Flags register instructions. clc, 0xf8, 0, NoSuf, {} cld, 0xfc, 0, NoSuf, {} cli, 0xfa, 0, NoSuf, {} -clts, 0xf06, Cpu286, NoSuf, {} +clts, 0xf06, i286, NoSuf, {} cmc, 0xf5, 0, NoSuf, {} lahf, 0x9f, 0, NoSuf, {} sahf, 0x9e, 0, NoSuf, {} -pushf, 0x9c, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} -pushf, 0x9c, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} -popf, 0x9d, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} -popf, 0x9d, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} +pushf, 0x9c, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} +pushf, 0x9c, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} +popf, 0x9d, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} +popf, 0x9d, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} stc, 0xf9, 0, NoSuf, {} std, 0xfd, 0, NoSuf, {} sti, 0xfb, 0, NoSuf, {} @@ -265,7 +280,7 @@ add, 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64| add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } add, 0x80/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -inc, 0x40, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } +inc, 0x40, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } inc, 0xfe/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sub, 0x28, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } @@ -273,7 +288,7 @@ sub, 0x83/5, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64| sub, 0x2c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } sub, 0x80/5, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -dec, 0x48, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } +dec, 0x48, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } dec, 0xfe/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sbb, 0x18, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } @@ -316,30 +331,30 @@ adc, 0x80/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|R neg, 0xf6/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } not, 0xf6/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -aaa, 0x37, CpuNo64, NoSuf, {} -aas, 0x3f, CpuNo64, NoSuf, {} -daa, 0x27, CpuNo64, NoSuf, {} -das, 0x2f, CpuNo64, NoSuf, {} -aad, 0xd50a, CpuNo64, NoSuf, {} -aad, 0xd5, CpuNo64, NoSuf, { Imm8 } -aam, 0xd40a, CpuNo64, NoSuf, {} -aam, 0xd4, CpuNo64, NoSuf, { Imm8 } +aaa, 0x37, No64, NoSuf, {} +aas, 0x3f, No64, NoSuf, {} +daa, 0x27, No64, NoSuf, {} +das, 0x2f, No64, NoSuf, {} +aad, 0xd50a, No64, NoSuf, {} +aad, 0xd5, No64, NoSuf, { Imm8 } +aam, 0xd40a, No64, NoSuf, {} +aam, 0xd4, No64, NoSuf, { Imm8 } // Conversion insns. // Intel naming cbw, 0x98, 0, Size16|NoSuf, {} -cwde, 0x98, Cpu386, Size32|NoSuf, {} -cdqe, 0x98, Cpu64, Size64|NoSuf, {} +cwde, 0x98, i386, Size32|NoSuf, {} +cdqe, 0x98, x64, Size64|NoSuf, {} cwd, 0x99, 0, Size16|NoSuf, {} -cdq, 0x99, Cpu386, Size32|NoSuf, {} -cqo, 0x99, Cpu64, Size64|NoSuf, {} +cdq, 0x99, i386, Size32|NoSuf, {} +cqo, 0x99, x64, Size64|NoSuf, {} // AT&T naming cbtw, 0x98, 0, Size16|NoSuf, {} -cwtl, 0x98, Cpu386, Size32|NoSuf, {} -cltq, 0x98, Cpu64, Size64|NoSuf, {} +cwtl, 0x98, i386, Size32|NoSuf, {} +cltq, 0x98, x64, Size64|NoSuf, {} cwtd, 0x99, 0, Size16|NoSuf, {} -cltd, 0x99, Cpu386, Size32|NoSuf, {} -cqto, 0x99, Cpu64, Size64|NoSuf, {} +cltd, 0x99, i386, Size32|NoSuf, {} +cqto, 0x99, x64, Size64|NoSuf, {} // Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are // expanding 64-bit multiplies, and *cannot* be selected to accomplish @@ -347,14 +362,14 @@ cqto, 0x99, Cpu64, Size64|NoSuf, {} // These multiplies can only be selected with single operand forms. mul, 0xf6/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } imul, 0xf6/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -imul, 0xfaf, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 } -imul, 0x6b, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -imul, 0x69, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +imul, 0xfaf, i386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 } +imul, 0x6b, i186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +imul, 0x69, i186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // imul with 2 operands mimics imul with 3 by putting the register in // both i.rm.reg & i.rm.regmem fields. RegKludge enables this // transformation. -imul, 0x6b, Cpu186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 } -imul, 0x69, Cpu186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } +imul, 0x6b, i186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 } +imul, 0x69, i186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } div, 0xf6/6, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } div, 0xf6/6, 0, W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } @@ -362,97 +377,97 @@ idiv, 0xf6/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword idiv, 0xf6/7, 0, W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -rol, 0xc0/0, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rol, 0xc0/0, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -ror, 0xc0/1, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +ror, 0xc0/1, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ror, 0xd2/1, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -rcl, 0xc0/2, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcl, 0xc0/2, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcl, 0xd2/2, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -rcr, 0xc0/3, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcr, 0xc0/3, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcr, 0xd2/3, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -sal, 0xc0/4, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sal, 0xc0/4, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sal, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -shl, 0xc0/4, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shl, 0xc0/4, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shl, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -shr, 0xc0/5, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shr, 0xc0/5, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shr, 0xd2/5, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -sar, 0xc0/7, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sar, 0xc0/7, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sar, 0xd2/7, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -shld, 0xfa4, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -shld, 0xfa5, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -shld, 0xfa5, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shld, 0xfa4, i386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shld, 0xfa5, i386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shld, 0xfa5, i386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -shrd, 0xfac, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -shrd, 0xfad, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -shrd, 0xfad, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shrd, 0xfac, i386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shrd, 0xfad, i386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shrd, 0xfad, i386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } // Control transfer instructions. -call, 0xe8, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 } -call, 0xe8, Cpu64, Amd64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32 } -call, 0xe8, Cpu64, Intel64|JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp32 } -call, 0xff/2, CpuNo64, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } -call, 0xff/2, Cpu64, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } -call, 0xff/2, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } +call, 0xe8, No64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 } +call, 0xe8, x64, Amd64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32 } +call, 0xe8, x64, Intel64|JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp32 } +call, 0xff/2, No64, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } +call, 0xff/2, x64, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } +call, 0xff/2, x64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } // Intel Syntax remaining call instances. -call, 0x9a, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } +call, 0x9a, No64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } call, 0xff/3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|NoSuf, { Dword|Fword|BaseIndex } -call, 0xff/3, Cpu64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex } -lcall, 0x9a, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } +call, 0xff/3, x64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex } +lcall, 0x9a, No64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } lcall, 0xff/3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex } -lcall, 0xff/3, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex } +lcall, 0xff/3, x64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex } jmp, 0xeb, 0, Amd64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 } -jmp, 0xeb, Cpu64, Intel64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp32 } -jmp, 0xff/4, CpuNo64, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } -jmp, 0xff/4, Cpu64, Amd64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } -jmp, 0xff/4, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } +jmp, 0xeb, x64, Intel64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp32 } +jmp, 0xff/4, No64, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } +jmp, 0xff/4, x64, Amd64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } +jmp, 0xff/4, x64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } // Intel Syntax remaining jmp instances. -jmp, 0xea, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } +jmp, 0xea, No64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } jmp, 0xff/5, 0, Amd64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|BaseIndex } -jmp, 0xff/5, Cpu64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex } -ljmp, 0xea, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } +jmp, 0xff/5, x64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex } +ljmp, 0xea, No64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 } ljmp, 0xff/5, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex } -ljmp, 0xff/5, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex } - -ret, 0xc3, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, {} -ret, 0xc2, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, { Imm16 } -ret, 0xc3, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} -ret, 0xc2, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } -ret, 0xc3, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} -ret, 0xc2, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } +ljmp, 0xff/5, x64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex } + +ret, 0xc3, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, {} +ret, 0xc2, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, { Imm16 } +ret, 0xc3, x64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} +ret, 0xc2, x64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } +ret, 0xc3, x64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} +ret, 0xc2, x64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } lret, 0xcb, 0, DefaultSize|No_bSuf|No_sSuf, {} lret, 0xca, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 } // Intel Syntax. retf, 0xcb, 0, DefaultSize|No_bSuf|No_sSuf, {} retf, 0xca, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 } -enter, 0xc8, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm8 } -enter, 0xc8, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16, Imm8 } -leave, 0xc9, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} -leave, 0xc9, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} +enter, 0xc8, i186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm8 } +enter, 0xc8, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16, Imm8 } +leave, 0xc9, i186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {} +leave, 0xc9, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} <cc:opc, o:0, no:1, b:2, c:2, nae:2, nb:3, nc:3, ae:3, e:4, z:4, ne:5, nz:5, be:6, na:6, nbe:7, a:7, + s:8, ns:9, p:a, pe:a, np:b, po:b, l:c, nge:c, nl:d, ge:d, le:e, ng:e, nle:f, g:f> @@ -461,37 +476,37 @@ leave, 0xc9, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {} j<cc>, 0x7<cc:opc>, 0, Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 } // jcxz vs. jecxz is chosen on the basis of the address size prefix. -jcxz, 0xe3, CpuNo64, JumpByte|Size16|NoSuf, { Disp8 } -jecxz, 0xe3, Cpu386, JumpByte|Size32|NoSuf, { Disp8 } -jrcxz, 0xe3, Cpu64, JumpByte|Size64|NoSuf|NoRex64, { Disp8 } +jcxz, 0xe3, No64, JumpByte|Size16|NoSuf, { Disp8 } +jecxz, 0xe3, i386, JumpByte|Size32|NoSuf, { Disp8 } +jrcxz, 0xe3, x64, JumpByte|Size64|NoSuf|NoRex64, { Disp8 } // The loop instructions also use the address size prefix to select // %cx rather than %ecx for the loop count, so the `w' form of these // instructions emit an address size prefix rather than a data size // prefix. -loop, 0xe2, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } -loop, 0xe2, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } -loopz, 0xe1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } -loopz, 0xe1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } -loope, 0xe1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } -loope, 0xe1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } -loopnz, 0xe0, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } -loopnz, 0xe0, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } -loopne, 0xe0, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } -loopne, 0xe0, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } +loop, 0xe2, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } +loop, 0xe2, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } +loopz, 0xe1, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } +loopz, 0xe1, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } +loope, 0xe1, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } +loope, 0xe1, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } +loopnz, 0xe0, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } +loopnz, 0xe0, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } +loopne, 0xe0, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 } +loopne, 0xe0, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 } // Set byte on flag instructions. -set<cc>, 0xf9<cc:opc>/0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Reg8|Byte|Unspecified|BaseIndex } +set<cc>, 0xf9<cc:opc>/0, i386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Reg8|Byte|Unspecified|BaseIndex } // String manipulation. cmps, 0xa6, 0, W|No_sSuf|RepPrefixOk, {} cmps, 0xa6, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } scmp, 0xa6, 0, W|No_sSuf|RepPrefixOk, {} scmp, 0xa6, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } -ins, 0x6c, Cpu186, W|No_sSuf|No_qSuf|RepPrefixOk, {} -ins, 0x6c, Cpu186, W|No_sSuf|No_qSuf|IsStringEsOp1|RepPrefixOk, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex } -outs, 0x6e, Cpu186, W|No_sSuf|No_qSuf|RepPrefixOk, {} -outs, 0x6e, Cpu186, W|No_sSuf|No_qSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Unspecified|BaseIndex, InOutPortReg } +ins, 0x6c, i186, W|No_sSuf|No_qSuf|RepPrefixOk, {} +ins, 0x6c, i186, W|No_sSuf|No_qSuf|IsStringEsOp1|RepPrefixOk, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex } +outs, 0x6e, i186, W|No_sSuf|No_qSuf|RepPrefixOk, {} +outs, 0x6e, i186, W|No_sSuf|No_qSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Unspecified|BaseIndex, InOutPortReg } lods, 0xac, 0, W|No_sSuf|RepPrefixOk, {} lods, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } lods, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } @@ -518,16 +533,16 @@ xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf, {} xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IsString, { Byte|Unspecified|BaseIndex } // Bit manipulation. -bsf, 0xfbc, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -bsr, 0xfbd, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -bt, 0xfa3, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -bt, 0xfba/4, Cpu386, Modrm|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -btc, 0xfbb, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -btc, 0xfba/7, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -btr, 0xfb3, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -btr, 0xfba/6, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -bts, 0xfab, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -bts, 0xfba/5, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +bsf, 0xfbc, i386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +bsr, 0xfbd, i386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +bt, 0xfa3, i386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +bt, 0xfba/4, i386, Modrm|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +btc, 0xfbb, i386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +btc, 0xfba/7, i386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +btr, 0xfb3, i386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +btr, 0xfba/6, i386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +bts, 0xfab, i386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +bts, 0xfba/5, i386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } // Interrupts & op. sys insns. // See gas/config/tc-i386.c for conversion of 'int $3' into the special @@ -535,291 +550,291 @@ bts, 0xfba/5, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|R int, 0xcd, 0, NoSuf, { Imm8 } int1, 0xf1, 0, NoSuf, {} int3, 0xcc, 0, NoSuf, {} -into, 0xce, CpuNo64, NoSuf, {} +into, 0xce, No64, NoSuf, {} iret, 0xcf, 0, DefaultSize|No_bSuf|No_sSuf, {} // i386sl, i486sl, later 486, and Pentium. -rsm, 0xfaa, Cpu386, NoSuf, {} +rsm, 0xfaa, i386, NoSuf, {} -bound, 0x62, Cpu186|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Dword|Qword|Unspecified|BaseIndex } +bound, 0x62, i186|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Dword|Qword|Unspecified|BaseIndex } hlt, 0xf4, 0, NoSuf, {} -nop, 0xf1f/0, CpuNop, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +nop, 0xf1f/0, Nop, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } // nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in // 32bit mode and "xchg %rax,%rax" in 64bit mode. nop, 0x90, 0, NoSuf|RepPrefixOk, {} // Protection control. -arpl, 0x63, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex } -lar, 0xf02, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } -lar, 0xf02, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -lgdt, 0xf01/2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } -lgdt, 0xf01/2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } -lidt, 0xf01/3, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } -lidt, 0xf01/3, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } -lldt, 0xf00/2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } -lmsw, 0xf01/6, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } -lsl, 0xf03, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } -lsl, 0xf03, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -ltr, 0xf00/3, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } - -sgdt, 0xf01/0, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } -sgdt, 0xf01/0, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } -sidt, 0xf01/1, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } -sidt, 0xf01/1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } -sldt, 0xf00/0, Cpu286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } -sldt, 0xf00/0, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } -smsw, 0xf01/4, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64 } -smsw, 0xf01/4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } -str, 0xf00/1, Cpu286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } -str, 0xf00/1, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } - -verr, 0xf00/4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } -verw, 0xf00/5, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } +arpl, 0x63, i286|No64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex } +lar, 0xf02, i286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } +lar, 0xf02, i286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lgdt, 0xf01/2, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } +lgdt, 0xf01/2, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } +lidt, 0xf01/3, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } +lidt, 0xf01/3, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } +lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } +lmsw, 0xf01/6, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } +lsl, 0xf03, i286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } +lsl, 0xf03, i286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } + +sgdt, 0xf01/0, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } +sgdt, 0xf01/0, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } +sidt, 0xf01/1, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex } +sidt, 0xf01/1, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } +sldt, 0xf00/0, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } +sldt, 0xf00/0, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } +smsw, 0xf01/4, i286, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64 } +smsw, 0xf01/4, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } +str, 0xf00/1, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } +str, 0xf00/1, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } + +verr, 0xf00/4, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } +verw, 0xf00/5, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex } // Floating point instructions. // load -fld, 0xd9c0, CpuFP, NoSuf, { FloatReg } -fld, 0xd9/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fld, 0xd9c0, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } +fld, 0xd9c0, FP, NoSuf, { FloatReg } +fld, 0xd9/0, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fld, 0xd9c0, FP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } // Intel Syntax -fld, 0xdb/5, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } -fild, 0xdf/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } -fild, 0xdf/5, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex } -fildll, 0xdf/5, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } -fldt, 0xdb/5, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex } -fbld, 0xdf/4, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } +fld, 0xdb/5, FP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } +fild, 0xdf/0, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fild, 0xdf/5, FP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex } +fildll, 0xdf/5, FP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } +fldt, 0xdb/5, FP, Modrm|NoSuf, { Unspecified|BaseIndex } +fbld, 0xdf/4, FP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } // store (no pop) -fst, 0xddd0, CpuFP, NoSuf, { FloatReg } -fst, 0xd9/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fst, 0xddd0, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } -fist, 0xdf/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fst, 0xddd0, FP, NoSuf, { FloatReg } +fst, 0xd9/2, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fst, 0xddd0, FP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } +fist, 0xdf/2, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } // store (with pop) -fstp, 0xddd8, CpuFP, NoSuf, { FloatReg } -fstp, 0xd9/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fstp, 0xddd8, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } +fstp, 0xddd8, FP, NoSuf, { FloatReg } +fstp, 0xd9/3, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fstp, 0xddd8, FP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } // Intel Syntax -fstp, 0xdb/7, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } -fistp, 0xdf/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } -fistp, 0xdf/7, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex } -fistpll, 0xdf/7, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } -fstpt, 0xdb/7, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex } -fbstp, 0xdf/6, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } +fstp, 0xdb/7, FP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } +fistp, 0xdf/3, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fistp, 0xdf/7, FP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex } +fistpll, 0xdf/7, FP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } +fstpt, 0xdb/7, FP, Modrm|NoSuf, { Unspecified|BaseIndex } +fbstp, 0xdf/6, FP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } // exchange %st<n> with %st0 -fxch, 0xd9c8, CpuFP, NoSuf, { FloatReg } +fxch, 0xd9c8, FP, NoSuf, { FloatReg } // alias for fxch %st(1) -fxch, 0xd9c9, CpuFP, NoSuf, {} +fxch, 0xd9c9, FP, NoSuf, {} // comparison (without pop) -fcom, 0xd8d0, CpuFP, NoSuf, { FloatReg } +fcom, 0xd8d0, FP, NoSuf, { FloatReg } // alias for fcom %st(1) -fcom, 0xd8d1, CpuFP, NoSuf, {} -fcom, 0xd8/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fcom, 0xd8d0, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } -ficom, 0xde/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fcom, 0xd8d1, FP, NoSuf, {} +fcom, 0xd8/2, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fcom, 0xd8d0, FP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } +ficom, 0xde/2, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } // comparison (with pop) -fcomp, 0xd8d8, CpuFP, NoSuf, { FloatReg } +fcomp, 0xd8d8, FP, NoSuf, { FloatReg } // alias for fcomp %st(1) -fcomp, 0xd8d9, CpuFP, NoSuf, {} -fcomp, 0xd8/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fcomp, 0xd8d8, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } -ficomp, 0xde/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } -fcompp, 0xded9, CpuFP, NoSuf, {} +fcomp, 0xd8d9, FP, NoSuf, {} +fcomp, 0xd8/3, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fcomp, 0xd8d8, FP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg } +ficomp, 0xde/3, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fcompp, 0xded9, FP, NoSuf, {} // unordered comparison (with pop) -fucom, 0xdde0, Cpu387, NoSuf, { FloatReg } +fucom, 0xdde0, i387, NoSuf, { FloatReg } // alias for fucom %st(1) -fucom, 0xdde1, Cpu387, NoSuf, {} -fucomp, 0xdde8, Cpu387, NoSuf, { FloatReg } +fucom, 0xdde1, i387, NoSuf, {} +fucomp, 0xdde8, i387, NoSuf, { FloatReg } // alias for fucomp %st(1) -fucomp, 0xdde9, Cpu387, NoSuf, {} -fucompp, 0xdae9, Cpu387, NoSuf, {} +fucomp, 0xdde9, i387, NoSuf, {} +fucompp, 0xdae9, i387, NoSuf, {} -ftst, 0xd9e4, CpuFP, NoSuf, {} -fxam, 0xd9e5, CpuFP, NoSuf, {} +ftst, 0xd9e4, FP, NoSuf, {} +fxam, 0xd9e5, FP, NoSuf, {} // load constants into %st0 -fld1, 0xd9e8, CpuFP, NoSuf, {} -fldl2t, 0xd9e9, CpuFP, NoSuf, {} -fldl2e, 0xd9ea, CpuFP, NoSuf, {} -fldpi, 0xd9eb, CpuFP, NoSuf, {} -fldlg2, 0xd9ec, CpuFP, NoSuf, {} -fldln2, 0xd9ed, CpuFP, NoSuf, {} -fldz, 0xd9ee, CpuFP, NoSuf, {} +fld1, 0xd9e8, FP, NoSuf, {} +fldl2t, 0xd9e9, FP, NoSuf, {} +fldl2e, 0xd9ea, FP, NoSuf, {} +fldpi, 0xd9eb, FP, NoSuf, {} +fldlg2, 0xd9ec, FP, NoSuf, {} +fldln2, 0xd9ed, FP, NoSuf, {} +fldz, 0xd9ee, FP, NoSuf, {} // Arithmetic. // add -fadd, 0xd8c0, CpuFP, D|NoSuf, { FloatReg, FloatAcc } +fadd, 0xd8c0, FP, D|NoSuf, { FloatReg, FloatAcc } // alias for fadd %st(i), %st -fadd, 0xd8c0, CpuFP, NoSuf, { FloatReg } +fadd, 0xd8c0, FP, NoSuf, { FloatReg } // alias for faddp -fadd, 0xdec1, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fadd, 0xd8/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fiadd, 0xde/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fadd, 0xdec1, FP, NoSuf|Ugh|ATTMnemonic, {} +fadd, 0xd8/0, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fiadd, 0xde/0, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } -faddp, 0xdec0, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg } -faddp, 0xdec0, CpuFP, NoSuf, { FloatReg } +faddp, 0xdec0, FP, D|NoSuf|Ugh, { FloatAcc, FloatReg } +faddp, 0xdec0, FP, NoSuf, { FloatReg } // alias for faddp %st, %st(1) -faddp, 0xdec1, CpuFP, NoSuf, {} +faddp, 0xdec1, FP, NoSuf, {} // subtract -fsub, 0xd8e0, CpuFP, NoSuf, { FloatReg } -fsub, 0xd8e0, CpuFP, D|NoSuf, { FloatReg, FloatAcc } +fsub, 0xd8e0, FP, NoSuf, { FloatReg } +fsub, 0xd8e0, FP, D|NoSuf, { FloatReg, FloatAcc } // alias for fsubp -fsub, 0xdee1, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} -fsub, 0xdee9, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fsub, 0xd8/4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fisub, 0xde/4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } - -fsubp, 0xdee0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } -fsubp, 0xdee0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } -fsubp, 0xdee1, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} -fsubp, 0xdee8, CpuFP, NoSuf, { FloatAcc, FloatReg } -fsubp, 0xdee8, CpuFP, NoSuf, { FloatReg } -fsubp, 0xdee9, CpuFP, NoSuf, {} +fsub, 0xdee1, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} +fsub, 0xdee9, FP, NoSuf|Ugh|ATTMnemonic, {} +fsub, 0xd8/4, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fisub, 0xde/4, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } + +fsubp, 0xdee0, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +fsubp, 0xdee0, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } +fsubp, 0xdee1, FP, NoSuf|ATTMnemonic|ATTSyntax, {} +fsubp, 0xdee8, FP, NoSuf, { FloatAcc, FloatReg } +fsubp, 0xdee8, FP, NoSuf, { FloatReg } +fsubp, 0xdee9, FP, NoSuf, {} // subtract reverse -fsubr, 0xd8e8, CpuFP, NoSuf, { FloatReg } -fsubr, 0xd8e8, CpuFP, D|NoSuf, { FloatReg, FloatAcc } +fsubr, 0xd8e8, FP, NoSuf, { FloatReg } +fsubr, 0xd8e8, FP, D|NoSuf, { FloatReg, FloatAcc } // alias for fsubrp -fsubr, 0xdee9, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} -fsubr, 0xdee1, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fsubr, 0xd8/5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fisubr, 0xde/5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } - -fsubrp, 0xdee8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } -fsubrp, 0xdee8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } -fsubrp, 0xdee9, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} -fsubrp, 0xdee0, CpuFP, NoSuf, { FloatAcc, FloatReg } -fsubrp, 0xdee0, CpuFP, NoSuf, { FloatReg } -fsubrp, 0xdee1, CpuFP, NoSuf, {} +fsubr, 0xdee9, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} +fsubr, 0xdee1, FP, NoSuf|Ugh|ATTMnemonic, {} +fsubr, 0xd8/5, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fisubr, 0xde/5, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } + +fsubrp, 0xdee8, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +fsubrp, 0xdee8, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } +fsubrp, 0xdee9, FP, NoSuf|ATTMnemonic|ATTSyntax, {} +fsubrp, 0xdee0, FP, NoSuf, { FloatAcc, FloatReg } +fsubrp, 0xdee0, FP, NoSuf, { FloatReg } +fsubrp, 0xdee1, FP, NoSuf, {} // multiply -fmul, 0xd8c8, CpuFP, D|NoSuf, { FloatReg, FloatAcc } -fmul, 0xd8c8, CpuFP, NoSuf, { FloatReg } +fmul, 0xd8c8, FP, D|NoSuf, { FloatReg, FloatAcc } +fmul, 0xd8c8, FP, NoSuf, { FloatReg } // alias for fmulp -fmul, 0xdec9, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fmul, 0xd8/1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fimul, 0xde/1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fmul, 0xdec9, FP, NoSuf|Ugh|ATTMnemonic, {} +fmul, 0xd8/1, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fimul, 0xde/1, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } -fmulp, 0xdec8, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg } -fmulp, 0xdec8, CpuFP, NoSuf, { FloatReg } +fmulp, 0xdec8, FP, D|NoSuf|Ugh, { FloatAcc, FloatReg } +fmulp, 0xdec8, FP, NoSuf, { FloatReg } // alias for fmulp %st, %st(1) -fmulp, 0xdec9, CpuFP, NoSuf, {} +fmulp, 0xdec9, FP, NoSuf, {} // divide -fdiv, 0xd8f0, CpuFP, NoSuf, { FloatReg } -fdiv, 0xd8f0, CpuFP, D|NoSuf, { FloatReg, FloatAcc } +fdiv, 0xd8f0, FP, NoSuf, { FloatReg } +fdiv, 0xd8f0, FP, D|NoSuf, { FloatReg, FloatAcc } // alias for fdivp -fdiv, 0xdef1, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} -fdiv, 0xdef9, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fdiv, 0xd8/6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fidiv, 0xde/6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } - -fdivp, 0xdef0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } -fdivp, 0xdef0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } -fdivp, 0xdef1, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} -fdivp, 0xdef8, CpuFP, NoSuf, { FloatAcc, FloatReg } -fdivp, 0xdef8, CpuFP, NoSuf, { FloatReg } -fdivp, 0xdef9, CpuFP, NoSuf, {} +fdiv, 0xdef1, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} +fdiv, 0xdef9, FP, NoSuf|Ugh|ATTMnemonic, {} +fdiv, 0xd8/6, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fidiv, 0xde/6, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } + +fdivp, 0xdef0, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +fdivp, 0xdef0, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } +fdivp, 0xdef1, FP, NoSuf|ATTMnemonic|ATTSyntax, {} +fdivp, 0xdef8, FP, NoSuf, { FloatAcc, FloatReg } +fdivp, 0xdef8, FP, NoSuf, { FloatReg } +fdivp, 0xdef9, FP, NoSuf, {} // divide reverse -fdivr, 0xd8f8, CpuFP, NoSuf, { FloatReg } -fdivr, 0xd8f8, CpuFP, D|NoSuf, { FloatReg, FloatAcc } +fdivr, 0xd8f8, FP, NoSuf, { FloatReg } +fdivr, 0xd8f8, FP, D|NoSuf, { FloatReg, FloatAcc } // alias for fdivrp -fdivr, 0xdef9, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} -fdivr, 0xdef1, CpuFP, NoSuf|Ugh|ATTMnemonic, {} -fdivr, 0xd8/7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } -fidivr, 0xde/7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } - -fdivrp, 0xdef8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } -fdivrp, 0xdef8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } -fdivrp, 0xdef9, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} -fdivrp, 0xdef0, CpuFP, NoSuf, { FloatAcc, FloatReg } -fdivrp, 0xdef0, CpuFP, NoSuf, { FloatReg } -fdivrp, 0xdef1, CpuFP, NoSuf, {} - -f2xm1, 0xd9f0, CpuFP, NoSuf, {} -fyl2x, 0xd9f1, CpuFP, NoSuf, {} -fptan, 0xd9f2, CpuFP, NoSuf, {} -fpatan, 0xd9f3, CpuFP, NoSuf, {} -fxtract, 0xd9f4, CpuFP, NoSuf, {} -fprem1, 0xd9f5, Cpu387, NoSuf, {} -fdecstp, 0xd9f6, CpuFP, NoSuf, {} -fincstp, 0xd9f7, CpuFP, NoSuf, {} -fprem, 0xd9f8, CpuFP, NoSuf, {} -fyl2xp1, 0xd9f9, CpuFP, NoSuf, {} -fsqrt, 0xd9fa, CpuFP, NoSuf, {} -fsincos, 0xd9fb, Cpu387, NoSuf, {} -frndint, 0xd9fc, CpuFP, NoSuf, {} -fscale, 0xd9fd, CpuFP, NoSuf, {} -fsin, 0xd9fe, Cpu387, NoSuf, {} -fcos, 0xd9ff, Cpu387, NoSuf, {} -fchs, 0xd9e0, CpuFP, NoSuf, {} -fabs, 0xd9e1, CpuFP, NoSuf, {} +fdivr, 0xdef9, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} +fdivr, 0xdef1, FP, NoSuf|Ugh|ATTMnemonic, {} +fdivr, 0xd8/7, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex } +fidivr, 0xde/7, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } + +fdivrp, 0xdef8, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +fdivrp, 0xdef8, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } +fdivrp, 0xdef9, FP, NoSuf|ATTMnemonic|ATTSyntax, {} +fdivrp, 0xdef0, FP, NoSuf, { FloatAcc, FloatReg } +fdivrp, 0xdef0, FP, NoSuf, { FloatReg } +fdivrp, 0xdef1, FP, NoSuf, {} + +f2xm1, 0xd9f0, FP, NoSuf, {} +fyl2x, 0xd9f1, FP, NoSuf, {} +fptan, 0xd9f2, FP, NoSuf, {} +fpatan, 0xd9f3, FP, NoSuf, {} +fxtract, 0xd9f4, FP, NoSuf, {} +fprem1, 0xd9f5, i387, NoSuf, {} +fdecstp, 0xd9f6, FP, NoSuf, {} +fincstp, 0xd9f7, FP, NoSuf, {} +fprem, 0xd9f8, FP, NoSuf, {} +fyl2xp1, 0xd9f9, FP, NoSuf, {} +fsqrt, 0xd9fa, FP, NoSuf, {} +fsincos, 0xd9fb, i387, NoSuf, {} +frndint, 0xd9fc, FP, NoSuf, {} +fscale, 0xd9fd, FP, NoSuf, {} +fsin, 0xd9fe, i387, NoSuf, {} +fcos, 0xd9ff, i387, NoSuf, {} +fchs, 0xd9e0, FP, NoSuf, {} +fabs, 0xd9e1, FP, NoSuf, {} // processor control -fninit, 0xdbe3, CpuFP, NoSuf, {} -finit, 0xdbe3, CpuFP, NoSuf|FWait, {} -fldcw, 0xd9/5, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } -fnstcw, 0xd9/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } -fstcw, 0xd9/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex } -fnstsw, 0xdfe0, Cpu287|Cpu387, IgnoreSize|NoSuf, { Acc|Word } -fnstsw, 0xdd/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } -fnstsw, 0xdfe0, Cpu287|Cpu387, NoSuf, {} -fstsw, 0xdfe0, Cpu287|Cpu387, IgnoreSize|NoSuf|FWait, { Acc|Word } -fstsw, 0xdd/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex } -fstsw, 0xdfe0, Cpu287|Cpu387, NoSuf|FWait, {} -fnclex, 0xdbe2, CpuFP, NoSuf, {} -fclex, 0xdbe2, CpuFP, NoSuf|FWait, {} +fninit, 0xdbe3, FP, NoSuf, {} +finit, 0xdbe3, FP, NoSuf|FWait, {} +fldcw, 0xd9/5, FP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } +fnstcw, 0xd9/7, FP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } +fstcw, 0xd9/7, FP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex } +fnstsw, 0xdfe0, i287|i387, IgnoreSize|NoSuf, { Acc|Word } +fnstsw, 0xdd/7, FP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } +fnstsw, 0xdfe0, i287|i387, NoSuf, {} +fstsw, 0xdfe0, i287|i387, IgnoreSize|NoSuf|FWait, { Acc|Word } +fstsw, 0xdd/7, FP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex } +fstsw, 0xdfe0, i287|i387, NoSuf|FWait, {} +fnclex, 0xdbe2, FP, NoSuf, {} +fclex, 0xdbe2, FP, NoSuf|FWait, {} // Short forms of fldenv, fstenv, fsave, and frstor use data size prefix. -fnstenv, 0xd9/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } -fstenv, 0xd9/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex } -fldenv, 0xd9/4, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } -fnsave, 0xdd/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } -fsave, 0xdd/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex } -frstor, 0xdd/4, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } +fnstenv, 0xd9/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } +fstenv, 0xd9/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex } +fldenv, 0xd9/4, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } +fnsave, 0xdd/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } +fsave, 0xdd/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex } +frstor, 0xdd/4, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex } // 8087 only -fneni, 0xdbe0, Cpu8087, NoSuf, {} -feni, 0xdbe0, Cpu8087, NoSuf|FWait, {} -fndisi, 0xdbe1, Cpu8087, NoSuf, {} -fdisi, 0xdbe1, Cpu8087, NoSuf|FWait, {} +fneni, 0xdbe0, i8087, NoSuf, {} +feni, 0xdbe0, i8087, NoSuf|FWait, {} +fndisi, 0xdbe1, i8087, NoSuf, {} +fdisi, 0xdbe1, i8087, NoSuf|FWait, {} // 287 only -fnsetpm, 0xdbe4, Cpu287, NoSuf, {} -fsetpm, 0xdbe4, Cpu287, NoSuf|FWait, {} -frstpm, 0xdbe5, Cpu287, NoSuf, {} +fnsetpm, 0xdbe4, i287, NoSuf, {} +fsetpm, 0xdbe4, i287, NoSuf|FWait, {} +frstpm, 0xdbe5, i287, NoSuf, {} -ffree, 0xddc0, CpuFP, NoSuf, { FloatReg } +ffree, 0xddc0, FP, NoSuf, { FloatReg } // P6:free st(i), pop st -ffreep, 0xdfc0, Cpu687, NoSuf, { FloatReg } -fnop, 0xd9d0, CpuFP, NoSuf, {} -fwait, 0x9b, CpuFP, NoSuf, {} +ffreep, 0xdfc0, i687, NoSuf, { FloatReg } +fnop, 0xd9d0, FP, NoSuf, {} +fwait, 0x9b, FP, NoSuf, {} // Opcode prefixes; we allow them as separate insns too. -addr16, 0x67, Cpu386|CpuNo64, Size16|IgnoreSize|NoSuf|IsPrefix, {} -addr32, 0x67, Cpu386, Size32|IgnoreSize|NoSuf|IsPrefix, {} -aword, 0x67, Cpu386|CpuNo64, Size16|IgnoreSize|NoSuf|IsPrefix, {} -adword, 0x67, Cpu386, Size32|IgnoreSize|NoSuf|IsPrefix, {} -data16, 0x66, Cpu386, Size16|IgnoreSize|NoSuf|IsPrefix, {} -data32, 0x66, Cpu386|CpuNo64, Size32|IgnoreSize|NoSuf|IsPrefix, {} -word, 0x66, Cpu386, Size16|IgnoreSize|NoSuf|IsPrefix, {} -dword, 0x66, Cpu386|CpuNo64, Size32|IgnoreSize|NoSuf|IsPrefix, {} +addr16, 0x67, i386|No64, Size16|IgnoreSize|NoSuf|IsPrefix, {} +addr32, 0x67, i386, Size32|IgnoreSize|NoSuf|IsPrefix, {} +aword, 0x67, i386|No64, Size16|IgnoreSize|NoSuf|IsPrefix, {} +adword, 0x67, i386, Size32|IgnoreSize|NoSuf|IsPrefix, {} +data16, 0x66, i386, Size16|IgnoreSize|NoSuf|IsPrefix, {} +data32, 0x66, i386|No64, Size32|IgnoreSize|NoSuf|IsPrefix, {} +word, 0x66, i386, Size16|IgnoreSize|NoSuf|IsPrefix, {} +dword, 0x66, i386|No64, Size32|IgnoreSize|NoSuf|IsPrefix, {} lock, 0xf0, 0, NoSuf|IsPrefix, {} wait, 0x9b, 0, NoSuf|IsPrefix, {} cs, 0x2e, 0, NoSuf|IsPrefix, {} ds, 0x3e, 0, NoSuf|IsPrefix, {} -es, 0x26, CpuNo64, NoSuf|IsPrefix, {} -fs, 0x64, Cpu386, NoSuf|IsPrefix, {} -gs, 0x65, Cpu386, NoSuf|IsPrefix, {} -ss, 0x36, CpuNo64, NoSuf|IsPrefix, {} +es, 0x26, No64, NoSuf|IsPrefix, {} +fs, 0x64, i386, NoSuf|IsPrefix, {} +gs, 0x65, i386, NoSuf|IsPrefix, {} +ss, 0x36, No64, NoSuf|IsPrefix, {} rep, 0xf3, 0, NoSuf|IsPrefix, {} repe, 0xf3, 0, NoSuf|IsPrefix, {} repz, 0xf3, 0, NoSuf|IsPrefix, {} @@ -827,176 +842,176 @@ repne, 0xf2, 0, NoSuf|IsPrefix, {} repnz, 0xf2, 0, NoSuf|IsPrefix, {} ht, 0x3e, 0, NoSuf|IsPrefix, {} hnt, 0x2e, 0, NoSuf|IsPrefix, {} -rex, 0x40, Cpu64, NoSuf|IsPrefix, {} -rexz, 0x41, Cpu64, NoSuf|IsPrefix, {} -rexy, 0x42, Cpu64, NoSuf|IsPrefix, {} -rexyz, 0x43, Cpu64, NoSuf|IsPrefix, {} -rexx, 0x44, Cpu64, NoSuf|IsPrefix, {} -rexxz, 0x45, Cpu64, NoSuf|IsPrefix, {} -rexxy, 0x46, Cpu64, NoSuf|IsPrefix, {} -rexxyz, 0x47, Cpu64, NoSuf|IsPrefix, {} -rex64, 0x48, Cpu64, NoSuf|IsPrefix, {} -rex64z, 0x49, Cpu64, NoSuf|IsPrefix, {} -rex64y, 0x4a, Cpu64, NoSuf|IsPrefix, {} -rex64yz, 0x4b, Cpu64, NoSuf|IsPrefix, {} -rex64x, 0x4c, Cpu64, NoSuf|IsPrefix, {} -rex64xz, 0x4d, Cpu64, NoSuf|IsPrefix, {} -rex64xy, 0x4e, Cpu64, NoSuf|IsPrefix, {} -rex64xyz, 0x4f, Cpu64, NoSuf|IsPrefix, {} -rex.b, 0x41, Cpu64, NoSuf|IsPrefix, {} -rex.x, 0x42, Cpu64, NoSuf|IsPrefix, {} -rex.xb, 0x43, Cpu64, NoSuf|IsPrefix, {} -rex.r, 0x44, Cpu64, NoSuf|IsPrefix, {} -rex.rb, 0x45, Cpu64, NoSuf|IsPrefix, {} -rex.rx, 0x46, Cpu64, NoSuf|IsPrefix, {} -rex.rxb, 0x47, Cpu64, NoSuf|IsPrefix, {} -rex.w, 0x48, Cpu64, NoSuf|IsPrefix, {} -rex.wb, 0x49, Cpu64, NoSuf|IsPrefix, {} -rex.wx, 0x4a, Cpu64, NoSuf|IsPrefix, {} -rex.wxb, 0x4b, Cpu64, NoSuf|IsPrefix, {} -rex.wr, 0x4c, Cpu64, NoSuf|IsPrefix, {} -rex.wrb, 0x4d, Cpu64, NoSuf|IsPrefix, {} -rex.wrx, 0x4e, Cpu64, NoSuf|IsPrefix, {} -rex.wrxb, 0x4f, Cpu64, NoSuf|IsPrefix, {} +rex, 0x40, x64, NoSuf|IsPrefix, {} +rexz, 0x41, x64, NoSuf|IsPrefix, {} +rexy, 0x42, x64, NoSuf|IsPrefix, {} +rexyz, 0x43, x64, NoSuf|IsPrefix, {} +rexx, 0x44, x64, NoSuf|IsPrefix, {} +rexxz, 0x45, x64, NoSuf|IsPrefix, {} +rexxy, 0x46, x64, NoSuf|IsPrefix, {} +rexxyz, 0x47, x64, NoSuf|IsPrefix, {} +rex64, 0x48, x64, NoSuf|IsPrefix, {} +rex64z, 0x49, x64, NoSuf|IsPrefix, {} +rex64y, 0x4a, x64, NoSuf|IsPrefix, {} +rex64yz, 0x4b, x64, NoSuf|IsPrefix, {} +rex64x, 0x4c, x64, NoSuf|IsPrefix, {} +rex64xz, 0x4d, x64, NoSuf|IsPrefix, {} +rex64xy, 0x4e, x64, NoSuf|IsPrefix, {} +rex64xyz, 0x4f, x64, NoSuf|IsPrefix, {} +rex.b, 0x41, x64, NoSuf|IsPrefix, {} +rex.x, 0x42, x64, NoSuf|IsPrefix, {} +rex.xb, 0x43, x64, NoSuf|IsPrefix, {} +rex.r, 0x44, x64, NoSuf|IsPrefix, {} +rex.rb, 0x45, x64, NoSuf|IsPrefix, {} +rex.rx, 0x46, x64, NoSuf|IsPrefix, {} +rex.rxb, 0x47, x64, NoSuf|IsPrefix, {} +rex.w, 0x48, x64, NoSuf|IsPrefix, {} +rex.wb, 0x49, x64, NoSuf|IsPrefix, {} +rex.wx, 0x4a, x64, NoSuf|IsPrefix, {} +rex.wxb, 0x4b, x64, NoSuf|IsPrefix, {} +rex.wr, 0x4c, x64, NoSuf|IsPrefix, {} +rex.wrb, 0x4d, x64, NoSuf|IsPrefix, {} +rex.wrx, 0x4e, x64, NoSuf|IsPrefix, {} +rex.wrxb, 0x4f, x64, NoSuf|IsPrefix, {} // Pseudo prefixes (base_opcode == PSEUDO_PREFIX) <pseudopfx:ident:cpu, disp8:Disp8:0, disp16:Disp16:0, disp32:Disp32:0, + load:Load:0, store:Store:0, + vex:VEX:0, vex2:VEX:0, vex3:VEX3:0, evex:EVEX:0, + - rex:REX:Cpu64, nooptimize:NoOptimize:0> + rex:REX:x64, nooptimize:NoOptimize:0> {<pseudopfx>}, PSEUDO_PREFIX/Prefix_<pseudopfx:ident>, <pseudopfx:cpu>, NoSuf|IsPrefix, {} // 486 extensions. -bswap, 0xfc8, Cpu486, No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64 } -xadd, 0xfc0, Cpu486, W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -cmpxchg, 0xfb0, Cpu486, W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -invd, 0xf08, Cpu486, NoSuf, {} -wbinvd, 0xf09, Cpu486, NoSuf, {} -invlpg, 0xf01/7, Cpu486, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +bswap, 0xfc8, i486, No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64 } +xadd, 0xfc0, i486, W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +cmpxchg, 0xfb0, i486, W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +invd, 0xf08, i486, NoSuf, {} +wbinvd, 0xf09, i486, NoSuf, {} +invlpg, 0xf01/7, i486, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } // 586 and late 486 extensions. -cpuid, 0xfa2, Cpu486, NoSuf, {} +cpuid, 0xfa2, i486, NoSuf, {} // Pentium extensions. -wrmsr, 0xf30, Cpu586, NoSuf, {} -rdtsc, 0xf31, Cpu586, NoSuf, {} -rdmsr, 0xf32, Cpu586, NoSuf, {} -cmpxchg8b, 0xfc7/1, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|HLEPrefixLock, { Qword|Unspecified|BaseIndex } +wrmsr, 0xf30, i586, NoSuf, {} +rdtsc, 0xf31, i586, NoSuf, {} +rdmsr, 0xf32, i586, NoSuf, {} +cmpxchg8b, 0xfc7/1, i586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|HLEPrefixLock, { Qword|Unspecified|BaseIndex } // Pentium II/Pentium Pro extensions. -sysenter, 0xf34, Cpu64, Intel64Only|NoSuf, {} -sysenter, 0xf34, Cpu686|CpuNo64, NoSuf, {} -sysexit, 0xf35, Cpu64, Intel64Only|No_bSuf|No_wSuf|No_sSuf, {} -sysexit, 0xf35, Cpu686|CpuNo64, NoSuf, {} -fxsave, 0xfae/0, CpuFXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } -fxsave64, 0xfae/0, CpuFXSR|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } -fxrstor, 0xfae/1, CpuFXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } -fxrstor64, 0xfae/1, CpuFXSR|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } -rdpmc, 0xf33, Cpu686, NoSuf, {} +sysenter, 0xf34, x64, Intel64Only|NoSuf, {} +sysenter, 0xf34, i686|No64, NoSuf, {} +sysexit, 0xf35, x64, Intel64Only|No_bSuf|No_wSuf|No_sSuf, {} +sysexit, 0xf35, i686|No64, NoSuf, {} +fxsave, 0xfae/0, FXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } +fxsave64, 0xfae/0, FXSR|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +fxrstor, 0xfae/1, FXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } +fxrstor64, 0xfae/1, FXSR|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +rdpmc, 0xf33, i686, NoSuf, {} // official undefined instr. -ud2, 0xf0b, Cpu186, NoSuf, {} +ud2, 0xf0b, i186, NoSuf, {} // alias for ud2 -ud2a, 0xf0b, Cpu186, NoSuf, {} +ud2a, 0xf0b, i186, NoSuf, {} // 2nd. official undefined instr. -ud1, 0xfb9, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +ud1, 0xfb9, i186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // alias for ud1 -ud2b, 0xfb9, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +ud2b, 0xfb9, i186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // 3rd official undefined instr (older CPUs don't take a ModR/M byte) -ud0, 0xfff, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } - -cmov<cc>, 0xf4<cc:opc>, CpuCMOV, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } - -fcmovb, 0xdac0, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovnae, 0xdac0, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmove, 0xdac8, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovbe, 0xdad0, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovna, 0xdad0, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovu, 0xdad8, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovae, 0xdbc0, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovnb, 0xdbc0, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovne, 0xdbc8, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmova, 0xdbd0, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovnbe, 0xdbd0, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcmovnu, 0xdbd8, Cpu687, NoSuf, { FloatReg, FloatAcc } - -fcomi, 0xdbf0, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcomi, 0xdbf1, Cpu687, NoSuf, {} -fcomi, 0xdbf0, Cpu687, NoSuf, { FloatReg } -fucomi, 0xdbe8, Cpu687, NoSuf, { FloatReg, FloatAcc } -fucomi, 0xdbe9, Cpu687, NoSuf, {} -fucomi, 0xdbe8, Cpu687, NoSuf, { FloatReg } -fcomip, 0xdff0, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcomip, 0xdff1, Cpu687, NoSuf, {} -fcomip, 0xdff0, Cpu687, NoSuf, { FloatReg } -fcompi, 0xdff0, Cpu687, NoSuf, { FloatReg, FloatAcc } -fcompi, 0xdff1, Cpu687, NoSuf, {} -fcompi, 0xdff0, Cpu687, NoSuf, { FloatReg } -fucomip, 0xdfe8, Cpu687, NoSuf, { FloatReg, FloatAcc } -fucomip, 0xdfe9, Cpu687, NoSuf, {} -fucomip, 0xdfe8, Cpu687, NoSuf, { FloatReg } -fucompi, 0xdfe8, Cpu687, NoSuf, { FloatReg, FloatAcc } -fucompi, 0xdfe9, Cpu687, NoSuf, {} -fucompi, 0xdfe8, Cpu687, NoSuf, { FloatReg } +ud0, 0xfff, i186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + +cmov<cc>, 0xf4<cc:opc>, CMOV, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + +fcmovb, 0xdac0, i687, NoSuf, { FloatReg, FloatAcc } +fcmovnae, 0xdac0, i687, NoSuf, { FloatReg, FloatAcc } +fcmove, 0xdac8, i687, NoSuf, { FloatReg, FloatAcc } +fcmovbe, 0xdad0, i687, NoSuf, { FloatReg, FloatAcc } +fcmovna, 0xdad0, i687, NoSuf, { FloatReg, FloatAcc } +fcmovu, 0xdad8, i687, NoSuf, { FloatReg, FloatAcc } +fcmovae, 0xdbc0, i687, NoSuf, { FloatReg, FloatAcc } +fcmovnb, 0xdbc0, i687, NoSuf, { FloatReg, FloatAcc } +fcmovne, 0xdbc8, i687, NoSuf, { FloatReg, FloatAcc } +fcmova, 0xdbd0, i687, NoSuf, { FloatReg, FloatAcc } +fcmovnbe, 0xdbd0, i687, NoSuf, { FloatReg, FloatAcc } +fcmovnu, 0xdbd8, i687, NoSuf, { FloatReg, FloatAcc } + +fcomi, 0xdbf0, i687, NoSuf, { FloatReg, FloatAcc } +fcomi, 0xdbf1, i687, NoSuf, {} +fcomi, 0xdbf0, i687, NoSuf, { FloatReg } +fucomi, 0xdbe8, i687, NoSuf, { FloatReg, FloatAcc } +fucomi, 0xdbe9, i687, NoSuf, {} +fucomi, 0xdbe8, i687, NoSuf, { FloatReg } +fcomip, 0xdff0, i687, NoSuf, { FloatReg, FloatAcc } +fcomip, 0xdff1, i687, NoSuf, {} +fcomip, 0xdff0, i687, NoSuf, { FloatReg } +fcompi, 0xdff0, i687, NoSuf, { FloatReg, FloatAcc } +fcompi, 0xdff1, i687, NoSuf, {} +fcompi, 0xdff0, i687, NoSuf, { FloatReg } +fucomip, 0xdfe8, i687, NoSuf, { FloatReg, FloatAcc } +fucomip, 0xdfe9, i687, NoSuf, {} +fucomip, 0xdfe8, i687, NoSuf, { FloatReg } +fucompi, 0xdfe8, i687, NoSuf, { FloatReg, FloatAcc } +fucompi, 0xdfe9, i687, NoSuf, {} +fucompi, 0xdfe8, i687, NoSuf, { FloatReg } // Pentium4 extensions. -movnti, 0xfc3, CpuSSE2, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } -clflush, 0xfae/7, CpuClflush, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -lfence, 0xfaee8, CpuSSE2, NoSuf, {} -mfence, 0xfaef0, CpuSSE2, NoSuf, {} +movnti, 0xfc3, SSE2, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +clflush, 0xfae/7, Clflush, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +lfence, 0xfaee8, SSE2, NoSuf, {} +mfence, 0xfaef0, SSE2, NoSuf, {} // Processors that do not support PAUSE treat this opcode as a NOP instruction. -pause, 0xf390, Cpu186, NoSuf, {} +pause, 0xf390, i186, NoSuf, {} // MMX/SSE2 instructions. <mmx:cpu:pfx:attr:shimm:reg:mem, + - $avx:CpuAVX:66:Vex128|VexVVVV|VexW0|SSE2AVX:Vex128|VexVVVV=2|VexW0|SSE2AVX:RegXMM:Xmmword, + - $sse:CpuSSE2:66:::RegXMM:Xmmword, + - $mmx:CpuMMX::::RegMMX:Qword> + $avx:AVX:66:Vex128|VexVVVV|VexW0|SSE2AVX:Vex128|VexVVVV=2|VexW0|SSE2AVX:RegXMM:Xmmword, + + $sse:SSE2:66:::RegXMM:Xmmword, + + $mmx:MMX::::RegMMX:Qword> <sse2:cpu:attr:scal:vvvv:shimm, + - $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV:Vex128|VexVVVV=2|VexW0|SSE2AVX, + - $sse:CpuSSE2::::> + $avx:AVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV:Vex128|VexVVVV=2|VexW0|SSE2AVX, + + $sse:SSE2::::> <bw:opc:vexw:elem:kcpu:kpfx:cpubmi, + - b:0:VexW0:Byte:CpuAVX512DQ:66:CpuAVX512VBMI, + - w:1:VexW1:Word:CpuAVX512F::CpuAVX512BW> + b:0:VexW0:Byte:AVX512DQ:66:AVX512VBMI, + + w:1:VexW1:Word:AVX512F::AVX512BW> <dq:opc:vexw:vexw64:elem:cpu64:gpr:kpfx, + d:0:VexW0::Dword::Reg32:66, + - q:1:VexW1:VexW1:Qword:Cpu64:Reg64:> + q:1:VexW1:VexW1:Qword:x64:Reg64:> -emms, 0xf77, CpuMMX, NoSuf, {} +emms, 0xf77, MMX, NoSuf, {} // These really shouldn't allow for Reg64 (movq is the right mnemonic for // copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's // spec). AMD's spec, having been in existence for much longer, failed to // recognize that and specified movd for 32- and 64-bit operations. -movd, 0x666e, CpuAVX, D|Modrm|Vex128|Space0F|VexW0|NoSuf|SSE2AVX, { Reg32|Unspecified|BaseIndex, RegXMM } -movd, 0x666e, CpuAVX|Cpu64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|BaseIndex, RegXMM } -movd, 0x660f6e, CpuSSE2, D|Modrm|IgnoreSize|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } -movd, 0x660f6e, CpuSSE2|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegXMM } +movd, 0x666e, AVX, D|Modrm|Vex128|Space0F|VexW0|NoSuf|SSE2AVX, { Reg32|Unspecified|BaseIndex, RegXMM } +movd, 0x666e, AVX|x64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|BaseIndex, RegXMM } +movd, 0x660f6e, SSE2, D|Modrm|IgnoreSize|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } +movd, 0x660f6e, SSE2|x64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegXMM } // The MMX templates have to remain after at least the SSE2AVX ones. -movd, 0xf6e, CpuMMX, D|Modrm|IgnoreSize|NoSuf, { Reg32|Unspecified|BaseIndex, RegMMX } -movd, 0xf6e, CpuMMX|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegMMX } -movq, 0xf37e, CpuAVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -movq, 0x66d6, CpuAVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } -movq, 0x666e, CpuAVX|Cpu64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM } -movq, 0xf30f7e, CpuSSE2, Load|Modrm|NoSuf, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM } -movq, 0x660fd6, CpuSSE2, Modrm|NoSuf, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM } -movq, 0x660f6e, CpuSSE2|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } +movd, 0xf6e, MMX, D|Modrm|IgnoreSize|NoSuf, { Reg32|Unspecified|BaseIndex, RegMMX } +movd, 0xf6e, MMX|x64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegMMX } +movq, 0xf37e, AVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +movq, 0x66d6, AVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } +movq, 0x666e, AVX|x64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM } +movq, 0xf30f7e, SSE2, Load|Modrm|NoSuf, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM } +movq, 0x660fd6, SSE2, Modrm|NoSuf, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM } +movq, 0x660f6e, SSE2|x64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } // The MMX templates have to remain after at least the SSE2AVX ones. -movq, 0xf6f, CpuMMX, D|Modrm|NoSuf, { Unspecified|Qword|BaseIndex|RegMMX, RegMMX } -movq, 0xf6e, CpuMMX|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegMMX } +movq, 0xf6f, MMX, D|Modrm|NoSuf, { Unspecified|Qword|BaseIndex|RegMMX, RegMMX } +movq, 0xf6e, MMX|x64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegMMX } packssdw<mmx>, 0x<mmx:pfx>0f6b, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } packsswb<mmx>, 0x<mmx:pfx>0f63, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } packuswb<mmx>, 0x<mmx:pfx>0f67, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } padd<bw><mmx>, 0x<mmx:pfx>0ffc | <bw:opc>, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } paddd<mmx>, 0x<mmx:pfx>0ffe, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } paddq<sse2>, 0x660fd4, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -paddq, 0xfd4, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +paddq, 0xfd4, SSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } padds<bw><mmx>, 0x<mmx:pfx>0fec | <bw:opc>, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } paddus<bw><mmx>, 0x<mmx:pfx>0fdc | <bw:opc>, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } pand<mmx>, 0x<mmx:pfx>0fdb, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } @@ -1024,25 +1039,25 @@ psrl<dq><mmx>, 0x<mmx:pfx>0f72 | <dq:opc>/2, <mmx:cpu>, Modrm|<mmx:shimm>|NoSuf, psub<bw><mmx>, 0x<mmx:pfx>0ff8 | <bw:opc>, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } psubd<mmx>, 0x<mmx:pfx>0ffa, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } psubq<sse2>, 0x660ffb, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -psubq, 0xffb, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +psubq, 0xffb, SSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } psubs<bw><mmx>, 0x<mmx:pfx>0fe8 | <bw:opc>, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } psubus<bw><mmx>, 0x<mmx:pfx>0fd8 | <bw:opc>, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } punpckhbw<mmx>, 0x<mmx:pfx>0f68, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } punpckhwd<mmx>, 0x<mmx:pfx>0f69, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } punpckhdq<mmx>, 0x<mmx:pfx>0f6a, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } punpcklbw<sse2>, 0x660f60, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -punpcklbw, 0xf60, CpuMMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } +punpcklbw, 0xf60, MMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } punpcklwd<sse2>, 0x660f61, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -punpcklwd, 0xf61, CpuMMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } +punpcklwd, 0xf61, MMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } punpckldq<sse2>, 0x660f62, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -punpckldq, 0xf62, CpuMMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } +punpckldq, 0xf62, MMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } pxor<mmx>, 0x<mmx:pfx>0fef, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } // SSE instructions. <sse:cpu:attr:scal:vvvv, + - $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV, + - $sse:CpuSSE:::> + $avx:AVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV, + + $sse:SSE:::> <frel:imm:comm, eq:0:C, lt:1:, le:2:, unord:3:C, neq:4:C, nlt:5:, nle:6:, ord:7:C> addps<sse>, 0x0f58, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1054,78 +1069,78 @@ cmp<frel>ss<sse>, 0xf30fc2/<frel:imm>, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|<f cmpps<sse>, 0x0fc2, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } cmpss<sse>, 0xf30fc2, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM } comiss<sse>, 0x0f2f, <sse:cpu>, Modrm|<sse:scal>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -cvtpi2ps, 0xf2a, CpuSSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegXMM } -cvtps2pi, 0xf2d, CpuSSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } -cvtsi2ss<sse>, 0xf30f2a, <sse:cpu>|CpuNo64, Modrm|<sse:scal>|<sse:vvvv>|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, RegXMM } -cvtsi2ss, 0xf32a, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } -cvtsi2ss, 0xf32a, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } -cvtsi2ss, 0xf30f2a, CpuSSE|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } -cvtsi2ss, 0xf30f2a, CpuSSE|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } -cvtss2si, 0xf32d, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -cvtss2si, 0xf30f2d, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -cvttps2pi, 0xf2c, CpuSSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } -cvttss2si, 0xf32c, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -cvttss2si, 0xf30f2c, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +cvtpi2ps, 0xf2a, SSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegXMM } +cvtps2pi, 0xf2d, SSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } +cvtsi2ss<sse>, 0xf30f2a, <sse:cpu>|No64, Modrm|<sse:scal>|<sse:vvvv>|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, RegXMM } +cvtsi2ss, 0xf32a, AVX|x64, Modrm|Vex=3|Space0F|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +cvtsi2ss, 0xf32a, AVX|x64, Modrm|Vex=3|Space0F|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +cvtsi2ss, 0xf30f2a, SSE|x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +cvtsi2ss, 0xf30f2a, SSE|x64, Modrm|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +cvtss2si, 0xf32d, AVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +cvtss2si, 0xf30f2d, SSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +cvttps2pi, 0xf2c, SSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } +cvttss2si, 0xf32c, AVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +cvttss2si, 0xf30f2c, SSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } divps<sse>, 0x0f5e, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } divss<sse>, 0xf30f5e, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } ldmxcsr<sse>, 0x0fae/2, <sse:cpu>, Modrm|<sse:attr>|NoSuf, { Dword|Unspecified|BaseIndex } -maskmovq, 0xff7, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { RegMMX, RegMMX } +maskmovq, 0xff7, SSE|3dnowA, Modrm|NoSuf, { RegMMX, RegMMX } maxps<sse>, 0x0f5f, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } maxss<sse>, 0xf30f5f, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } minps<sse>, 0x0f5d, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } minss<sse>, 0xf30f5d, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } movaps<sse>, 0x0f28, <sse:cpu>, D|Modrm|<sse:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } movhlps<sse>, 0x0f12, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM, RegXMM } -movhps, 0x16, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } -movhps, 0x17, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } -movhps, 0xf16, CpuSSE, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } +movhps, 0x16, AVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } +movhps, 0x17, AVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } +movhps, 0xf16, SSE, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } movlhps<sse>, 0x0f16, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM, RegXMM } -movlps, 0x12, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } -movlps, 0x13, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } -movlps, 0xf12, CpuSSE, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } +movlps, 0x12, AVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } +movlps, 0x13, AVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } +movlps, 0xf12, SSE, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } movmskps<sse>, 0x0f50, <sse:cpu>, Modrm|<sse:attr>|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegXMM, Reg32|Reg64 } movntps<sse>, 0x0f2b, <sse:cpu>, Modrm|<sse:attr>|NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } -movntq, 0xfe7, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { RegMMX, Qword|Unspecified|BaseIndex } +movntq, 0xfe7, SSE|3dnowA, Modrm|NoSuf, { RegMMX, Qword|Unspecified|BaseIndex } movntdq<sse2>, 0x660fe7, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } -movss, 0xf310, CpuAVX, D|Modrm|VexLIG|Space0F|VexW0|NoSuf|SSE2AVX, { Dword|Unspecified|BaseIndex, RegXMM } -movss, 0xf310, CpuAVX, D|Modrm|Vex=3|Space0F|VexVVVV=1|VexW=1|NoSuf|SSE2AVX, { RegXMM, RegXMM } -movss, 0xf30f10, CpuSSE, D|Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +movss, 0xf310, AVX, D|Modrm|VexLIG|Space0F|VexW0|NoSuf|SSE2AVX, { Dword|Unspecified|BaseIndex, RegXMM } +movss, 0xf310, AVX, D|Modrm|Vex=3|Space0F|VexVVVV=1|VexW=1|NoSuf|SSE2AVX, { RegXMM, RegXMM } +movss, 0xf30f10, SSE, D|Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } movups<sse>, 0x0f10, <sse:cpu>, D|Modrm|<sse:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } mulps<sse>, 0x0f59, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } mulss<sse>, 0xf30f59, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } orps<sse>, 0x0f56, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pavg<bw>, 0xfe0 | (3 * <bw:opc>), CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pavg<bw>, 0xfe0 | (3 * <bw:opc>), SSE|3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } pavg<bw><sse2>, 0x660fe0 | (3 * <bw:opc>), <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } pextrw<sse2>, 0x660fc5, <sse2:cpu>, Load|Modrm|<sse2:attr>|No_bSuf|No_wSuf|No_sSuf|IgnoreSize|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } -pextrw, 0xfc5, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Imm8, RegMMX, Reg32|Reg64 } +pextrw, 0xfc5, SSE|3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Imm8, RegMMX, Reg32|Reg64 } pinsrw<sse2>, 0x660fc4, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|No_bSuf|No_wSuf|No_sSuf|IgnoreSize|NoRex64, { Imm8, Reg32|Reg64, RegXMM } pinsrw<sse2>, 0x660fc4, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM } -pinsrw, 0xfc4, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Imm8, Reg32|Reg64, RegMMX } -pinsrw, 0xfc4, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegMMX } +pinsrw, 0xfc4, SSE|3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Imm8, Reg32|Reg64, RegMMX } +pinsrw, 0xfc4, SSE|3dnowA, Modrm|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegMMX } pmaxsw<sse2>, 0x660fee, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pmaxsw, 0xfee, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pmaxsw, 0xfee, SSE|3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } pmaxub<sse2>, 0x660fde, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pmaxub, 0xfde, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pmaxub, 0xfde, SSE|3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } pminsw<sse2>, 0x660fea, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pminsw, 0xfea, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pminsw, 0xfea, SSE|3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } pminub<sse2>, 0x660fda, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pminub, 0xfda, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pminub, 0xfda, SSE|3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } pmovmskb<sse2>, 0x660fd7, <sse2:cpu>, Modrm|<sse2:attr>|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegXMM, Reg32|Reg64 } -pmovmskb, 0xfd7, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegMMX, Reg32|Reg64 } +pmovmskb, 0xfd7, SSE|3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegMMX, Reg32|Reg64 } pmulhuw<sse2>, 0x660fe4, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pmulhuw, 0xfe4, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -prefetchnta, 0xf18/0, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -prefetcht0, 0xf18/1, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -prefetcht1, 0xf18/2, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -prefetcht2, 0xf18/3, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -psadbw, 0xff6, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pmulhuw, 0xfe4, SSE|3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +prefetchnta, 0xf18/0, SSE|3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +prefetcht0, 0xf18/1, SSE|3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +prefetcht1, 0xf18/2, SSE|3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +prefetcht2, 0xf18/3, SSE|3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +psadbw, 0xff6, SSE|3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } psadbw<sse2>, 0x660ff6, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pshufw, 0xf70, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Imm8, Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pshufw, 0xf70, SSE|3dnowA, Modrm|NoSuf, { Imm8, Qword|Unspecified|BaseIndex|RegMMX, RegMMX } rcpps<sse>, 0x0f53, <sse:cpu>, Modrm|<sse:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } rcpss<sse>, 0xf30f53, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } rsqrtps<sse>, 0x0f52, <sse:cpu>, Modrm|<sse:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } rsqrtss<sse>, 0xf30f52, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -sfence, 0xfaef8, CpuSSE|Cpu3dnowA, NoSuf, {} +sfence, 0xfaef8, SSE|3dnowA, NoSuf, {} shufps<sse>, 0x0fc6, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } sqrtps<sse>, 0x0f51, <sse:cpu>, Modrm|<sse:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } sqrtss<sse>, 0xf30f51, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } @@ -1148,14 +1163,14 @@ cmp<frel>sd<sse2>, 0xf20fc2/<frel:imm>, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv cmppd<sse2>, 0x660fc2, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } cmpsd<sse2>, 0xf20fc2, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM } comisd<sse2>, 0x660f2f, <sse2:cpu>, Modrm|<sse2:scal>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -cvtpi2pd, 0x660f2a, CpuSSE2, Modrm|NoSuf, { RegMMX, RegXMM } -cvtpi2pd, 0xf3e6, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } -cvtpi2pd, 0x660f2a, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } -cvtsi2sd<sse2>, 0xf20f2a, <sse2:cpu>|CpuNo64, Modrm|IgnoreSize|<sse2:scal>|<sse2:vvvv>|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, RegXMM } -cvtsi2sd, 0xf22a, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } -cvtsi2sd, 0xf22a, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } -cvtsi2sd, 0xf20f2a, CpuSSE2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } -cvtsi2sd, 0xf20f2a, CpuSSE2|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +cvtpi2pd, 0x660f2a, SSE2, Modrm|NoSuf, { RegMMX, RegXMM } +cvtpi2pd, 0xf3e6, AVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } +cvtpi2pd, 0x660f2a, SSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } +cvtsi2sd<sse2>, 0xf20f2a, <sse2:cpu>|No64, Modrm|IgnoreSize|<sse2:scal>|<sse2:vvvv>|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, RegXMM } +cvtsi2sd, 0xf22a, AVX|x64, Modrm|Vex=3|Space0F|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +cvtsi2sd, 0xf22a, AVX|x64, Modrm|Vex=3|Space0F|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +cvtsi2sd, 0xf20f2a, SSE2|x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } +cvtsi2sd, 0xf20f2a, SSE2|x64, Modrm|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } divpd<sse2>, 0x660f5e, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } divsd<sse2>, 0xf20f5e, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } maxpd<sse2>, 0x660f5f, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1163,17 +1178,17 @@ maxsd<sse2>, 0xf20f5f, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Qword| minpd<sse2>, 0x660f5d, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } minsd<sse2>, 0xf20f5d, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } movapd<sse2>, 0x660f28, <sse2:cpu>, D|Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -movhpd, 0x6616, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } -movhpd, 0x6617, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } -movhpd, 0x660f16, CpuSSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } -movlpd, 0x6612, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } -movlpd, 0x6613, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } -movlpd, 0x660f12, CpuSSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } +movhpd, 0x6616, AVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } +movhpd, 0x6617, AVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } +movhpd, 0x660f16, SSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } +movlpd, 0x6612, AVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } +movlpd, 0x6613, AVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } +movlpd, 0x660f12, SSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } movmskpd<sse2>, 0x660f50, <sse2:cpu>, Modrm|<sse2:attr>|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|NoRex64, { RegXMM, Reg32|Reg64 } movntpd<sse2>, 0x660f2b, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } -movsd, 0xf210, CpuAVX, D|Modrm|VexLIG|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } -movsd, 0xf210, CpuAVX, D|Modrm|Vex=3|Space0F|VexVVVV=1|VexW=1|NoSuf|SSE2AVX, { RegXMM, RegXMM } -movsd, 0xf20f10, CpuSSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +movsd, 0xf210, AVX, D|Modrm|VexLIG|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } +movsd, 0xf210, AVX, D|Modrm|Vex=3|Space0F|VexVVVV=1|VexW=1|NoSuf|SSE2AVX, { RegXMM, RegXMM } +movsd, 0xf20f10, SSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } movupd<sse2>, 0x660f10, <sse2:cpu>, D|Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } mulpd<sse2>, 0x660f59, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } mulsd<sse2>, 0xf20f59, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } @@ -1190,27 +1205,27 @@ xorpd<sse2>, 0x660f57, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegX cvtdq2pd<sse2>, 0xf30fe6, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } cvtpd2dq<sse2>, 0xf20fe6, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } cvtdq2ps<sse2>, 0x0f5b, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -cvtpd2pi, 0x660f2d, CpuSSE2, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegMMX } +cvtpd2pi, 0x660f2d, SSE2, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegMMX } cvtpd2ps<sse2>, 0x660f5a, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } cvtps2pd<sse2>, 0x0f5a, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } cvtps2dq<sse2>, 0x660f5b, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -cvtsd2si, 0xf22d, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -cvtsd2si, 0xf20f2d, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +cvtsd2si, 0xf22d, AVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +cvtsd2si, 0xf20f2d, SSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } cvtsd2ss<sse2>, 0xf20f5a, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } cvtss2sd<sse2>, 0xf30f5a, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -cvttpd2pi, 0x660f2c, CpuSSE2, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegMMX } -cvttsd2si, 0xf22c, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -cvttsd2si, 0xf20f2c, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +cvttpd2pi, 0x660f2c, SSE2, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegMMX } +cvttsd2si, 0xf22c, AVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +cvttsd2si, 0xf20f2c, SSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } cvttpd2dq<sse2>, 0x660fe6, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } cvttps2dq<sse2>, 0xf30f5b, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } maskmovdqu<sse2>, 0x660ff7, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM, RegXMM } movdqa<sse2>, 0x660f6f, <sse2:cpu>, D|Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } movdqu<sse2>, 0xf30f6f, <sse2:cpu>, D|Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -movdq2q, 0xf20fd6, CpuSSE2, Modrm|NoSuf, { RegXMM, RegMMX } -movq2dq, 0xf30fd6, CpuSSE2, Modrm|NoSuf, { RegMMX, RegXMM } +movdq2q, 0xf20fd6, SSE2, Modrm|NoSuf, { RegXMM, RegMMX } +movq2dq, 0xf30fd6, SSE2, Modrm|NoSuf, { RegMMX, RegXMM } pmuludq<sse2>, 0x660ff4, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pmuludq, 0xff4, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pmuludq, 0xff4, SSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } pshufd<sse2>, 0x660f70, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } pshufhw<sse2>, 0xf30f70, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } pshuflw<sse2>, 0xf20f70, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1223,7 +1238,7 @@ punpcklqdq<sse2>, 0x660f6c, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { R // SSE3 instructions. -<sse3:cpu:attr:vvvv, $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexVVVV, $sse:CpuSSE3::> +<sse3:cpu:attr:vvvv, $avx:AVX:Vex128|VexW0|SSE2AVX:VexVVVV, $sse:SSE3::> addsubpd<sse3>, 0x660fd0, <sse3:cpu>, Modrm|<sse3:attr>|<sse3:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } addsubps<sse3>, 0xf20fd0, <sse3:cpu>, Modrm|<sse3:attr>|<sse3:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1238,69 +1253,69 @@ movsldup<sse3>, 0xf30f12, <sse3:cpu>, Modrm|<sse3:attr>|NoSuf, { RegXMM|Unspecif // FPU instructions also covered by SSE3 CPUID flag. -fisttp, 0xdf/1, CpuFISTTP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } -fisttp, 0xdd/1, CpuFISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex } -fisttpll, 0xdd/1, CpuFISTTP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } +fisttp, 0xdf/1, FISTTP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex } +fisttp, 0xdd/1, FISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex } +fisttpll, 0xdd/1, FISTTP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } // CMPXCHG16B instruction. -cmpxchg16b, 0xfc7/1, CpuCX16|Cpu64, Modrm|NoSuf|Size64|LockPrefixOk, { Oword|Unspecified|BaseIndex } +cmpxchg16b, 0xfc7/1, CX16|x64, Modrm|NoSuf|Size64|LockPrefixOk, { Oword|Unspecified|BaseIndex } // MONITOR instructions. -monitor, 0xf01c8, CpuSSE3, NoSuf, {} +monitor, 0xf01c8, SSE3, NoSuf, {} // monitor is very special. CX and DX are always 32 bits. The // address size override prefix can be used to overrride the AX size in // all modes. -monitor, 0xf01c8, CpuSSE3, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } +monitor, 0xf01c8, SSE3, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } // The 64-bit form exists only for compatibility with older gas. -monitor, 0xf01c8, CpuSSE3|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } -mwait, 0xf01c9, CpuSSE3, NoSuf, {} +monitor, 0xf01c8, SSE3|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } +mwait, 0xf01c9, SSE3, NoSuf, {} // mwait is very special. AX and CX are always 32 bits. // The 64-bit form exists only for compatibility with older gas. -mwait, 0xf01c9, CpuSSE3, CheckRegSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword } +mwait, 0xf01c9, SSE3, CheckRegSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword } // VMX instructions. -vmcall, 0xf01c1, CpuVMX, NoSuf, {} -vmclear, 0x660fc7/6, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } -vmlaunch, 0xf01c2, CpuVMX, NoSuf, {} -vmresume, 0xf01c3, CpuVMX, NoSuf, {} -vmptrld, 0xfc7/6, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } -vmptrst, 0xfc7/7, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } -vmread, 0xf78, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32, Reg32|Unspecified|BaseIndex } -vmread, 0xf78, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Reg64, Reg64|Qword|Unspecified|BaseIndex } -vmwrite, 0xf79, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32 } -vmwrite, 0xf79, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Reg64|Qword|Unspecified|BaseIndex, Reg64 } -vmxoff, 0xf01c4, CpuVMX, NoSuf, {} -vmxon, 0xf30fc7/6, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } +vmcall, 0xf01c1, VMX, NoSuf, {} +vmclear, 0x660fc7/6, VMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } +vmlaunch, 0xf01c2, VMX, NoSuf, {} +vmresume, 0xf01c3, VMX, NoSuf, {} +vmptrld, 0xfc7/6, VMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } +vmptrst, 0xfc7/7, VMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } +vmread, 0xf78, VMX|No64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32, Reg32|Unspecified|BaseIndex } +vmread, 0xf78, VMX|x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Reg64, Reg64|Qword|Unspecified|BaseIndex } +vmwrite, 0xf79, VMX|No64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32 } +vmwrite, 0xf79, VMX|x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Reg64|Qword|Unspecified|BaseIndex, Reg64 } +vmxoff, 0xf01c4, VMX, NoSuf, {} +vmxon, 0xf30fc7/6, VMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } // VMFUNC instruction -vmfunc, 0xf01d4, CpuVMFUNC, NoSuf, {} +vmfunc, 0xf01d4, VMFUNC, NoSuf, {} // SMX instructions. -getsec, 0xf37, CpuSMX, NoSuf, {} +getsec, 0xf37, SMX, NoSuf, {} // EPT instructions. -invept, 0x660f3880, CpuEPT|CpuNo64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } -invept, 0x660f3880, CpuEPT|Cpu64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } -invvpid, 0x660f3881, CpuEPT|CpuNo64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } -invvpid, 0x660f3881, CpuEPT|Cpu64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } +invept, 0x660f3880, EPT|No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } +invept, 0x660f3880, EPT|x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } +invvpid, 0x660f3881, EPT|No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } +invvpid, 0x660f3881, EPT|x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } // INVPCID instruction -invpcid, 0x660f3882, CpuINVPCID|CpuNo64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } -invpcid, 0x660f3882, CpuINVPCID|Cpu64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } +invpcid, 0x660f3882, INVPCID|No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } +invpcid, 0x660f3882, INVPCID|x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } // SSSE3 instructions. <ssse3:cpu:pfx:attr:vvvv:reg:mem, + - $avx:CpuAVX:66:Vex128|VexW0|SSE2AVX:VexVVVV:RegXMM:Xmmword, + - $sse:CpuSSSE3:66:::RegXMM:Xmmword, + - $mmx:CpuSSSE3::::RegMMX:Qword> + $avx:AVX:66:Vex128|VexW0|SSE2AVX:VexVVVV:RegXMM:Xmmword, + + $sse:SSSE3:66:::RegXMM:Xmmword, + + $mmx:SSSE3::::RegMMX:Qword> phaddw<ssse3>, 0x<ssse3:pfx>0f3801, <ssse3:cpu>, Modrm|<ssse3:attr>|<ssse3:vvvv>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } phaddd<ssse3>, 0x<ssse3:pfx>0f3802, <ssse3:cpu>, Modrm|<ssse3:attr>|<ssse3:vvvv>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } @@ -1319,40 +1334,40 @@ pabsd<ssse3>, 0x<ssse3:pfx>0f381e, <ssse3:cpu>, Modrm|<ssse3:attr>|NoSuf, { <sss // SSE4.1 instructions. -<sse41:cpu:attr:scal:vvvv, $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV, $sse:CpuSSE4_1:::> +<sse41:cpu:attr:scal:vvvv, $avx:AVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV, $sse:SSE4_1:::> <sd:ppfx:spfx:opc:vexw:elem, s::f3:0:VexW0:Dword, d:66:f2:1:VexW1:Qword> blendp<sd><sse41>, 0x660f3a0c | <sd:opc>, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -blendvp<sd>, 0x664a | <sd:opc>, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -blendvp<sd>, 0x664a | <sd:opc>, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } -blendvp<sd>, 0x660f3814 | <sd:opc>, CpuSSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -blendvp<sd>, 0x660f3814 | <sd:opc>, CpuSSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +blendvp<sd>, 0x664a | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } +blendvp<sd>, 0x664a | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } +blendvp<sd>, 0x660f3814 | <sd:opc>, SSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } +blendvp<sd>, 0x660f3814 | <sd:opc>, SSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } dpp<sd><sse41>, 0x660f3a40 | <sd:opc>, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -extractps, 0x6617, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } -extractps, 0x6617, CpuAVX|Cpu64, RegMem|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64 } -extractps, 0x660f3a17, CpuSSE4_1, Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } -extractps, 0x660f3a17, CpuSSE4_1|Cpu64, RegMem|NoSuf|NoRex64, { Imm8, RegXMM, Reg64 } +extractps, 0x6617, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } +extractps, 0x6617, AVX|x64, RegMem|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64 } +extractps, 0x660f3a17, SSE4_1, Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } +extractps, 0x660f3a17, SSE4_1|x64, RegMem|NoSuf|NoRex64, { Imm8, RegXMM, Reg64 } insertps<sse41>, 0x660f3a21, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM } movntdqa<sse41>, 0x660f382a, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Xmmword|Unspecified|BaseIndex, RegXMM } mpsadbw<sse41>, 0x660f3a42, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } packusdw<sse41>, 0x660f382b, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pblendvb, 0x664c, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -pblendvb, 0x664c, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } -pblendvb, 0x660f3810, CpuSSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -pblendvb, 0x660f3810, CpuSSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +pblendvb, 0x664c, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } +pblendvb, 0x664c, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } +pblendvb, 0x660f3810, SSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } +pblendvb, 0x660f3810, SSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } pblendw<sse41>, 0x660f3a0e, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } pcmpeqq<sse41>, 0x660f3829, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } pextr<bw><sse41>, 0x660f3a14 | <bw:opc>, <sse41:cpu>, RegMem|<sse41:attr>|NoSuf|IgnoreSize|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } pextr<bw><sse41>, 0x660f3a14 | <bw:opc>, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Imm8, RegXMM, <bw:elem>|Unspecified|BaseIndex } pextrd<sse41>, 0x660f3a16, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf|IgnoreSize, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex } -pextrq, 0x6616, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|VexW1|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } -pextrq, 0x660f3a16, CpuSSE4_1|Cpu64, Modrm|Size64|NoSuf, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } +pextrq, 0x6616, AVX|x64, Modrm|Vex|Space0F3A|VexW1|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } +pextrq, 0x660f3a16, SSE4_1|x64, Modrm|Size64|NoSuf, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } phminposuw<sse41>, 0x660f3841, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } pinsrb<sse41>, 0x660f3a20, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf|IgnoreSize|NoRex64, { Imm8, Reg32|Reg64, RegXMM } pinsrb<sse41>, 0x660f3a20, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM } pinsrd<sse41>, 0x660f3a22, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf|IgnoreSize, { Imm8, Reg32|Unspecified|BaseIndex, RegXMM } -pinsrq, 0x6622, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|VexVVVV=1|VexW1|NoSuf|SSE2AVX, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } -pinsrq, 0x660f3a22, CpuSSE4_1|Cpu64, Modrm|Size64|NoSuf, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } +pinsrq, 0x6622, AVX|x64, Modrm|Vex|Space0F3A|VexVVVV=1|VexW1|NoSuf|SSE2AVX, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } +pinsrq, 0x660f3a22, SSE4_1|x64, Modrm|Size64|NoSuf, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } pmaxsb<sse41>, 0x660f383c, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } pmaxsd<sse41>, 0x660f383d, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } pmaxud<sse41>, 0x660f383f, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1381,68 +1396,68 @@ rounds<sd><sse41>, 0x660f3a0a | <sd:opc>, <sse41:cpu>, Modrm|<sse41:scal>|<sse41 // SSE4.2 instructions. -<sse42:cpu:attr:vvvv, $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexVVVV, $sse:CpuSSE4_2::> +<sse42:cpu:attr:vvvv, $avx:AVX:Vex128|VexW0|SSE2AVX:VexVVVV, $sse:SSE4_2::> pcmpgtq<sse42>, 0x660f3837, <sse42:cpu>, Modrm|<sse42:attr>|<sse42:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pcmpestri<sse42>, 0x660f3a61, <sse42:cpu>|CpuNo64, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -pcmpestri, 0x6661, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } -pcmpestri, 0x660f3a61, CpuSSE4_2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } -pcmpestrm<sse42>, 0x660f3a60, <sse42:cpu>|CpuNo64, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -pcmpestrm, 0x6660, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } -pcmpestrm, 0x660f3a60, CpuSSE4_2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +pcmpestri<sse42>, 0x660f3a61, <sse42:cpu>|No64, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +pcmpestri, 0x6661, AVX|x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +pcmpestri, 0x660f3a61, SSE4_2|x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +pcmpestrm<sse42>, 0x660f3a60, <sse42:cpu>|No64, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +pcmpestrm, 0x6660, AVX|x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +pcmpestrm, 0x660f3a60, SSE4_2|x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } pcmpistri<sse42>, 0x660f3a63, <sse42:cpu>, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } pcmpistrm<sse42>, 0x660f3a62, <sse42:cpu>, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -crc32, 0xf20f38f0, CpuSSE4_2, W|Modrm|No_sSuf|No_qSuf, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 } -crc32, 0xf20f38f0, CpuSSE4_2|Cpu64, W|Modrm|No_wSuf|No_lSuf|No_sSuf, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 } +crc32, 0xf20f38f0, SSE4_2, W|Modrm|No_sSuf|No_qSuf, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 } +crc32, 0xf20f38f0, SSE4_2|x64, W|Modrm|No_wSuf|No_lSuf|No_sSuf, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 } // xsave/xrstor New Instructions. -xsave, 0xfae/4, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } -xsave64, 0xfae/4, CpuXsave|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } -xrstor, 0xfae/5, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } -xrstor64, 0xfae/5, CpuXsave|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } -xgetbv, 0xf01d0, CpuXsave, NoSuf, {} -xsetbv, 0xf01d1, CpuXsave, NoSuf, {} +xsave, 0xfae/4, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } +xsave64, 0xfae/4, Xsave|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xrstor, 0xfae/5, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } +xrstor64, 0xfae/5, Xsave|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xgetbv, 0xf01d0, Xsave, NoSuf, {} +xsetbv, 0xf01d1, Xsave, NoSuf, {} // xsaveopt -xsaveopt, 0xfae/6, CpuXsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } -xsaveopt64, 0xfae/6, CpuXsaveopt|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xsaveopt, 0xfae/6, Xsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } +xsaveopt64, 0xfae/6, Xsaveopt|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } // AES instructions. -<aes:cpu:attr:vvvv, $avx:CpuAVX|:Vex128|VexW0|SSE2AVX:VexVVVV, $sse:::> +<aes:cpu:attr:vvvv, $avx:AVX|:Vex128|VexW0|SSE2AVX:VexVVVV, $sse:::> -aesdec<aes>, 0x660f38de, <aes:cpu>CpuAES, Modrm|<aes:attr>|<aes:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -aesdeclast<aes>, 0x660f38df, <aes:cpu>CpuAES, Modrm|<aes:attr>|<aes:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -aesenc<aes>, 0x660f38dc, <aes:cpu>CpuAES, Modrm|<aes:attr>|<aes:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -aesenclast<aes>, 0x660f38dd, <aes:cpu>CpuAES, Modrm|<aes:attr>|<aes:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -aesimc<aes>, 0x660f38db, <aes:cpu>CpuAES, Modrm|<aes:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -aeskeygenassist<aes>, 0x660f3adf, <aes:cpu>CpuAES, Modrm|<aes:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +aesdec<aes>, 0x660f38de, <aes:cpu>AES, Modrm|<aes:attr>|<aes:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +aesdeclast<aes>, 0x660f38df, <aes:cpu>AES, Modrm|<aes:attr>|<aes:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +aesenc<aes>, 0x660f38dc, <aes:cpu>AES, Modrm|<aes:attr>|<aes:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +aesenclast<aes>, 0x660f38dd, <aes:cpu>AES, Modrm|<aes:attr>|<aes:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +aesimc<aes>, 0x660f38db, <aes:cpu>AES, Modrm|<aes:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +aeskeygenassist<aes>, 0x660f3adf, <aes:cpu>AES, Modrm|<aes:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } // VAES -vaesdec, 0x66de, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } -vaesdeclast, 0x66df, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } -vaesenc, 0x66dc, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } -vaesenclast, 0x66dd, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } +vaesdec, 0x66de, VAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } +vaesdeclast, 0x66df, VAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } +vaesenc, 0x66dc, VAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } +vaesenclast, 0x66dd, VAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } // PCLMUL -<pclmul:cpu:attr, $avx:CpuAVX|:Vex128|VexW0|SSE2AVX|VexVVVV, $sse::> +<pclmul:cpu:attr, $avx:AVX|:Vex128|VexW0|SSE2AVX|VexVVVV, $sse::> -pclmulqdq<pclmul>, 0x660f3a44, <pclmul:cpu>CpuPCLMUL, Modrm|<pclmul:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -pclmullqlqdq<pclmul>, 0x660f3a44/0x00, <pclmul:cpu>CpuPCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } -pclmulhqlqdq<pclmul>, 0x660f3a44/0x01, <pclmul:cpu>CpuPCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } -pclmullqhqdq<pclmul>, 0x660f3a44/0x10, <pclmul:cpu>CpuPCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } -pclmulhqhqdq<pclmul>, 0x660f3a44/0x11, <pclmul:cpu>CpuPCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } +pclmulqdq<pclmul>, 0x660f3a44, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +pclmullqlqdq<pclmul>, 0x660f3a44/0x00, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } +pclmulhqlqdq<pclmul>, 0x660f3a44/0x01, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } +pclmullqhqdq<pclmul>, 0x660f3a44/0x10, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } +pclmulhqhqdq<pclmul>, 0x660f3a44/0x11, <pclmul:cpu>PCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } // GFNI -<gfni:cpu:w0:w1, $avx:CpuAVX|:Vex128|VexW0|SSE2AVX|VexVVVV:Vex128|VexW1|SSE2AVX|VexVVVV, $sse:::> +<gfni:cpu:w0:w1, $avx:AVX|:Vex128|VexW0|SSE2AVX|VexVVVV:Vex128|VexW1|SSE2AVX|VexVVVV, $sse:::> -gf2p8affineqb<gfni>, 0x660f3ace, <gfni:cpu>CpuGFNI, Modrm|<gfni:w1>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -gf2p8affineinvqb<gfni>, 0x660f3acf, <gfni:cpu>CpuGFNI, Modrm|<gfni:w1>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -gf2p8mulb<gfni>, 0x660f38cf, <gfni:cpu>CpuGFNI, Modrm|<gfni:w0>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +gf2p8affineqb<gfni>, 0x660f3ace, <gfni:cpu>GFNI, Modrm|<gfni:w1>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +gf2p8affineinvqb<gfni>, 0x660f3acf, <gfni:cpu>GFNI, Modrm|<gfni:w1>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +gf2p8mulb<gfni>, 0x660f38cf, <gfni:cpu>GFNI, Modrm|<gfni:w0>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } // AVX instructions. @@ -1463,366 +1478,366 @@ gf2p8mulb<gfni>, 0x660f38cf, <gfni:cpu>CpuGFNI, Modrm|<gfni:w0>|NoSuf, { RegXMM| x:Vex128:ATTSyntax:RegXMM|Unspecified|BaseIndex, + y:Vex256:ATTSyntax:RegYMM|Unspecified|BaseIndex> -vaddp<sd>, 0x<sd:ppfx>58, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vadds<sd>, 0x<sd:spfx>58, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vaddsubpd, 0x66d0, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vaddsubps, 0xf2d0, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vandnp<sd>, 0x<sd:ppfx>55, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vandp<sd>, 0x<sd:ppfx>54, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vblendp<sd>, 0x660c | <sd:opc>, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vblendvp<sd>, 0x664a | <sd:opc>, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexW0|VexSources=2|CheckRegSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vbroadcastf128, 0x661a, CpuAVX, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } -vbroadcastsd, 0x6619, CpuAVX, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } -vbroadcastss, 0x6618, CpuAVX, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM|RegYMM } -vcmp<frel>p<sd>, 0x<sd:ppfx>c2/0x<frel:imm>, CpuAVX, Modrm|<frel:comm>|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vcmp<frel>s<sd>, 0x<sd:spfx>c2/0x<frel:imm>, CpuAVX, Modrm|<frel:comm>|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } -vcmpp<sd>, 0x<sd:ppfx>c2, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vcmps<sd>, 0x<sd:spfx>c2, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vcomis<sd>, 0x<sd:ppfx>2f, CpuAVX, Modrm|VexLIG|Space0F|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM } -vcvtdq2pd, 0xf3e6, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vcvtdq2pd, 0xf3e6, CpuAVX, Modrm|Vex256|Space0F|VexWIG|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vcvtdq2ps, 0x5b, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vcvtpd2dq<Vxy>, 0xf2e6, CpuAVX, Modrm|<Vxy:vex>|Space0F|VexWIG|NoSuf|<Vxy:syntax>, { <Vxy:dst>, RegXMM } -vcvtpd2ps<Vxy>, 0x665a, CpuAVX, Modrm|<Vxy:vex>|Space0F|VexWIG|NoSuf|<Vxy:syntax>, { <Vxy:dst>, RegXMM } -vcvtps2dq, 0x665b, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vcvtps2pd, 0x5a, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vcvtps2pd, 0x5a, CpuAVX, Modrm|Vex256|Space0F|VexWIG|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vcvts<sd>2si, 0x<sd:spfx>2d, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -vcvtsd2ss, 0xf25a, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vcvtsi2s<sd>, 0x<sd:spfx>2a, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2s<sd>, 0x<sd:spfx>2a, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtss2sd, 0xf35a, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vcvttpd2dq<Vxy>, 0x66e6, CpuAVX, Modrm|<Vxy:vex>|Space0F|VexWIG|NoSuf|<Vxy:syntax>, { <Vxy:dst>, RegXMM } -vcvttps2dq, 0xf35b, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vcvtts<sd>2si, 0x<sd:spfx>2c, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -vdivp<sd>, 0x<sd:ppfx>5e, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vdivs<sd>, 0x<sd:spfx>5e, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vdppd, 0x6641, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vdpps, 0x6640, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vextractf128, 0x6619, CpuAVX, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } -vextractps, 0x6617, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } -vextractps, 0x6617, CpuAVX|Cpu64, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 } -vhaddpd, 0x667c, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vhaddps, 0xf27c, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vhsubpd, 0x667d, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vhsubps, 0xf27d, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vinsertf128, 0x6618, CpuAVX, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM } -vinsertps, 0x6621, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vlddqu, 0xf2f0, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } -vldmxcsr, 0xae/2, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex } -vmaskmovdqu, 0x66f7, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, RegXMM } -vmaskmovp<sd>, 0x662e | <sd:opc>, CpuAVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } -vmaskmovp<sd>, 0x662c | <sd:opc>, CpuAVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vmaxp<sd>, 0x<sd:ppfx>5f, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vmaxs<sd>, 0x<sd:spfx>5f, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vminp<sd>, 0x<sd:ppfx>5d, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vmins<sd>, 0x<sd:spfx>5d, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vmovap<sd>, 0x<sd:ppfx>28, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vaddp<sd>, 0x<sd:ppfx>58, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vadds<sd>, 0x<sd:spfx>58, AVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vaddsubpd, 0x66d0, AVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vaddsubps, 0xf2d0, AVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vandnp<sd>, 0x<sd:ppfx>55, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vandp<sd>, 0x<sd:ppfx>54, AVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vblendp<sd>, 0x660c | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vblendvp<sd>, 0x664a | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexW0|VexSources=2|CheckRegSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vbroadcastf128, 0x661a, AVX, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } +vbroadcastsd, 0x6619, AVX, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } +vbroadcastss, 0x6618, AVX, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM|RegYMM } +vcmp<frel>p<sd>, 0x<sd:ppfx>c2/0x<frel:imm>, AVX, Modrm|<frel:comm>|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vcmp<frel>s<sd>, 0x<sd:spfx>c2/0x<frel:imm>, AVX, Modrm|<frel:comm>|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } +vcmpp<sd>, 0x<sd:ppfx>c2, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vcmps<sd>, 0x<sd:spfx>c2, AVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vcomis<sd>, 0x<sd:ppfx>2f, AVX, Modrm|VexLIG|Space0F|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM } +vcvtdq2pd, 0xf3e6, AVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vcvtdq2pd, 0xf3e6, AVX, Modrm|Vex256|Space0F|VexWIG|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +vcvtdq2ps, 0x5b, AVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vcvtpd2dq<Vxy>, 0xf2e6, AVX, Modrm|<Vxy:vex>|Space0F|VexWIG|NoSuf|<Vxy:syntax>, { <Vxy:dst>, RegXMM } +vcvtpd2ps<Vxy>, 0x665a, AVX, Modrm|<Vxy:vex>|Space0F|VexWIG|NoSuf|<Vxy:syntax>, { <Vxy:dst>, RegXMM } +vcvtps2dq, 0x665b, AVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vcvtps2pd, 0x5a, AVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vcvtps2pd, 0x5a, AVX, Modrm|Vex256|Space0F|VexWIG|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +vcvts<sd>2si, 0x<sd:spfx>2d, AVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +vcvtsd2ss, 0xf25a, AVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vcvtsi2s<sd>, 0x<sd:spfx>2a, AVX, Modrm|VexLIG|Space0F|VexVVVV|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2s<sd>, 0x<sd:spfx>2a, AVX, Modrm|VexLIG|Space0F|VexVVVV|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtss2sd, 0xf35a, AVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vcvttpd2dq<Vxy>, 0x66e6, AVX, Modrm|<Vxy:vex>|Space0F|VexWIG|NoSuf|<Vxy:syntax>, { <Vxy:dst>, RegXMM } +vcvttps2dq, 0xf35b, AVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vcvtts<sd>2si, 0x<sd:spfx>2c, AVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } +vdivp<sd>, 0x<sd:ppfx>5e, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vdivs<sd>, 0x<sd:spfx>5e, AVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vdppd, 0x6641, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vdpps, 0x6640, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vextractf128, 0x6619, AVX, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } +vextractps, 0x6617, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } +vextractps, 0x6617, AVX|x64, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 } +vhaddpd, 0x667c, AVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vhaddps, 0xf27c, AVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vhsubpd, 0x667d, AVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vhsubps, 0xf27d, AVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vinsertf128, 0x6618, AVX, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM } +vinsertps, 0x6621, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vlddqu, 0xf2f0, AVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } +vldmxcsr, 0xae/2, AVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex } +vmaskmovdqu, 0x66f7, AVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, RegXMM } +vmaskmovp<sd>, 0x662e | <sd:opc>, AVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } +vmaskmovp<sd>, 0x662c | <sd:opc>, AVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vmaxp<sd>, 0x<sd:ppfx>5f, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vmaxs<sd>, 0x<sd:spfx>5f, AVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vminp<sd>, 0x<sd:ppfx>5d, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vmins<sd>, 0x<sd:spfx>5d, AVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vmovap<sd>, 0x<sd:ppfx>28, AVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } // vmovd really shouldn't allow for 64bit operand (vmovq is the right // mnemonic for copying between Reg64/Mem64 and RegXMM, as is mandated // by Intel AVX spec). To avoid extra template in gcc x86 backend and // support assembler for AMD64, we accept 64bit operand on vmovd so // that we can use one template for both SSE and AVX instructions. -vmovd, 0x666e, CpuAVX, D|Modrm|Vex=1|Space0F|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } -vmovd, 0x667e, CpuAVX|Cpu64, D|RegMem|Vex=1|Space0F|VexW=2|NoSuf|Size64, { RegXMM, Reg64 } -vmovddup, 0xf212, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vmovddup, 0xf212, CpuAVX, Modrm|Vex=2|Space0F|VexWIG|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM } -vmovdqa, 0x666f, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vmovdqu, 0xf36f, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vmovhlps, 0x12, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } -vmovhp<sd>, 0x<sd:ppfx>16, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vmovhp<sd>, 0x<sd:ppfx>17, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } -vmovlhps, 0x16, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } -vmovlp<sd>, 0x<sd:ppfx>12, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vmovlp<sd>, 0x<sd:ppfx>13, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } -vmovmskp<sd>, 0x<sd:ppfx>50, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { RegXMM|RegYMM, Reg32|Reg64 } -vmovntdq, 0x66e7, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } -vmovntdqa, 0x662a, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } -vmovntp<sd>, 0x<sd:ppfx>2b, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } -vmovq, 0xf37e, CpuAVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vmovq, 0x66d6, CpuAVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } -vmovq, 0x666e, CpuAVX|Cpu64, D|Modrm|Vex=1|Space0F|VexW=2|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } -vmovs<sd>, 0x<sd:spfx>10, CpuAVX, D|Modrm|VexLIG|Space0F|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex, RegXMM } -vmovs<sd>, 0x<sd:spfx>10, CpuAVX, D|Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } -vmovshdup, 0xf316, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vmovsldup, 0xf312, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vmovup<sd>, 0x<sd:ppfx>10, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vmpsadbw, 0x6642, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vmulp<sd>, 0x<sd:ppfx>59, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vmuls<sd>, 0x<sd:spfx>59, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vorp<sd>, 0x<sd:ppfx>56, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpabs<bw>, 0x661c | <bw:opc>, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpabsd, 0x661e, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpackssdw, 0x666b, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpacksswb, 0x6663, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpackusdw, 0x662b, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpackuswb, 0x6667, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpadds<bw>, 0x66ec | <bw:opc>, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpadd<bw>, 0x66fc | <bw:opc>, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpaddd, 0x66fe, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpaddq, 0x66d4, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpaddus<bw>, 0x66dc | <bw:opc>, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpalignr, 0x660f, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpand, 0x66db, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpandn, 0x66df, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpavg<bw>, 0x66e0 | (3 * <bw:opc>), CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpblendvb, 0x664c, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|VexSources=2|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpblendw, 0x660e, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcmpeq<bw>, 0x6674 | <bw:opc>, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcmpeqd, 0x6676, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcmpeqq, 0x6629, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcmpestri, 0x6661, CpuAVX|CpuNo64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } -vpcmpestri, 0x6661, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpcmpestrm, 0x6660, CpuAVX|CpuNo64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } -vpcmpestrm, 0x6660, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpcmpgt<bw>, 0x6664 | <bw:opc>, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcmpgtd, 0x6666, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcmpgtq, 0x6637, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcmpistri, 0x6663, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } -vpcmpistrm, 0x6662, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } -vperm2f128, 0x6606, CpuAVX, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpermilp<sd>, 0x660c | <sd:opc>, CpuAVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpermilp<sd>, 0x6604 | <sd:opc>, CpuAVX, Modrm|Vex|Space0F3A|VexW0|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpextr<dq>, 0x6616, CpuAVX|<dq:cpu64>, Modrm|Vex|Space0F3A|<dq:vexw64>|NoSuf, { Imm8, RegXMM, <dq:gpr>|Unspecified|BaseIndex } -vpextrw, 0x66c5, CpuAVX, Load|Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { Imm8, RegXMM, Reg32|Reg64 } -vpextr<bw>, 0x6614 | <bw:opc>, CpuAVX, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } -vpextr<bw>, 0x6614 | <bw:opc>, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, <bw:elem>|Unspecified|BaseIndex } -vphaddd, 0x6602, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vphaddsw, 0x6603, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vphaddw, 0x6601, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vphminposuw, 0x6641, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM } -vphsubd, 0x6606, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vphsubsw, 0x6607, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vphsubw, 0x6605, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpinsrb, 0x6620, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } -vpinsrb, 0x6620, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM } -vpinsr<dq>, 0x6622, CpuAVX|<dq:cpu64>, Modrm|Vex|Space0F3A|VexVVVV|<dq:vexw64>|NoSuf, { Imm8, <dq:gpr>|Unspecified|BaseIndex, RegXMM, RegXMM } -vpinsrw, 0x66c4, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_sSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } -vpinsrw, 0x66c4, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmaddubsw, 0x6604, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmaddwd, 0x66f5, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmaxsb, 0x663c, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmaxsd, 0x663d, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmaxsw, 0x66ee, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmaxub, 0x66de, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmaxud, 0x663f, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmaxuw, 0x663e, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpminsb, 0x6638, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpminsd, 0x6639, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpminsw, 0x66ea, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpminub, 0x66da, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpminud, 0x663b, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpminuw, 0x663a, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmovmskb, 0x66d7, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { RegXMM|RegYMM, Reg32|Reg64 } -vpmovsxbd, 0x6621, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovsxbq, 0x6622, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovsxbw, 0x6620, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovsxdq, 0x6625, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovsxwd, 0x6623, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovsxwq, 0x6624, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovzxbd, 0x6631, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovzxbq, 0x6632, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovzxbw, 0x6630, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovzxdq, 0x6635, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovzxwd, 0x6633, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmovzxwq, 0x6634, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } -vpmuldq, 0x6628, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmulhrsw, 0x660b, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmulhuw, 0x66e4, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmulhw, 0x66e5, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmulld, 0x6640, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmullw, 0x66d5, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpmuludq, 0x66f4, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpor, 0x66eb, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsadbw, 0x66f6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|C|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpshufb, 0x6600, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpshufd, 0x6670, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpshufhw, 0xf370, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpshuflw, 0xf270, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpsign<bw>, 0x6608 | <bw:opc>, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsignd, 0x660a, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsll<dq>, 0x6672 | <dq:opc>/6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsll<dq>, 0x66f2 | <dq:opc>, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpslldq, 0x6673/7, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsllw, 0x6671/6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsllw, 0x66f1, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrad, 0x6672/4, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrad, 0x66e2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsraw, 0x6671/4, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsraw, 0x66e1, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrl<dq>, 0x6672 | <dq:opc>/2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrl<dq>, 0x66d2 | <dq:opc>, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrldq, 0x6673/3, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrlw, 0x6671/2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrlw, 0x66d1, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsub<bw>, 0x66f8 | <bw:opc>, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsub<dq>, 0x66fa | <dq:opc>, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsubs<bw>, 0x66e8 | <bw:opc>, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsubus<bw>, 0x66d8 | <bw:opc>, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vptest, 0x6617, CpuAVX, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpunpckhbw, 0x6668, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpunpckhdq, 0x666a, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpunpckhqdq, 0x666d, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpunpckhwd, 0x6669, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpunpcklbw, 0x6660, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpunpckldq, 0x6662, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpunpcklqdq, 0x666c, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpunpcklwd, 0x6661, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpxor, 0x66ef, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vrcpps, 0x53, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vrcpss, 0xf353, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vroundp<sd>, 0x6608 | <sd:opc>, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vrounds<sd>, 0x660a | <sd:opc>, CpuAVX, Modrm|VexLIG|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vrsqrtps, 0x52, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vrsqrtss, 0xf352, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vshufp<sd>, 0x<sd:ppfx>c6, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vsqrtp<sd>, 0x<sd:ppfx>51, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vsqrts<sd>, 0x<sd:spfx>51, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vstmxcsr, 0xae/3, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex } -vsubp<sd>, 0x<sd:ppfx>5c, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vsubs<sd>, 0x<sd:spfx>5c, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vtestp<sd>, 0x660e | <sd:opc>, CpuAVX, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vucomis<sd>, 0x<sd:ppfx>2e, CpuAVX, Modrm|VexLIG|Space0F|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM } -vunpckhp<sd>, 0x<sd:ppfx>15, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vunpcklp<sd>, 0x<sd:ppfx>14, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vxorp<sd>, 0x<sd:ppfx>57, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vzeroall, 0x77, CpuAVX, Vex=2|Space0F|VexWIG|NoSuf, {} -vzeroupper, 0x77, CpuAVX, Vex|Space0F|VexWIG|NoSuf, {} +vmovd, 0x666e, AVX, D|Modrm|Vex=1|Space0F|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } +vmovd, 0x667e, AVX|x64, D|RegMem|Vex=1|Space0F|VexW=2|NoSuf|Size64, { RegXMM, Reg64 } +vmovddup, 0xf212, AVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vmovddup, 0xf212, AVX, Modrm|Vex=2|Space0F|VexWIG|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM } +vmovdqa, 0x666f, AVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vmovdqu, 0xf36f, AVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vmovhlps, 0x12, AVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } +vmovhp<sd>, 0x<sd:ppfx>16, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vmovhp<sd>, 0x<sd:ppfx>17, AVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } +vmovlhps, 0x16, AVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } +vmovlp<sd>, 0x<sd:ppfx>12, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vmovlp<sd>, 0x<sd:ppfx>13, AVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } +vmovmskp<sd>, 0x<sd:ppfx>50, AVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { RegXMM|RegYMM, Reg32|Reg64 } +vmovntdq, 0x66e7, AVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } +vmovntdqa, 0x662a, AVX|AVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } +vmovntp<sd>, 0x<sd:ppfx>2b, AVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } +vmovq, 0xf37e, AVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vmovq, 0x66d6, AVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } +vmovq, 0x666e, AVX|x64, D|Modrm|Vex=1|Space0F|VexW=2|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } +vmovs<sd>, 0x<sd:spfx>10, AVX, D|Modrm|VexLIG|Space0F|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex, RegXMM } +vmovs<sd>, 0x<sd:spfx>10, AVX, D|Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } +vmovshdup, 0xf316, AVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vmovsldup, 0xf312, AVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vmovup<sd>, 0x<sd:ppfx>10, AVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vmpsadbw, 0x6642, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vmulp<sd>, 0x<sd:ppfx>59, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vmuls<sd>, 0x<sd:spfx>59, AVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vorp<sd>, 0x<sd:ppfx>56, AVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpabs<bw>, 0x661c | <bw:opc>, AVX|AVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpabsd, 0x661e, AVX|AVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpackssdw, 0x666b, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpacksswb, 0x6663, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpackusdw, 0x662b, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpackuswb, 0x6667, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpadds<bw>, 0x66ec | <bw:opc>, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpadd<bw>, 0x66fc | <bw:opc>, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpaddd, 0x66fe, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpaddq, 0x66d4, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpaddus<bw>, 0x66dc | <bw:opc>, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpalignr, 0x660f, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpand, 0x66db, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpandn, 0x66df, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpavg<bw>, 0x66e0 | (3 * <bw:opc>), AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpblendvb, 0x664c, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|VexSources=2|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpblendw, 0x660e, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmpeq<bw>, 0x6674 | <bw:opc>, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmpeqd, 0x6676, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmpeqq, 0x6629, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmpestri, 0x6661, AVX|No64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } +vpcmpestri, 0x6661, AVX|x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpcmpestrm, 0x6660, AVX|No64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } +vpcmpestrm, 0x6660, AVX|x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpcmpgt<bw>, 0x6664 | <bw:opc>, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmpgtd, 0x6666, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmpgtq, 0x6637, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmpistri, 0x6663, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } +vpcmpistrm, 0x6662, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } +vperm2f128, 0x6606, AVX, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpermilp<sd>, 0x660c | <sd:opc>, AVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpermilp<sd>, 0x6604 | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexW0|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpextr<dq>, 0x6616, AVX|<dq:cpu64>, Modrm|Vex|Space0F3A|<dq:vexw64>|NoSuf, { Imm8, RegXMM, <dq:gpr>|Unspecified|BaseIndex } +vpextrw, 0x66c5, AVX, Load|Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { Imm8, RegXMM, Reg32|Reg64 } +vpextr<bw>, 0x6614 | <bw:opc>, AVX, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } +vpextr<bw>, 0x6614 | <bw:opc>, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, <bw:elem>|Unspecified|BaseIndex } +vphaddd, 0x6602, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vphaddsw, 0x6603, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vphaddw, 0x6601, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vphminposuw, 0x6641, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM } +vphsubd, 0x6606, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vphsubsw, 0x6607, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vphsubw, 0x6605, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpinsrb, 0x6620, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } +vpinsrb, 0x6620, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM } +vpinsr<dq>, 0x6622, AVX|<dq:cpu64>, Modrm|Vex|Space0F3A|VexVVVV|<dq:vexw64>|NoSuf, { Imm8, <dq:gpr>|Unspecified|BaseIndex, RegXMM, RegXMM } +vpinsrw, 0x66c4, AVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_sSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } +vpinsrw, 0x66c4, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmaddubsw, 0x6604, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmaddwd, 0x66f5, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmaxsb, 0x663c, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmaxsd, 0x663d, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmaxsw, 0x66ee, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmaxub, 0x66de, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmaxud, 0x663f, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmaxuw, 0x663e, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpminsb, 0x6638, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpminsd, 0x6639, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpminsw, 0x66ea, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpminub, 0x66da, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpminud, 0x663b, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpminuw, 0x663a, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmovmskb, 0x66d7, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { RegXMM|RegYMM, Reg32|Reg64 } +vpmovsxbd, 0x6621, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovsxbq, 0x6622, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovsxbw, 0x6620, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovsxdq, 0x6625, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovsxwd, 0x6623, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovsxwq, 0x6624, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovzxbd, 0x6631, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovzxbq, 0x6632, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovzxbw, 0x6630, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovzxdq, 0x6635, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovzxwd, 0x6633, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmovzxwq, 0x6634, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } +vpmuldq, 0x6628, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmulhrsw, 0x660b, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmulhuw, 0x66e4, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmulhw, 0x66e5, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmulld, 0x6640, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmullw, 0x66d5, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmuludq, 0x66f4, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpor, 0x66eb, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsadbw, 0x66f6, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|C|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpshufb, 0x6600, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpshufd, 0x6670, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpshufhw, 0xf370, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpshuflw, 0xf270, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpsign<bw>, 0x6608 | <bw:opc>, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsignd, 0x660a, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsll<dq>, 0x6672 | <dq:opc>/6, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsll<dq>, 0x66f2 | <dq:opc>, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpslldq, 0x6673/7, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsllw, 0x6671/6, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsllw, 0x66f1, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrad, 0x6672/4, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrad, 0x66e2, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsraw, 0x6671/4, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsraw, 0x66e1, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrl<dq>, 0x6672 | <dq:opc>/2, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrl<dq>, 0x66d2 | <dq:opc>, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrldq, 0x6673/3, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrlw, 0x6671/2, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrlw, 0x66d1, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsub<bw>, 0x66f8 | <bw:opc>, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsub<dq>, 0x66fa | <dq:opc>, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsubs<bw>, 0x66e8 | <bw:opc>, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsubus<bw>, 0x66d8 | <bw:opc>, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vptest, 0x6617, AVX, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpunpckhbw, 0x6668, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpunpckhdq, 0x666a, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpunpckhqdq, 0x666d, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpunpckhwd, 0x6669, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpunpcklbw, 0x6660, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpunpckldq, 0x6662, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpunpcklqdq, 0x666c, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpunpcklwd, 0x6661, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpxor, 0x66ef, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vrcpps, 0x53, AVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vrcpss, 0xf353, AVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vroundp<sd>, 0x6608 | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vrounds<sd>, 0x660a | <sd:opc>, AVX, Modrm|VexLIG|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vrsqrtps, 0x52, AVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vrsqrtss, 0xf352, AVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vshufp<sd>, 0x<sd:ppfx>c6, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vsqrtp<sd>, 0x<sd:ppfx>51, AVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vsqrts<sd>, 0x<sd:spfx>51, AVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vstmxcsr, 0xae/3, AVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex } +vsubp<sd>, 0x<sd:ppfx>5c, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vsubs<sd>, 0x<sd:spfx>5c, AVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vtestp<sd>, 0x660e | <sd:opc>, AVX, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vucomis<sd>, 0x<sd:ppfx>2e, AVX, Modrm|VexLIG|Space0F|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM } +vunpckhp<sd>, 0x<sd:ppfx>15, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vunpcklp<sd>, 0x<sd:ppfx>14, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vxorp<sd>, 0x<sd:ppfx>57, AVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vzeroall, 0x77, AVX, Vex=2|Space0F|VexWIG|NoSuf, {} +vzeroupper, 0x77, AVX, Vex|Space0F|VexWIG|NoSuf, {} // 256bit integer AVX2 instructions. -vpmovsxbd, 0x6621, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovsxbq, 0x6622, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovsxbw, 0x6620, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovsxdq, 0x6625, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovsxwd, 0x6623, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovsxwq, 0x6624, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovzxbd, 0x6631, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovzxbq, 0x6632, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovzxbw, 0x6630, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovzxdq, 0x6635, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovzxwd, 0x6633, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } -vpmovzxwq, 0x6634, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovsxbd, 0x6621, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovsxbq, 0x6622, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovsxbw, 0x6620, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovsxdq, 0x6625, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovsxwd, 0x6623, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovsxwq, 0x6624, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovzxbd, 0x6631, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovzxbq, 0x6632, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovzxbw, 0x6630, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovzxdq, 0x6635, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovzxwd, 0x6633, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +vpmovzxwq, 0x6634, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } // New AVX2 instructions. -vbroadcasti128, 0x665A, CpuAVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } -vbroadcastsd, 0x6619, CpuAVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { RegXMM, RegYMM } -vbroadcastss, 0x6618, CpuAVX2, Modrm|Vex|Space0F38|VexW=1|NoSuf, { RegXMM, RegXMM|RegYMM } -vpblendd, 0x6602, CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpbroadcast<bw>, 0x6678 | <bw:opc>, CpuAVX2, Modrm|Vex|Space0F38|VexW0|NoSuf, { <bw:elem>|Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM } -vpbroadcast<dq>, 0x6658 | <dq:opc>, CpuAVX2, Modrm|Vex|Space0F38|VexW0|NoSuf, { <dq:elem>|Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM } -vperm2i128, 0x6646, CpuAVX2, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpermd, 0x6636, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV=1|VexW=1|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpermpd, 0x6601, CpuAVX2, Modrm|Vex=2|Space0F3A|VexW=2|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM } -vpermps, 0x6616, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV=1|VexW=1|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpermq, 0x6600, CpuAVX2, Modrm|Vex=2|Space0F3A|VexW=2|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM } -vextracti128, 0x6639, CpuAVX2, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } -vinserti128, 0x6638, CpuAVX2, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM } -vpmaskmov<dq>, 0x668e, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckRegSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } -vpmaskmov<dq>, 0x668c, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpsllv<dq>, 0x6647, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsravd, 0x6646, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=1|VexW=1|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrlv<dq>, 0x6645, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vbroadcasti128, 0x665A, AVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } +vbroadcastsd, 0x6619, AVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { RegXMM, RegYMM } +vbroadcastss, 0x6618, AVX2, Modrm|Vex|Space0F38|VexW=1|NoSuf, { RegXMM, RegXMM|RegYMM } +vpblendd, 0x6602, AVX2, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpbroadcast<bw>, 0x6678 | <bw:opc>, AVX2, Modrm|Vex|Space0F38|VexW0|NoSuf, { <bw:elem>|Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM } +vpbroadcast<dq>, 0x6658 | <dq:opc>, AVX2, Modrm|Vex|Space0F38|VexW0|NoSuf, { <dq:elem>|Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM } +vperm2i128, 0x6646, AVX2, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpermd, 0x6636, AVX2, Modrm|Vex=2|Space0F38|VexVVVV=1|VexW=1|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpermpd, 0x6601, AVX2, Modrm|Vex=2|Space0F3A|VexW=2|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM } +vpermps, 0x6616, AVX2, Modrm|Vex=2|Space0F38|VexVVVV=1|VexW=1|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpermq, 0x6600, AVX2, Modrm|Vex=2|Space0F3A|VexW=2|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM } +vextracti128, 0x6639, AVX2, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } +vinserti128, 0x6638, AVX2, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM } +vpmaskmov<dq>, 0x668e, AVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckRegSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } +vpmaskmov<dq>, 0x668c, AVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpsllv<dq>, 0x6647, AVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsravd, 0x6646, AVX2, Modrm|Vex|Space0F38|VexVVVV=1|VexW=1|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrlv<dq>, 0x6645, AVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } // AVX gather instructions -vgatherdpd, 0x6692, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } -vgatherdps, 0x6692, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } -vgatherdps, 0x6692, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } -vgatherqp<sd>, 0x6693, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|NoSuf|VecSIB128, { RegXMM, <sd:elem>|Unspecified|BaseIndex, RegXMM } -vgatherqpd, 0x6693, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } -vgatherqps, 0x6693, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } -vpgatherdd, 0x6690, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } -vpgatherdd, 0x6690, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } -vpgatherdq, 0x6690, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } -vpgatherq<dq>, 0x6691, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|NoSuf|VecSIB128, { RegXMM, <dq:elem>|Unspecified|BaseIndex, RegXMM } -vpgatherqd, 0x6691, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } -vpgatherqq, 0x6691, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } +vgatherdpd, 0x6692, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } +vgatherdps, 0x6692, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } +vgatherdps, 0x6692, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } +vgatherqp<sd>, 0x6693, AVX2, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|NoSuf|VecSIB128, { RegXMM, <sd:elem>|Unspecified|BaseIndex, RegXMM } +vgatherqpd, 0x6693, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } +vgatherqps, 0x6693, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } +vpgatherdd, 0x6690, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } +vpgatherdd, 0x6690, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } +vpgatherdq, 0x6690, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } +vpgatherq<dq>, 0x6691, AVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|NoSuf|VecSIB128, { RegXMM, <dq:elem>|Unspecified|BaseIndex, RegXMM } +vpgatherqd, 0x6691, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } +vpgatherqq, 0x6691, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } // AES + AVX -vaesdec, 0x66de, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vaesdeclast, 0x66df, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vaesenc, 0x66dc, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vaesenclast, 0x66dd, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vaesimc, 0x66db, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM } -vaeskeygenassist, 0x66df, CpuAVX|CpuAES, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } +vaesdec, 0x66de, AVX|AES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vaesdeclast, 0x66df, AVX|AES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vaesenc, 0x66dc, AVX|AES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vaesenclast, 0x66dd, AVX|AES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vaesimc, 0x66db, AVX|AES, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM } +vaeskeygenassist, 0x66df, AVX|AES, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } // PCLMUL + AVX -vpclmulqdq, 0x6644, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vpclmullqlqdq, 0x6644/0x00, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vpclmulhqlqdq, 0x6644/0x01, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vpclmullqhqdq, 0x6644/0x10, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vpclmulhqhqdq, 0x6644/0x11, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vpclmulqdq, 0x6644, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vpclmullqlqdq, 0x6644/0x00, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vpclmulhqlqdq, 0x6644/0x01, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vpclmullqhqdq, 0x6644/0x10, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vpclmulhqhqdq, 0x6644/0x11, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } // GFNI + AVX -vgf2p8affineinvqb, 0x66cf, CpuAVX|CpuGFNI, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=2|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vgf2p8affineqb, 0x66ce, CpuAVX|CpuGFNI, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=2|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vgf2p8mulb, 0x66cf, CpuAVX|CpuGFNI, Modrm|Vex|Space0F38|VexVVVV=1|VexW=1|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vgf2p8affineinvqb, 0x66cf, AVX|GFNI, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=2|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vgf2p8affineqb, 0x66ce, AVX|GFNI, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=2|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vgf2p8mulb, 0x66cf, AVX|GFNI, Modrm|Vex|Space0F38|VexVVVV=1|VexW=1|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } // FSGSBASE, RDRND and F16C -rdfsbase, 0xf30fae/0, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } -rdgsbase, 0xf30fae/1, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } -rdrand, 0xfc7/6, CpuRdRnd, Modrm|NoSuf, { Reg16|Reg32|Reg64 } -wrfsbase, 0xf30fae/2, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } -wrgsbase, 0xf30fae/3, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } -vcvtph2ps, 0x6613, CpuF16C, Modrm|Vex|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vcvtph2ps, 0x6613, CpuF16C, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } -vcvtps2ph, 0x661d, CpuF16C, Modrm|Vex|Space0F3A|VexW0|NoSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex|RegXMM } -vcvtps2ph, 0x661d, CpuF16C, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } +rdfsbase, 0xf30fae/0, FSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } +rdgsbase, 0xf30fae/1, FSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } +rdrand, 0xfc7/6, RdRnd, Modrm|NoSuf, { Reg16|Reg32|Reg64 } +wrfsbase, 0xf30fae/2, FSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } +wrgsbase, 0xf30fae/3, FSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } +vcvtph2ps, 0x6613, F16C, Modrm|Vex|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vcvtph2ps, 0x6613, F16C, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +vcvtps2ph, 0x661d, F16C, Modrm|Vex|Space0F3A|VexW0|NoSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex|RegXMM } +vcvtps2ph, 0x661d, F16C, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } // FMA instructions <fma:opc, 132:10, 213:20, 231:30> -vfmadd<fma>p<sd>, 0x6688 | 0x<fma:opc>, CpuFMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmadd<fma>s<sd>, 0x6689 | 0x<fma:opc>, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV|<sd:vexw>|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vfmaddsub<fma>p<sd>, 0x6686 | 0x<fma:opc>, CpuFMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsub<fma>p<sd>, 0x668a | 0x<fma:opc>, CpuFMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsub<fma>s<sd>, 0x668b | 0x<fma:opc>, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV|<sd:vexw>|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vfmsubadd<fma>p<sd>, 0x6687 | 0x<fma:opc>, CpuFMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmadd<fma>p<sd>, 0x668c | 0x<fma:opc>, CpuFMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmadd<fma>s<sd>, 0x668d | 0x<fma:opc>, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV|<sd:vexw>|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vfnmsub<fma>p<sd>, 0x668e | 0x<fma:opc>, CpuFMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmsub<fma>s<sd>, 0x668f | 0x<fma:opc>, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV|<sd:vexw>|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vfmadd<fma>p<sd>, 0x6688 | 0x<fma:opc>, FMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmadd<fma>s<sd>, 0x6689 | 0x<fma:opc>, FMA, Modrm|VexLIG|Space0F38|VexVVVV|<sd:vexw>|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vfmaddsub<fma>p<sd>, 0x6686 | 0x<fma:opc>, FMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsub<fma>p<sd>, 0x668a | 0x<fma:opc>, FMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsub<fma>s<sd>, 0x668b | 0x<fma:opc>, FMA, Modrm|VexLIG|Space0F38|VexVVVV|<sd:vexw>|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vfmsubadd<fma>p<sd>, 0x6687 | 0x<fma:opc>, FMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmadd<fma>p<sd>, 0x668c | 0x<fma:opc>, FMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmadd<fma>s<sd>, 0x668d | 0x<fma:opc>, FMA, Modrm|VexLIG|Space0F38|VexVVVV|<sd:vexw>|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vfnmsub<fma>p<sd>, 0x668e | 0x<fma:opc>, FMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmsub<fma>s<sd>, 0x668f | 0x<fma:opc>, FMA, Modrm|VexLIG|Space0F38|VexVVVV|<sd:vexw>|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } // HLE prefixes -xacquire, 0xf2, CpuHLE, NoSuf|IsPrefix, {} -xrelease, 0xf3, CpuHLE, NoSuf|IsPrefix, {} +xacquire, 0xf2, HLE, NoSuf|IsPrefix, {} +xrelease, 0xf3, HLE, NoSuf|IsPrefix, {} // RTM instructions -xabort, 0xc6f8, CpuRTM, NoSuf, { Imm8 } -xbegin, 0xc7f8, CpuRTM, JumpDword|NoSuf, { Disp16|Disp32 } -xend, 0xf01d5, CpuRTM, NoSuf, {} -xtest, 0xf01d6, CpuHLE|CpuRTM, NoSuf, {} +xabort, 0xc6f8, RTM, NoSuf, { Imm8 } +xbegin, 0xc7f8, RTM, JumpDword|NoSuf, { Disp16|Disp32 } +xend, 0xf01d5, RTM, NoSuf, {} +xtest, 0xf01d6, HLE|RTM, NoSuf, {} // BMI2 instructions. -bzhi, 0xf5, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -mulx, 0xf2f6, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } -pdep, 0xf2f5, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } -pext, 0xf3f5, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } -rorx, 0xf2f0, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F3A|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf, { Imm8, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -sarx, 0xf3f7, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -shlx, 0x66f7, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -shrx, 0xf2f7, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +bzhi, 0xf5, BMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +mulx, 0xf2f6, BMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +pdep, 0xf2f5, BMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +pext, 0xf3f5, BMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +rorx, 0xf2f0, BMI2, Modrm|CheckRegSize|Vex128|Space0F3A|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf, { Imm8, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +sarx, 0xf3f7, BMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +shlx, 0x66f7, BMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +shrx, 0xf2f7, BMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } // FMA4 instructions -vfmaddp<sd>, 0x6668 | <sd:opc>, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmadds<sd>, 0x666a | <sd:opc>, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfmaddsubp<sd>, 0x665c | <sd:opc>, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubaddp<sd>, 0x665e | <sd:opc>, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubp<sd>, 0x666c | <sd:opc>, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubs<sd>, 0x666e | <sd:opc>, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmaddp<sd>, 0x6678 | <sd:opc>, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmadds<sd>, 0x667a | <sd:opc>, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmsubp<sd>, 0x667c | <sd:opc>, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmsubs<sd>, 0x667e | <sd:opc>, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddp<sd>, 0x6668 | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmadds<sd>, 0x666a | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddsubp<sd>, 0x665c | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsubaddp<sd>, 0x665e | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsubp<sd>, 0x666c | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsubs<sd>, 0x666e | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmaddp<sd>, 0x6678 | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmadds<sd>, 0x667a | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmsubp<sd>, 0x667c | <sd:opc>, FMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmsubs<sd>, 0x667e | <sd:opc>, FMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } // XOP instructions @@ -1830,41 +1845,41 @@ vfnmsubs<sd>, 0x667e | <sd:opc>, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1 <irel:imm, lt:0, le:1, gt:2, ge:3, eq:4, neq:5, false:6, true:7> <sign:opc, :00, u:20> -vfrczp<sd>, 0x80 | <sd:opc>, CpuXOP, Modrm|SpaceXOP09|VexW0|CheckRegSize|NoSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vfrczs<sd>, 0x82 | <sd:opc>, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { <sd:elem>|RegXMM|Unspecified|BaseIndex, RegXMM } -vpcmov, 0xa2, CpuXOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|CheckRegSize|NoSuf|Vex, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpcom<sign><xop>, 0xcc | 0x<sign:opc> | <xop:opc>, CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpcom<irel><sign><xop>, 0xcc | 0x<sign:opc> | <xop:opc>/<irel:imm>, CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpermil2p<sd>, 0x6648 | <sd:opc>, CpuXOP, Modrm|Space0F3A|VexVVVV|VexW0|Vex|VexSources=2|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpermil2p<sd>, 0x6648 | <sd:opc>, CpuXOP, Modrm|Space0F3A|VexVVVV|VexW1|Vex|VexSources=2|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vphaddb<dq>, 0xc2 | <dq:opc>, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphaddbw, 0xc1, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphadddq, 0xcb, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphaddub<dq>, 0xd2 | <dq:opc>, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphaddubw, 0xd1, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphaddudq, 0xdb, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphadduw<dq>, 0xd6 | <dq:opc>, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphaddw<dq>, 0xc6 | <dq:opc>, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphsubbw, 0xe1, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphsubdq, 0xe3, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphsubwd, 0xe2, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vpmacsdd, 0x9e, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsdqh, 0x9f, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsdql, 0x97, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssdd, 0x8e, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssdqh, 0x8f, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssdql, 0x87, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsswd, 0x86, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssww, 0x85, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacswd, 0x96, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsww, 0x95, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmadcsswd, 0xa6, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmadcswd, 0xb6, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpperm, 0xa3, CpuXOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vprot<xop>, 0x90 | <xop:opc>, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } -vprot<xop>, 0xc0 | <xop:opc>, CpuXOP, Modrm|Vex128|SpaceXOP08|VexW0|VexSources=1|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -vpsha<xop>, 0x98 | <xop:opc>, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } -vpshl<xop>, 0x94 | <xop:opc>, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } +vfrczp<sd>, 0x80 | <sd:opc>, XOP, Modrm|SpaceXOP09|VexW0|CheckRegSize|NoSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vfrczs<sd>, 0x82 | <sd:opc>, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { <sd:elem>|RegXMM|Unspecified|BaseIndex, RegXMM } +vpcmov, 0xa2, XOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|CheckRegSize|NoSuf|Vex, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcom<sign><xop>, 0xcc | 0x<sign:opc> | <xop:opc>, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpcom<irel><sign><xop>, 0xcc | 0x<sign:opc> | <xop:opc>/<irel:imm>, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpermil2p<sd>, 0x6648 | <sd:opc>, XOP, Modrm|Space0F3A|VexVVVV|VexW0|Vex|VexSources=2|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpermil2p<sd>, 0x6648 | <sd:opc>, XOP, Modrm|Space0F3A|VexVVVV|VexW1|Vex|VexSources=2|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vphaddb<dq>, 0xc2 | <dq:opc>, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphaddbw, 0xc1, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphadddq, 0xcb, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphaddub<dq>, 0xd2 | <dq:opc>, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphaddubw, 0xd1, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphaddudq, 0xdb, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphadduw<dq>, 0xd6 | <dq:opc>, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphaddw<dq>, 0xc6 | <dq:opc>, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphsubbw, 0xe1, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphsubdq, 0xe3, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphsubwd, 0xe2, XOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vpmacsdd, 0x9e, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsdqh, 0x9f, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsdql, 0x97, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdd, 0x8e, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdqh, 0x8f, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdql, 0x87, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsswd, 0x86, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssww, 0x85, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacswd, 0x96, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsww, 0x95, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmadcsswd, 0xa6, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmadcswd, 0xb6, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpperm, 0xa3, XOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vprot<xop>, 0x90 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } +vprot<xop>, 0xc0 | <xop:opc>, XOP, Modrm|Vex128|SpaceXOP08|VexW0|VexSources=1|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +vpsha<xop>, 0x98 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } +vpshl<xop>, 0x94 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } <xop> <irel> @@ -1872,160 +1887,160 @@ vpshl<xop>, 0x94 | <xop:opc>, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources // LWP instructions -llwpcb, 0x12/0, CpuLWP, Modrm|SpaceXOP09|NoSuf|Vex, { Reg32|Reg64 } -slwpcb, 0x12/1, CpuLWP, Modrm|SpaceXOP09|NoSuf|Vex, { Reg32|Reg64 } -lwpval, 0x12/1, CpuLWP, Modrm|SpaceXOP0A|NoSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseIndex, Reg32|Reg64 } -lwpins, 0x12/0, CpuLWP, Modrm|SpaceXOP0A|NoSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseIndex, Reg32|Reg64 } +llwpcb, 0x12/0, LWP, Modrm|SpaceXOP09|NoSuf|Vex, { Reg32|Reg64 } +slwpcb, 0x12/1, LWP, Modrm|SpaceXOP09|NoSuf|Vex, { Reg32|Reg64 } +lwpval, 0x12/1, LWP, Modrm|SpaceXOP0A|NoSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseIndex, Reg32|Reg64 } +lwpins, 0x12/0, LWP, Modrm|SpaceXOP0A|NoSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseIndex, Reg32|Reg64 } // BMI instructions -andn, 0xf2, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } -bextr, 0xf7, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blsi, 0xf3/3, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blsmsk, 0xf3/2, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blsr, 0xf3/1, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -tzcnt, 0xf30fbc, CpuBMI, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +andn, 0xf2, BMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +bextr, 0xf7, BMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blsi, 0xf3/3, BMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blsmsk, 0xf3/2, BMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blsr, 0xf3/1, BMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +tzcnt, 0xf30fbc, BMI, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // TBM instructions -bextr, 0x10, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP0A|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf, { Imm32|Imm32S, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blcfill, 0x01/1, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blci, 0x02/6, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blcic, 0x01/5, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blcmsk, 0x02/1, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blcs, 0x01/3, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blsfill, 0x01/2, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -blsic, 0x01/6, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -t1mskc, 0x01/7, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } -tzmsk, 0x01/4, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +bextr, 0x10, TBM, Modrm|CheckRegSize|Vex128|SpaceXOP0A|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf, { Imm32|Imm32S, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blcfill, 0x01/1, TBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blci, 0x02/6, TBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blcic, 0x01/5, TBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blcmsk, 0x02/1, TBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blcs, 0x01/3, TBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blsfill, 0x01/2, TBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +blsic, 0x01/6, TBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +t1mskc, 0x01/7, TBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +tzmsk, 0x01/4, TBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } // AMD 3DNow! instructions. -prefetch, 0xf0d/0, Cpu3dnow|CpuPRFCHW, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -prefetchw, 0xf0d/1, Cpu3dnow|CpuPRFCHW, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -femms, 0xf0e, Cpu3dnow, NoSuf, {} -pavgusb, 0xf0f/0xbf, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pf2id, 0xf0f/0x1d, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pf2iw, 0xf0f/0x1c, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfacc, 0xf0f/0xae, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfadd, 0xf0f/0x9e, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfcmpeq, 0xf0f/0xb0, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfcmpge, 0xf0f/0x90, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfcmpgt, 0xf0f/0xa0, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfmax, 0xf0f/0xa4, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfmin, 0xf0f/0x94, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfmul, 0xf0f/0xb4, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfnacc, 0xf0f/0x8a, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfpnacc, 0xf0f/0x8e, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfrcp, 0xf0f/0x96, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfrcpit1, 0xf0f/0xa6, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfrcpit2, 0xf0f/0xb6, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfrsqit1, 0xf0f/0xa7, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfrsqrt, 0xf0f/0x97, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfsub, 0xf0f/0x9a, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pfsubr, 0xf0f/0xaa, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pi2fd, 0xf0f/0x0d, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pi2fw, 0xf0f/0x0c, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pmulhrw, 0xf0f/0xb7, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pswapd, 0xf0f/0xbb, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +prefetch, 0xf0d/0, 3dnow|PRFCHW, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +prefetchw, 0xf0d/1, 3dnow|PRFCHW, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +femms, 0xf0e, 3dnow, NoSuf, {} +pavgusb, 0xf0f/0xbf, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pf2id, 0xf0f/0x1d, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pf2iw, 0xf0f/0x1c, 3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfacc, 0xf0f/0xae, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfadd, 0xf0f/0x9e, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfcmpeq, 0xf0f/0xb0, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfcmpge, 0xf0f/0x90, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfcmpgt, 0xf0f/0xa0, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfmax, 0xf0f/0xa4, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfmin, 0xf0f/0x94, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfmul, 0xf0f/0xb4, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfnacc, 0xf0f/0x8a, 3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfpnacc, 0xf0f/0x8e, 3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfrcp, 0xf0f/0x96, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfrcpit1, 0xf0f/0xa6, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfrcpit2, 0xf0f/0xb6, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfrsqit1, 0xf0f/0xa7, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfrsqrt, 0xf0f/0x97, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfsub, 0xf0f/0x9a, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pfsubr, 0xf0f/0xaa, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pi2fd, 0xf0f/0x0d, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pi2fw, 0xf0f/0x0c, 3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pmulhrw, 0xf0f/0xb7, 3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pswapd, 0xf0f/0xbb, 3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } // AMD extensions. -syscall, 0xf05, CpuSYSCALL, NoSuf, {} -sysret, 0xf07, CpuSYSCALL, No_bSuf|No_wSuf|No_sSuf, {} -swapgs, 0xf01f8, Cpu64, NoSuf, {} -rdtscp, 0xf01f9, CpuRdtscp, NoSuf, {} +syscall, 0xf05, SYSCALL, NoSuf, {} +sysret, 0xf07, SYSCALL, No_bSuf|No_wSuf|No_sSuf, {} +swapgs, 0xf01f8, x64, NoSuf, {} +rdtscp, 0xf01f9, Rdtscp, NoSuf, {} // AMD Pacifica additions. -clgi, 0xf01dd, CpuSVME, NoSuf, {} -invlpga, 0xf01df, CpuSVME, NoSuf, {} -invlpga, 0xf01df, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword } -skinit, 0xf01de, CpuSVME, NoSuf, {} -skinit, 0xf01de, CpuSVME, IgnoreSize|NoSuf, { Acc|Dword } -stgi, 0xf01dc, CpuSVME, NoSuf, {} -vmgexit, 0xf30f01d9, CpuSEV_ES, NoSuf, {} -vmload, 0xf01da, CpuSVME, NoSuf, {} -vmload, 0xf01da, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } -vmmcall, 0xf01d9, CpuSVME, NoSuf, {} -vmrun, 0xf01d8, CpuSVME, NoSuf, {} -vmrun, 0xf01d8, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } -vmsave, 0xf01db, CpuSVME, NoSuf, {} -vmsave, 0xf01db, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } +clgi, 0xf01dd, SVME, NoSuf, {} +invlpga, 0xf01df, SVME, NoSuf, {} +invlpga, 0xf01df, SVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword } +skinit, 0xf01de, SVME, NoSuf, {} +skinit, 0xf01de, SVME, IgnoreSize|NoSuf, { Acc|Dword } +stgi, 0xf01dc, SVME, NoSuf, {} +vmgexit, 0xf30f01d9, SEV_ES, NoSuf, {} +vmload, 0xf01da, SVME, NoSuf, {} +vmload, 0xf01da, SVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } +vmmcall, 0xf01d9, SVME, NoSuf, {} +vmrun, 0xf01d8, SVME, NoSuf, {} +vmrun, 0xf01d8, SVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } +vmsave, 0xf01db, SVME, NoSuf, {} +vmsave, 0xf01db, SVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } // SSE4a instructions -movntsd, 0xf20f2b, CpuSSE4a, Modrm|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } -movntss, 0xf30f2b, CpuSSE4a, Modrm|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } -extrq, 0x660f78/0, CpuSSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM } -extrq, 0x660f79, CpuSSE4a, Modrm|NoSuf, { RegXMM, RegXMM } -insertq, 0xf20f79, CpuSSE4a, Modrm|NoSuf, { RegXMM, RegXMM } -insertq, 0xf20f78, CpuSSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM, RegXMM } +movntsd, 0xf20f2b, SSE4a, Modrm|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } +movntss, 0xf30f2b, SSE4a, Modrm|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } +extrq, 0x660f78/0, SSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM } +extrq, 0x660f79, SSE4a, Modrm|NoSuf, { RegXMM, RegXMM } +insertq, 0xf20f79, SSE4a, Modrm|NoSuf, { RegXMM, RegXMM } +insertq, 0xf20f78, SSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM, RegXMM } // LZCNT instruction -lzcnt, 0xf30fbd, CpuLZCNT, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lzcnt, 0xf30fbd, LZCNT, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // POPCNT instruction -popcnt, 0xf30fb8, CpuPOPCNT, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +popcnt, 0xf30fb8, POPCNT, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // VIA PadLock extensions. -xstore-rng, 0xfa7c0, CpuPadLock, NoSuf|RepPrefixOk, {} -xcrypt-ecb, 0xf30fa7c8, CpuPadLock, NoSuf|RepPrefixOk, {} -xcrypt-cbc, 0xf30fa7d0, CpuPadLock, NoSuf|RepPrefixOk, {} -xcrypt-ctr, 0xf30fa7d8, CpuPadLock, NoSuf|RepPrefixOk, {} -xcrypt-cfb, 0xf30fa7e0, CpuPadLock, NoSuf|RepPrefixOk, {} -xcrypt-ofb, 0xf30fa7e8, CpuPadLock, NoSuf|RepPrefixOk, {} -montmul, 0xf30fa6c0, CpuPadLock, NoSuf|RepPrefixOk, {} -xsha1, 0xf30fa6c8, CpuPadLock, NoSuf|RepPrefixOk, {} -xsha256, 0xf30fa6d0, CpuPadLock, NoSuf|RepPrefixOk, {} +xstore-rng, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {} +xcrypt-ecb, 0xf30fa7c8, PadLock, NoSuf|RepPrefixOk, {} +xcrypt-cbc, 0xf30fa7d0, PadLock, NoSuf|RepPrefixOk, {} +xcrypt-ctr, 0xf30fa7d8, PadLock, NoSuf|RepPrefixOk, {} +xcrypt-cfb, 0xf30fa7e0, PadLock, NoSuf|RepPrefixOk, {} +xcrypt-ofb, 0xf30fa7e8, PadLock, NoSuf|RepPrefixOk, {} +montmul, 0xf30fa6c0, PadLock, NoSuf|RepPrefixOk, {} +xsha1, 0xf30fa6c8, PadLock, NoSuf|RepPrefixOk, {} +xsha256, 0xf30fa6d0, PadLock, NoSuf|RepPrefixOk, {} // Aliases without hyphens. -xstorerng, 0xfa7c0, CpuPadLock, NoSuf|RepPrefixOk, {} -xcryptecb, 0xf30fa7c8, CpuPadLock, NoSuf|RepPrefixOk, {} -xcryptcbc, 0xf30fa7d0, CpuPadLock, NoSuf|RepPrefixOk, {} -xcryptctr, 0xf30fa7d8, CpuPadLock, NoSuf|RepPrefixOk, {} -xcryptcfb, 0xf30fa7e0, CpuPadLock, NoSuf|RepPrefixOk, {} -xcryptofb, 0xf30fa7e8, CpuPadLock, NoSuf|RepPrefixOk, {} +xstorerng, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {} +xcryptecb, 0xf30fa7c8, PadLock, NoSuf|RepPrefixOk, {} +xcryptcbc, 0xf30fa7d0, PadLock, NoSuf|RepPrefixOk, {} +xcryptctr, 0xf30fa7d8, PadLock, NoSuf|RepPrefixOk, {} +xcryptcfb, 0xf30fa7e0, PadLock, NoSuf|RepPrefixOk, {} +xcryptofb, 0xf30fa7e8, PadLock, NoSuf|RepPrefixOk, {} // Alias for xstore-rng. -xstore, 0xfa7c0, CpuPadLock, NoSuf|RepPrefixOk, {} +xstore, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {} // Multy-precision Add Carry, rdseed instructions. -adcx, 0x660f38f6, CpuADX, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } -adox, 0xf30f38f6, CpuADX, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } -rdseed, 0xfc7/7, CpuRdSeed, Modrm|NoSuf, { Reg16|Reg32|Reg64 } +adcx, 0x660f38f6, ADX, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +adox, 0xf30f38f6, ADX, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +rdseed, 0xfc7/7, RdSeed, Modrm|NoSuf, { Reg16|Reg32|Reg64 } // SMAP instructions. -clac, 0xf01ca, CpuSMAP, NoSuf, {} -stac, 0xf01cb, CpuSMAP, NoSuf, {} +clac, 0xf01ca, SMAP, NoSuf, {} +stac, 0xf01cb, SMAP, NoSuf, {} // BND prefix -bnd, 0xf2, CpuMPX, NoSuf|IsPrefix, {} +bnd, 0xf2, MPX, NoSuf|IsPrefix, {} // MPX instructions. -bndmk, 0xf30f1b, CpuMPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } -bndmov, 0x660f1a, CpuMPX, D|Modrm|NoSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND } -bndcl, 0xf30f1a, CpuMPX|CpuNo64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } -bndcl, 0xf30f1a, CpuMPX|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } -bndcu, 0xf20f1a, CpuMPX|CpuNo64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } -bndcu, 0xf20f1a, CpuMPX|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } -bndcn, 0xf20f1b, CpuMPX|CpuNo64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } -bndcn, 0xf20f1b, CpuMPX|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } -bndstx, 0x0f1b, CpuMPX, Modrm|Anysize|IgnoreSize|NoSuf, { RegBND, BaseIndex } -bndldx, 0x0f1a, CpuMPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } +bndmk, 0xf30f1b, MPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } +bndmov, 0x660f1a, MPX, D|Modrm|NoSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND } +bndcl, 0xf30f1a, MPX|No64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } +bndcl, 0xf30f1a, MPX|x64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } +bndcu, 0xf20f1a, MPX|No64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } +bndcu, 0xf20f1a, MPX|x64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } +bndcn, 0xf20f1b, MPX|No64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } +bndcn, 0xf20f1b, MPX|x64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } +bndstx, 0x0f1b, MPX, Modrm|Anysize|IgnoreSize|NoSuf, { RegBND, BaseIndex } +bndldx, 0x0f1a, MPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } // SHA instructions. -sha1rnds4, 0xf3acc, CpuSHA, Modrm|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -sha1nexte, 0xf38c8, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -sha1msg1, 0xf38c9, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -sha1msg2, 0xf38ca, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -sha256rnds2, 0xf38cb, CpuSHA, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -sha256rnds2, 0xf38cb, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -sha256msg1, 0xf38cc, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -sha256msg2, 0xf38cd, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha1rnds4, 0xf3acc, SHA, Modrm|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +sha1nexte, 0xf38c8, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha1msg1, 0xf38c9, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha1msg2, 0xf38ca, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha256rnds2, 0xf38cb, SHA, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } +sha256rnds2, 0xf38cb, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha256msg1, 0xf38cc, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha256msg2, 0xf38cd, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } // VPCLMULQDQ instructions -vpclmulqdq, 0x6644, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpclmullqlqdq, 0x6644/0x00, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpclmulhqlqdq, 0x6644/0x01, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpclmullqhqdq, 0x6644/0x10, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpclmulhqhqdq, 0x6644/0x11, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpclmulqdq, 0x6644, VPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpclmullqlqdq, 0x6644/0x00, VPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpclmulhqlqdq, 0x6644/0x01, VPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpclmullqhqdq, 0x6644/0x10, VPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpclmulhqhqdq, 0x6644/0x11, VPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } // VPCLMULQDQ instructions end @@ -2035,17 +2050,17 @@ vpclmulhqhqdq, 0x6644/0x11, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV= #define MaskingMorZ Masking=DYNAMIC_MASKING <sdh:cpu:cpudq:ppfx:spfx:pfx:spc1:spc2:opc:vexw:elem, + - s:CpuAVX512F:CpuAVX512DQ::f3:66:Space0F:Space0F38:0:VexW0:Dword, + - d:CpuAVX512F:CpuAVX512DQ:66:f2:66:Space0F:Space0F38:1:VexW1:Qword, + - h:CpuAVX512_FP16:CpuAVX512_FP16::f3::EVexMap5:EVexMap6:0:VexW0:Word> + s:AVX512F:AVX512DQ::f3:66:Space0F:Space0F38:0:VexW0:Dword, + + d:AVX512F:AVX512DQ:66:f2:66:Space0F:Space0F38:1:VexW1:Qword, + + h:AVX512_FP16:AVX512_FP16::f3::EVexMap5:EVexMap6:0:VexW0:Word> // <Exy> is used for EVEX instructions with x/y suffixes. <Exy:vl:attr:sr:sae:src:dst, + $z::EVex512|Disp8MemShift=6:StaticRounding|SAE:SAE:RegZMM|Unspecified|BaseIndex:RegYMM, + - $i:CpuAVX512VL:Disp8ShiftVL|IntelSyntax:::RegXMM|RegYMM|Unspecified|BaseIndex:RegXMM, + - $a:CpuAVX512VL:Disp8ShiftVL|ATTSyntax:::RegXMM|RegYMM|BaseIndex:RegXMM, + - x:CpuAVX512VL:EVex128|Disp8MemShift=4|ATTSyntax:::RegXMM|Unspecified|BaseIndex:RegXMM, + - y:CpuAVX512VL:EVex256|Disp8MemShift=5|ATTSyntax:::RegYMM|Unspecified|BaseIndex:RegXMM> + $i:AVX512VL:Disp8ShiftVL|IntelSyntax:::RegXMM|RegYMM|Unspecified|BaseIndex:RegXMM, + + $a:AVX512VL:Disp8ShiftVL|ATTSyntax:::RegXMM|RegYMM|BaseIndex:RegXMM, + + x:AVX512VL:EVex128|Disp8MemShift=4|ATTSyntax:::RegXMM|Unspecified|BaseIndex:RegXMM, + + y:AVX512VL:EVex256|Disp8MemShift=5|ATTSyntax:::RegYMM|Unspecified|BaseIndex:RegXMM> kand<bw>, 0x<bw:kpfx>41, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } kandn<bw>, 0x<bw:kpfx>42, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } @@ -2063,7 +2078,7 @@ kortest<bw>, 0x<bw:kpfx>98, <bw:kcpu>, Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMa kshiftl<bw>, 0x6632, <bw:kcpu>, Modrm|Vex128|Space0F3A|<bw:vexw>|NoSuf, { Imm8, RegMask, RegMask } kshiftr<bw>, 0x6630, <bw:kcpu>, Modrm|Vex128|Space0F3A|<bw:vexw>|NoSuf, { Imm8, RegMask, RegMask } -kunpckbw, 0x664B, CpuAVX512F, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegMask, RegMask, RegMask } +kunpckbw, 0x664B, AVX512F, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegMask, RegMask, RegMask } vaddp<sdh>, 0x<sdh:ppfx>58, <sdh:cpu>, Modrm|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vdivp<sdh>, 0x<sdh:ppfx>5e, <sdh:cpu>, Modrm|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } @@ -2077,130 +2092,130 @@ vmuls<sdh>, 0x<sdh:spfx>59, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc1>|VexVVV vsqrts<sdh>, 0x<sdh:spfx>51, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } vsubs<sdh>, 0x<sdh:spfx>5C, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } -valign<dq>, 0x6603, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vblendmp<sd>, 0x6665, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpblendm<dq>, 0x6664, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermi2<dq>, 0x6676, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermi2p<sd>, 0x6677, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermt2<dq>, 0x667E, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermt2p<sd>, 0x667F, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxs<dq>, 0x663D, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxu<dq>, 0x663F, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmins<dq>, 0x6639, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminu<dq>, 0x663B, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmuldq, 0x6628, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmulld, 0x6640, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vprolv<dq>, 0x6615, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vprorv<dq>, 0x6614, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsllv<dq>, 0x6647, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrav<dq>, 0x6646, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrlv<dq>, 0x6645, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpternlog<dq>, 0x6625, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vbroadcastf32x4, 0x661A, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } -vbroadcasti32x4, 0x665A, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } - -vbroadcastf64x4, 0x661B, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=2|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } -vbroadcasti64x4, 0x665B, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=2|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } - -vbroadcastss, 0x6618, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vbroadcastsd, 0x6619, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } - -vpbroadcast<dq>, 0x6658 | <dq:opc>, CpuAVX512F, Modrm|Masking=3|Space0F38|<dq:vexw>|Disp8MemShift|NoSuf, { RegXMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpbroadcast<dq>, 0x667c, CpuAVX512F, Modrm|Masking=3|Space0F38|<dq:vexw64>|NoSuf, { <dq:gpr>, RegXMM|RegYMM|RegZMM } - -vcmp<frel>p<sd>, 0x<sd:ppfx>C2/0x<frel:imm>, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vcmpp<sd>, 0x<sd:ppfx>C2, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } - -vcmp<frel>s<sd>, 0x<sd:spfx>C2/0x<frel:imm>, CpuAVX512F, Modrm|EVexLIG|Masking=2|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegMask } -vcmps<sd>, 0x<sd:spfx>C2, CpuAVX512F, Modrm|EVexLIG|Masking=2|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegMask } +valign<dq>, 0x6603, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vblendmp<sd>, 0x6665, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpblendm<dq>, 0x6664, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermi2<dq>, 0x6676, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermi2p<sd>, 0x6677, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermt2<dq>, 0x667E, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermt2p<sd>, 0x667F, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxs<dq>, 0x663D, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxu<dq>, 0x663F, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmins<dq>, 0x6639, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminu<dq>, 0x663B, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmuldq, 0x6628, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmulld, 0x6640, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vprolv<dq>, 0x6615, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vprorv<dq>, 0x6614, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsllv<dq>, 0x6647, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrav<dq>, 0x6646, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrlv<dq>, 0x6645, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpternlog<dq>, 0x6625, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vbroadcastf32x4, 0x661A, AVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } +vbroadcasti32x4, 0x665A, AVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } + +vbroadcastf64x4, 0x661B, AVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=2|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } +vbroadcasti64x4, 0x665B, AVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=2|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } + +vbroadcastss, 0x6618, AVX512F, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vbroadcastsd, 0x6619, AVX512F, Modrm|Masking=3|Space0F38|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } + +vpbroadcast<dq>, 0x6658 | <dq:opc>, AVX512F, Modrm|Masking=3|Space0F38|<dq:vexw>|Disp8MemShift|NoSuf, { RegXMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpbroadcast<dq>, 0x667c, AVX512F, Modrm|Masking=3|Space0F38|<dq:vexw64>|NoSuf, { <dq:gpr>, RegXMM|RegYMM|RegZMM } + +vcmp<frel>p<sd>, 0x<sd:ppfx>C2/0x<frel:imm>, AVX512F, Modrm|Masking=2|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vcmpp<sd>, 0x<sd:ppfx>C2, AVX512F, Modrm|Masking=2|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } + +vcmp<frel>s<sd>, 0x<sd:spfx>C2/0x<frel:imm>, AVX512F, Modrm|EVexLIG|Masking=2|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegMask } +vcmps<sd>, 0x<sd:spfx>C2, AVX512F, Modrm|EVexLIG|Masking=2|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegMask } vcomis<sdh>, 0x<sdh:ppfx>2f, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM } vucomis<sdh>, 0x<sdh:ppfx>2e, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM } -vcompresspd, 0x668A, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vcompressps, 0x668A, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vpcompressq, 0x668B, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vpcompressd, 0x668B, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vcompresspd, 0x668A, AVX512F, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vcompressps, 0x668A, AVX512F, Modrm|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vpcompressq, 0x668B, AVX512F, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vpcompressd, 0x668B, AVX512F, Modrm|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vpscatterdd, 0x66A0, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|BaseIndex } -vpscatterdq, 0x66A0, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } -vpscatterqd, 0x66A1, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } -vpscatterqq, 0x66A1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } -vscatterdpd, 0x66A2, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } -vscatterdps, 0x66A2, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|BaseIndex } -vscatterqpd, 0x66A3, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } -vscatterqps, 0x66A3, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } +vpscatterdd, 0x66A0, AVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|BaseIndex } +vpscatterdq, 0x66A0, AVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } +vpscatterqd, 0x66A1, AVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } +vpscatterqq, 0x66A1, AVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } +vscatterdpd, 0x66A2, AVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } +vscatterdps, 0x66A2, AVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|BaseIndex } +vscatterqpd, 0x66A3, AVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } +vscatterqps, 0x66A3, AVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } -vcvtdq2pd, 0xF3E6, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F|VexW=1|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvtudq2pd, 0xF37A, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F|VexW=1|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtdq2pd, 0xF3E6, AVX512F, Modrm|EVex=1|Masking=3|Space0F|VexW=1|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtudq2pd, 0xF37A, AVX512F, Modrm|EVex=1|Masking=3|Space0F|VexW=1|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvtdq2ps, 0x5B, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtps2udq, 0x79, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtdq2ps, 0x5B, AVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtps2udq, 0x79, AVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtpd2dq<Exy>, 0xf2e6, CpuAVX512F|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } +vcvtpd2dq<Exy>, 0xf2e6, AVX512F|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } -vcvtpd2ps<Exy>, 0x665a, CpuAVX512F|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } +vcvtpd2ps<Exy>, 0x665a, AVX512F|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } -vcvtpd2udq<Exy>, 0x79, CpuAVX512F|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } +vcvtpd2udq<Exy>, 0x79, AVX512F|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } -vcvtph2ps, 0x6613, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexW0|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Unspecified|BaseIndex, RegZMM } +vcvtph2ps, 0x6613, AVX512F, Modrm|EVex512|Masking=3|Space0F38|VexW0|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Unspecified|BaseIndex, RegZMM } -vcvtps2dq, 0x665B, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtps2dq, 0x665B, AVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtps2pd, 0x5A, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtps2pd, 0x5A, AVX512F, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvtps2ph, 0x661D, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=5|NoSuf|SAE, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vcvtps2ph, 0x661D, AVX512F, Modrm|EVex512|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=5|NoSuf|SAE, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } -vcvts<sd>2si, 0x<sd:spfx>2d, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, Reg32|Reg64 } +vcvts<sd>2si, 0x<sd:spfx>2d, AVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, Reg32|Reg64 } vcvts<sdh>2usi, 0x<sdh:spfx>79, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, Reg32|Reg64 } -vcvtsd2ss, 0xF25A, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F|VexVVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsd2ss, 0xF25A, AVX512F, Modrm|EVexLIG|Masking=3|Space0F|VexVVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sd, 0xF22A, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sd, 0xF22A, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sd, 0xF22A, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sd, 0xF22A, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sd, 0xF27B, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sd, 0xF27B, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sd, 0xF27B, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sd, 0xF27B, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2ss, 0xF32A, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2ss, 0xF32A, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2ss, 0xF37B, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2ss, 0xF37B, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2ss, 0xF32A, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2ss, 0xF32A, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2ss, 0xF37B, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2ss, 0xF37B, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtss2sd, 0xF35A, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F|VexVVVV|VexW0|Disp8MemShift=2|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtss2sd, 0xF35A, AVX512F, Modrm|EVexLIG|Masking=3|Space0F|VexVVVV|VexW0|Disp8MemShift=2|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvttpd2dq<Exy>, 0x66e6, CpuAVX512F|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sae>, { <Exy:src>|Qword, <Exy:dst> } -vcvttpd2udq<Exy>, 0x78, CpuAVX512F|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sae>, { <Exy:src>|Qword, <Exy:dst> } +vcvttpd2dq<Exy>, 0x66e6, AVX512F|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sae>, { <Exy:src>|Qword, <Exy:dst> } +vcvttpd2udq<Exy>, 0x78, AVX512F|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sae>, { <Exy:src>|Qword, <Exy:dst> } -vcvttps2dq, 0xF35B, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttps2udq, 0x78, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttps2dq, 0xF35B, AVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttps2udq, 0x78, AVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtts<sd>2si, 0x<sd:spfx>2c, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, Reg32|Reg64 } +vcvtts<sd>2si, 0x<sd:spfx>2c, AVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, Reg32|Reg64 } vcvtts<sdh>2usi, 0x<sdh:spfx>78, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, Reg32|Reg64 } -vcvtudq2ps, 0xF27A, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtudq2ps, 0xF27A, AVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vexpandpd, 0x6688, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpexpandq, 0x6689, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vexpandpd, 0x6688, AVX512F, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpexpandq, 0x6689, AVX512F, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vexpandps, 0x6688, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpexpandd, 0x6689, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vexpandps, 0x6688, AVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpexpandd, 0x6689, AVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vextractf32x4, 0x6619, CpuAVX512F, Modrm|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } -vextracti32x4, 0x6639, CpuAVX512F, Modrm|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } +vextractf32x4, 0x6619, AVX512F, Modrm|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } +vextracti32x4, 0x6639, AVX512F, Modrm|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } -vextractf64x4, 0x661B, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } -vextracti64x4, 0x663B, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vextractf64x4, 0x661B, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vextracti64x4, 0x663B, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } -vextractps, 0x6617, CpuAVX512F, Modrm|EVex128|Space0F3A|VexWIG|Disp8MemShift=2|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } -vextractps, 0x6617, CpuAVX512F|Cpu64, RegMem|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 } +vextractps, 0x6617, AVX512F, Modrm|EVex128|Space0F3A|VexWIG|Disp8MemShift=2|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } +vextractps, 0x6617, AVX512F|x64, RegMem|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 } -vfixupimmp<sd>, 0x6654, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfixupimms<sd>, 0x6655, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } +vfixupimmp<sd>, 0x6654, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfixupimms<sd>, 0x6655, AVX512F, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } vgetmantp<sdh>, 0x<sdh:pfx>26, <sdh:cpu>, Modrm|Masking=3|Space0F3A|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vgetmants<sdh>, 0x<sdh:pfx>27, <sdh:cpu>, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } @@ -2222,27 +2237,27 @@ vfnmsub<fma>s<sdh>, 0x668f | 0x<fma:opc>, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sd vscalefp<sdh>, 0x662c, <sdh:cpu>, Modrm|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vscalefs<sdh>, 0x662d, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } -vgatherdpd, 0x6692, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } -vgatherdps, 0x6692, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegZMM } -vgatherqpd, 0x6693, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } -vgatherqps, 0x6693, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } -vpgatherdd, 0x6690, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegZMM } -vpgatherdq, 0x6690, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } -vpgatherqd, 0x6691, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } -vpgatherqq, 0x6691, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } +vgatherdpd, 0x6692, AVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } +vgatherdps, 0x6692, AVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegZMM } +vgatherqpd, 0x6693, AVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } +vgatherqps, 0x6693, AVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } +vpgatherdd, 0x6690, AVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegZMM } +vpgatherdq, 0x6690, AVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } +vpgatherqd, 0x6691, AVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } +vpgatherqq, 0x6691, AVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } -vmovntdqa, 0x662A, CpuAVX512F, Modrm|Space0F38|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { XMMword|YMMword|ZMMword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovntdqa, 0x662A, AVX512F, Modrm|Space0F38|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { XMMword|YMMword|ZMMword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vgetexpp<sdh>, 0x6642, <sdh:cpu>, Modrm|Masking=3|<sdh:spc2>|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vgetexps<sdh>, 0x6643, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } -vinsertf32x4, 0x6618, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vinserti32x4, 0x6638, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vinsertf32x4, 0x6618, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vinserti32x4, 0x6638, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vinsertf64x4, 0x661A, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } -vinserti64x4, 0x663A, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } +vinsertf64x4, 0x661A, AVX512F, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } +vinserti64x4, 0x663A, AVX512F, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } -vinsertps, 0x6621, CpuAVX512F, Modrm|EVex128|Space0F3A|VexVVVV|VexW0|Disp8MemShift=2|NoSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vinsertps, 0x6621, AVX512F, Modrm|EVex128|Space0F3A|VexVVVV|VexW0|Disp8MemShift=2|NoSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } vmaxp<sdh>, 0x<sdh:ppfx>5f, <sdh:cpu>, Modrm|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vmaxs<sdh>, 0x<sdh:spfx>5f, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } @@ -2250,454 +2265,454 @@ vmaxs<sdh>, 0x<sdh:spfx>5f, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc1>|VexVVV vminp<sdh>, 0x<sdh:ppfx>5d, <sdh:cpu>, Modrm|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vmins<sdh>, 0x<sdh:spfx>5d, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } -vmovap<sd>, 0x<sd:ppfx>28, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|<sd:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovntp<sd>, 0x<sd:ppfx>2B, CpuAVX512F, Modrm|Space0F|<sd:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex } -vmovup<sd>, 0x<sd:ppfx>10, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|<sd:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovap<sd>, 0x<sd:ppfx>28, AVX512F, D|Modrm|MaskingMorZ|Space0F|<sd:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovntp<sd>, 0x<sd:ppfx>2B, AVX512F, Modrm|Space0F|<sd:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex } +vmovup<sd>, 0x<sd:ppfx>10, AVX512F, D|Modrm|MaskingMorZ|Space0F|<sd:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovd, 0x666E, CpuAVX512F, D|Modrm|EVex=2|Space0F|Disp8MemShift=2|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } +vmovd, 0x666E, AVX512F, D|Modrm|EVex=2|Space0F|Disp8MemShift=2|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } -vmovddup, 0xF212, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM } +vmovddup, 0xF212, AVX512F, Modrm|Masking=3|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM } -vmovdqa64, 0x666F, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovdqa32, 0x666F, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovntdq, 0x66E7, CpuAVX512F, Modrm|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex } -vmovdqu32, 0xF36F, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovdqu64, 0xF36F, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovdqa64, 0x666F, AVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovdqa32, 0x666F, AVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovntdq, 0x66E7, AVX512F, Modrm|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex } +vmovdqu32, 0xF36F, AVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovdqu64, 0xF36F, AVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovhlps, 0x12, CpuAVX512F, Modrm|EVex=4|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegXMM, RegXMM, RegXMM } -vmovlhps, 0x16, CpuAVX512F, Modrm|EVex=4|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegXMM, RegXMM, RegXMM } +vmovhlps, 0x12, AVX512F, Modrm|EVex=4|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegXMM, RegXMM, RegXMM } +vmovlhps, 0x16, AVX512F, Modrm|EVex=4|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegXMM, RegXMM, RegXMM } -vmovhp<sd>, 0x<sd:ppfx>16, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vmovhp<sd>, 0x<sd:ppfx>17, CpuAVX512F, Modrm|EVexLIG|Space0F|<sd:vexw>|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } -vmovlp<sd>, 0x<sd:ppfx>12, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vmovlp<sd>, 0x<sd:ppfx>13, CpuAVX512F, Modrm|EVexLIG|Space0F|<sd:vexw>|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } +vmovhp<sd>, 0x<sd:ppfx>16, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vmovhp<sd>, 0x<sd:ppfx>17, AVX512F, Modrm|EVexLIG|Space0F|<sd:vexw>|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } +vmovlp<sd>, 0x<sd:ppfx>12, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vmovlp<sd>, 0x<sd:ppfx>13, AVX512F, Modrm|EVexLIG|Space0F|<sd:vexw>|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } -vmovq, 0x666E, CpuAVX512F|Cpu64, D|Modrm|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Reg64|Unspecified|BaseIndex, RegXMM } -vmovq, 0xF37E, CpuAVX512F, Load|Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vmovq, 0x66D6, CpuAVX512F, Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } +vmovq, 0x666E, AVX512F|x64, D|Modrm|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Reg64|Unspecified|BaseIndex, RegXMM } +vmovq, 0xF37E, AVX512F, Load|Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vmovq, 0x66D6, AVX512F, Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } vmovs<sdh>, 0x<sdh:spfx>10, <sdh:cpu>, D|Modrm|EVexLIG|MaskingMorZ|<sdh:spc1>|<sdh:vexw>|Disp8MemShift|NoSuf, { <sdh:elem>|Unspecified|BaseIndex, RegXMM } vmovs<sdh>, 0x<sdh:spfx>10, <sdh:cpu>, D|Modrm|EVexLIG|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|NoSuf, { RegXMM, RegXMM, RegXMM } -vmovshdup, 0xF316, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovsldup, 0xF312, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } - -vpabs<dq>, 0x661e | <dq:opc>, CpuAVX512F, Modrm|Masking=3|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpaddd, 0x66FE, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpaddq, 0x66d4, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpand<dq>, 0x66db, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpandn<dq>, 0x66df, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmuludq, 0x66f4, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpor<dq>, 0x66eb, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsub<dq>, 0x66fa | <dq:opc>, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckhdq, 0x666A, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckhqdq, 0x666d, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckldq, 0x6662, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpcklqdq, 0x666c, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpxor<dq>, 0x66ef, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vmovshdup, 0xF316, AVX512F, Modrm|Masking=3|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovsldup, 0xF312, AVX512F, Modrm|Masking=3|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +vpabs<dq>, 0x661e | <dq:opc>, AVX512F, Modrm|Masking=3|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpaddd, 0x66FE, AVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpaddq, 0x66d4, AVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpand<dq>, 0x66db, AVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpandn<dq>, 0x66df, AVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmuludq, 0x66f4, AVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpor<dq>, 0x66eb, AVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsub<dq>, 0x66fa | <dq:opc>, AVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckhdq, 0x666A, AVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckhqdq, 0x666d, AVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckldq, 0x6662, AVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpcklqdq, 0x666c, AVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpxor<dq>, 0x66ef, AVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } <irel:imm, eq:0, lt:1, le:2, neq:4, nlt:5, nle:6> -vpcmpeqd, 0x6676, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpeqq, 0x6629, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpgtd, 0x6666, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpgtq, 0x6637, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp<dq>, 0x661f, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpu<dq>, 0x661e, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp<irel><dq>, 0x661f/<irel:imm>, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp<irel>u<dq>, 0x661e/<irel:imm>, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpeqd, 0x6676, AVX512F, Modrm|Masking=2|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpeqq, 0x6629, AVX512F, Modrm|Masking=2|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpgtd, 0x6666, AVX512F, Modrm|Masking=2|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpgtq, 0x6637, AVX512F, Modrm|Masking=2|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp<dq>, 0x661f, AVX512F, Modrm|Masking=2|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpu<dq>, 0x661e, AVX512F, Modrm|Masking=2|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp<irel><dq>, 0x661f/<irel:imm>, AVX512F, Modrm|Masking=2|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp<irel>u<dq>, 0x661e/<irel:imm>, AVX512F, Modrm|Masking=2|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vptestm<dq>, 0x6627, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vptestnm<dq>, 0xf327, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vptestm<dq>, 0x6627, AVX512F, Modrm|Masking=2|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vptestnm<dq>, 0xf327, AVX512F, Modrm|Masking=2|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpermd, 0x6636, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpermps, 0x6616, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vpermd, 0x6636, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vpermps, 0x6616, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpermilp<sd>, 0x6604 | <sd:opc>, CpuAVX512F, Modrm|Masking=3|Space0F3A|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpermilp<sd>, 0x660C | <sd:opc>, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermilp<sd>, 0x6604 | <sd:opc>, AVX512F, Modrm|Masking=3|Space0F3A|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpermilp<sd>, 0x660C | <sd:opc>, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermpd, 0x6601, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } -vpermpd, 0x6616, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpermq, 0x6600, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } -vpermq, 0x6636, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vpermpd, 0x6601, AVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } +vpermpd, 0x6616, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vpermq, 0x6600, AVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } +vpermq, 0x6636, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpmovdb, 0xF331, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovsdb, 0xF321, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovusdb, 0xF311, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovdb, 0xF331, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovsdb, 0xF321, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovusdb, 0xF311, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovdw, 0xF333, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovsdw, 0xF323, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovusdw, 0xF313, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovdw, 0xF333, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovsdw, 0xF323, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovusdw, 0xF313, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovqb, 0xF332, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsqb, 0xF322, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusqb, 0xF312, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovqb, 0xF332, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsqb, 0xF322, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusqb, 0xF312, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovqd, 0xF335, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovsqd, 0xF325, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovusqd, 0xF315, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovqd, 0xF335, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovsqd, 0xF325, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovusqd, 0xF315, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovqw, 0xF334, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovsqw, 0xF324, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovusqw, 0xF314, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovqw, 0xF334, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovsqw, 0xF324, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovusqw, 0xF314, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovsxbd, 0x6621, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } -vpmovzxbd, 0x6631, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovsxbd, 0x6621, AVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovzxbd, 0x6631, AVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } -vpmovsxbq, 0x6622, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } -vpmovzxbq, 0x6632, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } +vpmovsxbq, 0x6622, AVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } +vpmovzxbq, 0x6632, AVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } -vpmovsxdq, 0x6625, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovzxdq, 0x6635, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovsxdq, 0x6625, AVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovzxdq, 0x6635, AVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovsxwd, 0x6623, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovzxwd, 0x6633, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovsxwd, 0x6623, AVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovzxwd, 0x6633, AVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovsxwq, 0x6624, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } -vpmovzxwq, 0x6634, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovsxwq, 0x6624, AVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovzxwq, 0x6634, AVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } -vprol<dq>, 0x6672/1, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpror<dq>, 0x6672/0, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vprol<dq>, 0x6672/1, AVX512F, Modrm|Masking=3|Space0F|VexVVVV=2|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpror<dq>, 0x6672/0, AVX512F, Modrm|Masking=3|Space0F|VexVVVV=2|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpshufd, 0x6670, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpshufd, 0x6670, AVX512F, Modrm|Masking=3|Space0F|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsll<dq>, 0x66f2 | <dq:opc>, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsll<dq>, 0x6672 | <dq:opc>/6, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsra<dq>, 0x66e2, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsra<dq>, 0x6672/4, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsrl<dq>, 0x66d2 | <dq:opc>, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrl<dq>, 0x6672 | <dq:opc>/2, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsll<dq>, 0x66f2 | <dq:opc>, AVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsll<dq>, 0x6672 | <dq:opc>/6, AVX512F, Modrm|Masking=3|Space0F|VexVVVV=2|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsra<dq>, 0x66e2, AVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsra<dq>, 0x6672/4, AVX512F, Modrm|Masking=3|Space0F|VexVVVV=2|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsrl<dq>, 0x66d2 | <dq:opc>, AVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrl<dq>, 0x6672 | <dq:opc>/2, AVX512F, Modrm|Masking=3|Space0F|VexVVVV=2|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrcp14p<sd>, 0x664C, CpuAVX512F, Modrm|Masking=3|Space0F38|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrcp14s<sd>, 0x664D, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } +vrcp14p<sd>, 0x664C, AVX512F, Modrm|Masking=3|Space0F38|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrcp14s<sd>, 0x664D, AVX512F, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } -vrsqrt14p<sd>, 0x664E, CpuAVX512F, Modrm|Masking=3|Space0F38|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrsqrt14s<sd>, 0x664F, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } +vrsqrt14p<sd>, 0x664E, AVX512F, Modrm|Masking=3|Space0F38|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrsqrt14s<sd>, 0x664F, AVX512F, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } -vshuff32x4, 0x6623, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshufi32x4, 0x6643, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshuff32x4, 0x6623, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshufi32x4, 0x6643, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshuff64x2, 0x6623, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshufi64x2, 0x6643, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshuff64x2, 0x6623, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshufi64x2, 0x6643, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshufp<sd>, 0x<sd:ppfx>C6, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vshufp<sd>, 0x<sd:ppfx>C6, AVX512F, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vunpckhp<sd>, 0x<sd:ppfx>15, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vunpcklp<sd>, 0x<sd:ppfx>14, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vunpckhp<sd>, 0x<sd:ppfx>15, AVX512F, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vunpcklp<sd>, 0x<sd:ppfx>14, AVX512F, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512F instructions end. // AVX512CD instructions. -vpbroadcastmb2q, 0xF32A, CpuAVX512CD, Modrm|Space0F38|EVex=5|VexW=2|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } -vpbroadcastmw2d, 0xF33A, CpuAVX512CD, Modrm|Space0F38|EVex=5|VexW=1|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } +vpbroadcastmb2q, 0xF32A, AVX512CD, Modrm|Space0F38|EVex=5|VexW=2|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } +vpbroadcastmw2d, 0xF33A, AVX512CD, Modrm|Space0F38|EVex=5|VexW=1|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } -vpconflict<dq>, 0x66c4, CpuAVX512CD, Modrm|Masking=3|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpconflict<dq>, 0x66c4, AVX512CD, Modrm|Masking=3|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vplzcnt<dq>, 0x6644, CpuAVX512CD, Modrm|Masking=3|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vplzcnt<dq>, 0x6644, AVX512CD, Modrm|Masking=3|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } // AVX512CD instructions end. // AVX512ER instructions. -vexp2p<sd>, 0x66C8, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM|<sd:elem>|Unspecified|BaseIndex, RegZMM } +vexp2p<sd>, 0x66C8, AVX512ER, Modrm|EVex512|Masking=3|Space0F38|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM|<sd:elem>|Unspecified|BaseIndex, RegZMM } -vrcp28p<sd>, 0x66CA, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM|<sd:elem>|Unspecified|BaseIndex, RegZMM } -vrcp28s<sd>, 0x66CB, CpuAVX512ER, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } +vrcp28p<sd>, 0x66CA, AVX512ER, Modrm|EVex512|Masking=3|Space0F38|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM|<sd:elem>|Unspecified|BaseIndex, RegZMM } +vrcp28s<sd>, 0x66CB, AVX512ER, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } -vrsqrt28p<sd>, 0x66CC, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM|<sd:elem>|Unspecified|BaseIndex, RegZMM } -vrsqrt28s<sd>, 0x66CD, CpuAVX512ER, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } +vrsqrt28p<sd>, 0x66CC, AVX512ER, Modrm|EVex512|Masking=3|Space0F38|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM|<sd:elem>|Unspecified|BaseIndex, RegZMM } +vrsqrt28s<sd>, 0x66CD, AVX512ER, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } // AVX512ER instructions end. // AVX512PF instructions. -vgatherpf0dpd, 0x66C6/1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } -vgatherpf0dps, 0x66C6/1, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } -vgatherpf0qp<sd>, 0x66C7/1, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } -vgatherpf1dpd, 0x66C6/2, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } -vgatherpf1dps, 0x66C6/2, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } -vgatherpf1qp<sd>, 0x66C7/2, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } +vgatherpf0dpd, 0x66C6/1, AVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } +vgatherpf0dps, 0x66C6/1, AVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } +vgatherpf0qp<sd>, 0x66C7/1, AVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } +vgatherpf1dpd, 0x66C6/2, AVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } +vgatherpf1dps, 0x66C6/2, AVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } +vgatherpf1qp<sd>, 0x66C7/2, AVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } -vscatterpf0dpd, 0x66C6/5, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } -vscatterpf0dps, 0x66C6/5, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } -vscatterpf0qp<sd>, 0x66C7/5, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } -vscatterpf1dpd, 0x66C6/6, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } -vscatterpf1dps, 0x66C6/6, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } -vscatterpf1qp<sd>, 0x66C7/6, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } +vscatterpf0dpd, 0x66C6/5, AVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } +vscatterpf0dps, 0x66C6/5, AVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } +vscatterpf0qp<sd>, 0x66C7/5, AVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } +vscatterpf1dpd, 0x66C6/6, AVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } +vscatterpf1dps, 0x66C6/6, AVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } +vscatterpf1qp<sd>, 0x66C7/6, AVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } // AVX512PF instructions end. -// CpuPREFETCHWT1 instructions. +// PREFETCHWT1 instructions. -prefetchwt1, 0x0F0D/2, CpuPREFETCHWT1, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +prefetchwt1, 0x0F0D/2, PREFETCHWT1, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -// CpuPREFETCHWT1 instructions end. +// PREFETCHWT1 instructions end. // CLFLUSHOPT instructions. -clflushopt, 0x660fae/7, CpuClflushOpt, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +clflushopt, 0x660fae/7, ClflushOpt, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } // CLFLUSHOPT instructions end. // XSAVES/XRSTORS instructions. -xrstors, 0xfc7/3, CpuXSAVES, Modrm|NoSuf, { Unspecified|BaseIndex } -xrstors64, 0xfc7/3, CpuXSAVES|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } -xsaves, 0xfc7/5, CpuXSAVES, Modrm|NoSuf, { Unspecified|BaseIndex } -xsaves64, 0xfc7/5, CpuXSAVES|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xrstors, 0xfc7/3, XSAVES, Modrm|NoSuf, { Unspecified|BaseIndex } +xrstors64, 0xfc7/3, XSAVES|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xsaves, 0xfc7/5, XSAVES, Modrm|NoSuf, { Unspecified|BaseIndex } +xsaves64, 0xfc7/5, XSAVES|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } // XSAVES instructions end. // XSAVEC instructions. -xsavec, 0xfc7/4, CpuXSAVEC, Modrm|NoSuf, { Unspecified|BaseIndex } -xsavec64, 0xfc7/4, CpuXSAVEC|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xsavec, 0xfc7/4, XSAVEC, Modrm|NoSuf, { Unspecified|BaseIndex } +xsavec64, 0xfc7/4, XSAVEC|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } // XSAVEC instructions end. // SGX instructions. -encls, 0xf01cf, CpuSE1, NoSuf, {} -enclu, 0xf01d7, CpuSE1, NoSuf, {} -enclv, 0xf01c0, CpuSE1, NoSuf, {} +encls, 0xf01cf, SE1, NoSuf, {} +enclu, 0xf01d7, SE1, NoSuf, {} +enclv, 0xf01c0, SE1, NoSuf, {} // SGX instructions end. // AVX512VL instructions. -vgatherdpd, 0x6692, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } -vgatherdps, 0x6692, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } -vgatherdps, 0x6692, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } -vgatherqp<sd>, 0x6693, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB128|NoSuf, { <sd:elem>|Unspecified|BaseIndex, RegXMM } -vgatherqpd, 0x6693, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } -vgatherqps, 0x6693, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } -vpgatherdd, 0x6690, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } -vpgatherdd, 0x6690, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } -vpgatherdq, 0x6690, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } -vpgatherq<dq>, 0x6691, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|<dq:vexw>|Disp8MemShift|VecSIB128|NoSuf, { <dq:elem>|Unspecified|BaseIndex, RegXMM } -vpgatherqd, 0x6691, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } -vpgatherqq, 0x6691, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } - -vpscatterdd, 0x66A0, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } -vpscatterdd, 0x66A0, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } -vpscatterdq, 0x66A0, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } -vpscatterq<dq>, 0x66A1, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|<dq:vexw>|Disp8MemShift|VecSIB128|NoSuf, { RegXMM, <dq:elem>|Unspecified|BaseIndex } -vpscatterqd, 0x66A1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } -vpscatterqq, 0x66A1, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } -vscatterdpd, 0x66A2, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } -vscatterdps, 0x66A2, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } -vscatterdps, 0x66A2, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } -vscatterqp<sd>, 0x66A3, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB128|NoSuf, { RegXMM, <sd:elem>|Unspecified|BaseIndex } -vscatterqpd, 0x66A3, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } -vscatterqps, 0x66A3, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } - -vcvtdq2pd, 0xF3E6, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvtdq2pd, 0xF3E6, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vcvtudq2pd, 0xF37A, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvtudq2pd, 0xF37A, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } - -vcvtph2ps, 0x6613, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2ps, 0x6613, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } - -vcvtps2pd, 0x5A, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvtps2pd, 0x5A, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } - -vcvtps2ph, 0x661D, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=3|NoSuf, { Imm8, RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vcvtps2ph, 0x661D, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, RegXMM|Unspecified|BaseIndex } - -vmovddup, 0xF212, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } - -vpmovdb, 0xF331, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovdb, 0xF331, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsdb, 0xF321, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovsdb, 0xF321, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusdb, 0xF311, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovusdb, 0xF311, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } - -vpmovdw, 0xF333, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovdw, 0xF333, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovsdw, 0xF323, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsdw, 0xF323, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovusdw, 0xF313, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusdw, 0xF313, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } - -vpmovqb, 0xF332, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } -vpmovqb, 0xF332, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovsqb, 0xF322, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } -vpmovsqb, 0xF322, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovusqb, 0xF312, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } -vpmovusqb, 0xF312, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } - -vpmovqd, 0xF335, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovqd, 0xF335, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovsqd, 0xF325, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsqd, 0xF325, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovusqd, 0xF315, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusqd, 0xF315, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } - -vpmovqw, 0xF334, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovqw, 0xF334, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsqw, 0xF324, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovsqw, 0xF324, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusqw, 0xF314, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovusqw, 0xF314, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } - -vpmovsxbd, 0x6621, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } -vpmovsxbd, 0x6621, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } -vpmovzxbd, 0x6631, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } -vpmovzxbd, 0x6631, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } - -vpmovsxbq, 0x6622, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } -vpmovsxbq, 0x6622, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vpmovzxbq, 0x6632, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } -vpmovzxbq, 0x6632, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } - -vpmovsxdq, 0x6625, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovsxdq, 0x6625, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vpmovzxdq, 0x6635, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovzxdq, 0x6635, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } - -vpmovsxwd, 0x6623, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovsxwd, 0x6623, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vpmovzxwd, 0x6633, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovzxwd, 0x6633, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } - -vpmovsxwq, 0x6624, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } -vpmovsxwq, 0x6624, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } -vpmovzxwq, 0x6634, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } -vpmovzxwq, 0x6634, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } +vgatherdpd, 0x6692, AVX512F|AVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } +vgatherdps, 0x6692, AVX512F|AVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } +vgatherdps, 0x6692, AVX512F|AVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } +vgatherqp<sd>, 0x6693, AVX512F|AVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB128|NoSuf, { <sd:elem>|Unspecified|BaseIndex, RegXMM } +vgatherqpd, 0x6693, AVX512F|AVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } +vgatherqps, 0x6693, AVX512F|AVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } +vpgatherdd, 0x6690, AVX512F|AVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } +vpgatherdd, 0x6690, AVX512F|AVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } +vpgatherdq, 0x6690, AVX512F|AVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } +vpgatherq<dq>, 0x6691, AVX512F|AVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|<dq:vexw>|Disp8MemShift|VecSIB128|NoSuf, { <dq:elem>|Unspecified|BaseIndex, RegXMM } +vpgatherqd, 0x6691, AVX512F|AVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } +vpgatherqq, 0x6691, AVX512F|AVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } + +vpscatterdd, 0x66A0, AVX512F|AVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } +vpscatterdd, 0x66A0, AVX512F|AVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } +vpscatterdq, 0x66A0, AVX512F|AVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } +vpscatterq<dq>, 0x66A1, AVX512F|AVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|<dq:vexw>|Disp8MemShift|VecSIB128|NoSuf, { RegXMM, <dq:elem>|Unspecified|BaseIndex } +vpscatterqd, 0x66A1, AVX512F|AVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } +vpscatterqq, 0x66A1, AVX512F|AVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } +vscatterdpd, 0x66A2, AVX512F|AVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } +vscatterdps, 0x66A2, AVX512F|AVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } +vscatterdps, 0x66A2, AVX512F|AVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } +vscatterqp<sd>, 0x66A3, AVX512F|AVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB128|NoSuf, { RegXMM, <sd:elem>|Unspecified|BaseIndex } +vscatterqpd, 0x66A3, AVX512F|AVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } +vscatterqps, 0x66A3, AVX512F|AVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } + +vcvtdq2pd, 0xF3E6, AVX512F|AVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvtdq2pd, 0xF3E6, AVX512F|AVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vcvtudq2pd, 0xF37A, AVX512F|AVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvtudq2pd, 0xF37A, AVX512F|AVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + +vcvtph2ps, 0x6613, AVX512F|AVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vcvtph2ps, 0x6613, AVX512F|AVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } + +vcvtps2pd, 0x5A, AVX512F|AVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvtps2pd, 0x5A, AVX512F|AVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + +vcvtps2ph, 0x661D, AVX512F|AVX512VL, Modrm|EVex128|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=3|NoSuf, { Imm8, RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vcvtps2ph, 0x661D, AVX512F|AVX512VL, Modrm|EVex256|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, RegXMM|Unspecified|BaseIndex } + +vmovddup, 0xF212, AVX512F|AVX512VL, Modrm|EVex=2|Masking=3|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } + +vpmovdb, 0xF331, AVX512F|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovdb, 0xF331, AVX512F|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsdb, 0xF321, AVX512F|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovsdb, 0xF321, AVX512F|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusdb, 0xF311, AVX512F|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovusdb, 0xF311, AVX512F|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } + +vpmovdw, 0xF333, AVX512F|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovdw, 0xF333, AVX512F|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +vpmovsdw, 0xF323, AVX512F|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsdw, 0xF323, AVX512F|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +vpmovusdw, 0xF313, AVX512F|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusdw, 0xF313, AVX512F|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } + +vpmovqb, 0xF332, AVX512F|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } +vpmovqb, 0xF332, AVX512F|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovsqb, 0xF322, AVX512F|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } +vpmovsqb, 0xF322, AVX512F|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovusqb, 0xF312, AVX512F|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } +vpmovusqb, 0xF312, AVX512F|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } + +vpmovqd, 0xF335, AVX512F|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovqd, 0xF335, AVX512F|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +vpmovsqd, 0xF325, AVX512F|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsqd, 0xF325, AVX512F|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +vpmovusqd, 0xF315, AVX512F|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusqd, 0xF315, AVX512F|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } + +vpmovqw, 0xF334, AVX512F|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovqw, 0xF334, AVX512F|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsqw, 0xF324, AVX512F|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovsqw, 0xF324, AVX512F|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusqw, 0xF314, AVX512F|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovusqw, 0xF314, AVX512F|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } + +vpmovsxbd, 0x6621, AVX512F|AVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +vpmovsxbd, 0x6621, AVX512F|AVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } +vpmovzxbd, 0x6631, AVX512F|AVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +vpmovzxbd, 0x6631, AVX512F|AVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } + +vpmovsxbq, 0x6622, AVX512F|AVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } +vpmovsxbq, 0x6622, AVX512F|AVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vpmovzxbq, 0x6632, AVX512F|AVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } +vpmovzxbq, 0x6632, AVX512F|AVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + +vpmovsxdq, 0x6625, AVX512F|AVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovsxdq, 0x6625, AVX512F|AVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +vpmovzxdq, 0x6635, AVX512F|AVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovzxdq, 0x6635, AVX512F|AVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } + +vpmovsxwd, 0x6623, AVX512F|AVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovsxwd, 0x6623, AVX512F|AVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +vpmovzxwd, 0x6633, AVX512F|AVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovzxwd, 0x6633, AVX512F|AVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } + +vpmovsxwq, 0x6624, AVX512F|AVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +vpmovsxwq, 0x6624, AVX512F|AVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } +vpmovzxwq, 0x6634, AVX512F|AVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +vpmovzxwq, 0x6634, AVX512F|AVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } // AVX512VL instructions end. // AVX512BW instructions. -kadd<dq>, 0x<dq:kpfx>4a, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } -kand<dq>, 0x<dq:kpfx>41, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } -kandn<dq>, 0x<dq:kpfx>42, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } -kmov<dq>, 0x<dq:kpfx>90, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask|<dq:elem>|Unspecified|BaseIndex, RegMask } -kmov<dq>, 0x<dq:kpfx>91, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, <dq:elem>|Unspecified|BaseIndex } -kmov<dq>, 0xf292, CpuAVX512BW, D|Modrm|Vex128|Space0F|<dq:vexw64>|NoSuf, { <dq:gpr>, RegMask } -knot<dq>, 0x<dq:kpfx>44, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } -kor<dq>, 0x<dq:kpfx>45, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } -kortest<dq>, 0x<dq:kpfx>98, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } -ktest<dq>, 0x<dq:kpfx>99, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } -kxnor<dq>, 0x<dq:kpfx>46, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } -kxor<dq>, 0x<dq:kpfx>47, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } -kunpckdq, 0x4B, CpuAVX512BW, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=2|NoSuf, { RegMask, RegMask, RegMask } -kunpckwd, 0x4B, CpuAVX512BW, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegMask, RegMask, RegMask } -kshiftl<dq>, 0x6633, CpuAVX512BW, Modrm|Vex128|Space0F3A|<dq:vexw>|NoSuf, { Imm8, RegMask, RegMask } -kshiftr<dq>, 0x6631, CpuAVX512BW, Modrm|Vex128|Space0F3A|<dq:vexw>|NoSuf, { Imm8, RegMask, RegMask } - -vdbpsadbw, 0x6642, CpuAVX512BW, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vmovdqu8, 0xF26F, CpuAVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovdqu16, 0xF26F, CpuAVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } - -vpabs<bw>, 0x661c | <bw:opc>, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpmaxsb, 0x663C, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminsb, 0x6638, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshufb, 0x6600, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpmaddubsw, 0x6604, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxuw, 0x663E, CpuAVX512BW, Modrm|Masking=3|VexWIG|Space0F38|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminuw, 0x663A, CpuAVX512BW, Modrm|Masking=3|VexWIG|Space0F38|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmulhrsw, 0x660B, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpackssdw, 0x666B, CpuAVX512BW, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpacksswb, 0x6663, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpackuswb, 0x6667, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpackusdw, 0x662B, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpadd<bw>, 0x66fc | <bw:opc>, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpadds<bw>, 0x66ec | <bw:opc>, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpaddus<bw>, 0x66dc | <bw:opc>, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpavg<bw>, 0x66e0 | (3 * <bw:opc>), CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxub, 0x66DE, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminub, 0x66DA, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsub<bw>, 0x66f8 | <bw:opc>, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsubs<bw>, 0x66e8 | <bw:opc>, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsubus<bw>, 0x66d8 | <bw:opc>, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckhbw, 0x6668, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpcklbw, 0x6660, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpmaxsw, 0x66EE, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminsw, 0x66EA, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmulhuw, 0x66E4, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmulhw, 0x66E5, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmullw, 0x66D5, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsllw, 0x6671/6, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsllw, 0x66F1, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsraw, 0x6671/4, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsraw, 0x66E1, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrlw, 0x6671/2, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsrlw, 0x66D1, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckhwd, 0x6669, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpcklwd, 0x6661, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpalignr, 0x660F, CpuAVX512BW, Modrm|Masking=3|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpblendm<bw>, 0x6666, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpbroadcast<bw>, 0x6678 | <bw:opc>, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift|NoSuf, { RegXMM|<bw:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpbroadcast<bw>, 0x667a | <bw:opc>, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexW0|NoSuf, { Reg32, RegXMM|RegYMM|RegZMM } +kadd<dq>, 0x<dq:kpfx>4a, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } +kand<dq>, 0x<dq:kpfx>41, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } +kandn<dq>, 0x<dq:kpfx>42, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } +kmov<dq>, 0x<dq:kpfx>90, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask|<dq:elem>|Unspecified|BaseIndex, RegMask } +kmov<dq>, 0x<dq:kpfx>91, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, <dq:elem>|Unspecified|BaseIndex } +kmov<dq>, 0xf292, AVX512BW, D|Modrm|Vex128|Space0F|<dq:vexw64>|NoSuf, { <dq:gpr>, RegMask } +knot<dq>, 0x<dq:kpfx>44, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } +kor<dq>, 0x<dq:kpfx>45, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } +kortest<dq>, 0x<dq:kpfx>98, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } +ktest<dq>, 0x<dq:kpfx>99, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } +kxnor<dq>, 0x<dq:kpfx>46, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } +kxor<dq>, 0x<dq:kpfx>47, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } +kunpckdq, 0x4B, AVX512BW, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=2|NoSuf, { RegMask, RegMask, RegMask } +kunpckwd, 0x4B, AVX512BW, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegMask, RegMask, RegMask } +kshiftl<dq>, 0x6633, AVX512BW, Modrm|Vex128|Space0F3A|<dq:vexw>|NoSuf, { Imm8, RegMask, RegMask } +kshiftr<dq>, 0x6631, AVX512BW, Modrm|Vex128|Space0F3A|<dq:vexw>|NoSuf, { Imm8, RegMask, RegMask } + +vdbpsadbw, 0x6642, AVX512BW, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vmovdqu8, 0xF26F, AVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovdqu16, 0xF26F, AVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +vpabs<bw>, 0x661c | <bw:opc>, AVX512BW, Modrm|Masking=3|Space0F38|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpmaxsb, 0x663C, AVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminsb, 0x6638, AVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshufb, 0x6600, AVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpmaddubsw, 0x6604, AVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxuw, 0x663E, AVX512BW, Modrm|Masking=3|VexWIG|Space0F38|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminuw, 0x663A, AVX512BW, Modrm|Masking=3|VexWIG|Space0F38|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmulhrsw, 0x660B, AVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpackssdw, 0x666B, AVX512BW, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpacksswb, 0x6663, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpackuswb, 0x6667, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpackusdw, 0x662B, AVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpadd<bw>, 0x66fc | <bw:opc>, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpadds<bw>, 0x66ec | <bw:opc>, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpaddus<bw>, 0x66dc | <bw:opc>, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpavg<bw>, 0x66e0 | (3 * <bw:opc>), AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxub, 0x66DE, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminub, 0x66DA, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsub<bw>, 0x66f8 | <bw:opc>, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsubs<bw>, 0x66e8 | <bw:opc>, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsubus<bw>, 0x66d8 | <bw:opc>, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckhbw, 0x6668, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpcklbw, 0x6660, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpmaxsw, 0x66EE, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminsw, 0x66EA, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmulhuw, 0x66E4, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmulhw, 0x66E5, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmullw, 0x66D5, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsllw, 0x6671/6, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsllw, 0x66F1, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsraw, 0x6671/4, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsraw, 0x66E1, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrlw, 0x6671/2, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsrlw, 0x66D1, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckhwd, 0x6669, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpcklwd, 0x6661, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpalignr, 0x660F, AVX512BW, Modrm|Masking=3|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpblendm<bw>, 0x6666, AVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpbroadcast<bw>, 0x6678 | <bw:opc>, AVX512BW, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift|NoSuf, { RegXMM|<bw:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpbroadcast<bw>, 0x667a | <bw:opc>, AVX512BW, Modrm|Masking=3|Space0F38|VexW0|NoSuf, { Reg32, RegXMM|RegYMM|RegZMM } vpermi2<bw>, 0x6675, <bw:cpubmi>, Modrm|Masking=3|Space0F38|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpermt2<bw>, 0x667d, <bw:cpubmi>, Modrm|Masking=3|Space0F38|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vperm<bw>, 0x668d, <bw:cpubmi>, Modrm|Masking=3|Space0F38|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsllvw, 0x6612, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsravw, 0x6611, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrlvw, 0x6610, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsllvw, 0x6612, AVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsravw, 0x6611, AVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrlvw, 0x6610, AVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpcmpeq<bw>, 0x6674 | <bw:opc>, CpuAVX512BW, Modrm|Masking=2|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpgt<bw>, 0x6664 | <bw:opc>, CpuAVX512BW, Modrm|Masking=2|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp<bw>, 0x663f, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpu<bw>, 0x663e, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp<irel><bw>, 0x663f/<irel:imm>, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp<irel>u<bw>, 0x663e/<irel:imm>, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpeq<bw>, 0x6674 | <bw:opc>, AVX512BW, Modrm|Masking=2|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpgt<bw>, 0x6664 | <bw:opc>, AVX512BW, Modrm|Masking=2|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp<bw>, 0x663f, AVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpu<bw>, 0x663e, AVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp<irel><bw>, 0x663f/<irel:imm>, AVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp<irel>u<bw>, 0x663e/<irel:imm>, AVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpslldq, 0x6673/7, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsrldq, 0x6673/3, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpslldq, 0x6673/7, AVX512BW, Modrm|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsrldq, 0x6673/3, AVX512BW, Modrm|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpextrw, 0x66C5, CpuAVX512BW, Load|Modrm|EVex128|Space0F|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } -vpextr<bw>, 0x6614 | <bw:opc>, CpuAVX512BW, RegMem|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } -vpextr<bw>, 0x6614 | <bw:opc>, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|Disp8MemShift|NoSuf, { Imm8, RegXMM, <bw:elem>|Unspecified|BaseIndex } +vpextrw, 0x66C5, AVX512BW, Load|Modrm|EVex128|Space0F|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } +vpextr<bw>, 0x6614 | <bw:opc>, AVX512BW, RegMem|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } +vpextr<bw>, 0x6614 | <bw:opc>, AVX512BW, Modrm|EVex128|Space0F3A|VexWIG|Disp8MemShift|NoSuf, { Imm8, RegXMM, <bw:elem>|Unspecified|BaseIndex } -vpinsrw, 0x66C4, CpuAVX512BW, Modrm|EVex128|Space0F|VexWIG|VexVVVV=1|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } -vpinsrw, 0x66C4, CpuAVX512BW, Modrm|EVex128|Space0F|VexWIG|VexVVVV|Disp8MemShift=1|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM } -vpinsrb, 0x6620, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|VexVVVV=1|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } -vpinsrb, 0x6620, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|VexVVVV|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM } +vpinsrw, 0x66C4, AVX512BW, Modrm|EVex128|Space0F|VexWIG|VexVVVV=1|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } +vpinsrw, 0x66C4, AVX512BW, Modrm|EVex128|Space0F|VexWIG|VexVVVV|Disp8MemShift=1|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vpinsrb, 0x6620, AVX512BW, Modrm|EVex128|Space0F3A|VexWIG|VexVVVV=1|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } +vpinsrb, 0x6620, AVX512BW, Modrm|EVex128|Space0F3A|VexWIG|VexVVVV|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmaddwd, 0x66F5, CpuAVX512BW, Modrm|Masking=3|Space0F|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaddwd, 0x66F5, AVX512BW, Modrm|Masking=3|Space0F|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmov<bw>2m, 0xf329, CpuAVX512BW, Modrm|EVexDYN|Space0F38|<bw:vexw>|NoSuf, { RegXMM|RegYMM|RegZMM, RegMask } -vpmovm2<bw>, 0xf328, CpuAVX512BW, Modrm|EVexDYN|Space0F38|<bw:vexw>|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } +vpmov<bw>2m, 0xf329, AVX512BW, Modrm|EVexDYN|Space0F38|<bw:vexw>|NoSuf, { RegXMM|RegYMM|RegZMM, RegMask } +vpmovm2<bw>, 0xf328, AVX512BW, Modrm|EVexDYN|Space0F38|<bw:vexw>|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } -vpmovswb, 0xF320, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovswb, 0xF320, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovswb, 0xF320, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +vpmovswb, 0xF320, AVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovswb, 0xF320, AVX512BW|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovswb, 0xF320, AVX512BW|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovuswb, 0xF310, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovuswb, 0xF310, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovuswb, 0xF310, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +vpmovuswb, 0xF310, AVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovuswb, 0xF310, AVX512BW|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovuswb, 0xF310, AVX512BW|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovwb, 0xF330, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovwb, 0xF330, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovwb, 0xF330, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } +vpmovwb, 0xF330, AVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovwb, 0xF330, AVX512BW|AVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovwb, 0xF330, AVX512BW|AVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovsxbw, 0x6620, CpuAVX512BW, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovsxbw, 0x6620, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovsxbw, 0x6620, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vpmovzxbw, 0x6630, CpuAVX512BW, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovzxbw, 0x6630, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovzxbw, 0x6630, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +vpmovsxbw, 0x6620, AVX512BW, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovsxbw, 0x6620, AVX512BW|AVX512VL, Modrm|EVex=2|Masking=3|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovsxbw, 0x6620, AVX512BW|AVX512VL, Modrm|EVex=3|Masking=3|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +vpmovzxbw, 0x6630, AVX512BW, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovzxbw, 0x6630, AVX512BW|AVX512VL, Modrm|EVex=2|Masking=3|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovzxbw, 0x6630, AVX512BW|AVX512VL, Modrm|EVex=3|Masking=3|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vpsadbw, 0x66F6, CpuAVX512BW, Modrm|Space0F|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsadbw, 0x66F6, AVX512BW, Modrm|Space0F|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshufhw, 0xF370, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpshuflw, 0xF270, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpshufhw, 0xF370, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpshuflw, 0xF270, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vptestm<bw>, 0x6626, CpuAVX512BW, Modrm|Masking=2|Space0F38|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vptestnm<bw>, 0xf326, CpuAVX512BW, Modrm|Masking=2|Space0F38|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vptestm<bw>, 0x6626, AVX512BW, Modrm|Masking=2|Space0F38|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vptestnm<bw>, 0xf326, AVX512BW, Modrm|Masking=2|Space0F38|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } // AVX512BW instructions end. @@ -2707,79 +2722,79 @@ vptestnm<bw>, 0xf326, CpuAVX512BW, Modrm|Masking=2|Space0F38|VexVVVV|<bw:vexw>|D $i::Disp8ShiftVL|IntelSyntax:StaticRounding|SAE::RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, + $a::Disp8ShiftVL|ATTSyntax:StaticRounding|SAE::RegXMM|RegYMM|RegZMM|BaseIndex, + z::EVex512|Disp8MemShift=6:StaticRounding|SAE:ATTSyntax:RegZMM|Unspecified|BaseIndex, + - x:CpuAVX512VL:EVex128|Disp8MemShift=4::ATTSyntax:RegXMM|Unspecified|BaseIndex, + - y:CpuAVX512VL:EVex256|Disp8MemShift=5::ATTSyntax:RegYMM|Unspecified|BaseIndex> - -kadd<bw>, 0x<bw:kpfx>4A, CpuAVX512DQ, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } -ktest<bw>, 0x<bw:kpfx>99, CpuAVX512DQ, Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } - -vandnp<sd>, 0x<sd:ppfx>55, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vandp<sd>, 0x<sd:ppfx>54, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vorp<sd>, 0x<sd:ppfx>56, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vxorp<sd>, 0x<sd:ppfx>57, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vbroadcastf32x2, 0x6619, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } -vbroadcastf32x8, 0x661B, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } -vbroadcasti32x2, 0x6659, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vbroadcasti32x8, 0x665B, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } - -vbroadcastf64x2, 0x661A, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } -vbroadcasti64x2, 0x665A, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } - -vcvtpd2qq, 0x667B, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtpd2uqq, 0x6679, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } - -vcvtps2qq, 0x667B, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvtps2qq, 0x667B, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvtps2qq, 0x667B, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vcvtps2uqq, 0x6679, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvtps2uqq, 0x6679, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvtps2uqq, 0x6679, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|RegXMM|Dword|Unspecified|BaseIndex, RegYMM } - -vcvtqq2pd, 0xF3E6, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtuqq2pd, 0xF37A, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } - -vcvtqq2ps<Exy>, 0x5b, CpuAVX512DQ|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } - -vcvttpd2qq, 0x667A, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttpd2uqq, 0x6678, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } - -vcvttps2qq, 0x667A, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvttps2qq, 0x667A, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvttps2qq, 0x667A, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vcvttps2uqq, 0x6678, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvttps2uqq, 0x6678, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvttps2uqq, 0x6678, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } - -vcvtuqq2ps<Exy>, 0xf27a, CpuAVX512DQ|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } - -vextractf32x8, 0x661B, CpuAVX512DQ, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } -vextracti32x8, 0x663B, CpuAVX512DQ, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } -vinsertf32x8, 0x661A, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } -vinserti32x8, 0x663A, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } - -vpextr<dq>, 0x6616, CpuAVX512DQ|<dq:cpu64>, Modrm|EVex128|Space0F3A|<dq:vexw64>|Disp8MemShift|NoSuf, { Imm8, RegXMM, <dq:gpr>|Unspecified|BaseIndex } -vpinsr<dq>, 0x6622, CpuAVX512DQ|<dq:cpu64>, Modrm|EVex128|Space0F3A|VexVVVV|<dq:vexw64>|Disp8MemShift|NoSuf, { Imm8, <dq:gpr>|Unspecified|BaseIndex, RegXMM, RegXMM } - -vextractf64x2, 0x6619, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } -vextracti64x2, 0x6639, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } -vinsertf64x2, 0x6618, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vinserti64x2, 0x6638, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } - -vfpclassp<sd>, 0x6666, CpuAVX512DQ, Modrm|Masking=2|Space0F3A|<sd:vexw>|Broadcast|Disp8ShiftVL|NoSuf|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegMask } -vfpclassp<sd>, 0x6666, CpuAVX512DQ, Modrm|Masking=2|Space0F3A|<sd:vexw>|Broadcast|Disp8ShiftVL|NoSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|BaseIndex, RegMask } -vfpclassp<sd>z, 0x6666, CpuAVX512DQ, Modrm|EVex512|Masking=2|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf, { Imm8, RegZMM|<sd:elem>|Unspecified|BaseIndex, RegMask } -vfpclassp<sd>x, 0x6666, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=2|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=4|NoSuf, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegMask } -vfpclassp<sd>y, 0x6666, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=2|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|<sd:elem>|Unspecified|BaseIndex, RegMask } + x:AVX512VL:EVex128|Disp8MemShift=4::ATTSyntax:RegXMM|Unspecified|BaseIndex, + + y:AVX512VL:EVex256|Disp8MemShift=5::ATTSyntax:RegYMM|Unspecified|BaseIndex> + +kadd<bw>, 0x<bw:kpfx>4A, AVX512DQ, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } +ktest<bw>, 0x<bw:kpfx>99, AVX512DQ, Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } + +vandnp<sd>, 0x<sd:ppfx>55, AVX512DQ, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vandp<sd>, 0x<sd:ppfx>54, AVX512DQ, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vorp<sd>, 0x<sd:ppfx>56, AVX512DQ, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vxorp<sd>, 0x<sd:ppfx>57, AVX512DQ, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vbroadcastf32x2, 0x6619, AVX512DQ, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } +vbroadcastf32x8, 0x661B, AVX512DQ, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } +vbroadcasti32x2, 0x6659, AVX512DQ, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vbroadcasti32x8, 0x665B, AVX512DQ, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } + +vbroadcastf64x2, 0x661A, AVX512DQ, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } +vbroadcasti64x2, 0x665A, AVX512DQ, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } + +vcvtpd2qq, 0x667B, AVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtpd2uqq, 0x6679, AVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +vcvtps2qq, 0x667B, AVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtps2qq, 0x667B, AVX512DQ|AVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvtps2qq, 0x667B, AVX512DQ|AVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vcvtps2uqq, 0x6679, AVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtps2uqq, 0x6679, AVX512DQ|AVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvtps2uqq, 0x6679, AVX512DQ|AVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + +vcvtqq2pd, 0xF3E6, AVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtuqq2pd, 0xF37A, AVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +vcvtqq2ps<Exy>, 0x5b, AVX512DQ|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } + +vcvttpd2qq, 0x667A, AVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttpd2uqq, 0x6678, AVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +vcvttps2qq, 0x667A, AVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvttps2qq, 0x667A, AVX512DQ|AVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvttps2qq, 0x667A, AVX512DQ|AVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vcvttps2uqq, 0x6678, AVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvttps2uqq, 0x6678, AVX512DQ|AVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvttps2uqq, 0x6678, AVX512DQ|AVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + +vcvtuqq2ps<Exy>, 0xf27a, AVX512DQ|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } + +vextractf32x8, 0x661B, AVX512DQ, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vextracti32x8, 0x663B, AVX512DQ, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vinsertf32x8, 0x661A, AVX512DQ, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } +vinserti32x8, 0x663A, AVX512DQ, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } + +vpextr<dq>, 0x6616, AVX512DQ|<dq:cpu64>, Modrm|EVex128|Space0F3A|<dq:vexw64>|Disp8MemShift|NoSuf, { Imm8, RegXMM, <dq:gpr>|Unspecified|BaseIndex } +vpinsr<dq>, 0x6622, AVX512DQ|<dq:cpu64>, Modrm|EVex128|Space0F3A|VexVVVV|<dq:vexw64>|Disp8MemShift|NoSuf, { Imm8, <dq:gpr>|Unspecified|BaseIndex, RegXMM, RegXMM } + +vextractf64x2, 0x6619, AVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } +vextracti64x2, 0x6639, AVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } +vinsertf64x2, 0x6618, AVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vinserti64x2, 0x6638, AVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } + +vfpclassp<sd>, 0x6666, AVX512DQ, Modrm|Masking=2|Space0F3A|<sd:vexw>|Broadcast|Disp8ShiftVL|NoSuf|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegMask } +vfpclassp<sd>, 0x6666, AVX512DQ, Modrm|Masking=2|Space0F3A|<sd:vexw>|Broadcast|Disp8ShiftVL|NoSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|BaseIndex, RegMask } +vfpclassp<sd>z, 0x6666, AVX512DQ, Modrm|EVex512|Masking=2|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf, { Imm8, RegZMM|<sd:elem>|Unspecified|BaseIndex, RegMask } +vfpclassp<sd>x, 0x6666, AVX512DQ|AVX512VL, Modrm|EVex128|Masking=2|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=4|NoSuf, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegMask } +vfpclassp<sd>y, 0x6666, AVX512DQ|AVX512VL, Modrm|EVex256|Masking=2|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|<sd:elem>|Unspecified|BaseIndex, RegMask } vfpclasss<sdh>, 0x<sdh:pfx>67, <sdh:cpudq>, Modrm|EVexLIG|Masking=2|Space0F3A|<sdh:vexw>|Disp8MemShift|NoSuf, { Imm8, RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegMask } -vpmov<dq>2m, 0xf339, CpuAVX512DQ, Modrm|EVexDYN|Space0F38|<dq:vexw>|NoSuf, { RegXMM|RegYMM|RegZMM, RegMask } -vpmovm2<dq>, 0xf338, CpuAVX512DQ, Modrm|EVexDYN|Space0F38|<dq:vexw>|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } +vpmov<dq>2m, 0xf339, AVX512DQ, Modrm|EVexDYN|Space0F38|<dq:vexw>|NoSuf, { RegXMM|RegYMM|RegZMM, RegMask } +vpmovm2<dq>, 0xf338, AVX512DQ, Modrm|EVexDYN|Space0F38|<dq:vexw>|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } -vpmullq, 0x6640, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmullq, 0x6640, AVX512DQ, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vrangep<sd>, 0x6650, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vranges<sd>, 0x6651, CpuAVX512DQ, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } +vrangep<sd>, 0x6650, AVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vranges<sd>, 0x6651, AVX512DQ, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } vreducep<sdh>, 0x<sdh:pfx>56, <sdh:cpudq>, Modrm|Masking=3|Space0F3A|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vreduces<sdh>, 0x<sdh:pfx>57, <sdh:cpudq>, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } @@ -2788,539 +2803,539 @@ vreduces<sdh>, 0x<sdh:pfx>57, <sdh:cpudq>, Modrm|EVexLIG|Masking=3|Space0F3A|Vex // CLWB instructions. -clwb, 0x660fae/6, CpuCLWB, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +clwb, 0x660fae/6, CLWB, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } // CLWB instructions end. // AVX512IFMA instructions -vpmadd52huq, 0x66B5, CpuAVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmadd52luq, 0x66B4, CpuAVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmadd52huq, 0x66B5, AVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmadd52luq, 0x66B4, AVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512IFMA instructions end // AVX-IFMA instructions. -vpmadd52huq, 0x66B5, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpmadd52luq, 0x66B4, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpmadd52huq, 0x66B5, AVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpmadd52luq, 0x66B4, AVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } // AVX-IFMA instructions end. // AVX512VBMI instructions -vpmultishiftqb, 0x6683, CpuAVX512VBMI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmultishiftqb, 0x6683, AVX512VBMI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512VBMI instructions end // AVX512_4FMAPS instructions -v4fmaddps, 0xf29a, CpuAVX512_4FMAPS, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } -v4fnmaddps, 0xf2aa, CpuAVX512_4FMAPS, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } -v4fmaddss, 0xf29b, CpuAVX512_4FMAPS, Modrm|EVex=4|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } -v4fnmaddss, 0xf2ab, CpuAVX512_4FMAPS, Modrm|EVex=4|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } +v4fmaddps, 0xf29a, AVX512_4FMAPS, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +v4fnmaddps, 0xf2aa, AVX512_4FMAPS, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +v4fmaddss, 0xf29b, AVX512_4FMAPS, Modrm|EVex=4|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } +v4fnmaddss, 0xf2ab, AVX512_4FMAPS, Modrm|EVex=4|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } // AVX512_4FMAPS instructions end // AVX512_4VNNIW instructions -vp4dpwssd, 0xf252, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } -vp4dpwssds, 0xf253, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vp4dpwssd, 0xf252, AVX512_4VNNIW, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vp4dpwssds, 0xf253, AVX512_4VNNIW, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } // AVX512_4VNNIW instructions end // AVX512_VPOPCNTDQ instructions -vpopcnt<dq>, 0x6655, CpuAVX512_VPOPCNTDQ, Modrm|Masking=3|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpopcnt<dq>, 0x6655, AVX512_VPOPCNTDQ, Modrm|Masking=3|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } // AVX512_VPOPCNTDQ instructions end // AVX512_VBMI2 instructions -vpcompressb, 0x6663, CpuAVX512_VBMI2, Modrm|MaskingMorZ|Space0F38|VexW=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vpcompressw, 0x6663, CpuAVX512_VBMI2, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vpcompressb, 0x6663, AVX512_VBMI2, Modrm|MaskingMorZ|Space0F38|VexW=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vpcompressw, 0x6663, AVX512_VBMI2, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vpexpandb, 0x6662, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexW=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpexpandw, 0x6662, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpexpandb, 0x6662, AVX512_VBMI2, Modrm|Masking=3|Space0F38|VexW=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpexpandw, 0x6662, AVX512_VBMI2, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpshldv<dq>, 0x6671, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshldvw, 0x6670, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshldv<dq>, 0x6671, AVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshldvw, 0x6670, AVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrdv<dq>, 0x6673, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrdvw, 0x6672, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrdv<dq>, 0x6673, AVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrdvw, 0x6672, AVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshld<dq>, 0x6671, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshldw, 0x6670, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshld<dq>, 0x6671, AVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshldw, 0x6670, AVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrd<dq>, 0x6673, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrdw, 0x6672, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrd<dq>, 0x6673, AVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrdw, 0x6672, AVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512_VBMI2 instructions end // AVX512_VNNI instructions -vpdpbusd, 0x6650, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpdpwssd, 0x6652, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpdpbusd, 0x6650, AVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpdpwssd, 0x6652, AVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpdpbusds, 0x6651, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpdpwssds, 0x6653, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpdpbusds, 0x6651, AVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpdpwssds, 0x6653, AVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512_VNNI instructions end // AVX_VNNI instructions -vpdpbusd, 0x6650, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpwssd, 0x6652, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbusd, 0x6650, AVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpwssd, 0x6652, AVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpbusds, 0x6651, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpwssds, 0x6653, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbusds, 0x6651, AVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpwssds, 0x6653, AVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } // AVX_VNNI instructions end // AVX-VNNI-INT8 instructions. -vpdpbuud, 0x50, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpbuuds, 0x51, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpbssd, 0xf250, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpbssds, 0xf251, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpbsud, 0xf350, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpdpbsuds, 0xf351, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbuud, 0x50, AVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbuuds, 0x51, AVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbssd, 0xf250, AVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbssds, 0xf251, AVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbsud, 0xf350, AVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpdpbsuds, 0xf351, AVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } // AVX-VNNI-INT8 instructions end. // AVX512_BITALG instructions -vpopcnt<bw>, 0x6654, CpuAVX512_BITALG, Modrm|Masking=3|Space0F38|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpopcnt<bw>, 0x6654, AVX512_BITALG, Modrm|Masking=3|Space0F38|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpshufbitqmb, 0x668f, CpuAVX512_BITALG, Modrm|Masking=2|Space0F38|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpshufbitqmb, 0x668f, AVX512_BITALG, Modrm|Masking=2|Space0F38|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } // AVX512_BITALG instructions end // AVX512 + GFNI instructions -vgf2p8affineinvqb, 0x66cf, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vgf2p8affineqb, 0x66ce, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vgf2p8mulb, 0x66cf, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vgf2p8affineinvqb, 0x66cf, GFNI|AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vgf2p8affineqb, 0x66ce, GFNI|AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vgf2p8mulb, 0x66cf, GFNI|AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512 + GFNI instructions end // AVX512 + VAES instructions -vaesdec, 0x66de, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vaesdeclast, 0x66df, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vaesenc, 0x66dc, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vaesenclast, 0x66dd, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vaesdec, 0x66de, VAES|AVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vaesdeclast, 0x66df, VAES|AVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vaesenc, 0x66dc, VAES|AVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vaesenclast, 0x66dd, VAES|AVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512 + VAES instructions end // AVX512 + VPCLMULQDQ instructions -vpclmulqdq, 0x6644, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpclmullqlqdq, 0x6644/0x00, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpclmulhqlqdq, 0x6644/0x01, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpclmullqhqdq, 0x6644/0x10, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpclmulhqhqdq, 0x6644/0x11, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpclmulqdq, 0x6644, VPCLMULQDQ|AVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpclmullqlqdq, 0x6644/0x00, VPCLMULQDQ|AVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpclmulhqlqdq, 0x6644/0x01, VPCLMULQDQ|AVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpclmullqhqdq, 0x6644/0x10, VPCLMULQDQ|AVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpclmulhqhqdq, 0x6644/0x11, VPCLMULQDQ|AVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512 + VPCLMULQDQ instructions end // INVLPGB instructions -invlpgb, 0xf01fe, CpuINVLPGB, NoSuf, {} -invlpgb, 0xf01fe, CpuINVLPGB, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } +invlpgb, 0xf01fe, INVLPGB, NoSuf, {} +invlpgb, 0xf01fe, INVLPGB, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } // INVLPGB instructions end // TLBSYNC instructions -tlbsync, 0xf01ff, CpuTLBSYNC, NoSuf, {} +tlbsync, 0xf01ff, TLBSYNC, NoSuf, {} // TLBSYNC instructions end // CLZERO instructions -clzero, 0xf01fc, CpuCLZERO, NoSuf, {} -clzero, 0xf01fc, CpuCLZERO, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } +clzero, 0xf01fc, CLZERO, NoSuf, {} +clzero, 0xf01fc, CLZERO, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } // CLZERO instructions end // MONITORX/MWAITX instructions -monitorx, 0xf01fa, CpuMWAITX, NoSuf, {} -monitorx, 0xf01fa, CpuMWAITX, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } +monitorx, 0xf01fa, MWAITX, NoSuf, {} +monitorx, 0xf01fa, MWAITX, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } // The 64-bit form exists only for compatibility with older gas. -monitorx, 0xf01fa, CpuMWAITX|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } +monitorx, 0xf01fa, MWAITX|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } -mwaitx, 0xf01fb, CpuMWAITX, NoSuf, {} +mwaitx, 0xf01fb, MWAITX, NoSuf, {} // The 64-bit form exists only for compatibility with older gas. -mwaitx, 0xf01fb, CpuMWAITX, CheckRegSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword, RegB|Dword|Qword } +mwaitx, 0xf01fb, MWAITX, CheckRegSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword, RegB|Dword|Qword } // MONITORX/MWAITX instructions end // OSPKE instructions. -rdpkru, 0xf01ee, CpuOSPKE, NoSuf, {} -wrpkru, 0xf01ef, CpuOSPKE, NoSuf, {} +rdpkru, 0xf01ee, OSPKE, NoSuf, {} +wrpkru, 0xf01ef, OSPKE, NoSuf, {} // OSPKE instructions end. // RDPID instructions. -rdpid, 0xf30fc7/7, CpuRDPID|CpuNo64, Modrm|IgnoreSize|NoSuf, { Reg32 } -rdpid, 0xf30fc7/7, CpuRDPID|Cpu64, Modrm|NoSuf|NoRex64, { Reg64 } +rdpid, 0xf30fc7/7, RDPID|No64, Modrm|IgnoreSize|NoSuf, { Reg32 } +rdpid, 0xf30fc7/7, RDPID|x64, Modrm|NoSuf|NoRex64, { Reg64 } // RDPID instructions end. // PTWRITE instructions. -ptwrite, 0xf30fae/4, CpuPTWRITE|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Unspecified|BaseIndex } -ptwrite, 0xf30fae/4, CpuPTWRITE|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex } +ptwrite, 0xf30fae/4, PTWRITE|No64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Unspecified|BaseIndex } +ptwrite, 0xf30fae/4, PTWRITE|x64, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex } // PTWRITE instructions end. // CET instructions. -incsspd, 0xf30fae/5, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32 } -incsspq, 0xf30fae/5, CpuSHSTK|Cpu64, Modrm|NoSuf, { Reg64 } -rdsspd, 0xf30f1e/1, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32 } -rdsspq, 0xf30f1e/1, CpuSHSTK|Cpu64, Modrm|NoSuf, { Reg64 } -saveprevssp, 0xf30f01ea, CpuSHSTK, NoSuf, {} -rstorssp, 0xf30f01/5, CpuSHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } -wrssd, 0x0f38f6, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } -wrssq, 0x0f38f6, CpuSHSTK|Cpu64, Modrm|NoSuf|Size64, { Reg64, Qword|Unspecified|BaseIndex } -wrussd, 0x660f38f5, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } -wrussq, 0x660f38f5, CpuSHSTK|Cpu64, Modrm|NoSuf, { Reg64, Qword|Unspecified|BaseIndex } -setssbsy, 0xf30f01e8, CpuSHSTK, NoSuf, {} -clrssbsy, 0xf30fae/6, CpuSHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } -endbr64, 0xf30f1efa, CpuIBT, NoSuf, {} -endbr32, 0xf30f1efb, CpuIBT, NoSuf, {} +incsspd, 0xf30fae/5, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32 } +incsspq, 0xf30fae/5, SHSTK|x64, Modrm|NoSuf, { Reg64 } +rdsspd, 0xf30f1e/1, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32 } +rdsspq, 0xf30f1e/1, SHSTK|x64, Modrm|NoSuf, { Reg64 } +saveprevssp, 0xf30f01ea, SHSTK, NoSuf, {} +rstorssp, 0xf30f01/5, SHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } +wrssd, 0x0f38f6, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } +wrssq, 0x0f38f6, SHSTK|x64, Modrm|NoSuf|Size64, { Reg64, Qword|Unspecified|BaseIndex } +wrussd, 0x660f38f5, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } +wrussq, 0x660f38f5, SHSTK|x64, Modrm|NoSuf, { Reg64, Qword|Unspecified|BaseIndex } +setssbsy, 0xf30f01e8, SHSTK, NoSuf, {} +clrssbsy, 0xf30fae/6, SHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } +endbr64, 0xf30f1efa, IBT, NoSuf, {} +endbr32, 0xf30f1efb, IBT, NoSuf, {} // notrack prefix -notrack, 0x3e, CpuIBT, NoSuf|IsPrefix, {} +notrack, 0x3e, IBT, NoSuf|IsPrefix, {} // CET instructions end. // WBNOINVD instruction. -wbnoinvd, 0xf30f09, CpuWBNOINVD, NoSuf, {} +wbnoinvd, 0xf30f09, WBNOINVD, NoSuf, {} // WBNOINVD instruction end. // PCONFIG instruction. -pconfig, 0x0f01c5, CpuPCONFIG, NoSuf, {} +pconfig, 0x0f01c5, PCONFIG, NoSuf, {} // PCONFIG instruction end. // WAITPKG instructions. -umonitor, 0xf30fae/6, CpuWAITPKG, Modrm|AddrPrefixOpReg|NoSuf, { Reg16|Reg32|Reg64 } -tpause, 0x660fae/6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32 } -tpause, 0x660fae/6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32, RegD|Dword, Acc|Dword } -umwait, 0xf20fae/6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32 } -umwait, 0xf20fae/6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32, RegD|Dword, Acc|Dword } +umonitor, 0xf30fae/6, WAITPKG, Modrm|AddrPrefixOpReg|NoSuf, { Reg16|Reg32|Reg64 } +tpause, 0x660fae/6, WAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32 } +tpause, 0x660fae/6, WAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32, RegD|Dword, Acc|Dword } +umwait, 0xf20fae/6, WAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32 } +umwait, 0xf20fae/6, WAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32, RegD|Dword, Acc|Dword } // WAITPKG instructions end. // CLDEMOTE instructions. -cldemote, 0x0f1c/0, CpuCLDEMOTE, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +cldemote, 0x0f1c/0, CLDEMOTE, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } // CLDEMOTE instructions end. // MOVDIR[I,64B] instructions. -movdiri, 0xf38f9, CpuMOVDIRI, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } -movdir64b, 0x660f38f8, CpuMOVDIR64B, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movdiri, 0xf38f9, MOVDIRI, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +movdir64b, 0x660f38f8, MOVDIR64B, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // MOVEDIR instructions end. // AVX512_BF16 instructions. -vcvtne2ps2bf16, 0xf272, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vcvtne2ps2bf16, 0xf272, AVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vcvtneps2bf16<Exy>, 0xf372, CpuAVX512_BF16|<Exy:vl>, Modrm|Space0F38|<Exy:attr>|Masking=3|VexW0|Broadcast|NoSuf, { <Exy:src>|Dword, <Exy:dst> } +vcvtneps2bf16<Exy>, 0xf372, AVX512_BF16|<Exy:vl>, Modrm|Space0F38|<Exy:attr>|Masking=3|VexW0|Broadcast|NoSuf, { <Exy:src>|Dword, <Exy:dst> } -vdpbf16ps, 0xf352, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vdpbf16ps, 0xf352, AVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512_BF16 instructions end. // AVX-NE-CONVERT instructions. -vbcstnebf162ps, 0xf3b1, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|NoSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM } -vbcstnesh2ps, 0x66b1, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|NoSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM } -vcvtneebf162ps, 0xf3b0, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } -vcvtneeph2ps, 0x66b0, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } -vcvtneobf162ps, 0xf2b0, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } -vcvtneoph2ps, 0xb0, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } -vcvtneps2bf16<Vxy>, 0xf372, CpuAVX_NE_CONVERT, Modrm|<Vxy:vex>|Space0F38|VexW0|NoSuf|<Vxy:syntax>, { <Vxy:dst>, RegXMM } +vbcstnebf162ps, 0xf3b1, AVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|NoSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM } +vbcstnesh2ps, 0x66b1, AVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|NoSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM } +vcvtneebf162ps, 0xf3b0, AVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } +vcvtneeph2ps, 0x66b0, AVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } +vcvtneobf162ps, 0xf2b0, AVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } +vcvtneoph2ps, 0xb0, AVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } +vcvtneps2bf16<Vxy>, 0xf372, AVX_NE_CONVERT, Modrm|<Vxy:vex>|Space0F38|VexW0|NoSuf|<Vxy:syntax>, { <Vxy:dst>, RegXMM } // AVX-NE-CONVERT instructions end. // ENQCMD instructions. -enqcmd, 0xf20f38f8, CpuENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -enqcmds, 0xf30f38f8, CpuENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +enqcmd, 0xf20f38f8, ENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +enqcmds, 0xf30f38f8, ENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // ENQCMD instructions end. // VP2INTERSECT instructions. -vp2intersect<dq>, 0xf268, CpuAVX512_VP2INTERSECT, Modrm|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vp2intersect<dq>, 0xf268, AVX512_VP2INTERSECT, Modrm|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } // VP2INTERSECT instructions end. // MCOMMIT instruction -mcommit, 0xf30f01fa, CpuMCOMMIT, NoSuf, {} +mcommit, 0xf30f01fa, MCOMMIT, NoSuf, {} // MCOMMIT instruction end // SNP instructions -psmash, 0xf30f01ff, CpuSNP|Cpu64, NoSuf, {} -psmash, 0xf30f01ff, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } -pvalidate, 0xf20f01ff, CpuSNP, NoSuf, {} -pvalidate, 0xf20f01ff, CpuSNP, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } -rmpupdate, 0xf20f01fe, CpuSNP|Cpu64, NoSuf, {} -rmpupdate, 0xf20f01fe, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword } -rmpadjust, 0xf30f01fe, CpuSNP|Cpu64, NoSuf, {} -rmpadjust, 0xf30f01fe, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } +psmash, 0xf30f01ff, SNP|x64, NoSuf, {} +psmash, 0xf30f01ff, SNP|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } +pvalidate, 0xf20f01ff, SNP, NoSuf, {} +pvalidate, 0xf20f01ff, SNP, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } +rmpupdate, 0xf20f01fe, SNP|x64, NoSuf, {} +rmpupdate, 0xf20f01fe, SNP|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword } +rmpadjust, 0xf30f01fe, SNP|x64, NoSuf, {} +rmpadjust, 0xf30f01fe, SNP|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } // The single-operand forms exist only for compatibility with older gas. -pvalidate, 0xf20f01ff, CpuSNP, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } -rmpupdate, 0xf20f01fe, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } -rmpadjust, 0xf30f01fe, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } +pvalidate, 0xf20f01ff, SNP, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } +rmpupdate, 0xf20f01fe, SNP|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } +rmpadjust, 0xf30f01fe, SNP|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } // SNP instructions end // RMPQUERY instruction -rmpquery, 0xf30f01fd, CpuRMPQUERY|Cpu64, NoSuf, {} -rmpquery, 0xf30f01fd, CpuRMPQUERY|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } +rmpquery, 0xf30f01fd, RMPQUERY|x64, NoSuf, {} +rmpquery, 0xf30f01fd, RMPQUERY|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } // RMPQUERY instruction end // RDPRU instruction -rdpru, 0x0f01fd, CpuRDPRU, NoSuf, {} +rdpru, 0x0f01fd, RDPRU, NoSuf, {} // RDPRU instruction end // SERIALIZE instruction. -serialize, 0x0f01e8, CpuSERIALIZE, NoSuf, {} +serialize, 0x0f01e8, SERIALIZE, NoSuf, {} // SERIALIZE instruction end. // TSXLDTRK instructions. -xsusldtrk, 0xf20f01e8, CpuTSXLDTRK, NoSuf, {} -xresldtrk, 0xf20f01e9, CpuTSXLDTRK, NoSuf, {} +xsusldtrk, 0xf20f01e8, TSXLDTRK, NoSuf, {} +xresldtrk, 0xf20f01e9, TSXLDTRK, NoSuf, {} // TSXLDTRK instructions end. // AMX instructions. -ldtilecfg, 0x49, CpuAMX_TILE|Cpu64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } -sttilecfg, 0x6649, CpuAMX_TILE|Cpu64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } +ldtilecfg, 0x49, AMX_TILE|x64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } +sttilecfg, 0x6649, AMX_TILE|x64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } -tdpbf16ps, 0xf35c, CpuAMX_BF16|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } -tdpfp16ps, 0xf25c, CpuAMX_FP16|Cpu64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } -tdpbssd, 0xf25e, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } -tdpbuud, 0x5e, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } -tdpbusd, 0x665e, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } -tdpbsud, 0xf35e, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +tdpbf16ps, 0xf35c, AMX_BF16|x64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +tdpfp16ps, 0xf25c, AMX_FP16|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +tdpbssd, 0xf25e, AMX_INT8|x64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +tdpbuud, 0x5e, AMX_INT8|x64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +tdpbusd, 0x665e, AMX_INT8|x64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } +tdpbsud, 0xf35e, AMX_INT8|x64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } -tileloadd, 0xf24b, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } -tileloaddt1, 0x664b, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } -tilestored, 0xf34b, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex } +tileloadd, 0xf24b, AMX_TILE|x64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } +tileloaddt1, 0x664b, AMX_TILE|x64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } +tilestored, 0xf34b, AMX_TILE|x64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex } -tilerelease, 0x49c0, CpuAMX_TILE|Cpu64, Vex128|Space0F38|VexW0|NoSuf, {} +tilerelease, 0x49c0, AMX_TILE|x64, Vex128|Space0F38|VexW0|NoSuf, {} -tilezero, 0xf249, CpuAMX_TILE|Cpu64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM } +tilezero, 0xf249, AMX_TILE|x64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM } // AMX instructions end. // KEYLOCKER instructions. -loadiwkey, 0xf30f38dc, CpuKL, Load|Modrm|NoSuf, { RegXMM, RegXMM } -encodekey128, 0xf30f38fa, CpuKL, Modrm|NoSuf, { Reg32, Reg32 } -encodekey256, 0xf30f38fb, CpuKL, Modrm|NoSuf, { Reg32, Reg32 } -aesenc128kl, 0xf30f38dc, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } -aesdec128kl, 0xf30f38dd, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } -aesenc256kl, 0xf30f38de, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } -aesdec256kl, 0xf30f38df, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } -aesencwide128kl, 0xf30f38d8/0, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } -aesdecwide128kl, 0xf30f38d8/1, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } -aesencwide256kl, 0xf30f38d8/2, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } -aesdecwide256kl, 0xf30f38d8/3, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +loadiwkey, 0xf30f38dc, KL, Load|Modrm|NoSuf, { RegXMM, RegXMM } +encodekey128, 0xf30f38fa, KL, Modrm|NoSuf, { Reg32, Reg32 } +encodekey256, 0xf30f38fb, KL, Modrm|NoSuf, { Reg32, Reg32 } +aesenc128kl, 0xf30f38dc, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesdec128kl, 0xf30f38dd, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesenc256kl, 0xf30f38de, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesdec256kl, 0xf30f38df, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesencwide128kl, 0xf30f38d8/0, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +aesdecwide128kl, 0xf30f38d8/1, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +aesencwide256kl, 0xf30f38d8/2, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +aesdecwide256kl, 0xf30f38d8/3, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } // KEYLOCKER instructions end. // TDX instructions. -tdcall, 0x660f01cc, CpuTDX, NoSuf, {} -seamret, 0x660f01cd, CpuTDX|Cpu64, NoSuf, {} -seamops, 0x660f01ce, CpuTDX|Cpu64, NoSuf, {} -seamcall, 0x660f01cf, CpuTDX|Cpu64, NoSuf, {} +tdcall, 0x660f01cc, TDX, NoSuf, {} +seamret, 0x660f01cd, TDX|x64, NoSuf, {} +seamops, 0x660f01ce, TDX|x64, NoSuf, {} +seamcall, 0x660f01cf, TDX|x64, NoSuf, {} // TDX instructions end. // UINTR instructions. -uiret, 0xf30f01ec, CpuUINTR|Cpu64, NoSuf, {} -clui, 0xf30f01ee, CpuUINTR|Cpu64, NoSuf, {} -stui, 0xf30f01ef, CpuUINTR|Cpu64, NoSuf, {} -testui, 0xf30f01ed, CpuUINTR|Cpu64, NoSuf, {} -senduipi, 0xf30fc7/6, CpuUINTR|Cpu64, Modrm|NoSuf|NoRex64, { Reg64 } +uiret, 0xf30f01ec, UINTR|x64, NoSuf, {} +clui, 0xf30f01ee, UINTR|x64, NoSuf, {} +stui, 0xf30f01ef, UINTR|x64, NoSuf, {} +testui, 0xf30f01ed, UINTR|x64, NoSuf, {} +senduipi, 0xf30fc7/6, UINTR|x64, Modrm|NoSuf|NoRex64, { Reg64 } // UINTR instructions end. // HRESET instructions. -hreset, 0xf30f3af0c0, CpuHRESET, NoSuf, { Imm8 } +hreset, 0xf30f3af0c0, HRESET, NoSuf, { Imm8 } // HRESET instructions end. // FP16 (HFNI) instructions. -vfcmaddcph, 0xf256, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfcmaddcsh, 0xf257, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vfcmaddcph, 0xf256, AVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfcmaddcsh, 0xf257, AVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vfmaddcph, 0xf356, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmaddcsh, 0xf357, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vfmaddcph, 0xf356, AVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfmaddcsh, 0xf357, AVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vfcmulcph, 0xf2d6, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfcmulcsh, 0xf2d7, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vfcmulcph, 0xf2d6, AVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfcmulcsh, 0xf2d7, AVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vfmulcph, 0xf3d6, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmulcsh, 0xf3d7, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vfmulcph, 0xf3d6, AVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfmulcsh, 0xf3d7, AVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcmp<frel>ph, 0xc2/0x<frel:imm>, CpuAVX512_FP16, Modrm|Masking=2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vcmpph, 0xc2, CpuAVX512_FP16, Modrm|Masking=2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vcmp<frel>ph, 0xc2/0x<frel:imm>, AVX512_FP16, Modrm|Masking=2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vcmpph, 0xc2, AVX512_FP16, Modrm|Masking=2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vcmp<frel>sh, 0xf3c2/0x<frel:imm>, CpuAVX512_FP16, Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } -vcmpsh, 0xf3c2, CpuAVX512_FP16, Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } +vcmp<frel>sh, 0xf3c2/0x<frel:imm>, AVX512_FP16, Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } +vcmpsh, 0xf3c2, AVX512_FP16, Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } -vcvtdq2ph<Exy>, 0x5b, CpuAVX512_FP16|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> } -vcvtudq2ph<Exy>, 0xf27a, CpuAVX512_FP16|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> } +vcvtdq2ph<Exy>, 0x5b, AVX512_FP16|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> } +vcvtudq2ph<Exy>, 0xf27a, AVX512_FP16|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> } -vcvtqq2ph<xyz>, 0x5b, CpuAVX512_FP16|<xyz:vl>, Modrm|<xyz:attr>|Masking=3|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM } -vcvtuqq2ph<xyz>, 0xf27a, CpuAVX512_FP16|<xyz:vl>, Modrm|<xyz:attr>|Masking=3|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM } +vcvtqq2ph<xyz>, 0x5b, AVX512_FP16|<xyz:vl>, Modrm|<xyz:attr>|Masking=3|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM } +vcvtuqq2ph<xyz>, 0xf27a, AVX512_FP16|<xyz:vl>, Modrm|<xyz:attr>|Masking=3|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM } -vcvtpd2ph<xyz>, 0x665a, CpuAVX512_FP16|<xyz:vl>, Modrm|<xyz:attr>|Masking=3|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM } +vcvtpd2ph<xyz>, 0x665a, AVX512_FP16|<xyz:vl>, Modrm|<xyz:attr>|Masking=3|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM } -vcvtps2phx<Exy>, 0x661d, CpuAVX512_FP16|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> } +vcvtps2phx<Exy>, 0x661d, AVX512_FP16|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> } -vcvtw2ph, 0xf37d, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtuw2ph, 0xf27d, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtw2ph, 0xf37d, AVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtuw2ph, 0xf27d, AVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtph2dq, 0x665b, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2dq, 0x665b, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvtph2dq, 0x665b, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2dq, 0x665b, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvtph2dq, 0x665b, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvtph2dq, 0x665b, AVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2udq, 0x79, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2udq, 0x79, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvtph2udq, 0x79, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2udq, 0x79, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvtph2udq, 0x79, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvtph2udq, 0x79, AVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2qq, 0x667b, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvtph2qq, 0x667b, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvtph2qq, 0x667b, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2qq, 0x667b, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvtph2qq, 0x667b, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvtph2qq, 0x667b, AVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2uqq, 0x6679, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvtph2uqq, 0x6679, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvtph2uqq, 0x6679, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2uqq, 0x6679, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvtph2uqq, 0x6679, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvtph2uqq, 0x6679, AVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2pd, 0x5a, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvtph2pd, 0x5a, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvtph2pd, 0x5a, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2pd, 0x5a, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvtph2pd, 0x5a, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvtph2pd, 0x5a, AVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2w, 0x667d, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtph2uw, 0x7d, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtph2w, 0x667d, AVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtph2uw, 0x7d, AVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtsd2sh, 0xf25a, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtss2sh, 0x1d, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=2|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsd2sh, 0xf25a, AVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtss2sh, 0x1d, AVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=2|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sh, 0xf32a, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sh, 0xf32a, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sh, 0xf32a, AVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sh, 0xf32a, AVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sh, 0xf37b, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sh, 0xf37b, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sh, 0xf37b, AVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sh, 0xf37b, AVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsh2sd, 0xf35a, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsh2ss, 0x13, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsh2sd, 0xf35a, AVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsh2ss, 0x13, AVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsh2si, 0xf32d, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } +vcvtsh2si, 0xf32d, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } -vcvttph2dq, 0xf35b, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvttph2dq, 0xf35b, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvttph2dq, 0xf35b, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvttph2dq, 0xf35b, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvttph2dq, 0xf35b, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvttph2dq, 0xf35b, AVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvttph2udq, 0x78, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvttph2udq, 0x78, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvttph2udq, 0x78, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvttph2udq, 0x78, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvttph2udq, 0x78, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvttph2udq, 0x78, AVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvttph2qq, 0x667a, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvttph2qq, 0x667a, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvttph2qq, 0x667a, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvttph2qq, 0x667a, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvttph2qq, 0x667a, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvttph2qq, 0x667a, AVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvttph2uqq, 0x6678, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvttph2uqq, 0x6678, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvttph2uqq, 0x6678, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvttph2uqq, 0x6678, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvttph2uqq, 0x6678, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvttph2uqq, 0x6678, AVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2psx, 0x6613, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2psx, 0x6613, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvtph2psx, 0x6613, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2psx, 0x6613, AVX512_FP16|AVX512VL, Modrm|EVex128|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvtph2psx, 0x6613, AVX512_FP16|AVX512VL, Modrm|EVex256|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvtph2psx, 0x6613, AVX512_FP16, Modrm|EVex512|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvttph2w, 0x667c, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttph2uw, 0x7c, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttph2w, 0x667c, AVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttph2uw, 0x7c, AVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttsh2si, 0xf32c, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } +vcvttsh2si, 0xf32c, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } -vfpclassph<xyz>, 0x66, CpuAVX512_FP16|<xyz:vl>, Modrm|<xyz:attr>|Masking=2|Space0F3A|VexW0|Broadcast|NoSuf|<xyz:att>, { Imm8, <xyz:src>|Word, RegMask } +vfpclassph<xyz>, 0x66, AVX512_FP16|<xyz:vl>, Modrm|<xyz:attr>|Masking=2|Space0F3A|VexW0|Broadcast|NoSuf|<xyz:att>, { Imm8, <xyz:src>|Word, RegMask } -vmovw, 0x666e, CpuAVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|NoSuf, { Word|Unspecified|BaseIndex, RegXMM } -vmovw, 0x667e, CpuAVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|NoSuf, { RegXMM, Reg32 } +vmovw, 0x666e, AVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|NoSuf, { Word|Unspecified|BaseIndex, RegXMM } +vmovw, 0x667e, AVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|NoSuf, { RegXMM, Reg32 } -vrcpph, 0x664c, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrcpph, 0x664c, AVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrcpsh, 0x664d, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vrcpsh, 0x664d, AVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } -vrsqrtph, 0x664e, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrsqrtph, 0x664e, AVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrsqrtsh, 0x664f, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vrsqrtsh, 0x664f, AVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } // FP16 (HFNI) instructions end. // PREFETCHI instructions. -prefetchit0, 0xf18/7, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } -prefetchit1, 0xf18/6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +prefetchit0, 0xf18/7, PREFETCHI|x64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } +prefetchit1, 0xf18/6, PREFETCHI|x64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } // PREFETCHI instructions end. // CMPCCXADD instructions. -cmp<cc>xadd, 0x66e<cc:opc>, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVVV|CheckRegSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +cmp<cc>xadd, 0x66e<cc:opc>, CMPCCXADD|x64, Modrm|Vex|Space0F38|VexVVVV|CheckRegSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } // CMPCCXADD instructions end. // WRMSRNS instruction. -wrmsrns, 0x0f01c6, CpuWRMSRNS, NoSuf, {} +wrmsrns, 0x0f01c6, WRMSRNS, NoSuf, {} // WRMSRNS instruction end. // MSRLIST instructions. -rdmsrlist, 0xf20f01c6, CpuMSRLIST|Cpu64, NoSuf, {} -wrmsrlist, 0xf30f01c6, CpuMSRLIST|Cpu64, NoSuf, {} +rdmsrlist, 0xf20f01c6, MSRLIST|x64, NoSuf, {} +wrmsrlist, 0xf30f01c6, MSRLIST|x64, NoSuf, {} // MSRLIST instructions end. // RAO-INT instructions. -aadd, 0xf38fc, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } -aand, 0x660f38fc, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } -aor, 0xf20f38fc, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } -axor, 0xf30f38fc, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +aadd, 0xf38fc, RAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +aand, 0x660f38fc, RAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +aor, 0xf20f38fc, RAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +axor, 0xf30f38fc, RAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } // RAO-INT instructions end. |