diff options
| author | Jan Beulich <jbeulich@suse.com> | 2024-05-17 10:52:53 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2024-05-17 10:52:53 +0200 |
| commit | 44fc9616c2e74396395f60c9a601317e4c4c4733 (patch) | |
| tree | 1b39bd961995e2c63137db1e5f893a554adb8332 | |
| parent | 132a0b0d77fe11db4b03182d3317ae204491a6a9 (diff) | |
| download | gdb-44fc9616c2e74396395f60c9a601317e4c4c4733.zip gdb-44fc9616c2e74396395f60c9a601317e4c4c4733.tar.gz gdb-44fc9616c2e74396395f60c9a601317e4c4c4733.tar.bz2 | |
aarch64: correct SVE2.1 ld2q (scalar plus scalar)
It's opcode was wrong, as was e.g. easily visible from the inappropriate
testcase expectation.
| -rw-r--r-- | gas/testsuite/gas/aarch64/sve2p1-1.d | 2 | ||||
| -rw-r--r-- | opcodes/aarch64-dis-2.c | 31 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 2 |
3 files changed, 22 insertions, 13 deletions
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d index 6f46433..b93920c 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-1.d +++ b/gas/testsuite/gas/aarch64/sve2p1-1.d @@ -93,7 +93,7 @@ .*: a49ef000 ld2q {z0.q, z1.q}, p4/z, \[x0, #-4, mul vl\] .*: a51ef000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, #-6, mul vl\] .*: a59ef000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, #-8, mul vl\] -.*: a4a2f000 ld2h {z0.h-z1.h}, p4/z, \[x0, #4, mul vl\] +.*: a4a29000 ld2q {z0.q, z1.q}, p4/z, \[x0, x2, lsl #4\] .*: a5249000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, x4, lsl #4\] .*: a5a69000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, x6, lsl #4\] .*: e4203200 st1q z0.q, p4, \[z16.d, x0\] diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 46f4e2f..36fd047 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -16985,21 +16985,32 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 14) & 0x1) == 0) { - if (((word >> 23) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 101001x00x1xxxxxx00xxxxxxxxxxxxx - ld1rob. */ - return 3044; + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 101001x00x1xxxxx000xxxxxxxxxxxxx + ld1rob. */ + return 3044; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 101001x01x1xxxxx000xxxxxxxxxxxxx + ld1roh. */ + return 3045; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 101001x01x1xxxxxx00xxxxxxxxxxxxx - ld1roh. */ - return 3045; + 101001x0xx1xxxxx100xxxxxxxxxxxxx + ld2q. */ + return 3323; } } else @@ -32880,8 +32891,6 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 1696: return NULL; /* ldff1b --> NULL. */ case 1714: value = 1715; break; /* ldff1h --> ldff1h. */ case 1715: return NULL; /* ldff1h --> NULL. */ - case 1669: value = 3323; break; /* ld2h --> ld2q. */ - case 3323: return NULL; /* ld2q --> NULL. */ case 2474: value = 3291; break; /* fclamp --> bfclamp. */ case 3291: return NULL; /* bfclamp --> NULL. */ case 1788: value = 1789; break; /* ldr --> ldr. */ diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 5cd5172..063343d 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -6484,7 +6484,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), SVE2p1_INSNC("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), - SVE2p1_INSNC("ld2q",0xa4a0e000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("ld2q",0xa4a08000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), SVE2p1_INSNC("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), SVE2p1_INSNC("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), |