Enable Intel VPCLMULQDQ instruction.

Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add VPCLMULQDQ.
	* doc/c-i386.texi: Document VPCLMULQDQ.
	* testsuite/gas/i386/i386.exp: Run VPCLMULQDQ tests.
	* testsuite/gas/i386/avx512f_vpclmulqdq-intel.d: New test.
	* testsuite/gas/i386/avx512f_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/x86-64-vpclmulqdq.s: Ditto.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
	(enum): Remove VEX_LEN_0F3A44_P_2.
	(vex_len_table): Ditto.
	(enum): Remove VEX_W_0F3A44_P_2.
	(vew_w_table): Ditto.
	(prefix_table): Adjust instructions (see prefixes above).
	* i386-dis-evex.h (evex_table):
	Add new instructions (see prefixes above).
	* i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
	(bitfield_cpu_flags): Ditto.
	* i386-opc.h (enum): Ditto.
	(i386_cpu_flags): Ditto.
	(CpuUnused): Comment out to avoid zero-width field problem.
	* i386-opc.tbl (vpclmulqdq): New instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.

38 files changed, 768 insertions, 15 deletions

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 4184996..f4b86f6 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1000,6 +1000,8 @@ static const arch_entry cpu_arch[] =
     CPU_GFNI_FLAGS, 0 },
   { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
     CPU_VAES_FLAGS, 0 },
+  { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
+    CPU_VPCLMULQDQ_FLAGS, 0 },
 };
 
 static const noarch_entry cpu_noarch[] =
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 551d9f2..44ade83 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -170,6 +170,7 @@ accept various extension mnemonics.  For example,
 @code{cet},
 @code{gfni},
 @code{vaes},
+@code{vpclmulqdq},
 @code{prefetchwt1},
 @code{clflushopt},
 @code{se1},
@@ -1228,7 +1229,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.gfni}
-@item @samp{.vaes}
+@item @samp{.vaes} @tab @samp{.vpclmulqdq}
 @end multitable
 
 Apart from the warning, there are only two other effects on
diff --git a/gas/testsuite/gas/i386/avx512f_vpclmulqdq-intel.d b/gas/testsuite/gas/i386/avx512f_vpclmulqdq-intel.d
new file mode 100644
index 0000000..0014df6
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512f_vpclmulqdq-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 AVX512F/VPCLMULQDQ insns (Intel disassembly)
+#source: avx512f_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 48 44 c9 ab[ 	]*vpclmulqdq zmm1,zmm3,zmm1,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 48 44 8c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq zmm1,zmm3,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 48 44 4a 7f 7b[ 	]*vpclmulqdq zmm1,zmm3,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 48 44 d2 ab[ 	]*vpclmulqdq zmm2,zmm2,zmm2,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 48 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq zmm2,zmm2,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 48 44 52 7f 7b[ 	]*vpclmulqdq zmm2,zmm2,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
+#pass
diff --git a/gas/testsuite/gas/i386/avx512f_vpclmulqdq-wig.s b/gas/testsuite/gas/i386/avx512f_vpclmulqdq-wig.s
new file mode 100644
index 0000000..4f97c87
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512f_vpclmulqdq-wig.s
@@ -0,0 +1,13 @@
+# Check 32bit AVX512F,VPCLMULQDQ WIG instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vpclmulqdq	$0xab, %zmm2, %zmm1, %zmm6	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	$123, -123456(%esp,%esi,8), %zmm1, %zmm6	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	$123, 8128(%edx), %zmm1, %zmm6	 # AVX512F,VPCLMULQDQ Disp8
+
+	.intel_syntax noprefix
+	vpclmulqdq	zmm5, zmm1, zmm2, 0xab	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	zmm5, zmm1, ZMMWORD PTR [esp+esi*8-123456], 123	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	zmm5, zmm1, ZMMWORD PTR [edx+8128], 123	 # AVX512F,VPCLMULQDQ Disp8
diff --git a/gas/testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d b/gas/testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d
new file mode 100644
index 0000000..3dbd5c1
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d
@@ -0,0 +1,18 @@
+#as: -mevexwig=1
+#objdump: -dw -Mintel
+#name: i386 AVX512F/VPCLMULQDQ wig insns (Intel disassembly)
+#source: avx512f_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 48 44 f2 ab[ 	]*vpclmulqdq zmm6,zmm1,zmm2,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 48 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq zmm6,zmm1,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 48 44 72 7f 7b[ 	]*vpclmulqdq zmm6,zmm1,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 48 44 ea ab[ 	]*vpclmulqdq zmm5,zmm1,zmm2,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 48 44 ac f4 c0 1d fe ff 7b[ 	]*vpclmulqdq zmm5,zmm1,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 48 44 6a 7f 7b[ 	]*vpclmulqdq zmm5,zmm1,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
+#pass
diff --git a/gas/testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d b/gas/testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d
new file mode 100644
index 0000000..5bdf1e1
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d
@@ -0,0 +1,18 @@
+#as: -mevexwig=1
+#objdump: -dw
+#name: i386 AVX512F/VPCLMULQDQ wig insns
+#source: avx512f_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 48 44 f2 ab[ 	]*vpclmulqdq \$0xab,%zmm2,%zmm1,%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 48 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm1,%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 48 44 72 7f 7b[ 	]*vpclmulqdq \$0x7b,0x1fc0\(%edx\),%zmm1,%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 48 44 ea ab[ 	]*vpclmulqdq \$0xab,%zmm2,%zmm1,%zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 48 44 ac f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm1,%zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 48 44 6a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x1fc0\(%edx\),%zmm1,%zmm5
+#pass
diff --git a/gas/testsuite/gas/i386/avx512f_vpclmulqdq.d b/gas/testsuite/gas/i386/avx512f_vpclmulqdq.d
new file mode 100644
index 0000000..7bc5188
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512f_vpclmulqdq.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: i386 AVX512F/VPCLMULQDQ insns
+#source: avx512f_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 48 44 c9 ab[ 	]*vpclmulqdq \$0xab,%zmm1,%zmm3,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 48 44 8c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm3,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 48 44 4a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x1fc0\(%edx\),%zmm3,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 48 44 d2 ab[ 	]*vpclmulqdq \$0xab,%zmm2,%zmm2,%zmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 48 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm2,%zmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 48 44 52 7f 7b[ 	]*vpclmulqdq \$0x7b,0x1fc0\(%edx\),%zmm2,%zmm2
+#pass
diff --git a/gas/testsuite/gas/i386/avx512f_vpclmulqdq.s b/gas/testsuite/gas/i386/avx512f_vpclmulqdq.s
new file mode 100644
index 0000000..db57eae
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512f_vpclmulqdq.s
@@ -0,0 +1,13 @@
+# Check 32bit AVX512F,VPCLMULQDQ instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vpclmulqdq	$0xab, %zmm1, %zmm3, %zmm1	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	$123, -123456(%esp,%esi,8), %zmm3, %zmm1	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	$123, 8128(%edx), %zmm3, %zmm1	 # AVX512F,VPCLMULQDQ Disp8
+
+	.intel_syntax noprefix
+	vpclmulqdq	zmm2, zmm2, zmm2, 0xab	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	zmm2, zmm2, ZMMWORD PTR [esp+esi*8-123456], 123	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	zmm2, zmm2, ZMMWORD PTR [edx+8128], 123	 # AVX512F,VPCLMULQDQ Disp8
diff --git a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d
new file mode 100644
index 0000000..47db805
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d
@@ -0,0 +1,36 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 AVX512VL/VPCLMULQDQ insns (Intel disassembly)
+#source: avx512vl_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 69 44 da ab[ 	]*vpclmulqdq xmm3,xmm2,xmm2,0xab
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 69 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq xmm3,xmm2,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 69 44 9a f0 07 00 00 7b[ 	]*vpclmulqdq xmm3,xmm2,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 e1 ab[ 	]*vpclmulqdq ymm4,ymm5,ymm1,0xab
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 a4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 a2 e0 0f 00 00 7b[ 	]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 da ab[ 	]*vpclmulqdq xmm3,xmm2,xmm2,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq xmm3,xmm2,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 5a 7f 7b[ 	]*vpclmulqdq xmm3,xmm2,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 e1 ab[ 	]*vpclmulqdq ymm4,ymm5,ymm1,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 62 7f 7b[ 	]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 db ab[ 	]*vpclmulqdq xmm3,xmm5,xmm3,0xab
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 9a f0 07 00 00 7b[ 	]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 6d 44 d2 ab[ 	]*vpclmulqdq ymm2,ymm2,ymm2,0xab
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 6d 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 6d 44 92 e0 0f 00 00 7b[ 	]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 db ab[ 	]*vpclmulqdq xmm3,xmm5,xmm3,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 5a 7f 7b[ 	]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 d2 ab[ 	]*vpclmulqdq ymm2,ymm2,ymm2,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 52 7f 7b[ 	]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[edx\+0xfe0\],0x7b
+#pass
diff --git a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s
new file mode 100644
index 0000000..109d009
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s
@@ -0,0 +1,33 @@
+# Check 32bit AVX512VL,VPCLMULQDQ WIG instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vpclmulqdq	$0xab, %xmm4, %xmm1, %xmm1	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, -123456(%esp,%esi,8), %xmm1, %xmm1	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, 2032(%edx), %xmm1, %xmm1	 # AVX512VL,VPCLMULQDQ Disp8
+	vpclmulqdq	$0xab, %ymm2, %ymm5, %ymm3	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, -123456(%esp,%esi,8), %ymm5, %ymm3	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, 4064(%edx), %ymm5, %ymm3	 # AVX512VL,VPCLMULQDQ Disp8
+
+	{evex} vpclmulqdq	$0xab, %xmm4, %xmm1, %xmm1	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, -123456(%esp,%esi,8), %xmm1, %xmm1	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, 2032(%edx), %xmm1, %xmm1	 # AVX512VL,VPCLMULQDQ Disp8
+	{evex} vpclmulqdq	$0xab, %ymm2, %ymm5, %ymm3	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, -123456(%esp,%esi,8), %ymm5, %ymm3	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, 4064(%edx), %ymm5, %ymm3	 # AVX512VL,VPCLMULQDQ Disp8
+
+	.intel_syntax noprefix
+	vpclmulqdq	xmm6, xmm4, xmm1, 0xab	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	xmm6, xmm4, XMMWORD PTR [esp+esi*8-123456], 123	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	xmm6, xmm4, XMMWORD PTR [edx+2032], 123	 # AVX512VL,VPCLMULQDQ Disp8
+	vpclmulqdq	ymm2, ymm4, ymm4, 0xab	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	ymm2, ymm4, YMMWORD PTR [esp+esi*8-123456], 123	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	ymm2, ymm4, YMMWORD PTR [edx+4064], 123	 # AVX512VL,VPCLMULQDQ Disp8
+
+	{evex} vpclmulqdq	xmm6, xmm4, xmm1, 0xab	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	xmm6, xmm4, XMMWORD PTR [esp+esi*8-123456], 123	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	xmm6, xmm4, XMMWORD PTR [edx+2032], 123	 # AVX512VL,VPCLMULQDQ Disp8
+	{evex} vpclmulqdq	ymm2, ymm4, ymm4, 0xab	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	ymm2, ymm4, YMMWORD PTR [esp+esi*8-123456], 123	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	ymm2, ymm4, YMMWORD PTR [edx+4064], 123	 # AVX512VL,VPCLMULQDQ Disp8
diff --git a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d
new file mode 100644
index 0000000..54a9275
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d
@@ -0,0 +1,36 @@
+#as: -mevexwig=1
+#objdump: -dw -Mintel
+#name: i386 AVX512VL/VPCLMULQDQ wig insns (Intel disassembly)
+#source: avx512vl_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 71 44 cc ab[ 	]*vpclmulqdq xmm1,xmm1,xmm4,0xab
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 71 44 8c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq xmm1,xmm1,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 71 44 8a f0 07 00 00 7b[ 	]*vpclmulqdq xmm1,xmm1,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 da ab[ 	]*vpclmulqdq ymm3,ymm5,ymm2,0xab
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 9a e0 0f 00 00 7b[ 	]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 cc ab[ 	]*vpclmulqdq xmm1,xmm1,xmm4,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 8c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq xmm1,xmm1,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 4a 7f 7b[ 	]*vpclmulqdq xmm1,xmm1,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 da ab[ 	]*vpclmulqdq ymm3,ymm5,ymm2,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 5a 7f 7b[ 	]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 59 44 f1 ab[ 	]*vpclmulqdq xmm6,xmm4,xmm1,0xab
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 59 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 59 44 b2 f0 07 00 00 7b[ 	]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 5d 44 d4 ab[ 	]*vpclmulqdq ymm2,ymm4,ymm4,0xab
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 5d 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 5d 44 92 e0 0f 00 00 7b[ 	]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 f1 ab[ 	]*vpclmulqdq xmm6,xmm4,xmm1,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 72 7f 7b[ 	]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 d4 ab[ 	]*vpclmulqdq ymm2,ymm4,ymm4,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 52 7f 7b[ 	]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[edx\+0xfe0\],0x7b
+#pass
diff --git a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d
new file mode 100644
index 0000000..85e04ce
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d
@@ -0,0 +1,36 @@
+#as: -mevexwig=1
+#objdump: -dw
+#name: i386 AVX512VL/VPCLMULQDQ wig insns
+#source: avx512vl_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 71 44 cc ab[ 	]*vpclmulqdq \$0xab,%xmm4,%xmm1,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 71 44 8c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm1,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 71 44 8a f0 07 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm1,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 da ab[ 	]*vpclmulqdq \$0xab,%ymm2,%ymm5,%ymm3
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm3
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 9a e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 cc ab[ 	]*vpclmulqdq \$0xab,%xmm4,%xmm1,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 8c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm1,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 4a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm1,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 da ab[ 	]*vpclmulqdq \$0xab,%ymm2,%ymm5,%ymm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 5a 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm3
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 59 44 f1 ab[ 	]*vpclmulqdq \$0xab,%xmm1,%xmm4,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 59 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm4,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 59 44 b2 f0 07 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm4,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 5d 44 d4 ab[ 	]*vpclmulqdq \$0xab,%ymm4,%ymm4,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 5d 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm4,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 5d 44 92 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm4,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 f1 ab[ 	]*vpclmulqdq \$0xab,%xmm1,%xmm4,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm4,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 72 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm4,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 d4 ab[ 	]*vpclmulqdq \$0xab,%ymm4,%ymm4,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm4,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 52 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm4,%ymm2
+#pass
diff --git a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.d b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.d
new file mode 100644
index 0000000..593c949
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.d
@@ -0,0 +1,36 @@
+#as:
+#objdump: -dw
+#name: i386 AVX512VL/VPCLMULQDQ insns
+#source: avx512vl_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 69 44 da ab[ 	]*vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 69 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 69 44 9a f0 07 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 e1 ab[ 	]*vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 a4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 a2 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 da ab[ 	]*vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 5a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 e1 ab[ 	]*vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 62 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 db ab[ 	]*vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 9a f0 07 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 6d 44 d2 ab[ 	]*vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 6d 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 6d 44 92 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 db ab[ 	]*vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 5a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 d2 ab[ 	]*vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 52 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
+#pass
diff --git a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.s b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.s
new file mode 100644
index 0000000..1d5ef40
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.s
@@ -0,0 +1,33 @@
+# Check 32bit AVX512VL,VPCLMULQDQ instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vpclmulqdq	$0xab, %xmm2, %xmm2, %xmm3	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, -123456(%esp,%esi,8), %xmm2, %xmm3	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, 2032(%edx), %xmm2, %xmm3	 # AVX512VL,VPCLMULQDQ Disp8
+	vpclmulqdq	$0xab, %ymm1, %ymm5, %ymm4	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, -123456(%esp,%esi,8), %ymm5, %ymm4	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, 4064(%edx), %ymm5, %ymm4	 # AVX512VL,VPCLMULQDQ Disp8
+
+	{evex} vpclmulqdq	$0xab, %xmm2, %xmm2, %xmm3	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, -123456(%esp,%esi,8), %xmm2, %xmm3	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, 2032(%edx), %xmm2, %xmm3	 # AVX512VL,VPCLMULQDQ Disp8
+	{evex} vpclmulqdq	$0xab, %ymm1, %ymm5, %ymm4	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, -123456(%esp,%esi,8), %ymm5, %ymm4	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, 4064(%edx), %ymm5, %ymm4	 # AVX512VL,VPCLMULQDQ Disp8
+
+	.intel_syntax noprefix
+	vpclmulqdq	xmm3, xmm5, xmm3, 0xab	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	xmm3, xmm5, XMMWORD PTR [esp+esi*8-123456], 123	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	xmm3, xmm5, XMMWORD PTR [edx+2032], 123	 # AVX512VL,VPCLMULQDQ Disp8
+	vpclmulqdq	ymm2, ymm2, ymm2, 0xab	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	ymm2, ymm2, YMMWORD PTR [esp+esi*8-123456], 123	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	ymm2, ymm2, YMMWORD PTR [edx+4064], 123	 # AVX512VL,VPCLMULQDQ Disp8
+
+	{evex} vpclmulqdq	xmm3, xmm5, xmm3, 0xab	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	xmm3, xmm5, XMMWORD PTR [esp+esi*8-123456], 123	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	xmm3, xmm5, XMMWORD PTR [edx+2032], 123	 # AVX512VL,VPCLMULQDQ Disp8
+	{evex} vpclmulqdq	ymm2, ymm2, ymm2, 0xab	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	ymm2, ymm2, YMMWORD PTR [esp+esi*8-123456], 123	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	ymm2, ymm2, YMMWORD PTR [edx+4064], 123	 # AVX512VL,VPCLMULQDQ Disp8
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index bb48e5d..78c3562 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -386,6 +386,14 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "avx512vl_vaes-intel"
     run_dump_test "avx512vl_vaes-wig1"
     run_dump_test "avx512vl_vaes-wig1-intel"
+    run_dump_test "avx512f_vpclmulqdq"
+    run_dump_test "avx512f_vpclmulqdq-intel"
+    run_dump_test "avx512f_vpclmulqdq-wig1"
+    run_dump_test "avx512f_vpclmulqdq-wig1-intel"
+    run_dump_test "avx512vl_vpclmulqdq"
+    run_dump_test "avx512vl_vpclmulqdq-intel"
+    run_dump_test "avx512vl_vpclmulqdq-wig1"
+    run_dump_test "avx512vl_vpclmulqdq-wig1-intel"
     run_dump_test "clzero"
     run_dump_test "disassem"
     run_dump_test "mwaitx-bdver4"
@@ -399,6 +407,8 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "gfni-intel"
     run_dump_test "vaes"
     run_dump_test "vaes-intel"
+    run_dump_test "vpclmulqdq"
+    run_dump_test "vpclmulqdq-intel"
     run_list_test "avx512vl-1" "-al"
     run_list_test "avx512vl-2" "-al"
     run_dump_test "fpu-bad"
@@ -829,6 +839,14 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-avx512vl_vaes-intel"
     run_dump_test "x86-64-avx512vl_vaes-wig1"
     run_dump_test "x86-64-avx512vl_vaes-wig1-intel"
+    run_dump_test "x86-64-avx512f_vpclmulqdq"
+    run_dump_test "x86-64-avx512f_vpclmulqdq-intel"
+    run_dump_test "x86-64-avx512f_vpclmulqdq-wig1"
+    run_dump_test "x86-64-avx512f_vpclmulqdq-wig1-intel"
+    run_dump_test "x86-64-avx512vl_vpclmulqdq"
+    run_dump_test "x86-64-avx512vl_vpclmulqdq-intel"
+    run_dump_test "x86-64-avx512vl_vpclmulqdq-wig1"
+    run_dump_test "x86-64-avx512vl_vpclmulqdq-wig1-intel"
     run_dump_test "x86-64-clzero"
     run_dump_test "x86-64-mwaitx-bdver4"
     run_list_test "x86-64-mwaitx-reg"
@@ -841,6 +859,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-gfni-intel"
     run_dump_test "x86-64-vaes"
     run_dump_test "x86-64-vaes-intel"
+    run_dump_test "x86-64-vpclmulqdq"
+    run_dump_test "x86-64-vpclmulqdq-intel"
     run_dump_test "x86-64-fence-as-lock-add-yes"
     run_dump_test "x86-64-fence-as-lock-add-no"
     run_dump_test "x86-64-pr20141"
diff --git a/gas/testsuite/gas/i386/vpclmulqdq-intel.d b/gas/testsuite/gas/i386/vpclmulqdq-intel.d
new file mode 100644
index 0000000..fa8ba5b
--- /dev/null
+++ b/gas/testsuite/gas/i386/vpclmulqdq-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 VPCLMULQDQ insns (Intel disassembly)
+#source: vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 f4 ab[ 	]*vpclmulqdq ymm6,ymm5,ymm4,0xab
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b2 e0 0f 00 00 7b[ 	]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 f4 ab[ 	]*vpclmulqdq ymm6,ymm5,ymm4,0xab
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b2 e0 0f 00 00 7b[ 	]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+#pass
diff --git a/gas/testsuite/gas/i386/vpclmulqdq.d b/gas/testsuite/gas/i386/vpclmulqdq.d
new file mode 100644
index 0000000..8de566f
--- /dev/null
+++ b/gas/testsuite/gas/i386/vpclmulqdq.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: i386 VPCLMULQDQ insns
+#source: vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 f4 ab[ 	]*vpclmulqdq \$0xab,%ymm4,%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b2 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 f4 ab[ 	]*vpclmulqdq \$0xab,%ymm4,%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b2 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
+#pass
diff --git a/gas/testsuite/gas/i386/vpclmulqdq.s b/gas/testsuite/gas/i386/vpclmulqdq.s
new file mode 100644
index 0000000..02965f9
--- /dev/null
+++ b/gas/testsuite/gas/i386/vpclmulqdq.s
@@ -0,0 +1,13 @@
+# Check VPCLMULQDQ instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vpclmulqdq	$0xab, %ymm4, %ymm5, %ymm6
+	vpclmulqdq	$123, -123456(%esp,%esi,8), %ymm5, %ymm6
+	vpclmulqdq	$123, 4064(%edx), %ymm5, %ymm6
+
+	.intel_syntax noprefix
+	vpclmulqdq	ymm6, ymm5, ymm4, 0xab
+	vpclmulqdq	ymm6, ymm5, YMMWORD PTR [esp+esi*8-123456], 123
+	vpclmulqdq	ymm6, ymm5, YMMWORD PTR [edx+4064], 123
diff --git a/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d
new file mode 100644
index 0000000..1d4c941
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 AVX512F/VPCLMULQDQ insns (Intel disassembly)
+#source: x86-64-avx512f_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 03 45 40 44 d0 ab[ 	]*vpclmulqdq zmm26,zmm23,zmm24,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 23 45 40 44 94 f0 23 01 00 00 7b[ 	]*vpclmulqdq zmm26,zmm23,ZMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 45 40 44 52 7f 7b[ 	]*vpclmulqdq zmm26,zmm23,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 83 55 40 44 eb ab[ 	]*vpclmulqdq zmm21,zmm21,zmm27,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 a3 55 40 44 ac f0 34 12 00 00 7b[ 	]*vpclmulqdq zmm21,zmm21,ZMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 e3 55 40 44 6a 7f 7b[ 	]*vpclmulqdq zmm21,zmm21,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s
new file mode 100644
index 0000000..0ba18d4
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s
@@ -0,0 +1,13 @@
+# Check 64bit AVX512F,VPCLMULQDQ WIG instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vpclmulqdq	$0xab, %zmm19, %zmm20, %zmm22	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	$123, 0x123(%rax,%r14,8), %zmm20, %zmm22	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	$123, 8128(%rdx), %zmm20, %zmm22	 # AVX512F,VPCLMULQDQ Disp8
+
+	.intel_syntax noprefix
+	vpclmulqdq	zmm29, zmm28, zmm23, 0xab	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	zmm29, zmm28, ZMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	zmm29, zmm28, ZMMWORD PTR [rdx+8128], 123	 # AVX512F,VPCLMULQDQ Disp8
diff --git a/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d
new file mode 100644
index 0000000..48c6a5c
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d
@@ -0,0 +1,18 @@
+#as: -mevexwig=1
+#objdump: -dw -Mintel
+#name: x86_64 AVX512F/VPCLMULQDQ wig insns (Intel disassembly)
+#source: x86-64-avx512f_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 a3 dd 40 44 f3 ab[ 	]*vpclmulqdq zmm22,zmm20,zmm19,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 a3 dd 40 44 b4 f0 23 01 00 00 7b[ 	]*vpclmulqdq zmm22,zmm20,ZMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 e3 dd 40 44 72 7f 7b[ 	]*vpclmulqdq zmm22,zmm20,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 23 9d 40 44 ef ab[ 	]*vpclmulqdq zmm29,zmm28,zmm23,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 23 9d 40 44 ac f0 34 12 00 00 7b[ 	]*vpclmulqdq zmm29,zmm28,ZMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 9d 40 44 6a 7f 7b[ 	]*vpclmulqdq zmm29,zmm28,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d
new file mode 100644
index 0000000..b1b0951
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d
@@ -0,0 +1,18 @@
+#as: -mevexwig=1
+#objdump: -dw
+#name: x86_64 AVX512F/VPCLMULQDQ wig insns
+#source: x86-64-avx512f_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 a3 dd 40 44 f3 ab[ 	]*vpclmulqdq \$0xab,%zmm19,%zmm20,%zmm22
+[ 	]*[a-f0-9]+:[ 	]*62 a3 dd 40 44 b4 f0 23 01 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%zmm20,%zmm22
+[ 	]*[a-f0-9]+:[ 	]*62 e3 dd 40 44 72 7f 7b[ 	]*vpclmulqdq \$0x7b,0x1fc0\(%rdx\),%zmm20,%zmm22
+[ 	]*[a-f0-9]+:[ 	]*62 23 9d 40 44 ef ab[ 	]*vpclmulqdq \$0xab,%zmm23,%zmm28,%zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 23 9d 40 44 ac f0 34 12 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%zmm28,%zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 63 9d 40 44 6a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x1fc0\(%rdx\),%zmm28,%zmm29
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d
new file mode 100644
index 0000000..475e652
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: x86_64 AVX512F/VPCLMULQDQ insns
+#source: x86-64-avx512f_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 03 45 40 44 d0 ab[ 	]*vpclmulqdq \$0xab,%zmm24,%zmm23,%zmm26
+[ 	]*[a-f0-9]+:[ 	]*62 23 45 40 44 94 f0 23 01 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%zmm23,%zmm26
+[ 	]*[a-f0-9]+:[ 	]*62 63 45 40 44 52 7f 7b[ 	]*vpclmulqdq \$0x7b,0x1fc0\(%rdx\),%zmm23,%zmm26
+[ 	]*[a-f0-9]+:[ 	]*62 83 55 40 44 eb ab[ 	]*vpclmulqdq \$0xab,%zmm27,%zmm21,%zmm21
+[ 	]*[a-f0-9]+:[ 	]*62 a3 55 40 44 ac f0 34 12 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%zmm21,%zmm21
+[ 	]*[a-f0-9]+:[ 	]*62 e3 55 40 44 6a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x1fc0\(%rdx\),%zmm21,%zmm21
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s
new file mode 100644
index 0000000..dae9520
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s
@@ -0,0 +1,13 @@
+# Check 64bit AVX512F,VPCLMULQDQ instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vpclmulqdq	$0xab, %zmm24, %zmm23, %zmm26	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	$123, 0x123(%rax,%r14,8), %zmm23, %zmm26	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	$123, 8128(%rdx), %zmm23, %zmm26	 # AVX512F,VPCLMULQDQ Disp8
+
+	.intel_syntax noprefix
+	vpclmulqdq	zmm21, zmm21, zmm27, 0xab	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	zmm21, zmm21, ZMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512F,VPCLMULQDQ
+	vpclmulqdq	zmm21, zmm21, ZMMWORD PTR [rdx+8128], 123	 # AVX512F,VPCLMULQDQ Disp8
diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d
new file mode 100644
index 0000000..96945c4
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d
@@ -0,0 +1,36 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 AVX512VL/VPCLMULQDQ insns (Intel disassembly)
+#source: x86-64-avx512vl_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 23 15 00 44 ca ab[ 	]*vpclmulqdq xmm25,xmm29,xmm18,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 23 15 00 44 8c f0 23 01 00 00 7b[ 	]*vpclmulqdq xmm25,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 15 00 44 4a 7f 7b[ 	]*vpclmulqdq xmm25,xmm29,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 23 6d 20 44 ea ab[ 	]*vpclmulqdq ymm29,ymm18,ymm18,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 23 6d 20 44 ac f0 23 01 00 00 7b[ 	]*vpclmulqdq ymm29,ymm18,YMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 6d 20 44 6a 7f 7b[ 	]*vpclmulqdq ymm29,ymm18,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 23 15 00 44 ca ab[ 	]*vpclmulqdq xmm25,xmm29,xmm18,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 23 15 00 44 8c f0 23 01 00 00 7b[ 	]*vpclmulqdq xmm25,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 15 00 44 4a 7f 7b[ 	]*vpclmulqdq xmm25,xmm29,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 23 6d 20 44 ea ab[ 	]*vpclmulqdq ymm29,ymm18,ymm18,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 23 6d 20 44 ac f0 23 01 00 00 7b[ 	]*vpclmulqdq ymm29,ymm18,YMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 6d 20 44 6a 7f 7b[ 	]*vpclmulqdq ymm29,ymm18,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 a3 2d 00 44 dc ab[ 	]*vpclmulqdq xmm19,xmm26,xmm20,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 a3 2d 00 44 9c f0 34 12 00 00 7b[ 	]*vpclmulqdq xmm19,xmm26,XMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 e3 2d 00 44 5a 7f 7b[ 	]*vpclmulqdq xmm19,xmm26,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 83 15 20 44 fb ab[ 	]*vpclmulqdq ymm23,ymm29,ymm27,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 a3 15 20 44 bc f0 34 12 00 00 7b[ 	]*vpclmulqdq ymm23,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 e3 15 20 44 7a 7f 7b[ 	]*vpclmulqdq ymm23,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 a3 2d 00 44 dc ab[ 	]*vpclmulqdq xmm19,xmm26,xmm20,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 a3 2d 00 44 9c f0 34 12 00 00 7b[ 	]*vpclmulqdq xmm19,xmm26,XMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 e3 2d 00 44 5a 7f 7b[ 	]*vpclmulqdq xmm19,xmm26,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 83 15 20 44 fb ab[ 	]*vpclmulqdq ymm23,ymm29,ymm27,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 a3 15 20 44 bc f0 34 12 00 00 7b[ 	]*vpclmulqdq ymm23,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 e3 15 20 44 7a 7f 7b[ 	]*vpclmulqdq ymm23,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s
new file mode 100644
index 0000000..4c5baa6
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s
@@ -0,0 +1,33 @@
+# Check 64bit AVX512VL,VPCLMULQDQ WIG instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vpclmulqdq	$0xab, %xmm23, %xmm21, %xmm17	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, 0x123(%rax,%r14,8), %xmm21, %xmm17	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, 2032(%rdx), %xmm21, %xmm17	 # AVX512VL,VPCLMULQDQ Disp8
+	vpclmulqdq	$0xab, %ymm19, %ymm18, %ymm23	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, 0x123(%rax,%r14,8), %ymm18, %ymm23	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, 4064(%rdx), %ymm18, %ymm23	 # AVX512VL,VPCLMULQDQ Disp8
+
+	{evex} vpclmulqdq	$0xab, %xmm23, %xmm21, %xmm17	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, 0x123(%rax,%r14,8), %xmm21, %xmm17	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, 2032(%rdx), %xmm21, %xmm17	 # AVX512VL,VPCLMULQDQ Disp8
+	{evex} vpclmulqdq	$0xab, %ymm19, %ymm18, %ymm23	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, 0x123(%rax,%r14,8), %ymm18, %ymm23	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, 4064(%rdx), %ymm18, %ymm23	 # AVX512VL,VPCLMULQDQ Disp8
+
+	.intel_syntax noprefix
+	vpclmulqdq	xmm18, xmm22, xmm17, 0xab	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	xmm18, xmm22, XMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	xmm18, xmm22, XMMWORD PTR [rdx+2032], 123	 # AVX512VL,VPCLMULQDQ Disp8
+	vpclmulqdq	ymm26, ymm25, ymm23, 0xab	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	ymm26, ymm25, YMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	ymm26, ymm25, YMMWORD PTR [rdx+4064], 123	 # AVX512VL,VPCLMULQDQ Disp8
+
+	{evex} vpclmulqdq	xmm18, xmm22, xmm17, 0xab	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	xmm18, xmm22, XMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	xmm18, xmm22, XMMWORD PTR [rdx+2032], 123	 # AVX512VL,VPCLMULQDQ Disp8
+	{evex} vpclmulqdq	ymm26, ymm25, ymm23, 0xab	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	ymm26, ymm25, YMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	ymm26, ymm25, YMMWORD PTR [rdx+4064], 123	 # AVX512VL,VPCLMULQDQ Disp8
diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d
new file mode 100644
index 0000000..423575b
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d
@@ -0,0 +1,36 @@
+#as: -mevexwig=1
+#objdump: -dw -Mintel
+#name: x86_64 AVX512VL/VPCLMULQDQ wig insns (Intel disassembly)
+#source: x86-64-avx512vl_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 a3 d5 00 44 cf ab[ 	]*vpclmulqdq xmm17,xmm21,xmm23,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 a3 d5 00 44 8c f0 23 01 00 00 7b[ 	]*vpclmulqdq xmm17,xmm21,XMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 e3 d5 00 44 4a 7f 7b[ 	]*vpclmulqdq xmm17,xmm21,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 a3 ed 20 44 fb ab[ 	]*vpclmulqdq ymm23,ymm18,ymm19,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 a3 ed 20 44 bc f0 23 01 00 00 7b[ 	]*vpclmulqdq ymm23,ymm18,YMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 e3 ed 20 44 7a 7f 7b[ 	]*vpclmulqdq ymm23,ymm18,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 a3 d5 00 44 cf ab[ 	]*vpclmulqdq xmm17,xmm21,xmm23,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 a3 d5 00 44 8c f0 23 01 00 00 7b[ 	]*vpclmulqdq xmm17,xmm21,XMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 e3 d5 00 44 4a 7f 7b[ 	]*vpclmulqdq xmm17,xmm21,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 a3 ed 20 44 fb ab[ 	]*vpclmulqdq ymm23,ymm18,ymm19,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 a3 ed 20 44 bc f0 23 01 00 00 7b[ 	]*vpclmulqdq ymm23,ymm18,YMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 e3 ed 20 44 7a 7f 7b[ 	]*vpclmulqdq ymm23,ymm18,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 a3 cd 00 44 d1 ab[ 	]*vpclmulqdq xmm18,xmm22,xmm17,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 a3 cd 00 44 94 f0 34 12 00 00 7b[ 	]*vpclmulqdq xmm18,xmm22,XMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 e3 cd 00 44 52 7f 7b[ 	]*vpclmulqdq xmm18,xmm22,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 23 b5 20 44 d7 ab[ 	]*vpclmulqdq ymm26,ymm25,ymm23,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 23 b5 20 44 94 f0 34 12 00 00 7b[ 	]*vpclmulqdq ymm26,ymm25,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 b5 20 44 52 7f 7b[ 	]*vpclmulqdq ymm26,ymm25,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 a3 cd 00 44 d1 ab[ 	]*vpclmulqdq xmm18,xmm22,xmm17,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 a3 cd 00 44 94 f0 34 12 00 00 7b[ 	]*vpclmulqdq xmm18,xmm22,XMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 e3 cd 00 44 52 7f 7b[ 	]*vpclmulqdq xmm18,xmm22,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 23 b5 20 44 d7 ab[ 	]*vpclmulqdq ymm26,ymm25,ymm23,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 23 b5 20 44 94 f0 34 12 00 00 7b[ 	]*vpclmulqdq ymm26,ymm25,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 b5 20 44 52 7f 7b[ 	]*vpclmulqdq ymm26,ymm25,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d
new file mode 100644
index 0000000..cf655c2
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d
@@ -0,0 +1,36 @@
+#as: -mevexwig=1
+#objdump: -dw
+#name: x86_64 AVX512VL/VPCLMULQDQ wig insns
+#source: x86-64-avx512vl_vpclmulqdq-wig.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 a3 d5 00 44 cf ab[ 	]*vpclmulqdq \$0xab,%xmm23,%xmm21,%xmm17
+[ 	]*[a-f0-9]+:[ 	]*62 a3 d5 00 44 8c f0 23 01 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%xmm21,%xmm17
+[ 	]*[a-f0-9]+:[ 	]*62 e3 d5 00 44 4a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm21,%xmm17
+[ 	]*[a-f0-9]+:[ 	]*62 a3 ed 20 44 fb ab[ 	]*vpclmulqdq \$0xab,%ymm19,%ymm18,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 a3 ed 20 44 bc f0 23 01 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%ymm18,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 e3 ed 20 44 7a 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm18,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 a3 d5 00 44 cf ab[ 	]*vpclmulqdq \$0xab,%xmm23,%xmm21,%xmm17
+[ 	]*[a-f0-9]+:[ 	]*62 a3 d5 00 44 8c f0 23 01 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%xmm21,%xmm17
+[ 	]*[a-f0-9]+:[ 	]*62 e3 d5 00 44 4a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm21,%xmm17
+[ 	]*[a-f0-9]+:[ 	]*62 a3 ed 20 44 fb ab[ 	]*vpclmulqdq \$0xab,%ymm19,%ymm18,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 a3 ed 20 44 bc f0 23 01 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%ymm18,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 e3 ed 20 44 7a 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm18,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 a3 cd 00 44 d1 ab[ 	]*vpclmulqdq \$0xab,%xmm17,%xmm22,%xmm18
+[ 	]*[a-f0-9]+:[ 	]*62 a3 cd 00 44 94 f0 34 12 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%xmm22,%xmm18
+[ 	]*[a-f0-9]+:[ 	]*62 e3 cd 00 44 52 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm22,%xmm18
+[ 	]*[a-f0-9]+:[ 	]*62 23 b5 20 44 d7 ab[ 	]*vpclmulqdq \$0xab,%ymm23,%ymm25,%ymm26
+[ 	]*[a-f0-9]+:[ 	]*62 23 b5 20 44 94 f0 34 12 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm25,%ymm26
+[ 	]*[a-f0-9]+:[ 	]*62 63 b5 20 44 52 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm25,%ymm26
+[ 	]*[a-f0-9]+:[ 	]*62 a3 cd 00 44 d1 ab[ 	]*vpclmulqdq \$0xab,%xmm17,%xmm22,%xmm18
+[ 	]*[a-f0-9]+:[ 	]*62 a3 cd 00 44 94 f0 34 12 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%xmm22,%xmm18
+[ 	]*[a-f0-9]+:[ 	]*62 e3 cd 00 44 52 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm22,%xmm18
+[ 	]*[a-f0-9]+:[ 	]*62 23 b5 20 44 d7 ab[ 	]*vpclmulqdq \$0xab,%ymm23,%ymm25,%ymm26
+[ 	]*[a-f0-9]+:[ 	]*62 23 b5 20 44 94 f0 34 12 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm25,%ymm26
+[ 	]*[a-f0-9]+:[ 	]*62 63 b5 20 44 52 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm25,%ymm26
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d
new file mode 100644
index 0000000..db8cbe8
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d
@@ -0,0 +1,36 @@
+#as:
+#objdump: -dw
+#name: x86_64 AVX512VL/VPCLMULQDQ insns
+#source: x86-64-avx512vl_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 23 15 00 44 ca ab[ 	]*vpclmulqdq \$0xab,%xmm18,%xmm29,%xmm25
+[ 	]*[a-f0-9]+:[ 	]*62 23 15 00 44 8c f0 23 01 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%xmm29,%xmm25
+[ 	]*[a-f0-9]+:[ 	]*62 63 15 00 44 4a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm29,%xmm25
+[ 	]*[a-f0-9]+:[ 	]*62 23 6d 20 44 ea ab[ 	]*vpclmulqdq \$0xab,%ymm18,%ymm18,%ymm29
+[ 	]*[a-f0-9]+:[ 	]*62 23 6d 20 44 ac f0 23 01 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%ymm18,%ymm29
+[ 	]*[a-f0-9]+:[ 	]*62 63 6d 20 44 6a 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm18,%ymm29
+[ 	]*[a-f0-9]+:[ 	]*62 23 15 00 44 ca ab[ 	]*vpclmulqdq \$0xab,%xmm18,%xmm29,%xmm25
+[ 	]*[a-f0-9]+:[ 	]*62 23 15 00 44 8c f0 23 01 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%xmm29,%xmm25
+[ 	]*[a-f0-9]+:[ 	]*62 63 15 00 44 4a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm29,%xmm25
+[ 	]*[a-f0-9]+:[ 	]*62 23 6d 20 44 ea ab[ 	]*vpclmulqdq \$0xab,%ymm18,%ymm18,%ymm29
+[ 	]*[a-f0-9]+:[ 	]*62 23 6d 20 44 ac f0 23 01 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%ymm18,%ymm29
+[ 	]*[a-f0-9]+:[ 	]*62 63 6d 20 44 6a 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm18,%ymm29
+[ 	]*[a-f0-9]+:[ 	]*62 a3 2d 00 44 dc ab[ 	]*vpclmulqdq \$0xab,%xmm20,%xmm26,%xmm19
+[ 	]*[a-f0-9]+:[ 	]*62 a3 2d 00 44 9c f0 34 12 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%xmm26,%xmm19
+[ 	]*[a-f0-9]+:[ 	]*62 e3 2d 00 44 5a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm26,%xmm19
+[ 	]*[a-f0-9]+:[ 	]*62 83 15 20 44 fb ab[ 	]*vpclmulqdq \$0xab,%ymm27,%ymm29,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 a3 15 20 44 bc f0 34 12 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm29,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 e3 15 20 44 7a 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 a3 2d 00 44 dc ab[ 	]*vpclmulqdq \$0xab,%xmm20,%xmm26,%xmm19
+[ 	]*[a-f0-9]+:[ 	]*62 a3 2d 00 44 9c f0 34 12 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%xmm26,%xmm19
+[ 	]*[a-f0-9]+:[ 	]*62 e3 2d 00 44 5a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm26,%xmm19
+[ 	]*[a-f0-9]+:[ 	]*62 83 15 20 44 fb ab[ 	]*vpclmulqdq \$0xab,%ymm27,%ymm29,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 a3 15 20 44 bc f0 34 12 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm29,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 e3 15 20 44 7a 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm23
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s
new file mode 100644
index 0000000..5794726
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s
@@ -0,0 +1,33 @@
+# Check 64bit AVX512VL,VPCLMULQDQ instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vpclmulqdq	$0xab, %xmm18, %xmm29, %xmm25	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, 0x123(%rax,%r14,8), %xmm29, %xmm25	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, 2032(%rdx), %xmm29, %xmm25	 # AVX512VL,VPCLMULQDQ Disp8
+	vpclmulqdq	$0xab, %ymm18, %ymm18, %ymm29	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, 0x123(%rax,%r14,8), %ymm18, %ymm29	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	$123, 4064(%rdx), %ymm18, %ymm29	 # AVX512VL,VPCLMULQDQ Disp8
+
+	{evex} vpclmulqdq	$0xab, %xmm18, %xmm29, %xmm25	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, 0x123(%rax,%r14,8), %xmm29, %xmm25	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, 2032(%rdx), %xmm29, %xmm25	 # AVX512VL,VPCLMULQDQ Disp8
+	{evex} vpclmulqdq	$0xab, %ymm18, %ymm18, %ymm29	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, 0x123(%rax,%r14,8), %ymm18, %ymm29	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	$123, 4064(%rdx), %ymm18, %ymm29	 # AVX512VL,VPCLMULQDQ Disp8
+
+	.intel_syntax noprefix
+	vpclmulqdq	xmm19, xmm26, xmm20, 0xab	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	xmm19, xmm26, XMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	xmm19, xmm26, XMMWORD PTR [rdx+2032], 123	 # AVX512VL,VPCLMULQDQ Disp8
+	vpclmulqdq	ymm23, ymm29, ymm27, 0xab	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	ymm23, ymm29, YMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512VL,VPCLMULQDQ
+	vpclmulqdq	ymm23, ymm29, YMMWORD PTR [rdx+4064], 123	 # AVX512VL,VPCLMULQDQ Disp8
+
+	{evex} vpclmulqdq	xmm19, xmm26, xmm20, 0xab	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	xmm19, xmm26, XMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	xmm19, xmm26, XMMWORD PTR [rdx+2032], 123	 # AVX512VL,VPCLMULQDQ Disp8
+	{evex} vpclmulqdq	ymm23, ymm29, ymm27, 0xab	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	ymm23, ymm29, YMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512VL,VPCLMULQDQ
+	{evex} vpclmulqdq	ymm23, ymm29, YMMWORD PTR [rdx+4064], 123	 # AVX512VL,VPCLMULQDQ Disp8
diff --git a/gas/testsuite/gas/i386/x86-64-vpclmulqdq-intel.d b/gas/testsuite/gas/i386/x86-64-vpclmulqdq-intel.d
new file mode 100644
index 0000000..3b09b1a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-vpclmulqdq-intel.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 VPCLMULQDQ insns (Intel disassembly)
+#source: x86-64-vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 03 15 20 44 f4 ab[ 	]*vpclmulqdq ymm30,ymm29,ymm28,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 23 15 20 44 b4 f0 24 01 00 00 7b[ 	]*vpclmulqdq ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x124\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 15 20 44 72 7f 7b[ 	]*vpclmulqdq ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 03 15 20 44 f4 ab[ 	]*vpclmulqdq ymm30,ymm29,ymm28,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 23 15 20 44 b4 f0 34 12 00 00 7b[ 	]*vpclmulqdq ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 15 20 44 72 7f 7b[ 	]*vpclmulqdq ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-vpclmulqdq.d b/gas/testsuite/gas/i386/x86-64-vpclmulqdq.d
new file mode 100644
index 0000000..bb85cb8
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-vpclmulqdq.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -dw
+#name: x86_64 VPCLMULQDQ insns
+#source: x86-64-vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 03 15 20 44 f4 ab[ 	]*vpclmulqdq \$0xab,%ymm28,%ymm29,%ymm30
+[ 	]*[a-f0-9]+:[ 	]*62 23 15 20 44 b4 f0 24 01 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x124\(%rax,%r14,8\),%ymm29,%ymm30
+[ 	]*[a-f0-9]+:[ 	]*62 63 15 20 44 72 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm30
+[ 	]*[a-f0-9]+:[ 	]*62 03 15 20 44 f4 ab[ 	]*vpclmulqdq \$0xab,%ymm28,%ymm29,%ymm30
+[ 	]*[a-f0-9]+:[ 	]*62 23 15 20 44 b4 f0 34 12 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm29,%ymm30
+[ 	]*[a-f0-9]+:[ 	]*62 63 15 20 44 72 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm30
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-vpclmulqdq.s b/gas/testsuite/gas/i386/x86-64-vpclmulqdq.s
new file mode 100644
index 0000000..a4d109f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-vpclmulqdq.s
@@ -0,0 +1,13 @@
+
+
+	.allow_index_reg
+	.text
+_start:
+	vpclmulqdq	$0xab, %ymm28, %ymm29, %ymm30
+	vpclmulqdq	$123, 0x124(%rax,%r14,8), %ymm29, %ymm30
+	vpclmulqdq	$123, 4064(%rdx), %ymm29, %ymm30
+
+	.intel_syntax noprefix
+	vpclmulqdq	ymm30, ymm29, ymm28, 0xab
+	vpclmulqdq	ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234], 123
+	vpclmulqdq	ymm30, ymm29, YMMWORD PTR [rdx+4064], 123
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index e72c472..ef5c963 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -662,7 +662,7 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { PREFIX_TABLE (PREFIX_EVEX_0F3A42) },
     { PREFIX_TABLE (PREFIX_EVEX_0F3A43) },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_0F3A44) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
@@ -2779,6 +2779,12 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F3A43_P_2) },
   },
+  /* PREFIX_EVEX_0F3A44 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "vpclmulqdq",	{ XM, Vex, EXx, Ib }, 0 },
+  },
   /* PREFIX_EVEX_0F3A50 */
   {
     { Bad_Opcode },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index fe9fcd9..7f3b18f 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1701,6 +1701,7 @@ enum
   PREFIX_EVEX_0F3A3F,
   PREFIX_EVEX_0F3A42,
   PREFIX_EVEX_0F3A43,
+  PREFIX_EVEX_0F3A44,
   PREFIX_EVEX_0F3A50,
   PREFIX_EVEX_0F3A51,
   PREFIX_EVEX_0F3A54,
@@ -1902,7 +1903,6 @@ enum
   VEX_LEN_0F3A38_P_2,
   VEX_LEN_0F3A39_P_2,
   VEX_LEN_0F3A41_P_2,
-  VEX_LEN_0F3A44_P_2,
   VEX_LEN_0F3A46_P_2,
   VEX_LEN_0F3A60_P_2,
   VEX_LEN_0F3A61_P_2,
@@ -2220,7 +2220,6 @@ enum
   VEX_W_0F3A40_P_2,
   VEX_W_0F3A41_P_2,
   VEX_W_0F3A42_P_2,
-  VEX_W_0F3A44_P_2,
   VEX_W_0F3A46_P_2,
   VEX_W_0F3A48_P_2,
   VEX_W_0F3A49_P_2,
@@ -6693,7 +6692,7 @@ static const struct dis386 prefix_table[][4] = {
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
+    { "vpclmulqdq",	{ XM, Vex, EXx, PCLMUL }, 0 },
   },
 
   /* PREFIX_VEX_0F3A46 */
@@ -10110,11 +10109,6 @@ static const struct dis386 vex_len_table[][2] = {
     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
   },
 
-  /* VEX_LEN_0F3A44_P_2 */
-  {
-    { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
-  },
-
   /* VEX_LEN_0F3A46_P_2 */
   {
     { Bad_Opcode },
@@ -11429,10 +11423,6 @@ static const struct dis386 vex_w_table[][2] = {
     { "vmpsadbw",	{ XM, Vex, EXx, Ib }, 0 },
   },
   {
-    /* VEX_W_0F3A44_P_2 */
-    { "vpclmulqdq",	{ XM, Vex128, EXx, PCLMUL }, 0 },
-  },
-  {
     /* VEX_W_0F3A46_P_2 */
     { "vperm2i128",	{ XM, Vex256, EXx, Ib }, 0 },
   },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 47a9ddb..c04b364 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -271,6 +271,8 @@ static initializer cpu_flag_init[] =
     "CpuGFNI" },
   { "CPU_VAES_FLAGS",
     "CpuVAES" },
+  { "CPU_VPCLMULQDQ_FLAGS",
+    "CpuVPCLMULQDQ" },
   { "CPU_ANY_X87_FLAGS",
     "CPU_ANY_287_FLAGS|Cpu8087" },
   { "CPU_ANY_287_FLAGS",
@@ -538,6 +540,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuCET),
   BITFIELD (CpuGFNI),
   BITFIELD (CpuVAES),
+  BITFIELD (CpuVPCLMULQDQ),
   BITFIELD (CpuRegMMX),
   BITFIELD (CpuRegXMM),
   BITFIELD (CpuRegYMM),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index c6c3f66..a14f66d 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -216,6 +216,8 @@ enum
   CpuGFNI,
   /* VAES instructions required */
   CpuVAES,
+  /* VPCLMULQDQ instructions required */
+  CpuVPCLMULQDQ,
   /* MMX register support required */
   CpuRegMMX,
   /* XMM register support required */
@@ -241,7 +243,7 @@ enum
 
 /* If you get a compiler error for zero width of the unused field,
    comment it out.  */
-#define CpuUnused	(CpuMax + 1)
+ #define CpuUnused	(CpuMax + 1)
 
 /* We can check if an instruction is available with array instead
    of bitfield. */
@@ -341,6 +343,7 @@ typedef union i386_cpu_flags
       unsigned int cpucet:1;
       unsigned int cpugfni:1;
       unsigned int cpuvaes:1;
+      unsigned int cpuvpclmulqdq:1;
       unsigned int cpuregmmx:1;
       unsigned int cpuregxmm:1;
       unsigned int cpuregymm:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 1511bdc..0dcc17b 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3122,6 +3122,12 @@ sha256rnds2, 2, 0xf38cb, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lS
 sha256msg1, 2, 0xf38cc, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
 sha256msg2, 2, 0xf38cd, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
 
+// VPCLMULQDQ instructions
+
+vpclmulqdq, 4, 0x6644, None, 1, CpuVPCLMULQDQ, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+
+// VPCLMULQDQ instructions end
+
 // AVX512F instructions.
 
 kandnw, 3, 0x42, None, 1, CpuAVX512F, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
@@ -6102,6 +6108,14 @@ vaesenclast, 3, 0x66dd, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=3|VexOpcode=1|V
 
 // AVX512 + VAES instructions end
 
+// AVX512 + VPCLMULQDQ instructions
+
+vpclmulqdq, 4, 0x6644, None, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|EVex=1|VexOpcode=2|VexVVVV=1|VecESize=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
+vpclmulqdq, 4, 0x6644, None, 1, CpuVPCLMULQDQ|CpuAVX512VL, Modrm|EVex=2|VexOpcode=2|VexVVVV=1|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
+vpclmulqdq, 4, 0x6644, None, 1, CpuVPCLMULQDQ|CpuAVX512VL, Modrm|EVex=3|VexOpcode=2|VexVVVV=1|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
+
+// AVX512 + VPCLMULQDQ instructions end
+
 // CLZERO instructions
 
 clzero, 0, 0xf01fc, None, 3, CpuCLZERO, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }