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authorVladimir Prus <vladimir@codesourcery.com>2008-08-19 12:31:35 +0000
committerVladimir Prus <vladimir@codesourcery.com>2008-08-19 12:31:35 +0000
commitaeac0ff9c2b0734cd9b0ce4ee0af9e9169c8dc6b (patch)
tree25b3f4a795322a49f7a335ddcb64a54b75317729
parentbfb8797a0171b72def4c2d5b2817c0d696333a83 (diff)
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* doc/gdb.texinfo (PowerPC): Fix typo.
(PowerPC features): Fix typo.
-rw-r--r--gdb/doc/ChangeLog5
-rw-r--r--gdb/doc/gdb.texinfo4
2 files changed, 7 insertions, 2 deletions
diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog
index e048b90..e76952e 100644
--- a/gdb/doc/ChangeLog
+++ b/gdb/doc/ChangeLog
@@ -1,3 +1,8 @@
+2008-08-19 Vladimir Prus <vladimir@codesourcery.com>
+
+ * doc/gdb.texinfo (PowerPC): Fix typo.
+ (PowerPC features): Fix typo.
+
2008-08-18 Pedro Alves <pedro@codesourcery.com>
* observer.texi (thread_ptid_changed): New.
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index 61c2917..21648b7 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -16427,7 +16427,7 @@ The pseudo-registers go from @code{$dl0} through @code{$dl15}, and are formed
by joining the even/odd register pairs @code{f0} and @code{f1} for @code{$dl0},
@code{f2} and @code{f3} for @code{$dl1} and so on.
-For POWER7 processors, @value{GDB} provides a set of pseudo-registers, the 64-bit
+For POWER7 processors, @value{GDBN} provides a set of pseudo-registers, the 64-bit
wide Extended Floating Point Registers (@samp{f32} through @samp{f63}).
@@ -27872,7 +27872,7 @@ The @samp{org.gnu.gdb.power.vsx} feature is optional. It should
contain registers @samp{vs0h} through @samp{vs31h}. @value{GDBN}
will combine these registers with the floating point registers
(@samp{f0} through @samp{f31}) and the altivec registers (@samp{vr0}
-through @samp{vr31}} to present the 128-bit wide registers @samp{vs0}
+through @samp{vr31}) to present the 128-bit wide registers @samp{vs0}
through @samp{vs63}, the set of vector registers for POWER7.
The @samp{org.gnu.gdb.power.spe} feature is optional. It should