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author | Mike Frysinger <vapier@gentoo.org> | 2015-06-09 23:44:13 +0800 |
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committer | Mike Frysinger <vapier@gentoo.org> | 2015-06-11 10:17:54 -0400 |
commit | a84f8df0e2027400910e339824444dc45ba6e4f4 (patch) | |
tree | f6911f9661b3245d35197aaf03b96caa5a0a2545 | |
parent | 926b1cd8cffbcd8cf2d37e779463a4e7e696f73b (diff) | |
download | gdb-a84f8df0e2027400910e339824444dc45ba6e4f4.zip gdb-a84f8df0e2027400910e339824444dc45ba6e4f4.tar.gz gdb-a84f8df0e2027400910e339824444dc45ba6e4f4.tar.bz2 |
sim: m68hc11: switch to common sim_resume
This code already matched the common sim reusme logic, so we can simply
drop it and pull in the common code.
-rw-r--r-- | sim/m68hc11/ChangeLog | 5 | ||||
-rw-r--r-- | sim/m68hc11/Makefile.in | 3 | ||||
-rw-r--r-- | sim/m68hc11/interp.c | 76 |
3 files changed, 7 insertions, 77 deletions
diff --git a/sim/m68hc11/ChangeLog b/sim/m68hc11/ChangeLog index ac228b8..8621ce4 100644 --- a/sim/m68hc11/ChangeLog +++ b/sim/m68hc11/ChangeLog @@ -1,5 +1,10 @@ 2015-06-11 Mike Frysinger <vapier@gentoo.org> + * Makefile.in (SIM_OBJS): Add sim-resume.o + * interp.c (has_stepped, sim_resume): Delete. + +2015-06-11 Mike Frysinger <vapier@gentoo.org> + * interp.c (INLINE): Delete define. 2015-04-29 Nick Clifton <nickc@redhat.com> diff --git a/sim/m68hc11/Makefile.in b/sim/m68hc11/Makefile.in index 9b931a1..98b811a 100644 --- a/sim/m68hc11/Makefile.in +++ b/sim/m68hc11/Makefile.in @@ -25,7 +25,8 @@ SIM_OBJS = $(M68HC11_OBJS) \ sim-load.o \ sim-hload.o \ sim-stop.o \ - sim-reason.o + sim-reason.o \ + sim-resume.o SIM_PROFILE= -DPROFILE=1 -DWITH_PROFILE=-1 # We must use 32-bit addresses to support memory bank switching. diff --git a/sim/m68hc11/interp.c b/sim/m68hc11/interp.c index e9f3aab..14a8231 100644 --- a/sim/m68hc11/interp.c +++ b/sim/m68hc11/interp.c @@ -699,79 +699,3 @@ sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length) return 2; } - -/* Halt the simulator after just one instruction */ - -static void -has_stepped (SIM_DESC sd, - void *data) -{ - ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); - sim_engine_halt (sd, NULL, NULL, NULL_CIA, sim_stopped, SIM_SIGTRAP); -} - - -/* Generic resume - assumes the existance of sim_engine_run */ - -void -sim_resume (SIM_DESC sd, - int step, - int siggnal) -{ - sim_engine *engine = STATE_ENGINE (sd); - jmp_buf buf; - int jmpval; - - ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); - - /* we only want to be single stepping the simulator once */ - if (engine->stepper != NULL) - { - sim_events_deschedule (sd, engine->stepper); - engine->stepper = NULL; - } - sim_module_resume (sd); - - /* run/resume the simulator */ - engine->jmpbuf = &buf; - jmpval = setjmp (buf); - if (jmpval == sim_engine_start_jmpval - || jmpval == sim_engine_restart_jmpval) - { - int last_cpu_nr = sim_engine_last_cpu_nr (sd); - int next_cpu_nr = sim_engine_next_cpu_nr (sd); - int nr_cpus = sim_engine_nr_cpus (sd); - - sim_events_preprocess (sd, last_cpu_nr >= nr_cpus, next_cpu_nr >= nr_cpus); - if (next_cpu_nr >= nr_cpus) - next_cpu_nr = 0; - - /* Only deliver the siggnal ]sic] the first time through - don't - re-deliver any siggnal during a restart. */ - if (jmpval == sim_engine_restart_jmpval) - siggnal = 0; - - /* Install the stepping event after having processed some - pending events. This is necessary for HC11/HC12 simulator - because the tick counter is incremented by the number of cycles - the instruction took. Some pending ticks to process can still - be recorded internally by the simulator and sim_events_preprocess - will handle them. If the stepping event is inserted before, - these pending ticks will raise the event and the simulator will - stop without having executed any instruction. */ - if (step) - engine->stepper = sim_events_schedule (sd, 0, has_stepped, sd); - -#ifdef SIM_CPU_EXCEPTION_RESUME - { - sim_cpu* cpu = STATE_CPU (sd, next_cpu_nr); - SIM_CPU_EXCEPTION_RESUME(sd, cpu, siggnal); - } -#endif - - sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal); - } - engine->jmpbuf = NULL; - - sim_module_suspend (sd); -} |