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| author | Richard Sandiford <richard.sandiford@arm.com> | 2017-02-15 16:51:17 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2017-02-15 16:51:17 +0000 |
| commit | 7a2114e7a4ee1fbb5a0611733c72a2a7acc733c7 (patch) | |
| tree | 1637dd6b3eafa526adb1c65558cd92a4f4007a56 | |
| parent | ebf0b03c706b28c990f5f3c6713dacd23f58341e (diff) | |
| download | gdb-7a2114e7a4ee1fbb5a0611733c72a2a7acc733c7.zip gdb-7a2114e7a4ee1fbb5a0611733c72a2a7acc733c7.tar.gz gdb-7a2114e7a4ee1fbb5a0611733c72a2a7acc733c7.tar.bz2 | |
[AArch64] Fix +sve documentation
The documentation entry for the SVE feature incorrectly said that
it was enabled by default for ARMv8-A or later. This patch fixes
that and also mentions that +sve implies +simd. (It also implies
+fp, but that follows by transitivity.)
gas/
* doc/c-aarch64.texi: Fix sve entry.
| -rw-r--r-- | gas/ChangeLog | 4 | ||||
| -rw-r--r-- | gas/doc/c-aarch64.texi | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 1844085..1a2949c 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,7 @@ +2017-02-15 Richard Sandiford <richard.sandiford@arm.com> + + * doc/c-aarch64.texi: Fix sve entry. + 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (md_convert_frag): Remove @pcl relocation diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 618f300..59467c5 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -155,8 +155,8 @@ automatically cause those extensions to be disabled. @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}. @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later @tab Enable Advanced SIMD extensions. This implies @code{fp}. -@item @code{sve} @tab ARMv8-A @tab ARMv8-A or later - @tab Enable the Scalable Vector Extensions. +@item @code{sve} @tab ARMv8-A @tab No + @tab Enable the Scalable Vector Extensions. This implies @code{simd}. @end multitable @node AArch64 Syntax |