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authorH.J. Lu <hjl.tools@gmail.com>2007-09-18 00:56:54 +0000
committerH.J. Lu <hjl.tools@gmail.com>2007-09-18 00:56:54 +0000
commit20e192ab8df5502cd405ffd7fe5161985b8a2373 (patch)
tree180111f0d0c494e969ed6a5adedc769f6df0442a
parentb10a8ae01c27969e5104f76209272fb457c1e20b (diff)
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gas/
2007-09-17 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (baseindex): Removed. (build_modrm_byte): Check reg_num for RIP register instead of reg_type. (i386_index_check): Likewise. opcodes/ 2007-09-17 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (RegRip): New. * i386-reg.tbl (rip): Use RegRip for reg_num. * i386-tbl.h: Regenerated.
-rw-r--r--gas/ChangeLog7
-rw-r--r--gas/config/tc-i386.c5
-rw-r--r--opcodes/ChangeLog7
-rw-r--r--opcodes/i386-opc.h1
-rw-r--r--opcodes/i386-reg.tbl2
-rw-r--r--opcodes/i386-tbl.h2
6 files changed, 19 insertions, 5 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index c62639e..81b5fdc 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,12 @@
2007-09-17 H.J. Lu <hongjiu.lu@intel.com>
+ * config/tc-i386.c (baseindex): Removed.
+ (build_modrm_byte): Check reg_num for RIP register instead of
+ reg_type.
+ (i386_index_check): Likewise.
+
+2007-09-17 H.J. Lu <hongjiu.lu@intel.com>
+
PR gas/5035
* config/obj-coff.c (obj_coff_endef): Remove checking size of
def_symbol_in_progress.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 5453a00..17bde04 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1098,7 +1098,6 @@ static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP;
-static const i386_operand_type baseindex = OPERAND_TYPE_BASEINDEX;
static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
@@ -4541,7 +4540,7 @@ build_modrm_byte (void)
}
}
/* RIP addressing for 64bit mode. */
- else if (UINTS_EQUAL (i.base_reg->reg_type, baseindex))
+ else if (i.base_reg->reg_num == RegRip)
{
i.rm.regmem = NO_BASE_REGISTER;
i.types[op].bitfield.disp8 = 0;
@@ -5977,7 +5976,7 @@ i386_index_check (const char *operand_string)
|| (i.prefix[ADDR_PREFIX]
&& !i.base_reg->reg_type.bitfield.reg32))
&& (i.index_reg
- || !UINTS_EQUAL (i.base_reg->reg_type, baseindex)))
+ || i.base_reg->reg_num != RegRip))
|| (i.index_reg
&& (!i.index_reg->reg_type.bitfield.baseindex
|| (i.prefix[ADDR_PREFIX] == 0
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a4abe95..2fea362 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2007-09-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.h (RegRip): New.
+
+ * i386-reg.tbl (rip): Use RegRip for reg_num.
+ * i386-tbl.h: Regenerated.
+
2007-09-17 Nick Clifton <nickc@redhat.com>
* po/es.po: Updated Spanish translation.
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 8a4f15b..00fbe1c 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -443,6 +443,7 @@ typedef struct
#define RegRex 0x1 /* Extended register. */
#define RegRex64 0x2 /* Extended 8 bit register. */
unsigned int reg_num;
+#define RegRip ((unsigned int ) ~0)
}
reg_entry;
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl
index a5103e1..28debd7 100644
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -189,7 +189,7 @@ xmm14, RegXMM, RegRex, 6
xmm15, RegXMM, RegRex, 7
// No type will make this register rejected for all purposes except
// for addressing. This saves creating one extra type for RIP.
-rip, BaseIndex, 0, 0
+rip, BaseIndex, 0, RegRip
// fp regs.
st(0), FloatReg|FloatAcc, 0, 0
st(1), FloatReg, 0, 1
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 792a186..2f18422 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -13278,7 +13278,7 @@ const reg_entry i386_regtab[] =
{ "rip",
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
- 0, 0 },
+ 0, RegRip },
{ "st(0)",
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 } },