[ARC] Misc minor edits/fixes

The code supporting -mspfp, -mdpfp, and -mfpuda options are in
sections of code that are commented as being for backward
compatibility only, and having no effect. However, they do have an
effect, enabling the SPX, DPX, and DPA instruction subclasses
respectively. This commit moves the code supporting these options
away from the comments indicating that they are dummy options, and
also fixes a small issue where -mnps400 had the additional effect
of enabling SPX instructions.

A couple of other minor edits (that make no functional change) are
also included.

gas/ChangeLog:

        * config/tc-arc.c (options, md_longopts, md_parse_option):
        Move -mspfp, -mdpfp and -mfpuda out of the sections for
        dummy options. Correct erroneous enabling of SPFP
        instructions when using -mnps400.

include/ChangeLog:

        * opcode/arc.h: Make insn_class_t alphabetical again.

opcodes/ChangeLog:

        * arc-opc.c: Correct description of availability of NPS400
        features.

6 files changed, 57 insertions, 42 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index ec4ad68..66c3607 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2016-06-23  Graham Markall  <graham.markall@embecosm.com>
+
+	* config/tc-arc.c (options, md_longopts, md_parse_option): Move
+	-mspfp, -mdpfp and -mfpuda out of the sections for dummy
+	options. Correct erroneous enabling of SPFP instructions when
+	using -mnps400.
+
 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 
 	* testsuite/gas/ppc/power9.d <brd, brh, brw, mffs, mffs., mffsce,
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 34d58a1..5755821 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -182,6 +182,10 @@ enum options
   OPTION_RELAX,
   OPTION_NPS400,
 
+  OPTION_SPFP,
+  OPTION_DPFP,
+  OPTION_FPUDA,
+
   /* The following options are deprecated and provided here only for
      compatibility reasons.  */
   OPTION_USER_MODE,
@@ -194,8 +198,6 @@ enum options
   OPTION_EA,
   OPTION_MUL64,
   OPTION_SIMD,
-  OPTION_SPFP,
-  OPTION_DPFP,
   OPTION_XMAC_D16,
   OPTION_XMAC_24,
   OPTION_DSP_PACKA,
@@ -205,8 +207,7 @@ enum options
   OPTION_XYMEMORY,
   OPTION_LOCK,
   OPTION_SWAPE,
-  OPTION_RTSC,
-  OPTION_FPUDA
+  OPTION_RTSC
 };
 
 struct option md_longopts[] =
@@ -225,6 +226,19 @@ struct option md_longopts[] =
   { "mrelax",           no_argument,       NULL, OPTION_RELAX },
   { "mnps400",          no_argument,       NULL, OPTION_NPS400 },
 
+  /* Floating point options */
+  { "mspfp", no_argument, NULL, OPTION_SPFP},
+  { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
+  { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
+  { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
+  { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
+  { "mdpfp", no_argument, NULL, OPTION_DPFP},
+  { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
+  { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
+  { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
+  { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
+  { "mfpuda", no_argument, NULL, OPTION_FPUDA},
+
   /* The following options are deprecated and provided here only for
      compatibility reasons.  */
   { "mav2em", no_argument, NULL, OPTION_ARCEM },
@@ -242,16 +256,6 @@ struct option md_longopts[] =
   { "mEA", no_argument, NULL, OPTION_EA },
   { "mmul64", no_argument, NULL, OPTION_MUL64 },
   { "msimd", no_argument, NULL, OPTION_SIMD},
-  { "mspfp", no_argument, NULL, OPTION_SPFP},
-  { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
-  { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
-  { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
-  { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
-  { "mdpfp", no_argument, NULL, OPTION_DPFP},
-  { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
-  { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
-  { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
-  { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
   { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
   { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
   { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
@@ -265,7 +269,6 @@ struct option md_longopts[] =
   { "mlock", no_argument, NULL, OPTION_LOCK},
   { "mswape", no_argument, NULL, OPTION_SWAPE},
   { "mrtsc", no_argument, NULL, OPTION_RTSC},
-  { "mfpuda", no_argument, NULL, OPTION_FPUDA},
 
   { NULL,		no_argument, NULL, 0 }
 };
@@ -3294,7 +3297,7 @@ arc_parse_name (const char *name,
    -mrelax                       Enable relaxation
 
    The following CPU names are recognized:
-   arc700, av2em, av2hs.  */
+   arc600, arc700, arcem, archs, nps400.  */
 
 int
 md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
@@ -3345,7 +3348,25 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
 
     case OPTION_NPS400:
       arc_features |= ARC_NPS400;
+      break;
 
+    case OPTION_SPFP:
+      arc_features |= ARC_SPFP;
+      break;
+
+    case OPTION_DPFP:
+      arc_features |= ARC_DPFP;
+      break;
+
+    case OPTION_FPUDA:
+      /* This option has an effect only on ARC EM.  */
+      if (arc_target & ARC_OPCODE_ARCv2EM)
+	arc_features |= ARC_FPUDA;
+      else
+	as_warn (_("FPUDA invalid for selected CPU"));
+      break;
+
+    /* Dummy options are accepted but have no effect.  */
     case OPTION_USER_MODE:
     case OPTION_LD_EXT_MASK:
     case OPTION_SWAP:
@@ -3356,17 +3377,6 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
     case OPTION_EA:
     case OPTION_MUL64:
     case OPTION_SIMD:
-      /* Dummy options are accepted but have no effect.  */
-      break;
-
-    case OPTION_SPFP:
-      arc_features |= ARC_SPFP;
-      break;
-
-    case OPTION_DPFP:
-      arc_features |= ARC_DPFP;
-      break;
-
     case OPTION_XMAC_D16:
     case OPTION_XMAC_24:
     case OPTION_DSP_PACKA:
@@ -3377,15 +3387,6 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
     case OPTION_LOCK:
     case OPTION_SWAPE:
     case OPTION_RTSC:
-      /* Dummy options are accepted but have no effect.  */
-      break;
-
-    case OPTION_FPUDA:
-      /* This option has an effect only on ARC EM.  */
-      if (arc_target & ARC_OPCODE_ARCv2EM)
-	arc_features |= ARC_FPUDA;
-      else
-	as_warn (_("FPUDA invalid for selected CPU"));
       break;
 
     default:
diff --git a/include/ChangeLog b/include/ChangeLog
index 72101bc..1ba3ea5 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2016-06-23  Graham Markall  <graham.markall@embecosm.com>
+
+	* opcode/arc.h: Make insn_class_t alphabetical again.
+
 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 
 	* elf/dlx.h: Wrap in extern C.
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index df89e3c..f0fefbbc 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -39,10 +39,13 @@ extern "C" {
 /* Instruction Class.  */
 typedef enum
   {
+    ACL,
     ARITH,
     AUXREG,
+    BITOP,
     BRANCH,
     CONTROL,
+    DPI,
     DSP,
     FLOAT,
     INVALID,
@@ -50,10 +53,7 @@ typedef enum
     KERNEL,
     LOGICAL,
     MEMORY,
-    BITOP,
     NET,
-    ACL,
-    DPI,
   } insn_class_t;
 
 /* Instruction Subclass.  */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b510736..c9cf9ed 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2016-06-23  Graham Markall  <graham.markall@embecosm.com>
+
+	* arc-opc.c: Correct description of availability of NPS400
+	features.
+
 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 
 	* ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index df18167..ad50ebc 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -27,9 +27,7 @@
 #include "libiberty.h"
 
 /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
-   instructions.  Support for this target is available when binutils is
-   configured and built for the 'arc*-mellanox-*-*' target.  As far as
-   possible all ARC NPS400 features are built into all ARC target builds as
+   instructions. All NPS400 features are built into all ARC target builds as
    this reduces the chances that regressions might creep in.  */
 
 /* Insert RB register into a 32-bit opcode.  */