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| author | Lifang Xia <lifang_xia@c-sky.com> | 2021-04-15 10:51:14 +0800 |
|---|---|---|
| committer | Lifang Xia <lifang_xia@c-sky.com> | 2021-04-16 11:25:15 +0800 |
| commit | a8ab20932084328fb48930c028b60a348c6644b3 (patch) | |
| tree | a65f0a2cac4ebfa15f49f757ae66a319830b0408 | |
| parent | ad7c46164f2d558be9f34c1902430259eb00e62b (diff) | |
| download | gdb-a8ab20932084328fb48930c028b60a348c6644b3.zip gdb-a8ab20932084328fb48930c028b60a348c6644b3.tar.gz gdb-a8ab20932084328fb48930c028b60a348c6644b3.tar.bz2 | |
RISC-V: compress "addi d,CV,z" to "c.mv d,CV"
PR 27732
gas/
* testsuite/gas/riscv/c-zero-imm.d: Compress addi a4,a4,0 to
c.mv a4,a4.
* testsuite/gas/riscv/c-zero-imm.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
"addi d,CV,z" to "c.mv d,CV".
| -rw-r--r-- | gas/testsuite/gas/riscv/c-zero-imm.d | 16 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/c-zero-imm.s | 2 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 1 |
3 files changed, 10 insertions, 9 deletions
diff --git a/gas/testsuite/gas/riscv/c-zero-imm.d b/gas/testsuite/gas/riscv/c-zero-imm.d index 97b845d..1f3e485 100644 --- a/gas/testsuite/gas/riscv/c-zero-imm.d +++ b/gas/testsuite/gas/riscv/c-zero-imm.d @@ -12,12 +12,12 @@ Disassembly of section .text: [ ]+4:[ ]+8a01[ ]+andi[ ]+a2,a2,0 [ ]+6:[ ]+8a81[ ]+andi[ ]+a3,a3,0 [ ]+8:[ ]+0001[ ]+nop -[ ]+a:[ ]+00070713[ ]+mv[ ]+a4,a4 -[ ]+e:[ ]+0781[ ]+addi[ ]+a5,a5,0 -[ ]+10:[ ]+00051513[ ]+slli[ ]+a0,a0,0x0 -[ ]+14:[ ]+0005d593[ ]+srli[ ]+a1,a1,0x0 -[ ]+18:[ ]+40065613[ ]+srai[ ]+a2,a2,0x0 -[ ]+1c:[ ]+0682[ ]+c.slli64[ ]+a3 -[ ]+1e:[ ]+8301[ ]+c.srli64[ ]+a4 -[ ]+20:[ ]+8781[ ]+c.srai64[ ]+a5 +[ ]+a:[ ]+873a[ ]+mv[ ]+a4,a4 +[ ]+c:[ ]+0781[ ]+addi[ ]+a5,a5,0 +[ ]+e:[ ]+00051513[ ]+slli[ ]+a0,a0,0x0 +[ ]+12:[ ]+0005d593[ ]+srli[ ]+a1,a1,0x0 +[ ]+16:[ ]+40065613[ ]+srai[ ]+a2,a2,0x0 +[ ]+1a:[ ]+0682[ ]+c.slli64[ ]+a3 +[ ]+1c:[ ]+8301[ ]+c.srli64[ ]+a4 +[ ]+1e:[ ]+8781[ ]+c.srai64[ ]+a5 #... diff --git a/gas/testsuite/gas/riscv/c-zero-imm.s b/gas/testsuite/gas/riscv/c-zero-imm.s index b0f4710..62c3e1a 100644 --- a/gas/testsuite/gas/riscv/c-zero-imm.s +++ b/gas/testsuite/gas/riscv/c-zero-imm.s @@ -5,7 +5,7 @@ andi a2,a2,0 c.andi a3,0 addi x0,x0,0 - # Don't let this compress to a hint. + # compress to c.mv. addi a4,a4,0 # These are hints. c.addi a5,0 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 1348ec7..f55a01b 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -276,6 +276,7 @@ const struct riscv_opcode riscv_opcodes[] = {"addi", 0, INSN_CLASS_C, "d,CU,z", MATCH_C_NOP, MASK_C_ADDI|MASK_RVC_IMM, match_c_nop, INSN_ALIAS }, {"addi", 0, INSN_CLASS_C, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, {"addi", 0, INSN_CLASS_C, "d,Cz,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS }, +{"addi", 0, INSN_CLASS_C, "d,CV,z", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, {"addi", 0, INSN_CLASS_I, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 }, {"add", 0, INSN_CLASS_C, "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, {"add", 0, INSN_CLASS_C, "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, |