aarch64: [SME] Add new SME system registers

This patch is adding miscellaneous SME related system registers.

gas/ChangeLog:

	* testsuite/gas/aarch64/sme-sysreg.d: New test.
	* testsuite/gas/aarch64/sme-sysreg.s: New test.
	* testsuite/gas/aarch64/sme-sysreg-illegal.d: New test.
	* testsuite/gas/aarch64/sme-sysreg-illegal.l: New test.
	* testsuite/gas/aarch64/sme-sysreg-illegal.s: New test.

opcodes/ChangeLog:

	* aarch64-opc.c: New system registers id_aa64smfr0_el1,
	smcr_el1, smcr_el12, smcr_el2, smcr_el3, smpri_el1,
	smprimap_el2, smidr_el1, tpidr2_el0 and mpamsm_el1.

6 files changed, 72 insertions, 1 deletions

diff --git a/gas/testsuite/gas/aarch64/sme-sysreg-illegal.d b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.d
new file mode 100644
index 0000000..ff0e855
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sme-sysreg-illegal.s
+#warning_output: sme-sysreg-illegal.l
diff --git a/gas/testsuite/gas/aarch64/sme-sysreg-illegal.l b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.l
new file mode 100644
index 0000000..6baad13
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.l
@@ -0,0 +1,3 @@
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Warning: specified register cannot be written to at operand 1 -- `msr id_aa64smfr0_el1,x0'
+[^:]*:[0-9]+: Warning: specified register cannot be written to at operand 1 -- `msr smidr_el1,x0'
diff --git a/gas/testsuite/gas/aarch64/sme-sysreg-illegal.s b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.s
new file mode 100644
index 0000000..057a6bf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.s
@@ -0,0 +1,3 @@
+/* Write to r/o SME system registers.  */
+msr id_aa64smfr0_el1, x0
+msr smidr_el1, x0
diff --git a/gas/testsuite/gas/aarch64/sme-sysreg.d b/gas/testsuite/gas/aarch64/sme-sysreg.d
new file mode 100644
index 0000000..8eaf73c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-sysreg.d
@@ -0,0 +1,29 @@
+#name: SME extension (system registers)
+#as: -march=armv8-a+sme
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+   0:	d53b4240 	mrs	x0, svcr
+   4:	d53804a0 	mrs	x0, id_aa64smfr0_el1
+   8:	d53812c0 	mrs	x0, smcr_el1
+   c:	d53d12c0 	mrs	x0, smcr_el12
+  10:	d53c12c0 	mrs	x0, smcr_el2
+  14:	d53e12c0 	mrs	x0, smcr_el3
+  18:	d5381280 	mrs	x0, smpri_el1
+  1c:	d53c12a0 	mrs	x0, smprimap_el2
+  20:	d53900c0 	mrs	x0, smidr_el1
+  24:	d53bd0a0 	mrs	x0, tpidr2_el0
+  28:	d538a560 	mrs	x0, mpamsm_el1
+  2c:	d51b4240 	msr	svcr, x0
+  30:	d51812c0 	msr	smcr_el1, x0
+  34:	d51d12c0 	msr	smcr_el12, x0
+  38:	d51c12c0 	msr	smcr_el2, x0
+  3c:	d51e12c0 	msr	smcr_el3, x0
+  40:	d5181280 	msr	smpri_el1, x0
+  44:	d51c12a0 	msr	smprimap_el2, x0
+  48:	d51bd0a0 	msr	tpidr2_el0, x0
+  4c:	d518a560 	msr	mpamsm_el1, x0
diff --git a/gas/testsuite/gas/aarch64/sme-sysreg.s b/gas/testsuite/gas/aarch64/sme-sysreg.s
new file mode 100644
index 0000000..ce8a294
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-sysreg.s
@@ -0,0 +1,23 @@
+/* Read SME system registers.  */
+mrs x0, svcr
+mrs x0, id_aa64smfr0_el1
+mrs x0, smcr_el1
+mrs x0, smcr_el12
+mrs x0, smcr_el2
+mrs x0, smcr_el3
+mrs x0, smpri_el1
+mrs x0, smprimap_el2
+mrs x0, smidr_el1
+mrs x0, tpidr2_el0
+mrs x0, mpamsm_el1
+
+/* Write to SME system registers.  */
+msr svcr, x0
+msr smcr_el1, x0
+msr smcr_el12, x0
+msr smcr_el2, x0
+msr smcr_el3, x0
+msr smpri_el1, x0
+msr smprimap_el2, x0
+msr tpidr2_el0, x0
+msr mpamsm_el1, x0
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index dba8bcb..923ddef 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4826,7 +4826,17 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   SR_CORE ("gpccr_el3",     CPENC (3,6,C2,C1,6), 0),
   SR_CORE ("gptbr_el3",     CPENC (3,6,C2,C1,4), 0),
 
-  SR_SME ("svcr",           CPENC (3,3,C4,C2,2), 0),
+  SR_SME ("svcr",             CPENC (3,3,C4,C2,2),  0),
+  SR_SME ("id_aa64smfr0_el1", CPENC (3,0,C0,C4,5),  F_REG_READ),
+  SR_SME ("smcr_el1",         CPENC (3,0,C1,C2,6),  0),
+  SR_SME ("smcr_el12",        CPENC (3,5,C1,C2,6),  0),
+  SR_SME ("smcr_el2",         CPENC (3,4,C1,C2,6),  0),
+  SR_SME ("smcr_el3",         CPENC (3,6,C1,C2,6),  0),
+  SR_SME ("smpri_el1",        CPENC (3,0,C1,C2,4),  0),
+  SR_SME ("smprimap_el2",     CPENC (3,4,C1,C2,5),  0),
+  SR_SME ("smidr_el1",        CPENC (3,1,C0,C0,6),  F_REG_READ),
+  SR_SME ("tpidr2_el0",       CPENC (3,3,C13,C0,5), 0),
+  SR_SME ("mpamsm_el1",       CPENC (3,0,C10,C5,3), 0),
 
   { 0, CPENC (0,0,0,0,0), 0, 0 }
 };