[binutils][arm] Implement Custom Datapath Extensions for MVE

Here we implement the custom datapath extensions for MVE.

This required the following changes:

- Adding a new register argument type (that takes either an MVE vector or
  a Neon S or D register).
- Adding two new immediate operands types (0-127 and 0-4095).
- Using the Neon type machinery to distinguish between instruction
  types.  This required the introduction of new neon shapes to account
  for the coprocessor operands to these instructions.
- Adding a new disassembly character to `print_insn_cde` to handle the
  new register types.

Specification can be found at
https://developer.arm.com/docs/ddi0607/latest

Successfully regression tested on arm-none-eabi, and arm-wince-pe.

gas/ChangeLog:

2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for
	instructions that can have 5 arguments.
	(enum operand_parse_code): Add new operands.
	(parse_operands): Account for new operands.
	(S5): New macro.
	(enum neon_shape_el): Introduce P suffixes for coprocessor.
	(neon_select_shape): Account for P suffix.
	(LOW1): Move macro to global position.
	(HI4): Move macro to global position.
	(vcx_assign_vec_d): New.
	(vcx_assign_vec_m): New.
	(vcx_assign_vec_n): New.
	(enum vcx_reg_type): New.
	(vcx_get_reg_type): New.
	(vcx_size_pos): New.
	(vcx_vec_pos): New.
	(vcx_handle_shape): New.
	(vcx_ensure_register_in_range): New.
	(vcx_handle_register_arguments): New.
	(vcx_handle_insn_block): New.
	(vcx_handle_common_checks): New.
	(do_vcx1): New.
	(do_vcx2): New.
	(do_vcx3): New.
	* testsuite/gas/arm/cde-missing-fp.d: New test.
	* testsuite/gas/arm/cde-missing-fp.l: New test.
	* testsuite/gas/arm/cde-missing-mve.d: New test.
	* testsuite/gas/arm/cde-missing-mve.l: New test.
	* testsuite/gas/arm/cde-mve-or-neon.d: New test.
	* testsuite/gas/arm/cde-mve-or-neon.s: New test.
	* testsuite/gas/arm/cde-mve.s: New test.
	* testsuite/gas/arm/cde-warnings.l:
	* testsuite/gas/arm/cde-warnings.s:
	* testsuite/gas/arm/cde.d:
	* testsuite/gas/arm/cde.s:

opcodes/ChangeLog:

2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (print_insn_cde): Define 'V' parse character.
	(cde_opcodes): Add VCX* instructions.

15 files changed, 1438 insertions, 4 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 6df870a..b086374 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,41 @@
+2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+	* config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for
+	instructions that can have 5 arguments.
+	(enum operand_parse_code): Add new operands.
+	(parse_operands): Account for new operands.
+	(S5): New macro.
+	(enum neon_shape_el): Introduce P suffixes for coprocessor.
+	(neon_select_shape): Account for P suffix.
+	(LOW1): Move macro to global position.
+	(HI4): Move macro to global position.
+	(vcx_assign_vec_d): New.
+	(vcx_assign_vec_m): New.
+	(vcx_assign_vec_n): New.
+	(enum vcx_reg_type): New.
+	(vcx_get_reg_type): New.
+	(vcx_size_pos): New.
+	(vcx_vec_pos): New.
+	(vcx_handle_shape): New.
+	(vcx_ensure_register_in_range): New.
+	(vcx_handle_register_arguments): New.
+	(vcx_handle_insn_block): New.
+	(vcx_handle_common_checks): New.
+	(do_vcx1): New.
+	(do_vcx2): New.
+	(do_vcx3): New.
+	* testsuite/gas/arm/cde-missing-fp.d: New test.
+	* testsuite/gas/arm/cde-missing-fp.l: New test.
+	* testsuite/gas/arm/cde-missing-mve.d: New test.
+	* testsuite/gas/arm/cde-missing-mve.l: New test.
+	* testsuite/gas/arm/cde-mve-or-neon.d: New test.
+	* testsuite/gas/arm/cde-mve-or-neon.s: New test.
+	* testsuite/gas/arm/cde-mve.s: New test.
+	* testsuite/gas/arm/cde-warnings.l:
+	* testsuite/gas/arm/cde-warnings.s:
+	* testsuite/gas/arm/cde.d:
+	* testsuite/gas/arm/cde.s:
+
 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 	    Matthew Malcomson  <matthew.malcomson@arm.com>
 
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 93d04ee..48b1d36 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -339,6 +339,11 @@ static const arm_feature_set mve_ext =
   ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE);
 static const arm_feature_set mve_fp_ext =
   ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP);
+/* Note: This has more than one bit set, which means using it with
+   mark_feature_used (which returns if *any* of the bits are set in the current
+   cpu variant) can give surprising results.  */
+static const arm_feature_set armv8m_fp =
+  ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16);
 #ifdef OBJ_ELF
 static const arm_feature_set fpu_vfp_fp16 =
   ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16);
@@ -478,7 +483,7 @@ struct neon_type_el
   unsigned size;
 };
 
-#define NEON_MAX_TYPE_ELS 4
+#define NEON_MAX_TYPE_ELS 5
 
 struct neon_type
 {
@@ -7092,6 +7097,7 @@ enum operand_parse_code
   OP_RIWG,	/* iWMMXt wCG register */
   OP_RXA,	/* XScale accumulator register */
 
+  OP_RNSDMQ,	/* Neon single, double or MVE vector register */
   OP_RNSDQMQ,	/* Neon single, double or quad register or MVE vector register
 		 */
   OP_RNSDQMQR,	/* Neon single, double or quad register, MVE vector register or
@@ -7160,8 +7166,10 @@ enum operand_parse_code
   OP_I63s,	/*		 -64 .. 63 */
   OP_I64,	/*		   1 .. 64 */
   OP_I64z,	/*		   0 .. 64 */
+  OP_I127,	/*		   0 .. 127 */
   OP_I255,	/*		   0 .. 255 */
   OP_I511,	/*		   0 .. 511 */
+  OP_I4095,	/*		   0 .. 4095 */
   OP_I8191,	/*		   0 .. 8191 */
   OP_I4b,	/* immediate, prefix optional, 1 .. 4 */
   OP_I7b,	/*			       0 .. 7 */
@@ -7480,6 +7488,12 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
 	case OP_RVSD_COND:
 	  po_reg_or_goto (REG_TYPE_VFSD, try_cond);
 	  break;
+	case OP_RNSDMQ:
+	  po_reg_or_goto (REG_TYPE_NSD, try_mq2);
+	  break;
+	  try_mq2:
+	  po_reg_or_fail (REG_TYPE_MQ);
+	  break;
 	case OP_oRNSDQ:
 	case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ);    break;
 	case OP_RNSDQMQR:
@@ -7676,8 +7690,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
 	case OP_I63:	 po_imm_or_fail (  0,     63, FALSE);   break;
 	case OP_I64:	 po_imm_or_fail (  1,     64, FALSE);   break;
 	case OP_I64z:	 po_imm_or_fail (  0,     64, FALSE);   break;
+	case OP_I127:	 po_imm_or_fail (  0,	 127, FALSE);	break;
 	case OP_I255:	 po_imm_or_fail (  0,	 255, FALSE);	break;
 	case OP_I511:	 po_imm_or_fail (  0,	 511, FALSE);	break;
+	case OP_I4095:	 po_imm_or_fail (  0,	 4095, FALSE);	break;
 	case OP_I8191:   po_imm_or_fail (  0,	 8191, FALSE);	break;
 	case OP_I4b:	 po_imm_or_fail (  1,	   4, TRUE);	break;
 	case OP_oI7b:
@@ -14797,6 +14813,15 @@ NEON_ENC_TAB
   X(2, (Q, R), QUAD),			\
   X(2, (D, I), DOUBLE),			\
   X(2, (Q, I), QUAD),			\
+  X(3, (P, F, I), SINGLE),		\
+  X(3, (P, D, I), DOUBLE),		\
+  X(3, (P, Q, I), QUAD),		\
+  X(4, (P, F, F, I), SINGLE),		\
+  X(4, (P, D, D, I), DOUBLE),		\
+  X(4, (P, Q, Q, I), QUAD),		\
+  X(5, (P, F, F, F, I), SINGLE),	\
+  X(5, (P, D, D, D, I), DOUBLE),	\
+  X(5, (P, Q, Q, Q, I), QUAD),		\
   X(3, (D, L, D), DOUBLE),		\
   X(2, (D, Q), MIXED),			\
   X(2, (Q, D), MIXED),			\
@@ -14845,6 +14870,7 @@ NEON_ENC_TAB
 #define S2(A,B)		NS_##A##B
 #define S3(A,B,C)	NS_##A##B##C
 #define S4(A,B,C,D)	NS_##A##B##C##D
+#define S5(A,B,C,D,E)	NS_##A##B##C##D##E
 
 #define X(N, L, C) S##N L
 
@@ -14858,6 +14884,7 @@ enum neon_shape
 #undef S2
 #undef S3
 #undef S4
+#undef S5
 
 enum neon_shape_class
 {
@@ -14886,7 +14913,8 @@ enum neon_shape_el
   SE_I,
   SE_S,
   SE_R,
-  SE_L
+  SE_L,
+  SE_P
 };
 
 /* Register widths of above.  */
@@ -14899,6 +14927,7 @@ static unsigned neon_shape_el_size[] =
   0,
   32,
   32,
+  0,
   0
 };
 
@@ -14911,6 +14940,7 @@ struct neon_shape_info
 #define S2(A,B)		{ SE_##A, SE_##B }
 #define S3(A,B,C)	{ SE_##A, SE_##B, SE_##C }
 #define S4(A,B,C,D)	{ SE_##A, SE_##B, SE_##C, SE_##D }
+#define S5(A,B,C,D,E)	{ SE_##A, SE_##B, SE_##C, SE_##D, SE_##E }
 
 #define X(N, L, C) { N, S##N L }
 
@@ -14923,6 +14953,7 @@ static struct neon_shape_info neon_shape_tab[] =
 #undef S2
 #undef S3
 #undef S4
+#undef S5
 
 /* Bit masks used in type checking given instructions.
   'N_EQK' means the type must be the same as (or based on in some way) the key
@@ -15112,6 +15143,7 @@ neon_select_shape (enum neon_shape shape, ...)
 		matches = 0;
 	      break;
 
+	    case SE_P:
 	    case SE_L:
 	      break;
 	    }
@@ -15840,6 +15872,8 @@ neon_logbits (unsigned x)
 
 #define LOW4(R) ((R) & 0xf)
 #define HI1(R) (((R) >> 4) & 1)
+#define LOW1(R) ((R) & 0x1)
+#define HI4(R) (((R) >> 1) & 0xf)
 
 static unsigned
 mve_get_vcmp_vpt_cond (struct neon_type_el et)
@@ -19728,8 +19762,6 @@ do_neon_fmac_maybe_scalar_long (int subtype)
   inst.instruction &= 0x00ffffff;
   inst.instruction |= high8;
 
-#define LOW1(R) ((R) & 0x1)
-#define HI4(R) (((R) >> 1) & 0xf)
   /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
      whether the instruction is in Q form and whether Vm is a scalar indexed
      operand.  */
@@ -21840,6 +21872,212 @@ do_cx3da (void)
   return do_custom_instruction_3 (1, 1);
 }
 
+static void
+vcx_assign_vec_d (unsigned regnum)
+{
+  inst.instruction |= HI4 (regnum) << 12;
+  inst.instruction |= LOW1 (regnum) << 22;
+}
+
+static void
+vcx_assign_vec_m (unsigned regnum)
+{
+  inst.instruction |= HI4 (regnum);
+  inst.instruction |= LOW1 (regnum) << 5;
+}
+
+static void
+vcx_assign_vec_n (unsigned regnum)
+{
+  inst.instruction |= HI4 (regnum) << 16;
+  inst.instruction |= LOW1 (regnum) << 7;
+}
+
+enum vcx_reg_type {
+    q_reg,
+    d_reg,
+    s_reg
+};
+
+static enum vcx_reg_type
+vcx_get_reg_type (enum neon_shape ns)
+{
+  gas_assert (ns == NS_PQI
+	      || ns == NS_PDI
+	      || ns == NS_PFI
+	      || ns == NS_PQQI
+	      || ns == NS_PDDI
+	      || ns == NS_PFFI
+	      || ns == NS_PQQQI
+	      || ns == NS_PDDDI
+	      || ns == NS_PFFFI);
+  if (ns == NS_PQI || ns == NS_PQQI || ns == NS_PQQQI)
+    return q_reg;
+  if (ns == NS_PDI || ns == NS_PDDI || ns == NS_PDDDI)
+    return d_reg;
+  return s_reg;
+}
+
+#define vcx_size_pos 24
+#define vcx_vec_pos 6
+static unsigned
+vcx_handle_shape (enum vcx_reg_type reg_type)
+{
+  unsigned mult = 2;
+  if (reg_type == q_reg)
+    inst.instruction |= 1 << vcx_vec_pos;
+  else if (reg_type == d_reg)
+    inst.instruction |= 1 << vcx_size_pos;
+  else
+    mult = 1;
+  /* NOTE:
+     The documentation says that the Q registers are encoded as 2*N in the D:Vd
+     bits (or equivalent for N and M registers).
+     Similarly the D registers are encoded as N in D:Vd bits.
+     While the S registers are encoded as N in the Vd:D bits.
+
+     Taking into account the maximum values of these registers we can see a
+     nicer pattern for calculation:
+       Q -> 7, D -> 15, S -> 31
+
+     If we say that everything is encoded in the Vd:D bits, then we can say
+     that Q is encoded as 4*N, and D is encoded as 2*N.
+     This way the bits will end up the same, and calculation is simpler.
+     (calculation is now:
+	1. Multiply by a number determined by the register letter.
+	2. Encode resulting number in Vd:D bits.)
+
+      This is made a little more complicated by automatic handling of 'Q'
+      registers elsewhere, which means the register number is already 2*N where
+      N is the number the user wrote after the register letter.
+     */
+  return mult;
+}
+#undef vcx_vec_pos
+#undef vcx_size_pos
+
+static void
+vcx_ensure_register_in_range (unsigned R, enum vcx_reg_type reg_type)
+{
+  if (reg_type == q_reg)
+    {
+      gas_assert (R % 2 == 0);
+      constraint (R >= 16, _("'q' register must be in range 0-7"));
+    }
+  else if (reg_type == d_reg)
+    constraint (R >= 16, _("'d' register must be in range 0-15"));
+  else
+    constraint (R >= 32, _("'s' register must be in range 0-31"));
+}
+
+static void (*vcx_assign_vec[3]) (unsigned) = {
+    vcx_assign_vec_d,
+    vcx_assign_vec_m,
+    vcx_assign_vec_n
+};
+
+static void
+vcx_handle_register_arguments (unsigned num_registers,
+			       enum vcx_reg_type reg_type)
+{
+  unsigned R;
+  unsigned reg_mult = vcx_handle_shape (reg_type);
+  for (unsigned i = 0; i < num_registers; i++)
+    {
+      R = inst.operands[i+1].reg;
+      vcx_ensure_register_in_range (R, reg_type);
+      if (num_registers == 3 && i > 0)
+	{
+	  if (i == 2)
+	    vcx_assign_vec[1] (R * reg_mult);
+	  else
+	    vcx_assign_vec[2] (R * reg_mult);
+	  continue;
+	}
+      vcx_assign_vec[i](R * reg_mult);
+    }
+}
+
+static void
+vcx_handle_insn_block (enum vcx_reg_type reg_type)
+{
+  if (reg_type == q_reg)
+    if (inst.cond > COND_ALWAYS)
+      inst.pred_insn_type = INSIDE_VPT_INSN;
+    else
+      inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+  else if (inst.cond == COND_ALWAYS)
+    inst.pred_insn_type = OUTSIDE_PRED_INSN;
+  else
+    inst.error = BAD_NOT_IT;
+}
+
+static void
+vcx_handle_common_checks (unsigned num_args, enum neon_shape rs)
+{
+  constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
+  cde_handle_coproc ();
+  enum vcx_reg_type reg_type = vcx_get_reg_type (rs);
+  vcx_handle_register_arguments (num_args, reg_type);
+  vcx_handle_insn_block (reg_type);
+  if (reg_type == q_reg)
+    constraint (!mark_feature_used (&mve_ext),
+		_("vcx instructions with Q registers require MVE"));
+  else
+    constraint (!(ARM_FSET_CPU_SUBSET (armv8m_fp, cpu_variant)
+		  && mark_feature_used (&armv8m_fp))
+		&& !mark_feature_used (&mve_ext),
+		_("vcx instructions with S or D registers require either MVE"
+		  " or Armv8-M floating point etension."));
+}
+
+static void
+do_vcx1 (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_PQI, NS_PDI, NS_PFI, NS_NULL);
+  vcx_handle_common_checks (1, rs);
+
+  unsigned imm = inst.operands[2].imm;
+  inst.instruction |= (imm & 0x03f);
+  inst.instruction |= (imm & 0x040) << 1;
+  inst.instruction |= (imm & 0x780) << 9;
+  if (rs != NS_PQI)
+    constraint (imm >= 2048,
+		_("vcx1 with S or D registers takes immediate within 0-2047"));
+  inst.instruction |= (imm & 0x800) << 13;
+}
+
+static void
+do_vcx2 (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_PQQI, NS_PDDI, NS_PFFI, NS_NULL);
+  vcx_handle_common_checks (2, rs);
+
+  unsigned imm = inst.operands[3].imm;
+  inst.instruction |= (imm & 0x01) << 4;
+  inst.instruction |= (imm & 0x02) << 6;
+  inst.instruction |= (imm & 0x3c) << 14;
+  if (rs != NS_PQQI)
+    constraint (imm >= 64,
+		_("vcx2 with S or D registers takes immediate within 0-63"));
+  inst.instruction |= (imm & 0x40) << 18;
+}
+
+static void
+do_vcx3 (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_PQQQI, NS_PDDDI, NS_PFFFI, NS_NULL);
+  vcx_handle_common_checks (3, rs);
+
+  unsigned imm = inst.operands[4].imm;
+  inst.instruction |= (imm & 0x1) << 4;
+  inst.instruction |= (imm & 0x6) << 19;
+  if (rs != NS_PQQQI)
+    constraint (imm >= 8,
+		_("vcx2 with S or D registers takes immediate within 0-7"));
+  inst.instruction |= (imm & 0x8) << 21;
+}
+
 /* Crypto v1 instructions.  */
 static void
 do_crypto_2op_1 (unsigned elttype, int op)
@@ -26400,7 +26638,17 @@ static const struct asm_opcode insns[] =
  ToC ("cx3a", fe800000, 5, (RCP, APSR_RR, APSR_RR, APSR_RR, I63), cx3a),
  ToC ("cx3d", ee800040, 6, (RCP, RR, APSR_RR, APSR_RR, APSR_RR, I63), cx3d),
  ToC ("cx3da", fe800040, 6, (RCP, RR, APSR_RR, APSR_RR, APSR_RR, I63), cx3da),
+
+ mToC ("vcx1", ec200000, 3, (RCP, RNSDMQ, I4095), vcx1),
+ mToC ("vcx1a", fc200000, 3, (RCP, RNSDMQ, I4095), vcx1),
+
+ mToC ("vcx2", ec300000, 4, (RCP, RNSDMQ, RNSDMQ, I127), vcx2),
+ mToC ("vcx2a", fc300000, 4, (RCP, RNSDMQ, RNSDMQ, I127), vcx2),
+
+ mToC ("vcx3", ec800000, 5, (RCP, RNSDMQ, RNSDMQ, RNSDMQ, I15), vcx3),
+ mToC ("vcx3a", fc800000, 5, (RCP, RNSDMQ, RNSDMQ, RNSDMQ, I15), vcx3),
 };
+
 #undef ARM_VARIANT
 #undef THUMB_VARIANT
 #undef TCE
diff --git a/gas/testsuite/gas/arm/cde-missing-fp.d b/gas/testsuite/gas/arm/cde-missing-fp.d
new file mode 100644
index 0000000..de7ebc8
--- /dev/null
+++ b/gas/testsuite/gas/arm/cde-missing-fp.d
@@ -0,0 +1,5 @@
+#name: Custom Datapath Extension FP missing (CDE)
+#source: cde.s
+#as: -mno-warn-deprecated -march=armv8-m.main+cdecp0+cdecp7 -I$srcdir/$subdir
+#as: -mno-warn-deprecated -march=armv8-m.main+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7 -I$srcdir/$subdir
+#error_output: cde-missing-fp.l
diff --git a/gas/testsuite/gas/arm/cde-missing-fp.l b/gas/testsuite/gas/arm/cde-missing-fp.l
new file mode 100644
index 0000000..2fbfa9d
--- /dev/null
+++ b/gas/testsuite/gas/arm/cde-missing-fp.l
@@ -0,0 +1,148 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#2048'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#1920'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#64'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#63'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p7,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q7,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#2048'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#1920'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#64'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#63'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p7,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q7,#0'
+[^ :]+:[0-9]+: Error: selected processor does not support `vptt\.i8 eq,q0,q0' in Thumb mode
+[^ :]+:[0-9]+: Error: bad instruction `vcx1t p0,q0,#0'
+[^ :]+:[0-9]+: Error: bad instruction `vcx1at p0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#64'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#60'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#2'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#1'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p7,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q7,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q7,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#64'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#60'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#2'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#1'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p7,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q7,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q7,#0'
+[^ :]+:[0-9]+: Error: selected processor does not support `vptt\.i8 eq,q0,q0' in Thumb mode
+[^ :]+:[0-9]+: Error: bad instruction `vcx2t p0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: bad instruction `vcx2at p0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#8'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#6'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#1'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p7,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q7,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q7,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q7,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#8'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#6'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#1'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p7,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q7,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q7,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q7,#0'
+[^ :]+:[0-9]+: Error: selected processor does not support `vptt\.i8 eq,q0,q0' in Thumb mode
+[^ :]+:[0-9]+: Error: bad instruction `vcx3t p0,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: bad instruction `vcx3at p0,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s0,#1920'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s0,#64'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s0,#63'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p7,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s1,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,s30,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,d0,#1920'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,d0,#64'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,d0,#63'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p7,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1 p0,d15,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s0,#1920'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s0,#64'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s0,#63'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p7,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s1,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,s30,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,d0,#1920'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,d0,#64'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,d0,#63'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p7,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx1a p0,d15,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s0,#60'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s0,#2'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s0,#1'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p7,s0,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s1,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s30,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s1,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,s0,s30,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d0,d0,#60'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d0,d0,#2'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d0,d0,#1'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p7,d0,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d15,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2 p0,d0,d15,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s0,#60'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s0,#2'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s0,#1'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p7,s0,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s1,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s30,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s1,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,s0,s30,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d0,d0,#60'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d0,d0,#2'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d0,d0,#1'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p7,d0,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d15,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx2a p0,d0,d15,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s0,s0,#6'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s0,s0,#1'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p7,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s1,s0,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s30,s0,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s1,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s30,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s0,s1,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,s0,s0,s30,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d0,d0,d0,#6'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d0,d0,d0,#1'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p7,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d15,d0,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d0,d15,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3 p0,d0,d0,d15,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s0,s0,#6'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s0,s0,#1'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p7,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s1,s0,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s30,s0,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s1,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s30,s0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s0,s1,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,s0,s0,s30,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d0,d0,d0,#6'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d0,d0,d0,#1'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p7,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d15,d0,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d0,d15,d0,#0'
+[^ :]+:[0-9]+: Error: vcx instructions with S or D registers require either MVE or Armv8-M floating point etension\. -- `vcx3a p0,d0,d0,d15,#0'
diff --git a/gas/testsuite/gas/arm/cde-missing-mve.d b/gas/testsuite/gas/arm/cde-missing-mve.d
new file mode 100644
index 0000000..22ac9fe
--- /dev/null
+++ b/gas/testsuite/gas/arm/cde-missing-mve.d
@@ -0,0 +1,7 @@
+#name: Custom Datapath Extension MVE missing (CDE)
+#source: cde.s
+#as: -mno-warn-deprecated -march=armv8.1-m.main+cdecp0+cdecp7+fp -I$srcdir/$subdir
+#as: -mno-warn-deprecated -march=armv8.1-m.main+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7+fp -I$srcdir/$subdir
+#as: -mno-warn-deprecated -march=armv8-m.main+cdecp0+cdecp7+fp -I$srcdir/$subdir
+#as: -mno-warn-deprecated -march=armv8-m.main+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7+fp -I$srcdir/$subdir
+#error_output: cde-missing-mve.l
diff --git a/gas/testsuite/gas/arm/cde-missing-mve.l b/gas/testsuite/gas/arm/cde-missing-mve.l
new file mode 100644
index 0000000..997fbe4
--- /dev/null
+++ b/gas/testsuite/gas/arm/cde-missing-mve.l
@@ -0,0 +1,57 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#2048'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#1920'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#64'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q0,#63'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p7,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,q7,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#2048'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#1920'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#64'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q0,#63'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p7,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,q7,#0'
+[^ :]+:[0-9]+: Error: selected processor does not support `vptt\.i8 eq,q0,q0' in Thumb mode
+[^ :]+:[0-9]+: Error: bad instruction `vcx1t p0,q0,#0'
+[^ :]+:[0-9]+: Error: bad instruction `vcx1at p0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#64'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#60'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#2'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q0,#1'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p7,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q7,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,q7,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#64'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#60'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#2'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q0,#1'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p7,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q7,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,q7,#0'
+[^ :]+:[0-9]+: Error: selected processor does not support `vptt\.i8 eq,q0,q0' in Thumb mode
+[^ :]+:[0-9]+: Error: bad instruction `vcx2t p0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: bad instruction `vcx2at p0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#8'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#6'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q0,#1'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p7,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q7,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q7,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,q7,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#8'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#6'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q0,#1'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p7,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q7,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q7,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,q7,#0'
+[^ :]+:[0-9]+: Error: selected processor does not support `vptt\.i8 eq,q0,q0' in Thumb mode
+[^ :]+:[0-9]+: Error: bad instruction `vcx3t p0,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: bad instruction `vcx3at p0,q0,q0,q0,#0'
+
diff --git a/gas/testsuite/gas/arm/cde-mve-or-neon.d b/gas/testsuite/gas/arm/cde-mve-or-neon.d
new file mode 100644
index 0000000..7d0a1b8
--- /dev/null
+++ b/gas/testsuite/gas/arm/cde-mve-or-neon.d
@@ -0,0 +1,99 @@
+#name: Custom Datapath Extension (CDE)
+#source: cde-mve-or-neon.s
+#as: -mno-warn-deprecated -march=armv8-m.main+cdecp0+cdecp7+fp -I$srcdir/$subdir
+#as: -mno-warn-deprecated -march=armv8-m.main+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7+fp -I$srcdir/$subdir
+#objdump: -M force-thumb -dr --show-raw-insn -marmv8-m.main -M coproc0=cde -M coproc7=cde
+#...
+00000000 <\.text>:
+ *[0-9a-f]+:	ec20 0000 	vcx1	p0, s0, #0
+ *[0-9a-f]+:	ec2f 0000 	vcx1	p0, s0, #1920
+ *[0-9a-f]+:	ec20 0080 	vcx1	p0, s0, #64
+ *[0-9a-f]+:	ec20 003f 	vcx1	p0, s0, #63
+ *[0-9a-f]+:	ec20 0700 	vcx1	p7, s0, #0
+ *[0-9a-f]+:	ec60 0000 	vcx1	p0, s1, #0
+ *[0-9a-f]+:	ec20 f000 	vcx1	p0, s30, #0
+ *[0-9a-f]+:	ed20 0000 	vcx1	p0, d0, #0
+ *[0-9a-f]+:	ed2f 0000 	vcx1	p0, d0, #1920
+ *[0-9a-f]+:	ed20 0080 	vcx1	p0, d0, #64
+ *[0-9a-f]+:	ed20 003f 	vcx1	p0, d0, #63
+ *[0-9a-f]+:	ed20 0700 	vcx1	p7, d0, #0
+ *[0-9a-f]+:	ed20 f000 	vcx1	p0, d15, #0
+ *[0-9a-f]+:	fc20 0000 	vcx1a	p0, s0, #0
+ *[0-9a-f]+:	fc2f 0000 	vcx1a	p0, s0, #1920
+ *[0-9a-f]+:	fc20 0080 	vcx1a	p0, s0, #64
+ *[0-9a-f]+:	fc20 003f 	vcx1a	p0, s0, #63
+ *[0-9a-f]+:	fc20 0700 	vcx1a	p7, s0, #0
+ *[0-9a-f]+:	fc60 0000 	vcx1a	p0, s1, #0
+ *[0-9a-f]+:	fc20 f000 	vcx1a	p0, s30, #0
+ *[0-9a-f]+:	fd20 0000 	vcx1a	p0, d0, #0
+ *[0-9a-f]+:	fd2f 0000 	vcx1a	p0, d0, #1920
+ *[0-9a-f]+:	fd20 0080 	vcx1a	p0, d0, #64
+ *[0-9a-f]+:	fd20 003f 	vcx1a	p0, d0, #63
+ *[0-9a-f]+:	fd20 0700 	vcx1a	p7, d0, #0
+ *[0-9a-f]+:	fd20 f000 	vcx1a	p0, d15, #0
+ *[0-9a-f]+:	ec30 0000 	vcx2	p0, s0, s0, #0
+ *[0-9a-f]+:	ec3f 0000 	vcx2	p0, s0, s0, #60
+ *[0-9a-f]+:	ec30 0080 	vcx2	p0, s0, s0, #2
+ *[0-9a-f]+:	ec30 0010 	vcx2	p0, s0, s0, #1
+ *[0-9a-f]+:	ec30 0700 	vcx2	p7, s0, s0, #0
+ *[0-9a-f]+:	ec70 0000 	vcx2	p0, s1, s0, #0
+ *[0-9a-f]+:	ec30 f000 	vcx2	p0, s30, s0, #0
+ *[0-9a-f]+:	ec30 0020 	vcx2	p0, s0, s1, #0
+ *[0-9a-f]+:	ec30 000f 	vcx2	p0, s0, s30, #0
+ *[0-9a-f]+:	ed30 0000 	vcx2	p0, d0, d0, #0
+ *[0-9a-f]+:	ed3f 0000 	vcx2	p0, d0, d0, #60
+ *[0-9a-f]+:	ed30 0080 	vcx2	p0, d0, d0, #2
+ *[0-9a-f]+:	ed30 0010 	vcx2	p0, d0, d0, #1
+ *[0-9a-f]+:	ed30 0700 	vcx2	p7, d0, d0, #0
+ *[0-9a-f]+:	ed30 f000 	vcx2	p0, d15, d0, #0
+ *[0-9a-f]+:	ed30 000f 	vcx2	p0, d0, d15, #0
+ *[0-9a-f]+:	fc30 0000 	vcx2a	p0, s0, s0, #0
+ *[0-9a-f]+:	fc3f 0000 	vcx2a	p0, s0, s0, #60
+ *[0-9a-f]+:	fc30 0080 	vcx2a	p0, s0, s0, #2
+ *[0-9a-f]+:	fc30 0010 	vcx2a	p0, s0, s0, #1
+ *[0-9a-f]+:	fc30 0700 	vcx2a	p7, s0, s0, #0
+ *[0-9a-f]+:	fc70 0000 	vcx2a	p0, s1, s0, #0
+ *[0-9a-f]+:	fc30 f000 	vcx2a	p0, s30, s0, #0
+ *[0-9a-f]+:	fc30 0020 	vcx2a	p0, s0, s1, #0
+ *[0-9a-f]+:	fc30 000f 	vcx2a	p0, s0, s30, #0
+ *[0-9a-f]+:	fd30 0000 	vcx2a	p0, d0, d0, #0
+ *[0-9a-f]+:	fd3f 0000 	vcx2a	p0, d0, d0, #60
+ *[0-9a-f]+:	fd30 0080 	vcx2a	p0, d0, d0, #2
+ *[0-9a-f]+:	fd30 0010 	vcx2a	p0, d0, d0, #1
+ *[0-9a-f]+:	fd30 0700 	vcx2a	p7, d0, d0, #0
+ *[0-9a-f]+:	fd30 f000 	vcx2a	p0, d15, d0, #0
+ *[0-9a-f]+:	fd30 000f 	vcx2a	p0, d0, d15, #0
+ *[0-9a-f]+:	ec80 0000 	vcx3	p0, s0, s0, s0, #0
+ *[0-9a-f]+:	ecb0 0000 	vcx3	p0, s0, s0, s0, #6
+ *[0-9a-f]+:	ec80 0010 	vcx3	p0, s0, s0, s0, #1
+ *[0-9a-f]+:	ec80 0700 	vcx3	p7, s0, s0, s0, #0
+ *[0-9a-f]+:	ecc0 0000 	vcx3	p0, s1, s0, s0, #0
+ *[0-9a-f]+:	ec80 f000 	vcx3	p0, s30, s0, s0, #0
+ *[0-9a-f]+:	ec80 0080 	vcx3	p0, s0, s1, s0, #0
+ *[0-9a-f]+:	ec8f 0000 	vcx3	p0, s0, s30, s0, #0
+ *[0-9a-f]+:	ec80 0020 	vcx3	p0, s0, s0, s1, #0
+ *[0-9a-f]+:	ec80 000f 	vcx3	p0, s0, s0, s30, #0
+ *[0-9a-f]+:	ed80 0000 	vcx3	p0, d0, d0, d0, #0
+ *[0-9a-f]+:	edb0 0000 	vcx3	p0, d0, d0, d0, #6
+ *[0-9a-f]+:	ed80 0010 	vcx3	p0, d0, d0, d0, #1
+ *[0-9a-f]+:	ed80 0700 	vcx3	p7, d0, d0, d0, #0
+ *[0-9a-f]+:	ed80 f000 	vcx3	p0, d15, d0, d0, #0
+ *[0-9a-f]+:	ed8f 0000 	vcx3	p0, d0, d15, d0, #0
+ *[0-9a-f]+:	ed80 000f 	vcx3	p0, d0, d0, d15, #0
+ *[0-9a-f]+:	fc80 0000 	vcx3a	p0, s0, s0, s0, #0
+ *[0-9a-f]+:	fcb0 0000 	vcx3a	p0, s0, s0, s0, #6
+ *[0-9a-f]+:	fc80 0010 	vcx3a	p0, s0, s0, s0, #1
+ *[0-9a-f]+:	fc80 0700 	vcx3a	p7, s0, s0, s0, #0
+ *[0-9a-f]+:	fcc0 0000 	vcx3a	p0, s1, s0, s0, #0
+ *[0-9a-f]+:	fc80 f000 	vcx3a	p0, s30, s0, s0, #0
+ *[0-9a-f]+:	fc80 0080 	vcx3a	p0, s0, s1, s0, #0
+ *[0-9a-f]+:	fc8f 0000 	vcx3a	p0, s0, s30, s0, #0
+ *[0-9a-f]+:	fc80 0020 	vcx3a	p0, s0, s0, s1, #0
+ *[0-9a-f]+:	fc80 000f 	vcx3a	p0, s0, s0, s30, #0
+ *[0-9a-f]+:	fd80 0000 	vcx3a	p0, d0, d0, d0, #0
+ *[0-9a-f]+:	fdb0 0000 	vcx3a	p0, d0, d0, d0, #6
+ *[0-9a-f]+:	fd80 0010 	vcx3a	p0, d0, d0, d0, #1
+ *[0-9a-f]+:	fd80 0700 	vcx3a	p7, d0, d0, d0, #0
+ *[0-9a-f]+:	fd80 f000 	vcx3a	p0, d15, d0, d0, #0
+ *[0-9a-f]+:	fd8f 0000 	vcx3a	p0, d0, d15, d0, #0
+ *[0-9a-f]+:	fd80 000f 	vcx3a	p0, d0, d0, d15, #0
diff --git a/gas/testsuite/gas/arm/cde-mve-or-neon.s b/gas/testsuite/gas/arm/cde-mve-or-neon.s
new file mode 100644
index 0000000..ba8bc72
--- /dev/null
+++ b/gas/testsuite/gas/arm/cde-mve-or-neon.s
@@ -0,0 +1,96 @@
+.syntax unified
+vcx1 p0, s0, #0
+vcx1 p0, s0, #1920
+vcx1 p0, s0, #64
+vcx1 p0, s0, #63
+vcx1 p7, s0, #0
+vcx1 p0, s1, #0
+vcx1 p0, s30, #0
+vcx1 p0, d0, #0
+vcx1 p0, d0, #1920
+vcx1 p0, d0, #64
+vcx1 p0, d0, #63
+vcx1 p7, d0, #0
+vcx1 p0, d15, #0
+vcx1a p0, s0, #0
+vcx1a p0, s0, #1920
+vcx1a p0, s0, #64
+vcx1a p0, s0, #63
+vcx1a p7, s0, #0
+vcx1a p0, s1, #0
+vcx1a p0, s30, #0
+vcx1a p0, d0, #0
+vcx1a p0, d0, #1920
+vcx1a p0, d0, #64
+vcx1a p0, d0, #63
+vcx1a p7, d0, #0
+vcx1a p0, d15, #0
+
+vcx2 p0, s0, s0, #0
+vcx2 p0, s0, s0, #60
+vcx2 p0, s0, s0, #2
+vcx2 p0, s0, s0, #1
+vcx2 p7, s0, s0, #0
+vcx2 p0, s1, s0, #0
+vcx2 p0, s30, s0, #0
+vcx2 p0, s0, s1, #0
+vcx2 p0, s0, s30, #0
+vcx2 p0, d0, d0, #0
+vcx2 p0, d0, d0, #60
+vcx2 p0, d0, d0, #2
+vcx2 p0, d0, d0, #1
+vcx2 p7, d0, d0, #0
+vcx2 p0, d15, d0, #0
+vcx2 p0, d0, d15, #0
+vcx2a p0, s0, s0, #0
+vcx2a p0, s0, s0, #60
+vcx2a p0, s0, s0, #2
+vcx2a p0, s0, s0, #1
+vcx2a p7, s0, s0, #0
+vcx2a p0, s1, s0, #0
+vcx2a p0, s30, s0, #0
+vcx2a p0, s0, s1, #0
+vcx2a p0, s0, s30, #0
+vcx2a p0, d0, d0, #0
+vcx2a p0, d0, d0, #60
+vcx2a p0, d0, d0, #2
+vcx2a p0, d0, d0, #1
+vcx2a p7, d0, d0, #0
+vcx2a p0, d15, d0, #0
+vcx2a p0, d0, d15, #0
+
+
+vcx3 p0, s0, s0, s0, #0
+vcx3 p0, s0, s0, s0, #6
+vcx3 p0, s0, s0, s0, #1
+vcx3 p7, s0, s0, s0, #0
+vcx3 p0, s1, s0, s0, #0
+vcx3 p0, s30, s0, s0, #0
+vcx3 p0, s0, s1, s0, #0
+vcx3 p0, s0, s30, s0, #0
+vcx3 p0, s0, s0, s1, #0
+vcx3 p0, s0, s0, s30, #0
+vcx3 p0, d0, d0, d0, #0
+vcx3 p0, d0, d0, d0, #6
+vcx3 p0, d0, d0, d0, #1
+vcx3 p7, d0, d0, d0, #0
+vcx3 p0, d15, d0, d0, #0
+vcx3 p0, d0, d15, d0, #0
+vcx3 p0, d0, d0, d15, #0
+vcx3a p0, s0, s0, s0, #0
+vcx3a p0, s0, s0, s0, #6
+vcx3a p0, s0, s0, s0, #1
+vcx3a p7, s0, s0, s0, #0
+vcx3a p0, s1, s0, s0, #0
+vcx3a p0, s30, s0, s0, #0
+vcx3a p0, s0, s1, s0, #0
+vcx3a p0, s0, s30, s0, #0
+vcx3a p0, s0, s0, s1, #0
+vcx3a p0, s0, s0, s30, #0
+vcx3a p0, d0, d0, d0, #0
+vcx3a p0, d0, d0, d0, #6
+vcx3a p0, d0, d0, d0, #1
+vcx3a p7, d0, d0, d0, #0
+vcx3a p0, d15, d0, d0, #0
+vcx3a p0, d0, d15, d0, #0
+vcx3a p0, d0, d0, d15, #0
diff --git a/gas/testsuite/gas/arm/cde-mve.s b/gas/testsuite/gas/arm/cde-mve.s
new file mode 100644
index 0000000..04e014c
--- /dev/null
+++ b/gas/testsuite/gas/arm/cde-mve.s
@@ -0,0 +1,62 @@
+.syntax unified
+
+vcx1 p0, q0, #0
+vcx1 p0, q0, #2048
+vcx1 p0, q0, #1920
+vcx1 p0, q0, #64
+vcx1 p0, q0, #63
+vcx1 p7, q0, #0
+vcx1 p0, q7, #0
+vcx1a p0, q0, #0
+vcx1a p0, q0, #2048
+vcx1a p0, q0, #1920
+vcx1a p0, q0, #64
+vcx1a p0, q0, #63
+vcx1a p7, q0, #0
+vcx1a p0, q7, #0
+
+vptt.i8 eq, q0, q0
+vcx1t p0, q0, #0
+vcx1at p0, q0, #0
+
+vcx2 p0, q0, q0, #0
+vcx2 p0, q0, q0, #64
+vcx2 p0, q0, q0, #60
+vcx2 p0, q0, q0, #2
+vcx2 p0, q0, q0, #1
+vcx2 p7, q0, q0, #0
+vcx2 p0, q7, q0, #0
+vcx2 p0, q0, q7, #0
+vcx2a p0, q0, q0, #0
+vcx2a p0, q0, q0, #64
+vcx2a p0, q0, q0, #60
+vcx2a p0, q0, q0, #2
+vcx2a p0, q0, q0, #1
+vcx2a p7, q0, q0, #0
+vcx2a p0, q7, q0, #0
+vcx2a p0, q0, q7, #0
+
+vptt.i8 eq, q0, q0
+vcx2t p0, q0, q0, #0
+vcx2at p0, q0, q0, #0
+
+vcx3 p0, q0, q0, q0, #0
+vcx3 p0, q0, q0, q0, #8
+vcx3 p0, q0, q0, q0, #6
+vcx3 p0, q0, q0, q0, #1
+vcx3 p7, q0, q0, q0, #0
+vcx3 p0, q7, q0, q0, #0
+vcx3 p0, q0, q7, q0, #0
+vcx3 p0, q0, q0, q7, #0
+vcx3a p0, q0, q0, q0, #0
+vcx3a p0, q0, q0, q0, #8
+vcx3a p0, q0, q0, q0, #6
+vcx3a p0, q0, q0, q0, #1
+vcx3a p7, q0, q0, q0, #0
+vcx3a p0, q7, q0, q0, #0
+vcx3a p0, q0, q7, q0, #0
+vcx3a p0, q0, q0, q7, #0
+
+vptt.i8 eq, q0, q0
+vcx3t p0, q0, q0, q0, #0
+vcx3at p0, q0, q0, q0, #0
diff --git a/gas/testsuite/gas/arm/cde-warnings.l b/gas/testsuite/gas/arm/cde-warnings.l
index abbd10a..d0380d9 100644
--- a/gas/testsuite/gas/arm/cde-warnings.l
+++ b/gas/testsuite/gas/arm/cde-warnings.l
@@ -173,3 +173,183 @@
 [^ :]+:[0-9]+: Error: constant expression required -- `cx3da p0,r0,r1,r0,r0,r0,#0'
 [^ :]+:[0-9]+: Error: syntax error -- `cx3d p0,r0,r0,r0,#0'
 [^ :]+:[0-9]+: Error: syntax error -- `cx3da p0,r0,r0,r0,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx1 p0,q0,#4096'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx1a p0,q0,#4096'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx1 p0,q0,#-1'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx1a p0,q0,#-1'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx1 p8,q0,#0'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx1a p8,q0,#0'
+[^ :]+:[0-9]+: Error: expected MVE register \[q0\.\.q7\] -- `vcx1 p0,q8,#0'
+[^ :]+:[0-9]+: Error: expected MVE register \[q0\.\.q7\] -- `vcx1a p0,q8,#0'
+[^ :]+:[0-9]+: Warning: instruction is UNPREDICTABLE in an IT block
+[^ :]+:[0-9]+: Error: syntax error -- `vcx1ne p0,q0,#0'
+[^ :]+:[0-9]+: Warning: instruction is UNPREDICTABLE in an IT block
+[^ :]+:[0-9]+: Error: syntax error -- `vcx1ane p0,q0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx1 p1,q0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx1a p1,q0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx1 p0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx1a p0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,#0'
+[^ :]+:[0-9]+: Error: vcx1 with S or D registers takes immediate within 0-2047 -- `vcx1 p0,d0,#2048'
+[^ :]+:[0-9]+: Error: vcx1 with S or D registers takes immediate within 0-2047 -- `vcx1a p0,d0,#2048'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx1 p0,d0,#-1'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx1a p0,d0,#-1'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx1 p8,d0,#0'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx1a p8,d0,#0'
+[^ :]+:[0-9]+: Error: 'd' register must be in range 0-15 -- `vcx1 p0,d16,#0'
+[^ :]+:[0-9]+: Error: 'd' register must be in range 0-15 -- `vcx1a p0,d16,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx1 p0,d0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx1ne p0,d0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx1a p0,d0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx1ane p0,d0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx1 p1,d0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx1a p1,d0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx1 p0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx1a p0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,#0'
+[^ :]+:[0-9]+: Error: vcx1 with S or D registers takes immediate within 0-2047 -- `vcx1 p0,s0,#2048'
+[^ :]+:[0-9]+: Error: vcx1 with S or D registers takes immediate within 0-2047 -- `vcx1a p0,s0,#2048'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx1 p0,s0,#-1'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx1a p0,s0,#-1'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx1 p8,s0,#0'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx1a p8,s0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,s32,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,s32,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx1 p0,s0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx1ne p0,s0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx1a p0,s0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx1ane p0,s0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx1 p1,s0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx1a p1,s0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx1 p0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx1a p0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1 p0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx1a p0,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx2 p0,q0,q0,#128'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx2a p0,q0,q0,#128'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx2 p0,q0,q0,#-1'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx2a p0,q0,q0,#-1'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx2 p8,q0,q0,#0'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx2a p8,q0,q0,#0'
+[^ :]+:[0-9]+: Error: expected MVE register \[q0\.\.q7\] -- `vcx2 p0,q8,q0,#0'
+[^ :]+:[0-9]+: Error: expected MVE register \[q0\.\.q7\] -- `vcx2a p0,q8,q0,#0'
+[^ :]+:[0-9]+: Error: expected MVE register \[q0\.\.q7\] -- `vcx2 p0,q0,q8,#0'
+[^ :]+:[0-9]+: Error: expected MVE register \[q0\.\.q7\] -- `vcx2a p0,q0,q8,#0'
+[^ :]+:[0-9]+: Warning: instruction is UNPREDICTABLE in an IT block
+[^ :]+:[0-9]+: Error: syntax error -- `vcx2ne p0,q0,q0,#0'
+[^ :]+:[0-9]+: Warning: instruction is UNPREDICTABLE in an IT block
+[^ :]+:[0-9]+: Error: syntax error -- `vcx2ane p0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx2 p1,q0,q0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx2a p1,q0,q0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx2 p0,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx2a p0,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,q0,#0'
+[^ :]+:[0-9]+: Error: vcx2 with S or D registers takes immediate within 0-63 -- `vcx2 p0,d0,d0,#64'
+[^ :]+:[0-9]+: Error: vcx2 with S or D registers takes immediate within 0-63 -- `vcx2a p0,d0,d0,#64'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx2 p0,d0,d0,#-1'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx2a p0,d0,d0,#-1'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx2 p8,d0,d0,#0'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx2a p8,d0,d0,#0'
+[^ :]+:[0-9]+: Error: 'd' register must be in range 0-15 -- `vcx2 p0,d16,d0,#0'
+[^ :]+:[0-9]+: Error: 'd' register must be in range 0-15 -- `vcx2a p0,d16,d0,#0'
+[^ :]+:[0-9]+: Error: 'd' register must be in range 0-15 -- `vcx2 p0,d0,d16,#0'
+[^ :]+:[0-9]+: Error: 'd' register must be in range 0-15 -- `vcx2a p0,d0,d16,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx2 p0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx2ne p0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx2a p0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx2ane p0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx2 p1,d0,d0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx2a p1,d0,d0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx2 p0,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx2a p0,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,d0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,d0,#0'
+[^ :]+:[0-9]+: Error: vcx2 with S or D registers takes immediate within 0-63 -- `vcx2 p0,s0,s0,#64'
+[^ :]+:[0-9]+: Error: vcx2 with S or D registers takes immediate within 0-63 -- `vcx2a p0,s0,s0,#64'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx2 p0,s0,s0,#-1'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx2a p0,s0,s0,#-1'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx2 p8,s0,s0,#0'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx2a p8,s0,s0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,s32,s0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,s32,s0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,s0,s32,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,s0,s32,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx2 p0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx2ne p0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx2a p0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx2ane p0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx2 p1,s0,s0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx2a p1,s0,s0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx2 p0,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx2a p0,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2 p0,s0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx2a p0,s0,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx3 p0,q0,q0,q0,#16'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx3a p0,q0,q0,q0,#16'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx3 p0,q0,q0,q0,#-1'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx3a p0,q0,q0,q0,#-1'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx3 p8,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx3a p8,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: expected MVE register \[q0\.\.q7\] -- `vcx3 p0,q8,q0,q0,#0'
+[^ :]+:[0-9]+: Error: expected MVE register \[q0\.\.q7\] -- `vcx3a p0,q8,q0,q0,#0'
+[^ :]+:[0-9]+: Error: expected MVE register \[q0\.\.q7\] -- `vcx3 p0,q8,q0,q0,#0'
+[^ :]+:[0-9]+: Error: expected MVE register \[q0\.\.q7\] -- `vcx3a p0,q0,q8,q0,#0'
+[^ :]+:[0-9]+: Error: expected MVE register \[q0\.\.q7\] -- `vcx3 p0,q0,q0,q8,#0'
+[^ :]+:[0-9]+: Error: expected MVE register \[q0\.\.q7\] -- `vcx3a p0,q0,q0,q8,#0'
+[^ :]+:[0-9]+: Warning: instruction is UNPREDICTABLE in an IT block
+[^ :]+:[0-9]+: Error: syntax error -- `vcx3ne p0,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Warning: instruction is UNPREDICTABLE in an IT block
+[^ :]+:[0-9]+: Error: syntax error -- `vcx3ane p0,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx3 p1,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx3a p1,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx3 p0,q0,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx3a p0,q0,q0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,q0,q0,#0'
+[^ :]+:[0-9]+: Error: vcx2 with S or D registers takes immediate within 0-7 -- `vcx3 p0,d0,d0,d0,#8'
+[^ :]+:[0-9]+: Error: vcx2 with S or D registers takes immediate within 0-7 -- `vcx3a p0,d0,d0,d0,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx3 p0,d0,d0,d0,#-1'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx3a p0,d0,d0,d0,#-1'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx3 p8,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx3a p8,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: 'd' register must be in range 0-15 -- `vcx3 p0,d16,d0,d0,#0'
+[^ :]+:[0-9]+: Error: 'd' register must be in range 0-15 -- `vcx3a p0,d16,d0,d0,#0'
+[^ :]+:[0-9]+: Error: 'd' register must be in range 0-15 -- `vcx3 p0,d0,d16,d0,#0'
+[^ :]+:[0-9]+: Error: 'd' register must be in range 0-15 -- `vcx3a p0,d0,d16,d0,#0'
+[^ :]+:[0-9]+: Error: 'd' register must be in range 0-15 -- `vcx3 p0,d0,d0,d16,#0'
+[^ :]+:[0-9]+: Error: 'd' register must be in range 0-15 -- `vcx3a p0,d0,d0,d16,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx3 p0,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx3ne p0,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx3a p0,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx3ane p0,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx3 p1,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx3a p1,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx3 p0,d0,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx3a p0,d0,d0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,d0,d0,#0'
+[^ :]+:[0-9]+: Error: vcx2 with S or D registers takes immediate within 0-7 -- `vcx3 p0,s0,s0,s0,#8'
+[^ :]+:[0-9]+: Error: vcx2 with S or D registers takes immediate within 0-7 -- `vcx3a p0,s0,s0,s0,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx3 p0,s0,s0,s0,#-1'
+[^ :]+:[0-9]+: Error: immediate value out of range -- `vcx3a p0,s0,s0,s0,#-1'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx3 p8,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: CDE Coprocessor must be in range 0-7 -- `vcx3a p8,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,s32,s0,s0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,s32,s0,s0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,s0,s32,s0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,s0,s32,s0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,s0,s0,s32,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,s0,s0,s32,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx3 p0,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx3ne p0,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx3a p0,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vcx3ane p0,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx3 p1,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `vcx3a p1,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx3 p0,s0,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: constant expression required -- `vcx3a p0,s0,s0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3 p0,s0,s0,#0'
+[^ :]+:[0-9]+: Error: MVE vector register expected -- `vcx3a p0,s0,s0,#0'
diff --git a/gas/testsuite/gas/arm/cde-warnings.s b/gas/testsuite/gas/arm/cde-warnings.s
index 8e5759a..34b923f 100644
--- a/gas/testsuite/gas/arm/cde-warnings.s
+++ b/gas/testsuite/gas/arm/cde-warnings.s
@@ -333,3 +333,272 @@ cx3da p0, r0, r1, r0, r0, r0, #0
 
 cx3d p0, r0, r0, r0, #0
 cx3da p0, r0, r0, r0, #0
+
+# vcx1{a}
+# Immediate out of range.
+# Each register out of range.
+# IT block => constrained unpredictable
+#
+# Error given when using coprocessor number not enabled on command line.
+# Too many arguments
+# Too little arguments
+
+vcx1 p0, q0, #4096
+vcx1a p0, q0, #4096
+vcx1 p0, q0, #-1
+vcx1a p0, q0, #-1
+
+vcx1 p8, q0, #0
+vcx1a p8, q0, #0
+vcx1 p0, q8, #0
+vcx1a p0, q8, #0
+
+itttt ne
+vcx1 p0, q0, #0
+vcx1ne p0, q0, #0
+vcx1a p0, q0, #0
+vcx1ane p0, q0, #0
+
+vcx1 p1, q0, #0
+vcx1a p1, q0, #0
+
+vcx1 p0, q0, q0, #0
+vcx1a p0, q0, q0, #0
+vcx1 p0, #0
+vcx1a p0, #0
+
+
+vcx1 p0, d0, #2048
+vcx1a p0, d0, #2048
+vcx1 p0, d0, #-1
+vcx1a p0, d0, #-1
+
+vcx1 p8, d0, #0
+vcx1a p8, d0, #0
+vcx1 p0, d16, #0
+vcx1a p0, d16, #0
+
+itttt ne
+vcx1 p0, d0, #0
+vcx1ne p0, d0, #0
+vcx1a p0, d0, #0
+vcx1ane p0, d0, #0
+
+vcx1 p1, d0, #0
+vcx1a p1, d0, #0
+
+vcx1 p0, d0, d0, #0
+vcx1a p0, d0, d0, #0
+vcx1 p0, #0
+vcx1a p0, #0
+
+
+vcx1 p0, s0, #2048
+vcx1a p0, s0, #2048
+vcx1 p0, s0, #-1
+vcx1a p0, s0, #-1
+
+vcx1 p8, s0, #0
+vcx1a p8, s0, #0
+vcx1 p0, s32, #0
+vcx1a p0, s32, #0
+
+itttt ne
+vcx1 p0, s0, #0
+vcx1ne p0, s0, #0
+vcx1a p0, s0, #0
+vcx1ane p0, s0, #0
+
+vcx1 p1, s0, #0
+vcx1a p1, s0, #0
+
+vcx1 p0, s0, s0, #0
+vcx1a p0, s0, s0, #0
+vcx1 p0, #0
+vcx1a p0, #0
+
+
+# vcx2{a}
+# Immediate out of range.
+# Each register out of range.
+# IT block => constrained unpredictable
+#
+# Error given when using coprocessor number not enabled on command line.
+# Too many arguments
+# Too little arguments
+
+vcx2 p0, q0, q0, #128
+vcx2a p0, q0, q0, #128
+vcx2 p0, q0, q0, #-1
+vcx2a p0, q0, q0, #-1
+
+vcx2 p8, q0, q0, #0
+vcx2a p8, q0, q0, #0
+vcx2 p0, q8, q0, #0
+vcx2a p0, q8, q0, #0
+vcx2 p0, q0, q8, #0
+vcx2a p0, q0, q8, #0
+
+itttt ne
+vcx2 p0, q0, q0, #0
+vcx2ne p0, q0, q0, #0
+vcx2a p0, q0, q0, #0
+vcx2ane p0, q0, q0, #0
+
+vcx2 p1, q0, q0, #0
+vcx2a p1, q0, q0, #0
+
+vcx2 p0, q0, q0, q0, #0
+vcx2a p0, q0, q0, q0, #0
+vcx2 p0, q0, #0
+vcx2a p0, q0, #0
+
+
+vcx2 p0, d0, d0, #64
+vcx2a p0, d0, d0, #64
+vcx2 p0, d0, d0, #-1
+vcx2a p0, d0, d0, #-1
+
+vcx2 p8, d0, d0, #0
+vcx2a p8, d0, d0, #0
+vcx2 p0, d16, d0, #0
+vcx2a p0, d16, d0, #0
+vcx2 p0, d0, d16, #0
+vcx2a p0, d0, d16, #0
+
+itttt ne
+vcx2 p0, d0, d0, #0
+vcx2ne p0, d0, d0, #0
+vcx2a p0, d0, d0, #0
+vcx2ane p0, d0, d0, #0
+
+vcx2 p1, d0, d0, #0
+vcx2a p1, d0, d0, #0
+
+vcx2 p0, d0, d0, d0, #0
+vcx2a p0, d0, d0, d0, #0
+vcx2 p0, d0, #0
+vcx2a p0, d0, #0
+
+
+vcx2 p0, s0, s0, #64
+vcx2a p0, s0, s0, #64
+vcx2 p0, s0, s0, #-1
+vcx2a p0, s0, s0, #-1
+
+vcx2 p8, s0, s0, #0
+vcx2a p8, s0, s0, #0
+vcx2 p0, s32, s0, #0
+vcx2a p0, s32, s0, #0
+vcx2 p0, s0, s32, #0
+vcx2a p0, s0, s32, #0
+
+itttt ne
+vcx2 p0, s0, s0, #0
+vcx2ne p0, s0, s0, #0
+vcx2a p0, s0, s0, #0
+vcx2ane p0, s0, s0, #0
+
+vcx2 p1, s0, s0, #0
+vcx2a p1, s0, s0, #0
+
+vcx2 p0, s0, s0, s0, #0
+vcx2a p0, s0, s0, s0, #0
+vcx2 p0, s0, #0
+vcx2a p0, s0, #0
+
+# vcx3{a}
+# Immediate out of range.
+# Each register out of range.
+# IT block => constrained unpredictable
+#
+# Error given when using coprocessor number not enabled on command line.
+# Too many arguments
+# Too little arguments
+
+vcx3 p0, q0, q0, q0, #16
+vcx3a p0, q0, q0, q0, #16
+vcx3 p0, q0, q0, q0, #-1
+vcx3a p0, q0, q0, q0, #-1
+
+vcx3 p8, q0, q0, q0, #0
+vcx3a p8, q0, q0, q0, #0
+vcx3 p0, q8, q0, q0, #0
+vcx3a p0, q8, q0, q0, #0
+vcx3 p0, q8, q0, q0, #0
+vcx3a p0, q0, q8, q0, #0
+vcx3 p0, q0, q0, q8, #0
+vcx3a p0, q0, q0, q8, #0
+
+itttt ne
+vcx3 p0, q0, q0, q0, #0
+vcx3ne p0, q0, q0, q0, #0
+vcx3a p0, q0, q0, q0, #0
+vcx3ane p0, q0, q0, q0, #0
+
+vcx3 p1, q0, q0, q0, #0
+vcx3a p1, q0, q0, q0, #0
+
+vcx3 p0, q0, q0, q0, q0, #0
+vcx3a p0, q0, q0, q0, q0, #0
+vcx3 p0, q0, q0, #0
+vcx3a p0, q0, q0, #0
+
+
+vcx3 p0, d0, d0, d0, #8
+vcx3a p0, d0, d0, d0, #8
+vcx3 p0, d0, d0, d0, #-1
+vcx3a p0, d0, d0, d0, #-1
+
+vcx3 p8, d0, d0, d0, #0
+vcx3a p8, d0, d0, d0, #0
+vcx3 p0, d16, d0, d0, #0
+vcx3a p0, d16, d0, d0, #0
+vcx3 p0, d0, d16, d0, #0
+vcx3a p0, d0, d16, d0, #0
+vcx3 p0, d0, d0, d16, #0
+vcx3a p0, d0, d0, d16, #0
+
+itttt ne
+vcx3 p0, d0, d0, d0, #0
+vcx3ne p0, d0, d0, d0, #0
+vcx3a p0, d0, d0, d0, #0
+vcx3ane p0, d0, d0, d0, #0
+
+vcx3 p1, d0, d0, d0, #0
+vcx3a p1, d0, d0, d0, #0
+
+vcx3 p0, d0, d0, d0, d0, #0
+vcx3a p0, d0, d0, d0, d0, #0
+vcx3 p0, d0, d0, #0
+vcx3a p0, d0, d0, #0
+
+
+vcx3 p0, s0, s0, s0, #8
+vcx3a p0, s0, s0, s0, #8
+vcx3 p0, s0, s0, s0, #-1
+vcx3a p0, s0, s0, s0, #-1
+
+vcx3 p8, s0, s0, s0, #0
+vcx3a p8, s0, s0, s0, #0
+vcx3 p0, s32, s0, s0, #0
+vcx3a p0, s32, s0, s0, #0
+vcx3 p0, s0, s32, s0, #0
+vcx3a p0, s0, s32, s0, #0
+vcx3 p0, s0, s0, s32, #0
+vcx3a p0, s0, s0, s32, #0
+
+itttt ne
+vcx3 p0, s0, s0, s0, #0
+vcx3ne p0, s0, s0, s0, #0
+vcx3a p0, s0, s0, s0, #0
+vcx3ane p0, s0, s0, s0, #0
+
+vcx3 p1, s0, s0, s0, #0
+vcx3a p1, s0, s0, s0, #0
+
+vcx3 p0, s0, s0, s0, s0, #0
+vcx3a p0, s0, s0, s0, s0, #0
+vcx3 p0, s0, s0, #0
+vcx3a p0, s0, s0, #0
+
diff --git a/gas/testsuite/gas/arm/cde.d b/gas/testsuite/gas/arm/cde.d
index 34de201..0fa02ad 100644
--- a/gas/testsuite/gas/arm/cde.d
+++ b/gas/testsuite/gas/arm/cde.d
@@ -117,3 +117,150 @@
  *[0-9a-f]+:	fe89 0040 	cx3da	p0, r0, r1, r9, r0, #0
  *[0-9a-f]+:	fe80 f040 	cx3da	p0, r0, r1, r0, APSR_nzcv, #0
  *[0-9a-f]+:	fe80 9040 	cx3da	p0, r0, r1, r0, r9, #0
+ *[0-9a-f]+:	ec20 0040 	vcx1	p0, q0, #0
+ *[0-9a-f]+:	ed20 0040 	vcx1	p0, q0, #2048
+ *[0-9a-f]+:	ec2f 0040 	vcx1	p0, q0, #1920
+ *[0-9a-f]+:	ec20 00c0 	vcx1	p0, q0, #64
+ *[0-9a-f]+:	ec20 007f 	vcx1	p0, q0, #63
+ *[0-9a-f]+:	ec20 0740 	vcx1	p7, q0, #0
+ *[0-9a-f]+:	ec20 e040 	vcx1	p0, q7, #0
+ *[0-9a-f]+:	fc20 0040 	vcx1a	p0, q0, #0
+ *[0-9a-f]+:	fd20 0040 	vcx1a	p0, q0, #2048
+ *[0-9a-f]+:	fc2f 0040 	vcx1a	p0, q0, #1920
+ *[0-9a-f]+:	fc20 00c0 	vcx1a	p0, q0, #64
+ *[0-9a-f]+:	fc20 007f 	vcx1a	p0, q0, #63
+ *[0-9a-f]+:	fc20 0740 	vcx1a	p7, q0, #0
+ *[0-9a-f]+:	fc20 e040 	vcx1a	p0, q7, #0
+ *[0-9a-f]+:	fe01 8f00 	vptt\.i8	eq, q0, q0
+ *[0-9a-f]+:	ec20 0040 	vcx1	p0, q0, #0
+ *[0-9a-f]+:	fc20 0040 	vcx1a	p0, q0, #0
+ *[0-9a-f]+:	ec30 0040 	vcx2	p0, q0, q0, #0
+ *[0-9a-f]+:	ed30 0040 	vcx2	p0, q0, q0, #64
+ *[0-9a-f]+:	ec3f 0040 	vcx2	p0, q0, q0, #60
+ *[0-9a-f]+:	ec30 00c0 	vcx2	p0, q0, q0, #2
+ *[0-9a-f]+:	ec30 0050 	vcx2	p0, q0, q0, #1
+ *[0-9a-f]+:	ec30 0740 	vcx2	p7, q0, q0, #0
+ *[0-9a-f]+:	ec30 e040 	vcx2	p0, q7, q0, #0
+ *[0-9a-f]+:	ec30 004e 	vcx2	p0, q0, q7, #0
+ *[0-9a-f]+:	fc30 0040 	vcx2a	p0, q0, q0, #0
+ *[0-9a-f]+:	fd30 0040 	vcx2a	p0, q0, q0, #64
+ *[0-9a-f]+:	fc3f 0040 	vcx2a	p0, q0, q0, #60
+ *[0-9a-f]+:	fc30 00c0 	vcx2a	p0, q0, q0, #2
+ *[0-9a-f]+:	fc30 0050 	vcx2a	p0, q0, q0, #1
+ *[0-9a-f]+:	fc30 0740 	vcx2a	p7, q0, q0, #0
+ *[0-9a-f]+:	fc30 e040 	vcx2a	p0, q7, q0, #0
+ *[0-9a-f]+:	fc30 004e 	vcx2a	p0, q0, q7, #0
+ *[0-9a-f]+:	fe01 8f00 	vptt\.i8	eq, q0, q0
+ *[0-9a-f]+:	ec30 0040 	vcx2	p0, q0, q0, #0
+ *[0-9a-f]+:	fc30 0040 	vcx2a	p0, q0, q0, #0
+ *[0-9a-f]+:	ec80 0040 	vcx3	p0, q0, q0, q0, #0
+ *[0-9a-f]+:	ed80 0040 	vcx3	p0, q0, q0, q0, #8
+ *[0-9a-f]+:	ecb0 0040 	vcx3	p0, q0, q0, q0, #6
+ *[0-9a-f]+:	ec80 0050 	vcx3	p0, q0, q0, q0, #1
+ *[0-9a-f]+:	ec80 0740 	vcx3	p7, q0, q0, q0, #0
+ *[0-9a-f]+:	ec80 e040 	vcx3	p0, q7, q0, q0, #0
+ *[0-9a-f]+:	ec8e 0040 	vcx3	p0, q0, q7, q0, #0
+ *[0-9a-f]+:	ec80 004e 	vcx3	p0, q0, q0, q7, #0
+ *[0-9a-f]+:	fc80 0040 	vcx3a	p0, q0, q0, q0, #0
+ *[0-9a-f]+:	fd80 0040 	vcx3a	p0, q0, q0, q0, #8
+ *[0-9a-f]+:	fcb0 0040 	vcx3a	p0, q0, q0, q0, #6
+ *[0-9a-f]+:	fc80 0050 	vcx3a	p0, q0, q0, q0, #1
+ *[0-9a-f]+:	fc80 0740 	vcx3a	p7, q0, q0, q0, #0
+ *[0-9a-f]+:	fc80 e040 	vcx3a	p0, q7, q0, q0, #0
+ *[0-9a-f]+:	fc8e 0040 	vcx3a	p0, q0, q7, q0, #0
+ *[0-9a-f]+:	fc80 004e 	vcx3a	p0, q0, q0, q7, #0
+ *[0-9a-f]+:	fe01 8f00 	vptt\.i8	eq, q0, q0
+ *[0-9a-f]+:	ec80 0040 	vcx3	p0, q0, q0, q0, #0
+ *[0-9a-f]+:	fc80 0040 	vcx3a	p0, q0, q0, q0, #0
+ *[0-9a-f]+:	ec20 0000 	vcx1	p0, s0, #0
+ *[0-9a-f]+:	ec2f 0000 	vcx1	p0, s0, #1920
+ *[0-9a-f]+:	ec20 0080 	vcx1	p0, s0, #64
+ *[0-9a-f]+:	ec20 003f 	vcx1	p0, s0, #63
+ *[0-9a-f]+:	ec20 0700 	vcx1	p7, s0, #0
+ *[0-9a-f]+:	ec60 0000 	vcx1	p0, s1, #0
+ *[0-9a-f]+:	ec20 f000 	vcx1	p0, s30, #0
+ *[0-9a-f]+:	ed20 0000 	vcx1	p0, d0, #0
+ *[0-9a-f]+:	ed2f 0000 	vcx1	p0, d0, #1920
+ *[0-9a-f]+:	ed20 0080 	vcx1	p0, d0, #64
+ *[0-9a-f]+:	ed20 003f 	vcx1	p0, d0, #63
+ *[0-9a-f]+:	ed20 0700 	vcx1	p7, d0, #0
+ *[0-9a-f]+:	ed20 f000 	vcx1	p0, d15, #0
+ *[0-9a-f]+:	fc20 0000 	vcx1a	p0, s0, #0
+ *[0-9a-f]+:	fc2f 0000 	vcx1a	p0, s0, #1920
+ *[0-9a-f]+:	fc20 0080 	vcx1a	p0, s0, #64
+ *[0-9a-f]+:	fc20 003f 	vcx1a	p0, s0, #63
+ *[0-9a-f]+:	fc20 0700 	vcx1a	p7, s0, #0
+ *[0-9a-f]+:	fc60 0000 	vcx1a	p0, s1, #0
+ *[0-9a-f]+:	fc20 f000 	vcx1a	p0, s30, #0
+ *[0-9a-f]+:	fd20 0000 	vcx1a	p0, d0, #0
+ *[0-9a-f]+:	fd2f 0000 	vcx1a	p0, d0, #1920
+ *[0-9a-f]+:	fd20 0080 	vcx1a	p0, d0, #64
+ *[0-9a-f]+:	fd20 003f 	vcx1a	p0, d0, #63
+ *[0-9a-f]+:	fd20 0700 	vcx1a	p7, d0, #0
+ *[0-9a-f]+:	fd20 f000 	vcx1a	p0, d15, #0
+ *[0-9a-f]+:	ec30 0000 	vcx2	p0, s0, s0, #0
+ *[0-9a-f]+:	ec3f 0000 	vcx2	p0, s0, s0, #60
+ *[0-9a-f]+:	ec30 0080 	vcx2	p0, s0, s0, #2
+ *[0-9a-f]+:	ec30 0010 	vcx2	p0, s0, s0, #1
+ *[0-9a-f]+:	ec30 0700 	vcx2	p7, s0, s0, #0
+ *[0-9a-f]+:	ec70 0000 	vcx2	p0, s1, s0, #0
+ *[0-9a-f]+:	ec30 f000 	vcx2	p0, s30, s0, #0
+ *[0-9a-f]+:	ec30 0020 	vcx2	p0, s0, s1, #0
+ *[0-9a-f]+:	ec30 000f 	vcx2	p0, s0, s30, #0
+ *[0-9a-f]+:	ed30 0000 	vcx2	p0, d0, d0, #0
+ *[0-9a-f]+:	ed3f 0000 	vcx2	p0, d0, d0, #60
+ *[0-9a-f]+:	ed30 0080 	vcx2	p0, d0, d0, #2
+ *[0-9a-f]+:	ed30 0010 	vcx2	p0, d0, d0, #1
+ *[0-9a-f]+:	ed30 0700 	vcx2	p7, d0, d0, #0
+ *[0-9a-f]+:	ed30 f000 	vcx2	p0, d15, d0, #0
+ *[0-9a-f]+:	ed30 000f 	vcx2	p0, d0, d15, #0
+ *[0-9a-f]+:	fc30 0000 	vcx2a	p0, s0, s0, #0
+ *[0-9a-f]+:	fc3f 0000 	vcx2a	p0, s0, s0, #60
+ *[0-9a-f]+:	fc30 0080 	vcx2a	p0, s0, s0, #2
+ *[0-9a-f]+:	fc30 0010 	vcx2a	p0, s0, s0, #1
+ *[0-9a-f]+:	fc30 0700 	vcx2a	p7, s0, s0, #0
+ *[0-9a-f]+:	fc70 0000 	vcx2a	p0, s1, s0, #0
+ *[0-9a-f]+:	fc30 f000 	vcx2a	p0, s30, s0, #0
+ *[0-9a-f]+:	fc30 0020 	vcx2a	p0, s0, s1, #0
+ *[0-9a-f]+:	fc30 000f 	vcx2a	p0, s0, s30, #0
+ *[0-9a-f]+:	fd30 0000 	vcx2a	p0, d0, d0, #0
+ *[0-9a-f]+:	fd3f 0000 	vcx2a	p0, d0, d0, #60
+ *[0-9a-f]+:	fd30 0080 	vcx2a	p0, d0, d0, #2
+ *[0-9a-f]+:	fd30 0010 	vcx2a	p0, d0, d0, #1
+ *[0-9a-f]+:	fd30 0700 	vcx2a	p7, d0, d0, #0
+ *[0-9a-f]+:	fd30 f000 	vcx2a	p0, d15, d0, #0
+ *[0-9a-f]+:	fd30 000f 	vcx2a	p0, d0, d15, #0
+ *[0-9a-f]+:	ec80 0000 	vcx3	p0, s0, s0, s0, #0
+ *[0-9a-f]+:	ecb0 0000 	vcx3	p0, s0, s0, s0, #6
+ *[0-9a-f]+:	ec80 0010 	vcx3	p0, s0, s0, s0, #1
+ *[0-9a-f]+:	ec80 0700 	vcx3	p7, s0, s0, s0, #0
+ *[0-9a-f]+:	ecc0 0000 	vcx3	p0, s1, s0, s0, #0
+ *[0-9a-f]+:	ec80 f000 	vcx3	p0, s30, s0, s0, #0
+ *[0-9a-f]+:	ec80 0080 	vcx3	p0, s0, s1, s0, #0
+ *[0-9a-f]+:	ec8f 0000 	vcx3	p0, s0, s30, s0, #0
+ *[0-9a-f]+:	ec80 0020 	vcx3	p0, s0, s0, s1, #0
+ *[0-9a-f]+:	ec80 000f 	vcx3	p0, s0, s0, s30, #0
+ *[0-9a-f]+:	ed80 0000 	vcx3	p0, d0, d0, d0, #0
+ *[0-9a-f]+:	edb0 0000 	vcx3	p0, d0, d0, d0, #6
+ *[0-9a-f]+:	ed80 0010 	vcx3	p0, d0, d0, d0, #1
+ *[0-9a-f]+:	ed80 0700 	vcx3	p7, d0, d0, d0, #0
+ *[0-9a-f]+:	ed80 f000 	vcx3	p0, d15, d0, d0, #0
+ *[0-9a-f]+:	ed8f 0000 	vcx3	p0, d0, d15, d0, #0
+ *[0-9a-f]+:	ed80 000f 	vcx3	p0, d0, d0, d15, #0
+ *[0-9a-f]+:	fc80 0000 	vcx3a	p0, s0, s0, s0, #0
+ *[0-9a-f]+:	fcb0 0000 	vcx3a	p0, s0, s0, s0, #6
+ *[0-9a-f]+:	fc80 0010 	vcx3a	p0, s0, s0, s0, #1
+ *[0-9a-f]+:	fc80 0700 	vcx3a	p7, s0, s0, s0, #0
+ *[0-9a-f]+:	fcc0 0000 	vcx3a	p0, s1, s0, s0, #0
+ *[0-9a-f]+:	fc80 f000 	vcx3a	p0, s30, s0, s0, #0
+ *[0-9a-f]+:	fc80 0080 	vcx3a	p0, s0, s1, s0, #0
+ *[0-9a-f]+:	fc8f 0000 	vcx3a	p0, s0, s30, s0, #0
+ *[0-9a-f]+:	fc80 0020 	vcx3a	p0, s0, s0, s1, #0
+ *[0-9a-f]+:	fc80 000f 	vcx3a	p0, s0, s0, s30, #0
+ *[0-9a-f]+:	fd80 0000 	vcx3a	p0, d0, d0, d0, #0
+ *[0-9a-f]+:	fdb0 0000 	vcx3a	p0, d0, d0, d0, #6
+ *[0-9a-f]+:	fd80 0010 	vcx3a	p0, d0, d0, d0, #1
+ *[0-9a-f]+:	fd80 0700 	vcx3a	p7, d0, d0, d0, #0
+ *[0-9a-f]+:	fd80 f000 	vcx3a	p0, d15, d0, d0, #0
+ *[0-9a-f]+:	fd8f 0000 	vcx3a	p0, d0, d15, d0, #0
+ *[0-9a-f]+:	fd80 000f 	vcx3a	p0, d0, d0, d15, #0
diff --git a/gas/testsuite/gas/arm/cde.s b/gas/testsuite/gas/arm/cde.s
index 1ee1870..e7ae1ea 100644
--- a/gas/testsuite/gas/arm/cde.s
+++ b/gas/testsuite/gas/arm/cde.s
@@ -1,3 +1,36 @@
 .syntax unified
 
 .include "cde-scalar.s"
+
+# vcx1{a} encoding has the following form
+# 111a110i0d10iiiidddd0pppi1iiiiii (vector form)
+
+# 111a110s0d10iiiidddd0pppi0iiiiii (S/D register form)
+#
+# Variants to test:
+# - immediates that set each set of `i` to ones in turn.
+# - each register set to something non-zero
+#   (where each block of register sets is set to all-ones if possible)
+# - coprocessor set to 7
+
+# vcx2{a} encoding has the following form
+# 111a110i0d11iiiidddd0pppi1mimmmm (vector form)
+# 111a110s0d11iiiidddd0pppi0mimmmm (S/D register form)
+#
+# Variants to test:
+# - immediates that set each set of `i` to ones in turn.
+# - each register set to something non-zero
+#   (where each block of register sets is set to all-ones if possible)
+# - coprocessor set to 7
+
+# vcx3{a} encoding has the following form
+# 111a110i1diinnnndddd0pppn1mimmmm (vector form)
+# 111a110s1diinnnndddd0pppn0mimmmm (S/D register form)
+#
+# Variants to test:
+# - immediates that set each set of `i` to ones in turn.
+# - each register set to something non-zero
+#   (where each block of register sets is set to all-ones if possible)
+# - coprocessor set to 7
+.include "cde-mve.s"
+.include "cde-mve-or-neon.s"
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fb4f262..7ab3a81 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+	* arm-dis.c (print_insn_cde): Define 'V' parse character.
+	(cde_opcodes): Add VCX* instructions.
+
 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 	    Matthew Malcomson  <matthew.malcomson@arm.com>
 
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 2a29887..b926b65 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -514,6 +514,27 @@ static const struct cdeopcode32 cde_opcodes[] =
 	      0xee800040, 0xef800840,
 	     "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"),
 
+  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+	      0xec200000, 0xeeb00840,
+	      "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"),
+  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+	      0xec200040, 0xeeb00840,
+	      "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"),
+
+  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+	      0xec300000, 0xeeb00840,
+	      "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"),
+  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+	      0xec300040, 0xeeb00840,
+	      "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"),
+
+  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+	      0xec800000, 0xee800840,
+	      "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"),
+  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
+	      0xec800040, 0xee800840,
+	      "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"),
+
   CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
 
 };
@@ -8920,6 +8941,25 @@ print_insn_cde (struct disassemble_info *info, long given, bfd_boolean thumb)
 		    func (stream, "%ld", value);
 		    break;
 
+		  case 'V':
+		    if (given & (1 << 6))
+		      func (stream, "q%ld", value >> 1);
+		    else if (given & (1 << 24))
+		      func (stream, "d%ld", value);
+		    else
+		      {
+			/* Encoding for S register is different than for D and
+			   Q registers.  S registers are encoded using the top
+			   single bit in position 22 as the lowest bit of the
+			   register number, while for Q and D it represents the
+			   highest bit of the register number.  */
+			uint8_t top_bit = (value >> 4) & 1;
+			uint8_t tmp = (value << 1) & 0x1e;
+			uint8_t res = tmp | top_bit;
+			func (stream, "s%u", res);
+		      }
+		    break;
+
 		default:
 		  abort ();
 		}