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| author | Michael Clark <michaeljclark@mac.com> | 2017-04-27 16:08:46 +1200 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-05-02 15:19:07 -0700 |
| commit | 43e379d74c994fe431368b5f25f778bf601a2981 (patch) | |
| tree | c35649586f7b5caa472a2c5a6e55079cae3e8372 | |
| parent | 763a5fa4f330d6d3859c94a69ba1fcab09330cf9 (diff) | |
| download | gdb-43e379d74c994fe431368b5f25f778bf601a2981.zip gdb-43e379d74c994fe431368b5f25f778bf601a2981.tar.gz gdb-43e379d74c994fe431368b5f25f778bf601a2981.tar.bz2 | |
RISC-V: Change CALL macro to use ra as the temporary address register
e.g.
1: auipc ra, %pcrel_hi(symbol)
jalr ra, %pcrel_lo(1b)(ra)
The use of ra instead of t1 for address construction provides an
opportunity for a microarchitecture to elide the write of the
destination address, and instead read the target address as an
immediate spread across the fused auipc+jalr pair. The link
register ra in the jalr overwrites the target address temporary.
2017-05-01 Michael Clark <michaeljclark@mac.com>
* riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
register.
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index dcde282..355a162 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2017-05-01 Michael Clark <michaeljclark@mac.com> + + * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary + register. + 2017-05-02 Maciej W. Rozycki <macro@imgtec.com> * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index c629d2f..0188a65 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -147,7 +147,7 @@ const struct riscv_opcode riscv_opcodes[] = {"jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS }, {"jal", "I", "a", MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS }, {"call", "I", "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, -{"call", "I", "c", (X_T1 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO }, +{"call", "I", "c", (X_RA << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO }, {"tail", "I", "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, {"jump", "I", "c,s", 0, (int) M_CALL, match_never, INSN_MACRO }, {"nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, |