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authorJim Wilson <wilson@tuliptree.org>2002-09-30 20:11:08 +0000
committerJim Wilson <wilson@tuliptree.org>2002-09-30 20:11:08 +0000
commit30458d39d6f791293f844ab9f75c4f465d52e74c (patch)
tree8a55b9eea403c0a40d598cffec3c9f4d8bbff7bf
parent28ee05e92474f1a72e289ff06050351938b8f807 (diff)
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Fix handling of v850e bit-twiddle instructions.
* simops.c (OP_E6077E0): And op1 with 7 after reading register, not before. (BIT_CHANGE_OP): Likewise.
-rw-r--r--sim/v850/ChangeLog6
-rw-r--r--sim/v850/simops.c4
2 files changed, 8 insertions, 2 deletions
diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index 100ece1..2053096 100644
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,3 +1,9 @@
+2002-09-27 Jim Wilson <wilson@redhat.com>
+
+ * simops.c (OP_E6077E0): And op1 with 7 after reading register, not
+ before.
+ (BIT_CHANGE_OP): Likewise.
+
2002-09-26 Jim Wilson <wilson@redhat.com>
* simops (OP_10007E0): Don't subtract 4 from PC.
diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index eba728f..0404523 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -1897,7 +1897,7 @@ OP_E607E0 (void)
temp = load_mem (State.regs[ OP[0] ], 1);
PSW &= ~PSW_Z;
- if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
+ if ((temp & (1 << (State.regs[ OP[1] ] & 0x7))) == 0)
PSW |= PSW_Z;
trace_output (OP_BIT);
@@ -1924,7 +1924,7 @@ OP_22207E0 (void)
\
trace_input (name, OP_BIT_CHANGE, 0); \
\
- bit = 1 << State.regs[ OP[1] & 0x7 ]; \
+ bit = 1 << (State.regs[ OP[1] ] & 0x7); \
temp = load_mem (State.regs[ OP[0] ], 1); \
\
PSW &= ~PSW_Z; \