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| author | Jozef Lawrynowicz <jozef.l@mittosystems.com> | 2020-01-22 21:44:54 +0000 |
|---|---|---|
| committer | Jozef Lawrynowicz <jozef.l@mittosystems.com> | 2020-01-22 21:52:29 +0000 |
| commit | b7dcc42dfde12c3a1ccb7149b3cf8ef2f0992ea3 (patch) | |
| tree | c2a177ad023f97f05bedfaa9271e035e371d6a09 | |
| parent | be4c5e58bdc839898739e0332aee84abf6e5299a (diff) | |
| download | gdb-b7dcc42dfde12c3a1ccb7149b3cf8ef2f0992ea3.zip gdb-b7dcc42dfde12c3a1ccb7149b3cf8ef2f0992ea3.tar.gz gdb-b7dcc42dfde12c3a1ccb7149b3cf8ef2f0992ea3.tar.bz2 | |
MSP430: Fix simulator execution of RRUX instruction
The MSP430X RRUX instruction (unsigned right shift) is synthesized as
the RRC (rotate right through carry) instruction, but with the ZC
(zero carry) bit of the opcode extention word set.
Ensure the carry flag is ignored when the ZC bit is set.
sim/msp430/ChangeLog:
2020-01-22 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* msp430-sim.c (msp430_step_once): Ignore the carry flag when executing
an RRC instruction, if the ZC bit of the extension word is set.
sim/testsuite/sim/msp430/ChangeLog:
2020-01-22 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* rrux.s: New test.
| -rw-r--r-- | sim/msp430/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/msp430/msp430-sim.c | 6 | ||||
| -rw-r--r-- | sim/testsuite/sim/msp430/ChangeLog | 4 | ||||
| -rw-r--r-- | sim/testsuite/sim/msp430/rrux.s | 14 |
4 files changed, 27 insertions, 2 deletions
diff --git a/sim/msp430/ChangeLog b/sim/msp430/ChangeLog index 324a6fc..0f27982 100644 --- a/sim/msp430/ChangeLog +++ b/sim/msp430/ChangeLog @@ -1,3 +1,8 @@ +2020-01-22 Jozef Lawrynowicz <jozef.l@mittosystems.com> + + * msp430-sim.c (msp430_step_once): Ignore the carry flag when executing + an RRC instruction, if the ZC bit of the extension word is set. + 2017-09-06 John Baldwin <jhb@FreeBSD.org> * configure: Regenerate. diff --git a/sim/msp430/msp430-sim.c b/sim/msp430/msp430-sim.c index cdb8eab..e21c8cf 100644 --- a/sim/msp430/msp430-sim.c +++ b/sim/msp430/msp430-sim.c @@ -1292,8 +1292,10 @@ msp430_step_once (SIM_DESC sd) u1 = SRC; carry_to_use = u1 & 1; uresult = u1 >> 1; - if (SR & MSP430_FLAG_C) - uresult |= (1 << (opcode->size - 1)); + /* If the ZC bit of the opcode is set, it means we are synthesizing + RRUX, so the carry bit must be ignored. */ + if (opcode->zc == 0 && (SR & MSP430_FLAG_C)) + uresult |= (1 << (opcode->size - 1)); TRACE_ALU (MSP430_CPU (sd), "RRC: %#x >>= %#x", u1, uresult); DEST (uresult); diff --git a/sim/testsuite/sim/msp430/ChangeLog b/sim/testsuite/sim/msp430/ChangeLog index 458ee21..7dc370f 100644 --- a/sim/testsuite/sim/msp430/ChangeLog +++ b/sim/testsuite/sim/msp430/ChangeLog @@ -1,3 +1,7 @@ +2020-01-22 Jozef Lawrynowicz <jozef.l@mittosystems.com> + + * rrux.s: New test. + 2016-01-05 Nick Clifton <nickc@redhat.com> * testutils.inc (__pass): Use the LMA addresses of the _passmsg diff --git a/sim/testsuite/sim/msp430/rrux.s b/sim/testsuite/sim/msp430/rrux.s new file mode 100644 index 0000000..07fc8d5 --- /dev/null +++ b/sim/testsuite/sim/msp430/rrux.s @@ -0,0 +1,14 @@ +# check that rrux (synthesized as rrc with ZC bit set) works. +# mach: msp430 + +.include "testutils.inc" + + start + + setc ; set the carry bit to ensure ZC bit is obeyed + mov.w #16, r10 + rrux.w r10 + cmp.w #8, r10 + jeq 1f + fail + 1: pass |