2007-05-18 Paul Brook <paul@codesourcery.com>

	bfd/
	* elf32-arm.c (ARM2THUMB_V5_STATIC_GLUE_SIZE): Define.
	(a2t1v5_ldr_insn, a2t1v5_ldr_insn): New.
	(record_arm_to_thumb_glue): Add v5t non-pic glue.
	(elf32_arm_create_thumb_stub): Ditto.

	ld/testsuite/
	* ld-arm/arm-call.d: Update expected output.

4 files changed, 41 insertions, 10 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index ab4a46f..6d8c673 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,10 @@
+2007-05-18  Paul Brook  <paul@codesourcery.com>
+
+	* elf32-arm.c (ARM2THUMB_V5_STATIC_GLUE_SIZE): Define.
+	(a2t1v5_ldr_insn, a2t1v5_ldr_insn): New.
+	(record_arm_to_thumb_glue): Add v5t non-pic glue.
+	(elf32_arm_create_thumb_stub): Ditto.
+
 2007-05-16  H.J. Lu  <hongjiu.lu@intel.com>
 	    Alan Modra  <amodra@bigpond.net.au>
 
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 8b5d31e..d36c923e 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -2582,6 +2582,13 @@ find_arm_glue (struct bfd_link_info *link_info,
    __func_addr:
    .word func    @ behave as if you saw a ARM_32 reloc.  
 
+   (v5t static images)
+   .arm
+   __func_from_arm:
+   ldr pc, __func_addr
+   __func_addr:
+   .word func    @ behave as if you saw a ARM_32 reloc.  
+
    (relocatable images)
    .arm
    __func_from_arm:
@@ -2597,6 +2604,10 @@ static const insn32 a2t1_ldr_insn = 0xe59fc000;
 static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
 static const insn32 a2t3_func_addr_insn = 0x00000001;
 
+#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
+static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
+static const insn32 a2t2v5_func_addr_insn = 0x00000001;
+
 #define ARM2THUMB_PIC_GLUE_SIZE 16
 static const insn32 a2t1p_ldr_insn = 0xe59fc004;
 static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
@@ -2745,6 +2756,8 @@ record_arm_to_thumb_glue (struct bfd_link_info * link_info,
   if (link_info->shared || globals->root.is_relocatable_executable
       || globals->pic_veneer)
     size = ARM2THUMB_PIC_GLUE_SIZE;
+  else if (globals->use_blx)
+    size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
   else
     size = ARM2THUMB_STATIC_GLUE_SIZE;
 
@@ -4187,6 +4200,15 @@ elf32_arm_create_thumb_stub (struct bfd_link_info * info,
 	  bfd_put_32 (output_bfd, ret_offset,
 		      s->contents + my_offset + 12);
 	}
+      else if (globals->use_blx)
+	{
+	  put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
+			s->contents + my_offset);
+
+	  /* It's a thumb address.  Add the low order bit.  */
+	  bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
+		      s->contents + my_offset + 4);
+	}
       else
 	{
 	  put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index acad897..d3b7727 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2007-05-18  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-call.d: Update expected output.
+
 2007-05-17  Paul Brook  <paul@codesourcery.com>
 
 	* ld-elf/multibss1.s: Use %nobits instead of @nobits.
diff --git a/ld/testsuite/ld-arm/arm-call.d b/ld/testsuite/ld-arm/arm-call.d
index fd4cd13..3a55deb 100644
--- a/ld/testsuite/ld-arm/arm-call.d
+++ b/ld/testsuite/ld-arm/arm-call.d
@@ -11,9 +11,9 @@ Disassembly of section .text:
     8010:	fa00000a 	blx	8040 <t1>
     8014:	fb000009 	blx	8042 <t2>
     8018:	ea00000f 	b	805c <__t1_from_arm>
-    801c:	ea000011 	b	8068 <__t2_from_arm>
+    801c:	ea000010 	b	8064 <__t2_from_arm>
     8020:	1b00000d 	blne	805c <__t1_from_arm>
-    8024:	1b00000f 	blne	8068 <__t2_from_arm>
+    8024:	1b00000e 	blne	8064 <__t2_from_arm>
     8028:	1b000003 	blne	803c <arm>
     802c:	eb000002 	bl	803c <arm>
     8030:	faffffff 	blx	8034 <thumblocal>
@@ -48,11 +48,9 @@ Disassembly of section .text:
     8058:	f7ff efd2 	blx	8000 <_start>
 
 0000805c <__t1_from_arm>:
-    805c:	e59fc000 	ldr	ip, \[pc, #0\]	; 8064 <__t1_from_arm\+0x8>
-    8060:	e12fff1c 	bx	ip
-    8064:	00008041 	andeq	r8, r0, r1, asr #32
-
-00008068 <__t2_from_arm>:
-    8068:	e59fc000 	ldr	ip, \[pc, #0\]	; 8070 <__t2_from_arm\+0x8>
-    806c:	e12fff1c 	bx	ip
-    8070:	00008043 	andeq	r8, r0, r3, asr #32
+    805c:	e51ff004 	ldr	pc, \[pc, #-4\]	; 8060 <__t1_from_arm\+0x4>
+    8060:	00008041 	andeq	r8, r0, r1, asr #32
+
+00008064 <__t2_from_arm>:
+    8064:	e51ff004 	ldr	pc, \[pc, #-4\]	; 8068 <__t2_from_arm\+0x4>
+    8068:	00008043 	andeq	r8, r0, r3, asr #32