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| author | Andrew Cagney <cagney@redhat.com> | 1997-10-20 06:28:53 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-10-20 06:28:53 +0000 |
| commit | fb5a2a3e39415db044b18604f0ffe0f07a9b83bf (patch) | |
| tree | 3d55edc821cbfc2f62a48e049af590075f1bec0b | |
| parent | 27637913f0a6553b6836761810564d1cdbf0a02f (diff) | |
| download | gdb-fb5a2a3e39415db044b18604f0ffe0f07a9b83bf.zip gdb-fb5a2a3e39415db044b18604f0ffe0f07a9b83bf.tar.gz gdb-fb5a2a3e39415db044b18604f0ffe0f07a9b83bf.tar.bz2 | |
Make mips registers of type unsigned_word.
Ensure all references to MIPS registers use same type.
| -rw-r--r-- | sim/mips/ChangeLog | 10 | ||||
| -rw-r--r-- | sim/mips/interp.c | 2 | ||||
| -rw-r--r-- | sim/mips/sim-main.h | 5 |
3 files changed, 14 insertions, 3 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 062eb62..ea4da46 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,13 @@ +Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word. + + * interp.c (sim_monitor): Make register pointers of type + unsigned_word*. + + * sim-main.h: Make registers of type unsigned_word not + signed_word. + Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com> start-sanitize-r5900 diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 9066b0b..613208b 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -1312,7 +1312,7 @@ sim_monitor(sd,reason) having to allocate and manage a temporary string buffer. */ if (AddressTranslation(A0,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL)) { char *s = (char *)((int)paddr); - ut_reg *ap = &A1; /* 1st argument */ + signed_word *ap = &A1; /* 1st argument */ /* TODO: Include check that we only use three arguments (A1, A2 and A3) */ for (; *s;) { if (*s == '%') { diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index 7822749..4a07706 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -72,9 +72,10 @@ typedef unsigned64 uword64; assume the HI32bits of the operand are zero, so we must perform a mask to ensure we can use the simple subtraction to sign-extend. */ #define SIGNEXTEND(e,b) \ + ((unsigned_word) \ (((e) & ((uword64) 1 << ((b) - 1))) \ ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \ - : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))) + : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1)))) /* Check if a value will fit within a halfword: */ #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1)) @@ -354,7 +355,7 @@ struct _sim_cpu { vector of registers. The internal simulator engine then uses manifests to access the correct slot. */ - signed_word registers[LAST_EMBED_REGNUM + 1]; + unsigned_word registers[LAST_EMBED_REGNUM + 1]; int register_widths[NUM_REGS]; #define REGISTERS ((STATE_CPU (sd,0))->registers) |