`.arch cpu_type' pseudo for x86.

6 files changed, 1060 insertions, 890 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 4c7dd46..742abf8 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,23 @@
+2000-05-13  Alan Modra  <alan@linuxcare.com.au>
+	    Alexander Sokolov <robocop@netlink.ru>
+
+	* doc/c-i386.texi (i386-Arch): New section.
+	(i386-Syntax): Mention .intel_syntax and .att_syntax.
+
+	* config/tc-i386.c (cpu_arch_name, cpu_arch_flags): New.
+	(smallest_imm_type): Use smallest opcode for shift by one if cpu
+	architecture has been given and is not 486.
+	(set_cpu_arch): New.
+	(md_pseudo_table): Add .arch.
+	(md_assemble): Warn if cpu architecture has been given and an
+	unsupported instruction.
+
+	* config/tc-i386.h (SMALLEST_DISP_TYPE): Delete.
+	Move operand_types bit defines after relevant template field.
+	(template): Add cpu_flags.
+	(Cpu*): Define.
+	(arch_entry): New.
+
 2000-05-12  Alexandre Oliva  <aoliva@cygnus.com>
 
 	* config/tc-mn10300.h (md_end): Define.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 6072e55..2ba676d 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -62,6 +62,7 @@ static int add_prefix PARAMS ((unsigned int));
 static void set_16bit_code_flag PARAMS ((int));
 static void set_16bit_gcc_code_flag PARAMS((int));
 static void set_intel_syntax PARAMS ((int));
+static void set_cpu_arch PARAMS ((int));
 
 #ifdef BFD_ASSEMBLER
 static bfd_reloc_code_real_type reloc
@@ -216,15 +217,20 @@ static const templates *current_templates;
 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
 static expressionS disp_expressions[2], im_expressions[2];
 
-static int this_operand;	/* current operand we are working on */
+static int this_operand;	  /* Current operand we are working on.  */
 
-static int flag_do_long_jump;	/* FIXME what does this do? */
+static int flag_do_long_jump;	  /* FIXME what does this do?  */
 
-static int flag_16bit_code;	/* 1 if we're writing 16-bit code, 0 if 32-bit */
+static int flag_16bit_code;	  /* 1 if we're writing 16-bit code,
+				     0 if 32-bit.  */
 
-static int intel_syntax = 0;	/* 1 for intel syntax, 0 if att syntax */
+static int intel_syntax = 0;	  /* 1 for intel syntax, 0 if att syntax.  */
 
-static int allow_naked_reg = 0;  /* 1 if register prefix % not required */
+static const char *cpu_arch_name = NULL; /* cpu name  */
+
+static unsigned int cpu_arch_flags = 0;  /* cpu feature flags  */
+
+static int allow_naked_reg = 0;   /* 1 if register prefix % not required  */
 
 static char stackop_size = '\0';  /* Used in 16 bit gcc mode to add an l
 				     suffix to call, ret, enter, leave, push,
@@ -301,6 +307,21 @@ const relax_typeS md_relax_table[] =
 
 };
 
+static const arch_entry cpu_arch[] = {
+  {"i8086",	Cpu086 },
+  {"i186",	Cpu086|Cpu186 },
+  {"i286",	Cpu086|Cpu186|Cpu286 },
+  {"i386",	Cpu086|Cpu186|Cpu286|Cpu386 },
+  {"i486",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
+  {"i586",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
+  {"i686",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
+  {"pentium",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
+  {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
+  {"k6",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX|Cpu3dnow },
+  {"athlon",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|Cpu3dnow },
+  {NULL, 0 }
+};
+
 
 void
 i386_align_code (fragP, count)
@@ -441,16 +462,17 @@ static int
 smallest_imm_type (num)
      offsetT num;
 {
-#if 0
-  /* This code is disabled because all the Imm1 forms in the opcode table
-     are slower on the i486, and they're the versions with the implicitly
-     specified single-position displacement, which has another syntax if
-     you really want to use that form.  If you really prefer to have the
-     one-byte-shorter Imm1 form despite these problems, re-enable this
-     code.  */
-  if (num == 1)
-    return Imm1 | Imm8 | Imm8S | Imm16 | Imm32;
-#endif
+  if (cpu_arch_flags != 0
+      && cpu_arch_flags != (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486))
+    {
+      /* This code is disabled on the 486 because all the Imm1 forms
+	 in the opcode table are slower on the i486.  They're the
+	 versions with the implicitly specified single-position
+	 displacement, which has another syntax if you really want to
+	 use that form.  */
+      if (num == 1)
+	return Imm1 | Imm8 | Imm8S | Imm16 | Imm32;
+    }
   return (fits_in_signed_byte (num)
 	  ? (Imm8S | Imm8 | Imm16 | Imm32)
 	  : fits_in_unsigned_byte (num)
@@ -600,16 +622,49 @@ set_intel_syntax (syntax_flag)
     allow_naked_reg = (ask_naked_reg < 0);
 }
 
+static void
+set_cpu_arch (dummy)
+    int dummy ATTRIBUTE_UNUSED;
+{
+  SKIP_WHITESPACE();
+
+  if (! is_end_of_line[(unsigned char) *input_line_pointer])
+    {
+      char *string = input_line_pointer;
+      int e = get_symbol_end ();
+      int i;
+
+      for (i = 0; cpu_arch[i].name; i++)
+	{
+	  if (strcmp (string, cpu_arch[i].name) == 0)
+	    {
+	      cpu_arch_name = cpu_arch[i].name;
+	      cpu_arch_flags = cpu_arch[i].flags;
+	      break;
+	    }
+	}
+      if (!cpu_arch[i].name)
+	as_bad (_("no such architecture: `%s'"), string);
+
+      *input_line_pointer = e;
+    }
+  else
+    as_bad (_("missing cpu architecture"));
+
+  demand_empty_rest_of_line ();
+}
+
 const pseudo_typeS md_pseudo_table[] =
 {
-#ifndef I386COFF
-  {"bss", s_bss, 0},
-#endif
 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
   {"align", s_align_bytes, 0},
 #else
   {"align", s_align_ptwo, 0},
 #endif
+  {"arch", set_cpu_arch, 0},
+#ifndef I386COFF
+  {"bss", s_bss, 0},
+#endif
   {"ffloat", float_cons, 'f'},
   {"dfloat", float_cons, 'd'},
   {"tfloat", float_cons, 'x'},
@@ -1058,7 +1113,7 @@ md_assemble (line)
 	    mnem_p++;
 	    if (mnem_p >= mnemonic + sizeof (mnemonic))
 	      {
-		as_bad (_("no such 386 instruction: `%s'"), token_start);
+		as_bad (_("no such instruction: `%s'"), token_start);
 		return;
 	      }
 	    l++;
@@ -1141,11 +1196,25 @@ md_assemble (line)
 	  }
 	if (!current_templates)
 	  {
-	    as_bad (_("no such 386 instruction: `%s'"), token_start);
+	    as_bad (_("no such instruction: `%s'"), token_start);
 	    return;
 	  }
       }
 
+    /* Check if instruction is supported on specified architecture.  */
+    if (cpu_arch_flags != 0)
+      {
+	if (current_templates->start->cpu_flags & ~ cpu_arch_flags)
+	  {
+	    as_warn (_("`%s' is not supported on `%s'"),
+		     current_templates->start->name, cpu_arch_name);
+	  }
+	else if ((Cpu386 & ~ cpu_arch_flags) && !flag_16bit_code)
+	  {
+	    as_warn (_("use .code16 to ensure correct addressing mode"));
+	  }
+      }
+
     /* check for rep/repne without a string instruction */
     if (expecting_string_instruction
 	&& !(current_templates->start->opcode_modifier & IsString))
diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h
index 2bf9a7f..c435690 100644
--- a/gas/config/tc-i386.h
+++ b/gas/config/tc-i386.h
@@ -239,77 +239,7 @@ extern const char extra_symbol_chars[];
 #define OFFSET_FLAT  6
 #define FLAT         7
 #define NONE_FOUND   8
-/*
-  When an operand is read in it is classified by its type.  This type includes
-  all the possible ways an operand can be used.  Thus, '%eax' is both 'register
-  # 0' and 'The Accumulator'.  In our language this is expressed by OR'ing
-  'Reg32' (any 32 bit register) and 'Acc' (the accumulator).
-  Operands are classified so that we can match given operand types with
-  the opcode table in opcode/i386.h.
-  */
-/* register */
-#define Reg8		   0x1	/* 8 bit reg */
-#define Reg16		   0x2	/* 16 bit reg */
-#define Reg32		   0x4	/* 32 bit reg */
-/* immediate */
-#define Imm8		   0x8	/* 8 bit immediate */
-#define Imm8S		  0x10	/* 8 bit immediate sign extended */
-#define Imm16		  0x20	/* 16 bit immediate */
-#define Imm32		  0x40	/* 32 bit immediate */
-#define Imm1		  0x80	/* 1 bit immediate */
-/* memory */
-#define BaseIndex	 0x100
-/* Disp8,16,32 are used in different ways, depending on the
-   instruction.  For jumps, they specify the size of the PC relative
-   displacement, for baseindex type instructions, they specify the
-   size of the offset relative to the base register, and for memory
-   offset instructions such as `mov 1234,%al' they specify the size of
-   the offset relative to the segment base.  */
-#define Disp8		 0x200	/* 8 bit displacement */
-#define Disp16		 0x400	/* 16 bit displacement */
-#define Disp32		 0x800	/* 32 bit displacement */
-/* specials */
-#define InOutPortReg	0x1000	/* register to hold in/out port addr = dx */
-#define ShiftCount	0x2000	/* register to hold shift cound = cl */
-#define Control	        0x4000	/* Control register */
-#define Debug	        0x8000	/* Debug register */
-#define Test	       0x10000	/* Test register */
-#define FloatReg       0x20000	/* Float register */
-#define FloatAcc       0x40000	/* Float stack top %st(0) */
-#define SReg2	       0x80000	/* 2 bit segment register */
-#define SReg3	      0x100000	/* 3 bit segment register */
-#define Acc	      0x200000	/* Accumulator %al or %ax or %eax */
-#define JumpAbsolute  0x400000
-#define RegMMX	      0x800000	/* MMX register */
-#define RegXMM	     0x1000000	/* XMM registers in PIII */
-#define EsSeg	     0x2000000	/* String insn operand with fixed es segment */
-/* InvMem is for instructions with a modrm byte that only allow a
-   general register encoding in the i.tm.mode and i.tm.regmem fields,
-   eg. control reg moves.  They really ought to support a memory form,
-   but don't, so we add an InvMem flag to the register operand to
-   indicate that it should be encoded in the i.tm.regmem field.  */
-#define InvMem	     0x4000000
 
-#define Reg	(Reg8|Reg16|Reg32)	/* gen'l register */
-#define WordReg (Reg16|Reg32)
-#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
-#define Imm	(Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
-#define Disp	(Disp8|Disp16|Disp32)	/* General displacement */
-#define AnyMem	(Disp|BaseIndex|InvMem)	/* General memory */
-/* The following aliases are defined because the opcode table
-   carefully specifies the allowed memory types for each instruction.
-   At the moment we can only tell a memory reference size by the
-   instruction suffix, so there's not much point in defining Mem8,
-   Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
-   the suffix directly to check memory operands.  */
-#define LLongMem AnyMem		/* 64 bits (or more) */
-#define LongMem AnyMem		/* 32 bit memory ref */
-#define ShortMem AnyMem		/* 16 bit memory ref */
-#define WordMem AnyMem		/* 16 or 32 bit memory ref */
-#define ByteMem AnyMem		/* 8 bit memory ref */
-
-#define SMALLEST_DISP_TYPE(num) \
-    (fits_in_signed_byte(num) ? (Disp8|Disp32) : Disp32)
 
 typedef struct
 {
@@ -330,6 +260,19 @@ typedef struct
   unsigned int extension_opcode;
 #define None 0xffff		/* If no extension_opcode is possible. */
 
+  /* cpu feature flags */
+  unsigned int cpu_flags;
+#define Cpu086		  0x1	/* Any old cpu will do, 0 does the same */
+#define Cpu186		  0x2	/* i186 or better required */
+#define Cpu286		  0x4	/* i286 or better required */
+#define Cpu386		  0x8	/* i386 or better required */
+#define Cpu486		 0x10	/* i486 or better required */
+#define Cpu586		 0x20	/* i585 or better required */
+#define Cpu686		 0x40	/* i686 or better required */
+#define CpuMMX		 0x80	/* MMX support required */
+#define CpuSSE		0x100	/* Streaming SIMD extensions required */
+#define Cpu3dnow	0x200	/* 3dnow! support required */
+
   /* the bits in opcode_modifier are used to generate the final opcode from
      the base_opcode.  These bits also are used to detect alternate forms of
      the same instruction */
@@ -371,8 +314,70 @@ typedef struct
   /* operand_types[i] describes the type of operand i.  This is made
      by OR'ing together all of the possible type masks.  (e.g.
      'operand_types[i] = Reg|Imm' specifies that operand i can be
-     either a register or an immediate operand */
+     either a register or an immediate operand.  */
   unsigned int operand_types[3];
+
+  /* operand_types[i] bits */
+  /* register */
+#define Reg8		   0x1	/* 8 bit reg */
+#define Reg16		   0x2	/* 16 bit reg */
+#define Reg32		   0x4	/* 32 bit reg */
+  /* immediate */
+#define Imm8		   0x8	/* 8 bit immediate */
+#define Imm8S		  0x10	/* 8 bit immediate sign extended */
+#define Imm16		  0x20	/* 16 bit immediate */
+#define Imm32		  0x40	/* 32 bit immediate */
+#define Imm1		  0x80	/* 1 bit immediate */
+  /* memory */
+#define BaseIndex	 0x100
+  /* Disp8,16,32 are used in different ways, depending on the
+     instruction.  For jumps, they specify the size of the PC relative
+     displacement, for baseindex type instructions, they specify the
+     size of the offset relative to the base register, and for memory
+     offset instructions such as `mov 1234,%al' they specify the size of
+     the offset relative to the segment base.  */
+#define Disp8		 0x200	/* 8 bit displacement */
+#define Disp16		 0x400	/* 16 bit displacement */
+#define Disp32		 0x800	/* 32 bit displacement */
+  /* specials */
+#define InOutPortReg	0x1000	/* register to hold in/out port addr = dx */
+#define ShiftCount	0x2000	/* register to hold shift cound = cl */
+#define Control	        0x4000	/* Control register */
+#define Debug	        0x8000	/* Debug register */
+#define Test	       0x10000	/* Test register */
+#define FloatReg       0x20000	/* Float register */
+#define FloatAcc       0x40000	/* Float stack top %st(0) */
+#define SReg2	       0x80000	/* 2 bit segment register */
+#define SReg3	      0x100000	/* 3 bit segment register */
+#define Acc	      0x200000	/* Accumulator %al or %ax or %eax */
+#define JumpAbsolute  0x400000
+#define RegMMX	      0x800000	/* MMX register */
+#define RegXMM	     0x1000000	/* XMM registers in PIII */
+#define EsSeg	     0x2000000	/* String insn operand with fixed es segment */
+  /* InvMem is for instructions with a modrm byte that only allow a
+     general register encoding in the i.tm.mode and i.tm.regmem fields,
+     eg. control reg moves.  They really ought to support a memory form,
+     but don't, so we add an InvMem flag to the register operand to
+     indicate that it should be encoded in the i.tm.regmem field.  */
+#define InvMem	     0x4000000
+
+#define Reg	(Reg8|Reg16|Reg32)	/* gen'l register */
+#define WordReg (Reg16|Reg32)
+#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
+#define Imm	(Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
+#define Disp	(Disp8|Disp16|Disp32)	/* General displacement */
+#define AnyMem	(Disp|BaseIndex|InvMem)	/* General memory */
+  /* The following aliases are defined because the opcode table
+     carefully specifies the allowed memory types for each instruction.
+     At the moment we can only tell a memory reference size by the
+     instruction suffix, so there's not much point in defining Mem8,
+     Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
+     the suffix directly to check memory operands.  */
+#define LLongMem AnyMem		/* 64 bits (or more) */
+#define LongMem AnyMem		/* 32 bit memory ref */
+#define ShortMem AnyMem		/* 16 bit memory ref */
+#define WordMem AnyMem		/* 16 or 32 bit memory ref */
+#define ByteMem AnyMem		/* 8 bit memory ref */
 }
 template;
 
@@ -384,45 +389,54 @@ template;
   END.
   */
 typedef struct
-  {
-    const template *start;
-    const template *end;
-  } templates;
+{
+  const template *start;
+  const template *end;
+}
+templates;
 
 /* these are for register name --> number & type hash lookup */
 typedef struct
-  {
-    char *reg_name;
-    unsigned int reg_type;
-    unsigned int reg_num;
-  }
+{
+  char *reg_name;
+  unsigned int reg_type;
+  unsigned int reg_num;
+}
 reg_entry;
 
 typedef struct
-  {
-    char *seg_name;
-    unsigned int seg_prefix;
-  }
+{
+  char *seg_name;
+  unsigned int seg_prefix;
+}
 seg_entry;
 
 /* 386 operand encoding bytes:  see 386 book for details of this. */
 typedef struct
-  {
-    unsigned int regmem;	/* codes register or memory operand */
-    unsigned int reg;		/* codes register operand (or extended opcode) */
-    unsigned int mode;		/* how to interpret regmem & reg */
-  }
+{
+  unsigned int regmem;	/* codes register or memory operand */
+  unsigned int reg;	/* codes register operand (or extended opcode) */
+  unsigned int mode;	/* how to interpret regmem & reg */
+}
 modrm_byte;
 
 /* 386 opcode byte to code indirect addressing. */
 typedef struct
-  {
-    unsigned base;
-    unsigned index;
-    unsigned scale;
-  }
+{
+  unsigned base;
+  unsigned index;
+  unsigned scale;
+}
 sib_byte;
 
+/* x86 arch names and features */
+typedef struct
+{
+  const char *name;	/* arch name */
+  unsigned int flags;	/* cpu feature flags */
+}
+arch_entry;
+
 /* The name of the global offset table generated by the compiler. Allow
    this to be overridden if need be. */
 #ifndef GLOBAL_OFFSET_TABLE_NAME
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 8a9c85a..84139db 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -24,6 +24,7 @@
 * i386-Float::                  Floating Point
 * i386-SIMD::                   Intel's MMX and AMD's 3DNow! SIMD Operations
 * i386-16bit::                  Writing 16-bit Code
+* i386-Arch::                   Specifying an x86 CPU architecture
 * i386-Bugs::                   AT&T Syntax bugs
 * i386-Notes::                  Notes
 @end menu
@@ -35,13 +36,23 @@
 @cindex i386 options (none)
 The 80386 has no machine dependent options.
 
+
 @node i386-Syntax
 @section AT&T Syntax versus Intel Syntax
 
+@cindex i386 intel_syntax pseudo op
+@cindex intel_syntax pseudo op, i386
+@cindex i386 att_syntax pseudo op
+@cindex att_syntax pseudo op, i386
 @cindex i386 syntax compatibility
 @cindex syntax compatibility, i386
-In order to maintain compatibility with the output of @code{@value{GCC}},
-@code{@value{AS}} supports AT&T System V/386 assembler syntax.  This is quite
+
+@code{@value{AS}} now supports assembly using Intel assembler syntax.
+@code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
+back to the usual AT&T mode for compatibility with the output of
+@code{@value{GCC}}.  Either of these directives may have an optional
+argument, @code{prefix}, or @code{noprefix} specifying whether registers
+require a @samp{%} prefix.  AT&T System V/386 assembler syntax is quite
 different from Intel syntax.  We mention these differences because
 almost all 80386 documents use Intel syntax.  Notable differences
 between the two syntaxes are:
@@ -506,6 +517,31 @@ non-commutative arithmetic floating point operations with two register
 operands where the source register is @samp{%st} and the destination
 register is @samp{%st(i)}.
 
+@node i386-Arch
+@section Specifying CPU Architecture
+
+@cindex arch directive, i386
+@cindex i386 arch directive
+
+@code{@value{AS}} may be told to assemble for a particular CPU
+architecture with the @code{.arch @var{cpu_type}} directive.  This
+directive enables a warning when gas detects an instruction that is not
+supported on the CPU specified.  The choices for @var{cpu_type} are:
+
+@multitable @columnfractions .20 .20 .20 .20
+@item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
+@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
+@item @samp{pentiumpro} @tab @samp{k6} @tab @samp{athlon}
+@end multitable
+
+Apart from the warning, there is only one other effect on
+@code{@value{AS}} operation;  If you specify a CPU other than
+@samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
+will automatically use a two byte opcode sequence.  The larger three
+byte opcode sequence is used on the 486 (and when no architecture is
+specified) because it executes faster on the 486.  Note that you can
+explicitly request the two byte opcode by writing @samp{sarl %eax}.
+
 @node i386-Notes
 @section Notes
 
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index eb5757c..a0eba42 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,13 @@
+2000-05-13  Alan Modra  <alan@linuxcare.com.au>,
+	    Alexander Sokolov <robocop@netlink.ru>
+
+	* i386.h (i386_optab): Add cpu_flags for all instructions.
+
+2000-05-13  Alan Modra  <alan@linuxcare.com.au>
+
+	From Gavin Romig-Koch <gavin@cygnus.com>
+	* i386.h (wld_Suf): Define.  Use on pushf, popf, pusha, popa.
+
 2000-05-04  Timothy Wall  <twall@cygnus.com>
 
 	* tic54x.h: New.
diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index d399f4e..4fcd2b7 100644
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -58,6 +58,7 @@ static const template i386_optab[] = {
 #define bw_Suf (No_lSuf|No_sSuf|No_dSuf|No_xSuf)
 #define bl_Suf (No_wSuf|No_sSuf|No_dSuf|No_xSuf)
 #define wl_Suf (No_bSuf|No_sSuf|No_dSuf|No_xSuf)
+#define wld_Suf (No_bSuf|No_sSuf|No_xSuf)
 #define sl_Suf (No_bSuf|No_wSuf|No_dSuf|No_xSuf)
 #define sld_Suf (No_bSuf|No_wSuf|No_xSuf)
 #define sldx_Suf (No_bSuf|No_wSuf)
@@ -81,973 +82,992 @@ static const template i386_optab[] = {
 
 /* Move instructions.  */
 #define MOV_AX_DISP32 0xa0
-{ "mov",   2,	0xa0, X, bwl_Suf|D|W,			{ Disp16|Disp32, Acc, 0 } },
-{ "mov",   2,	0x88, X, bwl_Suf|D|W|Modrm,		{ Reg, Reg|AnyMem, 0 } },
-{ "mov",   2,	0xb0, X, bwl_Suf|W|ShortForm,		{ Imm, Reg, 0 } },
-{ "mov",   2,	0xc6, X, bwl_Suf|W|Modrm,		{ Imm, Reg|AnyMem, 0 } },
-/* The next two instructions accept WordReg so that a segment register
+{ "mov",   2,	0xa0, X, 0,	 bwl_Suf|D|W,			{ Disp16|Disp32, Acc, 0 } },
+{ "mov",   2,	0x88, X, 0,	 bwl_Suf|D|W|Modrm,		{ Reg, Reg|AnyMem, 0 } },
+{ "mov",   2,	0xb0, X, 0,	 bwl_Suf|W|ShortForm,		{ Imm, Reg, 0 } },
+{ "mov",   2,	0xc6, X, 0,	 bwl_Suf|W|Modrm,		{ Imm, Reg|AnyMem, 0 } },
+/* The segment register moves accept WordReg so that a segment register
    can be copied to a 32 bit register, and vice versa, without using a
    size prefix.  When moving to a 32 bit register, the upper 16 bits
    are set to an implementation defined value (on the Pentium Pro,
    the implementation defined value is zero).  */
-{ "mov",   2,	0x8c, X, wl_Suf|Modrm,			{ SReg3|SReg2, WordReg|WordMem, 0 } },
-{ "mov",   2,	0x8e, X, wl_Suf|Modrm|IgnoreSize,	{ WordReg|WordMem, SReg3|SReg2, 0 } },
+{ "mov",   2,	0x8c, X, 0,	 wl_Suf|Modrm,			{ SReg2, WordReg|WordMem, 0 } },
+{ "mov",   2,	0x8c, X, Cpu386, wl_Suf|Modrm,			{ SReg3, WordReg|WordMem, 0 } },
+{ "mov",   2,	0x8e, X, 0,	 wl_Suf|Modrm|IgnoreSize,	{ WordReg|WordMem, SReg2, 0 } },
+{ "mov",   2,	0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize,	{ WordReg|WordMem, SReg3, 0 } },
 /* Move to/from control debug registers.  */
-{ "mov",   2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize,	{ Control, Reg32|InvMem, 0} },
-{ "mov",   2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize,	{ Debug, Reg32|InvMem, 0} },
-{ "mov",   2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize,	{ Test, Reg32|InvMem, 0} },
+{ "mov",   2, 0x0f20, X, Cpu386, l_Suf|D|Modrm|IgnoreSize,	{ Control, Reg32|InvMem, 0} },
+{ "mov",   2, 0x0f21, X, Cpu386, l_Suf|D|Modrm|IgnoreSize,	{ Debug, Reg32|InvMem, 0} },
+{ "mov",   2, 0x0f24, X, Cpu386, l_Suf|D|Modrm|IgnoreSize,	{ Test, Reg32|InvMem, 0} },
 
 /* Move with sign extend.  */
 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
    conflict with the "movs" string move instruction.  */
-{"movsbl", 2, 0x0fbe, X, NoSuf|Modrm,			{ Reg8|ByteMem, Reg32, 0} },
-{"movsbw", 2, 0x0fbe, X, NoSuf|Modrm,			{ Reg8|ByteMem, Reg16, 0} },
-{"movswl", 2, 0x0fbf, X, NoSuf|Modrm,			{ Reg16|ShortMem, Reg32, 0} },
+{"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm,			{ Reg8|ByteMem, Reg32, 0} },
+{"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm,			{ Reg8|ByteMem, Reg16, 0} },
+{"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm,			{ Reg16|ShortMem, Reg32, 0} },
 /* Intel Syntax */
-{"movsx",  2, 0x0fbf, X, w_Suf|Modrm|IgnoreSize,	{ Reg16|ShortMem, Reg32, 0} },
-{"movsx",  2, 0x0fbe, X, b_Suf|Modrm,			{ Reg8|ByteMem, WordReg, 0} },
+{"movsx",  2, 0x0fbf, X, Cpu386, w_Suf|Modrm|IgnoreSize,	{ Reg16|ShortMem, Reg32, 0} },
+{"movsx",  2, 0x0fbe, X, Cpu386, b_Suf|Modrm,			{ Reg8|ByteMem, WordReg, 0} },
 
 /* Move with zero extend.  */
-{"movzb",  2, 0x0fb6, X, wl_Suf|Modrm,			{ Reg8|ByteMem, WordReg, 0} },
-{"movzwl", 2, 0x0fb7, X, NoSuf|Modrm,			{ Reg16|ShortMem, Reg32, 0} },
+{"movzb",  2, 0x0fb6, X, Cpu386, wl_Suf|Modrm,			{ Reg8|ByteMem, WordReg, 0} },
+{"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm,			{ Reg16|ShortMem, Reg32, 0} },
 /* Intel Syntax */
-{"movzx",  2, 0x0fb7, X, w_Suf|Modrm|IgnoreSize,	{ Reg16|ShortMem, Reg32, 0} },
-{"movzx",  2, 0x0fb6, X, b_Suf|Modrm,			{ Reg8|ByteMem, WordReg, 0} },
+{"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize,	{ Reg16|ShortMem, Reg32, 0} },
+{"movzx",  2, 0x0fb6, X, Cpu386, b_Suf|Modrm,			{ Reg8|ByteMem, WordReg, 0} },
 
 /* Push instructions.  */
-{"push",   1,	0x50, X, wl_Suf|ShortForm|DefaultSize,	{ WordReg, 0, 0 } },
-{"push",   1,	0xff, 6, wl_Suf|Modrm|DefaultSize,	{ WordReg|WordMem, 0, 0 } },
-{"push",   1,	0x6a, X, wl_Suf|DefaultSize,		{ Imm8S, 0, 0} },
-{"push",   1,	0x68, X, wl_Suf|DefaultSize,		{ Imm16|Imm32, 0, 0} },
-{"push",   1,	0x06, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
-{"push",   1, 0x0fa0, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
-{"pusha",  0,	0x60, X, wl_Suf|DefaultSize,		{ 0, 0, 0 } },
+{"push",   1,	0x50, X, 0,	 wl_Suf|ShortForm|DefaultSize,	{ WordReg, 0, 0 } },
+{"push",   1,	0xff, 6, 0,	 wl_Suf|Modrm|DefaultSize,	{ WordReg|WordMem, 0, 0 } },
+{"push",   1,	0x6a, X, Cpu186, wl_Suf|DefaultSize,		{ Imm8S, 0, 0} },
+{"push",   1,	0x68, X, Cpu186, wl_Suf|DefaultSize,		{ Imm16|Imm32, 0, 0} },
+{"push",   1,	0x06, X, 0,	 wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
+{"push",   1, 0x0fa0, X, Cpu386, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
+{"pusha",  0,	0x60, X, Cpu186, wld_Suf|DefaultSize,		{ 0, 0, 0 } },
 
 /* Pop instructions.  */
-{"pop",	   1,	0x58, X, wl_Suf|ShortForm|DefaultSize,	{ WordReg, 0, 0 } },
-{"pop",	   1,	0x8f, 0, wl_Suf|Modrm|DefaultSize,	{ WordReg|WordMem, 0, 0 } },
+{"pop",	   1,	0x58, X, 0,	 wl_Suf|ShortForm|DefaultSize,	{ WordReg, 0, 0 } },
+{"pop",	   1,	0x8f, 0, 0,	 wl_Suf|Modrm|DefaultSize,	{ WordReg|WordMem, 0, 0 } },
 #define POP_SEG_SHORT 0x07
-{"pop",	   1,	0x07, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
-{"pop",	   1, 0x0fa1, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
-{"popa",   0,	0x61, X, wl_Suf|DefaultSize,		{ 0, 0, 0 } },
+{"pop",	   1,	0x07, X, 0,	 wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
+{"pop",	   1, 0x0fa1, X, Cpu386, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
+{"popa",   0,	0x61, X, Cpu186, wld_Suf|DefaultSize,		{ 0, 0, 0 } },
 
 /* Exchange instructions.
    xchg commutes:  we allow both operand orders.  */
-{"xchg",   2,	0x90, X, wl_Suf|ShortForm,	{ WordReg, Acc, 0 } },
-{"xchg",   2,	0x90, X, wl_Suf|ShortForm,	{ Acc, WordReg, 0 } },
-{"xchg",   2,	0x86, X, bwl_Suf|W|Modrm,	{ Reg, Reg|AnyMem, 0 } },
-{"xchg",   2,	0x86, X, bwl_Suf|W|Modrm,	{ Reg|AnyMem, Reg, 0 } },
+{"xchg",   2,	0x90, X, 0,	 wl_Suf|ShortForm,	{ WordReg, Acc, 0 } },
+{"xchg",   2,	0x90, X, 0,	 wl_Suf|ShortForm,	{ Acc, WordReg, 0 } },
+{"xchg",   2,	0x86, X, 0,	 bwl_Suf|W|Modrm,	{ Reg, Reg|AnyMem, 0 } },
+{"xchg",   2,	0x86, X, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, Reg, 0 } },
 
 /* In/out from ports.  */
-{"in",	   2,	0xe4, X, bwl_Suf|W,		{ Imm8, Acc, 0 } },
-{"in",	   2,	0xec, X, bwl_Suf|W,		{ InOutPortReg, Acc, 0 } },
-{"in",	   1,	0xe4, X, bwl_Suf|W,		{ Imm8, 0, 0 } },
-{"in",	   1,	0xec, X, bwl_Suf|W,		{ InOutPortReg, 0, 0 } },
-{"out",	   2,	0xe6, X, bwl_Suf|W,		{ Acc, Imm8, 0 } },
-{"out",	   2,	0xee, X, bwl_Suf|W,		{ Acc, InOutPortReg, 0 } },
-{"out",	   1,	0xe6, X, bwl_Suf|W,		{ Imm8, 0, 0 } },
-{"out",	   1,	0xee, X, bwl_Suf|W,		{ InOutPortReg, 0, 0 } },
+{"in",	   2,	0xe4, X, 0,	 bwl_Suf|W,		{ Imm8, Acc, 0 } },
+{"in",	   2,	0xec, X, 0,	 bwl_Suf|W,		{ InOutPortReg, Acc, 0 } },
+{"in",	   1,	0xe4, X, 0,	 bwl_Suf|W,		{ Imm8, 0, 0 } },
+{"in",	   1,	0xec, X, 0,	 bwl_Suf|W,		{ InOutPortReg, 0, 0 } },
+{"out",	   2,	0xe6, X, 0,	 bwl_Suf|W,		{ Acc, Imm8, 0 } },
+{"out",	   2,	0xee, X, 0,	 bwl_Suf|W,		{ Acc, InOutPortReg, 0 } },
+{"out",	   1,	0xe6, X, 0,	 bwl_Suf|W,		{ Imm8, 0, 0 } },
+{"out",	   1,	0xee, X, 0,	 bwl_Suf|W,		{ InOutPortReg, 0, 0 } },
 
 /* Load effective address.  */
-{"lea",	   2, 0x8d,   X, wl_Suf|Modrm,		{ WordMem, WordReg, 0 } },
+{"lea",	   2, 0x8d,   X, 0,	 wl_Suf|Modrm,		{ WordMem, WordReg, 0 } },
 
 /* Load segment registers from memory.  */
-{"lds",	   2,	0xc5, X, wl_Suf|Modrm,		{ WordMem, WordReg, 0} },
-{"les",	   2,	0xc4, X, wl_Suf|Modrm,		{ WordMem, WordReg, 0} },
-{"lfs",	   2, 0x0fb4, X, wl_Suf|Modrm,		{ WordMem, WordReg, 0} },
-{"lgs",	   2, 0x0fb5, X, wl_Suf|Modrm,		{ WordMem, WordReg, 0} },
-{"lss",	   2, 0x0fb2, X, wl_Suf|Modrm,		{ WordMem, WordReg, 0} },
+{"lds",	   2,	0xc5, X, 0,	 wl_Suf|Modrm,		{ WordMem, WordReg, 0} },
+{"les",	   2,	0xc4, X, 0,	 wl_Suf|Modrm,		{ WordMem, WordReg, 0} },
+{"lfs",	   2, 0x0fb4, X, Cpu386, wl_Suf|Modrm,		{ WordMem, WordReg, 0} },
+{"lgs",	   2, 0x0fb5, X, Cpu386, wl_Suf|Modrm,		{ WordMem, WordReg, 0} },
+{"lss",	   2, 0x0fb2, X, Cpu386, wl_Suf|Modrm,		{ WordMem, WordReg, 0} },
 
 /* Flags register instructions.  */
-{"clc",	   0,	0xf8, X, NoSuf,			{ 0, 0, 0} },
-{"cld",	   0,	0xfc, X, NoSuf,			{ 0, 0, 0} },
-{"cli",	   0,	0xfa, X, NoSuf,			{ 0, 0, 0} },
-{"clts",   0, 0x0f06, X, NoSuf,			{ 0, 0, 0} },
-{"cmc",	   0,	0xf5, X, NoSuf,			{ 0, 0, 0} },
-{"lahf",   0,	0x9f, X, NoSuf,			{ 0, 0, 0} },
-{"sahf",   0,	0x9e, X, NoSuf,			{ 0, 0, 0} },
-{"pushf",  0,	0x9c, X, wl_Suf|DefaultSize,	{ 0, 0, 0} },
-{"popf",   0,	0x9d, X, wl_Suf|DefaultSize,	{ 0, 0, 0} },
-{"stc",	   0,	0xf9, X, NoSuf,			{ 0, 0, 0} },
-{"std",	   0,	0xfd, X, NoSuf,			{ 0, 0, 0} },
-{"sti",	   0,	0xfb, X, NoSuf,			{ 0, 0, 0} },
+{"clc",	   0,	0xf8, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"cld",	   0,	0xfc, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"cli",	   0,	0xfa, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"clts",   0, 0x0f06, X, Cpu286, NoSuf,			{ 0, 0, 0} },
+{"cmc",	   0,	0xf5, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"lahf",   0,	0x9f, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"sahf",   0,	0x9e, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"pushf",  0,	0x9c, X, 0,	 wld_Suf|DefaultSize,	{ 0, 0, 0} },
+{"popf",   0,	0x9d, X, 0,	 wld_Suf|DefaultSize,	{ 0, 0, 0} },
+{"stc",	   0,	0xf9, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"std",	   0,	0xfd, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"sti",	   0,	0xfb, X, 0,	 NoSuf,			{ 0, 0, 0} },
 
 /* Arithmetic.  */
-{"add",	   2,	0x00, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
-{"add",	   2,	0x83, 0, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
-{"add",	   2,	0x04, X, bwl_Suf|W,		{ Imm, Acc, 0} },
-{"add",	   2,	0x80, 0, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
-
-{"inc",	   1,	0x40, X, wl_Suf|ShortForm,	{ WordReg, 0, 0} },
-{"inc",	   1,	0xfe, 0, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
-
-{"sub",	   2,	0x28, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
-{"sub",	   2,	0x83, 5, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
-{"sub",	   2,	0x2c, X, bwl_Suf|W,		{ Imm, Acc, 0} },
-{"sub",	   2,	0x80, 5, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
-
-{"dec",	   1,	0x48, X, wl_Suf|ShortForm,	{ WordReg, 0, 0} },
-{"dec",	   1,	0xfe, 1, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
-
-{"sbb",	   2,	0x18, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
-{"sbb",	   2,	0x83, 3, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
-{"sbb",	   2,	0x1c, X, bwl_Suf|W,		{ Imm, Acc, 0} },
-{"sbb",	   2,	0x80, 3, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
-
-{"cmp",	   2,	0x38, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
-{"cmp",	   2,	0x83, 7, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
-{"cmp",	   2,	0x3c, X, bwl_Suf|W,		{ Imm, Acc, 0} },
-{"cmp",	   2,	0x80, 7, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
-
-{"test",   2,	0x84, X, bwl_Suf|W|Modrm,	{ Reg|AnyMem, Reg, 0} },
-{"test",   2,	0x84, X, bwl_Suf|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
-{"test",   2,	0xa8, X, bwl_Suf|W,		{ Imm, Acc, 0} },
-{"test",   2,	0xf6, 0, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
-
-{"and",	   2,	0x20, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
-{"and",	   2,	0x83, 4, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
-{"and",	   2,	0x24, X, bwl_Suf|W,		{ Imm, Acc, 0} },
-{"and",	   2,	0x80, 4, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
-
-{"or",	   2,	0x08, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
-{"or",	   2,	0x83, 1, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
-{"or",	   2,	0x0c, X, bwl_Suf|W,		{ Imm, Acc, 0} },
-{"or",	   2,	0x80, 1, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
-
-{"xor",	   2,	0x30, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
-{"xor",	   2,	0x83, 6, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
-{"xor",	   2,	0x34, X, bwl_Suf|W,		{ Imm, Acc, 0} },
-{"xor",	   2,	0x80, 6, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
-
-/* iclr with 1 operand is really xor with 2 operands.  */
-{"clr",	   1,	0x30, X, bwl_Suf|W|Modrm|regKludge,	{ Reg, 0, 0 } },
-
-{"adc",	   2,	0x10, X, bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
-{"adc",	   2,	0x83, 2, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
-{"adc",	   2,	0x14, X, bwl_Suf|W,		{ Imm, Acc, 0} },
-{"adc",	   2,	0x80, 2, bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
-
-{"neg",	   1,	0xf6, 3, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
-{"not",	   1,	0xf6, 2, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
-
-{"aaa",	   0,	0x37, X, NoSuf,			{ 0, 0, 0} },
-{"aas",	   0,	0x3f, X, NoSuf,			{ 0, 0, 0} },
-{"daa",	   0,	0x27, X, NoSuf,			{ 0, 0, 0} },
-{"das",	   0,	0x2f, X, NoSuf,			{ 0, 0, 0} },
-{"aad",	   0, 0xd50a, X, NoSuf,			{ 0, 0, 0} },
-{"aad",	   1,   0xd5, X, NoSuf,			{ Imm8S, 0, 0} },
-{"aam",	   0, 0xd40a, X, NoSuf,			{ 0, 0, 0} },
-{"aam",	   1,   0xd4, X, NoSuf,			{ Imm8S, 0, 0} },
+{"add",	   2,	0x00, X, 0,	 bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"add",	   2,	0x83, 0, 0,	 wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"add",	   2,	0x04, X, 0,	 bwl_Suf|W,		{ Imm, Acc, 0} },
+{"add",	   2,	0x80, 0, 0,	 bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"inc",	   1,	0x40, X, 0,	 wl_Suf|ShortForm,	{ WordReg, 0, 0} },
+{"inc",	   1,	0xfe, 0, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"sub",	   2,	0x28, X, 0,	 bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"sub",	   2,	0x83, 5, 0,	 wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"sub",	   2,	0x2c, X, 0,	 bwl_Suf|W,		{ Imm, Acc, 0} },
+{"sub",	   2,	0x80, 5, 0,	 bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"dec",	   1,	0x48, X, 0,	 wl_Suf|ShortForm,	{ WordReg, 0, 0} },
+{"dec",	   1,	0xfe, 1, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"sbb",	   2,	0x18, X, 0,	 bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"sbb",	   2,	0x83, 3, 0,	 wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"sbb",	   2,	0x1c, X, 0,	 bwl_Suf|W,		{ Imm, Acc, 0} },
+{"sbb",	   2,	0x80, 3, 0,	 bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"cmp",	   2,	0x38, X, 0,	 bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"cmp",	   2,	0x83, 7, 0,	 wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"cmp",	   2,	0x3c, X, 0,	 bwl_Suf|W,		{ Imm, Acc, 0} },
+{"cmp",	   2,	0x80, 7, 0,	 bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"test",   2,	0x84, X, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, Reg, 0} },
+{"test",   2,	0x84, X, 0,	 bwl_Suf|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"test",   2,	0xa8, X, 0,	 bwl_Suf|W,		{ Imm, Acc, 0} },
+{"test",   2,	0xf6, 0, 0,	 bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"and",	   2,	0x20, X, 0,	 bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"and",	   2,	0x83, 4, 0,	 wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"and",	   2,	0x24, X, 0,	 bwl_Suf|W,		{ Imm, Acc, 0} },
+{"and",	   2,	0x80, 4, 0,	 bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"or",	   2,	0x08, X, 0,	 bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"or",	   2,	0x83, 1, 0,	 wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"or",	   2,	0x0c, X, 0,	 bwl_Suf|W,		{ Imm, Acc, 0} },
+{"or",	   2,	0x80, 1, 0,	 bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"xor",	   2,	0x30, X, 0,	 bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"xor",	   2,	0x83, 6, 0,	 wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"xor",	   2,	0x34, X, 0,	 bwl_Suf|W,		{ Imm, Acc, 0} },
+{"xor",	   2,	0x80, 6, 0,	 bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+/* clr with 1 operand is really xor with 2 operands.  */
+{"clr",	   1,	0x30, X, 0,	 bwl_Suf|W|Modrm|regKludge,	{ Reg, 0, 0 } },
+
+{"adc",	   2,	0x10, X, 0,	 bwl_Suf|D|W|Modrm,	{ Reg, Reg|AnyMem, 0} },
+{"adc",	   2,	0x83, 2, 0,	 wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, 0} },
+{"adc",	   2,	0x14, X, 0,	 bwl_Suf|W,		{ Imm, Acc, 0} },
+{"adc",	   2,	0x80, 2, 0,	 bwl_Suf|W|Modrm,	{ Imm, Reg|AnyMem, 0} },
+
+{"neg",	   1,	0xf6, 3, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+{"not",	   1,	0xf6, 2, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"aaa",	   0,	0x37, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"aas",	   0,	0x3f, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"daa",	   0,	0x27, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"das",	   0,	0x2f, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"aad",	   0, 0xd50a, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"aad",	   1,   0xd5, X, 0,	 NoSuf,			{ Imm8S, 0, 0} },
+{"aam",	   0, 0xd40a, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"aam",	   1,   0xd4, X, 0,	 NoSuf,			{ Imm8S, 0, 0} },
 
 /* Conversion insns.  */
 /* Intel naming */
-{"cbw",	   0,	0x98, X, NoSuf|Size16,		{ 0, 0, 0} },
-{"cwde",   0,	0x98, X, NoSuf|Size32,		{ 0, 0, 0} },
-{"cwd",	   0,	0x99, X, NoSuf|Size16,		{ 0, 0, 0} },
-{"cdq",	   0,	0x99, X, NoSuf|Size32,		{ 0, 0, 0} },
+{"cbw",	   0,	0x98, X, 0,	 NoSuf|Size16,		{ 0, 0, 0} },
+{"cwde",   0,	0x98, X, 0,	 NoSuf|Size32,		{ 0, 0, 0} },
+{"cwd",	   0,	0x99, X, 0,	 NoSuf|Size16,		{ 0, 0, 0} },
+{"cdq",	   0,	0x99, X, 0,	 NoSuf|Size32,		{ 0, 0, 0} },
 /* AT&T naming */
-{"cbtw",   0,	0x98, X, NoSuf|Size16,		{ 0, 0, 0} },
-{"cwtl",   0,	0x98, X, NoSuf|Size32,		{ 0, 0, 0} },
-{"cwtd",   0,	0x99, X, NoSuf|Size16,		{ 0, 0, 0} },
-{"cltd",   0,	0x99, X, NoSuf|Size32,		{ 0, 0, 0} },
+{"cbtw",   0,	0x98, X, 0,	 NoSuf|Size16,		{ 0, 0, 0} },
+{"cwtl",   0,	0x98, X, 0,	 NoSuf|Size32,		{ 0, 0, 0} },
+{"cwtd",   0,	0x99, X, 0,	 NoSuf|Size16,		{ 0, 0, 0} },
+{"cltd",   0,	0x99, X, 0,	 NoSuf|Size32,		{ 0, 0, 0} },
 
 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand!  They are
    expanding 64-bit multiplies, and *cannot* be selected to accomplish
    'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
    These multiplies can only be selected with single operand forms.  */
-{"mul",	   1,	0xf6, 4, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
-{"imul",   1,	0xf6, 5, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
-{"imul",   2, 0x0faf, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"imul",   3,	0x6b, X, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, WordReg} },
-{"imul",   3,	0x69, X, wl_Suf|Modrm,		{ Imm16|Imm32, WordReg|WordMem, WordReg} },
+{"mul",	   1,	0xf6, 4, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+{"imul",   1,	0xf6, 5, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+{"imul",   2, 0x0faf, X, Cpu386, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"imul",   3,	0x6b, X, Cpu186, wl_Suf|Modrm,		{ Imm8S, WordReg|WordMem, WordReg} },
+{"imul",   3,	0x69, X, Cpu186, wl_Suf|Modrm,		{ Imm16|Imm32, WordReg|WordMem, WordReg} },
 /* imul with 2 operands mimics imul with 3 by putting the register in
    both i.rm.reg & i.rm.regmem fields.  regKludge enables this
    transformation.  */
-{"imul",   2,	0x6b, X, wl_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
-{"imul",   2,	0x69, X, wl_Suf|Modrm|regKludge,{ Imm16|Imm32, WordReg, 0} },
-
-{"div",	   1,	0xf6, 6, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
-{"div",	   2,	0xf6, 6, bwl_Suf|W|Modrm,	{ Reg|AnyMem, Acc, 0} },
-{"idiv",   1,	0xf6, 7, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
-{"idiv",   2,	0xf6, 7, bwl_Suf|W|Modrm,	{ Reg|AnyMem, Acc, 0} },
-
-{"rol",	   2,	0xd0, 0, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
-{"rol",	   2,	0xc0, 0, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
-{"rol",	   2,	0xd2, 0, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
-{"rol",	   1,	0xd0, 0, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
-
-{"ror",	   2,	0xd0, 1, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
-{"ror",	   2,	0xc0, 1, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
-{"ror",	   2,	0xd2, 1, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
-{"ror",	   1,	0xd0, 1, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
-
-{"rcl",	   2,	0xd0, 2, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
-{"rcl",	   2,	0xc0, 2, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
-{"rcl",	   2,	0xd2, 2, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
-{"rcl",	   1,	0xd0, 2, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
-
-{"rcr",	   2,	0xd0, 3, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
-{"rcr",	   2,	0xc0, 3, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
-{"rcr",	   2,	0xd2, 3, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
-{"rcr",	   1,	0xd0, 3, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
-
-{"sal",	   2,	0xd0, 4, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
-{"sal",	   2,	0xc0, 4, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
-{"sal",	   2,	0xd2, 4, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
-{"sal",	   1,	0xd0, 4, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
-{"shl",	   2,	0xd0, 4, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
-{"shl",	   2,	0xc0, 4, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
-{"shl",	   2,	0xd2, 4, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
-{"shl",	   1,	0xd0, 4, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
-
-{"shld",   3, 0x0fa4, X, wl_Suf|Modrm,		{ Imm8, WordReg, WordReg|WordMem} },
-{"shld",   3, 0x0fa5, X, wl_Suf|Modrm,		{ ShiftCount, WordReg, WordReg|WordMem} },
-{"shld",   2, 0x0fa5, X, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
-
-{"shr",	   2,	0xd0, 5, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
-{"shr",	   2,	0xc0, 5, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
-{"shr",	   2,	0xd2, 5, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
-{"shr",	   1,	0xd0, 5, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
-
-{"shrd",   3, 0x0fac, X, wl_Suf|Modrm,		{ Imm8, WordReg, WordReg|WordMem} },
-{"shrd",   3, 0x0fad, X, wl_Suf|Modrm,		{ ShiftCount, WordReg, WordReg|WordMem} },
-{"shrd",   2, 0x0fad, X, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
-
-{"sar",	   2,	0xd0, 7, bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
-{"sar",	   2,	0xc0, 7, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
-{"sar",	   2,	0xd2, 7, bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
-{"sar",	   1,	0xd0, 7, bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+{"imul",   2,	0x6b, X, Cpu186, wl_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
+{"imul",   2,	0x69, X, Cpu186, wl_Suf|Modrm|regKludge,{ Imm16|Imm32, WordReg, 0} },
+
+{"div",	   1,	0xf6, 6, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+{"div",	   2,	0xf6, 6, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, Acc, 0} },
+{"idiv",   1,	0xf6, 7, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+{"idiv",   2,	0xf6, 7, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, Acc, 0} },
+
+{"rol",	   2,	0xd0, 0, 0,	 bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"rol",	   2,	0xc0, 0, Cpu186, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"rol",	   2,	0xd2, 0, 0,	 bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"rol",	   1,	0xd0, 0, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"ror",	   2,	0xd0, 1, 0,	 bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"ror",	   2,	0xc0, 1, Cpu186, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"ror",	   2,	0xd2, 1, 0,	 bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"ror",	   1,	0xd0, 1, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"rcl",	   2,	0xd0, 2, 0,	 bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"rcl",	   2,	0xc0, 2, Cpu186, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"rcl",	   2,	0xd2, 2, 0,	 bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"rcl",	   1,	0xd0, 2, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"rcr",	   2,	0xd0, 3, 0,	 bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"rcr",	   2,	0xc0, 3, Cpu186, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"rcr",	   2,	0xd2, 3, 0,	 bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"rcr",	   1,	0xd0, 3, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"sal",	   2,	0xd0, 4, 0,	 bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"sal",	   2,	0xc0, 4, Cpu186, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"sal",	   2,	0xd2, 4, 0,	 bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"sal",	   1,	0xd0, 4, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"shl",	   2,	0xd0, 4, 0,	 bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"shl",	   2,	0xc0, 4, Cpu186, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"shl",	   2,	0xd2, 4, 0,	 bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"shl",	   1,	0xd0, 4, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"shr",	   2,	0xd0, 5, 0,	 bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"shr",	   2,	0xc0, 5, Cpu186, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"shr",	   2,	0xd2, 5, 0,	 bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"shr",	   1,	0xd0, 5, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"sar",	   2,	0xd0, 7, 0,	 bwl_Suf|W|Modrm,	{ Imm1, Reg|AnyMem, 0} },
+{"sar",	   2,	0xc0, 7, Cpu186, bwl_Suf|W|Modrm,	{ Imm8, Reg|AnyMem, 0} },
+{"sar",	   2,	0xd2, 7, 0,	 bwl_Suf|W|Modrm,	{ ShiftCount, Reg|AnyMem, 0} },
+{"sar",	   1,	0xd0, 7, 0,	 bwl_Suf|W|Modrm,	{ Reg|AnyMem, 0, 0} },
+
+{"shld",   3, 0x0fa4, X, Cpu386, wl_Suf|Modrm,		{ Imm8, WordReg, WordReg|WordMem} },
+{"shld",   3, 0x0fa5, X, Cpu386, wl_Suf|Modrm,		{ ShiftCount, WordReg, WordReg|WordMem} },
+{"shld",   2, 0x0fa5, X, Cpu386, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
+
+{"shrd",   3, 0x0fac, X, Cpu386, wl_Suf|Modrm,		{ Imm8, WordReg, WordReg|WordMem} },
+{"shrd",   3, 0x0fad, X, Cpu386, wl_Suf|Modrm,		{ ShiftCount, WordReg, WordReg|WordMem} },
+{"shrd",   2, 0x0fad, X, Cpu386, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
 
 /* Control transfer instructions.  */
-{"call",   1,	0xe8, X, wl_Suf|JumpDword|DefaultSize,	{ Disp16|Disp32, 0, 0} },
-{"call",   1,	0xff, 2, wl_Suf|Modrm|DefaultSize,	{ WordReg|WordMem|JumpAbsolute, 0, 0} },
+{"call",   1,	0xe8, X, 0,	 wl_Suf|JumpDword|DefaultSize,	{ Disp16|Disp32, 0, 0} },
+{"call",   1,	0xff, 2, 0,	 wl_Suf|Modrm|DefaultSize,	{ WordReg|WordMem|JumpAbsolute, 0, 0} },
 /* Intel Syntax */
-{"call",   2,	0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
+{"call",   2,	0x9a, X, 0,	 wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
 /* Intel Syntax */
-{"call",   1,	0xff, 3, x_Suf|Modrm|DefaultSize,	{ WordMem, 0, 0} },
-{"lcall",  2,	0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
-{"lcall",  1,	0xff, 3, wl_Suf|Modrm|DefaultSize,	{ WordMem|JumpAbsolute, 0, 0} },
+{"call",   1,	0xff, 3, 0,	 x_Suf|Modrm|DefaultSize,	{ WordMem, 0, 0} },
+{"lcall",  2,	0x9a, X, 0,	 wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
+{"lcall",  1,	0xff, 3, 0,	 wl_Suf|Modrm|DefaultSize,	{ WordMem|JumpAbsolute, 0, 0} },
 
 #define JUMP_PC_RELATIVE 0xeb
-{"jmp",	   1,	0xeb, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jmp",	   1,	0xff, 4, wl_Suf|Modrm,		{ WordReg|WordMem|JumpAbsolute, 0, 0} },
+{"jmp",	   1,	0xeb, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jmp",	   1,	0xff, 4, 0,	 wl_Suf|Modrm,		{ WordReg|WordMem|JumpAbsolute, 0, 0} },
 /* Intel Syntax */
-{"jmp",    2,	0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
+{"jmp",    2,	0xea, X, 0,	 wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
 /* Intel Syntax */
-{"jmp",    1,	0xff, 5, x_Suf|Modrm,		{ WordMem, 0, 0} },
-{"ljmp",   2,	0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
-{"ljmp",   1,	0xff, 5, wl_Suf|Modrm,		{ WordMem|JumpAbsolute, 0, 0} },
+{"jmp",    1,	0xff, 5, 0,	 x_Suf|Modrm,		{ WordMem, 0, 0} },
+{"ljmp",   2,	0xea, X, 0,	 wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
+{"ljmp",   1,	0xff, 5, 0,	 wl_Suf|Modrm,		{ WordMem|JumpAbsolute, 0, 0} },
 
-{"ret",	   0,	0xc3, X, wl_Suf|DefaultSize,	{ 0, 0, 0} },
-{"ret",	   1,	0xc2, X, wl_Suf|DefaultSize,	{ Imm16, 0, 0} },
-{"lret",   0,	0xcb, X, wl_Suf|DefaultSize,	{ 0, 0, 0} },
-{"lret",   1,	0xca, X, wl_Suf|DefaultSize,	{ Imm16, 0, 0} },
-{"enter",  2,	0xc8, X, wl_Suf|DefaultSize,	{ Imm16, Imm8, 0} },
-{"leave",  0,	0xc9, X, wl_Suf|DefaultSize,	{ 0, 0, 0} },
+{"ret",	   0,	0xc3, X, 0,	 wl_Suf|DefaultSize,	{ 0, 0, 0} },
+{"ret",	   1,	0xc2, X, 0,	 wl_Suf|DefaultSize,	{ Imm16, 0, 0} },
+{"lret",   0,	0xcb, X, 0,	 wl_Suf|DefaultSize,	{ 0, 0, 0} },
+{"lret",   1,	0xca, X, 0,	 wl_Suf|DefaultSize,	{ Imm16, 0, 0} },
+{"enter",  2,	0xc8, X, Cpu186, wl_Suf|DefaultSize,	{ Imm16, Imm8, 0} },
+{"leave",  0,	0xc9, X, Cpu186, wl_Suf|DefaultSize,	{ 0, 0, 0} },
 
 /* Conditional jumps.  */
-{"jo",	   1,	0x70, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jno",	   1,	0x71, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jb",	   1,	0x72, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jc",	   1,	0x72, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jnae",   1,	0x72, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jnb",	   1,	0x73, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jnc",	   1,	0x73, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jae",	   1,	0x73, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"je",	   1,	0x74, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jz",	   1,	0x74, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jne",	   1,	0x75, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jnz",	   1,	0x75, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jbe",	   1,	0x76, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jna",	   1,	0x76, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jnbe",   1,	0x77, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"ja",	   1,	0x77, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"js",	   1,	0x78, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jns",	   1,	0x79, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jp",	   1,	0x7a, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jpe",	   1,	0x7a, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jnp",	   1,	0x7b, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jpo",	   1,	0x7b, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jl",	   1,	0x7c, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jnge",   1,	0x7c, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jnl",	   1,	0x7d, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jge",	   1,	0x7d, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jle",	   1,	0x7e, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jng",	   1,	0x7e, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jnle",   1,	0x7f, X, NoSuf|Jump,		{ Disp, 0, 0} },
-{"jg",	   1,	0x7f, X, NoSuf|Jump,		{ Disp, 0, 0} },
+{"jo",	   1,	0x70, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jno",	   1,	0x71, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jb",	   1,	0x72, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jc",	   1,	0x72, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnae",   1,	0x72, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnb",	   1,	0x73, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnc",	   1,	0x73, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jae",	   1,	0x73, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"je",	   1,	0x74, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jz",	   1,	0x74, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jne",	   1,	0x75, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnz",	   1,	0x75, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jbe",	   1,	0x76, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jna",	   1,	0x76, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnbe",   1,	0x77, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"ja",	   1,	0x77, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"js",	   1,	0x78, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jns",	   1,	0x79, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jp",	   1,	0x7a, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jpe",	   1,	0x7a, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnp",	   1,	0x7b, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jpo",	   1,	0x7b, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jl",	   1,	0x7c, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnge",   1,	0x7c, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnl",	   1,	0x7d, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jge",	   1,	0x7d, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jle",	   1,	0x7e, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jng",	   1,	0x7e, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jnle",   1,	0x7f, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
+{"jg",	   1,	0x7f, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
 
 /* jcxz vs. jecxz is chosen on the basis of the address size prefix.  */
-{"jcxz",   1,	0xe3, X, NoSuf|JumpByte|Size16, { Disp, 0, 0} },
-{"jecxz",  1,	0xe3, X, NoSuf|JumpByte|Size32, { Disp, 0, 0} },
+{"jcxz",   1,	0xe3, X, 0,	 NoSuf|JumpByte|Size16, { Disp, 0, 0} },
+{"jecxz",  1,	0xe3, X, 0,	 NoSuf|JumpByte|Size32, { Disp, 0, 0} },
 
 /* The loop instructions also use the address size prefix to select
    %cx rather than %ecx for the loop count, so the `w' form of these
    instructions emit an address size prefix rather than a data size
    prefix.  */
-{"loop",   1,	0xe2, X, wl_Suf|JumpByte,	{ Disp, 0, 0} },
-{"loopz",  1,	0xe1, X, wl_Suf|JumpByte,	{ Disp, 0, 0} },
-{"loope",  1,	0xe1, X, wl_Suf|JumpByte,	{ Disp, 0, 0} },
-{"loopnz", 1,	0xe0, X, wl_Suf|JumpByte,	{ Disp, 0, 0} },
-{"loopne", 1,	0xe0, X, wl_Suf|JumpByte,	{ Disp, 0, 0} },
+{"loop",   1,	0xe2, X, 0,	 wl_Suf|JumpByte,	{ Disp, 0, 0} },
+{"loopz",  1,	0xe1, X, 0,	 wl_Suf|JumpByte,	{ Disp, 0, 0} },
+{"loope",  1,	0xe1, X, 0,	 wl_Suf|JumpByte,	{ Disp, 0, 0} },
+{"loopnz", 1,	0xe0, X, 0,	 wl_Suf|JumpByte,	{ Disp, 0, 0} },
+{"loopne", 1,	0xe0, X, 0,	 wl_Suf|JumpByte,	{ Disp, 0, 0} },
 
 /* Set byte on flag instructions.  */
-{"seto",   1, 0x0f90, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setno",  1, 0x0f91, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setb",   1, 0x0f92, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setc",   1, 0x0f92, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setnae", 1, 0x0f92, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setnb",  1, 0x0f93, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setnc",  1, 0x0f93, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setae",  1, 0x0f93, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"sete",   1, 0x0f94, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setz",   1, 0x0f94, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setne",  1, 0x0f95, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setnz",  1, 0x0f95, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setbe",  1, 0x0f96, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setna",  1, 0x0f96, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setnbe", 1, 0x0f97, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"seta",   1, 0x0f97, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"sets",   1, 0x0f98, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setns",  1, 0x0f99, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setp",   1, 0x0f9a, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setpe",  1, 0x0f9a, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setnp",  1, 0x0f9b, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setpo",  1, 0x0f9b, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setl",   1, 0x0f9c, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setnge", 1, 0x0f9c, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setnl",  1, 0x0f9d, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setge",  1, 0x0f9d, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setle",  1, 0x0f9e, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setng",  1, 0x0f9e, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setnle", 1, 0x0f9f, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
-{"setg",   1, 0x0f9f, 0, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"seto",   1, 0x0f90, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setno",  1, 0x0f91, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setb",   1, 0x0f92, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setc",   1, 0x0f92, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnb",  1, 0x0f93, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnc",  1, 0x0f93, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setae",  1, 0x0f93, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"sete",   1, 0x0f94, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setz",   1, 0x0f94, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setne",  1, 0x0f95, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnz",  1, 0x0f95, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setbe",  1, 0x0f96, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setna",  1, 0x0f96, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"seta",   1, 0x0f97, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"sets",   1, 0x0f98, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setns",  1, 0x0f99, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setp",   1, 0x0f9a, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setpe",  1, 0x0f9a, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnp",  1, 0x0f9b, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setpo",  1, 0x0f9b, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setl",   1, 0x0f9c, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnl",  1, 0x0f9d, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setge",  1, 0x0f9d, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setle",  1, 0x0f9e, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setng",  1, 0x0f9e, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
+{"setg",   1, 0x0f9f, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
 
 /* String manipulation.  */
-{"cmps",   0,	0xa6, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
-{"cmps",   2,	0xa6, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, AnyMem, 0} },
-{"scmp",   0,	0xa6, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
-{"scmp",   2,	0xa6, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, AnyMem, 0} },
-{"ins",	   0,	0x6c, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
-{"ins",	   2,	0x6c, X, bwld_Suf|W|IsString,	{ InOutPortReg, AnyMem|EsSeg, 0} },
-{"outs",   0,	0x6e, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
-{"outs",   2,	0x6e, X, bwld_Suf|W|IsString,	{ AnyMem, InOutPortReg, 0} },
-{"lods",   0,	0xac, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
-{"lods",   1,	0xac, X, bwld_Suf|W|IsString,	{ AnyMem, 0, 0} },
-{"lods",   2,	0xac, X, bwld_Suf|W|IsString,	{ AnyMem, Acc, 0} },
-{"slod",   0,	0xac, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
-{"slod",   1,	0xac, X, bwld_Suf|W|IsString,	{ AnyMem, 0, 0} },
-{"slod",   2,	0xac, X, bwld_Suf|W|IsString,	{ AnyMem, Acc, 0} },
-{"movs",   0,	0xa4, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
-{"movs",   2,	0xa4, X, bwld_Suf|W|IsString,	{ AnyMem, AnyMem|EsSeg, 0} },
-{"smov",   0,	0xa4, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
-{"smov",   2,	0xa4, X, bwld_Suf|W|IsString,	{ AnyMem, AnyMem|EsSeg, 0} },
-{"scas",   0,	0xae, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
-{"scas",   1,	0xae, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, 0, 0} },
-{"scas",   2,	0xae, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, Acc, 0} },
-{"ssca",   0,	0xae, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
-{"ssca",   1,	0xae, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, 0, 0} },
-{"ssca",   2,	0xae, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, Acc, 0} },
-{"stos",   0,	0xaa, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
-{"stos",   1,	0xaa, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, 0, 0} },
-{"stos",   2,	0xaa, X, bwld_Suf|W|IsString,	{ Acc, AnyMem|EsSeg, 0} },
-{"ssto",   0,	0xaa, X, bwld_Suf|W|IsString,	{ 0, 0, 0} },
-{"ssto",   1,	0xaa, X, bwld_Suf|W|IsString,	{ AnyMem|EsSeg, 0, 0} },
-{"ssto",   2,	0xaa, X, bwld_Suf|W|IsString,	{ Acc, AnyMem|EsSeg, 0} },
-{"xlat",   0,	0xd7, X, b_Suf|IsString,	{ 0, 0, 0} },
-{"xlat",   1,	0xd7, X, b_Suf|IsString,	{ AnyMem, 0, 0} },
+{"cmps",   0,	0xa6, X, 0,	 bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"cmps",   2,	0xa6, X, 0,	 bwld_Suf|W|IsString,	{ AnyMem|EsSeg, AnyMem, 0} },
+{"scmp",   0,	0xa6, X, 0,	 bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"scmp",   2,	0xa6, X, 0,	 bwld_Suf|W|IsString,	{ AnyMem|EsSeg, AnyMem, 0} },
+{"ins",	   0,	0x6c, X, Cpu186, bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"ins",	   2,	0x6c, X, Cpu186, bwld_Suf|W|IsString,	{ InOutPortReg, AnyMem|EsSeg, 0} },
+{"outs",   0,	0x6e, X, Cpu186, bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"outs",   2,	0x6e, X, Cpu186, bwld_Suf|W|IsString,	{ AnyMem, InOutPortReg, 0} },
+{"lods",   0,	0xac, X, 0,	 bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"lods",   1,	0xac, X, 0,	 bwld_Suf|W|IsString,	{ AnyMem, 0, 0} },
+{"lods",   2,	0xac, X, 0,	 bwld_Suf|W|IsString,	{ AnyMem, Acc, 0} },
+{"slod",   0,	0xac, X, 0,	 bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"slod",   1,	0xac, X, 0,	 bwld_Suf|W|IsString,	{ AnyMem, 0, 0} },
+{"slod",   2,	0xac, X, 0,	 bwld_Suf|W|IsString,	{ AnyMem, Acc, 0} },
+{"movs",   0,	0xa4, X, 0,	 bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"movs",   2,	0xa4, X, 0,	 bwld_Suf|W|IsString,	{ AnyMem, AnyMem|EsSeg, 0} },
+{"smov",   0,	0xa4, X, 0,	 bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"smov",   2,	0xa4, X, 0,	 bwld_Suf|W|IsString,	{ AnyMem, AnyMem|EsSeg, 0} },
+{"scas",   0,	0xae, X, 0,	 bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"scas",   1,	0xae, X, 0,	 bwld_Suf|W|IsString,	{ AnyMem|EsSeg, 0, 0} },
+{"scas",   2,	0xae, X, 0,	 bwld_Suf|W|IsString,	{ AnyMem|EsSeg, Acc, 0} },
+{"ssca",   0,	0xae, X, 0,	 bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"ssca",   1,	0xae, X, 0,	 bwld_Suf|W|IsString,	{ AnyMem|EsSeg, 0, 0} },
+{"ssca",   2,	0xae, X, 0,	 bwld_Suf|W|IsString,	{ AnyMem|EsSeg, Acc, 0} },
+{"stos",   0,	0xaa, X, 0,	 bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"stos",   1,	0xaa, X, 0,	 bwld_Suf|W|IsString,	{ AnyMem|EsSeg, 0, 0} },
+{"stos",   2,	0xaa, X, 0,	 bwld_Suf|W|IsString,	{ Acc, AnyMem|EsSeg, 0} },
+{"ssto",   0,	0xaa, X, 0,	 bwld_Suf|W|IsString,	{ 0, 0, 0} },
+{"ssto",   1,	0xaa, X, 0,	 bwld_Suf|W|IsString,	{ AnyMem|EsSeg, 0, 0} },
+{"ssto",   2,	0xaa, X, 0,	 bwld_Suf|W|IsString,	{ Acc, AnyMem|EsSeg, 0} },
+{"xlat",   0,	0xd7, X, 0,	 b_Suf|IsString,	{ 0, 0, 0} },
+{"xlat",   1,	0xd7, X, 0,	 b_Suf|IsString,	{ AnyMem, 0, 0} },
 
 /* Bit manipulation.  */
-{"bsf",	   2, 0x0fbc, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"bsr",	   2, 0x0fbd, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"bt",	   2, 0x0fa3, X, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
-{"bt",	   2, 0x0fba, 4, wl_Suf|Modrm,		{ Imm8, WordReg|WordMem, 0} },
-{"btc",	   2, 0x0fbb, X, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
-{"btc",	   2, 0x0fba, 7, wl_Suf|Modrm,		{ Imm8, WordReg|WordMem, 0} },
-{"btr",	   2, 0x0fb3, X, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
-{"btr",	   2, 0x0fba, 6, wl_Suf|Modrm,		{ Imm8, WordReg|WordMem, 0} },
-{"bts",	   2, 0x0fab, X, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
-{"bts",	   2, 0x0fba, 5, wl_Suf|Modrm,		{ Imm8, WordReg|WordMem, 0} },
+{"bsf",	   2, 0x0fbc, X, Cpu386, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"bsr",	   2, 0x0fbd, X, Cpu386, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"bt",	   2, 0x0fa3, X, Cpu386, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
+{"bt",	   2, 0x0fba, 4, Cpu386, wl_Suf|Modrm,		{ Imm8, WordReg|WordMem, 0} },
+{"btc",	   2, 0x0fbb, X, Cpu386, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
+{"btc",	   2, 0x0fba, 7, Cpu386, wl_Suf|Modrm,		{ Imm8, WordReg|WordMem, 0} },
+{"btr",	   2, 0x0fb3, X, Cpu386, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
+{"btr",	   2, 0x0fba, 6, Cpu386, wl_Suf|Modrm,		{ Imm8, WordReg|WordMem, 0} },
+{"bts",	   2, 0x0fab, X, Cpu386, wl_Suf|Modrm,		{ WordReg, WordReg|WordMem, 0} },
+{"bts",	   2, 0x0fba, 5, Cpu386, wl_Suf|Modrm,		{ Imm8, WordReg|WordMem, 0} },
 
 /* Interrupts & op. sys insns.  */
 /* See gas/config/tc-i386.c for conversion of 'int $3' into the special
    int 3 insn.  */
 #define INT_OPCODE 0xcd
 #define INT3_OPCODE 0xcc
-{"int",	   1,	0xcd, X, NoSuf,			{ Imm8, 0, 0} },
-{"int3",   0,	0xcc, X, NoSuf,			{ 0, 0, 0} },
-{"into",   0,	0xce, X, NoSuf,			{ 0, 0, 0} },
-{"iret",   0,	0xcf, X, wl_Suf,		{ 0, 0, 0} },
+{"int",	   1,	0xcd, X, 0,	 NoSuf,			{ Imm8, 0, 0} },
+{"int3",   0,	0xcc, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"into",   0,	0xce, X, 0,	 NoSuf,			{ 0, 0, 0} },
+{"iret",   0,	0xcf, X, 0,	 wl_Suf,		{ 0, 0, 0} },
 /* i386sl, i486sl, later 486, and Pentium.  */
-{"rsm",	   0, 0x0faa, X, NoSuf,			{ 0, 0, 0} },
+{"rsm",	   0, 0x0faa, X, Cpu386, NoSuf,			{ 0, 0, 0} },
 
-{"bound",  2,	0x62, X, wl_Suf|Modrm,		{ WordReg, WordMem, 0} },
+{"bound",  2,	0x62, X, Cpu186, wl_Suf|Modrm,		{ WordReg, WordMem, 0} },
 
-{"hlt",	   0,	0xf4, X, NoSuf,			{ 0, 0, 0} },
+{"hlt",	   0,	0xf4, X, 0,	 NoSuf,			{ 0, 0, 0} },
 /* nop is actually 'xchgl %eax, %eax'.  */
-{"nop",	   0,	0x90, X, NoSuf,			{ 0, 0, 0} },
+{"nop",	   0,	0x90, X, 0,	 NoSuf,			{ 0, 0, 0} },
 
 /* Protection control.  */
-{"arpl",   2,	0x63, X, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
-{"lar",	   2, 0x0f02, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"lgdt",   1, 0x0f01, 2, wl_Suf|Modrm,		{ WordMem, 0, 0} },
-{"lidt",   1, 0x0f01, 3, wl_Suf|Modrm,		{ WordMem, 0, 0} },
-{"lldt",   1, 0x0f00, 2, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
-{"lmsw",   1, 0x0f01, 6, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
-{"lsl",	   2, 0x0f03, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"ltr",	   1, 0x0f00, 3, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
-
-{"sgdt",   1, 0x0f01, 0, wl_Suf|Modrm,		{ WordMem, 0, 0} },
-{"sidt",   1, 0x0f01, 1, wl_Suf|Modrm,		{ WordMem, 0, 0} },
-{"sldt",   1, 0x0f00, 0, wl_Suf|Modrm,		{ WordReg|WordMem, 0, 0} },
-{"smsw",   1, 0x0f01, 4, wl_Suf|Modrm,		{ WordReg|WordMem, 0, 0} },
-{"str",	   1, 0x0f00, 1, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
-
-{"verr",   1, 0x0f00, 4, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
-{"verw",   1, 0x0f00, 5, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
+{"arpl",   2,	0x63, X, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
+{"lar",	   2, 0x0f02, X, Cpu286, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"lgdt",   1, 0x0f01, 2, Cpu286, wl_Suf|Modrm,		{ WordMem, 0, 0} },
+{"lidt",   1, 0x0f01, 3, Cpu286, wl_Suf|Modrm,		{ WordMem, 0, 0} },
+{"lldt",   1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
+{"lmsw",   1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
+{"lsl",	   2, 0x0f03, X, Cpu286, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"ltr",	   1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
+
+{"sgdt",   1, 0x0f01, 0, Cpu286, wl_Suf|Modrm,		{ WordMem, 0, 0} },
+{"sidt",   1, 0x0f01, 1, Cpu286, wl_Suf|Modrm,		{ WordMem, 0, 0} },
+{"sldt",   1, 0x0f00, 0, Cpu286, wl_Suf|Modrm,		{ WordReg|WordMem, 0, 0} },
+{"smsw",   1, 0x0f01, 4, Cpu286, wl_Suf|Modrm,		{ WordReg|WordMem, 0, 0} },
+{"str",	   1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
+
+{"verr",   1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
+{"verw",   1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
 
 /* Floating point instructions.  */
 
 /* load */
-{"fld",	   1, 0xd9c0, X, FP|ShortForm,		{ FloatReg, 0, 0} }, /* register */
-{"fld",	   1,	0xd9, 0, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} }, /* %st0 <-- mem float/double */
-{"fld",	   1, 0xd9c0, X, l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
+{"fld",	   1, 0xd9c0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fld",	   1,	0xd9, 0, 0,	 sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fld",	   1, 0xd9c0, X, 0,	 l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
 /* Intel Syntax */
-{"fld",    1,	0xdb, 5, x_FP|Modrm,		{ LLongMem, 0, 0} }, /* %st0 <-- mem efloat */
-{"fild",   1,	0xdf, 0, sl_Suf|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} }, /* %st0 <-- mem word(16)/dword(32) */
+{"fld",    1,	0xdb, 5, 0,	 x_FP|Modrm,		{ LLongMem, 0, 0} },
+{"fild",   1,	0xdf, 0, 0,	 sl_Suf|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
 /* Intel Syntax */
-{"fildd",  1,	0xdf, 5, FP|Modrm,		{ LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */
-{"fildq",  1,	0xdf, 5, FP|Modrm,		{ LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */
-{"fildll", 1,	0xdf, 5, FP|Modrm,		{ LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */
-{"fldt",   1,	0xdb, 5, FP|Modrm,		{ LLongMem, 0, 0} }, /* %st0 <-- mem efloat */
-{"fbld",   1,	0xdf, 4, FP|Modrm,		{ LLongMem, 0, 0} }, /* %st0 <-- mem bcd */
+{"fildd",  1,	0xdf, 5, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
+{"fildq",  1,	0xdf, 5, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
+{"fildll", 1,	0xdf, 5, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
+{"fldt",   1,	0xdb, 5, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
+{"fbld",   1,	0xdf, 4, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
 
 /* store (no pop) */
-{"fst",	   1, 0xddd0, X, FP|ShortForm,		{ FloatReg, 0, 0} }, /* register */
-{"fst",	   1,	0xd9, 2, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} }, /* %st0 --> mem float/double */
-{"fst",	   1, 0xddd0, X, l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
-{"fist",   1,	0xdf, 2, sld_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */
+{"fst",	   1, 0xddd0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fst",	   1,	0xd9, 2, 0,	 sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fst",	   1, 0xddd0, X, 0,	 l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
+{"fist",   1,	0xdf, 2, 0,	 sld_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
 
 /* store (with pop) */
-{"fstp",   1, 0xddd8, X, FP|ShortForm,		{ FloatReg, 0, 0} }, /* register */
-{"fstp",   1,	0xd9, 3, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} }, /* %st0 --> mem float/double */
-{"fstp",   1, 0xddd8, X, l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
+{"fstp",   1, 0xddd8, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fstp",   1,	0xd9, 3, 0,	 sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fstp",   1, 0xddd8, X, 0,	 l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
 /* Intel Syntax */
-{"fstp",   1,	0xdb, 7, x_FP|Modrm,		{ LLongMem, 0, 0} }, /* %st0 --> mem efloat */
-{"fistp",  1,	0xdf, 3, sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */
+{"fstp",   1,	0xdb, 7, 0,	 x_FP|Modrm,		{ LLongMem, 0, 0} },
+{"fistp",  1,	0xdf, 3, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
 /* Intel Syntax */
-{"fistpd", 1,	0xdf, 7, FP|Modrm,		{ LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */
-{"fistpq", 1,	0xdf, 7, FP|Modrm,		{ LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */
-{"fistpll",1,	0xdf, 7, FP|Modrm,		{ LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */
-{"fstpt",  1,	0xdb, 7, FP|Modrm,		{ LLongMem, 0, 0} }, /* %st0 --> mem efloat */
-{"fbstp",  1,	0xdf, 6, FP|Modrm,		{ LLongMem, 0, 0} }, /* %st0 --> mem bcd */
+{"fistpd", 1,	0xdf, 7, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
+{"fistpq", 1,	0xdf, 7, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
+{"fistpll",1,	0xdf, 7, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
+{"fstpt",  1,	0xdb, 7, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
+{"fbstp",  1,	0xdf, 6, 0,	 FP|Modrm,		{ LLongMem, 0, 0} },
 
 /* exchange %st<n> with %st0 */
-{"fxch",   1, 0xd9c8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fxch",   0, 0xd9c9, X, FP,			{ 0, 0, 0} },	     /* alias for fxch %st(1) */
+{"fxch",   1, 0xd9c8, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+/* alias for fxch %st(1) */
+{"fxch",   0, 0xd9c9, X, 0,	 FP,			{ 0, 0, 0} },
 
 /* comparison (without pop) */
-{"fcom",   1, 0xd8d0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fcom",   0, 0xd8d1, X, FP,			{ 0, 0, 0} },	     /* alias for fcom %st(1) */
-{"fcom",   1,	0xd8, 2, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} }, /* compare %st0, mem float/double */
-{"fcom",   1, 0xd8d0, X, l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
-{"ficom",  1,	0xde, 2, sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} }, /* compare %st0, mem word/dword */
+{"fcom",   1, 0xd8d0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+/* alias for fcom %st(1) */
+{"fcom",   0, 0xd8d1, X, 0,	 FP,			{ 0, 0, 0} },
+{"fcom",   1,	0xd8, 2, 0,	 sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fcom",   1, 0xd8d0, X, 0,	 l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
+{"ficom",  1,	0xde, 2, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
 
 /* comparison (with pop) */
-{"fcomp",  1, 0xd8d8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fcomp",  0, 0xd8d9, X, FP,			{ 0, 0, 0} },	     /* alias for fcomp %st(1) */
-{"fcomp",  1,	0xd8, 3, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} }, /* compare %st0, mem float/double */
-{"fcomp",  1, 0xd8d8, X, l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
-{"ficomp", 1,	0xde, 3, sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} }, /* compare %st0, mem word/dword */
-{"fcompp", 0, 0xded9, X, FP,			{ 0, 0, 0} },	     /* compare %st0, %st1 & pop 2 */
+{"fcomp",  1, 0xd8d8, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+/* alias for fcomp %st(1) */
+{"fcomp",  0, 0xd8d9, X, 0,	 FP,			{ 0, 0, 0} },
+{"fcomp",  1,	0xd8, 3, 0,	 sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fcomp",  1, 0xd8d8, X, 0,	 l_FP|ShortForm|Ugh,	{ FloatReg, 0, 0} },
+{"ficomp", 1,	0xde, 3, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fcompp", 0, 0xded9, X, 0,	 FP,			{ 0, 0, 0} },
 
 /* unordered comparison (with pop) */
-{"fucom",  1, 0xdde0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fucom",  0, 0xdde1, X, FP,			{ 0, 0, 0} },	     /* alias for fucom %st(1) */
-{"fucomp", 1, 0xdde8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fucomp", 0, 0xdde9, X, FP,			{ 0, 0, 0} },	     /* alias for fucomp %st(1) */
-{"fucompp",0, 0xdae9, X, FP,			{ 0, 0, 0} },	     /* ucompare %st0, %st1 & pop twice */
+{"fucom",  1, 0xdde0, X, Cpu286, FP|ShortForm,		{ FloatReg, 0, 0} },
+/* alias for fucom %st(1) */
+{"fucom",  0, 0xdde1, X, Cpu286, FP,			{ 0, 0, 0} },
+{"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm,		{ FloatReg, 0, 0} },
+/* alias for fucomp %st(1) */
+{"fucomp", 0, 0xdde9, X, Cpu286, FP,			{ 0, 0, 0} },
+{"fucompp",0, 0xdae9, X, Cpu286, FP,			{ 0, 0, 0} },
 
-{"ftst",   0, 0xd9e4, X, FP,			{ 0, 0, 0} },	     /* test %st0 */
-{"fxam",   0, 0xd9e5, X, FP,			{ 0, 0, 0} },	     /* examine %st0 */
+{"ftst",   0, 0xd9e4, X, 0,	 FP,			{ 0, 0, 0} },
+{"fxam",   0, 0xd9e5, X, 0,	 FP,			{ 0, 0, 0} },
 
 /* load constants into %st0 */
-{"fld1",   0, 0xd9e8, X, FP,			{ 0, 0, 0} },	     /* %st0 <-- 1.0 */
-{"fldl2t", 0, 0xd9e9, X, FP,			{ 0, 0, 0} },	     /* %st0 <-- log2(10) */
-{"fldl2e", 0, 0xd9ea, X, FP,			{ 0, 0, 0} },	     /* %st0 <-- log2(e) */
-{"fldpi",  0, 0xd9eb, X, FP,			{ 0, 0, 0} },	     /* %st0 <-- pi */
-{"fldlg2", 0, 0xd9ec, X, FP,			{ 0, 0, 0} },	     /* %st0 <-- log10(2) */
-{"fldln2", 0, 0xd9ed, X, FP,			{ 0, 0, 0} },	     /* %st0 <-- ln(2) */
-{"fldz",   0, 0xd9ee, X, FP,			{ 0, 0, 0} },	     /* %st0 <-- 0.0 */
+{"fld1",   0, 0xd9e8, X, 0,	 FP,			{ 0, 0, 0} },
+{"fldl2t", 0, 0xd9e9, X, 0,	 FP,			{ 0, 0, 0} },
+{"fldl2e", 0, 0xd9ea, X, 0,	 FP,			{ 0, 0, 0} },
+{"fldpi",  0, 0xd9eb, X, 0,	 FP,			{ 0, 0, 0} },
+{"fldlg2", 0, 0xd9ec, X, 0,	 FP,			{ 0, 0, 0} },
+{"fldln2", 0, 0xd9ed, X, 0,	 FP,			{ 0, 0, 0} },
+{"fldz",   0, 0xd9ee, X, 0,	 FP,			{ 0, 0, 0} },
 
 /* arithmetic */
 
 /* add */
-{"fadd",   2, 0xd8c0, X, FP|ShortForm|FloatD,	{ FloatReg, FloatAcc, 0} },
-{"fadd",   1, 0xd8c0, X, FP|ShortForm,		{ FloatReg, 0, 0} }, /* alias for fadd %st(i), %st */
+{"fadd",   2, 0xd8c0, X, 0,	 FP|ShortForm|FloatD,	{ FloatReg, FloatAcc, 0} },
+/* alias for fadd %st(i), %st */
+{"fadd",   1, 0xd8c0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
 #if SYSV386_COMPAT
-{"fadd",   0, 0xdec1, X, FP|Ugh,		{ 0, 0, 0} },	     /* alias for faddp */
+/* alias for faddp */
+{"fadd",   0, 0xdec1, X, 0,	 FP|Ugh,		{ 0, 0, 0} },
 #endif
-{"fadd",   1,	0xd8, 0, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fiadd",  1,	0xde, 0, sld_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fadd",   1,	0xd8, 0, 0,	 sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fiadd",  1,	0xde, 0, 0,	 sld_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
 
-{"faddp",  2, 0xdec0, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
-{"faddp",  1, 0xdec0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"faddp",  0, 0xdec1, X, FP,			{ 0, 0, 0} },	     /* alias for faddp %st, %st(1) */
-{"faddp",  2, 0xdec0, X, FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
+{"faddp",  2, 0xdec0, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"faddp",  1, 0xdec0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+/* alias for faddp %st, %st(1) */
+{"faddp",  0, 0xdec1, X, 0,	 FP,			{ 0, 0, 0} },
+{"faddp",  2, 0xdec0, X, 0,	 FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
 
 /* subtract */
-{"fsub",   2, 0xd8e0, X, FP|ShortForm|FloatDR,	{ FloatReg, FloatAcc, 0} },
-{"fsub",   1, 0xd8e0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fsub",   2, 0xd8e0, X, 0,	 FP|ShortForm|FloatDR,	{ FloatReg, FloatAcc, 0} },
+{"fsub",   1, 0xd8e0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
 #if SYSV386_COMPAT
-{"fsub",   0, 0xdee1, X, FP|Ugh,		{ 0, 0, 0} },	     /* alias for fsubp */
+/* alias for fsubp */
+{"fsub",   0, 0xdee1, X, 0,	 FP|Ugh,		{ 0, 0, 0} },
 #endif
-{"fsub",   1,	0xd8, 4, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fisub",  1,	0xde, 4, sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fsub",   1,	0xd8, 4, 0,	 sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fisub",  1,	0xde, 4, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
 
 #if SYSV386_COMPAT
-{"fsubp",  2, 0xdee0, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
-{"fsubp",  1, 0xdee0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fsubp",  0, 0xdee1, X, FP,			{ 0, 0, 0} },
+{"fsubp",  2, 0xdee0, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fsubp",  1, 0xdee0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fsubp",  0, 0xdee1, X, 0,	 FP,			{ 0, 0, 0} },
 #if OLDGCC_COMPAT
-{"fsubp",  2, 0xdee0, X, FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
+{"fsubp",  2, 0xdee0, X, 0,	 FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
 #endif
 #else
-{"fsubp",  2, 0xdee8, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
-{"fsubp",  1, 0xdee8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fsubp",  0, 0xdee9, X, FP,			{ 0, 0, 0} },
+{"fsubp",  2, 0xdee8, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fsubp",  1, 0xdee8, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fsubp",  0, 0xdee9, X, 0,	 FP,			{ 0, 0, 0} },
 #endif
 
 /* subtract reverse */
-{"fsubr",  2, 0xd8e8, X, FP|ShortForm|FloatDR,	{ FloatReg, FloatAcc, 0} },
-{"fsubr",  1, 0xd8e8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fsubr",  2, 0xd8e8, X, 0,	 FP|ShortForm|FloatDR,	{ FloatReg, FloatAcc, 0} },
+{"fsubr",  1, 0xd8e8, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
 #if SYSV386_COMPAT
-{"fsubr",  0, 0xdee9, X, FP|Ugh,		{ 0, 0, 0} },	     /* alias for fsubrp */
+/* alias for fsubrp */
+{"fsubr",  0, 0xdee9, X, 0,	 FP|Ugh,		{ 0, 0, 0} },
 #endif
-{"fsubr",  1,	0xd8, 5, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fisubr", 1,	0xde, 5, sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fsubr",  1,	0xd8, 5, 0,	 sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fisubr", 1,	0xde, 5, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
 
 #if SYSV386_COMPAT
-{"fsubrp", 2, 0xdee8, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
-{"fsubrp", 1, 0xdee8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fsubrp", 0, 0xdee9, X, FP,			{ 0, 0, 0} },
+{"fsubrp", 2, 0xdee8, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fsubrp", 1, 0xdee8, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fsubrp", 0, 0xdee9, X, 0,	 FP,			{ 0, 0, 0} },
 #if OLDGCC_COMPAT
-{"fsubrp", 2, 0xdee8, X, FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
+{"fsubrp", 2, 0xdee8, X, 0,	 FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
 #endif
 #else
-{"fsubrp", 2, 0xdee0, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
-{"fsubrp", 1, 0xdee0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fsubrp", 0, 0xdee1, X, FP,			{ 0, 0, 0} },
+{"fsubrp", 2, 0xdee0, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fsubrp", 1, 0xdee0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fsubrp", 0, 0xdee1, X, 0,	 FP,			{ 0, 0, 0} },
 #endif
 
 /* multiply */
-{"fmul",   2, 0xd8c8, X, FP|ShortForm|FloatD,	{ FloatReg, FloatAcc, 0} },
-{"fmul",   1, 0xd8c8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fmul",   2, 0xd8c8, X, 0,	 FP|ShortForm|FloatD,	{ FloatReg, FloatAcc, 0} },
+{"fmul",   1, 0xd8c8, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
 #if SYSV386_COMPAT
-{"fmul",   0, 0xdec9, X, FP|Ugh,		{ 0, 0, 0} },	     /* alias for fmulp */
+/* alias for fmulp */
+{"fmul",   0, 0xdec9, X, 0,	 FP|Ugh,		{ 0, 0, 0} },
 #endif
-{"fmul",   1,	0xd8, 1, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fimul",  1,	0xde, 1, sld_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fmul",   1,	0xd8, 1, 0,	 sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fimul",  1,	0xde, 1, 0,	 sld_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
 
-{"fmulp",  2, 0xdec8, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
-{"fmulp",  1, 0xdec8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fmulp",  0, 0xdec9, X, FP,			{ 0, 0, 0} },
-{"fmulp",  2, 0xdec8, X, FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
+{"fmulp",  2, 0xdec8, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fmulp",  1, 0xdec8, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fmulp",  0, 0xdec9, X, 0,	 FP,			{ 0, 0, 0} },
+{"fmulp",  2, 0xdec8, X, 0,	 FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
 
 /* divide */
-{"fdiv",   2, 0xd8f0, X, FP|ShortForm|FloatDR,	{ FloatReg, FloatAcc, 0} },
-{"fdiv",   1, 0xd8f0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fdiv",   2, 0xd8f0, X, 0,	 FP|ShortForm|FloatDR,	{ FloatReg, FloatAcc, 0} },
+{"fdiv",   1, 0xd8f0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
 #if SYSV386_COMPAT
-{"fdiv",   0, 0xdef1, X, FP|Ugh,		{ 0, 0, 0} },	     /* alias for fdivp */
+/* alias for fdivp */
+{"fdiv",   0, 0xdef1, X, 0,	 FP|Ugh,		{ 0, 0, 0} },
 #endif
-{"fdiv",   1,	0xd8, 6, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fidiv",  1,	0xde, 6, sld_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fdiv",   1,	0xd8, 6, 0,	 sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fidiv",  1,	0xde, 6, 0,	 sld_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
 
 #if SYSV386_COMPAT
-{"fdivp",  2, 0xdef0, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
-{"fdivp",  1, 0xdef0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fdivp",  0, 0xdef1, X, FP,			{ 0, 0, 0} },
+{"fdivp",  2, 0xdef0, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fdivp",  1, 0xdef0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fdivp",  0, 0xdef1, X, 0,	 FP,			{ 0, 0, 0} },
 #if OLDGCC_COMPAT
-{"fdivp",  2, 0xdef0, X, FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
+{"fdivp",  2, 0xdef0, X, 0,	 FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
 #endif
 #else
-{"fdivp",  2, 0xdef8, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
-{"fdivp",  1, 0xdef8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fdivp",  0, 0xdef9, X, FP,			{ 0, 0, 0} },
+{"fdivp",  2, 0xdef8, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fdivp",  1, 0xdef8, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fdivp",  0, 0xdef9, X, 0,	 FP,			{ 0, 0, 0} },
 #endif
 
 /* divide reverse */
-{"fdivr",  2, 0xd8f8, X, FP|ShortForm|FloatDR,	{ FloatReg, FloatAcc, 0} },
-{"fdivr",  1, 0xd8f8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fdivr",  2, 0xd8f8, X, 0,	 FP|ShortForm|FloatDR,	{ FloatReg, FloatAcc, 0} },
+{"fdivr",  1, 0xd8f8, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
 #if SYSV386_COMPAT
-{"fdivr",  0, 0xdef9, X, FP|Ugh,		{ 0, 0, 0} },	     /* alias for fdivrp */
+/* alias for fdivrp */
+{"fdivr",  0, 0xdef9, X, 0,	 FP|Ugh,		{ 0, 0, 0} },
 #endif
-{"fdivr",  1,	0xd8, 7, sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
-{"fidivr", 1,	0xde, 7, sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
+{"fdivr",  1,	0xd8, 7, 0,	 sld_FP|FloatMF|Modrm,	{ LongMem|LLongMem, 0, 0} },
+{"fidivr", 1,	0xde, 7, 0,	 sl_FP|FloatMF|Modrm,	{ ShortMem|LongMem, 0, 0} },
 
 #if SYSV386_COMPAT
-{"fdivrp", 2, 0xdef8, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
-{"fdivrp", 1, 0xdef8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fdivrp", 0, 0xdef9, X, FP,			{ 0, 0, 0} },
+{"fdivrp", 2, 0xdef8, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fdivrp", 1, 0xdef8, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fdivrp", 0, 0xdef9, X, 0,	 FP,			{ 0, 0, 0} },
 #if OLDGCC_COMPAT
-{"fdivrp", 2, 0xdef8, X, FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
+{"fdivrp", 2, 0xdef8, X, 0,	 FP|ShortForm|Ugh,	{ FloatReg, FloatAcc, 0} },
 #endif
 #else
-{"fdivrp", 2, 0xdef0, X, FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
-{"fdivrp", 1, 0xdef0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fdivrp", 0, 0xdef1, X, FP,			{ 0, 0, 0} },
+{"fdivrp", 2, 0xdef0, X, 0,	 FP|ShortForm,		{ FloatAcc, FloatReg, 0} },
+{"fdivrp", 1, 0xdef0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fdivrp", 0, 0xdef1, X, 0,	 FP,			{ 0, 0, 0} },
 #endif
 
-{"f2xm1",  0, 0xd9f0, X, FP,			{ 0, 0, 0} },
-{"fyl2x",  0, 0xd9f1, X, FP,			{ 0, 0, 0} },
-{"fptan",  0, 0xd9f2, X, FP,			{ 0, 0, 0} },
-{"fpatan", 0, 0xd9f3, X, FP,			{ 0, 0, 0} },
-{"fxtract",0, 0xd9f4, X, FP,			{ 0, 0, 0} },
-{"fprem1", 0, 0xd9f5, X, FP,			{ 0, 0, 0} },
-{"fdecstp",0, 0xd9f6, X, FP,			{ 0, 0, 0} },
-{"fincstp",0, 0xd9f7, X, FP,			{ 0, 0, 0} },
-{"fprem",  0, 0xd9f8, X, FP,			{ 0, 0, 0} },
-{"fyl2xp1",0, 0xd9f9, X, FP,			{ 0, 0, 0} },
-{"fsqrt",  0, 0xd9fa, X, FP,			{ 0, 0, 0} },
-{"fsincos",0, 0xd9fb, X, FP,			{ 0, 0, 0} },
-{"frndint",0, 0xd9fc, X, FP,			{ 0, 0, 0} },
-{"fscale", 0, 0xd9fd, X, FP,			{ 0, 0, 0} },
-{"fsin",   0, 0xd9fe, X, FP,			{ 0, 0, 0} },
-{"fcos",   0, 0xd9ff, X, FP,			{ 0, 0, 0} },
-{"fchs",   0, 0xd9e0, X, FP,			{ 0, 0, 0} },
-{"fabs",   0, 0xd9e1, X, FP,			{ 0, 0, 0} },
+{"f2xm1",  0, 0xd9f0, X, 0,	 FP,			{ 0, 0, 0} },
+{"fyl2x",  0, 0xd9f1, X, 0,	 FP,			{ 0, 0, 0} },
+{"fptan",  0, 0xd9f2, X, 0,	 FP,			{ 0, 0, 0} },
+{"fpatan", 0, 0xd9f3, X, 0,	 FP,			{ 0, 0, 0} },
+{"fxtract",0, 0xd9f4, X, 0,	 FP,			{ 0, 0, 0} },
+{"fprem1", 0, 0xd9f5, X, Cpu286, FP,			{ 0, 0, 0} },
+{"fdecstp",0, 0xd9f6, X, 0,	 FP,			{ 0, 0, 0} },
+{"fincstp",0, 0xd9f7, X, 0,	 FP,			{ 0, 0, 0} },
+{"fprem",  0, 0xd9f8, X, 0,	 FP,			{ 0, 0, 0} },
+{"fyl2xp1",0, 0xd9f9, X, 0,	 FP,			{ 0, 0, 0} },
+{"fsqrt",  0, 0xd9fa, X, 0,	 FP,			{ 0, 0, 0} },
+{"fsincos",0, 0xd9fb, X, Cpu286, FP,			{ 0, 0, 0} },
+{"frndint",0, 0xd9fc, X, 0,	 FP,			{ 0, 0, 0} },
+{"fscale", 0, 0xd9fd, X, 0,	 FP,			{ 0, 0, 0} },
+{"fsin",   0, 0xd9fe, X, Cpu286, FP,			{ 0, 0, 0} },
+{"fcos",   0, 0xd9ff, X, Cpu286, FP,			{ 0, 0, 0} },
+{"fchs",   0, 0xd9e0, X, 0,	 FP,			{ 0, 0, 0} },
+{"fabs",   0, 0xd9e1, X, 0,	 FP,			{ 0, 0, 0} },
 
 /* processor control */
-{"fninit", 0, 0xdbe3, X, FP,			{ 0, 0, 0} },
-{"finit",  0, 0xdbe3, X, FP|FWait,		{ 0, 0, 0} },
-{"fldcw",  1,	0xd9, 5, FP|Modrm,		{ ShortMem, 0, 0} },
-{"fnstcw", 1,	0xd9, 7, FP|Modrm,		{ ShortMem, 0, 0} },
-{"fstcw",  1,	0xd9, 7, FP|FWait|Modrm,	{ ShortMem, 0, 0} },
-{"fnstsw", 1, 0xdfe0, X, FP,			{ Acc, 0, 0} },
-{"fnstsw", 1,	0xdd, 7, FP|Modrm,		{ ShortMem, 0, 0} },
-{"fnstsw", 0, 0xdfe0, X, FP,			{ 0, 0, 0} },
-{"fstsw",  1, 0xdfe0, X, FP|FWait,		{ Acc, 0, 0} },
-{"fstsw",  1,	0xdd, 7, FP|FWait|Modrm,	{ ShortMem, 0, 0} },
-{"fstsw",  0, 0xdfe0, X, FP|FWait,		{ 0, 0, 0} },
-{"fnclex", 0, 0xdbe2, X, FP,			{ 0, 0, 0} },
-{"fclex",  0, 0xdbe2, X, FP|FWait,		{ 0, 0, 0} },
+{"fninit", 0, 0xdbe3, X, 0,	 FP,			{ 0, 0, 0} },
+{"finit",  0, 0xdbe3, X, 0,	 FP|FWait,		{ 0, 0, 0} },
+{"fldcw",  1,	0xd9, 5, 0,	 FP|Modrm,		{ ShortMem, 0, 0} },
+{"fnstcw", 1,	0xd9, 7, 0,	 FP|Modrm,		{ ShortMem, 0, 0} },
+{"fstcw",  1,	0xd9, 7, 0,	 FP|FWait|Modrm,	{ ShortMem, 0, 0} },
+{"fnstsw", 1, 0xdfe0, X, 0,	 FP,			{ Acc, 0, 0} },
+{"fnstsw", 1,	0xdd, 7, 0,	 FP|Modrm,		{ ShortMem, 0, 0} },
+{"fnstsw", 0, 0xdfe0, X, 0,	 FP,			{ 0, 0, 0} },
+{"fstsw",  1, 0xdfe0, X, 0,	 FP|FWait,		{ Acc, 0, 0} },
+{"fstsw",  1,	0xdd, 7, 0,	 FP|FWait|Modrm,	{ ShortMem, 0, 0} },
+{"fstsw",  0, 0xdfe0, X, 0,	 FP|FWait,		{ 0, 0, 0} },
+{"fnclex", 0, 0xdbe2, X, 0,	 FP,			{ 0, 0, 0} },
+{"fclex",  0, 0xdbe2, X, 0,	 FP|FWait,		{ 0, 0, 0} },
 /* Short forms of fldenv, fstenv use data size prefix.  */
-{"fnstenv",1,	0xd9, 6, sl_Suf|Modrm,		{ LLongMem, 0, 0} },
-{"fstenv", 1,	0xd9, 6, sl_Suf|FWait|Modrm,	{ LLongMem, 0, 0} },
-{"fldenv", 1,	0xd9, 4, sl_Suf|Modrm,		{ LLongMem, 0, 0} },
-{"fnsave", 1,	0xdd, 6, sl_Suf|Modrm,		{ LLongMem, 0, 0} },
-{"fsave",  1,	0xdd, 6, sl_Suf|FWait|Modrm,	{ LLongMem, 0, 0} },
-{"frstor", 1,	0xdd, 4, sl_Suf|Modrm,		{ LLongMem, 0, 0} },
-
-{"ffree",  1, 0xddc0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fnstenv",1,	0xd9, 6, 0,	 sl_Suf|Modrm,		{ LLongMem, 0, 0} },
+{"fstenv", 1,	0xd9, 6, 0,	 sl_Suf|FWait|Modrm,	{ LLongMem, 0, 0} },
+{"fldenv", 1,	0xd9, 4, 0,	 sl_Suf|Modrm,		{ LLongMem, 0, 0} },
+{"fnsave", 1,	0xdd, 6, 0,	 sl_Suf|Modrm,		{ LLongMem, 0, 0} },
+{"fsave",  1,	0xdd, 6, 0,	 sl_Suf|FWait|Modrm,	{ LLongMem, 0, 0} },
+{"frstor", 1,	0xdd, 4, 0,	 sl_Suf|Modrm,		{ LLongMem, 0, 0} },
+
+{"ffree",  1, 0xddc0, X, 0,	 FP|ShortForm,		{ FloatReg, 0, 0} },
 /* P6:free st(i), pop st */
-{"ffreep", 1, 0xdfc0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fnop",   0, 0xd9d0, X, FP,			{ 0, 0, 0} },
+{"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fnop",   0, 0xd9d0, X, 0,	 FP,			{ 0, 0, 0} },
 #define FWAIT_OPCODE 0x9b
-{"fwait",  0,	0x9b, X, FP,			{ 0, 0, 0} },
+{"fwait",  0,	0x9b, X, 0,	 FP,			{ 0, 0, 0} },
 
 /* Opcode prefixes; we allow them as separate insns too.  */
 
 #define ADDR_PREFIX_OPCODE 0x67
-{"addr16", 0,	0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize,	{ 0, 0, 0} },
-{"addr32", 0,	0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize,	{ 0, 0, 0} },
-{"aword",  0,	0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize,	{ 0, 0, 0} },
-{"adword", 0,	0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize,	{ 0, 0, 0} },
+{"addr16", 0,	0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize,	{ 0, 0, 0} },
+{"addr32", 0,	0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize,	{ 0, 0, 0} },
+{"aword",  0,	0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize,	{ 0, 0, 0} },
+{"adword", 0,	0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize,	{ 0, 0, 0} },
 #define DATA_PREFIX_OPCODE 0x66
-{"data16", 0,	0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize,	{ 0, 0, 0} },
-{"data32", 0,	0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize,	{ 0, 0, 0} },
-{"word",   0,	0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize,	{ 0, 0, 0} },
-{"dword",  0,	0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize,	{ 0, 0, 0} },
+{"data16", 0,	0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize,	{ 0, 0, 0} },
+{"data32", 0,	0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize,	{ 0, 0, 0} },
+{"word",   0,	0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize,	{ 0, 0, 0} },
+{"dword",  0,	0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize,	{ 0, 0, 0} },
 #define LOCK_PREFIX_OPCODE 0xf0
-{"lock",   0,	0xf0, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
-{"wait",   0,   0x9b, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"lock",   0,	0xf0, X, 0,	 NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"wait",   0,   0x9b, X, 0,	 NoSuf|IsPrefix,	{ 0, 0, 0} },
 #define CS_PREFIX_OPCODE 0x2e
-{"cs",	   0,	0x2e, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"cs",	   0,	0x2e, X, 0,	 NoSuf|IsPrefix,	{ 0, 0, 0} },
 #define DS_PREFIX_OPCODE 0x3e
-{"ds",	   0,	0x3e, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"ds",	   0,	0x3e, X, 0,	 NoSuf|IsPrefix,	{ 0, 0, 0} },
 #define ES_PREFIX_OPCODE 0x26
-{"es",	   0,	0x26, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"es",	   0,	0x26, X, 0,	 NoSuf|IsPrefix,	{ 0, 0, 0} },
 #define FS_PREFIX_OPCODE 0x64
-{"fs",	   0,	0x64, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"fs",	   0,	0x64, X, Cpu386, NoSuf|IsPrefix,	{ 0, 0, 0} },
 #define GS_PREFIX_OPCODE 0x65
-{"gs",	   0,	0x65, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"gs",	   0,	0x65, X, Cpu386, NoSuf|IsPrefix,	{ 0, 0, 0} },
 #define SS_PREFIX_OPCODE 0x36
-{"ss",	   0,	0x36, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"ss",	   0,	0x36, X, 0,	 NoSuf|IsPrefix,	{ 0, 0, 0} },
 #define REPNE_PREFIX_OPCODE 0xf2
 #define REPE_PREFIX_OPCODE  0xf3
-{"rep",	   0,	0xf3, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
-{"repe",   0,	0xf3, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
-{"repz",   0,	0xf3, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
-{"repne",  0,	0xf2, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
-{"repnz",  0,	0xf2, X, NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"rep",	   0,	0xf3, X, 0,	 NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"repe",   0,	0xf3, X, 0,	 NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"repz",   0,	0xf3, X, 0,	 NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"repne",  0,	0xf2, X, 0,	 NoSuf|IsPrefix,	{ 0, 0, 0} },
+{"repnz",  0,	0xf2, X, 0,	 NoSuf|IsPrefix,	{ 0, 0, 0} },
 
 /* 486 extensions.  */
 
-{"bswap",   1, 0x0fc8, X, l_Suf|ShortForm,	{ Reg32, 0, 0 } },
-{"xadd",    2, 0x0fc0, X, bwl_Suf|W|Modrm,	{ Reg, Reg|AnyMem, 0 } },
-{"cmpxchg", 2, 0x0fb0, X, bwl_Suf|W|Modrm,	{ Reg, Reg|AnyMem, 0 } },
-{"invd",    0, 0x0f08, X, NoSuf,		{ 0, 0, 0} },
-{"wbinvd",  0, 0x0f09, X, NoSuf,		{ 0, 0, 0} },
-{"invlpg",  1, 0x0f01, 7, NoSuf|Modrm,		{ AnyMem, 0, 0} },
+{"bswap",   1, 0x0fc8, X, Cpu486, l_Suf|ShortForm,	{ Reg32, 0, 0 } },
+{"xadd",    2, 0x0fc0, X, Cpu486, bwl_Suf|W|Modrm,	{ Reg, Reg|AnyMem, 0 } },
+{"cmpxchg", 2, 0x0fb0, X, Cpu486, bwl_Suf|W|Modrm,	{ Reg, Reg|AnyMem, 0 } },
+{"invd",    0, 0x0f08, X, Cpu486, NoSuf,		{ 0, 0, 0} },
+{"wbinvd",  0, 0x0f09, X, Cpu486, NoSuf,		{ 0, 0, 0} },
+{"invlpg",  1, 0x0f01, 7, Cpu486, NoSuf|Modrm,		{ AnyMem, 0, 0} },
 
 /* 586 and late 486 extensions.  */
-{"cpuid",   0, 0x0fa2, X, NoSuf,		{ 0, 0, 0} },
+{"cpuid",   0, 0x0fa2, X, Cpu486, NoSuf,		{ 0, 0, 0} },
 
 /* Pentium extensions.  */
-{"wrmsr",   0, 0x0f30, X, NoSuf,		{ 0, 0, 0} },
-{"rdtsc",   0, 0x0f31, X, NoSuf,		{ 0, 0, 0} },
-{"rdmsr",   0, 0x0f32, X, NoSuf,		{ 0, 0, 0} },
-{"cmpxchg8b",1,0x0fc7, 1, NoSuf|Modrm,		{ LLongMem, 0, 0} },
-{"sysenter",0, 0x0f34, X, NoSuf,		{ 0, 0, 0} },
-{"sysexit", 0, 0x0f35, X, NoSuf,		{ 0, 0, 0} },
-{"fxsave",  1, 0x0fae, 0, FP|Modrm,		{ LLongMem, 0, 0} },
-{"fxrstor", 1, 0x0fae, 1, FP|Modrm,		{ LLongMem, 0, 0} },
+{"wrmsr",   0, 0x0f30, X, Cpu586, NoSuf,		{ 0, 0, 0} },
+{"rdtsc",   0, 0x0f31, X, Cpu586, NoSuf,		{ 0, 0, 0} },
+{"rdmsr",   0, 0x0f32, X, Cpu586, NoSuf,		{ 0, 0, 0} },
+{"cmpxchg8b",1,0x0fc7, 1, Cpu586, NoSuf|Modrm,		{ LLongMem, 0, 0} },
+{"sysenter",0, 0x0f34, X, Cpu586, NoSuf,		{ 0, 0, 0} },
+{"sysexit", 0, 0x0f35, X, Cpu586, NoSuf,		{ 0, 0, 0} },
+{"fxsave",  1, 0x0fae, 0, Cpu586, FP|Modrm,		{ LLongMem, 0, 0} },
+{"fxrstor", 1, 0x0fae, 1, Cpu586, FP|Modrm,		{ LLongMem, 0, 0} },
 
 /* Pentium Pro extensions.  */
-{"rdpmc",   0, 0x0f33, X, NoSuf,		{ 0, 0, 0} },
-
-{"ud2",	    0, 0x0f0b, X, NoSuf,		{ 0, 0, 0} }, /* official undefined instr. */
-{"ud2a",    0, 0x0f0b, X, NoSuf,		{ 0, 0, 0} }, /* alias for ud2 */
-{"ud2b",    0, 0x0fb9, X, NoSuf,		{ 0, 0, 0} }, /* 2nd. official undefined instr. */
-
-{"cmovo",   2, 0x0f40, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovno",  2, 0x0f41, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovb",   2, 0x0f42, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovc",   2, 0x0f42, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovnae", 2, 0x0f42, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovae",  2, 0x0f43, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovnc",  2, 0x0f43, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovnb",  2, 0x0f43, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmove",   2, 0x0f44, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovz",   2, 0x0f44, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovne",  2, 0x0f45, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovnz",  2, 0x0f45, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovbe",  2, 0x0f46, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovna",  2, 0x0f46, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmova",   2, 0x0f47, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovnbe", 2, 0x0f47, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovs",   2, 0x0f48, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovns",  2, 0x0f49, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovp",   2, 0x0f4a, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovnp",  2, 0x0f4b, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovl",   2, 0x0f4c, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovnge", 2, 0x0f4c, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovge",  2, 0x0f4d, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovnl",  2, 0x0f4d, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovle",  2, 0x0f4e, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovng",  2, 0x0f4e, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovg",   2, 0x0f4f, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-{"cmovnle", 2, 0x0f4f, X, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
-
-{"fcmovb",  2, 0xdac0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fcmovnae",2, 0xdac0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fcmove",  2, 0xdac8, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fcmovbe", 2, 0xdad0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fcmovna", 2, 0xdad0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fcmovu",  2, 0xdad8, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fcmovae", 2, 0xdbc0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fcmovnb", 2, 0xdbc0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fcmovne", 2, 0xdbc8, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fcmova",  2, 0xdbd0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fcmovnbe",2, 0xdbd0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fcmovnu", 2, 0xdbd8, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-
-{"fcomi",   2, 0xdbf0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fcomi",   0, 0xdbf1, X, FP|ShortForm,		{ 0, 0, 0} },
-{"fcomi",   1, 0xdbf0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fucomi",  2, 0xdbe8, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fucomi",  0, 0xdbe9, X, FP|ShortForm,		{ 0, 0, 0} },
-{"fucomi",  1, 0xdbe8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fcomip",  2, 0xdff0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fcompi",  2, 0xdff0, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fcompi",  0, 0xdff1, X, FP|ShortForm,		{ 0, 0, 0} },
-{"fcompi",  1, 0xdff0, X, FP|ShortForm,		{ FloatReg, 0, 0} },
-{"fucomip", 2, 0xdfe8, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fucompi", 2, 0xdfe8, X, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
-{"fucompi", 0, 0xdfe9, X, FP|ShortForm,		{ 0, 0, 0} },
-{"fucompi", 1, 0xdfe8, X, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"rdpmc",   0, 0x0f33, X, Cpu686, NoSuf,		{ 0, 0, 0} },
+/* official undefined instr. */
+{"ud2",	    0, 0x0f0b, X, Cpu686, NoSuf,		{ 0, 0, 0} },
+/* alias for ud2 */
+{"ud2a",    0, 0x0f0b, X, Cpu686, NoSuf,		{ 0, 0, 0} },
+/* 2nd. official undefined instr. */
+{"ud2b",    0, 0x0fb9, X, Cpu686, NoSuf,		{ 0, 0, 0} },
+
+{"cmovo",   2, 0x0f40, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovno",  2, 0x0f41, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovb",   2, 0x0f42, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovc",   2, 0x0f42, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnae", 2, 0x0f42, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovae",  2, 0x0f43, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnc",  2, 0x0f43, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnb",  2, 0x0f43, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmove",   2, 0x0f44, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovz",   2, 0x0f44, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovne",  2, 0x0f45, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnz",  2, 0x0f45, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovbe",  2, 0x0f46, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovna",  2, 0x0f46, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmova",   2, 0x0f47, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnbe", 2, 0x0f47, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovs",   2, 0x0f48, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovns",  2, 0x0f49, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovp",   2, 0x0f4a, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnp",  2, 0x0f4b, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovl",   2, 0x0f4c, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnge", 2, 0x0f4c, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovge",  2, 0x0f4d, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnl",  2, 0x0f4d, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovle",  2, 0x0f4e, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovng",  2, 0x0f4e, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovg",   2, 0x0f4f, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+{"cmovnle", 2, 0x0f4f, X, Cpu686, wl_Suf|Modrm,		{ WordReg|WordMem, WordReg, 0} },
+
+{"fcmovb",  2, 0xdac0, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmove",  2, 0xdac8, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovu",  2, 0xdad8, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmova",  2, 0xdbd0, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+
+{"fcomi",   2, 0xdbf0, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcomi",   0, 0xdbf1, X, Cpu686, FP|ShortForm,		{ 0, 0, 0} },
+{"fcomi",   1, 0xdbf0, X, Cpu686, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fucomi",  2, 0xdbe8, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fucomi",  0, 0xdbe9, X, Cpu686, FP|ShortForm,		{ 0, 0, 0} },
+{"fucomi",  1, 0xdbe8, X, Cpu686, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fcomip",  2, 0xdff0, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcompi",  2, 0xdff0, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fcompi",  0, 0xdff1, X, Cpu686, FP|ShortForm,		{ 0, 0, 0} },
+{"fcompi",  1, 0xdff0, X, Cpu686, FP|ShortForm,		{ FloatReg, 0, 0} },
+{"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm,		{ FloatReg, FloatAcc, 0} },
+{"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm,		{ 0, 0, 0} },
+{"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm,		{ FloatReg, 0, 0} },
 
 /* MMX instructions.  */
 
-{"emms",     0, 0x0f77, X, FP,			{ 0, 0, 0 } },
-{"movd",     2, 0x0f6e, X, FP|Modrm,		{ Reg32|LongMem, RegMMX, 0 } },
-{"movd",     2, 0x0f7e, X, FP|Modrm,		{ RegMMX, Reg32|LongMem, 0 } },
-{"movq",     2, 0x0f6f, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"movq",     2, 0x0f7f, X, FP|Modrm,		{ RegMMX, RegMMX|LongMem, 0 } },
-{"packssdw", 2, 0x0f6b, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"packsswb", 2, 0x0f63, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"packuswb", 2, 0x0f67, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"paddb",    2, 0x0ffc, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"paddw",    2, 0x0ffd, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"paddd",    2, 0x0ffe, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"paddsb",   2, 0x0fec, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"paddsw",   2, 0x0fed, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"paddusb",  2, 0x0fdc, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"paddusw",  2, 0x0fdd, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pand",     2, 0x0fdb, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pandn",    2, 0x0fdf, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpeqb",  2, 0x0f74, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpeqw",  2, 0x0f75, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpeqd",  2, 0x0f76, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpgtb",  2, 0x0f64, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpgtw",  2, 0x0f65, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pcmpgtd",  2, 0x0f66, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pmaddwd",  2, 0x0ff5, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pmulhw",   2, 0x0fe5, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pmullw",   2, 0x0fd5, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"por",	     2, 0x0feb, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psllw",    2, 0x0ff1, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psllw",    2, 0x0f71, 6, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"pslld",    2, 0x0ff2, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pslld",    2, 0x0f72, 6, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"psllq",    2, 0x0ff3, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psllq",    2, 0x0f73, 6, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"psraw",    2, 0x0fe1, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psraw",    2, 0x0f71, 4, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"psrad",    2, 0x0fe2, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psrad",    2, 0x0f72, 4, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"psrlw",    2, 0x0fd1, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psrlw",    2, 0x0f71, 2, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"psrld",    2, 0x0fd2, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psrld",    2, 0x0f72, 2, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"psrlq",    2, 0x0fd3, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psrlq",    2, 0x0f73, 2, FP|Modrm,		{ Imm8, RegMMX, 0 } },
-{"psubb",    2, 0x0ff8, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psubw",    2, 0x0ff9, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psubd",    2, 0x0ffa, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psubsb",   2, 0x0fe8, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psubsw",   2, 0x0fe9, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psubusb",  2, 0x0fd8, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"psubusw",  2, 0x0fd9, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"punpckhbw",2, 0x0f68, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"punpckhwd",2, 0x0f69, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"punpckhdq",2, 0x0f6a, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"punpcklbw",2, 0x0f60, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"punpcklwd",2, 0x0f61, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"punpckldq",2, 0x0f62, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
-{"pxor",     2, 0x0fef, X, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"emms",     0, 0x0f77, X, CpuMMX, FP,			{ 0, 0, 0 } },
+{"movd",     2, 0x0f6e, X, CpuMMX, FP|Modrm,		{ Reg32|LongMem, RegMMX, 0 } },
+{"movd",     2, 0x0f7e, X, CpuMMX, FP|Modrm,		{ RegMMX, Reg32|LongMem, 0 } },
+{"movq",     2, 0x0f6f, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"movq",     2, 0x0f7f, X, CpuMMX, FP|Modrm,		{ RegMMX, RegMMX|LongMem, 0 } },
+{"packssdw", 2, 0x0f6b, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"packsswb", 2, 0x0f63, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"packuswb", 2, 0x0f67, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddb",    2, 0x0ffc, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddw",    2, 0x0ffd, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddd",    2, 0x0ffe, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddsb",   2, 0x0fec, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddsw",   2, 0x0fed, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddusb",  2, 0x0fdc, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"paddusw",  2, 0x0fdd, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pand",     2, 0x0fdb, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pandn",    2, 0x0fdf, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpeqb",  2, 0x0f74, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpeqw",  2, 0x0f75, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpeqd",  2, 0x0f76, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpgtb",  2, 0x0f64, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpgtw",  2, 0x0f65, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pcmpgtd",  2, 0x0f66, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pmaddwd",  2, 0x0ff5, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pmulhw",   2, 0x0fe5, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pmullw",   2, 0x0fd5, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"por",	     2, 0x0feb, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psllw",    2, 0x0ff1, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psllw",    2, 0x0f71, 6, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"pslld",    2, 0x0ff2, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pslld",    2, 0x0f72, 6, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psllq",    2, 0x0ff3, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psllq",    2, 0x0f73, 6, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psraw",    2, 0x0fe1, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psraw",    2, 0x0f71, 4, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psrad",    2, 0x0fe2, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psrad",    2, 0x0f72, 4, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psrlw",    2, 0x0fd1, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psrlw",    2, 0x0f71, 2, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psrld",    2, 0x0fd2, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psrld",    2, 0x0f72, 2, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psrlq",    2, 0x0fd3, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psrlq",    2, 0x0f73, 2, CpuMMX, FP|Modrm,		{ Imm8, RegMMX, 0 } },
+{"psubb",    2, 0x0ff8, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubw",    2, 0x0ff9, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubd",    2, 0x0ffa, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubsb",   2, 0x0fe8, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubsw",   2, 0x0fe9, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubusb",  2, 0x0fd8, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"psubusw",  2, 0x0fd9, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpckhbw",2, 0x0f68, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpckhwd",2, 0x0f69, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpckhdq",2, 0x0f6a, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpcklbw",2, 0x0f60, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpcklwd",2, 0x0f61, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"punpckldq",2, 0x0f62, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
+{"pxor",     2, 0x0fef, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
 
 
 /* PIII Katmai New Instructions / SIMD instructions.  */
 
-{"addps",     2, 0x0f58,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"addss",     2, 0xf30f58,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"andnps",    2, 0x0f55,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"andps",     2, 0x0f54,    X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpeqps",   2, 0x0fc2,    0, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpeqss",   2, 0xf30fc2,  0, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpleps",   2, 0x0fc2,    2, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpless",   2, 0xf30fc2,  2, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpltps",   2, 0x0fc2,    1, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpltss",   2, 0xf30fc2,  1, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpneqps",  2, 0x0fc2,    4, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpneqss",  2, 0xf30fc2,  4, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpnleps",  2, 0x0fc2,    6, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpnless",  2, 0xf30fc2,  6, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpnltps",  2, 0x0fc2,    5, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpnltss",  2, 0xf30fc2,  5, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpordps",  2, 0x0fc2,    7, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpordss",  2, 0xf30fc2,  7, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpunordps",2, 0x0fc2,    3, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"cmpunordss",2, 0xf30fc2,  3, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cmpps",     3, 0x0fc2,    X, FP|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
-{"cmpss",     3, 0xf30fc2,  X, FP|Modrm,	{ Imm8, RegXMM|WordMem, RegXMM } },
-{"comiss",    2, 0x0f2f,    X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"cvtpi2ps",  2, 0x0f2a,    X, FP|Modrm,	{ RegMMX|LLongMem, RegXMM, 0 } },
-{"cvtps2pi",  2, 0x0f2d,    X, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
-{"cvtsi2ss",  2, 0xf30f2a,  X, FP|Modrm,	{ Reg32|WordMem, RegXMM, 0 } },
-{"cvtss2si",  2, 0xf30f2d,  X, FP|Modrm,	{ RegXMM|WordMem, Reg32, 0 } },
-{"cvttps2pi", 2, 0x0f2c,    X, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
-{"cvttss2si", 2, 0xf30f2c,  X, FP|Modrm,	{ RegXMM|WordMem, Reg32, 0 } },
-{"divps",     2, 0x0f5e,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"divss",     2, 0xf30f5e,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"ldmxcsr",   1, 0x0fae,    2, FP|Modrm, 	{ WordMem, 0, 0 } },
-{"maskmovq",  2, 0x0ff7,    X, FP|Modrm,	{ RegMMX|InvMem, RegMMX, 0 } },
-{"maxps",     2, 0x0f5f,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"maxss",     2, 0xf30f5f,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"minps",     2, 0x0f5d,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"minss",     2, 0xf30f5d,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"movaps",    2, 0x0f28,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"movaps",    2, 0x0f29,    X, FP|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
-{"movhlps",   2, 0x0f12,    X, FP|Modrm,	{ RegXMM|InvMem, RegXMM, 0 } },
-{"movhps",    2, 0x0f16,    X, FP|Modrm,	{ LLongMem, RegXMM, 0 } },
-{"movhps",    2, 0x0f17,    X, FP|Modrm,	{ RegXMM, LLongMem, 0 } },
-{"movlhps",   2, 0x0f16,    X, FP|Modrm,	{ RegXMM|InvMem, RegXMM, 0 } },
-{"movlps",    2, 0x0f12,    X, FP|Modrm,	{ LLongMem, RegXMM, 0 } },
-{"movlps",    2, 0x0f13,    X, FP|Modrm,	{ RegXMM, LLongMem, 0 } },
-{"movmskps",  2, 0x0f50,    X, FP|Modrm,	{ RegXMM|InvMem, Reg32, 0 } },
-{"movntps",   2, 0x0f2b,    X, FP|Modrm, 	{ RegXMM, LLongMem, 0 } },
-{"movntq",    2, 0x0fe7,    X, FP|Modrm, 	{ RegMMX, LLongMem, 0 } },
-{"movss",     2, 0xf30f10,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"movss",     2, 0xf30f11,  X, FP|Modrm,	{ RegXMM, RegXMM|WordMem, 0 } },
-{"movups",    2, 0x0f10,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"movups",    2, 0x0f11,    X, FP|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
-{"mulps",     2, 0x0f59,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"mulss",     2, 0xf30f59,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"orps",      2, 0x0f56,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pavgb",     2, 0x0fe0,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"pavgw",     2, 0x0fe3,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"pextrw",    3, 0x0fc5,    X, FP|Modrm,	{ Imm8, RegMMX, Reg32|InvMem } },
-{"pinsrw",    3, 0x0fc4,    X, FP|Modrm,	{ Imm8, Reg32|ShortMem, RegMMX } },
-{"pmaxsw",    2, 0x0fee,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"pmaxub",    2, 0x0fde,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"pminsw",    2, 0x0fea,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"pminub",    2, 0x0fda,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"pmovmskb",  2, 0x0fd7,    X, FP|Modrm,	{ RegMMX, Reg32|InvMem, 0 } },
-{"pmulhuw",   2, 0x0fe4,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"prefetchnta", 1, 0x0f18,  0, FP|Modrm, 	{ LLongMem, 0, 0 } },
-{"prefetcht0",  1, 0x0f18,  1, FP|Modrm, 	{ LLongMem, 0, 0 } },
-{"prefetcht1",  1, 0x0f18,  2, FP|Modrm, 	{ LLongMem, 0, 0 } },
-{"prefetcht2",  1, 0x0f18,  3, FP|Modrm, 	{ LLongMem, 0, 0 } },
-{"psadbw",    2, 0x0ff6,    X, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
-{"pshufw",    3, 0x0f70,    X, FP|Modrm,	{ Imm8, RegMMX|LLongMem, RegMMX } },
-{"rcpps",     2, 0x0f53,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"rcpss",     2, 0xf30f53,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"rsqrtps",   2, 0x0f52,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"rsqrtss",   2, 0xf30f52,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"sfence",    0, 0x0faef8,  X, FP,		{ 0, 0, 0 } },
-{"shufps",    3, 0x0fc6,    X, FP|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
-{"sqrtps",    2, 0x0f51,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"sqrtss",    2, 0xf30f51,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"stmxcsr",   1, 0x0fae,    3, FP|Modrm, 	{ WordMem, 0, 0 } },
-{"subps",     2, 0x0f5c,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"subss",     2, 0xf30f5c,  X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"ucomiss",   2, 0x0f2e,    X, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
-{"unpckhps",  2, 0x0f15,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"unpcklps",  2, 0x0f14,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"xorps",     2, 0x0f57,    X, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"addps",     2, 0x0f58,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"addss",     2, 0xf30f58,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"andnps",    2, 0x0f55,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"andps",     2, 0x0f54,    X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpeqps",   2, 0x0fc2,    0, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpeqss",   2, 0xf30fc2,  0, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpleps",   2, 0x0fc2,    2, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpless",   2, 0xf30fc2,  2, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpltps",   2, 0x0fc2,    1, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpltss",   2, 0xf30fc2,  1, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpneqps",  2, 0x0fc2,    4, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpneqss",  2, 0xf30fc2,  4, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpnleps",  2, 0x0fc2,    6, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpnless",  2, 0xf30fc2,  6, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpnltps",  2, 0x0fc2,    5, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpnltss",  2, 0xf30fc2,  5, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpordps",  2, 0x0fc2,    7, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpordss",  2, 0xf30fc2,  7, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpunordps",2, 0x0fc2,    3, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"cmpunordss",2, 0xf30fc2,  3, CpuSSE, FP|Modrm|ImmExt,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cmpps",     3, 0x0fc2,    X, CpuSSE, FP|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"cmpss",     3, 0xf30fc2,  X, CpuSSE, FP|Modrm,	{ Imm8, RegXMM|WordMem, RegXMM } },
+{"comiss",    2, 0x0f2f,    X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"cvtpi2ps",  2, 0x0f2a,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegXMM, 0 } },
+{"cvtps2pi",  2, 0x0f2d,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
+{"cvtsi2ss",  2, 0xf30f2a,  X, CpuSSE, FP|Modrm,	{ Reg32|WordMem, RegXMM, 0 } },
+{"cvtss2si",  2, 0xf30f2d,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, Reg32, 0 } },
+{"cvttps2pi", 2, 0x0f2c,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegMMX, 0 } },
+{"cvttss2si", 2, 0xf30f2c,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, Reg32, 0 } },
+{"divps",     2, 0x0f5e,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"divss",     2, 0xf30f5e,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"ldmxcsr",   1, 0x0fae,    2, CpuSSE, FP|Modrm, 	{ WordMem, 0, 0 } },
+{"maskmovq",  2, 0x0ff7,    X, CpuSSE, FP|Modrm,	{ RegMMX|InvMem, RegMMX, 0 } },
+{"maxps",     2, 0x0f5f,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"maxss",     2, 0xf30f5f,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"minps",     2, 0x0f5d,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"minss",     2, 0xf30f5d,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"movaps",    2, 0x0f28,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movaps",    2, 0x0f29,    X, CpuSSE, FP|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
+{"movhlps",   2, 0x0f12,    X, CpuSSE, FP|Modrm,	{ RegXMM|InvMem, RegXMM, 0 } },
+{"movhps",    2, 0x0f16,    X, CpuSSE, FP|Modrm,	{ LLongMem, RegXMM, 0 } },
+{"movhps",    2, 0x0f17,    X, CpuSSE, FP|Modrm,	{ RegXMM, LLongMem, 0 } },
+{"movlhps",   2, 0x0f16,    X, CpuSSE, FP|Modrm,	{ RegXMM|InvMem, RegXMM, 0 } },
+{"movlps",    2, 0x0f12,    X, CpuSSE, FP|Modrm,	{ LLongMem, RegXMM, 0 } },
+{"movlps",    2, 0x0f13,    X, CpuSSE, FP|Modrm,	{ RegXMM, LLongMem, 0 } },
+{"movmskps",  2, 0x0f50,    X, CpuSSE, FP|Modrm,	{ RegXMM|InvMem, Reg32, 0 } },
+{"movntps",   2, 0x0f2b,    X, CpuSSE, FP|Modrm, 	{ RegXMM, LLongMem, 0 } },
+{"movntq",    2, 0x0fe7,    X, CpuSSE, FP|Modrm, 	{ RegMMX, LLongMem, 0 } },
+{"movss",     2, 0xf30f10,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"movss",     2, 0xf30f11,  X, CpuSSE, FP|Modrm,	{ RegXMM, RegXMM|WordMem, 0 } },
+{"movups",    2, 0x0f10,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movups",    2, 0x0f11,    X, CpuSSE, FP|Modrm,	{ RegXMM, RegXMM|LLongMem, 0 } },
+{"mulps",     2, 0x0f59,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"mulss",     2, 0xf30f59,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"orps",      2, 0x0f56,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pavgb",     2, 0x0fe0,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pavgw",     2, 0x0fe3,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pextrw",    3, 0x0fc5,    X, CpuSSE, FP|Modrm,	{ Imm8, RegMMX, Reg32|InvMem } },
+{"pinsrw",    3, 0x0fc4,    X, CpuSSE, FP|Modrm,	{ Imm8, Reg32|ShortMem, RegMMX } },
+{"pmaxsw",    2, 0x0fee,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pmaxub",    2, 0x0fde,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pminsw",    2, 0x0fea,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pminub",    2, 0x0fda,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pmovmskb",  2, 0x0fd7,    X, CpuSSE, FP|Modrm,	{ RegMMX, Reg32|InvMem, 0 } },
+{"pmulhuw",   2, 0x0fe4,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"prefetchnta", 1, 0x0f18,  0, CpuSSE, FP|Modrm, 	{ LLongMem, 0, 0 } },
+{"prefetcht0",  1, 0x0f18,  1, CpuSSE, FP|Modrm, 	{ LLongMem, 0, 0 } },
+{"prefetcht1",  1, 0x0f18,  2, CpuSSE, FP|Modrm, 	{ LLongMem, 0, 0 } },
+{"prefetcht2",  1, 0x0f18,  3, CpuSSE, FP|Modrm, 	{ LLongMem, 0, 0 } },
+{"psadbw",    2, 0x0ff6,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
+{"pshufw",    3, 0x0f70,    X, CpuSSE, FP|Modrm,	{ Imm8, RegMMX|LLongMem, RegMMX } },
+{"rcpps",     2, 0x0f53,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"rcpss",     2, 0xf30f53,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"rsqrtps",   2, 0x0f52,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"rsqrtss",   2, 0xf30f52,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"sfence",    0, 0x0faef8,  X, CpuSSE, FP,		{ 0, 0, 0 } },
+{"shufps",    3, 0x0fc6,    X, CpuSSE, FP|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"sqrtps",    2, 0x0f51,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"sqrtss",    2, 0xf30f51,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"stmxcsr",   1, 0x0fae,    3, CpuSSE, FP|Modrm, 	{ WordMem, 0, 0 } },
+{"subps",     2, 0x0f5c,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"subss",     2, 0xf30f5c,  X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"ucomiss",   2, 0x0f2e,    X, CpuSSE, FP|Modrm,	{ RegXMM|WordMem, RegXMM, 0 } },
+{"unpckhps",  2, 0x0f15,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"unpcklps",  2, 0x0f14,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"xorps",     2, 0x0f57,    X, CpuSSE, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 
 /* AMD 3DNow! instructions.  */
 
-{"prefetch", 1, 0x0f0d,	   0, FP|Modrm,		{ ByteMem, 0, 0 } },
-{"prefetchw",1, 0x0f0d,	   1, FP|Modrm,		{ ByteMem, 0, 0 } },
-{"femms",    0, 0x0f0e,	   X, FP,		{ 0, 0, 0 } },
-{"pavgusb",  2, 0x0f0f, 0xbf, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pf2id",    2, 0x0f0f, 0x1d, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pf2iw",    2, 0x0f0f, 0x1c, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
-{"pfacc",    2, 0x0f0f, 0xae, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfadd",    2, 0x0f0f, 0x9e, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfcmpeq",  2, 0x0f0f, 0xb0, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfcmpge",  2, 0x0f0f, 0x90, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfcmpgt",  2, 0x0f0f, 0xa0, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfmax",    2, 0x0f0f, 0xa4, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfmin",    2, 0x0f0f, 0x94, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfmul",    2, 0x0f0f, 0xb4, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfnacc",   2, 0x0f0f, 0x8a, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
-{"pfpnacc",  2, 0x0f0f, 0x8e, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
-{"pfrcp",    2, 0x0f0f, 0x96, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfrcpit1", 2, 0x0f0f, 0xa6, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfrcpit2", 2, 0x0f0f, 0xb6, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfrsqit1", 2, 0x0f0f, 0xa7, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfrsqrt",  2, 0x0f0f, 0x97, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfsub",    2, 0x0f0f, 0x9a, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pfsubr",   2, 0x0f0f, 0xaa, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pi2fd",    2, 0x0f0f, 0x0d, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pi2fw",    2, 0x0f0f, 0x0c, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
-{"pmulhrw",  2, 0x0f0f, 0xb7, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
-{"pswapd",   2, 0x0f0f, 0xbb, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
-
-{NULL, 0, 0, 0, 0, { 0, 0, 0} }	/* sentinel */
+{"prefetch", 1, 0x0f0d,	   0, Cpu3dnow, FP|Modrm,		{ ByteMem, 0, 0 } },
+{"prefetchw",1, 0x0f0d,	   1, Cpu3dnow, FP|Modrm,		{ ByteMem, 0, 0 } },
+{"femms",    0, 0x0f0e,	   X, Cpu3dnow, FP,			{ 0, 0, 0 } },
+{"pavgusb",  2, 0x0f0f, 0xbf, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pf2id",    2, 0x0f0f, 0x1d, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pf2iw",    2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfacc",    2, 0x0f0f, 0xae, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfadd",    2, 0x0f0f, 0x9e, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfcmpeq",  2, 0x0f0f, 0xb0, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfcmpge",  2, 0x0f0f, 0x90, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfcmpgt",  2, 0x0f0f, 0xa0, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfmax",    2, 0x0f0f, 0xa4, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfmin",    2, 0x0f0f, 0x94, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfmul",    2, 0x0f0f, 0xb4, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfnacc",   2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfpnacc",  2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfrcp",    2, 0x0f0f, 0x96, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfrsqrt",  2, 0x0f0f, 0x97, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfsub",    2, 0x0f0f, 0x9a, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pfsubr",   2, 0x0f0f, 0xaa, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pi2fd",    2, 0x0f0f, 0x0d, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pi2fw",    2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pmulhrw",  2, 0x0f0f, 0xb7, Cpu3dnow, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+{"pswapd",   2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686, FP|Modrm|ImmExt,	{ RegMMX|LongMem, RegMMX, 0 } },
+
+/* sentinel */
+{NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }
 };
 #undef X
 #undef NoSuf
@@ -1059,6 +1079,7 @@ static const template i386_optab[] = {
 #undef bw_Suf
 #undef bl_Suf
 #undef wl_Suf
+#undef wld_Suf
 #undef sl_Suf
 #undef sld_Suf
 #undef sldx_Suf