IA-64 ELF support.

110 files changed, 40578 insertions, 1 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 458fbfa..c300410 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,31 @@
+Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
+			  David Mosberger  <davidm@hpl.hp.com>
+			  Timothy Wall <twall@cygnus.com>
+			  Jim Wilson  <wilson@cygnus.com>
+	
+	* Makefile.am (ALL_MACHINES): Add cpu-ia64.lo.
+	(ALL_MACHINES_CFILES): Add cpu-ia64.c.
+	(BFD64_BACKENDS): Add elf64-ia64.lo.
+	(BFD64_BACKENDS_CFILES): Add elf64-ia64.c.
+	(cpu-ia64.lo, elf64-ia64.lo): New rules.
+	* Makefile.in: Rebuild.
+	* archures.c (enum bfd_architecture): Add bfd_arch_ia64.
+	(bfd_ia64_arch): Declare.
+	(bfd_archures_list): Add bfd_ia64_arch.
+	* bfd-in2.h: Rebuild.
+	* config.bfd: (ia64*-*-linux-gnu*, ia64*-*-elf*): New targets.
+	* configure: Rebuild.
+	* configure.host: (ia64-*-linux*): New host.
+	* configure.in (bfd_elf64_ia64_little_vec, bfd_elf64_ia64_big_vec,
+	bfd_efi_app_ia64_vec, bfd_efi_app_ia64_vec): New vectors.
+	* elf.c (prep_headers): Add bfd_arch_ia64.
+	* libbfd.h: Rebuild.
+	* reloc.c: Add IA-64 relocations.
+	* targets.c (bfd_elf64_ia64_little_vec, bfd_elf64_ia64_big_vec):
+	Declare.
+	(bfd_target_vect): Add bfd_elf64_ia64_little_vec.
+	* cpu-ia64-opc.c, cpu-ia64.c, elf64-ia64.c: New files.
+	
 2000-04-21  Richard Henderson  <rth@cygnus.com>
 
 	* elf32-d30v.c (bfd_elf_d30v_reloc): Don't modify section
diff --git a/bfd/Makefile.am b/bfd/Makefile.am
index 142fa6d..fd7fe42 100644
--- a/bfd/Makefile.am
+++ b/bfd/Makefile.am
@@ -51,6 +51,7 @@ ALL_MACHINES = \
 	cpu-h8300.lo \
 	cpu-h8500.lo \
 	cpu-hppa.lo \
+	cpu-ia64.lo \
 	cpu-i370.lo \
 	cpu-i386.lo \
 	cpu-i860.lo \
@@ -89,6 +90,7 @@ ALL_MACHINES_CFILES = \
 	cpu-h8300.c \
 	cpu-h8500.c \
 	cpu-hppa.c \
+	cpu-ia64.c \
 	cpu-i370.c \
 	cpu-i386.c \
 	cpu-i860.c \
@@ -388,6 +390,7 @@ BFD64_BACKENDS = \
 	coff-ia64.lo \
 	demo64.lo \
 	elf64-alpha.lo \
+	elf64-ia64.lo \
 	elf64-gen.lo \
 	elf64-mips.lo \
 	elf64-sparc.lo \
@@ -401,6 +404,7 @@ BFD64_BACKENDS_CFILES = \
 	coff-ia64.c \
 	demo64.c \
 	elf64-alpha.c \
+	elf64-ia64.c \
 	elf64-gen.c \
 	elf64-mips.c \
 	elf64-sparc.c \
@@ -654,6 +658,11 @@ config.status: $(srcdir)/configure $(srcdir)/config.bfd $(srcdir)/configure.host
 	$(SHELL) ./config.status --recheck
 
 
+cpu-ia64.lo: cpu-ia64.c cpu-ia64-opc.c $(srcdir)/../opcodes/ia64-opc.h
+elf64-ia64.lo: elf64-ia64.c elf-bfd.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/reloc-macros.h \
+  elf64-target.h
 elfarm-oabi.lo: elfarm-oabi.c elf32-arm.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h elf32-target.h
diff --git a/bfd/Makefile.in b/bfd/Makefile.in
index 1421bb2..360b32d 100644
--- a/bfd/Makefile.in
+++ b/bfd/Makefile.in
@@ -166,6 +166,7 @@ ALL_MACHINES = \
 	cpu-h8300.lo \
 	cpu-h8500.lo \
 	cpu-hppa.lo \
+	cpu-ia64.lo \
 	cpu-i370.lo \
 	cpu-i386.lo \
 	cpu-i860.lo \
@@ -205,6 +206,7 @@ ALL_MACHINES_CFILES = \
 	cpu-h8300.c \
 	cpu-h8500.c \
 	cpu-hppa.c \
+	cpu-ia64.c \
 	cpu-i370.c \
 	cpu-i386.c \
 	cpu-i860.c \
@@ -507,6 +509,7 @@ BFD64_BACKENDS = \
 	coff-ia64.lo \
 	demo64.lo \
 	elf64-alpha.lo \
+	elf64-ia64.lo \
 	elf64-gen.lo \
 	elf64-mips.lo \
 	elf64-sparc.lo \
@@ -521,6 +524,7 @@ BFD64_BACKENDS_CFILES = \
 	coff-ia64.c \
 	demo64.c \
 	elf64-alpha.c \
+	elf64-ia64.c \
 	elf64-gen.c \
 	elf64-mips.c \
 	elf64-sparc.c \
@@ -1182,6 +1186,11 @@ stmp-lcoff-h: $(LIBCOFF_H_FILES)
 config.status: $(srcdir)/configure $(srcdir)/config.bfd $(srcdir)/configure.host
 	$(SHELL) ./config.status --recheck
 
+cpu-ia64.lo: cpu-ia64.c cpu-ia64-opc.c $(srcdir)/../opcodes/ia64-opc.h
+elf64-ia64.lo: elf64-ia64.c elf-bfd.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/reloc-macros.h \
+  elf64-target.h
 elfarm-oabi.lo: elfarm-oabi.c elf32-arm.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h elf32-target.h
diff --git a/bfd/archures.c b/bfd/archures.c
index d24ee82..536f2b1 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -199,6 +199,7 @@ DESCRIPTION
 .  bfd_arch_fr30,
 .#define bfd_mach_fr30		0x46523330
 .  bfd_arch_mcore,
+.  bfd_arch_ia64,      {* HP/Intel ia64 *}
 .  bfd_arch_pj,
 .  bfd_arch_avr,       {* Atmel AVR microcontrollers *}
 .#define bfd_mach_avr1		1
@@ -279,6 +280,7 @@ extern const bfd_arch_info_type bfd_v850_arch;
 extern const bfd_arch_info_type bfd_fr30_arch;
 extern const bfd_arch_info_type bfd_mcore_arch;
 extern const bfd_arch_info_type bfd_avr_arch;
+extern const bfd_arch_info_type bfd_ia64_arch;
 
 static const bfd_arch_info_type * const bfd_archures_list[] =
 {
@@ -320,6 +322,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
   &bfd_fr30_arch,
   &bfd_mcore_arch,
   &bfd_avr_arch,
+  &bfd_ia64_arch,
 #endif
   0
 };
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index e20c650..f00e8a1 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1432,6 +1432,7 @@ enum bfd_architecture
   bfd_arch_fr30,
 #define bfd_mach_fr30          0x46523330
   bfd_arch_mcore,
+  bfd_arch_ia64,       /* HP/Intel ia64 */
   bfd_arch_pj,
   bfd_arch_avr,        /* Atmel AVR microcontrollers */
 #define bfd_mach_avr1          1
@@ -2448,6 +2449,71 @@ is stored in the reloc's addend.  For Rel hosts, we are forced to put
 this offset in the reloc's section offset. */
   BFD_RELOC_VTABLE_INHERIT,
   BFD_RELOC_VTABLE_ENTRY,
+
+/* Intel IA64 Relocations. */
+  BFD_RELOC_IA64_IMM14,
+  BFD_RELOC_IA64_IMM22,
+  BFD_RELOC_IA64_IMM64,
+  BFD_RELOC_IA64_DIR32MSB,
+  BFD_RELOC_IA64_DIR32LSB,
+  BFD_RELOC_IA64_DIR64MSB,
+  BFD_RELOC_IA64_DIR64LSB,
+  BFD_RELOC_IA64_GPREL22,
+  BFD_RELOC_IA64_GPREL64I,
+  BFD_RELOC_IA64_GPREL32MSB,
+  BFD_RELOC_IA64_GPREL32LSB,
+  BFD_RELOC_IA64_GPREL64MSB,
+  BFD_RELOC_IA64_GPREL64LSB,
+  BFD_RELOC_IA64_LTOFF22,
+  BFD_RELOC_IA64_LTOFF64I,
+  BFD_RELOC_IA64_PLTOFF22,
+  BFD_RELOC_IA64_PLTOFF64I,
+  BFD_RELOC_IA64_PLTOFF64MSB,
+  BFD_RELOC_IA64_PLTOFF64LSB,
+  BFD_RELOC_IA64_FPTR64I,
+  BFD_RELOC_IA64_FPTR32MSB,
+  BFD_RELOC_IA64_FPTR32LSB,
+  BFD_RELOC_IA64_FPTR64MSB,
+  BFD_RELOC_IA64_FPTR64LSB,
+  BFD_RELOC_IA64_PCREL21B,
+  BFD_RELOC_IA64_PCREL21M,
+  BFD_RELOC_IA64_PCREL21F,
+  BFD_RELOC_IA64_PCREL32MSB,
+  BFD_RELOC_IA64_PCREL32LSB,
+  BFD_RELOC_IA64_PCREL64MSB,
+  BFD_RELOC_IA64_PCREL64LSB,
+  BFD_RELOC_IA64_LTOFF_FPTR22,
+  BFD_RELOC_IA64_LTOFF_FPTR64I,
+  BFD_RELOC_IA64_LTOFF_FPTR64MSB,
+  BFD_RELOC_IA64_LTOFF_FPTR64LSB,
+  BFD_RELOC_IA64_SEGBASE,
+  BFD_RELOC_IA64_SEGREL32MSB,
+  BFD_RELOC_IA64_SEGREL32LSB,
+  BFD_RELOC_IA64_SEGREL64MSB,
+  BFD_RELOC_IA64_SEGREL64LSB,
+  BFD_RELOC_IA64_SECREL32MSB,
+  BFD_RELOC_IA64_SECREL32LSB,
+  BFD_RELOC_IA64_SECREL64MSB,
+  BFD_RELOC_IA64_SECREL64LSB,
+  BFD_RELOC_IA64_REL32MSB,
+  BFD_RELOC_IA64_REL32LSB,
+  BFD_RELOC_IA64_REL64MSB,
+  BFD_RELOC_IA64_REL64LSB,
+  BFD_RELOC_IA64_LTV32MSB,
+  BFD_RELOC_IA64_LTV32LSB,
+  BFD_RELOC_IA64_LTV64MSB,
+  BFD_RELOC_IA64_LTV64LSB,
+  BFD_RELOC_IA64_IPLTMSB,
+  BFD_RELOC_IA64_IPLTLSB,
+  BFD_RELOC_IA64_EPLTMSB,
+  BFD_RELOC_IA64_EPLTLSB,
+  BFD_RELOC_IA64_COPY,
+  BFD_RELOC_IA64_TPREL22,
+  BFD_RELOC_IA64_TPREL64MSB,
+  BFD_RELOC_IA64_TPREL64LSB,
+  BFD_RELOC_IA64_LTOFF_TP22,
+  BFD_RELOC_IA64_LTOFF22X,
+  BFD_RELOC_IA64_LDXMOV,
   BFD_RELOC_UNUSED };
 typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
 reloc_howto_type *
diff --git a/bfd/config.bfd b/bfd/config.bfd
index eaaac05..9744cbd 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -80,6 +80,10 @@ case "${targ}" in
   alpha*-*-*)
     targ_defvec=ecoffalpha_little_vec
     ;;
+  ia64*-*-linux-gnu* | ia64*-*-elf*)
+    targ_defvec=bfd_elf64_ia64_little_vec
+    targ_selvecs="bfd_elf64_ia64_big_vec bfd_efi_app_ia64_vec"
+    ;;
 #endif /* BFD64 */
 
   arc-*-elf*)
diff --git a/bfd/configure b/bfd/configure
index feaae04..63a65ac 100755
--- a/bfd/configure
+++ b/bfd/configure
@@ -5112,6 +5112,13 @@ do
   				target64=true ;;
     bfd_elf64_alpha_vec)	tb="$tb elf64-alpha.lo elf64.lo $elf"
 				target64=true ;;
+    bfd_elf64_ia64_little_vec)	tb="$tb elf64-ia64.lo elf64.lo $elf"
+				target64=true ;;
+    bfd_elf64_ia64_big_vec)	tb="$tb elf64-ia64.lo elf64.lo $elf"
+				target64=true ;;
+    bfd_efi_app_ia32_vec)	tb="$tb efi-app-ia32.lo cofflink.lo" ;;
+    bfd_efi_app_ia64_vec)	tb="$tb efi-app-ia64.lo cofflink.lo"
+				target64=true ;;
     bfd_elf32_avr_vec)		tb="$tb elf32-avr.lo elf32.lo $elf" ;;
     bfd_elf32_littlearc_vec)	tb="$tb elf32-arc.lo elf32.lo $elf" ;;
     bfd_elf32_littlearm_vec)	tb="$tb elfarm-nabi.lo elf32.lo $elf" ;;
diff --git a/bfd/configure.host b/bfd/configure.host
index e24cd60..bd5391c 100644
--- a/bfd/configure.host
+++ b/bfd/configure.host
@@ -27,6 +27,8 @@ hppa*-*-mpeix*)		HDEFINES=-DHOST_HPPAMPEIX ;;
 hppa*-*-bsd*)		HDEFINES=-DHOST_HPPABSD ;;
 hppa*-*-osf*)		HDEFINES=-DHOST_HPPAOSF ;;
 
+ia64-*-linux*)		host64=true; HOST_64BIT_TYPE=long ;;
+
 i[3456]86-sequent-bsd*)	HDEFINES=-Dshared=genshared ;;
 i[3456]86-sequent-sysv4*) ;;
 i[3456]86-sequent-sysv*)	HDEFINES=-Dshared=genshared ;;
diff --git a/bfd/configure.in b/bfd/configure.in
index e62fcee..1a9b94a 100644
--- a/bfd/configure.in
+++ b/bfd/configure.in
@@ -469,6 +469,13 @@ do
   				target64=true ;;
     bfd_elf64_alpha_vec)	tb="$tb elf64-alpha.lo elf64.lo $elf"
 				target64=true ;;
+    bfd_elf64_ia64_little_vec)	tb="$tb elf64-ia64.lo elf64.lo $elf"
+				target64=true ;;
+    bfd_elf64_ia64_big_vec)	tb="$tb elf64-ia64.lo elf64.lo $elf"
+				target64=true ;;
+    bfd_efi_app_ia32_vec)	tb="$tb efi-app-ia32.lo cofflink.lo" ;;
+    bfd_efi_app_ia64_vec)	tb="$tb efi-app-ia64.lo cofflink.lo"
+				target64=true ;;
     bfd_elf32_avr_vec)		tb="$tb elf32-avr.lo elf32.lo $elf" ;;
     bfd_elf32_littlearc_vec)	tb="$tb elf32-arc.lo elf32.lo $elf" ;;
     bfd_elf32_littlearm_vec)	tb="$tb elfarm-nabi.lo elf32.lo $elf" ;;
diff --git a/bfd/cpu-ia64-opc.c b/bfd/cpu-ia64-opc.c
new file mode 100644
index 0000000..130dbe7
--- /dev/null
+++ b/bfd/cpu-ia64-opc.c
@@ -0,0 +1,586 @@
+/* Copyright (C) 1998, 1999  Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+
+/* Logically, this code should be part of libopcode but since some of
+   the operand insertion/extraction functions help bfd to implement
+   relocations, this code is included as part of elf64-ia64.c.  This
+   avoids circular dependencies between libopcode and libbfd and also
+   obviates the need for applications to link in libopcode when all
+   they really want is libbfd.
+
+   --davidm Mon Apr 13 22:14:02 1998 */
+
+#include "../opcodes/ia64-opc.h"
+
+#define NELEMS(a)  ((int) (sizeof (a) / sizeof ((a)[0])))
+
+static const char*
+ins_rsvd (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  return "internal error---this shouldn't happen";
+}
+
+static const char*
+ext_rsvd (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+  return "internal error---this shouldn't happen";
+}
+
+static const char*
+ins_const (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  return 0;
+}
+
+static const char*
+ext_const (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+  return 0;
+}
+
+static const char*
+ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  if (value >= 1u << self->field[0].bits)
+    return "register number out of range";
+
+  *code |= value << self->field[0].shift;
+  return 0;
+}
+
+static const char*
+ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+  *valuep = ((code >> self->field[0].shift)
+	     & ((1u << self->field[0].bits) - 1));
+  return 0;
+}
+
+static const char*
+ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  ia64_insn new = 0;
+  int i;
+
+  for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
+    {
+      new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
+	      << self->field[i].shift);
+      value >>= self->field[i].bits;
+    }
+  if (value)
+    return "integer operand out of range";
+
+  *code |= new;
+  return 0;
+}
+
+static const char*
+ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+  BFD_HOST_U_64_BIT value = 0;
+  int i, bits = 0, total = 0;
+
+  for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
+    {
+      bits = self->field[i].bits;
+      value |= ((code >> self->field[i].shift)
+		& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
+      total += bits;
+    }
+  *valuep = value;
+  return 0;
+}
+
+static const char*
+ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  if (value & 0x7)
+    return "value not an integer multiple of 8";
+  return ins_immu (self, value >> 3, code);
+}
+
+static const char*
+ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+  const char *result;
+
+  result = ext_immu (self, code, valuep);
+  if (result)
+    return result;
+
+  *valuep = *valuep << 3;
+  return 0;
+}
+
+static const char*
+ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
+		 ia64_insn *code, int scale)
+{
+  BFD_HOST_64_BIT svalue = value, sign_bit;
+  ia64_insn new = 0;
+  int i;
+
+  svalue >>= scale;
+
+  for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
+    {
+      new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
+	      << self->field[i].shift);
+      sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
+      svalue >>= self->field[i].bits;
+    }
+  if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
+    return "integer operand out of range";
+
+  *code |= new;
+  return 0;
+}
+
+static const char*
+ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
+		 ia64_insn *valuep, int scale)
+{
+  int i, bits = 0, total = 0, shift;
+  BFD_HOST_64_BIT val = 0;
+
+  for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
+    {
+      bits = self->field[i].bits;
+      val |= ((code >> self->field[i].shift)
+	      & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
+      total += bits;
+    }
+  /* sign extend: */
+  shift = 8*sizeof (val) - total;
+  val = (val << shift) >> shift;
+
+  *valuep = (val << scale);
+  return 0;
+}
+
+static const char*
+ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  return ins_imms_scaled (self, value, code, 0);
+}
+
+static const char*
+ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  if (value == (BFD_HOST_U_64_BIT) 0x100000000)
+    value = 0;
+  else
+    value = (((BFD_HOST_64_BIT)value << 32) >> 32);
+
+  return ins_imms_scaled (self, value, code, 0);
+}
+
+static const char*
+ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+  return ext_imms_scaled (self, code, valuep, 0);
+}
+
+static const char*
+ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  --value;
+  return ins_imms_scaled (self, value, code, 0);
+}
+
+static const char*
+ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
+	      ia64_insn *code)
+{
+  if (value == (BFD_HOST_U_64_BIT) 0x100000000)
+    value = 0;
+  else
+    value = (((BFD_HOST_64_BIT)value << 32) >> 32);
+
+  --value;
+  return ins_imms_scaled (self, value, code, 0);
+}
+
+static const char*
+ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+  const char *res = ext_imms_scaled (self, code, valuep, 0);
+
+  ++*valuep;
+  return res;
+}
+
+static const char*
+ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  return ins_imms_scaled (self, value, code, 1);
+}
+
+static const char*
+ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+  return ext_imms_scaled (self, code, valuep, 1);
+}
+
+static const char*
+ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  return ins_imms_scaled (self, value, code, 4);
+}
+
+static const char*
+ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+  return ext_imms_scaled (self, code, valuep, 4);
+}
+
+static const char*
+ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  return ins_imms_scaled (self, value, code, 16);
+}
+
+static const char*
+ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+  return ext_imms_scaled (self, code, valuep, 16);
+}
+
+static const char*
+ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
+  return ins_immu (self, value ^ mask, code);
+}
+
+static const char*
+ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+  const char *result;
+  ia64_insn mask;
+
+  mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
+  result = ext_immu (self, code, valuep);
+  if (!result)
+    {
+      mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
+      *valuep ^= mask;
+    }
+  return result;
+}
+
+static const char*
+ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  --value;
+  if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits)
+    return "count out of range";
+
+  *code |= value << self->field[0].shift;
+  return 0;
+}
+
+static const char*
+ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+  *valuep = ((code >> self->field[0].shift)
+	     & ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1;
+  return 0;
+}
+
+static const char*
+ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  --value;
+
+  if (value > 2)
+    return "count must be in range 1..3";
+
+  *code |= value << self->field[0].shift;
+  return 0;
+}
+
+static const char*
+ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+  *valuep = ((code >> self->field[0].shift) & 0x3) + 1;
+  return 0;
+}
+
+static const char*
+ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  switch (value)
+    {
+    case 0:	value = 0; break;
+    case 7:	value = 1; break;
+    case 15:	value = 2; break;
+    case 16:	value = 3; break;
+    default:	return "count must be 0, 7, 15, or 16";
+    }
+  *code |= value << self->field[0].shift;
+  return 0;
+}
+
+static const char*
+ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+  ia64_insn value;
+
+  value = (code >> self->field[0].shift) & 0x3;
+  switch (value)
+    {
+    case 0: value =  0; break;
+    case 1: value =  7; break;
+    case 2: value = 15; break;
+    case 3: value = 16; break;
+    }
+  *valuep = value;
+  return 0;
+}
+
+static const char*
+ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
+{
+  BFD_HOST_64_BIT val = value;
+  BFD_HOST_U_64_BIT sign = 0;
+
+  if (val < 0)
+    {
+      sign = 0x4;
+      value = -value;
+    }
+  switch (value)
+    {
+    case  1:	value = 3; break;
+    case  4:	value = 2; break;
+    case  8:	value = 1; break;
+    case 16:	value = 0; break;
+    default:	return "count must be +/- 1, 4, 8, or 16";
+    }
+  *code |= (sign | value) << self->field[0].shift;
+  return 0;
+}
+
+static const char*
+ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
+{
+  BFD_HOST_64_BIT val;
+  int negate;
+
+  val = (code >> self->field[0].shift) & 0x7;
+  negate = val & 0x4;
+  switch (val & 0x3)
+    {
+    case 0: val = 16; break;
+    case 1: val =  8; break;
+    case 2: val =  4; break;
+    case 3: val =  1; break;
+    }
+  if (negate)
+    val = -val;
+
+  *valuep = val;
+  return 0;
+}
+
+#define CST	IA64_OPND_CLASS_CST
+#define REG	IA64_OPND_CLASS_REG
+#define IND	IA64_OPND_CLASS_IND
+#define ABS	IA64_OPND_CLASS_ABS
+#define REL	IA64_OPND_CLASS_REL
+
+#define SDEC	IA64_OPND_FLAG_DECIMAL_SIGNED
+#define UDEC	IA64_OPND_FLAG_DECIMAL_UNSIGNED
+
+const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
+  {
+    /* constants: */
+    { CST, ins_const, ext_const, "NIL",		{{ 0, }}, 0, "<none>" },
+    { CST, ins_const, ext_const, "ar.ccv",	{{ 0, }}, 0, "ar.ccv" },
+    { CST, ins_const, ext_const, "ar.pfs",	{{ 0, }}, 0, "ar.pfs" },
+    { CST, ins_const, ext_const, "1",		{{ 0, }}, 0, "1" },
+    { CST, ins_const, ext_const, "8",		{{ 0, }}, 0, "1" },
+    { CST, ins_const, ext_const, "16",		{{ 0, }}, 0, "16" },
+    { CST, ins_const, ext_const, "r0",		{{ 0, }}, 0, "r0" },
+    { CST, ins_const, ext_const, "ip",		{{ 0, }}, 0, "ip" },
+    { CST, ins_const, ext_const, "pr",		{{ 0, }}, 0, "pr" },
+    { CST, ins_const, ext_const, "pr.rot",	{{ 0, }}, 0, "pr.rot" },
+    { CST, ins_const, ext_const, "psr",		{{ 0, }}, 0, "psr" },
+    { CST, ins_const, ext_const, "psr.l",	{{ 0, }}, 0, "psr.l" },
+    { CST, ins_const, ext_const, "psr.um",	{{ 0, }}, 0, "psr.um" },
+
+    /* register operands: */
+    { REG, ins_reg,   ext_reg,	"ar", {{ 7, 20}}, 0,		/* AR3 */
+      "an application register" },
+    { REG, ins_reg,   ext_reg,	 "b", {{ 3,  6}}, 0,		/* B1 */
+      "a branch register" },
+    { REG, ins_reg,   ext_reg,	 "b", {{ 3, 13}}, 0,		/* B2 */
+      "a branch register"},
+    { REG, ins_reg,   ext_reg,	"cr", {{ 7, 20}}, 0,		/* CR */
+      "a control register"},
+    { REG, ins_reg,   ext_reg,	 "f", {{ 7,  6}}, 0,		/* F1 */
+      "a floating-point register" },
+    { REG, ins_reg,   ext_reg,	 "f", {{ 7, 13}}, 0,		/* F2 */
+      "a floating-point register" },
+    { REG, ins_reg,   ext_reg,	 "f", {{ 7, 20}}, 0,		/* F3 */
+      "a floating-point register" },
+    { REG, ins_reg,   ext_reg,	 "f", {{ 7, 27}}, 0,		/* F4 */
+      "a floating-point register" },
+    { REG, ins_reg,   ext_reg,	 "p", {{ 6,  6}}, 0,		/* P1 */
+      "a predicate register" },
+    { REG, ins_reg,   ext_reg,	 "p", {{ 6, 27}}, 0,		/* P2 */
+      "a predicate register" },
+    { REG, ins_reg,   ext_reg,	 "r", {{ 7,  6}}, 0,		/* R1 */
+      "a general register" },
+    { REG, ins_reg,   ext_reg,	 "r", {{ 7, 13}}, 0,		/* R2 */
+      "a general register" },
+    { REG, ins_reg,   ext_reg,	 "r", {{ 7, 20}}, 0,		/* R3 */
+      "a general register" },
+    { REG, ins_reg,   ext_reg,	 "r", {{ 2, 20}}, 0,		/* R3_2 */
+      "a general register r0-r3" },
+
+    /* indirect operands: */
+    { IND, ins_reg,   ext_reg,	"cpuid", {{7, 20}}, 0,		/* CPUID_R3 */
+      "a cpuid register" },
+    { IND, ins_reg,   ext_reg,	"dbr",   {{7, 20}}, 0,		/* DBR_R3 */
+      "a dbr register" },
+    { IND, ins_reg,   ext_reg,	"dtr",   {{7, 20}}, 0,		/* DTR_R3 */
+      "a dtr register" },
+    { IND, ins_reg,   ext_reg,	"itr",   {{7, 20}}, 0,		/* ITR_R3 */
+      "an itr register" },
+    { IND, ins_reg,   ext_reg,	"ibr",   {{7, 20}}, 0,		/* IBR_R3 */
+      "an ibr register" },
+    { IND, ins_reg,   ext_reg,	"",      {{7, 20}}, 0,		/* MR3 */
+      "an indirect memory address" },
+    { IND, ins_reg,   ext_reg,	"msr",   {{7, 20}}, 0,		/* MSR_R3 */
+      "an msr register" },
+    { IND, ins_reg,   ext_reg,	"pkr",   {{7, 20}}, 0,		/* PKR_R3 */
+      "a pkr register" },
+    { IND, ins_reg,   ext_reg,	"pmc",   {{7, 20}}, 0,		/* PMC_R3 */
+      "a pmc register" },
+    { IND, ins_reg,   ext_reg,	"pmd",   {{7, 20}}, 0,		/* PMD_R3 */
+      "a pmd register" },
+    { IND, ins_reg,   ext_reg,	"rr",    {{7, 20}}, 0,		/* RR_R3 */
+      "an rr register" },
+
+    /* immediate operands: */
+    { ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC,		/* CCNT5 */
+      "a 5-bit count (0-31)" },
+    { ABS, ins_cnt,   ext_cnt,   0, {{ 2, 27 }}, UDEC,		/* CNT2a */
+      "a 2-bit count (1-4)" },
+    { ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC,		/* CNT2b */
+      "a 2-bit count (1-3)" },
+    { ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC,		/* CNT2c */
+      "a count (0, 7, 15, or 16)" },
+    { ABS, ins_immu,  ext_immu,  0, {{ 5, 14}}, UDEC,		/* CNT5 */
+      "a 5-bit count (0-31)" },
+    { ABS, ins_immu,  ext_immu,  0, {{ 6, 27}}, UDEC,		/* CNT6 */
+      "a 6-bit count (0-63)" },
+    { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC,		/* CPOS6a */
+      "a 6-bit bit pos (0-63)" },
+    { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC,		/* CPOS6b */
+      "a 6-bit bit pos (0-63)" },
+    { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC,		/* CPOS6c */
+      "a 6-bit bit pos (0-63)" },
+    { ABS, ins_imms,  ext_imms,  0, {{ 1, 36}}, SDEC,		/* IMM1 */
+      "a 1-bit integer (-1, 0)" },
+    { ABS, ins_immu,  ext_immu,  0, {{ 2, 13}}, UDEC,		/* IMMU2 */
+      "a 2-bit unsigned (0-3)" },
+    { ABS, ins_immu,  ext_immu,  0, {{ 7, 13}}, 0,		/* IMMU7a */
+      "a 7-bit unsigned (0-127)" },
+    { ABS, ins_immu,  ext_immu,  0, {{ 7, 20}}, 0,		/* IMMU7b */
+      "a 7-bit unsigned (0-127)" },
+    { ABS, ins_immu,  ext_immu,  0, {{ 7, 13}}, UDEC,		/* SOF */
+      "a frame size (register count)" },
+    { ABS, ins_immu,  ext_immu,  0, {{ 7, 20}}, UDEC,		/* SOL */
+      "a local register count" },
+    { ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC,		/* SOR */
+      "a rotating register count (integer multiple of 8)" },
+    { ABS, ins_imms,  ext_imms,  0,				/* IMM8 */
+      {{ 7, 13}, { 1, 36}}, SDEC,
+      "an 8-bit integer (-128-127)" },
+    { ABS, ins_immsu4,  ext_imms,  0,				/* IMM8U4 */
+      {{ 7, 13}, { 1, 36}}, SDEC,
+      "an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
+    { ABS, ins_immsm1,  ext_immsm1,  0,				/* IMM8M1 */
+      {{ 7, 13}, { 1, 36}}, SDEC,
+      "an 8-bit integer (-127-128)" },
+    { ABS, ins_immsm1u4,  ext_immsm1,  0,			/* IMM8M1U4 */
+      {{ 7, 13}, { 1, 36}}, SDEC,
+      "an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
+    { ABS, ins_immsm1,  ext_immsm1,  0,				/* IMM8M1U8 */
+      {{ 7, 13}, { 1, 36}}, SDEC,
+      "an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
+    { ABS, ins_immu,  ext_immu,  0, {{ 2, 33}, { 7, 20}}, 0,	/* IMMU9 */
+      "a 9-bit unsigned (0-511)" },
+    { ABS, ins_imms,  ext_imms,  0,				/* IMM9a */
+      {{ 7,  6}, { 1, 27}, { 1, 36}}, SDEC,
+      "a 9-bit integer (-256-255)" },
+    { ABS, ins_imms,  ext_imms, 0,				/* IMM9b */
+      {{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
+      "a 9-bit integer (-256-255)" },
+    { ABS, ins_imms,  ext_imms, 0,				/* IMM14 */
+      {{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
+      "a 14-bit integer (-8192-8191)" },
+    { ABS, ins_imms1, ext_imms1, 0,				/* IMM17 */
+      {{ 7,  6}, { 8, 24}, { 1, 36}}, 0,
+      "a 17-bit integer (-65536-65535)" },
+    { ABS, ins_immu,  ext_immu,  0, {{20,  6}, { 1, 36}}, 0,	/* IMMU21 */
+      "a 21-bit unsigned" },
+    { ABS, ins_imms,  ext_imms,  0,				/* IMM22 */
+      {{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
+      "a 22-bit integer" },
+    { ABS, ins_immu,  ext_immu,  0,				/* IMMU24 */
+      {{21,  6}, { 2, 31}, { 1, 36}}, 0,
+      "a 24-bit unsigned" },
+    { ABS, ins_imms16,ext_imms16,0, {{27,  6}, { 1, 36}}, 0,	/* IMM44 */
+      "a 44-bit unsigned (least 16 bits ignored/zeroes)" },
+    { ABS, ins_rsvd,  ext_rsvd,	0, {{0,  0}}, 0,		/* IMMU62 */
+      "a 62-bit unsigned" },        
+    { ABS, ins_rsvd,  ext_rsvd,	0, {{0,  0}}, 0,		/* IMMU64 */
+      "a 64-bit unsigned" },
+    { ABS, ins_inc3,  ext_inc3,  0, {{ 3, 13}}, SDEC,		/* INC3 */
+      "an increment (+/- 1, 4, 8, or 16)" },
+    { ABS, ins_cnt,   ext_cnt,   0, {{ 4, 27}}, UDEC,		/* LEN4 */
+      "a 4-bit length (1-16)" },
+    { ABS, ins_cnt,   ext_cnt,   0, {{ 6, 27}}, UDEC,		/* LEN6 */
+      "a 6-bit length (1-64)" },
+    { ABS, ins_immu,  ext_immu,  0, {{ 4, 20}},	0,		/* MBTYPE4 */
+      "a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
+    { ABS, ins_immu,  ext_immu,  0, {{ 8, 20}},	0,		/* MBTYPE8 */
+      "an 8-bit mix type" },
+    { ABS, ins_immu,  ext_immu,  0, {{ 6, 14}}, UDEC,		/* POS6 */
+      "a 6-bit bit pos (0-63)" },
+    { REL, ins_imms4, ext_imms4, 0, {{ 7,  6}, { 2, 33}}, 0,	/* TAG13 */
+      "a branch tag" },
+    { REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0,		/* TAG13b */
+      "a branch tag" },
+    { REL, ins_imms4, ext_imms4, 0, {{20,  6}, { 1, 36}}, 0,	/* TGT25 */
+      "a branch target" },
+    { REL, ins_imms4, ext_imms4, 0,				/* TGT25b */
+      {{ 7,  6}, {13, 20}, { 1, 36}}, 0,
+      "a branch target" },
+    { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0,	/* TGT25c */
+      "a branch target" },         
+    { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0,                  /* TGT64  */ 
+      "a branch target" },
+  };
diff --git a/bfd/cpu-ia64.c b/bfd/cpu-ia64.c
new file mode 100644
index 0000000..8069b1a
--- /dev/null
+++ b/bfd/cpu-ia64.c
@@ -0,0 +1,42 @@
+/* BFD support for the ia64 architecture.
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "libbfd.h"
+
+const bfd_arch_info_type bfd_ia64_arch =
+  {
+    64,	/* 64 bits in a word */
+    64,	/* 64 bits in an address */
+    8,	/* 8 bits in a byte */
+    bfd_arch_ia64,
+    0,	/* only 1 machine */
+    "ia64",
+    "ia64",
+    3,	/* log2 of section alignment */
+    true, /* the one and only */
+    bfd_default_compatible, 
+    bfd_default_scan ,
+    0,
+  };
+
+#include "cpu-ia64-opc.c"
diff --git a/bfd/elf.c b/bfd/elf.c
index 8830ff0..82b9b45 100644
--- a/bfd/elf.c
+++ b/bfd/elf.c
@@ -3237,6 +3237,9 @@ prep_headers (abfd)
     case bfd_arch_i386:
       i_ehdrp->e_machine = EM_386;
       break;
+    case bfd_arch_ia64:
+      i_ehdrp->e_machine = EM_IA_64;
+      break;
     case bfd_arch_m68k:
       i_ehdrp->e_machine = EM_68K;
       break;
diff --git a/bfd/elf64-ia64.c b/bfd/elf64-ia64.c
new file mode 100644
index 0000000..c24c91d
--- /dev/null
+++ b/bfd/elf64-ia64.c
@@ -0,0 +1,3696 @@
+/* IA-64 support for 64-bit ELF
+   Copyright 1998, 1999 Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "libbfd.h"
+#include "elf-bfd.h"
+#include "opcode/ia64.h"
+#include "elf/ia64.h"
+
+/*
+ * THE RULES for all the stuff the linker creates --
+ *
+ * GOT		Entries created in response to LTOFF or LTOFF_FPTR
+ *		relocations.  Dynamic relocs created for dynamic
+ *		symbols in an application; REL relocs for locals
+ *		in a shared library.
+ *
+ * FPTR		The canonical function descriptor.  Created for local
+ *		symbols in applications.  Descriptors for dynamic symbols
+ *		and local symbols in shared libraries are created by
+ *		ld.so.  Thus there are no dynamic relocs against these
+ *		objects.  The FPTR relocs for such _are_ passed through
+ *		to the dynamic relocation tables.
+ *
+ * FULL_PLT	Created for a PCREL21B relocation against a dynamic symbol.
+ *		Requires the creation of a PLTOFF entry.  This does not
+ *		require any dynamic relocations.
+ *
+ * PLTOFF	Created by PLTOFF relocations.  For local symbols, this
+ *		is an alternate function descriptor, and in shared libraries
+ *		requires two REL relocations.  Note that this cannot be
+ *		transformed into an FPTR relocation, since it must be in
+ *		range of the GP.  For dynamic symbols, this is a function
+ *		descriptor for a MIN_PLT entry, and requires one IPLT reloc.
+ *
+ * MIN_PLT	Created by PLTOFF entries against dynamic symbols.  This
+ *		does not reqire dynamic relocations.
+ */
+
+#define USE_RELA		/* we want RELA relocs, not REL */
+
+#define NELEMS(a)	((int) (sizeof (a) / sizeof ((a)[0])))
+
+typedef struct bfd_hash_entry *(*new_hash_entry_func)
+  PARAMS ((struct bfd_hash_entry *, struct bfd_hash_table *, const char *));
+
+/* In dynamically (linker-) created sections, we generally need to keep track
+   of the place a symbol or expression got allocated to. This is done via hash
+   tables that store entries of the following type.  */
+
+struct elf64_ia64_dyn_sym_info
+{
+  /* The addend for which this entry is relevant.  */
+  bfd_vma addend;
+
+  /* Next addend in the list.  */
+  struct elf64_ia64_dyn_sym_info *next;
+
+  bfd_vma got_offset;
+  bfd_vma fptr_offset;
+  bfd_vma pltoff_offset;
+  bfd_vma plt_offset;
+  bfd_vma plt2_offset;
+
+  /* The symbol table entry, if any, that this was derrived from.  */
+  struct elf_link_hash_entry *h;
+  
+  /* Used to count non-got, non-plt relocations for delayed sizing
+     of relocation sections.  */
+  struct elf64_ia64_dyn_reloc_entry
+  {
+    struct elf64_ia64_dyn_reloc_entry *next;
+    asection *srel;
+    int type;
+    int count;
+  } *reloc_entries;
+
+  /* True when the section contents have been updated.  */
+  unsigned got_done : 1;
+  unsigned fptr_done : 1;
+  unsigned pltoff_done : 1;
+
+  /* True for the different kinds of linker data we want created.  */
+  unsigned want_got : 1;
+  unsigned want_fptr : 1;
+  unsigned want_ltoff_fptr : 1;
+  unsigned want_plt : 1;
+  unsigned want_plt2 : 1;
+  unsigned want_pltoff : 1;
+};
+
+struct elf64_ia64_local_hash_entry
+{
+  struct bfd_hash_entry root;
+  struct elf64_ia64_dyn_sym_info *info;
+};
+
+struct elf64_ia64_local_hash_table
+{
+  struct bfd_hash_table root;
+  /* No additional fields for now.  */
+};
+
+struct elf64_ia64_link_hash_entry
+{
+  struct elf_link_hash_entry root;
+  struct elf64_ia64_dyn_sym_info *info;
+};
+
+struct elf64_ia64_link_hash_table
+{
+  /* The main hash table */
+  struct elf_link_hash_table root;
+
+  asection *got_sec;		/* the linkage table section (or NULL) */
+  asection *rel_got_sec;	/* dynamic relocation section for same */
+  asection *fptr_sec;		/* function descriptor table (or NULL) */
+  asection *plt_sec;		/* the primary plt section (or NULL) */
+  asection *pltoff_sec;		/* private descriptors for plt (or NULL) */
+  asection *rel_pltoff_sec;	/* dynamic relocation section for same */
+
+  bfd_size_type minplt_entries;	/* number of minplt entries */
+
+  struct elf64_ia64_local_hash_table loc_hash_table;
+};
+
+#define elf64_ia64_hash_table(p) \
+  ((struct elf64_ia64_link_hash_table *) ((p)->hash))
+
+static bfd_reloc_status_type elf64_ia64_reloc
+  PARAMS ((bfd *abfd, arelent *reloc, asymbol *sym, PTR data,
+	   asection *input_section, bfd *output_bfd, char **error_message));
+static reloc_howto_type * lookup_howto
+  PARAMS ((unsigned int rtype));
+static reloc_howto_type *elf64_ia64_reloc_type_lookup
+  PARAMS ((bfd *abfd, bfd_reloc_code_real_type bfd_code));
+static void elf64_ia64_info_to_howto
+  PARAMS ((bfd *abfd, arelent *bfd_reloc, Elf64_Internal_Rela *elf_reloc));
+static boolean elf64_ia64_section_from_shdr
+  PARAMS ((bfd *, Elf64_Internal_Shdr *, char *));
+static boolean elf64_ia64_fake_sections
+  PARAMS ((bfd *abfd, Elf64_Internal_Shdr *hdr, asection *sec));
+static boolean elf64_ia64_add_symbol_hook
+  PARAMS ((bfd *abfd, struct bfd_link_info *info, const Elf_Internal_Sym *sym,
+	   const char **namep, flagword *flagsp, asection **secp,
+	   bfd_vma *valp));
+static int elf64_ia64_additional_program_headers
+  PARAMS ((bfd *abfd));
+static boolean elf64_ia64_is_local_label_name
+  PARAMS ((bfd *abfd, const char *name));
+static boolean elf64_ia64_dynamic_symbol_p
+  PARAMS ((struct elf_link_hash_entry *h, struct bfd_link_info *info));
+static boolean elf64_ia64_local_hash_table_init
+  PARAMS ((struct elf64_ia64_local_hash_table *ht, bfd *abfd,
+	   new_hash_entry_func new));
+static struct bfd_hash_entry *elf64_ia64_new_loc_hash_entry
+  PARAMS ((struct bfd_hash_entry *entry, struct bfd_hash_table *table,
+	   const char *string));
+static struct bfd_hash_entry *elf64_ia64_new_elf_hash_entry
+  PARAMS ((struct bfd_hash_entry *entry, struct bfd_hash_table *table,
+	   const char *string));
+static struct bfd_link_hash_table *elf64_ia64_hash_table_create
+  PARAMS ((bfd *abfd));
+static struct elf64_ia64_local_hash_entry *elf64_ia64_local_hash_lookup
+  PARAMS ((struct elf64_ia64_local_hash_table *table, const char *string,
+	   boolean create, boolean copy));
+static void elf64_ia64_dyn_sym_traverse
+  PARAMS ((struct elf64_ia64_link_hash_table *ia64_info,
+	   boolean (*func)(struct elf64_ia64_dyn_sym_info *, PTR),
+	   PTR info));
+static boolean elf64_ia64_create_dynamic_sections
+  PARAMS ((bfd *abfd, struct bfd_link_info *info));
+static struct elf64_ia64_dyn_sym_info * get_dyn_sym_info
+  PARAMS ((struct elf64_ia64_link_hash_table *ia64_info,
+	   struct elf_link_hash_entry *h,
+	   bfd *abfd, const Elf_Internal_Rela *rel, boolean create));
+static asection *get_got
+  PARAMS ((bfd *abfd, struct bfd_link_info *info,
+	   struct elf64_ia64_link_hash_table *ia64_info));
+static asection *get_fptr
+  PARAMS ((bfd *abfd, struct bfd_link_info *info,
+	   struct elf64_ia64_link_hash_table *ia64_info));
+static asection *get_pltoff
+  PARAMS ((bfd *abfd, struct bfd_link_info *info,
+	   struct elf64_ia64_link_hash_table *ia64_info));
+static asection *get_reloc_section
+  PARAMS ((bfd *abfd, struct elf64_ia64_link_hash_table *ia64_info,
+	   asection *sec, boolean create));
+static boolean count_dyn_reloc
+  PARAMS ((bfd *abfd, struct elf64_ia64_dyn_sym_info *dyn_i,
+	   asection *srel, int type));
+static boolean elf64_ia64_check_relocs
+  PARAMS ((bfd *abfd, struct bfd_link_info *info, asection *sec,
+	   const Elf_Internal_Rela *relocs));
+static boolean elf64_ia64_adjust_dynamic_symbol
+  PARAMS ((struct bfd_link_info *info, struct elf_link_hash_entry *h));
+static unsigned long global_sym_index
+  PARAMS ((struct elf_link_hash_entry *h));
+static boolean allocate_fptr
+  PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean allocate_global_data_got
+  PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean allocate_global_fptr_got
+  PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean allocate_local_got
+  PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean allocate_pltoff_entries
+  PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean allocate_plt_entries
+  PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean allocate_plt2_entries
+  PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean allocate_dynrel_entries
+  PARAMS ((struct elf64_ia64_dyn_sym_info *dyn_i, PTR data));
+static boolean elf64_ia64_size_dynamic_sections
+  PARAMS ((bfd *output_bfd, struct bfd_link_info *info));
+static bfd_reloc_status_type elf64_ia64_install_value
+  PARAMS ((bfd *abfd, bfd_byte *hit_addr, bfd_vma val, unsigned int r_type));
+static void elf64_ia64_install_dyn_reloc
+  PARAMS ((bfd *abfd, struct bfd_link_info *info, asection *sec,
+	   asection *srel, bfd_vma offset, unsigned int type,
+	   long dynindx, bfd_vma addend));
+static bfd_vma set_got_entry
+  PARAMS ((bfd *abfd, struct bfd_link_info *info,
+	   struct elf64_ia64_dyn_sym_info *dyn_i, long dynindx,
+	   bfd_vma addend, bfd_vma value, unsigned int dyn_r_type));
+static bfd_vma set_fptr_entry
+  PARAMS ((bfd *abfd, struct bfd_link_info *info,
+	   struct elf64_ia64_dyn_sym_info *dyn_i,
+	   bfd_vma value));
+static bfd_vma set_pltoff_entry
+  PARAMS ((bfd *abfd, struct bfd_link_info *info,
+	   struct elf64_ia64_dyn_sym_info *dyn_i,
+	   bfd_vma value, boolean));
+static boolean elf64_ia64_final_link
+  PARAMS ((bfd *abfd, struct bfd_link_info *info));
+static boolean elf64_ia64_relocate_section
+  PARAMS ((bfd *output_bfd, struct bfd_link_info *info, bfd *input_bfd,
+	   asection *input_section, bfd_byte *contents,
+	   Elf_Internal_Rela *relocs, Elf_Internal_Sym *local_syms,
+	   asection **local_sections));
+static boolean elf64_ia64_finish_dynamic_symbol
+  PARAMS ((bfd *output_bfd, struct bfd_link_info *info,
+	   struct elf_link_hash_entry *h, Elf_Internal_Sym *sym));
+static boolean elf64_ia64_finish_dynamic_sections
+  PARAMS ((bfd *abfd, struct bfd_link_info *info));
+static boolean elf64_ia64_set_private_flags
+  PARAMS ((bfd *abfd, flagword flags));
+static boolean elf64_ia64_copy_private_bfd_data
+  PARAMS ((bfd *ibfd, bfd *obfd));
+static boolean elf64_ia64_merge_private_bfd_data
+  PARAMS ((bfd *ibfd, bfd *obfd));
+static boolean elf64_ia64_print_private_bfd_data
+  PARAMS ((bfd *abfd, PTR ptr));
+
+
+/* ia64-specific relocation */
+
+/* Perform a relocation.  Not much to do here as all the hard work is
+   done in elf64_ia64_final_link_relocate.  */
+static bfd_reloc_status_type
+elf64_ia64_reloc (abfd, reloc, sym, data, input_section,
+		  output_bfd, error_message)
+     bfd *abfd;
+     arelent *reloc;
+     asymbol *sym;
+     PTR data;
+     asection *input_section;
+     bfd *output_bfd;
+     char **error_message;
+{
+  if (output_bfd)
+    {
+      reloc->address += input_section->output_offset;
+      return bfd_reloc_ok;
+    }
+  *error_message = "Unsupported call to elf64_ia64_reloc";
+  return bfd_reloc_notsupported;
+}
+
+#define IA64_HOWTO(TYPE, NAME, SIZE, PCREL, IN)			\
+  HOWTO (TYPE, 0, SIZE, 0, PCREL, 0, complain_overflow_signed,	\
+	 elf64_ia64_reloc, NAME, false, 0, 0, IN)
+
+/* This table has to be sorted according to increasing number of the
+   TYPE field.  */
+static reloc_howto_type ia64_howto_table[] =
+  {
+    IA64_HOWTO (R_IA64_NONE,	    "NONE",	   0, false, true),
+
+    IA64_HOWTO (R_IA64_IMM14,	    "IMM14",	   0, false, true),
+    IA64_HOWTO (R_IA64_IMM22,	    "IMM22",	   0, false, true),
+    IA64_HOWTO (R_IA64_IMM64,	    "IMM64",	   0, false, true),
+    IA64_HOWTO (R_IA64_DIR32MSB,    "DIR32MSB",	   2, false, true),
+    IA64_HOWTO (R_IA64_DIR32LSB,    "DIR32LSB",	   2, false, true),
+    IA64_HOWTO (R_IA64_DIR64MSB,    "DIR64MSB",	   4, false, true),
+    IA64_HOWTO (R_IA64_DIR64LSB,    "DIR64LSB",	   4, false, true),
+
+    IA64_HOWTO (R_IA64_GPREL22,	    "GPREL22",	   0, false, true),
+    IA64_HOWTO (R_IA64_GPREL64I,    "GPREL64I",	   0, false, true),
+    IA64_HOWTO (R_IA64_GPREL32MSB,  "GPREL32MSB",  2, false, true),
+    IA64_HOWTO (R_IA64_GPREL32LSB,  "GPREL32LSB",  2, false, true),
+    IA64_HOWTO (R_IA64_GPREL64MSB,  "GPREL64MSB",  4, false, true),
+    IA64_HOWTO (R_IA64_GPREL64LSB,  "GPREL64LSB",  4, false, true),
+
+    IA64_HOWTO (R_IA64_LTOFF22,	    "LTOFF22",	   0, false, true),
+    IA64_HOWTO (R_IA64_LTOFF64I,    "LTOFF64I",	   0, false, true),
+
+    IA64_HOWTO (R_IA64_PLTOFF22,    "PLTOFF22",	   0, false, true),
+    IA64_HOWTO (R_IA64_PLTOFF64I,   "PLTOFF64I",   0, false, true),
+    IA64_HOWTO (R_IA64_PLTOFF64MSB, "PLTOFF64MSB", 4, false, true),
+    IA64_HOWTO (R_IA64_PLTOFF64LSB, "PLTOFF64LSB", 4, false, true),
+
+    IA64_HOWTO (R_IA64_FPTR64I,	    "FPTR64I",	   4, false, true),
+    IA64_HOWTO (R_IA64_FPTR32MSB,   "FPTR32MSB",   2, false, true),
+    IA64_HOWTO (R_IA64_FPTR32LSB,   "FPTR32LSB",   2, false, true),
+    IA64_HOWTO (R_IA64_FPTR64MSB,   "FPTR64MSB",   4, false, true),
+    IA64_HOWTO (R_IA64_FPTR64LSB,   "FPTR64LSB",   4, false, true),
+
+    IA64_HOWTO (R_IA64_PCREL21B,    "PCREL21B",	   0, true, true),
+    IA64_HOWTO (R_IA64_PCREL21M,    "PCREL21M",	   0, true, true),
+    IA64_HOWTO (R_IA64_PCREL21F,    "PCREL21F",	   0, true, true),
+    IA64_HOWTO (R_IA64_PCREL32MSB,  "PCREL32MSB",  2, true, true),
+    IA64_HOWTO (R_IA64_PCREL32LSB,  "PCREL32LSB",  2, true, true),
+    IA64_HOWTO (R_IA64_PCREL64MSB,  "PCREL64MSB",  4, true, true),
+    IA64_HOWTO (R_IA64_PCREL64LSB,  "PCREL64LSB",  4, true, true),
+
+    IA64_HOWTO (R_IA64_LTOFF_FPTR22, "LTOFF_FPTR22", 4, false, true),
+    IA64_HOWTO (R_IA64_LTOFF_FPTR64I, "LTOFF_FPTR64I", 4, false, true),
+    IA64_HOWTO (R_IA64_LTOFF_FPTR64MSB, "LTOFF_FPTR64MSB", 4, false, true),
+    IA64_HOWTO (R_IA64_LTOFF_FPTR64LSB, "LTOFF_FPTR64LSB", 4, false, true),
+
+    IA64_HOWTO (R_IA64_SEGBASE,	    "SEGBASE",	   4, false, true),
+    IA64_HOWTO (R_IA64_SEGREL32MSB, "SEGREL32MSB", 2, false, true),
+    IA64_HOWTO (R_IA64_SEGREL32LSB, "SEGREL32LSB", 2, false, true),
+    IA64_HOWTO (R_IA64_SEGREL64MSB, "SEGREL64MSB", 4, false, true),
+    IA64_HOWTO (R_IA64_SEGREL64LSB, "SEGREL64LSB", 4, false, true),
+
+    IA64_HOWTO (R_IA64_SECREL32MSB, "SECREL32MSB", 2, false, true),
+    IA64_HOWTO (R_IA64_SECREL32LSB, "SECREL32LSB", 2, false, true),
+    IA64_HOWTO (R_IA64_SECREL64MSB, "SECREL64MSB", 4, false, true),
+    IA64_HOWTO (R_IA64_SECREL64LSB, "SECREL64LSB", 4, false, true),
+
+    IA64_HOWTO (R_IA64_REL32MSB,    "REL32MSB",	   2, false, true),
+    IA64_HOWTO (R_IA64_REL32LSB,    "REL32LSB",	   2, false, true),
+    IA64_HOWTO (R_IA64_REL64MSB,    "REL64MSB",	   4, false, true),
+    IA64_HOWTO (R_IA64_REL64LSB,    "REL64LSB",	   4, false, true),
+
+    IA64_HOWTO (R_IA64_LTV32MSB,    "LTV32MSB",	   2, false, true),
+    IA64_HOWTO (R_IA64_LTV32LSB,    "LTV32LSB",	   2, false, true),
+    IA64_HOWTO (R_IA64_LTV64MSB,    "LTV64MSB",	   4, false, true),
+    IA64_HOWTO (R_IA64_LTV64LSB,    "LTV64LSB",	   4, false, true),
+
+    IA64_HOWTO (R_IA64_IPLTMSB,	    "IPLTMSB",	   4, false, true),
+    IA64_HOWTO (R_IA64_IPLTLSB,	    "IPLTLSB",	   4, false, true),
+    IA64_HOWTO (R_IA64_EPLTMSB,	    "EPLTMSB",	   4, false, true),
+    IA64_HOWTO (R_IA64_EPLTLSB,	    "EPLTLSB",	   4, false, true),
+    IA64_HOWTO (R_IA64_COPY,	    "COPY",	   4, false, true),
+    IA64_HOWTO (R_IA64_LTOFF22X,    "LTOFF22X",	   0, false, true),
+    IA64_HOWTO (R_IA64_LDXMOV,	    "LDXMOV",	   0, false, true),
+
+    IA64_HOWTO (R_IA64_TPREL22,	    "TPREL22",	   4, false, false),
+    IA64_HOWTO (R_IA64_TPREL64MSB,  "TPREL64MSB",  8, false, false),
+    IA64_HOWTO (R_IA64_TPREL64LSB,  "TPREL64LSB",  8, false, false),
+    IA64_HOWTO (R_IA64_LTOFF_TP22,  "LTOFF_TP22",  4, false, false),
+  };
+
+static unsigned char elf_code_to_howto_index[R_IA64_MAX_RELOC_CODE + 1];
+
+/* Given a BFD reloc type, return the matching HOWTO structure.  */
+
+static reloc_howto_type*
+lookup_howto (rtype)
+     unsigned int rtype;
+{
+  static int inited = 0;
+  int i;
+
+  if (!inited)
+    {
+      inited = 1;
+
+      memset (elf_code_to_howto_index, 0xff, sizeof (elf_code_to_howto_index));
+      for (i = 0; i < NELEMS (ia64_howto_table); ++i)
+	elf_code_to_howto_index[ia64_howto_table[i].type] = i;
+    }
+
+  BFD_ASSERT (rtype <= R_IA64_MAX_RELOC_CODE);
+  i = elf_code_to_howto_index[rtype];
+  if (i >= NELEMS (ia64_howto_table))
+    return 0;
+  return ia64_howto_table + i;
+}
+
+static reloc_howto_type*
+elf64_ia64_reloc_type_lookup (abfd, bfd_code)
+     bfd *abfd;
+     bfd_reloc_code_real_type bfd_code;
+{
+  unsigned int rtype;
+
+  switch (bfd_code)
+    {
+    case BFD_RELOC_NONE:		rtype = R_IA64_NONE; break;
+
+    case BFD_RELOC_IA64_IMM14:		rtype = R_IA64_IMM14; break;
+    case BFD_RELOC_IA64_IMM22:		rtype = R_IA64_IMM22; break;
+    case BFD_RELOC_IA64_IMM64:		rtype = R_IA64_IMM64; break;
+
+    case BFD_RELOC_IA64_DIR32MSB:	rtype = R_IA64_DIR32MSB; break;
+    case BFD_RELOC_IA64_DIR32LSB:	rtype = R_IA64_DIR32LSB; break;
+    case BFD_RELOC_IA64_DIR64MSB:	rtype = R_IA64_DIR64MSB; break;
+    case BFD_RELOC_IA64_DIR64LSB:	rtype = R_IA64_DIR64LSB; break;
+
+    case BFD_RELOC_IA64_GPREL22:	rtype = R_IA64_GPREL22; break;
+    case BFD_RELOC_IA64_GPREL64I:	rtype = R_IA64_GPREL64I; break;
+    case BFD_RELOC_IA64_GPREL32MSB:	rtype = R_IA64_GPREL32MSB; break;
+    case BFD_RELOC_IA64_GPREL32LSB:	rtype = R_IA64_GPREL32LSB; break;
+    case BFD_RELOC_IA64_GPREL64MSB:	rtype = R_IA64_GPREL64MSB; break;
+    case BFD_RELOC_IA64_GPREL64LSB:	rtype = R_IA64_GPREL64LSB; break;
+
+    case BFD_RELOC_IA64_LTOFF22:	rtype = R_IA64_LTOFF22; break;
+    case BFD_RELOC_IA64_LTOFF64I:	rtype = R_IA64_LTOFF64I; break;
+
+    case BFD_RELOC_IA64_PLTOFF22:	rtype = R_IA64_PLTOFF22; break;
+    case BFD_RELOC_IA64_PLTOFF64I:	rtype = R_IA64_PLTOFF64I; break;
+    case BFD_RELOC_IA64_PLTOFF64MSB:	rtype = R_IA64_PLTOFF64MSB; break;
+    case BFD_RELOC_IA64_PLTOFF64LSB:	rtype = R_IA64_PLTOFF64LSB; break;
+    case BFD_RELOC_IA64_FPTR64I:	rtype = R_IA64_FPTR64I; break;
+    case BFD_RELOC_IA64_FPTR32MSB:	rtype = R_IA64_FPTR32MSB; break;
+    case BFD_RELOC_IA64_FPTR32LSB:	rtype = R_IA64_FPTR32LSB; break;
+    case BFD_RELOC_IA64_FPTR64MSB:	rtype = R_IA64_FPTR64MSB; break;
+    case BFD_RELOC_IA64_FPTR64LSB:	rtype = R_IA64_FPTR64LSB; break;
+
+    case BFD_RELOC_IA64_PCREL21B:	rtype = R_IA64_PCREL21B; break;
+    case BFD_RELOC_IA64_PCREL21M:	rtype = R_IA64_PCREL21M; break;
+    case BFD_RELOC_IA64_PCREL21F:	rtype = R_IA64_PCREL21F; break;
+    case BFD_RELOC_IA64_PCREL32MSB:	rtype = R_IA64_PCREL32MSB; break;
+    case BFD_RELOC_IA64_PCREL32LSB:	rtype = R_IA64_PCREL32LSB; break;
+    case BFD_RELOC_IA64_PCREL64MSB:	rtype = R_IA64_PCREL64MSB; break;
+    case BFD_RELOC_IA64_PCREL64LSB:	rtype = R_IA64_PCREL64LSB; break;
+
+    case BFD_RELOC_IA64_LTOFF_FPTR22:	rtype = R_IA64_LTOFF_FPTR22; break;
+    case BFD_RELOC_IA64_LTOFF_FPTR64I:	rtype = R_IA64_LTOFF_FPTR64I; break;
+    case BFD_RELOC_IA64_LTOFF_FPTR64MSB: rtype = R_IA64_LTOFF_FPTR64MSB; break;
+    case BFD_RELOC_IA64_LTOFF_FPTR64LSB: rtype = R_IA64_LTOFF_FPTR64LSB; break;
+
+    case BFD_RELOC_IA64_SEGBASE:	rtype = R_IA64_SEGBASE; break;
+    case BFD_RELOC_IA64_SEGREL32MSB:	rtype = R_IA64_SEGREL32MSB; break;
+    case BFD_RELOC_IA64_SEGREL32LSB:	rtype = R_IA64_SEGREL32LSB; break;
+    case BFD_RELOC_IA64_SEGREL64MSB:	rtype = R_IA64_SEGREL64MSB; break;
+    case BFD_RELOC_IA64_SEGREL64LSB:	rtype = R_IA64_SEGREL64LSB; break;
+
+    case BFD_RELOC_IA64_SECREL32MSB:	rtype = R_IA64_SECREL32MSB; break;
+    case BFD_RELOC_IA64_SECREL32LSB:	rtype = R_IA64_SECREL32LSB; break;
+    case BFD_RELOC_IA64_SECREL64MSB:	rtype = R_IA64_SECREL64MSB; break;
+    case BFD_RELOC_IA64_SECREL64LSB:	rtype = R_IA64_SECREL64LSB; break;
+
+    case BFD_RELOC_IA64_REL32MSB:	rtype = R_IA64_REL32MSB; break;
+    case BFD_RELOC_IA64_REL32LSB:	rtype = R_IA64_REL32LSB; break;
+    case BFD_RELOC_IA64_REL64MSB:	rtype = R_IA64_REL64MSB; break;
+    case BFD_RELOC_IA64_REL64LSB:	rtype = R_IA64_REL64LSB; break;
+
+    case BFD_RELOC_IA64_LTV32MSB:	rtype = R_IA64_LTV32MSB; break;
+    case BFD_RELOC_IA64_LTV32LSB:	rtype = R_IA64_LTV32LSB; break;
+    case BFD_RELOC_IA64_LTV64MSB:	rtype = R_IA64_LTV64MSB; break;
+    case BFD_RELOC_IA64_LTV64LSB:	rtype = R_IA64_LTV64LSB; break;
+
+    case BFD_RELOC_IA64_IPLTMSB:	rtype = R_IA64_IPLTMSB; break;
+    case BFD_RELOC_IA64_IPLTLSB:	rtype = R_IA64_IPLTLSB; break;
+    case BFD_RELOC_IA64_EPLTMSB:	rtype = R_IA64_EPLTMSB; break;
+    case BFD_RELOC_IA64_EPLTLSB:	rtype = R_IA64_EPLTLSB; break;
+    case BFD_RELOC_IA64_COPY:		rtype = R_IA64_COPY; break;
+    case BFD_RELOC_IA64_LTOFF22X:	rtype = R_IA64_LTOFF22X; break;
+    case BFD_RELOC_IA64_LDXMOV:		rtype = R_IA64_LDXMOV; break;
+
+    case BFD_RELOC_IA64_TPREL22:	rtype = R_IA64_TPREL22; break;
+    case BFD_RELOC_IA64_TPREL64MSB:	rtype = R_IA64_TPREL64MSB; break;
+    case BFD_RELOC_IA64_TPREL64LSB:	rtype = R_IA64_TPREL64LSB; break;
+    case BFD_RELOC_IA64_LTOFF_TP22:	rtype = R_IA64_LTOFF_TP22; break;
+
+    default: return 0;
+    }
+  return lookup_howto (rtype);
+}
+
+/* Given a ELF reloc, return the matching HOWTO structure.  */
+
+static void
+elf64_ia64_info_to_howto (abfd, bfd_reloc, elf_reloc)
+     bfd *abfd;
+     arelent *bfd_reloc;
+     Elf64_Internal_Rela *elf_reloc;
+{
+  bfd_reloc->howto = lookup_howto (ELF64_R_TYPE (elf_reloc->r_info));
+}
+
+#define PLT_HEADER_SIZE		(3 * 16)
+#define PLT_MIN_ENTRY_SIZE	(1 * 16)
+#define PLT_FULL_ENTRY_SIZE	(2 * 16)
+#define PLT_RESERVED_WORDS	3
+
+static const bfd_byte plt_header[PLT_HEADER_SIZE] =
+{
+  0x0b, 0x10, 0x00, 0x1c, 0x00, 0x21,  /*   [MMI]       mov r2=r14;;       */
+  0xe0, 0x00, 0x08, 0x00, 0x48, 0x00,  /*               addl r14=0,r2      */
+  0x00, 0x00, 0x04, 0x00,              /*               nop.i 0x0;;        */
+  0x0b, 0x80, 0x20, 0x1c, 0x18, 0x14,  /*   [MMI]       ld8 r16=[r14],8;;  */
+  0x10, 0x41, 0x38, 0x30, 0x28, 0x00,  /*               ld8 r17=[r14],8    */
+  0x00, 0x00, 0x04, 0x00,              /*               nop.i 0x0;;        */
+  0x11, 0x08, 0x00, 0x1c, 0x18, 0x10,  /*   [MIB]       ld8 r1=[r14]       */
+  0x60, 0x88, 0x04, 0x80, 0x03, 0x00,  /*               mov b6=r17         */
+  0x60, 0x00, 0x80, 0x00               /*               br.few b6;;        */
+};
+
+static const bfd_byte plt_min_entry[PLT_MIN_ENTRY_SIZE] =
+{
+  0x11, 0x78, 0x00, 0x00, 0x00, 0x24,  /*   [MIB]       mov r15=0          */
+  0x00, 0x00, 0x00, 0x02, 0x00, 0x00,  /*               nop.i 0x0          */
+  0x00, 0x00, 0x00, 0x40               /*               br.few 0 <PLT0>;;  */
+};
+
+static const bfd_byte plt_full_entry[PLT_FULL_ENTRY_SIZE] =
+{
+  0x0b, 0x78, 0x00, 0x02, 0x00, 0x24,  /*   [MMI]       addl r15=0,r1;;    */
+  0x00, 0x41, 0x3c, 0x30, 0x28, 0xc0,  /*               ld8 r16=[r15],8    */
+  0x01, 0x08, 0x00, 0x84,              /*               mov r14=r1;;       */
+  0x11, 0x08, 0x00, 0x1e, 0x18, 0x10,  /*   [MIB]       ld8 r1=[r15]       */
+  0x60, 0x80, 0x04, 0x80, 0x03, 0x00,  /*               mov b6=r16         */
+  0x60, 0x00, 0x80, 0x00               /*               br.few b6;;        */
+};
+
+#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
+
+/* Handle an IA-64 specific section when reading an object file.  This
+   is called when elfcode.h finds a section with an unknown type.  */
+
+static boolean
+elf64_ia64_section_from_shdr (abfd, hdr, name)
+     bfd *abfd;
+     Elf64_Internal_Shdr *hdr;
+     char *name;
+{
+  asection *newsect;
+
+  /* There ought to be a place to keep ELF backend specific flags, but
+     at the moment there isn't one.  We just keep track of the
+     sections by their name, instead.  Fortunately, the ABI gives
+     suggested names for all the MIPS specific sections, so we will
+     probably get away with this.  */
+  switch (hdr->sh_type)
+    {
+    case SHT_IA_64_UNWIND:
+      if (strcmp (name, ELF_STRING_ia64_unwind) != 0)
+	return false;
+      break;
+
+    case SHT_IA_64_EXT:
+      if (strcmp (name, ELF_STRING_ia64_archext) != 0)
+	return false;
+      break;
+
+    default:
+      return false;
+    }
+
+  if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name))
+    return false;
+  newsect = hdr->bfd_section;
+
+  if (hdr->sh_flags & SHF_IA_64_SHORT)
+    newsect->flags |= SEC_SMALL_DATA;
+
+  return true;
+}
+
+/* Set the correct type for an IA-64 ELF section.  We do this by the
+   section name, which is a hack, but ought to work.  */
+
+static boolean
+elf64_ia64_fake_sections (abfd, hdr, sec)
+     bfd *abfd;
+     Elf64_Internal_Shdr *hdr;
+     asection *sec;
+{
+  register const char *name;
+
+  name = bfd_get_section_name (abfd, sec);
+
+  if (strcmp (name, ELF_STRING_ia64_unwind) == 0)
+    hdr->sh_type = SHT_IA_64_UNWIND;
+  else if (strcmp (name, ELF_STRING_ia64_archext) == 0)
+    hdr->sh_type = SHT_IA_64_EXT;
+  else if (strcmp (name, ".reloc") == 0)
+    /*
+     * This is an ugly, but unfortunately necessary hack that is
+     * needed when producing EFI binaries on IA-64. It tells
+     * elf.c:elf_fake_sections() not to consider ".reloc" as a section
+     * containing ELF relocation info.  We need this hack in order to
+     * be able to generate ELF binaries that can be translated into
+     * EFI applications (which are essentially COFF objects).  Those
+     * files contain a COFF ".reloc" section inside an ELF64 object,
+     * which would normally cause BFD to segfault because it would
+     * attempt to interpret this section as containing relocation
+     * entries for section "oc".  With this hack enabled, ".reloc"
+     * will be treated as a normal data section, which will avoid the
+     * segfault.  However, you won't be able to create an ELF64 binary
+     * with a section named "oc" that needs relocations, but that's
+     * the kind of ugly side-effects you get when detecting section
+     * types based on their names...  In practice, this limitation is
+     * unlikely to bite.
+     */
+    hdr->sh_type = SHT_PROGBITS;
+
+  if (sec->flags & SEC_SMALL_DATA)
+    hdr->sh_flags |= SHF_IA_64_SHORT;
+
+  return true;
+}
+
+/* Hook called by the linker routine which adds symbols from an object
+   file.  We use it to put .comm items in .sbss, and not .bss.  */
+
+static boolean
+elf64_ia64_add_symbol_hook (abfd, info, sym, namep, flagsp, secp, valp)
+     bfd *abfd;
+     struct bfd_link_info *info;
+     const Elf_Internal_Sym *sym;
+     const char **namep;
+     flagword *flagsp;
+     asection **secp;
+     bfd_vma *valp;
+{
+  if (sym->st_shndx == SHN_COMMON
+      && !info->relocateable
+      && sym->st_size <= bfd_get_gp_size (abfd))
+    {
+      /* Common symbols less than or equal to -G nn bytes are
+	 automatically put into .sbss.  */
+
+      asection *scomm = bfd_get_section_by_name (abfd, ".scommon");
+
+      if (scomm == NULL)
+	{
+	  scomm = bfd_make_section (abfd, ".scommon");
+	  if (scomm == NULL
+	      || !bfd_set_section_flags (abfd, scomm, (SEC_ALLOC
+						       | SEC_IS_COMMON
+						       | SEC_LINKER_CREATED)))
+	    return false;
+	}
+
+      *secp = scomm;
+      *valp = sym->st_size;
+    }
+
+  return true;
+}
+
+/* Return the number of additional phdrs we will need.  */
+
+static int
+elf64_ia64_additional_program_headers (abfd)
+     bfd *abfd;
+{
+  asection *s;
+  int ret = 0;
+
+  /* See if we need a PT_IA_64_ARCHEXT segment.  */
+  s = bfd_get_section_by_name (abfd, ELF_STRING_ia64_archext);
+  if (s && (s->flags & SEC_LOAD))
+    ++ret;
+
+  /* See if we need a PT_IA_64_UNWIND segment.  */
+  s = bfd_get_section_by_name (abfd, ELF_STRING_ia64_unwind);
+  if (s && (s->flags & SEC_LOAD))
+    ++ret;
+
+  return ret;
+}
+
+static boolean
+elf64_ia64_modify_segment_map (abfd)
+     bfd *abfd;
+{
+  struct elf_segment_map *m, **pm;
+  asection *s;
+
+  /* If we need a PT_IA_64_ARCHEXT segment, it must come before
+     all PT_LOAD segments.  */
+  s = bfd_get_section_by_name (abfd, ELF_STRING_ia64_archext);
+  if (s && (s->flags & SEC_LOAD))
+    {
+      for (m = elf_tdata (abfd)->segment_map; m != NULL; m = m->next)
+	if (m->p_type == PT_IA_64_ARCHEXT)
+	  break;
+      if (m == NULL)
+	{
+	  m = (struct elf_segment_map *) bfd_zalloc (abfd, sizeof *m);
+	  if (m == NULL)
+	    return false;
+
+	  m->p_type = PT_IA_64_ARCHEXT;
+	  m->count = 1;
+	  m->sections[0] = s;
+
+	  /* We want to put it after the PHDR and INTERP segments.  */
+	  pm = &elf_tdata (abfd)->segment_map;
+	  while (*pm != NULL
+		 && ((*pm)->p_type == PT_PHDR
+		     || (*pm)->p_type == PT_INTERP))
+	    pm = &(*pm)->next;
+
+	  m->next = *pm;
+	  *pm = m;
+	}
+    }
+
+  /* Install the PT_IA_64_UNWIND segment, if needed.  */
+  s = bfd_get_section_by_name (abfd, ELF_STRING_ia64_unwind);
+  if (s && (s->flags & SEC_LOAD))
+    {
+      for (m = elf_tdata (abfd)->segment_map; m != NULL; m = m->next)
+	if (m->p_type == PT_IA_64_UNWIND)
+	  break;
+      if (m == NULL)
+	{
+	  m = (struct elf_segment_map *) bfd_zalloc (abfd, sizeof *m);
+	  if (m == NULL)
+	    return false;
+
+	  m->p_type = PT_IA_64_UNWIND;
+	  m->count = 1;
+	  m->sections[0] = s;
+	  m->next = NULL;
+
+	  /* We want to put it last.  */
+	  pm = &elf_tdata (abfd)->segment_map;
+	  while (*pm != NULL)
+	    pm = &(*pm)->next;
+	  *pm = m;
+	}
+    }
+
+  /* Turn on PF_IA_64_NORECOV if needed.  This involves traversing all of
+     the input sections for each output section in the segment and testing
+     for SHF_IA_64_NORECOV on each.  */
+  for (m = elf_tdata (abfd)->segment_map; m != NULL; m = m->next)
+    if (m->p_type == PT_LOAD)
+      {
+	int i;
+	for (i = m->count - 1; i >= 0; --i)
+	  {
+	    struct bfd_link_order *order = m->sections[i]->link_order_head;
+	    while (order)
+	      {
+		if (order->type == bfd_indirect_link_order)
+		  {
+		    asection *is = order->u.indirect.section;
+		    bfd_vma flags = elf_section_data(is)->this_hdr.sh_flags;
+		    if (flags & SHF_IA_64_NORECOV)
+		      {
+			m->p_flags |= PF_IA_64_NORECOV;
+			goto found;
+		      }
+		  }
+		order = order->next;
+	      }
+	  }
+      found:;
+      }
+
+  return true;
+}
+
+
+/* According to the Tahoe assembler spec, all labels starting with a
+   '.' are local.  */
+
+static boolean
+elf64_ia64_is_local_label_name (abfd, name)
+     bfd *abfd;
+     const char *name;
+{
+  return name[0] == '.';
+}
+
+/* Should we do dynamic things to this symbol?  */
+
+static boolean
+elf64_ia64_dynamic_symbol_p (h, info)
+     struct elf_link_hash_entry *h;
+     struct bfd_link_info *info;
+{
+  if (h == NULL)
+    return false;
+
+  while (h->root.type == bfd_link_hash_indirect
+	 || h->root.type == bfd_link_hash_warning)
+    h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+  if (h->dynindx == -1)
+    return false;
+
+  if (h->root.type == bfd_link_hash_undefweak
+      || h->root.type == bfd_link_hash_defweak)
+    return true;
+
+  if ((info->shared && !info->symbolic)
+      || ((h->elf_link_hash_flags
+	   & (ELF_LINK_HASH_DEF_DYNAMIC | ELF_LINK_HASH_REF_REGULAR))
+	  == (ELF_LINK_HASH_DEF_DYNAMIC | ELF_LINK_HASH_REF_REGULAR)))
+    return true;
+
+  return false;
+}
+
+static boolean
+elf64_ia64_local_hash_table_init (ht, abfd, new)
+     struct elf64_ia64_local_hash_table *ht;
+     bfd *abfd;
+     new_hash_entry_func new;
+{
+  memset (ht, 0, sizeof(*ht));
+  return bfd_hash_table_init (&ht->root, new);
+}
+
+static struct bfd_hash_entry*
+elf64_ia64_new_loc_hash_entry (entry, table, string)
+     struct bfd_hash_entry *entry;
+     struct bfd_hash_table *table;
+     const char *string;
+{
+  struct elf64_ia64_local_hash_entry *ret;
+  ret = (struct elf64_ia64_local_hash_entry *) entry;
+
+  /* Allocate the structure if it has not already been allocated by a
+     subclass.  */
+  if (!ret)
+    ret = bfd_hash_allocate (table, sizeof (*ret));
+
+  if (!ret)
+    return 0;
+
+  /* Initialize our local data.  All zeros, and definitely easier
+     than setting a handful of bit fields.  */
+  memset (ret, 0, sizeof(*ret));
+
+  /* Call the allocation method of the superclass.  */
+  ret = ((struct elf64_ia64_local_hash_entry *)
+	 bfd_hash_newfunc ((struct bfd_hash_entry *) ret, table, string));
+
+  return (struct bfd_hash_entry *) ret;
+}
+
+static struct bfd_hash_entry*
+elf64_ia64_new_elf_hash_entry (entry, table, string)
+     struct bfd_hash_entry *entry;
+     struct bfd_hash_table *table;
+     const char *string;
+{
+  struct elf64_ia64_link_hash_entry *ret;
+  ret = (struct elf64_ia64_link_hash_entry *) entry;
+
+  /* Allocate the structure if it has not already been allocated by a
+     subclass.  */
+  if (!ret)
+    ret = bfd_hash_allocate (table, sizeof (*ret));
+
+  if (!ret)
+    return 0;
+
+  /* Initialize our local data.  All zeros, and definitely easier
+     than setting a handful of bit fields.  */
+  memset (ret, 0, sizeof(*ret));
+
+  /* Call the allocation method of the superclass.  */
+  ret = ((struct elf64_ia64_link_hash_entry *)
+	 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
+				     table, string));
+
+  return (struct bfd_hash_entry *) ret;
+}
+
+static void
+elf64_ia64_hash_copy_indirect (xdir, xind)
+     struct elf_link_hash_entry *xdir, *xind;
+{
+  struct elf64_ia64_link_hash_entry *dir, *ind;
+
+  dir = (struct elf64_ia64_link_hash_entry *)xdir;
+  ind = (struct elf64_ia64_link_hash_entry *)xind;
+
+  /* Copy down any references that we may have already seen to the 
+     symbol which just became indirect.  */
+
+  dir->root.elf_link_hash_flags |=
+    (ind->root.elf_link_hash_flags
+     & (ELF_LINK_HASH_REF_DYNAMIC
+        | ELF_LINK_HASH_REF_REGULAR
+        | ELF_LINK_HASH_REF_REGULAR_NONWEAK));
+
+  /* Copy over the got and plt data.  This would have been done
+     by check_relocs.  */
+
+  if (dir->info == NULL)
+    {
+      struct elf64_ia64_dyn_sym_info *dyn_i;
+
+      dir->info = dyn_i = ind->info;
+      ind->info = NULL;
+
+      /* Fix up the dyn_sym_info pointers to the global symbol.  */
+      for (; dyn_i; dyn_i = dyn_i->next)
+	dyn_i->h = &dir->root;
+    }
+  BFD_ASSERT (ind->info == NULL);
+
+  /* Copy over the dynindx.  */
+
+  if (dir->root.dynindx == -1)
+    {
+      dir->root.dynindx = ind->root.dynindx;
+      dir->root.dynstr_index = ind->root.dynstr_index;
+      ind->root.dynindx = -1;
+      ind->root.dynstr_index = 0;
+    }
+  BFD_ASSERT (ind->root.dynindx == -1);
+}
+
+static void
+elf64_ia64_hash_hide_symbol (xh)
+     struct elf_link_hash_entry *xh;
+{
+  struct elf64_ia64_link_hash_entry *h;
+  struct elf64_ia64_dyn_sym_info *dyn_i;
+
+  h = (struct elf64_ia64_link_hash_entry *)xh;
+
+  h->root.elf_link_hash_flags &= ~ELF_LINK_HASH_NEEDS_PLT;
+  h->root.dynindx = -1;
+
+  for (dyn_i = h->info; dyn_i; dyn_i = dyn_i->next)
+    dyn_i->want_plt2 = 0;
+}
+
+/* Create the derived linker hash table.  The IA-64 ELF port uses this
+   derived hash table to keep information specific to the IA-64 ElF
+   linker (without using static variables).  */
+
+static struct bfd_link_hash_table*
+elf64_ia64_hash_table_create (abfd)
+     bfd *abfd;
+{
+  struct elf64_ia64_link_hash_table *ret;
+
+  ret = bfd_alloc (abfd, sizeof (*ret));
+  if (!ret)
+    return 0;
+  if (!_bfd_elf_link_hash_table_init (&ret->root, abfd,
+				      elf64_ia64_new_elf_hash_entry))
+    {
+      bfd_release (abfd, ret);
+      return 0;
+    }
+
+  if (!elf64_ia64_local_hash_table_init (&ret->loc_hash_table, abfd,
+				         elf64_ia64_new_loc_hash_entry))
+    return 0;
+  return &ret->root.root;
+}
+
+/* Look up an entry in a Alpha ELF linker hash table.  */
+
+static INLINE struct elf64_ia64_local_hash_entry *
+elf64_ia64_local_hash_lookup(table, string, create, copy)
+     struct elf64_ia64_local_hash_table *table;
+     const char *string;
+     boolean create, copy;
+{
+  return ((struct elf64_ia64_local_hash_entry *)
+	  bfd_hash_lookup (&table->root, string, create, copy));
+}
+
+/* Traverse both local and global hash tables.  */
+
+struct elf64_ia64_dyn_sym_traverse_data
+{
+  boolean (*func) PARAMS ((struct elf64_ia64_dyn_sym_info *, PTR));
+  PTR data;
+};
+
+static boolean
+elf64_ia64_global_dyn_sym_thunk (xentry, xdata)
+     struct bfd_hash_entry *xentry;
+     PTR xdata;
+{
+  struct elf64_ia64_link_hash_entry *entry
+    = (struct elf64_ia64_link_hash_entry *) xentry;
+  struct elf64_ia64_dyn_sym_traverse_data *data
+    = (struct elf64_ia64_dyn_sym_traverse_data *) xdata;
+  struct elf64_ia64_dyn_sym_info *dyn_i;
+
+  for (dyn_i = entry->info; dyn_i; dyn_i = dyn_i->next)
+    if (! (*data->func) (dyn_i, data->data))
+      return false;
+  return true;
+}
+
+static boolean
+elf64_ia64_local_dyn_sym_thunk (xentry, xdata)
+     struct bfd_hash_entry *xentry;
+     PTR xdata;
+{
+  struct elf64_ia64_local_hash_entry *entry
+    = (struct elf64_ia64_local_hash_entry *) xentry;
+  struct elf64_ia64_dyn_sym_traverse_data *data
+    = (struct elf64_ia64_dyn_sym_traverse_data *) xdata;
+  struct elf64_ia64_dyn_sym_info *dyn_i;
+
+  for (dyn_i = entry->info; dyn_i; dyn_i = dyn_i->next)
+    if (! (*data->func) (dyn_i, data->data))
+      return false;
+  return true;
+}
+
+static void
+elf64_ia64_dyn_sym_traverse (ia64_info, func, data)
+     struct elf64_ia64_link_hash_table *ia64_info;
+     boolean (*func) PARAMS ((struct elf64_ia64_dyn_sym_info *, PTR));
+     PTR data;
+{
+  struct elf64_ia64_dyn_sym_traverse_data xdata;
+
+  xdata.func = func;
+  xdata.data = data;
+
+  elf_link_hash_traverse (&ia64_info->root,
+			  elf64_ia64_global_dyn_sym_thunk, &xdata);
+  bfd_hash_traverse (&ia64_info->loc_hash_table.root,
+		     elf64_ia64_local_dyn_sym_thunk, &xdata);
+}
+
+static boolean
+elf64_ia64_create_dynamic_sections (abfd, info)
+     bfd *abfd;
+     struct bfd_link_info *info;
+{
+  struct elf64_ia64_link_hash_table *ia64_info;
+  struct elf_link_hash_entry *h;
+  asection *s;
+
+  if (! _bfd_elf_create_dynamic_sections (abfd, info))
+    return false;
+
+  ia64_info = elf64_ia64_hash_table (info);
+
+  ia64_info->plt_sec = bfd_get_section_by_name (abfd, ".plt");
+  ia64_info->got_sec = bfd_get_section_by_name (abfd, ".got");
+
+  {
+    flagword flags = bfd_get_section_flags (abfd, ia64_info->got_sec);
+    bfd_set_section_flags (abfd, ia64_info->got_sec, SEC_SMALL_DATA | flags);
+  }
+
+  if (!get_pltoff (abfd, info, ia64_info))
+    return false;
+
+  s = bfd_make_section(abfd, ".rela.IA_64.pltoff");
+  if (s == NULL
+      || !bfd_set_section_flags (abfd, s, (SEC_ALLOC | SEC_LOAD
+					   | SEC_HAS_CONTENTS
+					   | SEC_IN_MEMORY
+					   | SEC_LINKER_CREATED
+					   | SEC_READONLY))
+      || !bfd_set_section_alignment (abfd, s, 3))
+    return false;
+  ia64_info->rel_pltoff_sec = s;
+
+  s = bfd_make_section(abfd, ".rela.got");
+  if (s == NULL
+      || !bfd_set_section_flags (abfd, s, (SEC_ALLOC | SEC_LOAD
+					   | SEC_HAS_CONTENTS
+					   | SEC_IN_MEMORY
+					   | SEC_LINKER_CREATED
+					   | SEC_READONLY))
+      || !bfd_set_section_alignment (abfd, s, 3))
+    return false;
+  ia64_info->rel_got_sec = s;
+
+  return true;
+}
+
+/* Find and/or create a descriptor for dynamic symbol info.  This will
+   vary based on global or local symbol, and the addend to the reloc.  */
+
+static struct elf64_ia64_dyn_sym_info *
+get_dyn_sym_info (ia64_info, h, abfd, rel, create)
+     struct elf64_ia64_link_hash_table *ia64_info;
+     struct elf_link_hash_entry *h;
+     bfd *abfd;
+     const Elf_Internal_Rela *rel;
+     boolean create;
+{
+  struct elf64_ia64_dyn_sym_info **pp;
+  struct elf64_ia64_dyn_sym_info *dyn_i;
+  bfd_vma addend = rel ? rel->r_addend : 0;
+  
+  if (h)
+    pp = &((struct elf64_ia64_link_hash_entry *)h)->info;
+  else
+    {
+      struct elf64_ia64_local_hash_entry *loc_h;
+      char *addr_name;
+      size_t len;
+
+      /* Construct a string for use in the elf64_ia64_local_hash_table.
+         The name describes what was once anonymous memory.  */
+
+      len = sizeof(void*)*2 + 1 + sizeof(bfd_vma)*4 + 1 + 1;
+      len += 10;	/* %p slop */
+
+      addr_name = alloca (len);
+      sprintf (addr_name, "%p:%lx", abfd, ELF64_R_SYM (rel->r_info));
+
+      /* Collect the canonical entry data for this address.  */
+      loc_h = elf64_ia64_local_hash_lookup (&ia64_info->loc_hash_table,
+					    addr_name, create, create);
+      BFD_ASSERT (loc_h);
+
+      pp = &loc_h->info;
+    }    
+
+  for (dyn_i = *pp; dyn_i && dyn_i->addend != addend; dyn_i = *pp)
+    pp = &dyn_i->next;
+
+  if (dyn_i == NULL && create)
+    {
+      dyn_i = (struct elf64_ia64_dyn_sym_info *)
+	bfd_zalloc (abfd, sizeof *dyn_i);
+      *pp = dyn_i;
+      dyn_i->addend = addend;
+    }
+
+  return dyn_i;
+}
+
+static asection *
+get_got (abfd, info, ia64_info)
+     bfd *abfd;
+     struct bfd_link_info *info;
+     struct elf64_ia64_link_hash_table *ia64_info;
+{
+  asection *got, *srel;
+  bfd *dynobj;
+
+  got = ia64_info->got_sec;
+  if (!got)
+    {
+      flagword flags;
+
+      dynobj = ia64_info->root.dynobj;
+      if (!dynobj)
+	ia64_info->root.dynobj = dynobj = abfd;
+      if (!_bfd_elf_create_got_section (dynobj, info))
+	return 0;
+
+      got = bfd_get_section_by_name (dynobj, ".got");
+      BFD_ASSERT (got);
+      ia64_info->got_sec = got;
+
+      flags = bfd_get_section_flags (abfd, got);
+      bfd_set_section_flags (abfd, got, SEC_SMALL_DATA | flags);
+    }
+
+  return got;
+}
+
+/* Create function descriptor section (.opd).  This section is called .opd
+   because it contains "official prodecure descriptors".  The "official"
+   refers to the fact that these descriptors are used when taking the address
+   of a procedure, thus ensuring a unique address for each procedure.  */
+
+static asection *
+get_fptr (abfd, info, ia64_info)
+     bfd *abfd;
+     struct bfd_link_info *info;
+     struct elf64_ia64_link_hash_table *ia64_info;
+{
+  asection *fptr;
+  bfd *dynobj;
+
+  fptr = ia64_info->fptr_sec;
+  if (!fptr)
+    {
+      dynobj = ia64_info->root.dynobj;
+      if (!dynobj)
+	ia64_info->root.dynobj = dynobj = abfd;
+
+      fptr = bfd_make_section (dynobj, ".opd");
+      if (!fptr
+	  || !bfd_set_section_flags (dynobj, fptr,
+				     (SEC_ALLOC
+				      | SEC_LOAD
+				      | SEC_HAS_CONTENTS
+				      | SEC_IN_MEMORY
+				      | SEC_READONLY
+				      | SEC_LINKER_CREATED))
+	  || !bfd_set_section_alignment (abfd, fptr, 4))
+	{
+	  BFD_ASSERT (0);
+	  return NULL;
+	}
+
+      ia64_info->fptr_sec = fptr;
+    }
+
+  return fptr;
+}
+
+static asection *
+get_pltoff (abfd, info, ia64_info)
+     bfd *abfd;
+     struct bfd_link_info *info;
+     struct elf64_ia64_link_hash_table *ia64_info;
+{
+  asection *pltoff;
+  bfd *dynobj;
+
+  pltoff = ia64_info->pltoff_sec;
+  if (!pltoff)
+    {
+      dynobj = ia64_info->root.dynobj;
+      if (!dynobj)
+	ia64_info->root.dynobj = dynobj = abfd;
+
+      pltoff = bfd_make_section (dynobj, ELF_STRING_ia64_pltoff);
+      if (!pltoff
+	  || !bfd_set_section_flags (dynobj, pltoff,
+				     (SEC_ALLOC
+				      | SEC_LOAD
+				      | SEC_HAS_CONTENTS
+				      | SEC_IN_MEMORY
+				      | SEC_SMALL_DATA
+				      | SEC_LINKER_CREATED))
+	  || !bfd_set_section_alignment (abfd, pltoff, 4))
+	{
+	  BFD_ASSERT (0);
+	  return NULL;
+	}
+
+      ia64_info->pltoff_sec = pltoff;
+    }
+
+  return pltoff;
+}
+
+static asection *
+get_reloc_section (abfd, ia64_info, sec, create)
+     bfd *abfd;
+     struct elf64_ia64_link_hash_table *ia64_info;
+     asection *sec;
+     boolean create;
+{
+  const char *srel_name;
+  asection *srel;
+  bfd *dynobj;
+
+  srel_name = (bfd_elf_string_from_elf_section
+	       (abfd, elf_elfheader(abfd)->e_shstrndx,
+		elf_section_data(sec)->rel_hdr.sh_name));
+  if (srel_name == NULL)
+    return NULL;
+
+  BFD_ASSERT ((strncmp (srel_name, ".rela", 5) == 0
+	       && strcmp (bfd_get_section_name (abfd, sec),
+			  srel_name+5) == 0)
+	      || (strncmp (srel_name, ".rel", 4) == 0
+		  && strcmp (bfd_get_section_name (abfd, sec),
+			     srel_name+4) == 0));
+
+  dynobj = ia64_info->root.dynobj;
+  if (!dynobj)
+    ia64_info->root.dynobj = dynobj = abfd;
+
+  srel = bfd_get_section_by_name (dynobj, srel_name);
+  if (srel == NULL && create)
+    {
+      srel = bfd_make_section (dynobj, srel_name);
+      if (srel == NULL
+	  || !bfd_set_section_flags (dynobj, srel,
+				     (SEC_ALLOC
+				      | SEC_LOAD
+				      | SEC_HAS_CONTENTS
+				      | SEC_IN_MEMORY
+				      | SEC_LINKER_CREATED
+				      | SEC_READONLY))
+	  || !bfd_set_section_alignment (dynobj, srel, 3))
+	return NULL;
+    }
+
+  return srel;
+}
+
+static boolean
+count_dyn_reloc (abfd, dyn_i, srel, type)
+     bfd *abfd;
+     struct elf64_ia64_dyn_sym_info *dyn_i;
+     asection *srel;
+     int type;
+{
+  struct elf64_ia64_dyn_reloc_entry *rent;
+
+  for (rent = dyn_i->reloc_entries; rent; rent = rent->next)
+    if (rent->srel == srel && rent->type == type)
+      break;
+
+  if (!rent)
+    {
+      rent = (struct elf64_ia64_dyn_reloc_entry *)
+	bfd_alloc (abfd, sizeof (*rent));
+      if (!rent)
+	return false;
+
+      rent->next = dyn_i->reloc_entries;
+      rent->srel = srel;
+      rent->type = type;
+      rent->count = 0;
+      dyn_i->reloc_entries = rent;
+    }
+  rent->count++;
+
+  return true;
+}
+
+static boolean
+elf64_ia64_check_relocs (abfd, info, sec, relocs)
+     bfd *abfd;
+     struct bfd_link_info *info;
+     asection *sec;
+     const Elf_Internal_Rela *relocs;
+{
+  struct elf64_ia64_link_hash_table *ia64_info;
+  const Elf_Internal_Rela *relend;
+  Elf_Internal_Shdr *symtab_hdr;
+  const Elf_Internal_Rela *rel;
+  asection *got, *fptr, *srel;
+
+  if (info->relocateable)
+    return true;
+
+  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+  ia64_info = elf64_ia64_hash_table (info);
+
+  got = fptr = srel = NULL;
+
+  relend = relocs + sec->reloc_count;
+  for (rel = relocs; rel < relend; ++rel)
+    {
+      enum {
+	NEED_GOT = 1,
+	NEED_FPTR = 2,
+	NEED_PLTOFF = 4,
+	NEED_MIN_PLT = 8,
+	NEED_FULL_PLT = 16,
+	NEED_DYNREL = 32,
+	NEED_LTOFF_FPTR = 64,
+      };
+
+      struct elf_link_hash_entry *h = NULL;
+      unsigned long r_symndx = ELF64_R_SYM (rel->r_info);
+      struct elf64_ia64_dyn_sym_info *dyn_i;
+      int need_entry;
+      boolean maybe_dynamic;
+      int dynrel_type;
+
+      if (r_symndx >= symtab_hdr->sh_info)
+	{
+	  /* We're dealing with a global symbol -- find its hash entry
+	     and mark it as being referenced.  */
+	  long indx = r_symndx - symtab_hdr->sh_info;
+	  h = elf_sym_hashes (abfd)[indx];
+	  while (h->root.type == bfd_link_hash_indirect
+		 || h->root.type == bfd_link_hash_warning)
+	    h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+	  h->elf_link_hash_flags |= ELF_LINK_HASH_REF_REGULAR;
+	}
+
+      /* We can only get preliminary data on whether a symbol is
+	 locally or externally defined, as not all of the input files
+	 have yet been processed.  Do something with what we know, as
+	 this may help reduce memory usage and processing time later.  */
+      maybe_dynamic = false;
+      if (h && ((info->shared && ! info->symbolic)
+		|| ! (h->elf_link_hash_flags & ELF_LINK_HASH_DEF_REGULAR)
+		|| h->root.type == bfd_link_hash_defweak))
+	maybe_dynamic = true;
+
+      need_entry = 0;
+      switch (ELF64_R_TYPE (rel->r_info))
+	{
+	case R_IA64_TPREL22:
+	case R_IA64_TPREL64MSB:
+	case R_IA64_TPREL64LSB:
+	case R_IA64_LTOFF_TP22:
+	  return false;
+
+	case R_IA64_LTOFF_FPTR22:
+	case R_IA64_LTOFF_FPTR64I:
+	case R_IA64_LTOFF_FPTR64MSB:
+	case R_IA64_LTOFF_FPTR64LSB:
+	  need_entry = NEED_FPTR | NEED_GOT | NEED_LTOFF_FPTR;
+	  break;
+
+	case R_IA64_FPTR64I:
+	case R_IA64_FPTR32MSB:
+	case R_IA64_FPTR32LSB:
+	case R_IA64_FPTR64MSB:
+	case R_IA64_FPTR64LSB:
+	  if (info->shared || h)
+	    need_entry = NEED_FPTR | NEED_DYNREL;
+	  else
+	    need_entry = NEED_FPTR;
+	  dynrel_type = R_IA64_FPTR64LSB;
+	  break;
+
+	case R_IA64_LTOFF22:
+	case R_IA64_LTOFF22X:
+	case R_IA64_LTOFF64I:
+	  need_entry = NEED_GOT;
+	  break;
+
+	case R_IA64_PLTOFF22:
+	case R_IA64_PLTOFF64I:
+	case R_IA64_PLTOFF64MSB:
+	case R_IA64_PLTOFF64LSB:
+	  need_entry = NEED_PLTOFF;
+	  if (h)
+	    {
+	      if (maybe_dynamic)
+		need_entry |= NEED_MIN_PLT;
+	    }
+	  else
+	    {
+	      (*info->callbacks->warning)
+		(info, _("@pltoff reloc against local symbol"), 0,
+		 abfd, 0, 0);
+	    }
+	  break;
+
+	case R_IA64_PCREL21B:
+	  /* Depending on where this symbol is defined, we may or may not
+	     need a full plt entry.  Only skip if we know we'll not need
+	     the entry -- static or symbolic, and the symbol definition
+	     has already been seen.  */
+	  if (maybe_dynamic && rel->r_addend == 0)
+	    need_entry = NEED_FULL_PLT;
+	  break;
+
+	case R_IA64_IMM14:
+	case R_IA64_IMM22:
+	case R_IA64_IMM64:
+	case R_IA64_DIR32MSB:
+	case R_IA64_DIR32LSB:
+	case R_IA64_DIR64MSB:
+	case R_IA64_DIR64LSB:
+	  /* Shared objects will always need at least a REL relocation.  */
+	  if (info->shared || maybe_dynamic)
+	    need_entry = NEED_DYNREL;
+	  dynrel_type = R_IA64_DIR64LSB;
+	  break;
+
+	case R_IA64_PCREL32MSB:
+	case R_IA64_PCREL32LSB:
+	case R_IA64_PCREL64MSB:
+	case R_IA64_PCREL64LSB:
+	  if (maybe_dynamic)
+	    need_entry = NEED_DYNREL;
+	  dynrel_type = R_IA64_PCREL64LSB;
+	  break;
+	}
+
+      if (!need_entry)
+	continue;
+
+      if ((need_entry & NEED_FPTR) != 0
+	  && rel->r_addend)
+	{
+	  (*info->callbacks->warning)
+	    (info, _("non-zero addend in @fptr reloc"), 0,
+	     abfd, 0, 0);
+	}
+
+      dyn_i = get_dyn_sym_info (ia64_info, h, abfd, rel, true);
+
+      /* Record whether or not this is a local symbol.  */
+      dyn_i->h = h;
+
+      /* Create what's needed.  */
+      if (need_entry & NEED_GOT)
+	{
+	  if (!got)
+	    {
+	      got = get_got (abfd, info, ia64_info);
+	      if (!got)
+		return false;
+	    }
+	  dyn_i->want_got = 1;
+	}
+      if (need_entry & NEED_FPTR)
+	{
+	  if (!fptr)
+	    {
+	      fptr = get_fptr (abfd, info, ia64_info);
+	      if (!fptr)
+		return false;
+	    }
+
+	  /* FPTRs for shared libraries are allocated by the dynamic
+	     linker.  Make sure this local symbol will appear in the
+	     dynamic symbol table.  */
+	  if (!h && info->shared)
+	    {
+	      if (! (_bfd_elf64_link_record_local_dynamic_symbol
+		     (info, abfd, r_symndx)))
+		return false;
+	    }
+
+	  dyn_i->want_fptr = 1;
+	}
+      if (need_entry & NEED_LTOFF_FPTR)
+	dyn_i->want_ltoff_fptr = 1;
+      if (need_entry & (NEED_MIN_PLT | NEED_FULL_PLT))
+	{
+          if (!ia64_info->root.dynobj)
+	    ia64_info->root.dynobj = abfd;
+	  h->elf_link_hash_flags |= ELF_LINK_HASH_NEEDS_PLT;
+	  dyn_i->want_plt = 1;
+	}
+      if (need_entry & NEED_FULL_PLT)
+	dyn_i->want_plt2 = 1;
+      if (need_entry & NEED_PLTOFF)
+	dyn_i->want_pltoff = 1;
+      if ((need_entry & NEED_DYNREL) && (sec->flags & SEC_ALLOC))
+	{
+	  if (!srel)
+	    {
+	      srel = get_reloc_section (abfd, ia64_info, sec, true);
+	      if (!srel)
+		return false;
+	    }
+	  if (!count_dyn_reloc (abfd, dyn_i, srel, dynrel_type))
+	    return false;
+	}
+    }
+
+  return true;
+}
+
+struct elf64_ia64_allocate_data
+{
+  struct bfd_link_info *info;
+  bfd_size_type ofs;
+};
+
+/* For cleanliness, and potentially faster dynamic loading, allocate
+   external GOT entries first.  */
+
+static boolean
+allocate_global_data_got (dyn_i, data)
+     struct elf64_ia64_dyn_sym_info *dyn_i;
+     PTR data;
+{
+  struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+
+  if (dyn_i->want_got
+      && ! dyn_i->want_fptr
+      && elf64_ia64_dynamic_symbol_p (dyn_i->h, x->info))
+     {
+       dyn_i->got_offset = x->ofs;
+       x->ofs += 8;
+     }
+  return true;
+}
+
+/* Next, allocate all the GOT entries used by LTOFF_FPTR relocs.  */
+
+static boolean
+allocate_global_fptr_got (dyn_i, data)
+     struct elf64_ia64_dyn_sym_info *dyn_i;
+     PTR data;
+{
+  struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+
+  if (dyn_i->want_got
+      && dyn_i->want_fptr
+      && elf64_ia64_dynamic_symbol_p (dyn_i->h, x->info))
+    {
+      dyn_i->got_offset = x->ofs;
+      x->ofs += 8;
+    }
+  return true;
+}
+
+/* Lastly, allocate all the GOT entries for local data.  */
+
+static boolean
+allocate_local_got (dyn_i, data)
+     struct elf64_ia64_dyn_sym_info *dyn_i;
+     PTR data;
+{
+  struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+
+  if (dyn_i->want_got
+      && ! elf64_ia64_dynamic_symbol_p (dyn_i->h, x->info))
+    {
+      dyn_i->got_offset = x->ofs;
+      x->ofs += 8;
+    }
+  return true;
+}
+
+/* Search for the index of a global symbol in it's defining object file.  */
+
+static unsigned long
+global_sym_index (h)
+     struct elf_link_hash_entry *h;
+{
+  struct elf_link_hash_entry **p;
+  bfd *obj;
+
+  BFD_ASSERT (h->root.type == bfd_link_hash_defined
+	      || h->root.type == bfd_link_hash_defweak);
+
+  obj = h->root.u.def.section->owner;
+  for (p = elf_sym_hashes (obj); *p != h; ++p)
+    continue;
+
+  return p - elf_sym_hashes (obj) + elf_tdata (obj)->symtab_hdr.sh_info;
+}
+
+/* Allocate function descriptors.  We can do these for every function
+   in a main executable that is not exported.  */
+
+static boolean
+allocate_fptr (dyn_i, data)
+     struct elf64_ia64_dyn_sym_info *dyn_i;
+     PTR data;
+{
+  struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+
+  if (dyn_i->want_fptr)
+    {
+      struct elf_link_hash_entry *h = dyn_i->h;
+      
+      if (h)
+	while (h->root.type == bfd_link_hash_indirect
+	       || h->root.type == bfd_link_hash_warning)
+	  h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+      if (x->info->shared)
+	{
+	  if (h && h->dynindx == -1)
+	    {
+	      BFD_ASSERT ((h->root.type == bfd_link_hash_defined)
+			  || (h->root.type == bfd_link_hash_defweak));
+
+	      if (!_bfd_elf64_link_record_local_dynamic_symbol
+		    (x->info, h->root.u.def.section->owner,
+		     global_sym_index (h)))
+		return false;
+	    }
+
+	  dyn_i->want_fptr = 0;
+	}
+      else if (h == NULL || h->dynindx == -1)
+	{
+	  dyn_i->fptr_offset = x->ofs;
+	  x->ofs += 16;
+	}
+      else
+	dyn_i->want_fptr = 0;
+    }
+  return true;
+}
+
+/* Allocate all the minimal PLT entries.  */
+
+static boolean
+allocate_plt_entries (dyn_i, data)
+     struct elf64_ia64_dyn_sym_info *dyn_i;
+     PTR data;
+{
+  struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+
+  if (dyn_i->want_plt)
+    {
+      struct elf_link_hash_entry *h = dyn_i->h;
+
+      if (h)
+	while (h->root.type == bfd_link_hash_indirect
+	       || h->root.type == bfd_link_hash_warning)
+	  h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+      /* ??? Versioned symbols seem to lose ELF_LINK_HASH_NEEDS_PLT.  */
+      if (elf64_ia64_dynamic_symbol_p (h, x->info))
+	{
+	  bfd_size_type offset = x->ofs;
+	  if (offset == 0)
+	    offset = PLT_HEADER_SIZE;
+	  dyn_i->plt_offset = offset;
+	  x->ofs = offset + PLT_MIN_ENTRY_SIZE;
+
+	  dyn_i->want_pltoff = 1;
+	}
+      else
+	{
+	  dyn_i->want_plt = 0;
+	  dyn_i->want_plt2 = 0;
+	}
+    }
+  return true;
+}
+
+/* Allocate all the full PLT entries.  */
+
+static boolean
+allocate_plt2_entries (dyn_i, data)
+     struct elf64_ia64_dyn_sym_info *dyn_i;
+     PTR data;
+{
+  struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+
+  if (dyn_i->want_plt2)
+    {
+      struct elf_link_hash_entry *h = dyn_i->h;
+      bfd_size_type ofs = x->ofs;
+
+      dyn_i->plt2_offset = ofs;
+      x->ofs = ofs + PLT_FULL_ENTRY_SIZE;
+
+      while (h->root.type == bfd_link_hash_indirect
+	     || h->root.type == bfd_link_hash_warning)
+	h = (struct elf_link_hash_entry *) h->root.u.i.link;
+      dyn_i->h->plt.offset = ofs;
+    }
+  return true;
+}
+
+/* Allocate all the PLTOFF entries requested by relocations and
+   plt entries.  We can't share space with allocated FPTR entries,
+   because the latter are not necessarily addressable by the GP.
+   ??? Relaxation might be able to determine that they are.  */
+
+static boolean
+allocate_pltoff_entries (dyn_i, data)
+     struct elf64_ia64_dyn_sym_info *dyn_i;
+     PTR data;
+{
+  struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+
+  if (dyn_i->want_pltoff)
+    {
+      dyn_i->pltoff_offset = x->ofs;
+      x->ofs += 16;
+    }
+  return true;
+}
+
+/* Allocate dynamic relocations for those symbols that turned out
+   to be dynamic.  */
+
+static boolean
+allocate_dynrel_entries (dyn_i, data)
+     struct elf64_ia64_dyn_sym_info *dyn_i;
+     PTR data;
+{
+  struct elf64_ia64_allocate_data *x = (struct elf64_ia64_allocate_data *)data;
+  struct elf64_ia64_link_hash_table *ia64_info;
+  struct elf64_ia64_dyn_reloc_entry *rent;
+  boolean dynamic_symbol, shared;
+
+  ia64_info = elf64_ia64_hash_table (x->info);
+  dynamic_symbol = elf64_ia64_dynamic_symbol_p (dyn_i->h, x->info);
+  shared = x->info->shared;
+
+  /* Take care of the normal data relocations.  */
+
+  for (rent = dyn_i->reloc_entries; rent; rent = rent->next)
+    {
+      switch (rent->type)
+	{
+	case R_IA64_FPTR64LSB:
+	  /* Allocate one iff !want_fptr, which by this point will
+	     be true only if we're actually allocating one statically
+	     in the main executable.  */
+	  if (dyn_i->want_fptr)
+	    continue;
+	  break;
+	case R_IA64_PCREL64LSB:
+	  if (!dynamic_symbol)
+	    continue;
+	  break;
+	case R_IA64_DIR64LSB:
+	  if (!dynamic_symbol && !shared)
+	    continue;
+	  break;
+	}
+      rent->srel->_raw_size += sizeof (Elf64_External_Rela) * rent->count;
+    }
+
+  /* Take care of the GOT and PLT relocations.  */
+
+  if (((dynamic_symbol || shared) && dyn_i->want_got)
+      || (dyn_i->want_ltoff_fptr && dyn_i->h && dyn_i->h->dynindx != -1))
+    ia64_info->rel_got_sec->_raw_size += sizeof (Elf64_External_Rela);
+
+  if (dyn_i->want_pltoff)
+    {
+      bfd_size_type t = 0;
+
+      /* Dynamic symbols get one IPLT relocation.  Local symbols in
+	 shared libraries get two REL relocations.  Local symbols in
+	 main applications get nothing.  */
+      if (dynamic_symbol)
+	t = sizeof (Elf64_External_Rela);
+      else if (shared)
+	t = 2 * sizeof (Elf64_External_Rela);
+
+      ia64_info->rel_pltoff_sec->_raw_size += t;
+    }
+
+  return true;
+}
+
+static boolean
+elf64_ia64_adjust_dynamic_symbol (info, h)
+     struct bfd_link_info *info;
+     struct elf_link_hash_entry *h;
+{
+  /* ??? Undefined symbols with PLT entries should be re-defined
+     to be the PLT entry.  */
+
+  /* If this is a weak symbol, and there is a real definition, the
+     processor independent code will have arranged for us to see the
+     real definition first, and we can just use the same value.  */
+  if (h->weakdef != NULL)
+    {
+      BFD_ASSERT (h->weakdef->root.type == bfd_link_hash_defined
+                  || h->weakdef->root.type == bfd_link_hash_defweak);
+      h->root.u.def.section = h->weakdef->root.u.def.section;
+      h->root.u.def.value = h->weakdef->root.u.def.value;
+      return true;
+    }
+
+  /* If this is a reference to a symbol defined by a dynamic object which
+     is not a function, we might allocate the symbol in our .dynbss section
+     and allocate a COPY dynamic relocation.
+
+     But IA-64 code is canonically PIC, so as a rule we can avoid this sort
+     of hackery.  */
+
+  return true;
+}
+
+static boolean
+elf64_ia64_size_dynamic_sections (output_bfd, info)
+     bfd *output_bfd;
+     struct bfd_link_info *info;
+{
+  struct elf64_ia64_allocate_data data;
+  struct elf64_ia64_link_hash_table *ia64_info;
+  asection *sec;
+  bfd *dynobj;
+  boolean reltext = false;
+  boolean relplt = false;
+
+  dynobj = elf_hash_table(info)->dynobj;
+  ia64_info = elf64_ia64_hash_table (info);
+  BFD_ASSERT(dynobj != NULL);
+  data.info = info;
+
+  /* Set the contents of the .interp section to the interpreter.  */
+  if (ia64_info->root.dynamic_sections_created
+      && !info->shared)
+    {
+      sec = bfd_get_section_by_name (dynobj, ".interp");
+      BFD_ASSERT (sec != NULL);
+      sec->contents = (bfd_byte *) ELF_DYNAMIC_INTERPRETER;
+      sec->_raw_size = strlen (ELF_DYNAMIC_INTERPRETER) + 1;
+    }
+
+  /* DT_INIT and DT_FINI get function descriptors not raw code addresses.
+     Force their symbols to have pltoff entries so we can use those.  */
+  if (ia64_info->root.dynamic_sections_created)
+    {
+      struct elf_link_hash_entry *h;
+      struct elf64_ia64_dyn_sym_info *dyn_i;
+ 
+      if (info->init_function
+	  && (h = elf_link_hash_lookup (elf_hash_table (info), 
+					info->init_function, false,
+					false, false))
+          && (h->elf_link_hash_flags & (ELF_LINK_HASH_REF_REGULAR
+                                        | ELF_LINK_HASH_DEF_REGULAR)) != 0)
+        {
+	  dyn_i = get_dyn_sym_info (ia64_info, h, output_bfd, NULL, true);
+	  dyn_i->want_pltoff = 1;
+        }
+
+      if (info->fini_function
+	  && (h = elf_link_hash_lookup (elf_hash_table (info), 
+					info->fini_function, false,
+					false, false))
+          && (h->elf_link_hash_flags & (ELF_LINK_HASH_REF_REGULAR
+                                        | ELF_LINK_HASH_DEF_REGULAR)) != 0)
+        {
+	  dyn_i = get_dyn_sym_info (ia64_info, h, output_bfd, NULL, true);
+	  dyn_i->want_pltoff = 1;
+        }
+    }
+
+  /* Allocate the GOT entries.  */
+
+  if (ia64_info->got_sec)
+    {
+      data.ofs = 0;
+      elf64_ia64_dyn_sym_traverse (ia64_info, allocate_global_data_got, &data);
+      elf64_ia64_dyn_sym_traverse (ia64_info, allocate_global_fptr_got, &data);
+      elf64_ia64_dyn_sym_traverse (ia64_info, allocate_local_got, &data);
+      ia64_info->got_sec->_raw_size = data.ofs;
+    }
+
+  /* Allocate the FPTR entries.  */
+
+  if (ia64_info->fptr_sec)
+    {
+      data.ofs = 0;
+      elf64_ia64_dyn_sym_traverse (ia64_info, allocate_fptr, &data);
+      ia64_info->fptr_sec->_raw_size = data.ofs;
+    }
+
+  /* Now that we've seen all of the input files, we can decide which
+     symbols need plt entries.  Allocate the minimal PLT entries first.
+     We do this even though dynamic_sections_created may be false, because
+     this has the side-effect of clearing want_plt and want_plt2.  */
+
+  data.ofs = 0;
+  elf64_ia64_dyn_sym_traverse (ia64_info, allocate_plt_entries, &data);
+
+  ia64_info->minplt_entries = 0;
+  if (data.ofs)
+    {
+      ia64_info->minplt_entries
+	= (data.ofs - PLT_HEADER_SIZE) / PLT_MIN_ENTRY_SIZE;
+    }
+
+  /* Align the pointer for the plt2 entries.  */
+  data.ofs = (data.ofs + 31) & -32;
+
+  elf64_ia64_dyn_sym_traverse (ia64_info, allocate_plt2_entries, &data);
+  if (data.ofs != 0)
+    {
+      BFD_ASSERT (ia64_info->root.dynamic_sections_created);
+
+      ia64_info->plt_sec->_raw_size = data.ofs;
+
+      /* If we've got a .plt, we need some extra memory for the dynamic
+	 linker.  We stuff these in .got.plt.  */
+      sec = bfd_get_section_by_name (dynobj, ".got.plt");
+      sec->_raw_size = 8 * PLT_RESERVED_WORDS;
+    }
+
+  /* Allocate the PLTOFF entries.  */
+
+  if (ia64_info->pltoff_sec)
+    {
+      data.ofs = 0;
+      elf64_ia64_dyn_sym_traverse (ia64_info, allocate_pltoff_entries, &data);
+      ia64_info->pltoff_sec->_raw_size = data.ofs;
+    }
+
+  if (ia64_info->root.dynamic_sections_created)
+    {
+      /* Allocate space for the dynamic relocations that turned out to be
+	 required.  */
+
+      elf64_ia64_dyn_sym_traverse (ia64_info, allocate_dynrel_entries, &data);
+    }
+
+  /* We have now determined the sizes of the various dynamic sections.
+     Allocate memory for them.  */
+  for (sec = dynobj->sections; sec != NULL; sec = sec->next)
+    {
+      boolean strip;
+
+      if (!(sec->flags & SEC_LINKER_CREATED))
+	continue;
+
+      /* If we don't need this section, strip it from the output file.
+	 There were several sections primarily related to dynamic
+	 linking that must be create before the linker maps input
+	 sections to output sections.  The linker does that before
+	 bfd_elf_size_dynamic_sections is called, and it is that
+	 function which decides whether anything needs to go into
+	 these sections.  */
+
+      strip = (sec->_raw_size == 0);
+
+      if (sec == ia64_info->got_sec)
+	strip = false;
+      else if (sec == ia64_info->rel_got_sec)
+	{
+	  if (strip)
+	    ia64_info->rel_got_sec = NULL;
+	  else
+	    /* We use the reloc_count field as a counter if we need to
+	       copy relocs into the output file.  */
+	    sec->reloc_count = 0;
+	}
+      else if (sec == ia64_info->fptr_sec)
+	{
+	  if (strip)
+	    ia64_info->fptr_sec = NULL;
+	}
+      else if (sec == ia64_info->plt_sec)
+	{
+	  if (strip)
+	    ia64_info->plt_sec = NULL;
+	}
+      else if (sec == ia64_info->pltoff_sec)
+	{
+	  if (strip)
+	    ia64_info->pltoff_sec = NULL;
+	}
+      else if (sec == ia64_info->rel_pltoff_sec)
+	{
+	  if (strip)
+	    ia64_info->rel_pltoff_sec = NULL;
+	  else
+	    {
+	      relplt = true;
+	      /* We use the reloc_count field as a counter if we need to
+		 copy relocs into the output file.  */
+	      sec->reloc_count = 0;
+	    }
+	}
+      else
+	{
+	  const char *name;
+
+	  /* It's OK to base decisions on the section name, because none
+	     of the dynobj section names depend upon the input files.  */
+	  name = bfd_get_section_name (dynobj, sec);
+
+	  if (strcmp (name, ".got.plt") == 0)
+	    strip = false;
+	  else if (strncmp (name, ".rel", 4) == 0)
+	    {
+	      if (!strip)
+		{
+		  const char *outname;
+		  asection *target;
+
+		  /* If this relocation section applies to a read only
+		     section, then we probably need a DT_TEXTREL entry.  */
+		  outname = bfd_get_section_name (output_bfd,
+						  sec->output_section);
+		  if (outname[4] == 'a')
+		    outname += 5;
+		  else
+		    outname += 4;
+
+		  target = bfd_get_section_by_name (output_bfd, outname);
+		  if (target != NULL
+		      && (target->flags & SEC_READONLY) != 0
+		      && (target->flags & SEC_ALLOC) != 0)
+		    reltext = true;
+
+		  /* We use the reloc_count field as a counter if we need to
+		     copy relocs into the output file.  */
+		  sec->reloc_count = 0;
+		}
+	    }
+	  else
+	    continue;
+	}
+
+      if (strip)
+	_bfd_strip_section_from_output (info, sec);
+      else
+	{
+	  /* Allocate memory for the section contents.  */
+	  sec->contents = (bfd_byte *) bfd_zalloc(dynobj, sec->_raw_size);
+	  if (sec->contents == NULL && sec->_raw_size != 0)
+	    return false;
+	}
+    }
+
+  if (elf_hash_table (info)->dynamic_sections_created)
+    {
+      /* Add some entries to the .dynamic section.  We fill in the values
+	 later (in finish_dynamic_sections) but we must add the entries now
+	 so that we get the correct size for the .dynamic section.  */
+
+      if (!info->shared)
+	{
+	  /* The DT_DEBUG entry is filled in by the dynamic linker and used
+	     by the debugger.  */
+	  if (!bfd_elf64_add_dynamic_entry (info, DT_DEBUG, 0))
+	    return false;
+	}
+
+      if (! bfd_elf64_add_dynamic_entry (info, DT_IA_64_PLT_RESERVE, 0))
+	return false;
+      if (! bfd_elf64_add_dynamic_entry (info, DT_PLTGOT, 0))
+	return false;
+
+      if (relplt)
+	{
+	  if (! bfd_elf64_add_dynamic_entry (info, DT_PLTRELSZ, 0)
+	      || ! bfd_elf64_add_dynamic_entry (info, DT_PLTREL, DT_RELA)
+	      || ! bfd_elf64_add_dynamic_entry (info, DT_JMPREL, 0))
+	    return false;
+	}
+
+      if (! bfd_elf64_add_dynamic_entry (info, DT_RELA, 0)
+	  || ! bfd_elf64_add_dynamic_entry (info, DT_RELASZ, 0)
+	  || ! bfd_elf64_add_dynamic_entry (info, DT_RELAENT,
+					    sizeof(Elf64_External_Rela)))
+	return false;
+
+      if (reltext)
+	{
+	  if (! bfd_elf64_add_dynamic_entry (info, DT_TEXTREL, 0))
+	    return false;
+	}
+    }
+
+  /* ??? Perhaps force __gp local.  */
+
+  return true;
+}
+
+static bfd_reloc_status_type
+elf64_ia64_install_value (abfd, hit_addr, val, r_type)
+     bfd *abfd;
+     bfd_byte *hit_addr;
+     bfd_vma val;
+     unsigned int r_type;
+{
+  const struct ia64_operand *op;
+  int bigendian = 0, shift = 0;
+  bfd_vma t0, t1, insn, dword;
+  enum ia64_opnd opnd;
+  const char *err;
+  size_t size = 8;
+
+  opnd = IA64_OPND_NIL;
+  switch (r_type)
+    {
+    case R_IA64_NONE:
+    case R_IA64_LDXMOV:
+      return bfd_reloc_ok;
+
+      /* Instruction relocations. */
+
+    case R_IA64_IMM14:		opnd = IA64_OPND_IMM14; break;
+    case R_IA64_PCREL21F:	opnd = IA64_OPND_TGT25; break;
+    case R_IA64_PCREL21M:	opnd = IA64_OPND_TGT25b; break;
+    case R_IA64_PCREL21B:	opnd = IA64_OPND_TGT25c; break;
+
+    case R_IA64_IMM22:
+    case R_IA64_GPREL22:
+    case R_IA64_LTOFF22:
+    case R_IA64_LTOFF22X:
+    case R_IA64_PLTOFF22:
+    case R_IA64_LTOFF_FPTR22:
+      opnd = IA64_OPND_IMM22;
+      break;
+
+    case R_IA64_IMM64:
+    case R_IA64_GPREL64I:
+    case R_IA64_LTOFF64I:
+    case R_IA64_PLTOFF64I:
+    case R_IA64_FPTR64I:
+    case R_IA64_LTOFF_FPTR64I:
+      opnd = IA64_OPND_IMMU64;
+      break;
+
+      /* Data relocations.  */
+
+    case R_IA64_DIR32MSB:
+    case R_IA64_GPREL32MSB:
+    case R_IA64_FPTR32MSB:
+    case R_IA64_PCREL32MSB:
+    case R_IA64_SEGREL32MSB:
+    case R_IA64_SECREL32MSB:
+    case R_IA64_LTV32MSB:
+      size = 4; bigendian = 1;
+      break;
+
+    case R_IA64_DIR32LSB:
+    case R_IA64_GPREL32LSB:
+    case R_IA64_FPTR32LSB:
+    case R_IA64_PCREL32LSB:
+    case R_IA64_SEGREL32LSB:
+    case R_IA64_SECREL32LSB:
+    case R_IA64_LTV32LSB:
+      size = 4; bigendian = 0;
+      break;
+
+    case R_IA64_DIR64MSB:
+    case R_IA64_GPREL64MSB:
+    case R_IA64_PLTOFF64MSB:
+    case R_IA64_FPTR64MSB:
+    case R_IA64_PCREL64MSB:
+    case R_IA64_LTOFF_FPTR64MSB:
+    case R_IA64_SEGREL64MSB:
+    case R_IA64_SECREL64MSB:
+    case R_IA64_LTV64MSB:
+      size = 8; bigendian = 1;
+      break;
+
+    case R_IA64_DIR64LSB:
+    case R_IA64_GPREL64LSB:
+    case R_IA64_PLTOFF64LSB:
+    case R_IA64_FPTR64LSB:
+    case R_IA64_PCREL64LSB:
+    case R_IA64_LTOFF_FPTR64LSB:
+    case R_IA64_SEGREL64LSB:
+    case R_IA64_SECREL64LSB:
+    case R_IA64_LTV64LSB:
+      size = 8; bigendian = 0;
+      break;
+
+      /* Unsupported / Dynamic relocations.  */
+
+    case R_IA64_REL32MSB:
+    case R_IA64_REL32LSB:
+    case R_IA64_REL64MSB:
+    case R_IA64_REL64LSB:
+
+    case R_IA64_IPLTMSB:
+    case R_IA64_IPLTLSB:
+    case R_IA64_EPLTMSB:
+    case R_IA64_EPLTLSB:
+    case R_IA64_COPY:
+
+    case R_IA64_SEGBASE:
+
+    case R_IA64_TPREL22:
+    case R_IA64_TPREL64MSB:
+    case R_IA64_TPREL64LSB:
+    case R_IA64_LTOFF_TP22:
+
+    default:
+      return bfd_reloc_notsupported;
+    }
+
+  switch (opnd)
+    {
+    case IA64_OPND_IMMU64:
+      hit_addr -= (long) hit_addr & 0x3;
+      t0 = bfd_get_64 (abfd, hit_addr);
+      t1 = bfd_get_64 (abfd, hit_addr + 8);
+
+      /* tmpl/s: bits  0.. 5 in t0
+	 slot 0: bits  5..45 in t0
+	 slot 1: bits 46..63 in t0, bits 0..22 in t1
+	 slot 2: bits 23..63 in t1 */
+
+      /* First, clear the bits that form the 64 bit constant.  */
+      t0 &= ~(0x3ffffLL << 46);
+      t1 &= ~(0x7fffffLL
+	      | ((  (0x07fLL << 13) | (0x1ffLL << 27)
+		    | (0x01fLL << 22) | (0x001LL << 21)
+		    | (0x001LL << 36)) << 23));
+
+      t0 |= ((val >> 22) & 0x03ffffLL) << 46;		/* 18 lsbs of imm41 */
+      t1 |= ((val >> 40) & 0x7fffffLL) <<  0;		/* 23 msbs of imm41 */
+      t1 |= (  (((val >>  0) & 0x07f) << 13)		/* imm7b */
+	       | (((val >>  7) & 0x1ff) << 27)		/* imm9d */
+	       | (((val >> 16) & 0x01f) << 22)		/* imm5c */
+	       | (((val >> 21) & 0x001) << 21)		/* ic */
+	       | (((val >> 63) & 0x001) << 36)) << 23;	/* i */
+
+      bfd_put_64 (abfd, t0, hit_addr);
+      bfd_put_64 (abfd, t1, hit_addr + 8);
+      break;
+
+    default:
+      switch ((long) hit_addr & 0x3)
+	{
+	case 0: shift =  5; break;
+	case 1: shift = 14; hit_addr += 3; break;
+	case 2: shift = 23; hit_addr += 6; break;
+	case 3: return bfd_reloc_notsupported; /* shouldn't happen... */
+	}
+      dword = bfd_get_64 (abfd, hit_addr);
+      insn = (dword >> shift) & 0x1ffffffffffLL;
+
+      op = elf64_ia64_operands + opnd;
+      err = (*op->insert) (op, val, &insn);
+      if (err)
+	return bfd_reloc_overflow;
+
+      dword &= ~(0x1ffffffffffLL << shift);
+      dword |= (insn << shift);
+      bfd_put_64 (abfd, dword, hit_addr);
+      break;
+
+    case IA64_OPND_NIL:
+      /* A data relocation.  */
+      if (bigendian)
+	if (size == 4)
+	  bfd_putb32 (val, hit_addr);
+	else
+	  bfd_putb64 (val, hit_addr);
+      else
+	if (size == 4)
+	  bfd_putl32 (val, hit_addr);
+	else
+	  bfd_putl64 (val, hit_addr);
+      break;
+    }
+
+  return bfd_reloc_ok;
+}
+
+static void
+elf64_ia64_install_dyn_reloc (abfd, info, sec, srel, offset, type,
+			      dynindx, addend)
+     bfd *abfd;
+     struct bfd_link_info *info;
+     asection *sec;
+     asection *srel;
+     bfd_vma offset;
+     unsigned int type;
+     long dynindx;
+     bfd_vma addend;
+{
+  Elf_Internal_Rela outrel;
+
+  outrel.r_offset = (sec->output_section->vma
+		     + sec->output_offset
+		     + offset);
+
+  BFD_ASSERT (dynindx != -1);
+  outrel.r_info = ELF64_R_INFO (dynindx, type);
+  outrel.r_addend = addend;
+
+  if (elf_section_data (sec)->stab_info != NULL)
+    {
+      /* This may be NULL for linker-generated relocations, as it is
+	 inconvenient to pass all the bits around.  And this shouldn't
+	 happen.  */
+      BFD_ASSERT (info != NULL);
+
+      offset = (_bfd_stab_section_offset
+		(abfd, &elf_hash_table (info)->stab_info, sec,
+		 &elf_section_data (sec)->stab_info, offset));
+      if (offset == (bfd_vma) -1)
+	{
+	  /* Run for the hills.  We shouldn't be outputting a relocation
+	     for this.  So do what everyone else does and output a no-op.  */
+	  outrel.r_info = ELF64_R_INFO (0, R_IA64_NONE);
+	  outrel.r_addend = 0;
+	  offset = 0;
+	}
+      outrel.r_offset = offset;
+    }
+
+  bfd_elf64_swap_reloca_out (abfd, &outrel,
+			     ((Elf64_External_Rela *) srel->contents
+			      + srel->reloc_count++));
+  BFD_ASSERT (sizeof(Elf64_External_Rela) * srel->reloc_count
+	      <= srel->_cooked_size);
+}
+
+/* Store an entry for target address TARGET_ADDR in the linkage table
+   and return the gp-relative address of the linkage table entry.  */
+
+static bfd_vma
+set_got_entry (abfd, info, dyn_i, dynindx, addend, value, dyn_r_type)
+     bfd *abfd;
+     struct bfd_link_info *info;
+     struct elf64_ia64_dyn_sym_info *dyn_i;
+     long dynindx;
+     bfd_vma addend;
+     bfd_vma value;
+     unsigned int dyn_r_type;
+{
+  struct elf64_ia64_link_hash_table *ia64_info;
+  asection *got_sec;
+
+  ia64_info = elf64_ia64_hash_table (info);
+  got_sec = ia64_info->got_sec;
+
+  BFD_ASSERT ((dyn_i->got_offset & 7) == 0);
+
+  if (! dyn_i->got_done)
+    {
+      dyn_i->got_done = true;
+
+      /* Store the target address in the linkage table entry.  */
+      bfd_put_64 (abfd, value, got_sec->contents + dyn_i->got_offset);
+
+      /* Install a dynamic relocation if needed.  */
+      if (info->shared
+          || elf64_ia64_dynamic_symbol_p (dyn_i->h, info)
+	  || (dynindx != -1 && dyn_r_type == R_IA64_FPTR64LSB))
+	{
+	  if (dynindx == -1)
+	    {
+	      dyn_r_type = R_IA64_REL64LSB;
+	      dynindx = 0;
+	      addend = value;
+	    }
+
+	  if (bfd_big_endian (abfd))
+	    {
+	      switch (dyn_r_type)
+		{
+		case R_IA64_REL64LSB:
+		  dyn_r_type = R_IA64_REL64MSB;
+		  break;
+		case R_IA64_DIR64LSB:
+		  dyn_r_type = R_IA64_DIR64MSB;
+		  break;
+		case R_IA64_FPTR64LSB:
+		  dyn_r_type = R_IA64_FPTR64MSB;
+		  break;
+		default:
+		  BFD_ASSERT (false);
+		  break;
+		}
+	    }
+
+	  elf64_ia64_install_dyn_reloc (abfd, NULL, got_sec,
+					ia64_info->rel_got_sec,
+					dyn_i->got_offset, dyn_r_type,
+					dynindx, addend);
+	}
+    }
+
+  /* Return the address of the linkage table entry.  */
+  value = (got_sec->output_section->vma
+	   + got_sec->output_offset
+	   + dyn_i->got_offset);
+
+  return value;
+}
+
+/* Fill in a function descriptor consisting of the function's code
+   address and its global pointer.  Return the descriptor's address.  */
+
+static bfd_vma
+set_fptr_entry (abfd, info, dyn_i, value)
+     bfd *abfd;
+     struct bfd_link_info *info;
+     struct elf64_ia64_dyn_sym_info *dyn_i;
+     bfd_vma value;
+{
+  struct elf64_ia64_link_hash_table *ia64_info;
+  asection *fptr_sec;
+
+  ia64_info = elf64_ia64_hash_table (info);
+  fptr_sec = ia64_info->fptr_sec;
+
+  if (!dyn_i->fptr_done)
+    {
+      dyn_i->fptr_done = 1;
+
+      /* Fill in the function descriptor.  */
+      bfd_put_64 (abfd, value, fptr_sec->contents + dyn_i->fptr_offset);
+      bfd_put_64 (abfd, _bfd_get_gp_value (abfd),
+		  fptr_sec->contents + dyn_i->fptr_offset + 8);
+    }
+
+  /* Return the descriptor's address.  */
+  value = (fptr_sec->output_section->vma
+	   + fptr_sec->output_offset
+	   + dyn_i->fptr_offset);
+
+  return value;
+}
+
+/* Fill in a PLTOFF entry consisting of the function's code address
+   and its global pointer.  Return the descriptor's address.  */
+
+static bfd_vma
+set_pltoff_entry (abfd, info, dyn_i, value, is_plt)
+     bfd *abfd;
+     struct bfd_link_info *info;
+     struct elf64_ia64_dyn_sym_info *dyn_i;
+     bfd_vma value;
+     boolean is_plt;
+{
+  struct elf64_ia64_link_hash_table *ia64_info;
+  asection *pltoff_sec;
+
+  ia64_info = elf64_ia64_hash_table (info);
+  pltoff_sec = ia64_info->pltoff_sec;
+
+  /* Don't do anything if this symbol uses a real PLT entry.  In
+     that case, we'll fill this in during finish_dynamic_symbol.  */
+  if ((! dyn_i->want_plt || is_plt)
+      && !dyn_i->pltoff_done)
+    {
+      /* Fill in the function descriptor.  */
+      bfd_put_64 (abfd, value, pltoff_sec->contents + dyn_i->pltoff_offset);
+      bfd_put_64 (abfd, _bfd_get_gp_value (abfd),
+		  pltoff_sec->contents + dyn_i->pltoff_offset + 8);
+
+      /* Install dynamic relocations if needed.  */
+      if (!is_plt && info->shared)
+	{
+	  unsigned int dyn_r_type;
+
+	  if (bfd_big_endian (abfd))
+	    dyn_r_type = R_IA64_REL64MSB;
+	  else
+	    dyn_r_type = R_IA64_REL64LSB;
+
+	  elf64_ia64_install_dyn_reloc (abfd, NULL, pltoff_sec,
+					ia64_info->rel_pltoff_sec,
+					dyn_i->pltoff_offset,
+					dyn_r_type, 0, 0);
+	  elf64_ia64_install_dyn_reloc (abfd, NULL, pltoff_sec,
+					ia64_info->rel_pltoff_sec,
+					dyn_i->pltoff_offset + 8,
+					dyn_r_type, 0, 0);
+	}
+
+      dyn_i->pltoff_done = 1;
+    }
+
+  /* Return the descriptor's address.  */
+  value = (pltoff_sec->output_section->vma
+	   + pltoff_sec->output_offset
+	   + dyn_i->pltoff_offset);
+
+  return value;
+}
+
+static boolean
+elf64_ia64_final_link (abfd, info)
+     bfd *abfd;
+     struct bfd_link_info *info;
+{
+  struct elf64_ia64_link_hash_table *ia64_info;
+  ia64_info = elf64_ia64_hash_table (info);
+
+  /* Make sure we've got ourselves a nice fat __gp value.  */
+  if (!info->relocateable)
+    {
+      bfd_vma min_vma = (bfd_vma) -1, max_vma = 0;
+      bfd_vma min_short_vma = min_vma, max_short_vma = 0;
+      struct elf_link_hash_entry *gp;
+      bfd_vma gp_val;
+      asection *os;
+
+      /* Find the min and max vma of all sections marked short.  Also
+	 collect min and max vma of any type, for use in selecting a
+	 nice gp.  */
+      for (os = abfd->sections; os ; os = os->next)
+	{
+	  bfd_vma lo, hi;
+
+	  if ((os->flags & SEC_ALLOC) == 0)
+	    continue;
+
+	  lo = os->vma;
+	  hi = os->vma + os->_raw_size;
+	  if (hi < lo)
+	    hi = (bfd_vma) -1;
+
+	  if (min_vma > lo)
+	    min_vma = lo;
+	  if (max_vma < hi)
+	    max_vma = hi;
+	  if (os->flags & SEC_SMALL_DATA)
+	    {
+	      if (min_short_vma > lo)
+		min_short_vma = lo;
+	      if (max_short_vma < hi)
+		max_short_vma = hi;
+	    }
+	}
+
+      /* See if the user wants to force a value.  */
+      gp = elf_link_hash_lookup (elf_hash_table (info), "__gp", false,
+				 false, false);
+
+      if (gp
+	  && (gp->root.type == bfd_link_hash_defined
+	      || gp->root.type == bfd_link_hash_defweak))
+	{
+	  asection *gp_sec = gp->root.u.def.section;
+	  gp_val = (gp->root.u.def.value
+		    + gp_sec->output_section->vma
+		    + gp_sec->output_offset);
+	}
+      else
+	{
+	  /* Pick a sensible value.  */
+
+	  asection *got_sec = ia64_info->got_sec;
+
+	  /* Start with just the address of the .got.  */
+	  if (got_sec)
+	    gp_val = got_sec->output_section->vma;
+	  else if (max_short_vma != 0)
+	    gp_val = min_short_vma;
+	  else
+	    gp_val = min_vma;
+
+	  /* If it is possible to address the entire image, but we
+	     don't with the choice above, adjust.  */
+	  if (max_vma - min_vma < 0x400000
+	      && max_vma - gp_val <= 0x200000
+	      && gp_val - min_vma > 0x200000)
+	    gp_val = min_vma + 0x200000;
+	  else if (max_short_vma != 0)
+	    {
+	      /* If we don't cover all the short data, adjust.  */
+	      if (max_short_vma - gp_val >= 0x200000)
+		gp_val = min_short_vma + 0x200000;
+
+	      /* If we're addressing stuff past the end, adjust back.  */
+	      if (gp_val > max_vma)
+		gp_val = max_vma - 0x200000 + 8;
+	    }
+	}
+
+      /* Validate whether all SHF_IA_64_SHORT sections are within
+	 range of the chosen GP.  */
+
+      if (max_short_vma != 0)
+	{
+	  if (max_short_vma - min_short_vma >= 0x400000)
+	    {
+	      (*_bfd_error_handler)
+		(_("%s: short data segment overflowed (0x%lx >= 0x400000)"),
+		 bfd_get_filename (abfd),
+		 (unsigned long)(max_short_vma - min_short_vma));
+	      return false;
+	    }
+	  else if ((gp_val > min_short_vma
+		    && gp_val - min_short_vma > 0x200000)
+		   || (gp_val < max_short_vma
+		       && max_short_vma - gp_val >= 0x200000))
+	    {
+	      (*_bfd_error_handler)
+		(_("%s: __gp does not cover short data segment"),
+		 bfd_get_filename (abfd));
+	      return false;
+	    }
+	}
+
+      _bfd_set_gp_value (abfd, gp_val);
+    }
+
+  /* Tricky bits.  DT_INIT and DT_FINI use a pltoff entry, which is
+     normally initialized in finish_dynamic_sections.  Except that
+     we need all non-plt pltoff entries to be initialized before
+     finish_dynamic_symbols.  This because the array of relocations
+     used for plt entries (aka DT_JMPREL) begins after all the 
+     non-plt pltoff relocations.  If the order gets confused, we
+     munge either the array or the array base.  */
+  if (ia64_info->root.dynamic_sections_created)
+    {
+      struct elf_link_hash_entry *h;
+      struct elf64_ia64_dyn_sym_info *dyn_i;
+      bfd_vma addr;
+ 
+      if (info->init_function
+	  && (h = elf_link_hash_lookup (elf_hash_table (info), 
+					info->init_function, false,
+					false, false))
+          && (h->elf_link_hash_flags & (ELF_LINK_HASH_REF_REGULAR
+                                        | ELF_LINK_HASH_DEF_REGULAR)) != 0)
+        {
+	  dyn_i = get_dyn_sym_info (ia64_info, h, NULL, NULL, false);
+	  addr = (h->root.u.def.section->output_section->vma
+		  + h->root.u.def.section->output_offset
+		  + h->root.u.def.value);
+	  (void) set_pltoff_entry (abfd, info, dyn_i, addr, false);
+        }
+
+      if (info->fini_function
+	  && (h = elf_link_hash_lookup (elf_hash_table (info), 
+					info->fini_function, false,
+					false, false))
+          && (h->elf_link_hash_flags & (ELF_LINK_HASH_REF_REGULAR
+                                        | ELF_LINK_HASH_DEF_REGULAR)) != 0)
+        {
+	  dyn_i = get_dyn_sym_info (ia64_info, h, NULL, NULL, false);
+	  addr = (h->root.u.def.section->output_section->vma
+		  + h->root.u.def.section->output_offset
+		  + h->root.u.def.value);
+	  (void) set_pltoff_entry (abfd, info, dyn_i, addr, false);
+        }
+    }
+
+  /* Invoke the regular ELF backend linker to do all the work.  */
+  return bfd_elf64_bfd_final_link (abfd, info);
+}
+
+static boolean
+elf64_ia64_relocate_section (output_bfd, info, input_bfd, input_section,
+			     contents, relocs, local_syms, local_sections)
+     bfd *output_bfd;
+     struct bfd_link_info *info;
+     bfd *input_bfd;
+     asection *input_section;
+     bfd_byte *contents;
+     Elf_Internal_Rela *relocs;
+     Elf_Internal_Sym *local_syms;
+     asection **local_sections;
+{
+  struct elf64_ia64_link_hash_table *ia64_info;
+  Elf_Internal_Shdr *symtab_hdr;
+  Elf_Internal_Rela *rel;
+  Elf_Internal_Rela *relend;
+  asection *srel;
+  boolean ret_val = true;	/* for non-fatal errors */
+  bfd_vma gp_val;
+
+  symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
+  ia64_info = elf64_ia64_hash_table (info);
+
+  /* Infect various flags from the input section to the output section.  */
+  if (info->relocateable)
+    {
+      bfd_vma flags;
+
+      flags = elf_section_data(input_section)->this_hdr.sh_flags;
+      flags &= SHF_IA_64_NORECOV;
+
+      elf_section_data(input_section->output_section)
+	->this_hdr.sh_flags |= flags;
+    }
+
+  gp_val = _bfd_get_gp_value (output_bfd);
+  srel = get_reloc_section (input_bfd, ia64_info, input_section, false);
+
+  rel = relocs;
+  relend = relocs + input_section->reloc_count;
+  for (; rel < relend; ++rel)
+    {
+      struct elf_link_hash_entry *h;
+      struct elf64_ia64_dyn_sym_info *dyn_i;
+      bfd_reloc_status_type r;
+      reloc_howto_type *howto;
+      unsigned long r_symndx;
+      Elf_Internal_Sym *sym;
+      unsigned int r_type;
+      bfd_vma value;
+      asection *sym_sec;
+      bfd_byte *hit_addr;
+      boolean dynamic_symbol_p;
+      boolean undef_weak_ref;
+
+      r_type = ELF64_R_TYPE (rel->r_info);
+      if (r_type > R_IA64_MAX_RELOC_CODE)
+	{
+	  (*_bfd_error_handler)
+	    (_("%s: unknown relocation type %d"),
+	     bfd_get_filename (input_bfd), (int)r_type);
+	  bfd_set_error (bfd_error_bad_value);
+	  ret_val = false;
+	  continue;
+	}
+      howto = lookup_howto (r_type);
+      r_symndx = ELF64_R_SYM (rel->r_info);
+
+      if (info->relocateable)
+	{
+	  /* This is a relocateable link.  We don't have to change
+	     anything, unless the reloc is against a section symbol,
+	     in which case we have to adjust according to where the
+	     section symbol winds up in the output section.  */
+	  if (r_symndx < symtab_hdr->sh_info)
+	    {
+	      sym = local_syms + r_symndx;
+	      if (ELF_ST_TYPE (sym->st_info) == STT_SECTION)
+		{
+		  sym_sec = local_sections[r_symndx];
+		  rel->r_addend += sym_sec->output_offset;
+		}
+	    }
+	  continue;
+	}
+
+      /* This is a final link.  */
+
+      h = NULL;
+      sym = NULL;
+      sym_sec = NULL;
+      undef_weak_ref = false;
+
+      if (r_symndx < symtab_hdr->sh_info)
+	{
+	  /* Reloc against local symbol.  */
+	  sym = local_syms + r_symndx;
+	  sym_sec = local_sections[r_symndx];
+	  value  = (sym_sec->output_section->vma
+		    + sym_sec->output_offset
+		    + sym->st_value);
+	}
+      else
+	{
+	  long indx;
+
+	  /* Reloc against global symbol.  */
+	  indx = r_symndx - symtab_hdr->sh_info;
+	  h = elf_sym_hashes (input_bfd)[indx];
+	  while (h->root.type == bfd_link_hash_indirect
+		 || h->root.type == bfd_link_hash_warning)
+	    h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+	  value = 0;
+	  if (h->root.type == bfd_link_hash_defined
+	      || h->root.type == bfd_link_hash_defweak)
+	    {
+	      sym_sec = h->root.u.def.section;
+
+	      /* Detect the cases that sym_sec->output_section is
+		 expected to be NULL -- all cases in which the symbol
+		 is defined in another shared module.  This includes
+		 PLT relocs for which we've created a PLT entry and
+		 other relocs for which we're prepared to create
+		 dynamic relocations.  */
+	      /* ??? Just accept it NULL and continue.  */
+
+	      if (sym_sec->output_section != NULL)
+		{
+		  value = (h->root.u.def.value
+			   + sym_sec->output_section->vma
+			   + sym_sec->output_offset);
+		}
+	    }
+	  else if (h->root.type == bfd_link_hash_undefweak)
+	    undef_weak_ref = true;
+	  else if (info->shared && !info->symbolic && !info->no_undefined)
+	    ;
+	  else
+	    {
+	      if (! ((*info->callbacks->undefined_symbol)
+		     (info, h->root.root.string, input_bfd,
+		      input_section, rel->r_offset,
+		      (!info->shared || info->no_undefined))))
+		return false;
+	      ret_val = false;
+	      continue;
+	    }
+	}
+
+      hit_addr = contents + rel->r_offset;
+      value += rel->r_addend;
+      dynamic_symbol_p = elf64_ia64_dynamic_symbol_p (h, info);
+
+      switch (r_type)
+	{
+	case R_IA64_NONE:
+	case R_IA64_LDXMOV:
+	  continue;
+
+	case R_IA64_IMM14:
+	case R_IA64_IMM22:
+	case R_IA64_IMM64:
+	case R_IA64_DIR32MSB:
+	case R_IA64_DIR32LSB:
+	case R_IA64_DIR64MSB:
+	case R_IA64_DIR64LSB:
+	  /* Install a dynamic relocation for this reloc.  */
+	  if ((dynamic_symbol_p || info->shared)
+	      && (input_section->flags & SEC_ALLOC) != 0)
+	    {
+	      unsigned int dyn_r_type;
+	      long dynindx;
+
+	      BFD_ASSERT (srel != NULL);
+
+	      /* If we don't need dynamic symbol lookup, find a
+		 matching RELATIVE relocation.  */
+	      dyn_r_type = r_type;
+	      if (dynamic_symbol_p)
+		dynindx = h->dynindx;
+	      else
+		{
+		  switch (r_type)
+		    {
+		    case R_IA64_DIR32MSB:
+		      dyn_r_type = R_IA64_REL32MSB;
+		      break;
+		    case R_IA64_DIR32LSB:
+		      dyn_r_type = R_IA64_REL32LSB;
+		      break;
+		    case R_IA64_DIR64MSB:
+		      dyn_r_type = R_IA64_REL64MSB;
+		      break;
+		    case R_IA64_DIR64LSB:
+		      dyn_r_type = R_IA64_REL64LSB;
+		      break;
+
+		    default:
+		      /* We can't represent this without a dynamic symbol.
+			 Adjust the relocation to be against an output
+			 section symbol, which are always present in the
+			 dynamic symbol table.  */
+		      /* ??? People shouldn't be doing non-pic code in
+			 shared libraries.  Hork.  */
+		      (*_bfd_error_handler)
+			(_("%s: linking non-pic code in a shared library"),
+			 bfd_get_filename (input_bfd));
+		      ret_val = false;
+		      continue;
+		    }
+		  dynindx = 0;
+		}
+
+	      elf64_ia64_install_dyn_reloc (output_bfd, info, input_section,
+					    srel, rel->r_offset, dyn_r_type,
+					    dynindx, rel->r_addend);
+	    }
+	  /* FALLTHRU */
+
+	case R_IA64_LTV32MSB:
+	case R_IA64_LTV32LSB:
+	case R_IA64_LTV64MSB:
+	case R_IA64_LTV64LSB:
+	  r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+	  break;
+
+	case R_IA64_GPREL22:
+	case R_IA64_GPREL64I:
+	case R_IA64_GPREL32MSB:
+	case R_IA64_GPREL32LSB:
+	case R_IA64_GPREL64MSB:
+	case R_IA64_GPREL64LSB:
+	  if (dynamic_symbol_p)
+	    {
+	      (*_bfd_error_handler)
+		(_("%s: @gprel relocation against dynamic symbol %s"),
+		 bfd_get_filename (input_bfd), h->root.root.string);
+	      ret_val = false;
+	      continue;
+	    }
+	  value -= gp_val;
+	  r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+	  break;
+
+	case R_IA64_LTOFF22:
+	case R_IA64_LTOFF22X:
+	case R_IA64_LTOFF64I:
+          dyn_i = get_dyn_sym_info (ia64_info, h, input_bfd, rel, false);
+	  value = set_got_entry (input_bfd, info, dyn_i, (h ? h->dynindx : -1),
+				 rel->r_addend, value, R_IA64_DIR64LSB);
+	  value -= gp_val;
+	  r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+	  break;
+
+	case R_IA64_PLTOFF22:
+	case R_IA64_PLTOFF64I:
+	case R_IA64_PLTOFF64MSB:
+	case R_IA64_PLTOFF64LSB:
+          dyn_i = get_dyn_sym_info (ia64_info, h, input_bfd, rel, false);
+	  value = set_pltoff_entry (output_bfd, info, dyn_i, value, false);
+	  value -= gp_val;
+	  r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+	  break;
+
+	case R_IA64_FPTR64I:
+	case R_IA64_FPTR32MSB:
+	case R_IA64_FPTR32LSB:
+	case R_IA64_FPTR64MSB:
+	case R_IA64_FPTR64LSB:
+          dyn_i = get_dyn_sym_info (ia64_info, h, input_bfd, rel, false);
+	  if (dyn_i->want_fptr)
+	    {
+	      if (!undef_weak_ref)
+		value = set_fptr_entry (output_bfd, info, dyn_i, value);
+	    }
+	  else
+	    {
+	      long dynindx;
+
+	      /* Otherwise, we expect the dynamic linker to create
+		 the entry.  */
+
+	      if (h)
+		{
+		  if (h->dynindx != -1)
+		    dynindx = h->dynindx;
+		  else
+		    dynindx = (_bfd_elf_link_lookup_local_dynindx
+			       (info, h->root.u.def.section->owner,
+				global_sym_index (h)));
+		}
+	      else
+		{
+		  dynindx = (_bfd_elf_link_lookup_local_dynindx
+			     (info, input_bfd, r_symndx));
+		}
+
+	      elf64_ia64_install_dyn_reloc (output_bfd, info, input_section,
+					    srel, rel->r_offset, r_type,
+					    dynindx, rel->r_addend);
+	      value = 0;
+	    }
+
+	  r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+	  break;
+
+	case R_IA64_LTOFF_FPTR22:
+	case R_IA64_LTOFF_FPTR64I:
+	case R_IA64_LTOFF_FPTR64MSB:
+	case R_IA64_LTOFF_FPTR64LSB:
+	  {
+	    long dynindx;
+
+	    dyn_i = get_dyn_sym_info (ia64_info, h, input_bfd, rel, false);
+	    if (dyn_i->want_fptr)
+	      {
+		BFD_ASSERT (h == NULL || h->dynindx == -1)
+	        if (!undef_weak_ref)
+	          value = set_fptr_entry (output_bfd, info, dyn_i, value);
+		dynindx = -1;
+	      }
+	    else
+	      {
+	        /* Otherwise, we expect the dynamic linker to create
+		   the entry.  */
+	        if (h)
+		  {
+		    if (h->dynindx != -1)
+		      dynindx = h->dynindx;
+		    else
+		      dynindx = (_bfd_elf_link_lookup_local_dynindx
+				 (info, h->root.u.def.section->owner,
+				  global_sym_index (h)));
+		  }
+		else
+		  dynindx = (_bfd_elf_link_lookup_local_dynindx
+			     (info, input_bfd, r_symndx));
+		value = 0;
+	      }
+
+	    value = set_got_entry (output_bfd, info, dyn_i, dynindx,
+				   rel->r_addend, value, R_IA64_FPTR64LSB);
+	    value -= gp_val;
+	    r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+	  }
+	  break;
+
+	case R_IA64_PCREL32MSB:
+	case R_IA64_PCREL32LSB:
+	case R_IA64_PCREL64MSB:
+	case R_IA64_PCREL64LSB:
+	  /* Install a dynamic relocation for this reloc.  */
+	  if (dynamic_symbol_p)
+	    {
+	      BFD_ASSERT (srel != NULL);
+
+	      elf64_ia64_install_dyn_reloc (output_bfd, info, input_section,
+					    srel, rel->r_offset, r_type,
+					    h->dynindx, rel->r_addend);
+	    }
+	  goto finish_pcrel;
+
+	case R_IA64_PCREL21F:
+	case R_IA64_PCREL21M:
+	  /* ??? These two are only used for speculation fixup code.
+	     They should never be dynamic.  */
+	  if (dynamic_symbol_p)
+	    {
+	      (*_bfd_error_handler)
+		(_("%s: dynamic relocation against speculation fixup"),
+		 bfd_get_filename (input_bfd));
+	      ret_val = false;
+	      continue;
+	    }
+	  if (undef_weak_ref)
+	    {
+	      (*_bfd_error_handler)
+		(_("%s: speculation fixup against undefined weak symbol"),
+		 bfd_get_filename (input_bfd));
+	      ret_val = false;
+	      continue;
+	    }
+	  goto finish_pcrel;
+
+	case R_IA64_PCREL21B:
+	  /* We should have created a PLT entry for any dynamic symbol.  */
+	  /* ??? How to handle out of range branches, which are supposed
+	     to be fixed up by a conforming linker.  */
+
+	  dyn_i = NULL;
+	  if (h)
+	    dyn_i = get_dyn_sym_info (ia64_info, h, NULL, NULL, false);
+
+	  if (dyn_i && dyn_i->want_plt2)
+	    {
+	      /* Should have caught this earlier.  */
+	      BFD_ASSERT (rel->r_addend == 0);
+
+	      value = (ia64_info->plt_sec->output_section->vma
+		       + ia64_info->plt_sec->output_offset
+		       + dyn_i->plt2_offset);
+	    }
+	  else
+	    {
+	      /* Since there's no PLT entry, Validate that this is
+		 locally defined.  */
+	      BFD_ASSERT (undef_weak_ref || sym_sec->output_section != NULL);
+
+	      /* If the symbol is undef_weak, we shouldn't be trying
+		 to call it.  There's every chance that we'd wind up
+		 with an out-of-range fixup here.  Don't bother setting
+		 any value at all.  */
+	      if (undef_weak_ref)
+		continue;
+	    }
+	  goto finish_pcrel;
+
+	finish_pcrel:
+	  /* Make pc-relative.  */
+	  value -= (input_section->output_section->vma
+		    + input_section->output_offset
+		    + rel->r_offset) & ~ (bfd_vma) 0x3;
+	  r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+	  break;
+
+	case R_IA64_SEGREL32MSB:
+	case R_IA64_SEGREL32LSB:
+	case R_IA64_SEGREL64MSB:
+	case R_IA64_SEGREL64LSB:
+	  {
+	    struct elf_segment_map *m;
+	    Elf_Internal_Phdr *p;
+
+	    /* Find the segment that contains the output_section.  */
+	    for (m = elf_tdata (output_bfd)->segment_map,
+		   p = elf_tdata (output_bfd)->phdr;
+		 m != NULL;
+		 m = m->next, p++)
+	      {
+		int i;
+		for (i = m->count - 1; i >= 0; i--)
+		  if (m->sections[i] == sym_sec->output_section)
+		    break;
+		if (i >= 0)
+		  break;
+	      }
+
+	    if (m == NULL)
+	      {
+		/* If the input section was discarded from the output, then
+		   do nothing.  */
+
+		if (bfd_is_abs_section (sym_sec->output_section))
+		  r = bfd_reloc_ok;
+		else
+		  r = bfd_reloc_notsupported;
+	      }
+	    else
+	      {
+		/* The VMA of the segment is the vaddr of the associated
+		   program header.  */
+		if (value > p->p_vaddr)
+		  value -= p->p_vaddr;
+		else
+		  value = 0;
+		r = elf64_ia64_install_value (output_bfd, hit_addr, value,
+					      r_type);
+	      }
+	    break;
+	  }
+
+	case R_IA64_SECREL32MSB:
+	case R_IA64_SECREL32LSB:
+	case R_IA64_SECREL64MSB:
+	case R_IA64_SECREL64LSB:
+	  /* Make output-section relative.  */
+	  if (value > input_section->output_section->vma)
+	    value -= input_section->output_section->vma;
+	  else
+	    value = 0;
+	  r = elf64_ia64_install_value (output_bfd, hit_addr, value, r_type);
+	  break;
+
+	case R_IA64_SEGBASE:
+
+	case R_IA64_REL32MSB:
+	case R_IA64_REL32LSB:
+	case R_IA64_REL64MSB:
+	case R_IA64_REL64LSB:
+
+	case R_IA64_IPLTMSB:
+	case R_IA64_IPLTLSB:
+	case R_IA64_EPLTMSB:
+	case R_IA64_EPLTLSB:
+	case R_IA64_COPY:
+
+	case R_IA64_TPREL22:
+	case R_IA64_TPREL64MSB:
+	case R_IA64_TPREL64LSB:
+	case R_IA64_LTOFF_TP22:
+	default:
+	  r = bfd_reloc_notsupported;
+	  break;
+	}
+
+      switch (r)
+	{
+	case bfd_reloc_ok:
+	  break;
+
+	case bfd_reloc_undefined:
+	  /* This can happen for global table relative relocs if
+	     __gp is undefined.  This is a panic situation so we
+	     don't try to continue.  */
+	  (*info->callbacks->undefined_symbol)
+	    (info, "__gp", input_bfd, input_section, rel->r_offset, 1);
+	  return false;
+
+	case bfd_reloc_notsupported:
+	  {
+	    const char *name;
+
+	    if (h)
+	      name = h->root.root.string;
+	    else
+	      {
+		name = bfd_elf_string_from_elf_section (input_bfd,
+							symtab_hdr->sh_link,
+							sym->st_name);
+		if (name == NULL)
+		  return false;
+		if (*name == '\0')
+		  name = bfd_section_name (input_bfd, input_section);
+	      }
+	    if (!(*info->callbacks->warning) (info, _("unsupported reloc"),
+					      name, input_bfd,
+					      input_section, rel->r_offset))
+	      return false;
+	    ret_val = false;
+	  }
+	  break;
+
+	case bfd_reloc_dangerous:
+	case bfd_reloc_outofrange:
+	case bfd_reloc_overflow:
+	default:
+	  {
+	    const char *name;
+
+	    if (h)
+	      name = h->root.root.string;
+	    else
+	      {
+		name = bfd_elf_string_from_elf_section (input_bfd,
+							symtab_hdr->sh_link,
+							sym->st_name);
+		if (name == NULL)
+		  return false;
+		if (*name == '\0')
+		  name = bfd_section_name (input_bfd, input_section);
+	      }
+	    if (!(*info->callbacks->reloc_overflow) (info, name,
+						     howto->name, 0,
+						     input_bfd,
+						     input_section,
+						     rel->r_offset))
+	      return false;
+	    ret_val = false;
+	  }
+	  break;
+	}
+    }
+
+  return ret_val;
+}
+
+static boolean
+elf64_ia64_finish_dynamic_symbol (output_bfd, info, h, sym)
+     bfd *output_bfd;
+     struct bfd_link_info *info;
+     struct elf_link_hash_entry *h;
+     Elf_Internal_Sym *sym;
+{
+  struct elf64_ia64_link_hash_table *ia64_info;
+  struct elf64_ia64_dyn_sym_info *dyn_i;
+
+  ia64_info = elf64_ia64_hash_table (info);
+  dyn_i = get_dyn_sym_info (ia64_info, h, NULL, NULL, false);
+
+  /* Fill in the PLT data, if required.  */
+  if (dyn_i && dyn_i->want_plt)
+    {
+      Elf_Internal_Rela outrel;
+      bfd_byte *loc;
+      asection *plt_sec;
+      bfd_vma plt_addr, pltoff_addr, gp_val, index;
+      Elf64_External_Rela *rel;
+
+      gp_val = _bfd_get_gp_value (output_bfd);
+
+      /* Initialize the minimal PLT entry.  */
+
+      index = (dyn_i->plt_offset - PLT_HEADER_SIZE) / PLT_MIN_ENTRY_SIZE;
+      plt_sec = ia64_info->plt_sec;
+      loc = plt_sec->contents + dyn_i->plt_offset;
+
+      memcpy (loc, plt_min_entry, PLT_MIN_ENTRY_SIZE);
+      elf64_ia64_install_value (output_bfd, loc, index, R_IA64_IMM22);
+      elf64_ia64_install_value (output_bfd, loc+2, -dyn_i->plt_offset,
+				R_IA64_PCREL21B);
+
+      plt_addr = (plt_sec->output_section->vma
+		  + plt_sec->output_offset
+		  + dyn_i->plt_offset);
+      pltoff_addr = set_pltoff_entry (output_bfd, info, dyn_i, plt_addr, true);
+
+      /* Initialize the FULL PLT entry, if needed.  */
+      if (dyn_i->want_plt2)
+	{
+	  loc = plt_sec->contents + dyn_i->plt2_offset;
+
+	  memcpy (loc, plt_full_entry, PLT_FULL_ENTRY_SIZE);
+	  elf64_ia64_install_value (output_bfd, loc, pltoff_addr - gp_val,
+				    R_IA64_IMM22);
+
+	  /* Mark the symbol as undefined, rather than as defined in the
+	     plt section.  Leave the value alone.  */
+	  /* ??? We didn't redefine it in adjust_dynamic_symbol in the
+	     first place.  But perhaps elflink.h did some for us.  */
+	  if ((h->elf_link_hash_flags & ELF_LINK_HASH_DEF_REGULAR) == 0)
+	    sym->st_shndx = SHN_UNDEF;
+	}
+
+      /* Create the dynamic relocation.  */
+      outrel.r_offset = pltoff_addr;
+      if (bfd_little_endian (output_bfd))
+	outrel.r_info = ELF64_R_INFO (h->dynindx, R_IA64_IPLTLSB);
+      else
+	outrel.r_info = ELF64_R_INFO (h->dynindx, R_IA64_IPLTMSB);
+      outrel.r_addend = 0;
+
+      /* This is fun.  In the .IA_64.pltoff section, we've got entries
+	 that correspond both to real PLT entries, and those that
+	 happened to resolve to local symbols but need to be created
+	 to satisfy @pltoff relocations.  The .rela.IA_64.pltoff
+	 relocations for the real PLT should come at the end of the
+	 section, so that they can be indexed by plt entry at runtime.
+
+	 We emitted all of the relocations for the non-PLT @pltoff
+	 entries during relocate_section.  So we can consider the
+	 existing sec->reloc_count to be the base of the array of
+	 PLT relocations.  */
+
+      rel = (Elf64_External_Rela *)ia64_info->rel_pltoff_sec->contents;
+      rel += ia64_info->rel_pltoff_sec->reloc_count;
+
+      bfd_elf64_swap_reloca_out (output_bfd, &outrel, rel + index);
+    }
+
+  /* Mark some specially defined symbols as absolute.  */
+  if (strcmp (h->root.root.string, "_DYNAMIC") == 0
+      || strcmp (h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0
+      || strcmp (h->root.root.string, "_PROCEDURE_LINKAGE_TABLE_") == 0)
+    sym->st_shndx = SHN_ABS;
+
+  return true;
+}
+
+static boolean
+elf64_ia64_finish_dynamic_sections (abfd, info)
+     bfd *abfd;
+     struct bfd_link_info *info;
+{
+  struct elf64_ia64_link_hash_table *ia64_info;
+  bfd *dynobj;
+
+  ia64_info = elf64_ia64_hash_table (info);
+  dynobj = ia64_info->root.dynobj;
+
+  if (elf_hash_table (info)->dynamic_sections_created)
+    {
+      Elf64_External_Dyn *dyncon, *dynconend;
+      asection *sdyn, *sgotplt;
+      bfd_vma gp_val;
+
+      sdyn = bfd_get_section_by_name (dynobj, ".dynamic");
+      sgotplt = bfd_get_section_by_name (dynobj, ".got.plt");
+      BFD_ASSERT (sdyn != NULL);
+      dyncon = (Elf64_External_Dyn *) sdyn->contents;
+      dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->_raw_size);
+
+      gp_val = _bfd_get_gp_value (abfd);
+
+      for (; dyncon < dynconend; dyncon++)
+	{
+	  Elf_Internal_Dyn dyn;
+	  const char *name;
+	  asection *s;
+
+	  bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn);
+
+	  switch (dyn.d_tag)
+	    {
+	    case DT_PLTGOT:
+	      dyn.d_un.d_ptr = gp_val;
+	      break;
+
+	    case DT_PLTRELSZ:
+	      dyn.d_un.d_val = (ia64_info->minplt_entries
+				* sizeof (Elf64_External_Rela));
+	      break;
+
+	    case DT_JMPREL:
+	      /* See the comment above in finish_dynamic_symbol.  */
+	      dyn.d_un.d_ptr = (ia64_info->rel_pltoff_sec->output_section->vma
+				+ ia64_info->rel_pltoff_sec->output_offset
+				+ (ia64_info->rel_pltoff_sec->reloc_count
+				   * sizeof (Elf64_External_Rela)));
+	      break;
+
+	    case DT_IA_64_PLT_RESERVE:
+	      dyn.d_un.d_ptr = (sgotplt->output_section->vma
+				+ sgotplt->output_offset);
+	      break;
+
+	    case DT_RELASZ:
+	      /* Do not have RELASZ include JMPREL.  This makes things
+		 easier on ld.so.  This is not what the rest of BFD set up. */
+	      dyn.d_un.d_val -= (ia64_info->minplt_entries
+				 * sizeof (Elf64_External_Rela));
+	      break;
+
+	    case DT_INIT:
+	    case DT_FINI:
+	      {
+		struct elf_link_hash_entry *h;
+		struct elf64_ia64_dyn_sym_info *dyn_i;
+		const char *which;
+ 
+		if (dyn.d_tag == DT_INIT)
+		  which = info->init_function;
+		else
+		  which = info->fini_function;
+
+		h = elf_link_hash_lookup (elf_hash_table (info), which,
+					  false, false, false);
+		dyn_i = get_dyn_sym_info (ia64_info, h, NULL, NULL, false);
+		dyn.d_un.d_ptr = set_pltoff_entry (abfd, info, dyn_i,
+						   dyn.d_un.d_ptr, 0);
+	      }
+	    }
+
+	  bfd_elf64_swap_dyn_out (abfd, &dyn, dyncon);
+	}
+
+      /* Initialize the PLT0 entry */
+      if (ia64_info->plt_sec)
+	{
+	  bfd_byte *loc = ia64_info->plt_sec->contents;
+	  bfd_vma pltres;
+
+	  memcpy (loc, plt_header, PLT_HEADER_SIZE);
+
+	  pltres = (sgotplt->output_section->vma
+		    + sgotplt->output_offset
+		    - gp_val);
+
+	  elf64_ia64_install_value (abfd, loc+1, pltres, R_IA64_GPREL22);
+	}
+    }
+
+  return true;
+}
+
+/* ELF file flag handling: */
+
+/* Function to keep IA-64 specific file flags. */
+static boolean
+elf64_ia64_set_private_flags (abfd, flags)
+     bfd *abfd;
+     flagword flags;
+{
+  BFD_ASSERT (!elf_flags_init (abfd)
+	      || elf_elfheader (abfd)->e_flags == flags);
+
+  elf_elfheader (abfd)->e_flags = flags;
+  elf_flags_init (abfd) = true;
+  return true;
+}
+
+/* Copy backend specific data from one object module to another */
+static boolean
+elf64_ia64_copy_private_bfd_data (ibfd, obfd)
+     bfd *ibfd, *obfd;
+{
+  if (   bfd_get_flavour (ibfd) != bfd_target_elf_flavour
+      || bfd_get_flavour (obfd) != bfd_target_elf_flavour)
+    return true;
+
+  BFD_ASSERT (!elf_flags_init (obfd)
+	      || (elf_elfheader (obfd)->e_flags
+		  == elf_elfheader (ibfd)->e_flags));
+
+  elf_elfheader (obfd)->e_flags = elf_elfheader (ibfd)->e_flags;
+  elf_flags_init (obfd) = true;
+  return true;
+}
+
+/* Merge backend specific data from an object file to the output
+   object file when linking.  */
+static boolean
+elf64_ia64_merge_private_bfd_data (ibfd, obfd)
+     bfd *ibfd, *obfd;
+{
+  flagword out_flags;
+  flagword in_flags;
+  boolean ok = true;
+
+  /* Don't even pretend to support mixed-format linking.  */
+  if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour
+      || bfd_get_flavour (obfd) != bfd_target_elf_flavour)
+    return false;
+
+  in_flags  = elf_elfheader (ibfd)->e_flags;
+  out_flags = elf_elfheader (obfd)->e_flags;
+
+  if (! elf_flags_init (obfd))
+    {
+      elf_flags_init (obfd) = true;
+      elf_elfheader (obfd)->e_flags = in_flags;
+
+      if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
+	  && bfd_get_arch_info (obfd)->the_default)
+	{
+	  return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd),
+				    bfd_get_mach (ibfd));
+	}
+
+      return true;
+    }
+
+  /* Check flag compatibility.  */
+  if (in_flags == out_flags)
+    return true;
+
+  if ((in_flags & EF_IA_64_TRAPNIL) != (out_flags & EF_IA_64_TRAPNIL))
+    {
+      (*_bfd_error_handler)
+	(_("%s: linking trap-on-NULL-dereference with non-trapping files"),
+	 bfd_get_filename (ibfd));
+
+      bfd_set_error (bfd_error_bad_value);
+      ok = false;
+    }
+  if ((in_flags & EF_IA_64_BE) != (out_flags & EF_IA_64_BE))
+    {
+      (*_bfd_error_handler)
+	(_("%s: linking big-endian files with little-endian files"),
+	 bfd_get_filename (ibfd));
+
+      bfd_set_error (bfd_error_bad_value);
+      ok = false;
+    }
+  if ((in_flags & EF_IA_64_ABI64) != (out_flags & EF_IA_64_ABI64))
+    {
+      (*_bfd_error_handler)
+	(_("%s: linking 64-bit files with 32-bit files"),
+	 bfd_get_filename (ibfd));
+
+      bfd_set_error (bfd_error_bad_value);
+      ok = false;
+    }
+
+  return ok;
+}
+
+static boolean
+elf64_ia64_print_private_bfd_data (abfd, ptr)
+     bfd *abfd;
+     PTR ptr;
+{
+  FILE *file = (FILE *) ptr;
+  flagword flags = elf_elfheader (abfd)->e_flags;
+
+  BFD_ASSERT (abfd != NULL && ptr != NULL);
+
+  fprintf (file, "private flags = %s%s%s%s\n",
+	   (flags & EF_IA_64_TRAPNIL) ? "TRAPNIL, " : "",
+	   (flags & EF_IA_64_EXT) ? "EXT, " : "",
+	   (flags & EF_IA_64_BE) ? "BE, " : "LE, ",
+	   (flags & EF_IA_64_ABI64) ? "ABI64" : "ABI32");
+  _bfd_elf_print_private_bfd_data (abfd, ptr);
+  return true;
+}
+
+#define TARGET_LITTLE_SYM		bfd_elf64_ia64_little_vec
+#define TARGET_LITTLE_NAME		"elf64-ia64-little"
+#define TARGET_BIG_SYM			bfd_elf64_ia64_big_vec
+#define TARGET_BIG_NAME			"elf64-ia64-big"
+#define ELF_ARCH			bfd_arch_ia64
+#define ELF_MACHINE_CODE		EM_IA_64
+#define ELF_MACHINE_ALT1		1999	/* EAS2.3 */
+#define ELF_MACHINE_ALT2		1998	/* EAS2.2 */
+#define ELF_MAXPAGESIZE			0x10000	/* 64KB */
+
+#define elf_backend_section_from_shdr \
+	elf64_ia64_section_from_shdr
+#define elf_backend_fake_sections \
+	elf64_ia64_fake_sections
+#define elf_backend_add_symbol_hook \
+	elf64_ia64_add_symbol_hook
+#define elf_backend_additional_program_headers \
+	elf64_ia64_additional_program_headers
+#define elf_backend_modify_segment_map \
+	elf64_ia64_modify_segment_map
+#define elf_info_to_howto \
+	elf64_ia64_info_to_howto
+
+#define bfd_elf64_bfd_reloc_type_lookup \
+	elf64_ia64_reloc_type_lookup
+#define bfd_elf64_bfd_is_local_label_name \
+	elf64_ia64_is_local_label_name
+
+/* Stuff for the BFD linker: */
+#define bfd_elf64_bfd_link_hash_table_create \
+	elf64_ia64_hash_table_create
+#define elf_backend_create_dynamic_sections \
+	elf64_ia64_create_dynamic_sections
+#define elf_backend_check_relocs \
+	elf64_ia64_check_relocs
+#define elf_backend_adjust_dynamic_symbol \
+	elf64_ia64_adjust_dynamic_symbol
+#define elf_backend_size_dynamic_sections \
+	elf64_ia64_size_dynamic_sections
+#define elf_backend_relocate_section \
+	elf64_ia64_relocate_section
+#define elf_backend_finish_dynamic_symbol \
+	elf64_ia64_finish_dynamic_symbol
+#define elf_backend_finish_dynamic_sections \
+	elf64_ia64_finish_dynamic_sections
+#define bfd_elf64_bfd_final_link \
+	elf64_ia64_final_link
+
+#define bfd_elf64_bfd_copy_private_bfd_data \
+	elf64_ia64_copy_private_bfd_data
+#define bfd_elf64_bfd_merge_private_bfd_data \
+	elf64_ia64_merge_private_bfd_data
+#define bfd_elf64_bfd_set_private_flags \
+	elf64_ia64_set_private_flags
+#define bfd_elf64_bfd_print_private_bfd_data \
+	elf64_ia64_print_private_bfd_data
+
+#define elf_backend_plt_readonly	1
+#define elf_backend_want_plt_sym	0
+#define elf_backend_plt_alignment	5
+#define elf_backend_got_header_size	0
+#define elf_backend_plt_header_size	PLT_HEADER_SIZE
+#define elf_backend_want_got_plt	1
+#define elf_backend_may_use_rel_p	1
+#define elf_backend_may_use_rela_p	1
+#define elf_backend_default_use_rela_p	1
+#define elf_backend_want_dynbss		0
+#define elf_backend_copy_indirect_symbol elf64_ia64_hash_copy_indirect
+#define elf_backend_hide_symbol		elf64_ia64_hash_hide_symbol
+
+#include "elf64-target.h"
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 20ffcdc..8aef81b 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -898,6 +898,69 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_AVR_CALL",
   "BFD_RELOC_VTABLE_INHERIT",
   "BFD_RELOC_VTABLE_ENTRY",
+  "BFD_RELOC_IA64_IMM14",
+  "BFD_RELOC_IA64_IMM22",
+  "BFD_RELOC_IA64_IMM64",
+  "BFD_RELOC_IA64_DIR32MSB",
+  "BFD_RELOC_IA64_DIR32LSB",
+  "BFD_RELOC_IA64_DIR64MSB",
+  "BFD_RELOC_IA64_DIR64LSB",
+  "BFD_RELOC_IA64_GPREL22",
+  "BFD_RELOC_IA64_GPREL64I",
+  "BFD_RELOC_IA64_GPREL32MSB",
+  "BFD_RELOC_IA64_GPREL32LSB",
+  "BFD_RELOC_IA64_GPREL64MSB",
+  "BFD_RELOC_IA64_GPREL64LSB",
+  "BFD_RELOC_IA64_LTOFF22",
+  "BFD_RELOC_IA64_LTOFF64I",
+  "BFD_RELOC_IA64_PLTOFF22",
+  "BFD_RELOC_IA64_PLTOFF64I",
+  "BFD_RELOC_IA64_PLTOFF64MSB",
+  "BFD_RELOC_IA64_PLTOFF64LSB",
+  "BFD_RELOC_IA64_FPTR64I",
+  "BFD_RELOC_IA64_FPTR32MSB",
+  "BFD_RELOC_IA64_FPTR32LSB",
+  "BFD_RELOC_IA64_FPTR64MSB",
+  "BFD_RELOC_IA64_FPTR64LSB",
+  "BFD_RELOC_IA64_PCREL21B",
+  "BFD_RELOC_IA64_PCREL21M",
+  "BFD_RELOC_IA64_PCREL21F",
+  "BFD_RELOC_IA64_PCREL32MSB",
+  "BFD_RELOC_IA64_PCREL32LSB",
+  "BFD_RELOC_IA64_PCREL64MSB",
+  "BFD_RELOC_IA64_PCREL64LSB",
+  "BFD_RELOC_IA64_LTOFF_FPTR22",
+  "BFD_RELOC_IA64_LTOFF_FPTR64I",
+  "BFD_RELOC_IA64_LTOFF_FPTR64MSB",
+  "BFD_RELOC_IA64_LTOFF_FPTR64LSB",
+  "BFD_RELOC_IA64_SEGBASE",
+  "BFD_RELOC_IA64_SEGREL32MSB",
+  "BFD_RELOC_IA64_SEGREL32LSB",
+  "BFD_RELOC_IA64_SEGREL64MSB",
+  "BFD_RELOC_IA64_SEGREL64LSB",
+  "BFD_RELOC_IA64_SECREL32MSB",
+  "BFD_RELOC_IA64_SECREL32LSB",
+  "BFD_RELOC_IA64_SECREL64MSB",
+  "BFD_RELOC_IA64_SECREL64LSB",
+  "BFD_RELOC_IA64_REL32MSB",
+  "BFD_RELOC_IA64_REL32LSB",
+  "BFD_RELOC_IA64_REL64MSB",
+  "BFD_RELOC_IA64_REL64LSB",
+  "BFD_RELOC_IA64_LTV32MSB",
+  "BFD_RELOC_IA64_LTV32LSB",
+  "BFD_RELOC_IA64_LTV64MSB",
+  "BFD_RELOC_IA64_LTV64LSB",
+  "BFD_RELOC_IA64_IPLTMSB",
+  "BFD_RELOC_IA64_IPLTLSB",
+  "BFD_RELOC_IA64_EPLTMSB",
+  "BFD_RELOC_IA64_EPLTLSB",
+  "BFD_RELOC_IA64_COPY",
+  "BFD_RELOC_IA64_TPREL22",
+  "BFD_RELOC_IA64_TPREL64MSB",
+  "BFD_RELOC_IA64_TPREL64LSB",
+  "BFD_RELOC_IA64_LTOFF_TP22",
+  "BFD_RELOC_IA64_LTOFF22X",
+  "BFD_RELOC_IA64_LDXMOV",
  "@@overflow: BFD_RELOC_UNUSED@@",
 };
 #endif
diff --git a/bfd/reloc.c b/bfd/reloc.c
index f312ffc..12f07b6 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -2749,6 +2749,134 @@ ENUMDOC
   is stored in the reloc's addend.  For Rel hosts, we are forced to put
   this offset in the reloc's section offset.
 
+ENUM
+  BFD_RELOC_IA64_IMM14
+ENUMX
+  BFD_RELOC_IA64_IMM22
+ENUMX
+  BFD_RELOC_IA64_IMM64
+ENUMX
+  BFD_RELOC_IA64_DIR32MSB
+ENUMX
+  BFD_RELOC_IA64_DIR32LSB
+ENUMX
+  BFD_RELOC_IA64_DIR64MSB
+ENUMX
+  BFD_RELOC_IA64_DIR64LSB
+ENUMX
+  BFD_RELOC_IA64_GPREL22
+ENUMX
+  BFD_RELOC_IA64_GPREL64I
+ENUMX
+  BFD_RELOC_IA64_GPREL32MSB
+ENUMX
+  BFD_RELOC_IA64_GPREL32LSB
+ENUMX
+  BFD_RELOC_IA64_GPREL64MSB
+ENUMX
+  BFD_RELOC_IA64_GPREL64LSB
+ENUMX
+  BFD_RELOC_IA64_LTOFF22
+ENUMX
+  BFD_RELOC_IA64_LTOFF64I
+ENUMX
+  BFD_RELOC_IA64_PLTOFF22
+ENUMX
+  BFD_RELOC_IA64_PLTOFF64I
+ENUMX
+  BFD_RELOC_IA64_PLTOFF64MSB
+ENUMX
+  BFD_RELOC_IA64_PLTOFF64LSB
+ENUMX
+  BFD_RELOC_IA64_FPTR64I
+ENUMX
+  BFD_RELOC_IA64_FPTR32MSB
+ENUMX
+  BFD_RELOC_IA64_FPTR32LSB
+ENUMX
+  BFD_RELOC_IA64_FPTR64MSB
+ENUMX
+  BFD_RELOC_IA64_FPTR64LSB
+ENUMX
+  BFD_RELOC_IA64_PCREL21B
+ENUMX
+  BFD_RELOC_IA64_PCREL21M
+ENUMX
+  BFD_RELOC_IA64_PCREL21F
+ENUMX
+  BFD_RELOC_IA64_PCREL32MSB
+ENUMX
+  BFD_RELOC_IA64_PCREL32LSB
+ENUMX
+  BFD_RELOC_IA64_PCREL64MSB
+ENUMX
+  BFD_RELOC_IA64_PCREL64LSB
+ENUMX
+  BFD_RELOC_IA64_LTOFF_FPTR22
+ENUMX
+  BFD_RELOC_IA64_LTOFF_FPTR64I
+ENUMX
+  BFD_RELOC_IA64_LTOFF_FPTR64MSB
+ENUMX
+  BFD_RELOC_IA64_LTOFF_FPTR64LSB
+ENUMX
+  BFD_RELOC_IA64_SEGBASE
+ENUMX
+  BFD_RELOC_IA64_SEGREL32MSB
+ENUMX
+  BFD_RELOC_IA64_SEGREL32LSB
+ENUMX
+  BFD_RELOC_IA64_SEGREL64MSB
+ENUMX
+  BFD_RELOC_IA64_SEGREL64LSB
+ENUMX
+  BFD_RELOC_IA64_SECREL32MSB
+ENUMX
+  BFD_RELOC_IA64_SECREL32LSB
+ENUMX
+  BFD_RELOC_IA64_SECREL64MSB
+ENUMX
+  BFD_RELOC_IA64_SECREL64LSB
+ENUMX
+  BFD_RELOC_IA64_REL32MSB
+ENUMX
+  BFD_RELOC_IA64_REL32LSB
+ENUMX
+  BFD_RELOC_IA64_REL64MSB
+ENUMX
+  BFD_RELOC_IA64_REL64LSB
+ENUMX
+  BFD_RELOC_IA64_LTV32MSB
+ENUMX
+  BFD_RELOC_IA64_LTV32LSB
+ENUMX
+  BFD_RELOC_IA64_LTV64MSB
+ENUMX
+  BFD_RELOC_IA64_LTV64LSB
+ENUMX
+  BFD_RELOC_IA64_IPLTMSB
+ENUMX
+  BFD_RELOC_IA64_IPLTLSB
+ENUMX
+  BFD_RELOC_IA64_EPLTMSB
+ENUMX
+  BFD_RELOC_IA64_EPLTLSB
+ENUMX
+  BFD_RELOC_IA64_COPY
+ENUMX
+  BFD_RELOC_IA64_TPREL22
+ENUMX
+  BFD_RELOC_IA64_TPREL64MSB
+ENUMX
+  BFD_RELOC_IA64_TPREL64LSB
+ENUMX
+  BFD_RELOC_IA64_LTOFF_TP22
+ENUMX
+  BFD_RELOC_IA64_LTOFF22X
+ENUMX
+  BFD_RELOC_IA64_LDXMOV
+ENUMDOC
+  Intel IA64 Relocations.
 ENDSENUM
   BFD_RELOC_UNUSED
 CODE_FRAGMENT
diff --git a/bfd/targets.c b/bfd/targets.c
index 8217d56..b92a1c3 100644
--- a/bfd/targets.c
+++ b/bfd/targets.c
@@ -508,6 +508,8 @@ extern const bfd_target b_out_vec_little_host;
 extern const bfd_target bfd_efi_app_ia32_vec;
 extern const bfd_target bfd_efi_app_ia64_vec;
 extern const bfd_target bfd_elf64_alpha_vec;
+extern const bfd_target bfd_elf64_ia64_little_vec;
+extern const bfd_target bfd_elf64_ia64_big_vec;
 extern const bfd_target bfd_elf32_avr_vec;
 extern const bfd_target bfd_elf32_bigarc_vec;
 extern const bfd_target bfd_elf32_bigarm_vec;
@@ -703,6 +705,8 @@ const bfd_target * const bfd_target_vector[] = {
 	&bfd_elf32_big_generic_vec,
 #ifdef BFD64
 	&bfd_elf64_alpha_vec,
+	&bfd_elf64_ia64_little_vec,
+	&bfd_elf64_ia64_big_vec,
 #endif
 	&bfd_elf32_avr_vec,
 	&bfd_elf32_bigarc_vec,
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 8621445..030251b 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,11 @@
+Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
+			  David Mosberger  <davidm@hpl.hp.com>
+
+	* Makefile.am (readelf.o): Add elf/ia64.h.
+	* Makefile.in: Rebuild.
+	* readelf.c: Include elf/ia64.h.
+	(guess_is_rela, dump_relocations): Handle EM_IA_64.
+	
 2000-04-17  Timothy Wall  <twall@cygnus.com>
 
 	* objdump.c (disassemble_data): Set octets per byte *after*
diff --git a/binutils/Makefile.am b/binutils/Makefile.am
index c8d7302..97e403e 100644
--- a/binutils/Makefile.am
+++ b/binutils/Makefile.am
@@ -481,6 +481,7 @@ readelf.o: readelf.c ../bfd/bfd.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/elf/sparc.h $(INCDIR)/elf/m32r.h $(INCDIR)/elf/d10v.h \
   $(INCDIR)/elf/d30v.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/mn10200.h \
   $(INCDIR)/elf/mn10300.h $(INCDIR)/elf/hppa.h $(INCDIR)/elf/arc.h \
+  $(INCDIR)/elf/ia64.h \
   $(INCDIR)/elf/fr30.h $(INCDIR)/elf/mcore.h $(INCDIR)/elf/i960.h \
   $(INCDIR)/elf/pj.h $(INCDIR)/elf/avr.h bucomm.h config.h \
   $(INCDIR)/bin-bugs.h $(INCDIR)/fopen-same.h
diff --git a/binutils/Makefile.in b/binutils/Makefile.in
index 2221633..5e6c1a5 100644
--- a/binutils/Makefile.in
+++ b/binutils/Makefile.in
@@ -1337,6 +1337,7 @@ readelf.o: readelf.c ../bfd/bfd.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/elf/sparc.h $(INCDIR)/elf/m32r.h $(INCDIR)/elf/d10v.h \
   $(INCDIR)/elf/d30v.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/mn10200.h \
   $(INCDIR)/elf/mn10300.h $(INCDIR)/elf/hppa.h $(INCDIR)/elf/arc.h \
+  $(INCDIR)/elf/ia64.h \
   $(INCDIR)/elf/fr30.h $(INCDIR)/elf/mcore.h $(INCDIR)/elf/i960.h \
   $(INCDIR)/elf/pj.h $(INCDIR)/elf/avr.h bucomm.h config.h \
   $(INCDIR)/bin-bugs.h $(INCDIR)/fopen-same.h
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 152ce1e..504c51b 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -70,6 +70,7 @@
 #include "elf/i960.h"
 #include "elf/pj.h"
 #include "elf/avr.h"
+#include "elf/ia64.h"
 
 #include "bucomm.h"
 #include "getopt.h"
@@ -562,6 +563,7 @@ guess_is_rela (e_machine)
     case EM_SH:
     case EM_ALPHA:
     case EM_MCORE:
+    case EM_IA_64:
       return TRUE;
 
     case EM_MMA:
@@ -873,6 +875,9 @@ dump_relocations (file, rel_offset, rel_size, symtab, nsyms, strtab, is_rela)
 	case EM_PJ:
 	  rtype = elf_pj_reloc_type (type);
 	  break;
+	case EM_IA_64:
+	  rtype = elf_ia64_reloc_type (type);
+	  break;
 	}
 
       if (rtype == NULL)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 7845ae5..ca922ec 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,21 @@
+Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
+			  David Mosberger  <davidm@hpl.hp.com>
+			  Timothy Wall <twall@cygnus.com>
+			  Andrew MacLeod  <amacleod@cygnus.com>
+			  Jim Wilson  <wilson@cygnus.com>
+
+	* Makefile.am (CPU_TYPES): Add ia64.
+	(TARGET_CPU_CFILES): Add cofnig/tc-ia64.c.
+	(TARGET_CPU_HFILES): Add config/tc-ia64.h.
+	* Makefile.in: Rebuild.
+	* app.c (do_scrub_chars): Handle DOUBLESLASH_COMMENTS.
+	* configure: Rebuild.
+	* configure.in: Recognize ia64 as cpu type.  Set bfd_gas.
+	(ia64-*-elf*, ia64-*-linux-gnu*): New targets.
+	* expr.c (expr): Handle md_optimize_expr.
+	* read.c (LEX_HASH): Add comment.
+	* config/tc-ia64.c, config/tc-ia64.h: New files.
+	
 2000-04-21  Richard Henderson  <rth@cygnus.com>
 
 	* config/tc-d30v.c (write_2_short): Disregard opcode1->ecc when
diff --git a/gas/Makefile.am b/gas/Makefile.am
index 12f8caa..d46b1bd 100644
--- a/gas/Makefile.am
+++ b/gas/Makefile.am
@@ -48,6 +48,7 @@ CPU_TYPES = \
 	h8300 \
 	h8500 \
 	hppa \
+	ia64 \
 	i370 \
 	i386 \
 	i860 \
@@ -218,6 +219,7 @@ TARGET_CPU_CFILES = \
 	config/tc-h8300.c \
 	config/tc-h8500.c \
 	config/tc-hppa.c \
+	config/tc-ia64.c \
 	config/tc-i370.c \
 	config/tc-i386.c \
 	config/tc-i860.c \
@@ -254,6 +256,7 @@ TARGET_CPU_HFILES = \
 	config/tc-h8300.h \
 	config/tc-h8500.h \
 	config/tc-hppa.h \
+	config/tc-ia64.h \
 	config/tc-i370.h \
 	config/tc-i386.h \
 	config/tc-i860.h \
diff --git a/gas/Makefile.in b/gas/Makefile.in
index d3237c0..96d5f28 100644
--- a/gas/Makefile.in
+++ b/gas/Makefile.in
@@ -152,6 +152,7 @@ CPU_TYPES = \
 	h8300 \
 	h8500 \
 	hppa \
+	ia64 \
 	i370 \
 	i386 \
 	i860 \
@@ -328,6 +329,7 @@ TARGET_CPU_CFILES = \
 	config/tc-h8300.c \
 	config/tc-h8500.c \
 	config/tc-hppa.c \
+	config/tc-ia64.c \
 	config/tc-i370.c \
 	config/tc-i386.c \
 	config/tc-i860.c \
@@ -365,6 +367,7 @@ TARGET_CPU_HFILES = \
 	config/tc-h8300.h \
 	config/tc-h8500.h \
 	config/tc-hppa.h \
+	config/tc-ia64.h \
 	config/tc-i370.h \
 	config/tc-i386.h \
 	config/tc-i860.h \
diff --git a/gas/app.c b/gas/app.c
index 2613e74..1b2243a 100644
--- a/gas/app.c
+++ b/gas/app.c
@@ -913,6 +913,21 @@ do_scrub_chars (get, tostart, tolen)
 	      ch = ' ';
 	      goto recycle;
 	    }
+#ifdef DOUBLESLASH_LINE_COMMENTS
+	  else if (ch2 == '/')
+	    {
+	      do
+		{
+		  ch = GET ();
+		}
+	      while (ch != EOF && !IS_NEWLINE (ch));
+	      if (ch == EOF)
+		as_warn ("end of file in comment; newline inserted");
+	      state = 0;
+	      PUT ('\n');
+	      break;
+	    }
+#endif
 	  else
 	    {
 	      if (ch2 != EOF)
diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c
new file mode 100644
index 0000000..e4b6bbe
--- /dev/null
+++ b/gas/config/tc-ia64.c
@@ -0,0 +1,8295 @@
+/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
+   Copyright (C) 1998, 1999 Free Software Foundation.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+/*
+  TODO:
+
+  - optional operands
+  - directives:
+	.alias
+	.eb
+	.estate
+	.lb
+	.popsection
+	.previous
+	.psr
+	.pushsection
+	.save
+	.vframe
+  - labels are wrong if automatic alignment is introduced
+    (e.g., checkout the second real10 definition in test-data.s)
+  - DV-related stuff:
+        <reg>.safe_across_calls and any other DV-related directives I don't
+          have documentation for.
+        verify mod-sched-brs reads/writes are checked/marked (and other
+        notes) 
+
+ */
+
+#include "as.h"
+#include "dwarf2dbg.h"
+#include "subsegs.h"
+
+#include "opcode/ia64.h"
+
+#include "elf/ia64.h"
+
+#define NELEMS(a)	((int) (sizeof (a)/sizeof ((a)[0])))
+#define MIN(a,b)	((a) < (b) ? (a) : (b))
+
+#define NUM_SLOTS	4
+#define PREV_SLOT	md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
+#define CURR_SLOT	md.slot[md.curr_slot]
+
+#define O_pseudo_fixup (O_max + 1)
+
+enum special_section
+  {
+    SPECIAL_SECTION_BSS = 0,
+    SPECIAL_SECTION_SBSS,
+    SPECIAL_SECTION_SDATA,
+    SPECIAL_SECTION_RODATA,
+    SPECIAL_SECTION_COMMENT,
+    SPECIAL_SECTION_UNWIND,
+    SPECIAL_SECTION_UNWIND_INFO
+  };
+
+enum reloc_func
+  {
+    FUNC_FPTR_RELATIVE,
+    FUNC_GP_RELATIVE,
+    FUNC_LT_RELATIVE,
+    FUNC_PLT_RELATIVE,
+    FUNC_SEC_RELATIVE,
+    FUNC_SEG_RELATIVE,
+    FUNC_LTV_RELATIVE,
+    FUNC_LT_FPTR_RELATIVE,
+  };
+
+enum reg_symbol
+  {
+    REG_GR	= 0,
+    REG_FR	= (REG_GR + 128),
+    REG_AR	= (REG_FR + 128),
+    REG_CR	= (REG_AR + 128),
+    REG_P	= (REG_CR + 128),
+    REG_BR	= (REG_P  + 64),
+    REG_IP	= (REG_BR + 8),
+    REG_CFM,
+    REG_PR,
+    REG_PR_ROT,
+    REG_PSR,
+    REG_PSR_L,
+    REG_PSR_UM,
+    /* The following are pseudo-registers for use by gas only.  */
+    IND_CPUID,
+    IND_DBR,
+    IND_DTR,
+    IND_ITR,
+    IND_IBR,
+    IND_MEM,
+    IND_MSR,
+    IND_PKR,
+    IND_PMC,
+    IND_PMD,
+    IND_RR,
+    REG_NUM
+  };
+
+enum dynreg_type
+  {
+    DYNREG_GR = 0,	/* dynamic general purpose register */
+    DYNREG_FR,		/* dynamic floating point register */
+    DYNREG_PR,		/* dynamic predicate register */
+    DYNREG_NUM_TYPES
+  };
+
+/* On the ia64, we can't know the address of a text label until the
+   instructions are packed into a bundle.  To handle this, we keep
+   track of the list of labels that appear in front of each
+   instruction.  */
+struct label_fix
+  {
+    struct label_fix *next;
+    struct symbol *sym;
+  };
+
+extern int target_big_endian;
+
+/* Characters which always start a comment.  */
+const char comment_chars[] = "";
+
+/* Characters which start a comment at the beginning of a line.  */
+const char line_comment_chars[] = "#";
+
+/* Characters which may be used to separate multiple commands on a
+   single line.  */
+const char line_separator_chars[] = ";";
+
+/* Characters which are used to indicate an exponent in a floating
+   point number.  */
+const char EXP_CHARS[] = "eE";
+
+/* Characters which mean that a number is a floating point constant,
+   as in 0d1.0.  */
+const char FLT_CHARS[] = "rRsSfFdDxXpP";
+
+/* ia64-specific option processing: */
+
+const char *md_shortopts = "M:N:x::";
+
+struct option md_longopts[] =
+  {
+    { NULL, no_argument, NULL, 0}
+  };
+
+size_t md_longopts_size = sizeof (md_longopts);
+
+static struct
+  {
+    struct hash_control *pseudo_hash;	/* pseudo opcode hash table */
+    struct hash_control *reg_hash;	/* register name hash table */
+    struct hash_control *dynreg_hash;	/* dynamic register hash table */
+    struct hash_control *const_hash;	/* constant hash table */
+    struct hash_control *entry_hash;    /* code entry hint hash table */
+
+    symbolS *regsym[REG_NUM];
+
+    /* If X_op is != O_absent, the registername for the instruction's
+       qualifying predicate.  If NULL, p0 is assumed for instructions
+       that are predicatable.  */
+    expressionS qp;
+
+    unsigned int
+      manual_bundling : 1, 
+      debug_dv: 1,
+      detect_dv: 1,
+      explicit_mode : 1,            /* which mode we're in */
+      default_explicit_mode : 1,    /* which mode is the default */
+      mode_explicitly_set : 1,      /* was the current mode explicitly set? */
+      auto_align : 1;
+
+    /* Each bundle consists of up to three instructions.  We keep
+       track of four most recent instructions so we can correctly set
+       the end_of_insn_group for the last instruction in a bundle. */
+    int curr_slot;
+    int num_slots_in_use;
+    struct slot
+      {
+	unsigned int
+	  end_of_insn_group : 1,
+	  manual_bundling_on : 1,
+	  manual_bundling_off : 1;
+	signed char user_template;	/* user-selected template, if any */
+	unsigned char qp_regno;		/* qualifying predicate */
+	/* This duplicates a good fraction of "struct fix" but we
+	   can't use a "struct fix" instead since we can't call
+	   fix_new_exp() until we know the address of the instruction.  */
+	int num_fixups;
+	struct insn_fix
+	  {
+	    bfd_reloc_code_real_type code;
+	    enum ia64_opnd opnd;	/* type of operand in need of fix */
+	    unsigned int is_pcrel : 1;	/* is operand pc-relative? */
+	    expressionS expr;		/* the value to be inserted */
+	  }
+	fixup[2];			/* at most two fixups per insn */
+	struct ia64_opcode *idesc;
+	struct label_fix *label_fixups;
+	struct unw_rec_list *unwind_record;	/* Unwind directive.  */
+	expressionS opnd[6];
+	char *src_file;
+	unsigned int src_line;
+	struct dwarf2_line_info debug_line;
+      }
+    slot[NUM_SLOTS];
+
+    segT last_text_seg;
+
+    struct dynreg
+      {
+	struct dynreg *next;		/* next dynamic register */
+	const char *name;
+	unsigned short base;		/* the base register number */
+	unsigned short num_regs;	/* # of registers in this set */
+      }
+    *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
+
+    flagword flags;			/* ELF-header flags */
+
+    struct mem_offset {
+      unsigned hint:1;              /* is this hint currently valid? */
+      bfd_vma offset;               /* mem.offset offset */
+      bfd_vma base;                 /* mem.offset base */
+    } mem_offset;
+
+    int path;                       /* number of alt. entry points seen */
+    const char **entry_labels;      /* labels of all alternate paths in
+                                       the current DV-checking block. */
+    int maxpaths;                   /* size currently allocated for
+                                       entry_labels */
+  }
+md;
+
+/* application registers: */
+
+#define AR_K0           0
+#define AR_K7           7
+#define AR_RSC          16
+#define AR_BSP          17
+#define AR_BSPSTORE     18
+#define AR_RNAT         19
+#define AR_UNAT         36
+#define AR_FPSR         40
+#define AR_ITC          44
+
+static const struct
+  {
+    const char *name;
+    int regnum;
+  }
+ar[] =
+  {
+    {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
+    {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
+    {"ar.rsc",		16}, {"ar.bsp",		17},
+    {"ar.bspstore",	18}, {"ar.rnat",	19},
+    {"ar.fcr",		21}, {"ar.eflag",	24},
+    {"ar.csd",		25}, {"ar.ssd",		26},
+    {"ar.cflg",		27}, {"ar.fsr",		28},
+    {"ar.fir",		29}, {"ar.fdr",		30},
+    {"ar.ccv",		32}, {"ar.unat",	36},
+    {"ar.fpsr",		40}, {"ar.itc",		44},
+    {"ar.pfs",		64}, {"ar.lc",		65},
+    {"ar.ec",		66}, 
+  };
+
+#define CR_IPSR         16
+#define CR_ISR          17
+#define CR_IIP          19
+#define CR_IFA          20
+#define CR_ITIR         21
+#define CR_IIPA         22
+#define CR_IFS          23
+#define CR_IIM          24
+#define CR_IHA          25
+#define CR_IVR          65
+#define CR_TPR          66
+#define CR_EOI          67
+#define CR_IRR0         68
+#define CR_IRR3         71
+#define CR_LRR0         80
+#define CR_LRR1         81
+
+/* control registers: */
+static const struct
+  {
+    const char *name;
+    int regnum;
+  }
+cr[] =
+  {
+    {"cr.dcr",	 0},
+    {"cr.itm",	 1},
+    {"cr.iva",	 2},
+    {"cr.pta",	 8},
+    {"cr.gpta",	 9},
+    {"cr.ipsr",	16},
+    {"cr.isr",	17},
+    {"cr.iip",	19},
+    {"cr.ifa",	20},
+    {"cr.itir",	21},
+    {"cr.iipa",	22},
+    {"cr.ifs",	23},
+    {"cr.iim",	24},
+    {"cr.iha",	25},
+    {"cr.lid",	64},
+    {"cr.ivr",	65},
+    {"cr.tpr",	66},
+    {"cr.eoi",	67},
+    {"cr.irr0",	68},
+    {"cr.irr1",	69},
+    {"cr.irr2",	70},
+    {"cr.irr3",	71},
+    {"cr.itv",	72},
+    {"cr.pmv",	73},
+    {"cr.cmcv",	74},
+    {"cr.lrr0",	80},
+    {"cr.lrr1",	81}
+  };
+
+#define PSR_MFL         4
+#define PSR_IC          13
+#define PSR_DFL         18
+#define PSR_CPL         32
+
+static const struct const_desc
+  {
+    const char *name;
+    valueT value;
+  }
+const_bits[] =
+  {
+    /* PSR constant masks: */
+
+    /* 0: reserved */
+    {"psr.be",	((valueT) 1) << 1},
+    {"psr.up",	((valueT) 1) << 2},
+    {"psr.ac",	((valueT) 1) << 3},
+    {"psr.mfl",	((valueT) 1) << 4},
+    {"psr.mfh",	((valueT) 1) << 5},
+    /* 6-12: reserved */
+    {"psr.ic",	((valueT) 1) << 13},
+    {"psr.i",	((valueT) 1) << 14},
+    {"psr.pk",	((valueT) 1) << 15},
+    /* 16: reserved */
+    {"psr.dt",	((valueT) 1) << 17},
+    {"psr.dfl",	((valueT) 1) << 18},
+    {"psr.dfh",	((valueT) 1) << 19},
+    {"psr.sp",	((valueT) 1) << 20},
+    {"psr.pp",	((valueT) 1) << 21},
+    {"psr.di",	((valueT) 1) << 22},
+    {"psr.si",	((valueT) 1) << 23},
+    {"psr.db",	((valueT) 1) << 24},
+    {"psr.lp",	((valueT) 1) << 25},
+    {"psr.tb",	((valueT) 1) << 26},
+    {"psr.rt",	((valueT) 1) << 27},
+    /* 28-31: reserved */
+    /* 32-33: cpl (current privilege level) */
+    {"psr.is",	((valueT) 1) << 34},
+    {"psr.mc",	((valueT) 1) << 35},
+    {"psr.it",	((valueT) 1) << 36},
+    {"psr.id",	((valueT) 1) << 37},
+    {"psr.da",	((valueT) 1) << 38},
+    {"psr.dd",	((valueT) 1) << 39},
+    {"psr.ss",	((valueT) 1) << 40},
+    /* 41-42: ri (restart instruction) */
+    {"psr.ed",	((valueT) 1) << 43},
+    {"psr.bn",	((valueT) 1) << 44},
+  };
+
+/* indirect register-sets/memory: */
+
+static const struct
+  {
+    const char *name;
+    int regnum;
+  }
+indirect_reg[] =
+  {
+    { "CPUID",	IND_CPUID },
+    { "cpuid",	IND_CPUID },
+    { "dbr",	IND_DBR },
+    { "dtr",	IND_DTR },
+    { "itr",	IND_ITR },
+    { "ibr",	IND_IBR },
+    { "msr",	IND_MSR },
+    { "pkr",	IND_PKR },
+    { "pmc",	IND_PMC },
+    { "pmd",	IND_PMD },
+    { "rr",	IND_RR },
+  };
+
+/* Pseudo functions used to indicate relocation types (these functions
+   start with an at sign (@).  */
+static struct
+  {
+    const char *name;
+    enum pseudo_type
+      {
+	PSEUDO_FUNC_NONE,
+	PSEUDO_FUNC_RELOC,
+	PSEUDO_FUNC_CONST,
+	PSEUDO_FUNC_FLOAT
+      }
+    type;
+    union
+      {
+	unsigned long ival;
+	symbolS *sym;
+      }
+    u;
+  }
+pseudo_func[] =
+  {
+    /* reloc pseudo functions (these must come first!): */
+    { "fptr",	PSEUDO_FUNC_RELOC },
+    { "gprel",	PSEUDO_FUNC_RELOC },
+    { "ltoff",	PSEUDO_FUNC_RELOC },
+    { "pltoff",	PSEUDO_FUNC_RELOC },
+    { "secrel",	PSEUDO_FUNC_RELOC },
+    { "segrel",	PSEUDO_FUNC_RELOC },
+    { "ltv",	PSEUDO_FUNC_RELOC },
+    { 0, },		/* placeholder for FUNC_LT_FPTR_RELATIVE */
+
+    /* mbtype4 constants: */
+    { "alt",	PSEUDO_FUNC_CONST, { 0xa } },
+    { "brcst",	PSEUDO_FUNC_CONST, { 0x0 } },
+    { "mix",	PSEUDO_FUNC_CONST, { 0x8 } },
+    { "rev",	PSEUDO_FUNC_CONST, { 0xb } },
+    { "shuf",	PSEUDO_FUNC_CONST, { 0x9 } },
+
+    /* fclass constants: */
+    { "natval",	PSEUDO_FUNC_CONST, { 0x100 } },
+    { "qnan",	PSEUDO_FUNC_CONST, { 0x080 } },
+    { "snan",	PSEUDO_FUNC_CONST, { 0x040 } },
+    { "pos",	PSEUDO_FUNC_CONST, { 0x001 } },
+    { "neg",	PSEUDO_FUNC_CONST, { 0x002 } },
+    { "zero",	PSEUDO_FUNC_CONST, { 0x004 } },
+    { "unorm",	PSEUDO_FUNC_CONST, { 0x008 } },
+    { "norm",	PSEUDO_FUNC_CONST, { 0x010 } },
+    { "inf",	PSEUDO_FUNC_CONST, { 0x020 } },
+  };
+
+/* 41-bit nop opcodes (one per unit): */
+static const bfd_vma nop[IA64_NUM_UNITS] =
+  {
+    0x0000000000LL,	/* NIL => break 0 */
+    0x0008000000LL,	/* I-unit nop */
+    0x0008000000LL,	/* M-unit nop */
+    0x4000000000LL,	/* B-unit nop */
+    0x0008000000LL,	/* F-unit nop */
+    0x0008000000LL,	/* L-"unit" nop */
+    0x0008000000LL,	/* X-unit nop */
+  };
+
+/* Can't be `const' as it's passed to input routines (which have the
+   habit of setting temporary sentinels.  */
+static char special_section_name[][20] =
+  {
+    {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
+    {".IA_64.unwind"}, {".IA_64.unwind_info"}
+  };
+
+/* The best template for a particular sequence of up to three
+   instructions:  */
+#define N	IA64_NUM_TYPES
+static unsigned char best_template[N][N][N];
+#undef N
+
+/* Resource dependencies currently in effect */
+static struct rsrc {
+  int depind;                       /* dependency index */
+  const struct ia64_dependency *dependency; /* actual dependency */
+  unsigned specific:1,              /* is this a specific bit/regno? */
+    link_to_qp_branch:1;           /* will a branch on the same QP clear it?*/
+  int index;                        /* specific regno/bit within dependency */
+  int note;                         /* optional qualifying note (0 if none) */
+#define STATE_NONE 0
+#define STATE_STOP 1
+#define STATE_SRLZ 2
+  int insn_srlz;                    /* current insn serialization state */
+  int data_srlz;                    /* current data serialization state */
+  int qp_regno;                     /* qualifying predicate for this usage */
+  char *file;                       /* what file marked this dependency */
+  int line;                         /* what line marked this dependency */
+  struct mem_offset mem_offset;     /* optional memory offset hint */
+  int path;                         /* corresponding code entry index */
+} *regdeps = NULL;
+static int regdepslen = 0;
+static int regdepstotlen = 0;
+static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
+static const char *dv_sem[] = { "none", "implied", "impliedf",
+                                "data", "instr", "specific", "other" };
+
+/* Current state of PR mutexation */
+static struct qpmutex {
+  valueT prmask;
+  int path;
+} *qp_mutexes = NULL;          /* QP mutex bitmasks */
+static int qp_mutexeslen = 0;
+static int qp_mutexestotlen = 0;
+static valueT qp_safe_across_calls = 0; 
+
+/* Current state of PR implications */
+static struct qp_imply {
+  unsigned p1:6;
+  unsigned p2:6;
+  unsigned p2_branched:1;
+  int path;
+} *qp_implies = NULL;
+static int qp_implieslen = 0;
+static int qp_impliestotlen = 0;
+
+/* Keep track of static GR values so that indirect register usage can 
+   sometimes be tracked. */
+static struct gr {
+  unsigned known:1;
+  int path;
+  valueT value;
+} gr_values[128] = {{ 1, 0 }};
+
+/* These are the routines required to output the various types of
+   unwind records.  */
+
+typedef struct unw_rec_list {
+  unwind_record r;
+  unsigned long  slot_number;
+  struct unw_rec_list *next;
+} unw_rec_list;
+
+#define SLOT_NUM_NOT_SET        -1
+
+/* TRUE if processing unwind directives in a prologue region.  */
+static int unwind_prologue = 0;
+
+/* Maintain a list of unwind entries for the current function.  */
+static unw_rec_list *unwind_list = 0;
+static unw_rec_list *unwind_tail = 0;
+
+/* Any unwind entires that should be attached to the current
+   slot that an insn is being constructed for.  */
+static unw_rec_list *current_unwind_entry = 0;
+
+/* These are used to create the unwind table entry for this function.  */
+static symbolS *proc_start = 0;
+static symbolS *proc_end = 0;
+static symbolS *unwind_info = 0;
+static symbolS *personality_routine = 0;
+
+typedef void (*vbyte_func) PARAMS ((int, char *, char *));
+
+/* Forward delarations: */
+static int ar_is_in_integer_unit PARAMS ((int regnum));
+static void set_section PARAMS ((char *name));
+static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
+					  unsigned int, unsigned int));
+static void dot_radix PARAMS ((int));
+static void dot_special_section PARAMS ((int));
+static void dot_proc PARAMS ((int));
+static void dot_fframe PARAMS ((int));
+static void dot_vframe PARAMS ((int));
+static void dot_save PARAMS ((int));
+static void dot_restore PARAMS ((int));
+static void dot_handlerdata  PARAMS ((int));
+static void dot_unwentry PARAMS ((int));
+static void dot_altrp PARAMS ((int));
+static void dot_savesp PARAMS ((int));
+static void dot_savepsp PARAMS ((int));
+static void dot_saveg PARAMS ((int));
+static void dot_savef PARAMS ((int));
+static void dot_saveb PARAMS ((int));
+static void dot_savegf PARAMS ((int));
+static void dot_spill PARAMS ((int));
+static void dot_unwabi PARAMS ((int));
+static void dot_personality PARAMS ((int));
+static void dot_body PARAMS ((int));
+static void dot_prologue PARAMS ((int));
+static void dot_endp PARAMS ((int));
+static void dot_template PARAMS ((int));
+static void dot_regstk PARAMS ((int));
+static void dot_rot PARAMS ((int));
+static void dot_byteorder PARAMS ((int));
+static void dot_psr PARAMS ((int));
+static void dot_alias PARAMS ((int));
+static void dot_ln PARAMS ((int));
+static char *parse_section_name PARAMS ((void));
+static void dot_xdata PARAMS ((int));
+static void stmt_float_cons PARAMS ((int));
+static void stmt_cons_ua PARAMS ((int));
+static void dot_xfloat_cons PARAMS ((int));
+static void dot_xstringer PARAMS ((int));
+static void dot_xdata_ua PARAMS ((int));
+static void dot_xfloat_cons_ua PARAMS ((int));
+static void dot_pred_rel PARAMS ((int));
+static void dot_reg_val PARAMS ((int));
+static void dot_dv_mode PARAMS ((int));
+static void dot_entry PARAMS ((int));
+static void dot_mem_offset PARAMS ((int));
+static symbolS* declare_register PARAMS ((const char *name, int regnum));
+static void declare_register_set PARAMS ((const char *, int, int));
+static unsigned int operand_width PARAMS ((enum ia64_opnd));
+static int operand_match PARAMS ((const struct ia64_opcode *idesc,
+				  int index, expressionS *e));
+static int parse_operand PARAMS ((expressionS *e));
+static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
+static void build_insn PARAMS ((struct slot *, bfd_vma *));
+static void emit_one_bundle PARAMS ((void));
+static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
+static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym, 
+								  bfd_reloc_code_real_type r_type));
+static void insn_group_break PARAMS ((int, int, int));
+static void add_qp_mutex PARAMS((valueT mask));
+static void add_qp_imply PARAMS((int p1, int p2));
+static void clear_qp_branch_flag PARAMS((valueT mask));
+static void clear_qp_mutex PARAMS((valueT mask));
+static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
+static void clear_register_values PARAMS ((void));
+static void print_dependency PARAMS ((const char *action, int depind));
+static int is_conditional_branch PARAMS ((struct ia64_opcode *));
+static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
+static int check_dv PARAMS((struct ia64_opcode *idesc));
+static void check_dependencies PARAMS((struct ia64_opcode *));
+static void mark_resources PARAMS((struct ia64_opcode *));
+static void update_dependencies PARAMS((struct ia64_opcode *));
+static void note_register_values PARAMS((struct ia64_opcode *));
+static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
+static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
+static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
+
+/* Determine if application register REGNUM resides in the integer
+   unit (as opposed to the memory unit).  */
+static int
+ar_is_in_integer_unit (reg)
+     int reg;
+{
+  reg -= REG_AR;
+
+  return (reg == 64	/* pfs */
+	  || reg == 65	/* lc */
+	  || reg == 66	/* ec */
+	  /* ??? ias accepts and puts these in the integer unit.  */
+	  || (reg >= 112 && reg <= 127));
+}
+
+/* Switch to section NAME and create section if necessary.  It's
+   rather ugly that we have to manipulate input_line_pointer but I
+   don't see any other way to accomplish the same thing without
+   changing obj-elf.c (which may be the Right Thing, in the end).  */
+static void
+set_section (name)
+     char *name;
+{
+  char *saved_input_line_pointer;
+
+  saved_input_line_pointer = input_line_pointer;
+  input_line_pointer = name;
+  obj_elf_section (0);
+  input_line_pointer = saved_input_line_pointer;
+}
+
+/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA.  */
+
+flagword
+ia64_elf_section_flags (flags, attr, type)
+     flagword flags;
+     int attr, type;
+{
+  if (attr & SHF_IA_64_SHORT)
+    flags |= SEC_SMALL_DATA;
+  return flags;
+}
+
+static unsigned int
+set_regstack (ins, locs, outs, rots)
+     unsigned int ins, locs, outs, rots;
+{
+  unsigned int sof;	/* size of frame */
+
+  sof = ins + locs + outs;
+  if (sof > 96)
+    {
+      as_bad ("Size of frame exceeds maximum of 96 registers");
+      return 0;
+    }
+  if (rots > sof)
+    {
+      as_warn ("Size of rotating registers exceeds frame size");
+      return 0;
+    }
+  md.in.base = REG_GR + 32;
+  md.loc.base = md.in.base + ins;
+  md.out.base = md.loc.base + locs;
+
+  md.in.num_regs  = ins;
+  md.loc.num_regs = locs;
+  md.out.num_regs = outs;
+  md.rot.num_regs = rots;
+  return sof;
+}
+
+void
+ia64_flush_insns ()
+{
+  struct label_fix *lfix;
+  segT saved_seg;
+  subsegT saved_subseg;
+
+  if (!md.last_text_seg)
+    return;
+
+  saved_seg = now_seg;
+  saved_subseg = now_subseg;
+
+  subseg_set (md.last_text_seg, 0);
+
+  while (md.num_slots_in_use > 0)
+    emit_one_bundle ();		/* force out queued instructions */
+
+  /* In case there are labels following the last instruction, resolve
+     those now: */
+  for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
+    {
+      S_SET_VALUE (lfix->sym, frag_now_fix ());
+      symbol_set_frag (lfix->sym, frag_now);
+    }
+  CURR_SLOT.label_fixups = 0;
+
+  subseg_set (saved_seg, saved_subseg);
+}
+
+void
+ia64_do_align (nbytes)
+     int nbytes;
+{
+  char *saved_input_line_pointer = input_line_pointer;
+
+  input_line_pointer = "";
+  s_align_bytes (nbytes);
+  input_line_pointer = saved_input_line_pointer;
+}
+
+void
+ia64_cons_align (nbytes)
+     int nbytes;
+{
+  if (md.auto_align)
+    {
+      char *saved_input_line_pointer = input_line_pointer;
+      input_line_pointer = "";
+      s_align_bytes (nbytes);
+      input_line_pointer = saved_input_line_pointer;
+    }
+}
+
+/* Output COUNT bytes to a memory location.  */
+static unsigned char *vbyte_mem_ptr = NULL;
+
+void 
+output_vbyte_mem (count, ptr, comment)
+     int count;
+     char *ptr;
+     char *comment;
+{
+  int x;
+  if (vbyte_mem_ptr == NULL)
+    abort ();
+
+  if (count == 0)
+    return;
+  for (x = 0; x < count; x++)
+    *(vbyte_mem_ptr++) = ptr[x];
+}
+
+/* Count the number of bytes required for records.  */
+static int vbyte_count = 0;
+void 
+count_output (count, ptr, comment)
+     int count;
+     char *ptr;
+     char *comment;
+{
+  vbyte_count += count;
+}
+
+static void
+output_R1_format (f, rtype, rlen)
+     vbyte_func f;
+     unw_record_type rtype;
+     int rlen;
+{
+  int r;
+  char byte;
+  if (rlen > 0x1f)
+    {
+      output_R3_format (f, rtype, rlen);
+      return;
+    }
+  if (rtype == prologue)
+    r = 0;
+  else
+    if (rtype == body)
+      r = 1;
+    else
+      as_bad ("record type is not valid");
+  
+  byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
+  (*f) (1, &byte, NULL);
+}
+
+static void
+output_R2_format (f, mask, grsave, rlen)
+     vbyte_func f;
+     int mask, grsave;
+     unsigned long rlen;
+{
+  char bytes[20];
+  int count = 2;
+  mask = (mask & 0x0f);
+  grsave = (grsave & 0x7f);
+
+  bytes[0] = (UNW_R2 | (mask >> 1));
+  bytes[1] = (((mask & 0x01) << 7) | grsave);
+  count += output_leb128 (bytes + 2, rlen, 0);
+  (*f) (count, bytes, NULL);
+}
+
+static void
+output_R3_format (f, rtype, rlen)
+     vbyte_func f;
+     unw_record_type rtype;
+     unsigned long rlen;
+{
+  int r, count;
+  char bytes[20];
+  if (rlen <= 0x1f)
+    {
+      output_R1_format (f, rtype, rlen);
+      return;
+    }
+  if (rtype == prologue)
+    r = 0;
+  else
+    if (rtype == body)
+      r = 1;
+    else
+      as_bad ("record type is not valid");
+  bytes[0] = (UNW_R3 | r);
+  count = output_leb128 (bytes + 1, rlen, 0);
+  (*f) (count + 1, bytes, NULL);
+}
+
+static void
+output_P1_format (f, brmask)
+     vbyte_func f;
+     int brmask;
+{
+  char byte;
+  byte = UNW_P1 | (brmask & 0x1f);
+  (*f) (1, &byte, NULL);
+}
+
+static void
+output_P2_format (f, brmask, gr)
+     vbyte_func f;
+     int brmask;
+     int gr;
+{
+  char bytes[2];
+  brmask = (brmask & 0x1f);
+  bytes[0] = UNW_P2 | (brmask >> 1);
+  bytes[1] = (((brmask & 1) << 7) | gr);
+  (*f) (2, bytes, NULL);
+}
+
+static void
+output_P3_format (f, rtype, reg)
+     vbyte_func f;
+     unw_record_type rtype;
+     int reg;
+{
+  char bytes[2];
+  int r;
+  reg = (reg & 0x7f);
+  switch (rtype)
+  {
+    case psp_gr:
+      r = 0;
+      break;
+    case rp_gr:
+      r = 1;
+      break;
+    case pfs_gr:
+      r = 2;
+      break;
+    case preds_gr:
+      r = 3;
+      break;
+    case unat_gr:
+      r = 4;
+      break;
+    case lc_gr:
+      r = 5;
+      break;
+    case rp_br:
+      r = 6;
+      break;
+    case rnat_gr:
+      r = 7;
+      break;
+    case bsp_gr:
+      r = 8;
+      break;
+    case bspstore_gr:
+      r = 9;
+      break;
+    case fpsr_gr:
+      r = 10;
+      break;
+    case priunat_gr:
+      r = 11;
+      break;
+    default:
+      as_bad ("Invalid record type for P3 format.");
+  }
+  bytes[0] = (UNW_P3 | (r >> 1));
+  bytes[1] = (((r & 1) << 7) | reg);
+  (*f) (2, bytes, NULL);
+}
+
+
+static void
+output_P4_format (f, count, imask)
+     vbyte_func f;
+     int count;
+     char *imask;
+{
+  char *bytes;
+  bytes = alloca (count + 1);
+  bytes[0] = UNW_P4;
+  memcpy (bytes + 1, imask, count);
+  (*f) (count + 1, bytes, NULL);
+}
+
+static void
+output_P5_format (f, grmask, frmask)
+     vbyte_func f;
+     int grmask;
+     unsigned long frmask;
+{
+  char bytes[4];
+  grmask = (grmask & 0x0f);
+
+  bytes[0] = UNW_P5;
+  bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
+  bytes[2] = ((frmask & 0x0000ff00) >> 8);
+  bytes[3] = (frmask & 0x000000ff);
+  (*f) (4, bytes, NULL);
+}
+
+static void
+output_P6_format (f, rtype, rmask)
+     vbyte_func f;
+     unw_record_type rtype;
+     int rmask;
+{
+  char byte;
+  int r;
+  if (rtype == fr_mem)
+    r = 0;
+  else
+    if (rtype == gr_mem)
+      r = 1;
+    else
+      as_bad ("Invalid record type for format P6");
+  byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
+  (*f) (1, &byte, NULL);
+}
+
+static void
+output_P7_format (f, rtype, w1, w2)
+     vbyte_func f;
+     unw_record_type rtype;
+     unsigned long w1;
+     unsigned long w2;
+{
+  char bytes[20];
+  int count = 1;
+  int r;
+  count += output_leb128 (bytes + 1, w1, 0);
+  switch (rtype)
+    {
+      case mem_stack_f:
+        r = 0;
+	count += output_leb128 (bytes + count, w2, 0);
+	break;
+      case mem_stack_v:
+        r = 1;
+	break;
+      case spill_base:
+        r = 2;
+	break;
+      case psp_sprel:
+        r = 3;
+	break;
+      case rp_when:
+        r = 4;
+	break;
+      case rp_psprel:
+        r = 5;
+	break;
+      case pfs_when:
+        r = 6;
+	break;
+      case pfs_psprel:
+        r = 7;
+	break;
+      case preds_when:
+        r = 8;
+	break;
+      case preds_psprel:
+        r = 9;
+	break;
+      case lc_when:
+        r = 10;
+	break;
+      case lc_psprel:
+        r = 11;
+	break;
+      case unat_when:
+        r = 12;
+	break;
+      case unat_psprel:
+        r = 13;
+	break;
+      case fpsr_when:
+        r = 14;
+	break;
+      case fpsr_psprel:
+        r = 15;
+	break;
+    }
+  bytes[0] = (UNW_P7 | r);
+  (*f) (count, bytes, NULL);
+}
+
+static void
+output_P8_format (f, rtype, t)
+     vbyte_func f;
+     unw_record_type rtype;
+     unsigned long t;
+{
+  char bytes[20];
+  int r;
+  int count = 2;
+  bytes[0] = UNW_P8;
+  switch (rtype)
+    {
+      case rp_sprel:
+        r = 1;
+	break;
+      case pfs_sprel:
+        r = 2;
+	break;
+      case preds_sprel:
+        r = 3;
+	break;
+      case lc_sprel:
+        r = 4;
+	break;
+      case unat_sprel:
+        r = 5;
+	break;
+      case fpsr_sprel:
+        r = 6;
+	break;
+      case bsp_when:
+        r = 7;
+	break;
+      case bsp_psprel:
+        r = 8;
+	break;
+      case bsp_sprel:
+        r = 9;
+	break;
+      case bspstore_when:
+        r = 10;
+	break;
+      case bspstore_psprel:
+        r = 11;
+	break;
+      case bspstore_sprel:
+        r = 12;
+	break;
+      case rnat_when:
+        r = 13;
+	break;
+      case rnat_psprel:
+        r = 14;
+	break;
+      case rnat_sprel:
+        r = 15;
+	break;
+      case priunat_when_gr:
+        r = 16;
+	break;
+      case priunat_psprel:
+        r = 17;
+	break;
+      case priunat_sprel:
+        r = 18;
+	break;
+      case priunat_when_mem:
+        r = 19;
+	break;
+    }
+  bytes[1] = r;
+  count += output_leb128 (bytes + 2, t, 0);
+  (*f) (count, bytes, NULL);
+}
+
+static void
+output_P9_format (f, grmask, gr)
+     vbyte_func f;
+     int grmask;
+     int gr;
+{
+  char bytes[3];
+  bytes[0] = UNW_P9;
+  bytes[1] = (grmask & 0x0f);
+  bytes[2] = (gr & 0x7f);
+  (*f) (3, bytes, NULL);
+}
+
+static void
+output_P10_format (f, abi, context)
+     vbyte_func f;
+     int abi;
+     int context;
+{
+  char bytes[3];
+  bytes[0] = UNW_P10;
+  bytes[1] = (abi & 0xff);
+  bytes[2] = (context & 0xff);
+  (*f) (3, bytes, NULL);
+}
+
+static void
+output_B1_format (f, rtype, label)
+     vbyte_func f;
+     unw_record_type rtype;
+     unsigned long label;
+{
+  char byte;
+  int r;
+  if (label > 0x1f) 
+    {
+      output_B4_format (f, rtype, label);
+      return;
+    }
+  if (rtype == label_state)
+    r = 0;
+  else
+    if (rtype == copy_state)
+      r = 1;
+    else
+      as_bad ("Invalid record type for format B1");
+
+  byte = (UNW_B1 | (r << 5) | (label & 0x1f));
+  (*f) (1, &byte, NULL);
+}
+
+static void
+output_B2_format (f, ecount, t)
+     vbyte_func f;
+     unsigned long ecount;
+     unsigned long t;
+{
+  char bytes[20];
+  int count = 1;
+  if (ecount > 0x1f)
+    {
+      output_B3_format (f, ecount, t);
+      return;
+    }
+  bytes[0] = (UNW_B2 | (ecount & 0x1f));
+  count += output_leb128 (bytes + 1, t, 0);
+  (*f) (count, bytes, NULL);
+}
+
+static void
+output_B3_format (f, ecount, t)
+     vbyte_func f;
+     unsigned long ecount;
+     unsigned long t;
+{
+  char bytes[20];
+  int count = 1;
+  if (ecount <= 0x1f)
+    {
+      output_B2_format (f, ecount, t);
+      return;
+    }
+  bytes[0] = UNW_B3;
+  count += output_leb128 (bytes + 1, t, 0);
+  count += output_leb128 (bytes + count, ecount, 0);
+  (*f) (count, bytes, NULL);
+}
+
+static void
+output_B4_format (f, rtype, label)
+     vbyte_func f;
+     unw_record_type rtype;
+     unsigned long label;
+{
+  char bytes[20];
+  int r;
+  int count = 1;
+  if (label <= 0x1f) 
+    {
+      output_B1_format (f, rtype, label);
+      return;
+    }
+  if (rtype == label_state)
+    r = 0;
+  else
+    if (rtype == copy_state)
+      r = 1;
+    else
+      as_bad ("Invalid record type for format B1");
+
+  bytes[0] = (UNW_B4 | (r << 3));
+  count += output_leb128 (bytes + 1, label, 0);
+  (*f) (count, bytes, NULL);
+}
+
+static char
+format_a_b_reg (a, b, reg)
+  int a, b;
+  int reg;
+{
+  int ret;
+  a = (a & 1);
+  b = (b & 1);
+  reg = (reg & 0x1f);
+  ret = (a << 6) | (a << 5) | reg;
+  return ret;
+}
+
+static void
+output_X1_format (f, rtype, a, b, reg, t, w1)
+     vbyte_func f;
+     unw_record_type rtype;
+     int a, b, reg;
+     unsigned long t;
+     unsigned long w1;
+{
+  char bytes[20];
+  int r;
+  int count = 2;
+  bytes[0] = UNW_X1;
+  if (rtype == spill_psprel)
+    r = 0;
+  else
+    if (rtype = spill_sprel)
+      r = 1;
+    else
+      as_bad ("Invalid record type for format X1");
+  bytes[1] = ((r << 7) | format_a_b_reg (a, b, reg));
+  count += output_leb128 (bytes + 2, t, 0);
+  count += output_leb128 (bytes + count, w1, 0);
+  (*f) (count, bytes, NULL);
+}
+
+static void
+output_X2_format (f, a, b, reg, x, y, treg, t)
+     vbyte_func f;
+     int a, b, reg;
+     int x, y, treg;
+     unsigned long t;
+{
+  char bytes[20];
+  int r;
+  int count = 3;
+  bytes[0] = UNW_X2;
+  bytes[1] = (((x & 1) << 7) | format_a_b_reg (a, b, reg));
+  bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
+  count += output_leb128 (bytes + 3, t, 0);
+  (*f) (count, bytes, NULL);
+}
+
+static void
+output_X3_format (f, rtype, qp, a, b, reg, t, w1)
+     vbyte_func f;
+     unw_record_type rtype;
+     int qp;
+     int a, b, reg;
+     unsigned long t;
+     unsigned long w1;
+{
+  char bytes[20];
+  int r;
+  int count = 3;
+  bytes[0] = UNW_X1;
+  if (rtype == spill_psprel_p)
+    r = 0;
+  else
+    if (rtype = spill_sprel_p)
+      r = 1;
+    else
+      as_bad ("Invalid record type for format X1");
+  bytes[1] = ((r << 7) | (qp & 0x3f));
+  bytes[2] = format_a_b_reg (a, b, reg);
+  count += output_leb128 (bytes + 3, t, 0);
+  count += output_leb128 (bytes + count, w1, 0);
+  (*f) (count, bytes, NULL);
+}
+
+static void
+output_X4_format (f, qp, a, b, reg, x, y, treg, t)
+     vbyte_func f;
+     int qp;
+     int a, b, reg;
+     int x, y, treg;
+     unsigned long t;
+{
+  char bytes[20];
+  int r;
+  int count = 4;
+  bytes[0] = UNW_X2;
+  bytes[1] = (qp & 0x3f);
+  bytes[2] = (((x & 1) << 7) | format_a_b_reg (a, b, reg));
+  bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
+  count += output_leb128 (bytes + 4, t, 0);
+  (*f) (count, bytes, NULL);
+}
+
+/* This function allocates a record list structure, and initializes fields.  */
+static unw_rec_list *
+alloc_record (unw_record_type t) 
+{
+  unw_rec_list *ptr;
+  ptr = xmalloc (sizeof (*ptr));
+  ptr->next = NULL;
+  ptr->slot_number = SLOT_NUM_NOT_SET;
+  ptr->r.type = t;
+  return ptr;
+}
+
+/* This function frees a record list structure.  */
+static void
+free_record (unw_rec_list *ptr)
+{
+  free (ptr);
+}
+
+/* This function frees an entire list of record structures.  */
+void
+free_list_records (unw_rec_list *first)
+{
+  unw_rec_list *ptr;
+  for (ptr = first; ptr != NULL; )
+    {
+      unw_rec_list *tmp = ptr;
+      ptr = ptr->next;
+      free (tmp);
+    }
+}
+
+static unw_rec_list *
+output_prologue ()
+{
+  unw_rec_list *ptr = alloc_record (prologue);
+  return ptr;
+}
+
+static unw_rec_list *
+output_prologue_gr (saved_mask, reg)
+     unsigned int saved_mask;
+     unsigned int reg;
+{
+  unw_rec_list *ptr = alloc_record (prologue_gr);
+  ptr->r.record.r.mask = saved_mask;
+  ptr->r.record.r.grsave = reg;
+  return ptr;
+}
+
+static unw_rec_list *
+output_body ()
+{
+  unw_rec_list *ptr = alloc_record (body);
+  return ptr;
+}
+
+static unw_rec_list *
+output_mem_stack_f (size)
+     unsigned int size;
+{
+  unw_rec_list *ptr = alloc_record (mem_stack_f);
+  ptr->r.record.p.size = size;
+  return ptr;
+}
+
+static unw_rec_list *
+output_mem_stack_v ()
+{
+  unw_rec_list *ptr = alloc_record (mem_stack_v);
+  return ptr;
+}
+
+static unw_rec_list *
+output_psp_gr (gr)
+     unsigned int gr;
+{
+  unw_rec_list *ptr = alloc_record (psp_gr);
+  ptr->r.record.p.gr = gr;
+  return ptr;
+}
+
+static unw_rec_list *
+output_psp_sprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (psp_sprel);
+  ptr->r.record.p.spoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_rp_when ()
+{
+  unw_rec_list *ptr = alloc_record (rp_when);
+  return ptr;
+}
+
+static unw_rec_list *
+output_rp_gr (gr)
+     unsigned int gr;
+{
+  unw_rec_list *ptr = alloc_record (rp_gr);
+  ptr->r.record.p.gr = gr;
+  return ptr;
+}
+
+static unw_rec_list *
+output_rp_br (br)
+     unsigned int br;
+{
+  unw_rec_list *ptr = alloc_record (rp_br);
+  ptr->r.record.p.br = br;
+  return ptr;
+}
+
+static unw_rec_list *
+output_rp_psprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (rp_psprel);
+  ptr->r.record.p.pspoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_rp_sprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (rp_sprel);
+  ptr->r.record.p.spoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_pfs_when ()
+{
+  unw_rec_list *ptr = alloc_record (pfs_when);
+  return ptr;
+}
+
+static unw_rec_list *
+output_pfs_gr (gr)
+     unsigned int gr;
+{
+  unw_rec_list *ptr = alloc_record (pfs_gr);
+  ptr->r.record.p.gr = gr;
+  return ptr;
+}
+
+static unw_rec_list *
+output_pfs_psprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (pfs_psprel);
+  ptr->r.record.p.pspoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_pfs_sprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (pfs_sprel);
+  ptr->r.record.p.spoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_preds_when ()
+{
+  unw_rec_list *ptr = alloc_record (preds_when);
+  return ptr;
+}
+
+static unw_rec_list *
+output_preds_gr (gr)
+     unsigned int gr;
+{
+  unw_rec_list *ptr = alloc_record (preds_gr);
+  ptr->r.record.p.gr = gr;
+  return ptr;
+}
+
+static unw_rec_list *
+output_preds_psprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (preds_psprel);
+  ptr->r.record.p.pspoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_preds_sprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (preds_sprel);
+  ptr->r.record.p.spoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_fr_mem (mask)
+     unsigned int mask;
+{
+  unw_rec_list *ptr = alloc_record (fr_mem);
+  ptr->r.record.p.rmask = mask;
+  return ptr;
+}
+
+static unw_rec_list *
+output_frgr_mem (gr_mask, fr_mask)
+     unsigned int gr_mask;
+     unsigned int fr_mask;
+{
+  unw_rec_list *ptr = alloc_record (frgr_mem);
+  ptr->r.record.p.grmask = gr_mask;
+  ptr->r.record.p.frmask = fr_mask;
+  return ptr;
+}
+
+static unw_rec_list *
+output_gr_gr (mask, reg)
+     unsigned int mask;
+     unsigned int reg;
+{
+  unw_rec_list *ptr = alloc_record (gr_gr);
+  ptr->r.record.p.grmask = mask;
+  ptr->r.record.p.gr = reg;
+  return ptr;
+}
+
+static unw_rec_list *
+output_gr_mem (mask)
+     unsigned int mask;
+{
+  unw_rec_list *ptr = alloc_record (gr_mem);
+  ptr->r.record.p.rmask = mask;
+  return ptr;
+}
+
+static unw_rec_list *
+output_br_mem (unsigned int mask)
+{
+  unw_rec_list *ptr = alloc_record (br_mem);
+  ptr->r.record.p.brmask = mask;
+  return ptr;
+}
+
+static unw_rec_list *
+output_br_gr (save_mask, reg)
+     unsigned int save_mask;
+     unsigned int reg;
+{
+  unw_rec_list *ptr = alloc_record (br_gr);
+  ptr->r.record.p.brmask = save_mask;
+  ptr->r.record.p.gr = reg;
+  return ptr;
+}
+
+static unw_rec_list *
+output_spill_base (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (spill_base);
+  ptr->r.record.p.pspoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_spill_mask ()
+{
+/* TODO - how to implement this record.... I guess GAS could fill in the
+   correct fields from the record list and construct one of these
+   after the symbols have been resolved and we know how big the
+   region is.  This could be done in fixup_unw_records.  */
+  unw_rec_list *ptr = NULL;
+  return ptr;
+}
+
+static unw_rec_list *
+output_unat_when ()
+{
+  unw_rec_list *ptr = alloc_record (unat_when);
+  return ptr;
+}
+
+static unw_rec_list *
+output_unat_gr (gr)
+     unsigned int gr;
+{
+  unw_rec_list *ptr = alloc_record (unat_gr);
+  ptr->r.record.p.gr = gr;
+  return ptr;
+}
+
+static unw_rec_list *
+output_unat_psprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (unat_psprel);
+  ptr->r.record.p.pspoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_unat_sprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (unat_sprel);
+  ptr->r.record.p.spoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_lc_when ()
+{
+  unw_rec_list *ptr = alloc_record (lc_when);
+  return ptr;
+}
+
+static unw_rec_list *
+output_lc_gr (gr)
+     unsigned int gr;
+{
+  unw_rec_list *ptr = alloc_record (lc_gr);
+  ptr->r.record.p.gr = gr;
+  return ptr;
+}
+
+static unw_rec_list *
+output_lc_psprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (lc_psprel);
+  ptr->r.record.p.pspoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_lc_sprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (lc_sprel);
+  ptr->r.record.p.spoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_fpsr_when ()
+{
+  unw_rec_list *ptr = alloc_record (fpsr_when);
+  return ptr;
+}
+
+static unw_rec_list *
+output_fpsr_gr (gr)
+     unsigned int gr;
+{
+  unw_rec_list *ptr = alloc_record (fpsr_gr);
+  ptr->r.record.p.gr = gr;
+  return ptr;
+}
+
+static unw_rec_list *
+output_fpsr_psprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (fpsr_psprel);
+  ptr->r.record.p.pspoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_fpsr_sprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (fpsr_sprel);
+  ptr->r.record.p.spoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_priunat_when_gr ()
+{
+  unw_rec_list *ptr = alloc_record (priunat_when_gr);
+  return ptr;
+}
+
+static unw_rec_list *
+output_priunat_when_mem ()
+{
+  unw_rec_list *ptr = alloc_record (priunat_when_mem);
+  return ptr;
+}
+
+static unw_rec_list *
+output_priunat_gr (gr)
+     unsigned int gr;
+{
+  unw_rec_list *ptr = alloc_record (priunat_gr);
+  ptr->r.record.p.gr = gr;
+  return ptr;
+}
+
+static unw_rec_list *
+output_priunat_psprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (priunat_psprel);
+  ptr->r.record.p.pspoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_priunat_sprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (priunat_sprel);
+  ptr->r.record.p.spoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_bsp_when ()
+{
+  unw_rec_list *ptr = alloc_record (bsp_when);
+  return ptr;
+}
+
+static unw_rec_list *
+output_bsp_gr (gr)
+     unsigned int gr;
+{
+  unw_rec_list *ptr = alloc_record (bsp_gr);
+  ptr->r.record.p.gr = gr;
+  return ptr;
+}
+
+static unw_rec_list *
+output_bsp_psprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (bsp_psprel);
+  ptr->r.record.p.pspoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_bsp_sprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (bsp_sprel);
+  ptr->r.record.p.spoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_bspstore_when ()
+{
+  unw_rec_list *ptr = alloc_record (bspstore_when);
+  return ptr;
+}
+
+static unw_rec_list *
+output_bspstore_gr (gr)
+     unsigned int gr;
+{
+  unw_rec_list *ptr = alloc_record (bspstore_gr);
+  ptr->r.record.p.gr = gr;
+  return ptr;
+}
+
+static unw_rec_list *
+output_bspstore_psprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (bspstore_psprel);
+  ptr->r.record.p.pspoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_bspstore_sprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (bspstore_sprel);
+  ptr->r.record.p.spoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_rnat_when ()
+{
+  unw_rec_list *ptr = alloc_record (rnat_when);
+  return ptr;
+}
+
+static unw_rec_list *
+output_rnat_gr (gr)
+     unsigned int gr;
+{
+  unw_rec_list *ptr = alloc_record (rnat_gr);
+  ptr->r.record.p.gr = gr;
+  return ptr;
+}
+
+static unw_rec_list *
+output_rnat_psprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (rnat_psprel);
+  ptr->r.record.p.pspoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_rnat_sprel (offset)
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (rnat_sprel);
+  ptr->r.record.p.spoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_epilogue ()
+{
+  unw_rec_list *ptr = NULL;
+  return ptr;
+}
+
+static unw_rec_list *
+output_label_state ()
+{
+  unw_rec_list *ptr = NULL;
+  return ptr;
+}
+
+static unw_rec_list *
+output_copy_state ()
+{
+  unw_rec_list *ptr = NULL;
+  return ptr;
+}
+
+static unw_rec_list *
+output_spill_psprel (reg, offset)
+     unsigned int reg;
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (spill_psprel);
+  ptr->r.record.x.reg = reg;
+  ptr->r.record.x.pspoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_spill_sprel (reg, offset)
+     unsigned int reg;
+     unsigned int offset;
+{
+  unw_rec_list *ptr = alloc_record (spill_sprel);
+  ptr->r.record.x.reg = reg;
+  ptr->r.record.x.spoff = offset;
+  return ptr;
+}
+
+static unw_rec_list *
+output_spill_psprel_p (reg, offset, predicate)
+     unsigned int reg;
+     unsigned int offset;
+     unsigned int predicate;
+{
+  unw_rec_list *ptr = alloc_record (spill_psprel_p);
+  ptr->r.record.x.reg = reg;
+  ptr->r.record.x.pspoff = offset;
+  ptr->r.record.x.qp = predicate;
+  return ptr;
+}
+
+static unw_rec_list *
+output_spill_sprel_p (reg, offset, predicate)
+     unsigned int reg;
+     unsigned int offset;
+     unsigned int predicate;
+{
+  unw_rec_list *ptr = alloc_record (spill_sprel_p);
+  ptr->r.record.x.reg = reg;
+  ptr->r.record.x.spoff = offset;
+  ptr->r.record.x.qp = predicate;
+  return ptr;
+}
+
+static unw_rec_list *
+output_spill_reg (reg, targ_reg, xy)
+     unsigned int reg;
+     unsigned int targ_reg;
+     unsigned int xy;
+{
+  unw_rec_list *ptr = alloc_record (spill_reg);
+  ptr->r.record.x.reg = reg;
+  ptr->r.record.x.treg = targ_reg;
+  ptr->r.record.x.xy = xy;
+  return ptr;
+}
+
+static unw_rec_list *
+output_spill_reg_p (reg, targ_reg, xy, predicate)
+     unsigned int reg;
+     unsigned int targ_reg;
+     unsigned int xy;
+     unsigned int predicate;
+{
+  unw_rec_list *ptr = alloc_record (spill_reg_p);
+  ptr->r.record.x.reg = reg;
+  ptr->r.record.x.treg = targ_reg;
+  ptr->r.record.x.xy = xy;
+  ptr->r.record.x.qp = predicate;
+  return ptr;
+}
+
+/* Given a unw_rec_list process the correct format with the 
+   specified function.  */
+static void
+process_one_record (ptr, f)
+     unw_rec_list *ptr;
+     vbyte_func f;
+{
+  switch (ptr->r.type) 
+    {
+      case prologue:
+      case body:
+	output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
+	break;
+      case prologue_gr:
+	output_R2_format (f, ptr->r.record.r.mask, 
+			  ptr->r.record.r.grsave, ptr->r.record.r.rlen);
+	break;
+      case mem_stack_f:
+      case mem_stack_v:
+	output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 
+			  ptr->r.record.p.size);
+	break;
+      case psp_gr:
+      case rp_gr:
+      case pfs_gr:
+      case preds_gr:
+      case unat_gr:
+      case lc_gr:
+      case fpsr_gr:
+      case priunat_gr:
+      case bsp_gr:
+      case bspstore_gr:
+      case rnat_gr:
+	output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
+	break;
+      case rp_br:
+	output_P3_format (f, rp_br, ptr->r.record.p.br);
+	break;
+      case psp_sprel:
+	output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
+	break;
+      case rp_when:
+      case pfs_when:
+      case preds_when:
+      case unat_when:
+      case lc_when:
+      case fpsr_when:
+	output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
+	break;
+      case rp_psprel:
+      case pfs_psprel:
+      case preds_psprel:
+      case unat_psprel:
+      case lc_psprel:
+      case fpsr_psprel:
+      case spill_base:
+	output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
+	break;
+      case rp_sprel:
+      case pfs_sprel:
+      case preds_sprel:
+      case unat_sprel:
+      case lc_sprel:
+      case fpsr_sprel:
+      case priunat_sprel:
+      case bsp_sprel:
+      case bspstore_sprel:
+      case rnat_sprel:
+	output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
+	break;
+      case fr_mem:
+      case gr_mem:
+	output_P6_format (f, ptr->r.type, ptr->r.record.p.rmask);
+	break;
+      case frgr_mem:
+	output_P5_format (f, ptr->r.record.p.grmask, ptr->r.record.p.frmask);
+	break;
+      case gr_gr:
+	output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
+	break;
+      case br_mem:
+	output_P1_format (f, ptr->r.record.p.brmask);
+	break;
+      case br_gr:
+	output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
+	break;
+      case spill_mask:
+	as_bad ("spill_mask record unimplemented.");
+	break;
+      case priunat_when_gr:
+      case priunat_when_mem:
+      case bsp_when:
+      case bspstore_when:
+      case rnat_when:
+	output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
+	break;
+      case priunat_psprel:
+      case bsp_psprel:
+      case bspstore_psprel:
+      case rnat_psprel:
+	output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
+	break;
+      case epilogue:
+	as_bad ("epilogue record unimplemented.");
+	break;
+      case label_state:
+	as_bad ("label_state record unimplemented.");
+	break;
+      case copy_state:
+	as_bad ("copy_state record unimplemented.");
+	break;
+      case spill_psprel:
+      case spill_sprel:
+      case spill_reg:
+      case spill_psprel_p:
+      case spill_sprel_p:
+      case spill_reg_p:
+	as_bad ("spill_* record unimplemented.");
+	break;
+      default:
+	as_bad ("record_type_not_valid");
+	break;
+    }
+}
+
+/* Given a unw_rec_list list, process all the records with 
+   the specified function.  */
+static void
+process_unw_records (list, f)
+     unw_rec_list *list;
+     vbyte_func f;
+{
+  unw_rec_list *ptr;
+  for (ptr = list; ptr; ptr = ptr->next)
+    process_one_record (ptr, f);
+}
+
+/* Determine the size of a record list in bytes.  */
+static int
+calc_record_size (list)
+     unw_rec_list *list;
+{
+  vbyte_count = 0;
+  process_unw_records (list, count_output);
+  return vbyte_count;
+}
+
+/* Given a complete record list, process any records which have
+   unresolved fields, (ie length counts for a prologue).  After
+   this has been run, all neccessary information should be available 
+   within each record to generate an image.  */
+static void
+fixup_unw_records (list)
+     unw_rec_list *list;
+{
+  unw_rec_list *ptr;
+  unsigned long first_addr = 0;
+  for (ptr = list; ptr; ptr = ptr->next)
+    {
+      if (ptr->slot_number == SLOT_NUM_NOT_SET)
+        as_bad (" Insn slot not set in unwind record.");
+      switch (ptr->r.type)
+	{
+	  case prologue:
+	  case prologue_gr:
+	  case body:
+	    {
+	      unw_rec_list *last;
+	      int size;
+	      unsigned long last_addr;
+	      first_addr = ptr->slot_number;
+	      ptr->slot_number = 0;
+	      /* Find either the next body/prologue start, or the end of 
+		 the list, and determine the size of the region.  */
+	      for (last = ptr; last->next != NULL; last = last->next)
+		if (last->next->r.type == prologue
+		    || last->next->r.type == prologue_gr
+		    || last->next->r.type == body)
+		  {
+		    break;
+		  }
+	      last_addr = last->slot_number;
+	      size = ((last_addr - first_addr) / 16) * 3 + last_addr % 4;
+	      ptr->r.record.r.rlen = size;
+	      break;
+	    }
+	  case mem_stack_f:
+	  case mem_stack_v:
+	  case rp_when:
+	  case pfs_when:
+	  case preds_when:
+	  case unat_when:
+	  case lc_when:
+	  case fpsr_when:
+	  case priunat_when_gr:
+	  case priunat_when_mem:
+	  case bsp_when:
+	  case bspstore_when:
+	  case rnat_when:
+	    {
+	      /* All the time fields.  */
+	      int x = ptr->slot_number - first_addr;
+	      ptr->r.record.p.t = (x / 16) * 3 + (ptr->slot_number % 4);
+	      break;
+	    }
+	  /* TODO. We also need to combine all the register masks into a single
+	     record. (Ie, all the save.g save.gf, save.f and save.br's)  */
+	}
+    }
+}
+
+/* Generate an unwind image from a record list.  Returns the number of
+   bytes in the resulting image. The memory image itselof is returned
+   in the 'ptr' parameter.  */
+static int
+output_unw_records (list, ptr)
+     unw_rec_list *list;
+     void **ptr;
+{
+  int size, x, extra = 0;
+  unsigned char *mem;
+
+  fixup_unw_records (list);
+  size = calc_record_size (list);
+
+  /* pad to 8 byte boundry.  */
+  x = size % 8;
+  if (x != 0)
+    extra = 8 - x;
+  /* Add 8 for the header + 8 more bytes for the personality offset.  */
+  mem = xmalloc (size + extra + 16);
+
+  vbyte_mem_ptr = mem + 8;
+  /* Clear the padding area and personality.  */
+  memset (mem + 8 + size, 0 , extra + 8);
+  /* Initialize the header area.  */
+  md_number_to_chars (mem, 1, 2);	/* version number. */
+  md_number_to_chars (mem + 2, 0x03, 2);  /* Set E and U handler bits.  */    
+
+  /* Length in double words.  */
+  md_number_to_chars (mem + 4, (size + extra) / 8, 4);
+
+  process_unw_records (list, output_vbyte_mem);
+
+  *ptr = mem;
+  return size + extra + 16;
+}
+
+static void
+dot_radix (dummy)
+     int dummy;
+{
+  int radix;
+
+  SKIP_WHITESPACE ();
+  radix = *input_line_pointer++;
+
+  if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
+    {
+      as_bad ("Radix `%c' unsupported", *input_line_pointer);
+      ignore_rest_of_line  ();
+      return;
+    }
+}
+
+/* .sbss, .bss etc. are macros that expand into ".section SECNAME".  */
+static void
+dot_special_section (which)
+     int which;
+{
+  set_section ((char *) special_section_name[which]);
+}
+
+static void
+add_unwind_entry (ptr)
+     unw_rec_list *ptr;
+{
+  if (unwind_tail)
+    unwind_tail->next = ptr;
+  else
+    unwind_list = ptr;
+  unwind_tail = ptr;
+
+  /* The current entry can in fact be a chain of unwind entries.  */
+  if (current_unwind_entry == NULL)
+    current_unwind_entry = ptr;
+}
+
+static void 
+dot_fframe (dummy)
+     int dummy;
+{
+  expressionS e;
+  parse_operand (&e);
+  
+  if (e.X_op != O_constant)
+    as_bad ("Operand to .fframe must be a constant");
+  else
+    {
+      add_unwind_entry (output_mem_stack_f (e.X_add_number));
+    }
+}
+
+static void 
+dot_vframe (dummy)
+     int dummy;
+{
+  discard_rest_of_line ();
+}
+
+static void 
+dot_save (dummy)
+     int dummy;
+{
+  expressionS e1, e2;
+  int sep;
+  int reg1, reg2;
+
+  sep = parse_operand (&e1);
+  if (sep != ',')
+    as_bad ("No second operand to .save");
+  sep = parse_operand (&e2);
+
+  reg1 = e1.X_add_number - REG_AR;
+  reg2 = e2.X_add_number - REG_GR;
+  
+  /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'.  */
+  if (e1.X_op == O_register 
+      && ((reg1 >=0 && reg1 < 128) || reg1 == REG_BR - REG_AR))
+    {
+      if (e2.X_op == O_register && reg2 >=0 && reg2 < 128)
+	{
+	  switch (reg1)
+	    {
+	      case 17:		/* ar.bsp */
+	        add_unwind_entry (output_bsp_when ());
+	        add_unwind_entry (output_bsp_gr (reg2));
+		break;
+	      case 18:		/* ar.bspstore */
+	        add_unwind_entry (output_bspstore_when ());
+	        add_unwind_entry (output_bspstore_gr (reg2));
+		break;
+	      case 19:		/* ar.rnat */
+	        add_unwind_entry (output_rnat_when ());
+	        add_unwind_entry (output_rnat_gr (reg2));
+		break;
+	      case 36:		/* ar.unat */
+	        add_unwind_entry (output_unat_when ());
+	        add_unwind_entry (output_unat_gr (reg2));
+		break;
+	      case 40:		/* ar.fpsr */
+	        add_unwind_entry (output_fpsr_when ());
+	        add_unwind_entry (output_fpsr_gr (reg2));
+		break;
+	      case 64:		/* ar.pfs */
+	        add_unwind_entry (output_pfs_when ());
+	        add_unwind_entry (output_pfs_gr (reg2));
+		break;
+	      case 65:		/* ar.lc */
+	        add_unwind_entry (output_lc_when ());
+	        add_unwind_entry (output_lc_gr (reg2));
+		break;
+	      case REG_BR - REG_AR:	/* rp  */
+		add_unwind_entry (output_rp_when ());
+		add_unwind_entry (output_rp_gr (reg2));
+		break;
+	      default:
+	        as_bad ("first operand is unknown application register");
+	    }
+	}
+      else
+	as_bad (" Second operand not a valid register");
+    }
+  else
+    as_bad ("First operand not a valid register");
+}
+
+static void 
+dot_restore (dummy)
+     int dummy;
+{
+  discard_rest_of_line ();
+}
+
+static int
+generate_unwind_image ()
+{
+  int size;
+  unsigned char *unw_rec;
+  int x;
+
+  /* Generate the unwind record.  */
+  size = output_unw_records (unwind_list, &unw_rec);
+  if (size % 4 != 0)
+    as_bad ("Unwind record is ont a multiple of 4 bytes.");
+
+  /* If there are unwind records, switch sections, and output the info.  */
+  if (size != 0)
+    {
+      int x;
+      unsigned char *where;
+      unsigned char *personality;
+      expressionS exp;
+      char *save;
+      set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND_INFO]);
+
+      /* Set expression which points to start of unwind descriptor area.  */
+      unwind_info = expr_build_dot ();
+
+      where = (unsigned char *)frag_more (size);
+
+      /* Issue a label for this address, and keep track of it to put it
+	 in the unwind section.  */
+
+      /* Copy the information from the unwind record into this section. The
+	 data is already in the correct byte order.  */
+      memcpy (where, unw_rec, size);
+      /* Add the personality address to the image.  */
+      if (personality_routine != 0)
+        {
+	  exp.X_op  = O_symbol;
+	  exp.X_add_symbol = personality_routine;
+	  exp.X_add_number = 0;
+	  fix_new_exp (frag_now, frag_now_fix () - 8, 8,
+	  		     &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB);
+	  personality_routine = 0;
+        }
+      obj_elf_previous (0);
+    }
+
+  free_list_records (unwind_list);
+  unwind_list = unwind_tail = current_unwind_entry = NULL;
+
+  return size;
+}
+
+static void 
+dot_handlerdata  (dummy)
+     int dummy;
+{
+  generate_unwind_image ();
+}
+
+static void 
+dot_unwentry (dummy)
+     int dummy;
+{
+  discard_rest_of_line ();
+}
+
+static void 
+dot_altrp (dummy)
+     int dummy;
+{
+  discard_rest_of_line ();
+}
+
+static void 
+dot_savesp (dummy)
+     int dummy;
+{
+  expressionS e1, e2;
+  int sep;
+  int reg1, val;
+
+  sep = parse_operand (&e1);
+  if (sep != ',')
+    as_bad ("No second operand to .savesp");
+  sep = parse_operand (&e2);
+
+  reg1 = e1.X_add_number - REG_AR;
+  val = e2.X_add_number;
+  
+  /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'.  */
+  if (e1.X_op == O_register 
+      && ((reg1 >=0 && reg1 < 128) || reg1 == REG_BR - REG_AR || reg1 == REG_PR - REG_AR))
+    {
+      if (e2.X_op == O_constant)
+	{
+	  switch (reg1)
+	    {
+	      case 17:		/* ar.bsp */
+	        add_unwind_entry (output_bsp_when ());
+	        add_unwind_entry (output_bsp_sprel (val));
+		break;
+	      case 18:		/* ar.bspstore */
+	        add_unwind_entry (output_bspstore_when ());
+	        add_unwind_entry (output_bspstore_sprel (val));
+		break;
+	      case 19:		/* ar.rnat */
+	        add_unwind_entry (output_rnat_when ());
+	        add_unwind_entry (output_rnat_sprel (val));
+		break;
+	      case 36:		/* ar.unat */
+	        add_unwind_entry (output_unat_when ());
+	        add_unwind_entry (output_unat_sprel (val));
+		break;
+	      case 40:		/* ar.fpsr */
+	        add_unwind_entry (output_fpsr_when ());
+	        add_unwind_entry (output_fpsr_sprel (val));
+		break;
+	      case 64:		/* ar.pfs */
+	        add_unwind_entry (output_pfs_when ());
+	        add_unwind_entry (output_pfs_sprel (val));
+		break;
+	      case 65:		/* ar.lc */
+	        add_unwind_entry (output_lc_when ());
+	        add_unwind_entry (output_lc_sprel (val));
+		break;
+	      case REG_BR - REG_AR:	/* rp  */
+		add_unwind_entry (output_rp_when ());
+		add_unwind_entry (output_rp_sprel (val));
+		break;
+	      case REG_PR - REG_AR:     /* Predicate registers.  */
+		add_unwind_entry (output_preds_when ());
+		add_unwind_entry (output_preds_sprel (val));
+		break;
+	      default:
+	        as_bad ("first operand is unknown application register");
+	    }
+	}
+      else
+	as_bad (" Second operand not a valid constant");
+    }
+  else
+    as_bad ("First operand not a valid register");
+}
+
+static void 
+dot_savepsp (dummy)
+     int dummy;
+{
+  discard_rest_of_line ();
+}
+
+static void 
+dot_saveg (dummy)
+     int dummy;
+{
+  expressionS e1, e2;
+  int sep;
+  sep = parse_operand (&e1);
+  if (sep == ',')
+    parse_operand (&e2);
+  
+  if (e1.X_op != O_constant)
+    as_bad ("First operand to .save.g must be a constant.");
+  else
+    {
+      int grmask = e1.X_add_number;
+      if (sep != ',')
+	add_unwind_entry (output_gr_mem (grmask));
+      else
+        {
+	  int reg = e2.X_add_number - REG_GR;
+	  if (e2.X_op == O_register && reg >=0 && reg < 128)
+	    add_unwind_entry (output_gr_gr (grmask, reg));
+	  else
+	    as_bad ("Second operand is an invalid register.");
+	}
+    }
+}
+
+static void 
+dot_savef (dummy)
+     int dummy;
+{
+  expressionS e1, e2;
+  int sep;
+  sep = parse_operand (&e1);
+  
+  if (e1.X_op != O_constant)
+    as_bad ("Operand to .save.f must be a constant.");
+  else
+    {
+      int frmask = e1.X_add_number;
+      add_unwind_entry (output_fr_mem (e1.X_add_number));
+    }
+}
+
+static void 
+dot_saveb (dummy)
+     int dummy;
+{
+  expressionS e1;
+  int sep;
+  sep = parse_operand (&e1);
+  
+  if (e1.X_op != O_constant)
+    as_bad ("Operand to .save.b must be a constant.");
+  else
+    {
+      int brmask = e1.X_add_number;
+      add_unwind_entry (output_br_mem (brmask));
+    }
+}
+
+static void 
+dot_savegf (dummy)
+     int dummy;
+{
+  expressionS e1, e2;
+  int sep;
+  sep = parse_operand (&e1);
+  if (sep == ',')
+    parse_operand (&e2);
+  
+  if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
+    as_bad ("Both operands of .save.gf must be constants.");
+  else
+    {
+      int grmask = e1.X_add_number;
+      int frmask = e2.X_add_number;
+      add_unwind_entry (output_frgr_mem (grmask, frmask));
+    }
+}
+
+static void 
+dot_spill (dummy)
+     int dummy;
+{
+  expressionS e;
+  parse_operand (&e);
+  
+  if (e.X_op != O_constant)
+    as_bad ("Operand to .spill must be a constant");
+  else
+    {
+      add_unwind_entry (output_spill_base (e.X_add_number));
+    }
+}
+
+static void 
+dot_unwabi (dummy)
+     int dummy;
+{
+  discard_rest_of_line ();
+}
+
+static void 
+dot_personality (dummy)
+     int dummy;
+{
+  char *name, *p, c;
+  SKIP_WHITESPACE ();
+  name = input_line_pointer;
+  c = get_symbol_end ();
+  p = input_line_pointer;
+  personality_routine = symbol_find_or_make (name);
+  *p = c;
+  SKIP_WHITESPACE ();
+  demand_empty_rest_of_line ();
+}
+
+static void
+dot_proc (dummy)
+     int dummy;
+{
+  char *name, *p, c;
+  symbolS *sym;
+
+  proc_start = expr_build_dot ();
+  /* Parse names of main and alternate entry points and mark them s
+     function symbols: */
+  while (1)
+    {
+      SKIP_WHITESPACE ();
+      name = input_line_pointer;
+      c = get_symbol_end ();
+      p = input_line_pointer;
+      sym = symbol_find_or_make (name);
+      if (proc_start == 0)
+        {
+	  proc_start = sym;
+	}
+      symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
+      *p = c;
+      SKIP_WHITESPACE ();
+      if (*input_line_pointer != ',')
+	break;
+      ++input_line_pointer;
+    }
+  demand_empty_rest_of_line ();
+  ia64_do_align (16);
+
+  unwind_list = unwind_tail = current_unwind_entry = NULL;
+  personality_routine = 0;
+}
+
+static void
+dot_body (dummy)
+     int dummy;
+{
+  unwind_prologue = 0;
+  add_unwind_entry (output_body ());
+}
+
+static void
+dot_prologue (dummy)
+     int dummy;
+{
+  unwind_prologue = 1;
+  SKIP_WHITESPACE ();
+  if (! is_end_of_line[(unsigned char) *input_line_pointer])
+    {
+      expressionS e1, e2;
+      char sep;
+      sep = parse_operand (&e1);
+      if (sep != ',')
+	as_bad ("No second operand to .prologue");
+      sep = parse_operand (&e2);
+
+      if (e1.X_op == O_constant)
+        {
+	  if (e2.X_op == O_constant)
+	    {
+	      int mask = e1.X_add_number;
+	      int reg = e2.X_add_number;
+	      add_unwind_entry (output_prologue_gr (mask, reg));
+	    }
+	  else
+	    as_bad ("Second operand not a constant");
+	}
+      else
+	as_bad ("First operand not a constant");
+    }
+  else
+    add_unwind_entry (output_prologue ());
+}
+
+static void
+dot_endp (dummy)
+     int dummy;
+{
+  expressionS e;
+  unsigned char *ptr;
+  int size;
+  long where;
+  segT saved_seg;
+  subsegT saved_subseg;
+
+  saved_seg = now_seg;
+  saved_subseg = now_subseg;
+
+  expression (&e);
+  demand_empty_rest_of_line ();
+
+  insn_group_break (1, 0, 0);
+  ia64_flush_insns ();
+
+  /* If there was a .handlerdata, we haven't generated an image yet.  */
+  if (unwind_info == 0)
+    {
+      generate_unwind_image ();
+    }
+
+  subseg_set (md.last_text_seg, 0);
+  proc_end = expr_build_dot ();
+
+  set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND]);
+  ptr = frag_more (24);
+  where = frag_now_fix () - 24;
+
+  /* Issue the values of  a) Proc Begin,  b) Proc End,  c) Unwind Record.  */
+  e.X_op = O_pseudo_fixup;
+  e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
+  e.X_add_number = 0;
+  e.X_add_symbol = proc_start;
+  ia64_cons_fix_new (frag_now, where, 8, &e);
+
+  e.X_op = O_pseudo_fixup;
+  e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
+  e.X_add_number = 0;
+  e.X_add_symbol = proc_end;
+  ia64_cons_fix_new (frag_now, where + 8, 8, &e);
+
+  if (unwind_info != 0)
+    {
+      e.X_op = O_pseudo_fixup;
+      e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
+      e.X_add_number = 0;
+      e.X_add_symbol = unwind_info;
+      ia64_cons_fix_new (frag_now, where + 16, 8, &e);
+    }
+  else
+    md_number_to_chars (ptr + 16, 0, 8);
+
+  subseg_set (saved_seg, saved_subseg);
+  proc_start = proc_end = unwind_info = 0;
+}
+
+static void
+dot_template (template)
+     int template;
+{
+  CURR_SLOT.user_template = template;
+}
+
+static void
+dot_regstk (dummy)
+     int dummy;
+{
+  int ins, locs, outs, rots;
+
+  if (is_it_end_of_statement ())
+    ins = locs = outs = rots = 0;
+  else
+    {
+      ins = get_absolute_expression ();
+      if (*input_line_pointer++ != ',')
+	goto err;
+      locs = get_absolute_expression ();
+      if (*input_line_pointer++ != ',')
+	goto err;
+      outs = get_absolute_expression ();
+      if (*input_line_pointer++ != ',')
+	goto err;
+      rots = get_absolute_expression ();
+    }
+  set_regstack (ins, locs, outs, rots);
+  return;
+
+ err:
+  as_bad ("Comma expected");
+  ignore_rest_of_line ();
+}
+
+static void
+dot_rot (type)
+     int type;
+{
+  unsigned num_regs, num_alloced = 0;
+  struct dynreg **drpp, *dr;
+  int ch, base_reg = 0;
+  char *name, *start;
+  size_t len;
+
+  switch (type)
+    {
+    case DYNREG_GR: base_reg = REG_GR + 32; break;
+    case DYNREG_FR: base_reg = REG_FR + 32; break;
+    case DYNREG_PR: base_reg = REG_P + 16; break;
+    default: break;
+    }
+
+  /* first, remove existing names from hash table: */
+  for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
+    {
+      hash_delete (md.dynreg_hash, dr->name);
+      dr->num_regs = 0;
+    }
+
+  drpp = &md.dynreg[type];
+  while (1)
+    {
+      start = input_line_pointer;
+      ch = get_symbol_end ();
+      *input_line_pointer = ch;
+      len = (input_line_pointer - start);
+
+      SKIP_WHITESPACE ();
+      if (*input_line_pointer != '[')
+	{
+	  as_bad ("Expected '['");
+	  goto err;
+	}
+      ++input_line_pointer;	/* skip '[' */
+
+      num_regs = get_absolute_expression ();
+
+      if (*input_line_pointer++ != ']')
+	{
+	  as_bad ("Expected ']'");
+	  goto err;
+	}
+      SKIP_WHITESPACE ();
+
+      num_alloced += num_regs;
+      switch (type)
+	{
+	case DYNREG_GR:
+	  if (num_alloced > md.rot.num_regs)
+	    {
+	      as_bad ("Used more than the declared %d rotating registers",
+		      md.rot.num_regs);
+	      goto err;
+	    }
+	  break;
+	case DYNREG_FR:
+	  if (num_alloced > 96)
+	    {
+	      as_bad ("Used more than the available 96 rotating registers");
+	      goto err;
+	    }
+	  break;
+	case DYNREG_PR:
+	  if (num_alloced > 48)
+	    {
+	      as_bad ("Used more than the available 48 rotating registers");
+	      goto err;
+	    }
+	  break;
+
+	default:
+	  break;
+	}
+
+      name = obstack_alloc (&notes, len + 1);
+      memcpy (name, start, len);
+      name[len] = '\0';
+
+      if (!*drpp)
+	{
+	  *drpp = obstack_alloc (&notes, sizeof (*dr));
+	  memset (*drpp, 0, sizeof (*dr));
+	}
+
+      dr = *drpp;
+      dr->name = name;
+      dr->num_regs = num_regs;
+      dr->base = base_reg;
+      drpp = &dr->next;
+      base_reg += num_regs;
+
+      if (hash_insert (md.dynreg_hash, name, dr))
+	{
+	  as_bad ("Attempt to redefine register set `%s'", name);
+	  goto err;
+	}
+
+      if (*input_line_pointer != ',')
+	break;
+      ++input_line_pointer;	/* skip comma */
+      SKIP_WHITESPACE ();
+    }
+  demand_empty_rest_of_line ();
+  return;
+
+ err:
+  ignore_rest_of_line ();
+}
+
+static void
+dot_byteorder (byteorder)
+     int byteorder;
+{
+  target_big_endian = byteorder;
+}
+
+static void
+dot_psr (dummy)
+     int dummy;
+{
+  char *option;
+  int ch;
+
+  while (1)
+    {
+      option = input_line_pointer;
+      ch = get_symbol_end ();
+      if (strcmp (option, "lsb") == 0)
+	md.flags &= ~EF_IA_64_BE;
+      else if (strcmp (option, "msb") == 0)
+	md.flags |= EF_IA_64_BE;
+      else if (strcmp (option, "abi32") == 0)
+	md.flags &= ~EF_IA_64_ABI64;
+      else if (strcmp (option, "abi64") == 0)
+	md.flags |= EF_IA_64_ABI64;
+      else
+	as_bad ("Unknown psr option `%s'", option);
+      *input_line_pointer = ch;
+
+      SKIP_WHITESPACE ();
+      if (*input_line_pointer != ',')
+	break;
+
+      ++input_line_pointer;
+      SKIP_WHITESPACE ();
+    }
+  demand_empty_rest_of_line ();
+}
+
+static void
+dot_alias (dummy)
+     int dummy;
+{
+  as_bad (".alias not implemented yet");
+}
+
+static void
+dot_ln (dummy)
+     int dummy;
+{
+  new_logical_line (0, get_absolute_expression ());
+  demand_empty_rest_of_line ();
+}
+
+static char*
+parse_section_name ()
+{
+  char *name;
+  int len;
+
+  SKIP_WHITESPACE ();
+  if (*input_line_pointer != '"')
+    {
+      as_bad ("Missing section name");
+      ignore_rest_of_line ();
+      return 0;
+    }
+  name = demand_copy_C_string (&len);
+  if (!name)
+    {
+      ignore_rest_of_line ();
+      return 0;
+    }
+  SKIP_WHITESPACE ();
+  if (*input_line_pointer != ',')
+    {
+      as_bad ("Comma expected after section name");
+      ignore_rest_of_line ();
+      return 0;
+    }
+  ++input_line_pointer;		/* skip comma */
+  return name;
+}
+
+static void
+dot_xdata (size)
+     int size;
+{
+  char *name = parse_section_name ();
+  if (!name)
+    return;
+
+  set_section (name);
+  cons (size);
+  obj_elf_previous (0);
+}
+
+/* Why doesn't float_cons() call md_cons_align() the way cons() does?  */
+static void
+stmt_float_cons (kind)
+     int kind;
+{
+  size_t size;
+
+  switch (kind)
+    {
+    case 'd': size = 8; break;
+    case 'x': size = 10; break;
+
+    case 'f':
+    default:
+      size = 4;
+      break;
+    }
+  ia64_do_align (size);
+  float_cons (kind);
+}
+
+static void
+stmt_cons_ua (size)
+     int size;
+{
+  int saved_auto_align = md.auto_align;
+
+  md.auto_align = 0;
+  cons (size);
+  md.auto_align = saved_auto_align;
+}
+
+static void
+dot_xfloat_cons (kind)
+     int kind;
+{
+  char *name = parse_section_name ();
+  if (!name)
+    return;
+
+  set_section (name);
+  stmt_float_cons (kind);
+  obj_elf_previous (0);
+}
+
+static void
+dot_xstringer (zero)
+     int zero;
+{
+  char *name = parse_section_name ();
+  if (!name)
+    return;
+
+  set_section (name);
+  stringer (zero);
+  obj_elf_previous (0);
+}
+
+static void
+dot_xdata_ua (size)
+     int size;
+{
+  int saved_auto_align = md.auto_align;
+  char *name = parse_section_name ();
+  if (!name)
+    return;
+
+  set_section (name);
+  md.auto_align = 0;
+  cons (size);
+  md.auto_align = saved_auto_align;
+  obj_elf_previous (0);
+}
+
+static void
+dot_xfloat_cons_ua (kind)
+     int kind;
+{
+  int saved_auto_align = md.auto_align;
+  char *name = parse_section_name ();
+  if (!name)
+    return;
+
+  set_section (name);
+  md.auto_align = 0;
+  stmt_float_cons (kind);
+  md.auto_align = saved_auto_align;
+  obj_elf_previous (0);
+}
+
+/* .reg.val <regname>,value */
+static void
+dot_reg_val (dummy)
+  int dummy;
+{
+  expressionS reg;
+
+  expression (&reg);
+  if (reg.X_op != O_register)
+    {
+      as_bad (_("Register name expected"));
+      ignore_rest_of_line ();
+    }
+  else if (*input_line_pointer++ != ',')
+    {
+      as_bad (_("Comma expected"));
+      ignore_rest_of_line ();
+    }
+  else 
+    {
+      valueT value = get_absolute_expression ();
+      int regno = reg.X_add_number;
+      if (regno < REG_GR || regno > REG_GR+128)
+        as_warn (_("Register value annotation ignored"));
+      else
+        {
+          gr_values[regno-REG_GR].known = 1;
+          gr_values[regno-REG_GR].value = value;
+          gr_values[regno-REG_GR].path = md.path;
+        }
+    }
+  demand_empty_rest_of_line ();
+}
+
+/* select dv checking mode 
+   .auto
+   .explicit
+   .default
+
+   A stop is inserted when changing modes 
+ */
+static void
+dot_dv_mode (type)
+  int type;
+{
+  if (md.manual_bundling)
+    as_warn (_("Directive invalid within a bundle"));
+
+  if (type == 'E' || type == 'A')
+    md.mode_explicitly_set = 0;
+  else
+    md.mode_explicitly_set = 1;
+
+  md.detect_dv = 1;
+  switch (type)
+    {
+    case 'A':
+    case 'a':
+      if (md.explicit_mode)
+        insn_group_break (1, 0, 0);
+      md.explicit_mode = 0;
+      break;
+    case 'E':
+    case 'e':
+      if (!md.explicit_mode)
+        insn_group_break (1, 0, 0);
+      md.explicit_mode = 1;
+      break;
+    default:
+    case 'd':
+      if (md.explicit_mode != md.default_explicit_mode)
+        insn_group_break (1, 0, 0);
+      md.explicit_mode = md.default_explicit_mode;
+      md.mode_explicitly_set = 0;
+      break;
+    }
+}
+
+static void
+print_prmask (mask)
+  valueT mask;
+{
+  int regno;
+  char *comma = "";
+  for (regno = 0;regno < 64;regno++)
+    {
+      if (mask & ((valueT)1<<regno))
+        {
+          fprintf (stderr, "%s p%d", comma, regno);
+          comma = ",";
+        }
+    }
+}
+
+/*
+  .pred.rel.clear [p1 [,p2 [,...]]]     (also .pred.rel "clear")
+  .pred.rel.imply p1, p2                (also .pred.rel "imply")
+  .pred.rel.mutex p1, p2 [,...]         (also .pred.rel "mutex")
+  .pred.safe_across_calls p1 [, p2 [,...]]
+ */
+static void
+dot_pred_rel (type)
+  int type;
+{
+  valueT mask = 0;
+  int count = 0;
+  int p1 = -1, p2 = -1;
+
+  if (type == 0)
+    {
+      if (*input_line_pointer != '"')
+        {
+          as_bad (_("Missing predicate relation type"));
+          ignore_rest_of_line ();
+          return;
+        }
+      else 
+        {
+          int len;
+          char *form = demand_copy_C_string (&len);
+          if (strcmp (form, "mutex") == 0) 
+            type = 'm';
+          else if (strcmp (form, "clear") == 0)
+            type = 'c';
+          else if (strcmp (form, "imply") == 0)
+            type = 'i';
+          else 
+            {
+              as_bad (_("Unrecognized predicate relation type"));
+              ignore_rest_of_line ();
+              return;
+            }
+        }
+      if (*input_line_pointer == ',')
+        ++input_line_pointer;
+      SKIP_WHITESPACE ();
+    }
+
+  SKIP_WHITESPACE ();
+  while (1)
+    {
+      valueT bit = 1;
+      int regno;
+      
+      if (toupper (*input_line_pointer) != 'P'
+          || (regno = atoi (++input_line_pointer)) < 0
+          || regno > 63)
+        {
+          as_bad (_("Predicate register expected"));
+          ignore_rest_of_line ();
+          return;
+        }
+      while (isdigit (*input_line_pointer))
+        ++input_line_pointer;
+      if (p1 == -1)
+        p1 = regno;
+      else if (p2 == -1)
+        p2 = regno;
+      bit <<= regno;
+      if (mask & bit)
+        as_warn (_("Duplicate predicate register ignored"));
+      mask |= bit; count++;
+      /* see if it's a range */
+      if (*input_line_pointer == '-')
+        {
+          valueT stop = 1;
+          ++input_line_pointer;
+
+          if (toupper (*input_line_pointer) != 'P'
+              || (regno = atoi (++input_line_pointer)) < 0
+              || regno > 63)
+            {
+              as_bad (_("Predicate register expected"));
+              ignore_rest_of_line ();
+              return;
+            }
+          while (isdigit (*input_line_pointer))
+            ++input_line_pointer;
+          stop <<= regno;
+          if (bit >= stop)
+            {
+              as_bad (_("Bad register range"));
+              ignore_rest_of_line ();
+              return;
+            }
+          while (bit < stop)
+            {
+              bit <<= 1;
+              mask |= bit; count++;
+            }
+          SKIP_WHITESPACE ();
+        }
+      if (*input_line_pointer != ',')
+        break;
+      ++input_line_pointer;
+      SKIP_WHITESPACE ();
+    }
+
+  switch (type)
+    {
+    case 'c':
+      if (count == 0)
+        mask = ~(valueT)0;
+      clear_qp_mutex (mask);
+      clear_qp_implies (mask, (valueT)0);
+      break;
+    case 'i':
+      if (count != 2 || p1 == -1 || p2 == -1)
+        as_bad (_("Predicate source and target required"));
+      else if (p1 == 0 || p2 == 0)
+        as_bad (_("Use of p0 is not valid in this context"));
+      else
+        add_qp_imply (p1, p2);
+      break;
+    case 'm':
+      if (count < 2)
+        {
+          as_bad (_("At least two PR arguments expected"));
+          break;
+        }
+      else if (mask & 1)
+        {
+          as_bad (_("Use of p0 is not valid in this context"));
+          break;
+        }
+      add_qp_mutex (mask);
+      break;
+    case 's':
+      /* note that we don't override any existing relations */
+      if (count == 0)
+        {
+          as_bad (_("At least one PR argument expected"));
+          break;
+        }
+      if (md.debug_dv)
+        {
+          fprintf (stderr, "Safe across calls: ");
+          print_prmask (mask);
+          fprintf (stderr, "\n");
+        }
+      qp_safe_across_calls = mask;
+      break;
+    }
+  demand_empty_rest_of_line ();
+}
+
+/* .entry label [, label [, ...]]
+   Hint to DV code that the given labels are to be considered entry points.
+   Otherwise, only global labels are considered entry points.
+ */
+static void
+dot_entry (dummy)
+  int dummy;
+{
+  const char *err;
+  char *name;
+  int c;
+  symbolS *symbolP;
+
+  do
+    {
+      name = input_line_pointer;
+      c = get_symbol_end ();
+      symbolP = symbol_find_or_make (name);
+
+      err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
+      if (err)
+        as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
+                    name, err);
+
+      *input_line_pointer = c;
+      SKIP_WHITESPACE ();
+      c = *input_line_pointer;
+      if (c == ',')
+	{
+	  input_line_pointer++;
+	  SKIP_WHITESPACE ();
+	  if (*input_line_pointer == '\n')
+	    c = '\n';
+	}
+    }
+  while (c == ',');
+
+  demand_empty_rest_of_line ();
+}
+
+/* .mem.offset offset, base 
+   "base" is used to distinguish between offsets from a different base.
+ */
+static void
+dot_mem_offset (dummy)
+  int dummy;
+{
+  md.mem_offset.hint = 1;
+  md.mem_offset.offset = get_absolute_expression ();
+  if (*input_line_pointer != ',')
+    {
+      as_bad (_("Comma expected"));
+      ignore_rest_of_line ();
+      return;
+    }
+  ++input_line_pointer;
+  md.mem_offset.base = get_absolute_expression ();
+  demand_empty_rest_of_line ();
+}
+
+/* ia64-specific pseudo-ops: */
+const pseudo_typeS md_pseudo_table[] =
+  {
+    { "radix", dot_radix, 0 },
+    { "lcomm", s_lcomm_bytes, 1 },
+    { "bss", dot_special_section, SPECIAL_SECTION_BSS },
+    { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
+    { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
+    { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
+    { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
+    { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
+    { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
+    { "proc", dot_proc, 0 },
+    { "body", dot_body, 0 },
+    { "prologue", dot_prologue, 0 },
+    { "endp", dot_endp },
+    { "file", dwarf2_directive_file },
+    { "loc", dwarf2_directive_loc },
+
+    { "fframe", dot_fframe },
+    { "vframe", dot_vframe },
+    { "save", dot_save },
+    { "restore", dot_restore },
+    { "handlerdata", dot_handlerdata },
+    { "unwentry", dot_unwentry },
+    { "alprp", dot_altrp },
+    { "savesp", dot_savesp },
+    { "savepsp", dot_savepsp },
+    { "save.g", dot_saveg },
+    { "save.f", dot_savef },
+    { "save.b", dot_saveb },
+    { "save.gf", dot_savegf },
+    { "spill", dot_spill },
+    { "unwabi", dot_unwabi },
+    { "personality", dot_personality },
+#if 0
+    { "estate", dot_estate },
+#endif
+    { "mii", dot_template, 0x0 },
+    { "mli", dot_template, 0x2 }, /* old format, for compatibility */
+    { "mlx", dot_template, 0x2 },
+    { "mmi", dot_template, 0x4 },
+    { "mfi", dot_template, 0x6 },
+    { "mmf", dot_template, 0x7 },
+    { "mib", dot_template, 0x8 },
+    { "mbb", dot_template, 0x9 },
+    { "bbb", dot_template, 0xb },
+    { "mmb", dot_template, 0xc },
+    { "mfb", dot_template, 0xe },
+#if 0
+    { "lb", dot_scope, 0 },
+    { "le", dot_scope, 1 },
+#endif
+    { "align", s_align_bytes, 0 },
+    { "regstk", dot_regstk, 0 },
+    { "rotr", dot_rot, DYNREG_GR },
+    { "rotf", dot_rot, DYNREG_FR },
+    { "rotp", dot_rot, DYNREG_PR },
+    { "lsb", dot_byteorder, 0 },
+    { "msb", dot_byteorder, 1 },
+    { "psr", dot_psr, 0 },
+    { "alias", dot_alias, 0 },
+    { "ln", dot_ln, 0 },		/* source line info (for debugging) */
+
+    { "xdata1", dot_xdata, 1 },
+    { "xdata2", dot_xdata, 2 },
+    { "xdata4", dot_xdata, 4 },
+    { "xdata8", dot_xdata, 8 },
+    { "xreal4", dot_xfloat_cons, 'f' },
+    { "xreal8", dot_xfloat_cons, 'd' },
+    { "xreal10", dot_xfloat_cons, 'x' },
+    { "xstring", dot_xstringer, 0 },
+    { "xstringz", dot_xstringer, 1 },
+
+    /* unaligned versions: */
+    { "xdata2.ua", dot_xdata_ua, 2 },
+    { "xdata4.ua", dot_xdata_ua, 4 },
+    { "xdata8.ua", dot_xdata_ua, 8 },
+    { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
+    { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
+    { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
+
+    /* annotations/DV checking support */
+    { "entry", dot_entry, 0 },
+    { "mem.offset", dot_mem_offset },
+    { "pred.rel", dot_pred_rel, 0 },
+    { "pred.rel.clear", dot_pred_rel, 'c' },
+    { "pred.rel.imply", dot_pred_rel, 'i' },
+    { "pred.rel.mutex", dot_pred_rel, 'm' },
+    { "pred.safe_across_calls", dot_pred_rel, 's' },
+    { "reg.val", dot_reg_val },
+    { "auto", dot_dv_mode, 'a' },
+    { "explicit", dot_dv_mode, 'e' },
+    { "default", dot_dv_mode, 'd' },
+
+    { NULL, 0, 0 }
+  };
+
+static const struct pseudo_opcode
+  {
+    const char *name;
+    void (*handler) (int);
+    int arg;
+  }
+pseudo_opcode[] =
+  {
+    /* these are more like pseudo-ops, but don't start with a dot */
+    { "data1", cons, 1 },
+    { "data2", cons, 2 },
+    { "data4", cons, 4 },
+    { "data8", cons, 8 },
+    { "real4", stmt_float_cons, 'f' },
+    { "real8", stmt_float_cons, 'd' },
+    { "real10", stmt_float_cons, 'x' },
+    { "string", stringer, 0 },
+    { "stringz", stringer, 1 },
+
+    /* unaligned versions: */
+    { "data2.ua", stmt_cons_ua, 2 },
+    { "data4.ua", stmt_cons_ua, 4 },
+    { "data8.ua", stmt_cons_ua, 8 },
+    { "real4.ua", float_cons, 'f' },
+    { "real8.ua", float_cons, 'd' },
+    { "real10.ua", float_cons, 'x' },
+  };
+
+/* Declare a register by creating a symbol for it and entering it in
+   the symbol table.  */
+static symbolS*
+declare_register (name, regnum)
+     const char *name;
+     int regnum;
+{
+  const char *err;
+  symbolS *sym;
+
+  sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
+
+  err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
+  if (err)
+    as_fatal ("Inserting \"%s\" into register table failed: %s",
+	      name, err);
+
+  return sym;
+}
+
+static void
+declare_register_set (prefix, num_regs, base_regnum)
+     const char *prefix;
+     int num_regs;
+     int base_regnum;
+{
+  char name[8];
+  int i;
+
+  for (i = 0; i < num_regs; ++i)
+    {
+      sprintf (name, "%s%u", prefix, i);
+      declare_register (name, base_regnum + i);
+    }
+}
+
+static unsigned int
+operand_width (opnd)
+     enum ia64_opnd opnd;
+{
+  const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
+  unsigned int bits = 0;
+  int i;
+
+  bits = 0;
+  for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
+    bits += odesc->field[i].bits;
+
+  return bits;
+}
+
+static int
+operand_match (idesc, index, e)
+     const struct ia64_opcode *idesc;
+     int index;
+     expressionS *e;
+{
+  enum ia64_opnd opnd = idesc->operands[index];
+  int bits, relocatable = 0;
+  struct insn_fix *fix;
+  bfd_signed_vma val;
+
+  switch (opnd)
+    {
+      /* constants: */
+
+    case IA64_OPND_AR_CCV:
+      if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
+	return 1;
+      break;
+
+    case IA64_OPND_AR_PFS:
+      if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
+	return 1;
+      break;
+
+    case IA64_OPND_GR0:
+      if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
+	return 1;
+      break;
+
+    case IA64_OPND_IP:
+      if (e->X_op == O_register && e->X_add_number == REG_IP)
+	return 1;
+      break;
+
+    case IA64_OPND_PR:
+      if (e->X_op == O_register && e->X_add_number == REG_PR)
+	return 1;
+      break;
+
+    case IA64_OPND_PR_ROT:
+      if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
+	return 1;
+      break;
+
+    case IA64_OPND_PSR:
+      if (e->X_op == O_register && e->X_add_number == REG_PSR)
+	return 1;
+      break;
+
+    case IA64_OPND_PSR_L:
+      if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
+	return 1;
+      break;
+
+    case IA64_OPND_PSR_UM:
+      if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
+	return 1;
+      break;
+
+    case IA64_OPND_C1:
+      if (e->X_op == O_constant && e->X_add_number == 1)
+	return 1;
+      break;
+
+    case IA64_OPND_C8:
+      if (e->X_op == O_constant && e->X_add_number == 8)
+	return 1;
+      break;
+
+    case IA64_OPND_C16:
+      if (e->X_op == O_constant && e->X_add_number == 16)
+	return 1;
+      break;
+
+      /* register operands: */
+
+    case IA64_OPND_AR3:
+      if (e->X_op == O_register && e->X_add_number >= REG_AR
+	  && e->X_add_number < REG_AR + 128)
+	return 1;
+      break;
+
+    case IA64_OPND_B1:
+    case IA64_OPND_B2:
+      if (e->X_op == O_register && e->X_add_number >= REG_BR
+	  && e->X_add_number < REG_BR + 8)
+	return 1;
+      break;
+
+    case IA64_OPND_CR3:
+      if (e->X_op == O_register && e->X_add_number >= REG_CR
+	  && e->X_add_number < REG_CR + 128)
+	return 1;
+      break;
+
+    case IA64_OPND_F1:
+    case IA64_OPND_F2:
+    case IA64_OPND_F3:
+    case IA64_OPND_F4:
+      if (e->X_op == O_register && e->X_add_number >= REG_FR
+	  && e->X_add_number < REG_FR + 128)
+	return 1;
+      break;
+
+    case IA64_OPND_P1:
+    case IA64_OPND_P2:
+      if (e->X_op == O_register && e->X_add_number >= REG_P
+	  && e->X_add_number < REG_P + 64)
+	return 1;
+      break;
+
+    case IA64_OPND_R1:
+    case IA64_OPND_R2:
+    case IA64_OPND_R3:
+      if (e->X_op == O_register && e->X_add_number >= REG_GR
+	  && e->X_add_number < REG_GR + 128)
+	return 1;
+      break;
+
+    case IA64_OPND_R3_2:
+      if (e->X_op == O_register && e->X_add_number >= REG_GR
+	  && e->X_add_number < REG_GR + 4)
+	return 1;
+      break;
+
+      /* indirect operands: */
+    case IA64_OPND_CPUID_R3:
+    case IA64_OPND_DBR_R3:
+    case IA64_OPND_DTR_R3:
+    case IA64_OPND_ITR_R3:
+    case IA64_OPND_IBR_R3:
+    case IA64_OPND_MSR_R3:
+    case IA64_OPND_PKR_R3:
+    case IA64_OPND_PMC_R3:
+    case IA64_OPND_PMD_R3:
+    case IA64_OPND_RR_R3:
+      if (e->X_op == O_index && e->X_op_symbol
+	  && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
+	      == opnd - IA64_OPND_CPUID_R3))
+	return 1;
+      break;
+
+    case IA64_OPND_MR3:
+      if (e->X_op == O_index && !e->X_op_symbol)
+	return 1;
+      break;
+
+      /* immediate operands: */
+    case IA64_OPND_CNT2a:
+    case IA64_OPND_LEN4:
+    case IA64_OPND_LEN6:
+      bits = operand_width (idesc->operands[index]);
+      if (e->X_op == O_constant
+	  && (bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
+	return 1;
+      break;
+
+    case IA64_OPND_CNT2b:
+      if (e->X_op == O_constant
+	  && (bfd_vma) (e->X_add_number - 1) < 3)
+	return 1;
+      break;
+
+    case IA64_OPND_CNT2c:
+      val = e->X_add_number;
+      if (e->X_op == O_constant
+	  && (val == 0 || val == 7 || val == 15 || val == 16))
+	return 1;
+      break;
+
+    case IA64_OPND_SOR:
+      /* SOR must be an integer multiple of 8 */
+      if (e->X_add_number & 0x7)
+	break;
+    case IA64_OPND_SOF:
+    case IA64_OPND_SOL:
+      if (e->X_op == O_constant &&
+	  (bfd_vma) e->X_add_number <= 96)
+	return 1;
+      break;
+
+    case IA64_OPND_IMMU62:
+      if (e->X_op == O_constant)
+        {
+	  if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
+            return 1;
+        }
+      else 
+        {
+          /* FIXME -- need 62-bit relocation type */
+          as_bad (_("62-bit relocation not yet implemented"));
+        }
+      break;
+
+    case IA64_OPND_IMMU64:
+      if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
+	  || e->X_op == O_subtract)
+	{
+	  fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
+	  fix->code = BFD_RELOC_IA64_IMM64;
+	  if (e->X_op != O_subtract)
+	    {
+	      fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
+	      if (e->X_op == O_pseudo_fixup)
+		e->X_op = O_symbol;
+	    }
+
+	  fix->opnd = idesc->operands[index];
+	  fix->expr = *e;
+	  fix->is_pcrel = 0;
+	  ++CURR_SLOT.num_fixups;
+	  return 1;
+	}
+      else if (e->X_op == O_constant)
+	return 1;
+      break;
+
+    case IA64_OPND_CCNT5:
+    case IA64_OPND_CNT5:
+    case IA64_OPND_CNT6:
+    case IA64_OPND_CPOS6a:
+    case IA64_OPND_CPOS6b:
+    case IA64_OPND_CPOS6c:
+    case IA64_OPND_IMMU2:
+    case IA64_OPND_IMMU7a:
+    case IA64_OPND_IMMU7b:
+    case IA64_OPND_IMMU9:
+    case IA64_OPND_IMMU21:
+    case IA64_OPND_IMMU24:
+    case IA64_OPND_MBTYPE4:
+    case IA64_OPND_MHTYPE8:
+    case IA64_OPND_POS6:
+      bits = operand_width (idesc->operands[index]);
+      if (e->X_op == O_constant
+	  && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
+	return 1;
+      break;
+
+    case IA64_OPND_IMM44:
+      /* least 16 bits must be zero */
+      if ((e->X_add_number & 0xffff) != 0)
+        as_warn (_("lower 16 bits of mask ignored"));
+
+      if (e->X_op == O_constant
+	  && ((e->X_add_number >= 0
+	       && e->X_add_number < ((bfd_vma) 1 << 44))
+	      || (e->X_add_number < 0
+		  && -e->X_add_number <= ((bfd_vma) 1 << 44))))
+        {
+          /* sign-extend */
+          if (e->X_add_number >= 0
+              && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
+            {
+              e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
+            }
+          return 1;
+        }
+      break;
+
+    case IA64_OPND_IMM17:
+      /* bit 0 is a don't care (pr0 is hardwired to 1) */
+      if (e->X_op == O_constant
+	  && ((e->X_add_number >= 0
+	       && e->X_add_number < ((bfd_vma) 1 << 17))
+	      || (e->X_add_number < 0
+		  && -e->X_add_number <= ((bfd_vma) 1 << 17))))
+        {
+          /* sign-extend */
+          if (e->X_add_number >= 0
+              && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
+            {
+              e->X_add_number |= ~(((bfd_vma)1 << 17) - 1);
+            }
+          return 1;
+        }
+      break;
+
+    case IA64_OPND_IMM14:
+    case IA64_OPND_IMM22:
+      relocatable = 1;
+    case IA64_OPND_IMM1:
+    case IA64_OPND_IMM8:
+    case IA64_OPND_IMM8U4:
+    case IA64_OPND_IMM8M1:
+    case IA64_OPND_IMM8M1U4:
+    case IA64_OPND_IMM8M1U8:
+    case IA64_OPND_IMM9a:
+    case IA64_OPND_IMM9b:
+      bits = operand_width (idesc->operands[index]);
+      if (relocatable && (e->X_op == O_symbol
+			  || e->X_op == O_subtract
+			  || e->X_op == O_pseudo_fixup))
+	{
+	  fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
+
+	  if (idesc->operands[index] == IA64_OPND_IMM14)
+	    fix->code = BFD_RELOC_IA64_IMM14;
+	  else
+	    fix->code = BFD_RELOC_IA64_IMM22;
+
+	  if (e->X_op != O_subtract)
+	    {
+	      fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
+	      if (e->X_op == O_pseudo_fixup)
+		e->X_op = O_symbol;
+	    }
+
+	  fix->opnd = idesc->operands[index];
+	  fix->expr = *e;
+	  fix->is_pcrel = 0;
+	  ++CURR_SLOT.num_fixups;
+	  return 1;
+	}
+      else if (e->X_op != O_constant
+	       && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
+	return 0;
+
+      if (opnd == IA64_OPND_IMM8M1U4)
+	{
+	  /* Zero is not valid for unsigned compares that take an adjusted
+	     constant immediate range.  */
+	  if (e->X_add_number == 0)
+	    return 0;
+
+	  /* Sign-extend 32-bit unsigned numbers, so that the following range
+	     checks will work.  */
+	  val = e->X_add_number;
+	  if (((val & (~(bfd_vma)0 << 32)) == 0)
+	      && ((val & ((bfd_vma)1 << 31)) != 0))
+	    val = ((val << 32) >> 32);
+
+	  /* Check for 0x100000000.  This is valid because
+	     0x100000000-1 is the same as ((uint32_t) -1).  */
+	  if (val == ((bfd_signed_vma) 1 << 32))
+	    return 1;
+
+	  val = val - 1;
+	}
+      else if (opnd == IA64_OPND_IMM8M1U8)
+	{
+	  /* Zero is not valid for unsigned compares that take an adjusted
+	     constant immediate range.  */
+	  if (e->X_add_number == 0)
+	    return 0;
+
+	  /* Check for 0x10000000000000000.  */
+	  if (e->X_op == O_big)
+	    {
+	      if (generic_bignum[0] == 0
+		  && generic_bignum[1] == 0
+		  && generic_bignum[2] == 0
+		  && generic_bignum[3] == 0
+		  && generic_bignum[4] == 1)
+		return 1;
+	      else
+		return 0;
+	    }
+	  else
+	    val = e->X_add_number - 1;
+	}
+      else if (opnd == IA64_OPND_IMM8M1)
+	val = e->X_add_number - 1;
+      else if (opnd == IA64_OPND_IMM8U4)
+	{
+	  /* Sign-extend 32-bit unsigned numbers, so that the following range
+	     checks will work.  */
+	  val = e->X_add_number;
+	  if (((val & (~(bfd_vma)0 << 32)) == 0)
+	      && ((val & ((bfd_vma)1 << 31)) != 0))
+	    val = ((val << 32) >> 32);
+	}
+      else
+	val = e->X_add_number;
+
+      if ((val >= 0 && val < ((bfd_vma) 1 << (bits - 1)))
+	  || (val < 0 && -val <= ((bfd_vma) 1 << (bits - 1))))
+	return 1;
+      break;
+
+    case IA64_OPND_INC3:
+      /* +/- 1, 4, 8, 16 */
+      val = e->X_add_number;
+      if (val < 0)
+	val = -val;
+      if (e->X_op == O_constant
+	  && (val == 1 || val == 4 || val == 8 || val == 16))
+	return 1;
+      break;
+
+    case IA64_OPND_TGT25:
+    case IA64_OPND_TGT25b:
+    case IA64_OPND_TGT25c:
+    case IA64_OPND_TGT64:
+      if (e->X_op == O_symbol)
+	{
+	  fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
+	  if (opnd == IA64_OPND_TGT25)
+	    fix->code = BFD_RELOC_IA64_PCREL21F;
+	  else if (opnd == IA64_OPND_TGT25b)
+	    fix->code = BFD_RELOC_IA64_PCREL21M;
+	  else if (opnd == IA64_OPND_TGT25c)
+	    fix->code = BFD_RELOC_IA64_PCREL21B;
+          else 
+            /* FIXME -- use appropriate relocation type */
+            as_bad (_("long branch targets not implemented"));
+	  fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
+	  fix->opnd = idesc->operands[index];
+	  fix->expr = *e;
+	  fix->is_pcrel = 1;
+	  ++CURR_SLOT.num_fixups;
+	  return 1;
+	}
+    case IA64_OPND_TAG13:
+    case IA64_OPND_TAG13b:
+      switch (e->X_op)
+	{
+	case O_constant:
+	  return 1;
+
+	case O_symbol:
+	  fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
+	  fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, 0);
+	  fix->opnd = idesc->operands[index];
+	  fix->expr = *e;
+	  fix->is_pcrel = 1;
+	  ++CURR_SLOT.num_fixups;
+	  return 1;
+
+	default:
+	  break;
+	}
+      break;
+
+    default:
+      break;
+    }
+  return 0;
+}
+
+static int
+parse_operand (e)
+     expressionS *e;
+{
+  int sep = '\0';
+
+  memset (e, 0, sizeof (*e));
+  e->X_op = O_absent;
+  SKIP_WHITESPACE ();
+  if (*input_line_pointer != '}')
+    expression (e);
+  sep = *input_line_pointer++;
+
+  if (sep == '}')
+    {
+      if (!md.manual_bundling)
+	as_warn ("Found '}' when manual bundling is off");
+      else
+	CURR_SLOT.manual_bundling_off = 1;
+      md.manual_bundling = 0;
+      sep = '\0';
+    }
+  return sep;
+}
+
+/* Returns the next entry in the opcode table that matches the one in
+   IDESC, and frees the entry in IDESC.  If no matching entry is
+   found, NULL is returned instead. */
+
+static struct ia64_opcode *
+get_next_opcode (struct ia64_opcode *idesc)
+{
+  struct ia64_opcode *next = ia64_find_next_opcode (idesc);
+  ia64_free_opcode (idesc);
+  return next;
+}
+
+/* Parse the operands for the opcode and find the opcode variant that
+   matches the specified operands, or NULL if no match is possible.  */
+static struct ia64_opcode*
+parse_operands (idesc)
+     struct ia64_opcode *idesc;
+{
+  int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
+  int sep = 0;
+  enum ia64_opnd expected_operand = IA64_OPND_NIL;
+  char mnemonic[129];
+  char *first_arg = 0, *end, *saved_input_pointer;
+  unsigned int sof;
+
+  assert (strlen (idesc->name) <= 128);
+
+  strcpy (mnemonic, idesc->name);
+  if (idesc->operands[2] == IA64_OPND_SOF)
+    {
+      /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
+	 can't parse the first operand until we have parsed the
+	 remaining operands of the "alloc" instruction.  */
+      SKIP_WHITESPACE ();
+      first_arg = input_line_pointer;
+      end = strchr (input_line_pointer, '=');
+      if (!end)
+	{
+	  as_bad ("Expected separator `='");
+	  return 0;
+	}
+      input_line_pointer = end + 1;
+      ++i;
+      ++num_outputs;
+    }
+
+  for (; i < NELEMS (CURR_SLOT.opnd); ++i)
+    {
+      sep = parse_operand (CURR_SLOT.opnd + i);
+      if (CURR_SLOT.opnd[i].X_op == O_absent)
+	break;
+
+      ++num_operands;
+
+      if (sep != '=' && sep != ',')
+	break;
+
+      if (sep == '=')
+	{
+	  if (num_outputs > 0)
+	    as_bad ("Duplicate equal sign (=) in instruction");
+	  else
+	    num_outputs = i + 1;
+	}
+    }
+  if (sep != '\0')
+    {
+      as_bad ("Illegal operand separator `%c'", sep);
+      return 0;
+    }
+  
+  if (idesc->operands[2] == IA64_OPND_SOF)
+    {
+      /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
+      know (strcmp (idesc->name, "alloc") == 0);
+      if (num_operands == 5 /* first_arg not included in this count! */
+	  && CURR_SLOT.opnd[2].X_op == O_constant
+	  && CURR_SLOT.opnd[3].X_op == O_constant
+	  && CURR_SLOT.opnd[4].X_op == O_constant
+	  && CURR_SLOT.opnd[5].X_op == O_constant)
+	{
+	  sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
+			      CURR_SLOT.opnd[3].X_add_number,
+			      CURR_SLOT.opnd[4].X_add_number,
+			      CURR_SLOT.opnd[5].X_add_number);
+
+	  /* now we can parse the first arg: */
+	  saved_input_pointer = input_line_pointer;
+	  input_line_pointer = first_arg;
+	  sep = parse_operand (CURR_SLOT.opnd + 0);
+	  if (sep != '=')
+	    --num_outputs;	/* force error */
+	  input_line_pointer = saved_input_pointer;
+
+	  CURR_SLOT.opnd[2].X_add_number = sof;
+	  CURR_SLOT.opnd[3].X_add_number
+	    = sof - CURR_SLOT.opnd[4].X_add_number;
+	  CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
+	}
+    }
+
+  highest_unmatched_operand = 0;
+  expected_operand = idesc->operands[0];
+  for (; idesc; idesc = get_next_opcode (idesc))
+    {
+      if (num_outputs != idesc->num_outputs)
+	continue;		/* mismatch in # of outputs */
+
+      CURR_SLOT.num_fixups = 0;
+      for (i = 0; i < num_operands && idesc->operands[i]; ++i)
+	if (!operand_match (idesc, i, CURR_SLOT.opnd + i))
+	  break;
+
+      if (i != num_operands)
+	{
+	  if (i > highest_unmatched_operand)
+	    {
+	      highest_unmatched_operand = i;
+	      expected_operand = idesc->operands[i];
+	    }
+	  continue;
+	}
+
+      if (num_operands < NELEMS (idesc->operands)
+	  && idesc->operands[num_operands])
+	continue;		/* mismatch in number of arguments */
+
+      break;
+    }
+  if (!idesc)
+    {
+      if (expected_operand)
+	as_bad ("Operand %u of `%s' should be %s",
+		highest_unmatched_operand + 1, mnemonic,
+		elf64_ia64_operands[expected_operand].desc);
+      else
+	as_bad ("Operand mismatch");
+      return 0;
+    }
+  return idesc;
+}
+
+static void
+build_insn (slot, insnp)
+     struct slot *slot;
+     bfd_vma *insnp;
+{
+  const struct ia64_operand *odesc, *o2desc;
+  struct ia64_opcode *idesc = slot->idesc;
+  bfd_signed_vma insn, val;
+  const char *err;
+  int i;
+
+  insn = idesc->opcode | slot->qp_regno;
+
+  for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
+    {
+      if (idesc->operands[i] == IA64_OPND_IMMU64)
+	{
+	  val = slot->opnd[i].X_add_number;
+	  *insnp++ = (val >> 22) & 0x1ffffffffffLL;
+	  insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
+		   | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
+		   | (((val >> 63) & 0x1) << 36));
+	}
+      else if (idesc->operands[i] == IA64_OPND_IMMU62)
+        {
+          val = slot->opnd[i].X_add_number & 0x3fffffffffffffffULL;
+          if (val != slot->opnd[i].X_add_number)
+            as_warn (_("Value truncated to 62 bits"));
+          *insnp++ = (val >> 21) & 0x1ffffffffffLL;
+          insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
+        }
+      else if (idesc->operands[i] == IA64_OPND_TGT64)
+        {
+          // FIXME -- need to implement the target address encoding properly
+          as_bad (_("long branch target encoding not implemented"));
+          *insnp++ = 0;
+        }
+      else if (slot->opnd[i].X_op == O_register
+	       || slot->opnd[i].X_op == O_constant
+	       || slot->opnd[i].X_op == O_index
+	       || slot->opnd[i].X_op == O_big)
+	{
+	  if (slot->opnd[i].X_op == O_big)
+	    {
+	      /* This must be the value 0x10000000000000000.  */
+	      assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
+	      val = 0;
+	    }
+	  else
+	    val = slot->opnd[i].X_add_number;
+
+	  switch (idesc->operands[i])
+	    {
+	    case IA64_OPND_AR3:				val -= REG_AR; break;
+	    case IA64_OPND_B1: case IA64_OPND_B2:	val -= REG_BR; break;
+	    case IA64_OPND_CR3:				val -= REG_CR; break;
+	    case IA64_OPND_F1: case IA64_OPND_F2:
+	    case IA64_OPND_F3: case IA64_OPND_F4:	val -= REG_FR; break;
+	    case IA64_OPND_P1: case IA64_OPND_P2:	val -= REG_P;  break;
+
+	    case IA64_OPND_R1:	     case IA64_OPND_R2:
+	    case IA64_OPND_R3:       case IA64_OPND_R3_2:
+	    case IA64_OPND_CPUID_R3: case IA64_OPND_DBR_R3:
+	    case IA64_OPND_DTR_R3:   case IA64_OPND_ITR_R3:
+	    case IA64_OPND_IBR_R3:   case IA64_OPND_MR3:
+	    case IA64_OPND_MSR_R3:   case IA64_OPND_PKR_R3:
+	    case IA64_OPND_PMC_R3:   case IA64_OPND_PMD_R3:
+	    case IA64_OPND_RR_R3:    
+	      val -= REG_GR;
+	      break;
+
+	    default:
+	      break;
+	    }
+	  odesc = elf64_ia64_operands + idesc->operands[i];
+	  err = (*odesc->insert) (odesc, val, &insn);
+	  if (err)
+	    as_bad_where (slot->src_file, slot->src_line,
+			  "Bad operand value: %s", err);
+	  if (idesc->flags & IA64_OPCODE_PSEUDO)
+	    {
+	      if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
+		  && odesc == elf64_ia64_operands + IA64_OPND_F3)
+		{
+		  o2desc = elf64_ia64_operands + IA64_OPND_F2;
+		  (*o2desc->insert) (o2desc, val, &insn);
+		      
+		}
+	      if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
+		  && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
+		      || odesc == elf64_ia64_operands + IA64_OPND_POS6))
+		{
+		  o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
+		  (*o2desc->insert) (o2desc, 64 - val, &insn);
+		}
+	    }
+	}
+    }
+  *insnp = insn;
+}
+
+static void
+emit_one_bundle ()
+{
+  unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
+  unsigned int manual_bundling = 0;
+  enum ia64_unit required_unit, insn_unit = 0;
+  enum ia64_insn_type type[3], insn_type;
+  unsigned int template, orig_template;
+  bfd_vma insn[3] = {-1, -1, -1};
+  struct ia64_opcode *idesc;
+  int end_of_insn_group = 0, user_template = -1;
+  int n, i, j, first, curr;
+  bfd_vma t0 = 0, t1 = 0;
+  struct label_fix *lfix;
+  struct insn_fix *ifix;
+  char mnemonic[16];
+  fixS *fix;
+  char *f;
+
+  first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
+  know (first >= 0 & first < NUM_SLOTS);
+  n = MIN (3, md.num_slots_in_use);
+
+  /* Determine template: user user_template if specified, best match
+     otherwise: */
+
+  if (md.slot[first].user_template >= 0)
+    user_template = template = md.slot[first].user_template;
+  else
+    {
+      /* auto select appropriate template */
+      memset (type, 0, sizeof (type));
+      curr = first;
+      for (i = 0; i < n; ++i)
+	{
+	  type[i] = md.slot[curr].idesc->type;
+	  curr = (curr + 1) % NUM_SLOTS;
+	}
+      template = best_template[type[0]][type[1]][type[2]];
+    }
+
+  /* initialize instructions with appropriate nops: */
+  for (i = 0; i < 3; ++i)
+    insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
+
+  f = frag_more (16);
+
+  /* now fill in slots with as many insns as possible: */
+  curr = first;
+  idesc = md.slot[curr].idesc;
+  end_of_insn_group = 0;
+  for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
+    {
+      if (idesc->flags & IA64_OPCODE_SLOT2)
+	{
+	  if (manual_bundling && i != 2)
+	    as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
+			  "`%s' must be last in bundle", idesc->name);
+	  else
+	    i = 2;
+	}
+      if (idesc->flags & IA64_OPCODE_LAST)
+	{
+	  int required_slot, required_template;
+
+	  /* If we need a stop bit after an M slot, our only choice is
+	     template 5 (M;;MI).  If we need a stop bit after a B
+	     slot, our only choice is to place it at the end of the
+	     bundle, because the only available templates are MIB,
+	     MBB, BBB, MMB, and MFB.  We don't handle anything other
+	     than M and B slots because these are the only kind of
+	     instructions that can have the IA64_OPCODE_LAST bit set.  */
+	  required_template = template;
+	  switch (idesc->type)
+	    {
+	    case IA64_TYPE_M:
+	      required_slot = 0;
+	      required_template = 5;
+	      break;
+
+	    case IA64_TYPE_B:
+	      required_slot = 2;
+	      break;
+
+	    default:
+	      as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
+			    "Internal error: don't know how to force %s to end"
+			    "of instruction group", idesc->name);
+	      required_slot = i;
+	      break;
+	    }
+	  if (manual_bundling && i != required_slot)
+	    as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
+			  "`%s' must be last in instruction group",
+			  idesc->name);
+	  if (required_slot < i)
+	    /* Can't fit this instruction.  */
+	    break;
+
+	  i = required_slot;
+	  if (required_template != template)
+	    {
+	      /* If we switch the template, we need to reset the NOPs
+	         after slot i.  The slot-types of the instructions ahead
+	         of i never change, so we don't need to worry about
+	         changing NOPs in front of this slot.  */
+	      for (j = i; j < 3; ++j)
+	        insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
+	    }
+	  template = required_template;
+	}
+      if (curr != first && md.slot[curr].label_fixups)
+	{
+	  if (manual_bundling_on)
+	    as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
+			  "Label must be first in a bundle");
+	  /* This insn must go into the first slot of a bundle.  */
+	  break;
+	}
+
+      manual_bundling_on = md.slot[curr].manual_bundling_on;
+      manual_bundling_off = md.slot[curr].manual_bundling_off;
+
+      if (manual_bundling_on)
+	{
+	  if (curr == first)
+	    manual_bundling = 1;
+	  else
+	    break;			/* need to start a new bundle */
+	}
+
+      if (end_of_insn_group && md.num_slots_in_use >= 1)
+	{
+	  /* We need an instruction group boundary in the middle of a
+	     bundle.  See if we can switch to an other template with
+	     an appropriate boundary.  */
+
+	  orig_template = template;
+	  if (i == 1 && (user_template == 4
+			 || (user_template < 0
+			     && (ia64_templ_desc[template].exec_unit[0]
+				 == IA64_UNIT_M))))
+	    {
+	      template = 5;
+	      end_of_insn_group = 0;
+	    }
+	  else if (i == 2 && (user_template == 0
+			      || (user_template < 0
+				  && (ia64_templ_desc[template].exec_unit[1]
+				      == IA64_UNIT_I)))
+		   /* This test makes sure we don't switch the template if
+		      the next instruction is one that needs to be first in
+		      an instruction group.  Since all those instructions are
+		      in the M group, there is no way such an instruction can
+		      fit in this bundle even if we switch the template.  The
+		      reason we have to check for this is that otherwise we
+		      may end up generating "MI;;I M.." which has the deadly
+		      effect that the second M instruction is no longer the
+		      first in the bundle! --davidm 99/12/16  */
+		   && (idesc->flags & IA64_OPCODE_FIRST) == 0)
+	    {
+	      template = 1;
+	      end_of_insn_group = 0;
+	    }
+	  else if (curr != first)
+	    /* can't fit this insn */
+	    break;
+
+	  if (template != orig_template)
+	    /* if we switch the template, we need to reset the NOPs
+	       after slot i.  The slot-types of the instructions ahead
+	       of i never change, so we don't need to worry about
+	       changing NOPs in front of this slot.  */
+	    for (j = i; j < 3; ++j)
+	      insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
+	}
+      required_unit = ia64_templ_desc[template].exec_unit[i];
+
+      /* resolve dynamic opcodes such as "break" and "nop": */
+      if (idesc->type == IA64_TYPE_DYN)
+	{
+	  if ((strcmp (idesc->name, "nop") == 0)
+	      || (strcmp (idesc->name, "break") == 0))
+	    insn_unit = required_unit;
+	  else if (strcmp (idesc->name, "chk.s") == 0)
+	    {
+	      insn_unit = IA64_UNIT_M;
+	      if (required_unit == IA64_UNIT_I)
+		insn_unit = IA64_UNIT_I;
+	    }
+	  else
+	    as_fatal ("emit_one_bundle: unexpected dynamic op");
+
+	  sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
+	  md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
+#if 0
+	  know (!idesc->next);	/* no resolved dynamic ops have collisions */
+#endif
+	}
+      else
+	{
+	  insn_type = idesc->type;
+	  insn_unit = IA64_UNIT_NIL;
+	  switch (insn_type)
+	    {
+	    case IA64_TYPE_A:
+	      if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
+		insn_unit = required_unit;
+	      break;
+            case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
+	    case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
+	    case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
+	    case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
+	    case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
+	    default:				       break;
+	    }
+	}
+
+      if (insn_unit != required_unit)
+	{
+	  if (required_unit == IA64_UNIT_L
+              && insn_unit == IA64_UNIT_I
+	      && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
+	    {
+	      /* we got ourselves an MLX template but the current
+		 instruction isn't an X-unit, or an I-unit instruction 
+		 that can go into the X slot of an MLX template.  Duh.  */
+	      if (md.num_slots_in_use >= NUM_SLOTS)
+		{
+		  as_bad_where (md.slot[curr].src_file,
+				md.slot[curr].src_line,
+				"`%s' can't go in X slot of "
+				"MLX template", idesc->name);
+		  /* drop this insn so we don't livelock: */
+		  --md.num_slots_in_use;
+		}
+	      break;
+	    }
+	  continue;		/* try next slot */
+	}
+
+      if (debug_type == DEBUG_DWARF2)
+	{
+	  bfd_vma addr;
+
+	  addr = frag_now->fr_address + frag_now_fix () - 16 + 1*i;
+	  dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
+	}
+
+      build_insn (md.slot + curr, insn + i);
+
+      /* Set slot counts for unwind records.  */
+      while (md.slot[curr].unwind_record) 
+	{
+	  md.slot[curr].unwind_record->slot_number = (unsigned long) (f + i);
+	  md.slot[curr].unwind_record = md.slot[curr].unwind_record->next;
+	}
+      if (required_unit == IA64_UNIT_L)
+	{
+	  know (i == 1);
+	  /* skip one slot for long/X-unit instructions */
+	  ++i;
+	}
+      --md.num_slots_in_use;
+
+      /* now is a good time to fix up the labels for this insn: */
+      for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
+	{
+	  S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
+	  symbol_set_frag (lfix->sym, frag_now);
+	}
+
+      for (j = 0; j < md.slot[curr].num_fixups; ++j)
+	{
+	  ifix = md.slot[curr].fixup + j;
+	  fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 4,
+			     &ifix->expr, ifix->is_pcrel, ifix->code);
+	  fix->tc_fix_data.opnd = ifix->opnd;
+	  fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
+	  fix->fx_file = md.slot[curr].src_file;
+	  fix->fx_line = md.slot[curr].src_line;
+	}
+
+      end_of_insn_group = md.slot[curr].end_of_insn_group;
+
+      /* clear slot: */
+      ia64_free_opcode (md.slot[curr].idesc);
+      memset (md.slot + curr, 0, sizeof (md.slot[curr]));
+      md.slot[curr].user_template = -1;
+
+      if (manual_bundling_off)
+	{
+	  manual_bundling = 0;
+	  break;
+	}
+      curr = (curr + 1) % NUM_SLOTS;
+      idesc = md.slot[curr].idesc;
+    }
+  if (manual_bundling)
+    {
+      if (md.num_slots_in_use > 0)
+	as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
+		      "`%s' does not fit into %s template",
+		      idesc->name, ia64_templ_desc[template].name);
+      else
+	as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
+		      "Missing '}' at end of file");
+    }
+  know (md.num_slots_in_use < NUM_SLOTS);
+
+  t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
+  t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
+
+  md_number_to_chars (f + 0, t0, 8);
+  md_number_to_chars (f + 8, t1, 8);
+}
+
+int
+md_parse_option (c, arg)
+     int c;
+     char *arg;
+{
+  /* Switches from the Intel assembler.  */
+  switch (c)
+    {
+    case 'M':
+      if (strcmp (arg, "ilp64") == 0
+	  || strcmp (arg, "lp64") == 0
+	  || strcmp (arg, "p64") == 0)
+	{
+	  md.flags |= EF_IA_64_ABI64;
+	}
+      else if (strcmp (arg, "ilp32") == 0)
+	{
+	  md.flags &= ~EF_IA_64_ABI64;
+	}
+      else if (strcmp (arg, "le") == 0)
+	{
+	  md.flags &= ~EF_IA_64_BE;
+	}
+      else if (strcmp (arg, "be") == 0)
+	{
+	  md.flags |= EF_IA_64_BE;
+	}
+      else
+	return 0;
+      break;
+
+    case 'N':
+      if (strcmp (arg, "so") == 0)
+	{
+          /* Suppress signon message. */
+	}
+      else if (strcmp (arg, "pi") == 0)
+	{
+	  /* Reject privileged instructions.  FIXME */
+	}
+      else if (strcmp (arg, "us") == 0)
+	{
+	  /* Allow union of signed and unsigned range.  FIXME */
+	}
+      else if (strcmp (arg, "close_fcalls") == 0)
+	{
+	  /* Do not resolve global function calls.  */
+	}
+      else
+	return 0;
+      break;
+
+    case 'C':
+      /* temp[="prefix"]  Insert temporary labels into the object file
+			  symbol table prefixed by "prefix".
+			  Default prefix is ":temp:".
+       */
+      break;
+
+    case 'a':
+      /* ??? Conflicts with gas' listing option.  */
+      /* indirect=<tgt>	Assume unannotated indirect branches behavior
+			according to <tgt> --
+			exit:	branch out from the current context (default)
+			labels:	all labels in context may be branch targets
+       */
+      break;
+
+    case 'x':
+      /* -X conflicts with an ignored option, use -x instead */
+      md.detect_dv = 1;
+      if (!arg || strcmp (arg, "explicit") == 0)
+        {
+          /* set default mode to explicit */
+          md.default_explicit_mode = 1;
+          break;
+        }
+      else if (strcmp (arg, "auto") == 0)
+        {
+          md.default_explicit_mode = 0;
+        }
+      else if (strcmp (arg, "debug") == 0)
+        {
+          md.debug_dv = 1;
+        }
+      else if (strcmp (arg, "debugx") == 0)
+        {
+          md.default_explicit_mode = 1;
+          md.debug_dv = 1;
+        }
+      else
+        {
+          as_bad (_("Unrecognized option '-x%s'"), arg);
+        }
+      break;
+
+    case 'S':
+      /* nops		Print nops statistics.  */
+      break;
+
+    default:
+      return 0;
+    }
+
+  return 1;
+}
+
+void
+md_show_usage (stream)
+     FILE *stream;
+{
+  fputs(_("\
+IA-64 options:\n\
+  -Milp32|-Milp64|-Mlp64|-Mp64	select data model (default -Mlp64)\n\
+  -Mle | -Mbe		  select little- or big-endian byte order (default -Mle)\n\
+  -x | -xexplicit	  turn on dependency violation checking (default)\n\
+  -xauto		  automagically remove dependency violations\n\
+  -xdebug		  debug dependency violation checker\n"),
+	stream);
+}
+
+static inline int
+match (int templ, int type, int slot)
+{
+  enum ia64_unit unit;
+  int result;
+
+  unit = ia64_templ_desc[templ].exec_unit[slot];
+  switch (type)
+    {
+    case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
+    case IA64_TYPE_A:
+      result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
+      break;
+    case IA64_TYPE_X:	result = (unit == IA64_UNIT_L); break;
+    case IA64_TYPE_I:	result = (unit == IA64_UNIT_I); break;
+    case IA64_TYPE_M:	result = (unit == IA64_UNIT_M); break;
+    case IA64_TYPE_B:	result = (unit == IA64_UNIT_B); break;
+    case IA64_TYPE_F:	result = (unit == IA64_UNIT_F); break;
+    default:		result = 0; break;
+    }
+  return result;
+}
+
+/* This function is called once, at assembler startup time.  It sets
+   up all the tables, etc. that the MD part of the assembler will need
+   that can be determined before arguments are parsed.  */
+void
+md_begin ()
+{
+  int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum;
+  const char *err;
+  char name[8];
+
+  md.auto_align = 1;
+  md.explicit_mode = md.default_explicit_mode;
+
+  bfd_set_section_alignment (stdoutput, text_section, 4);
+
+  target_big_endian = 0;
+  pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
+      symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
+		  &zero_address_frag);
+
+  pseudo_func[FUNC_GP_RELATIVE].u.sym =
+      symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
+		  &zero_address_frag);
+
+  pseudo_func[FUNC_LT_RELATIVE].u.sym =
+      symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
+		  &zero_address_frag);
+
+  pseudo_func[FUNC_PLT_RELATIVE].u.sym =
+      symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
+		  &zero_address_frag);
+
+  pseudo_func[FUNC_SEC_RELATIVE].u.sym =
+      symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
+		  &zero_address_frag);
+
+  pseudo_func[FUNC_SEG_RELATIVE].u.sym =
+      symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
+		  &zero_address_frag);
+
+  pseudo_func[FUNC_LTV_RELATIVE].u.sym =
+      symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
+		  &zero_address_frag);
+
+  pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
+      symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
+		  &zero_address_frag);
+
+  /* compute the table of best templates: */
+  for (i = 0; i < IA64_NUM_TYPES; ++i)
+    for (j = 0; j < IA64_NUM_TYPES; ++j)
+      for (k = 0; k < IA64_NUM_TYPES; ++k)
+	{
+	  best = 0;
+	  for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
+	    {
+	      goodness = 0;
+	      if (match (t, i, 0))
+		{
+		  if (match (t, j, 1))
+		    {
+		      if (match (t, k, 2))
+			goodness = 3;
+		      else
+			goodness = 2;
+		    }
+		  else if (match (t, j, 2))
+		    goodness = 2;
+		  else
+		    goodness = 1;
+		}
+	      else if (match (t, i, 1))
+		{
+		  if (match (t, j, 2))
+		    goodness = 2;
+		  else
+		    goodness = 1;
+		}
+	      else if (match (t, i, 2))
+		goodness = 1;
+
+	      if (goodness > best)
+		{
+		  best = goodness;
+		  best_template[i][j][k] = t;
+		}
+	    }
+	}
+
+  for (i = 0; i < NUM_SLOTS; ++i)
+    md.slot[i].user_template = -1;
+
+  md.pseudo_hash = hash_new ();
+  for (i = 0; i < NELEMS (pseudo_opcode); ++i)
+    {
+      err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
+			 (void *) (pseudo_opcode + i));
+      if (err)
+	as_fatal ("ia64.md_begin: can't hash `%s': %s",
+		  pseudo_opcode[i].name, err);
+    }
+
+  md.reg_hash = hash_new ();
+  md.dynreg_hash = hash_new ();
+  md.const_hash = hash_new ();
+  md.entry_hash = hash_new ();
+
+  /* general registers: */
+
+  total = 128;
+  for (i = 0; i < total; ++i)
+    {
+      sprintf (name, "r%d", i - REG_GR);
+      md.regsym[i] = declare_register (name, i);
+    }
+
+  /* floating point registers: */
+  total += 128;
+  for (; i < total; ++i)
+    {
+      sprintf (name, "f%d", i - REG_FR);
+      md.regsym[i] = declare_register (name, i);
+    }
+
+  /* application registers: */
+  total += 128;
+  ar_base = i;
+  for (; i < total; ++i)
+    {
+      sprintf (name, "ar%d", i - REG_AR);
+      md.regsym[i] = declare_register (name, i);
+    }
+
+  /* control registers: */
+  total += 128;
+  cr_base = i;
+  for (; i < total; ++i)
+    {
+      sprintf (name, "cr%d", i - REG_CR);
+      md.regsym[i] = declare_register (name, i);
+    }
+
+  /* predicate registers: */
+  total += 64;
+  for (; i < total; ++i)
+    {
+      sprintf (name, "p%d", i - REG_P);
+      md.regsym[i] = declare_register (name, i);
+    }
+
+  /* branch registers: */
+  total += 8;
+  for (; i < total; ++i)
+    {
+      sprintf (name, "b%d", i - REG_BR);
+      md.regsym[i] = declare_register (name, i);
+    }
+
+  md.regsym[REG_IP] = declare_register ("ip", REG_IP);
+  md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
+  md.regsym[REG_PR] = declare_register ("pr", REG_PR);
+  md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
+  md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
+  md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
+  md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
+
+  for (i = 0; i < NELEMS (indirect_reg); ++i)
+    {
+      regnum = indirect_reg[i].regnum;
+      md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
+    }
+
+  /* define synonyms for application registers: */
+  for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
+    md.regsym[i] = declare_register (ar[i - REG_AR].name,
+				     REG_AR + ar[i - REG_AR].regnum);
+
+  /* define synonyms for control registers: */
+  for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
+    md.regsym[i] = declare_register (cr[i - REG_CR].name,
+				     REG_CR + cr[i - REG_CR].regnum);
+
+  declare_register ("gp", REG_GR +  1);
+  declare_register ("sp", REG_GR + 12);
+  declare_register ("rp", REG_BR +  0);
+
+  declare_register_set ("ret", 4, REG_GR + 8);
+  declare_register_set ("farg", 8, REG_FR + 8);
+  declare_register_set ("fret", 8, REG_FR + 8);
+
+  for (i = 0; i < NELEMS (const_bits); ++i)
+    {
+      err = hash_insert (md.const_hash, const_bits[i].name,
+			 (PTR) (const_bits + i));
+      if (err)
+	as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
+		  name, err);
+    }
+
+  /* Default to 64-bit mode.  */
+  md.flags = EF_IA_64_ABI64;
+
+  md.mem_offset.hint = 0;
+  md.path = 0;
+  md.maxpaths = 0;
+  md.entry_labels = NULL;
+}
+
+void
+ia64_end_of_source ()
+{
+  /* terminate insn group upon reaching end of file: */
+  insn_group_break (1, 0, 0);
+
+  /* emits slots we haven't written yet: */
+  ia64_flush_insns ();
+
+  bfd_set_private_flags (stdoutput, md.flags);
+
+  if (debug_type == DEBUG_DWARF2)
+    dwarf2_finish ();
+
+  md.mem_offset.hint = 0;
+}
+
+void
+ia64_start_line ()
+{
+  md.qp.X_op = O_absent;
+
+  if (ignore_input ())
+    return;
+
+  if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
+    {
+      if (md.detect_dv && !md.explicit_mode)
+        as_warn (_("Explicit stops are ignored in auto mode"));
+      else
+        insn_group_break (1, 0, 0);
+    }
+}
+
+int
+ia64_unrecognized_line (ch)
+     int ch;
+{
+  switch (ch)
+    {
+    case '(':
+      expression (&md.qp);
+      if (*input_line_pointer++ != ')')
+	{
+	  as_bad ("Expected ')'");
+	  return 0;
+	}
+      if (md.qp.X_op != O_register)
+	{
+	  as_bad ("Qualifying predicate expected");
+	  return 0;
+	}
+      if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
+	{
+	  as_bad ("Predicate register expected");
+	  return 0;
+	}
+      return 1;
+
+    case '{':
+      if (md.manual_bundling)
+	as_warn ("Found '{' when manual bundling is already turned on");
+      else
+	CURR_SLOT.manual_bundling_on = 1;
+      md.manual_bundling = 1;
+
+      /* bundling is only acceptable in explicit mode
+         or when in default automatic mode */
+      if (md.detect_dv && !md.explicit_mode)
+        {
+          if (!md.mode_explicitly_set
+              && !md.default_explicit_mode)
+            dot_dv_mode ('E');
+          else
+            as_warn (_("Found '{' after explicit switch to automatic mode"));
+        }
+      return 1;
+
+    case '}':
+      if (!md.manual_bundling)
+	as_warn ("Found '}' when manual bundling is off");
+      else
+	PREV_SLOT.manual_bundling_off = 1;
+      md.manual_bundling = 0;
+
+      /* switch back to automatic mode, if applicable */
+      if (md.detect_dv 
+          && md.explicit_mode
+          && !md.mode_explicitly_set
+          && !md.default_explicit_mode)
+        dot_dv_mode ('A');
+
+      /* Allow '{' to follow on the same line.  We also allow ";;", but that
+	 happens automatically because ';' is an end of line marker.  */
+      SKIP_WHITESPACE ();
+      if (input_line_pointer[0] == '{')
+	{
+	  input_line_pointer++;
+	  return ia64_unrecognized_line ('{');
+	}
+
+      demand_empty_rest_of_line ();
+      return 1;
+
+    default:
+      break;
+    }
+  return 0;	/* not a valid line */
+}
+
+void
+ia64_frob_label (sym)
+     struct symbol *sym;
+{
+  struct label_fix *fix;
+
+  if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
+    {
+      md.last_text_seg = now_seg;
+      fix = obstack_alloc (&notes, sizeof (*fix));
+      fix->sym = sym;
+      fix->next = CURR_SLOT.label_fixups;
+      CURR_SLOT.label_fixups = fix;
+
+      /* keep track of how many code entry points we've seen */
+      if (md.path == md.maxpaths)
+        {
+          md.maxpaths += 20;
+          md.entry_labels = (const char **)
+            xrealloc ((void *)md.entry_labels, md.maxpaths * sizeof (char *));
+        }
+      md.entry_labels[md.path++] = S_GET_NAME (sym);
+    }
+}
+
+void
+ia64_flush_pending_output ()
+{
+  if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
+    {
+      /* ??? This causes many unnecessary stop bits to be emitted.
+	 Unfortunately, it isn't clear if it is safe to remove this.  */
+      insn_group_break (1, 0, 0);
+      ia64_flush_insns ();
+    }
+}
+
+/* Do ia64-specific expression optimization.  All that's done here is
+   to transform index expressions that are either due to the indexing
+   of rotating registers or due to the indexing of indirect register
+   sets.  */
+int
+ia64_optimize_expr (l, op, r)
+     expressionS *l;
+     operatorT op;
+     expressionS *r;
+{
+  unsigned num_regs;
+
+  if (op == O_index)
+    {
+      if (l->X_op == O_register && r->X_op == O_constant)
+	{
+	  num_regs = (l->X_add_number >> 16);
+	  if ((unsigned) r->X_add_number >= num_regs)
+	    {
+	      if (!num_regs)
+		as_bad ("No current frame");
+	      else
+		as_bad ("Index out of range 0..%u", num_regs - 1);
+	      r->X_add_number = 0;
+	    }
+	  l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
+	  return 1;
+	}
+      else if (l->X_op == O_register && r->X_op == O_register)
+	{
+	  if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
+	      || l->X_add_number == IND_MEM)
+	    {
+	      as_bad ("Indirect register set name expected");
+	      l->X_add_number = IND_CPUID;
+	    }
+	  l->X_op = O_index;
+	  l->X_op_symbol = md.regsym[l->X_add_number];
+	  l->X_add_number = r->X_add_number;
+	  return 1;
+	}
+    }
+  return 0;
+}
+
+int
+ia64_parse_name (name, e)
+     char *name;
+     expressionS *e;
+{
+  struct const_desc *cdesc;
+  struct dynreg *dr = 0;
+  unsigned int regnum;
+  struct symbol *sym;
+  char *end;
+
+  /* first see if NAME is a known register name: */
+  sym = hash_find (md.reg_hash, name);
+  if (sym)
+    {
+      e->X_op = O_register;
+      e->X_add_number = S_GET_VALUE (sym);
+      return 1;
+    }
+
+  cdesc = hash_find (md.const_hash, name);
+  if (cdesc)
+    {
+      e->X_op = O_constant;
+      e->X_add_number = cdesc->value;
+      return 1;
+    }
+
+  /* check for inN, locN, or outN: */
+  switch (name[0])
+    {
+    case 'i':
+      if (name[1] == 'n' && isdigit (name[2]))
+	{
+	  dr = &md.in;
+	  name += 2;
+	}
+      break;
+
+    case 'l':
+      if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3]))
+	{
+	  dr = &md.loc;
+	  name += 3;
+	}
+      break;
+
+    case 'o':
+      if (name[1] == 'u' && name[2] == 't' && isdigit (name[3]))
+	{
+	  dr = &md.out;
+	  name += 3;
+	}
+      break;
+
+    default:
+      break;
+    }
+
+  if (dr)
+    {
+      /* the name is inN, locN, or outN; parse the register number: */
+      regnum = strtoul (name, &end, 10);
+      if (end > name && *end == '\0')
+	{
+	  if ((unsigned) regnum >= dr->num_regs)
+	    {
+	      if (!dr->num_regs)
+		as_bad ("No current frame");
+	      else
+		as_bad ("Register number out of range 0..%u", dr->num_regs-1);
+	      regnum = 0;
+	    }
+	  e->X_op = O_register;
+	  e->X_add_number = dr->base + regnum;
+	  return 1;
+	}
+    }
+
+  if ((dr = hash_find (md.dynreg_hash, name)))
+    {
+      /* We've got ourselves the name of a rotating register set.
+         Store the base register number in the low 16 bits of
+         X_add_number and the size of the register set in the top 16
+         bits.  */
+      e->X_op = O_register;
+      e->X_add_number = dr->base | (dr->num_regs << 16);
+      return 1;
+    }
+  return 0;
+}
+
+/* Remove the '#' suffix that indicates a symbol as opposed to a register.  */
+
+char *
+ia64_canonicalize_symbol_name (name)
+     char *name;
+{
+  size_t len = strlen(name);
+  if (len > 1 && name[len-1] == '#')
+    name[len-1] = '\0';
+  return name;
+}
+
+static int
+is_conditional_branch (idesc)
+  struct ia64_opcode *idesc;
+{
+  return (strncmp (idesc->name, "br", 2) == 0
+          && (strcmp (idesc->name, "br") == 0 
+              || strncmp (idesc->name, "br.cond", 7) == 0
+              || strncmp (idesc->name, "br.call", 7) == 0
+              || strncmp (idesc->name, "br.ret", 6) == 0
+              || strcmp (idesc->name, "brl") == 0
+              || strncmp (idesc->name, "brl.cond", 7) == 0
+              || strncmp (idesc->name, "brl.call", 7) == 0
+              || strncmp (idesc->name, "brl.ret", 6) == 0));
+}
+
+/* Return whether the given opcode is a taken branch.  If there's any doubt,
+   returns zero */
+static int
+is_taken_branch (idesc)
+  struct ia64_opcode *idesc;
+{
+  return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
+          || strncmp (idesc->name, "br.ia", 5) == 0);
+}
+
+/* Return whether the given opcode is an interruption or rfi.  If there's any
+   doubt, returns zero */
+static int
+is_interruption_or_rfi (idesc)
+  struct ia64_opcode *idesc;
+{
+  if (strcmp (idesc->name, "rfi") == 0)
+    return 1;
+  return 0;
+}
+
+/* Returns the index of the given dependency in the opcode's list of chks, or
+   -1 if there is no dependency.  */
+static int
+depends_on (depind, idesc)
+  int depind;
+  struct ia64_opcode *idesc;
+{
+  int i;
+  const struct ia64_opcode_dependency *dep = idesc->dependencies;
+  for (i = 0;i < dep->nchks; i++)
+    {
+      if (depind == DEP(dep->chks[i]))
+        return i;
+    }
+  return -1;
+}
+
+/* Determine a set of specific resources used for a particular resource
+   class.  Returns the number of specific resources identified  For those
+   cases which are not determinable statically, the resource returned is
+   marked nonspecific.  
+
+   Meanings of value in 'NOTE':
+   1) only read/write when the register number is explicitly encoded in the
+   insn.
+   2) only read CFM when accessing a rotating GR, FR, or PR.  mov pr only
+   accesses CFM when qualifying predicate is in the rotating region. 
+   3) general register value is used to specify an indirect register; not
+   determinable statically.
+   4) only read the given resource when bits 7:0 of the indirect index
+   register value does not match the register number of the resource; not
+   determinable statically.
+   5) all rules are implementation specific.
+   6) only when both the index specified by the reader and the index specified
+   by the writer have the same value in bits 63:61; not determinable
+   statically. 
+   7) only access the specified resource when the corresponding mask bit is
+   set 
+   8) PSR.dfh is only read when these insns reference FR32-127.  PSR.dfl is
+   only read when these insns reference FR2-31
+   9) PSR.mfl is only written when these insns write FR2-31.  PSR.mfh is only
+   written when these insns write FR32-127
+   10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
+   instruction
+   11) The target predicates are written independently of PR[qp], but source
+   registers are only read if PR[qp] is true.  Since the state of PR[qp]
+   cannot statically be determined, all source registers are marked used.
+   12) This insn only reads the specified predicate register when that
+   register is the PR[qp].
+   13) This reference to ld-c only applies to teh GR whose value is loaded
+   with data returned from memory, not the post-incremented address register.  
+   14) The RSE resource includes the implementation-specific RSE internal
+   state resources.  At least one (and possibly more) of these resources are
+   read by each instruction listed in IC:rse-readers.  At least one (and
+   possibly more) of these resources are written by each insn listed in
+   IC:rse-writers. 
+   15+16) Represents reserved instructions, which the assembler does not
+   generate. 
+
+   Memory resources (i.e. locations in memory) are *not* marked or tracked by
+   this code; there are no dependency violations based on memory access.
+
+*/
+
+#define MAX_SPECS 256
+#define DV_CHK 1
+#define DV_REG 0
+
+static int
+specify_resource (dep, idesc, type, specs, note, path)
+  const struct ia64_dependency *dep;
+  struct ia64_opcode *idesc;
+  int type;                         /* is this a DV chk or a DV reg? */
+  struct rsrc specs[MAX_SPECS];     /* returned specific resources */
+  int note;                         /* resource note for this insn's usage */
+  int path;                         /* which execution path to examine */
+{
+  int count = 0;
+  int i;
+  int rsrc_write = 0;
+  struct rsrc tmpl;
+ 
+  if (dep->mode == IA64_DV_WAW
+      || (dep->mode == IA64_DV_RAW && type == DV_REG)
+      || (dep->mode == IA64_DV_WAR && type == DV_CHK))
+    rsrc_write = 1;
+
+  /* template for any resources we identify */
+  tmpl.dependency = dep;
+  tmpl.note = note;
+  tmpl.insn_srlz = tmpl.data_srlz = 0;
+  tmpl.qp_regno = CURR_SLOT.qp_regno;
+  tmpl.link_to_qp_branch = 1;
+  tmpl.mem_offset.hint = 0;
+  tmpl.specific = 1;
+  tmpl.index = 0;
+
+#define UNHANDLED \
+as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
+dep->name, idesc->name, (rsrc_write?"write":"read"), note)
+#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
+
+  /* we don't need to track these */
+  if (dep->semantics == IA64_DVS_NONE)
+    return 0;
+
+  switch (dep->specifier)
+    {
+    case IA64_RS_AR_K:
+      if (note == 1)
+        {
+          if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
+            {
+              int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
+              if (regno >= 0 && regno <= 7)
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = regno;
+                }
+            }
+        }
+      else if (note == 0)
+        {
+          for(i=0;i < 8;i++)
+            {
+              specs[count] = tmpl;
+              specs[count++].index = i;
+            }
+        }
+      else
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_AR_UNAT:
+      /* This is a mov =AR or mov AR= instruction.  */
+      if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
+	{
+	  int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
+	  if (regno == AR_UNAT)
+	    {
+	      specs[count++] = tmpl;
+	    }
+	}
+      else
+	{
+	  /* This is a spill/fill, or other instruction that modifies the
+	     unat register.  */
+
+	  /* Unless we can determine the specific bits used, mark the whole
+	     thing; bits 8:3 of the memory address indicate the bit used in
+	     UNAT.  The .mem.offset hint may be used to eliminate a small
+	     subset of conflicts.  */
+	  specs[count] = tmpl;
+	  if (md.mem_offset.hint)
+	    {
+              if (md.debug_dv)
+                fprintf (stderr, "  Using hint for spill/fill\n");
+	      /* the index isn't actually used, just set it to something
+		 approximating the bit index */
+	      specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
+	      specs[count].mem_offset.hint = 1;
+	      specs[count].mem_offset.offset = md.mem_offset.offset;
+	      specs[count++].mem_offset.base = md.mem_offset.base;
+	    }
+	  else
+	    {
+	      specs[count++].specific = 0;
+	    }
+	}
+      break;
+
+    case IA64_RS_AR:
+      if (note == 1)
+        { 
+          if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
+            {
+              int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
+              if ((regno >= 8 && regno <= 15)
+                  || (regno >= 20 && regno <= 23)
+                  || (regno >= 31 && regno <= 39)
+                  || (regno >= 41 && regno <= 47)
+                  || (regno >= 67 && regno <= 111))
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = regno;
+                }
+            }
+        }
+      else
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_ARb:
+      if (note == 1)
+        {
+          if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
+            {
+              int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
+              if ((regno >= 48 && regno <= 63)
+                  || (regno >= 112 && regno <= 127))
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = regno;
+                }
+            }
+        }
+      else if (note == 0)
+        {
+          for (i=48;i < 64;i++)
+            {
+              specs[count] = tmpl;
+              specs[count++].index = i;
+            }
+          for (i=112;i < 128;i++)
+            {
+              specs[count] = tmpl;
+              specs[count++].index = i;
+            }
+        }
+      else 
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_BR:
+      if (note != 1)
+        {
+          UNHANDLED;
+        }
+      else
+        {
+          if (rsrc_write)
+            {
+              for (i=0;i < idesc->num_outputs;i++)
+                if (idesc->operands[i] == IA64_OPND_B1
+                    || idesc->operands[i] == IA64_OPND_B2)
+                  {
+                    specs[count] = tmpl;
+                    specs[count++].index = 
+                      CURR_SLOT.opnd[i].X_add_number - REG_BR;
+                  }
+            }
+          else
+            {
+              for (i = idesc->num_outputs;i < NELEMS(idesc->operands);i++)
+                if (idesc->operands[i] == IA64_OPND_B1
+                    || idesc->operands[i] == IA64_OPND_B2)
+                  {
+                    specs[count] = tmpl;
+                    specs[count++].index = 
+                      CURR_SLOT.opnd[i].X_add_number - REG_BR;
+                  }
+            }
+        }
+      break;
+
+    case IA64_RS_CPUID: /* four or more registers */
+      if (note == 3)
+        {
+          if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
+            {
+              int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
+              if (regno >= 0 && regno < NELEMS(gr_values)
+                  && KNOWN(regno))
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = gr_values[regno].value & 0xFF;
+                }
+              else
+                {
+                  specs[count] = tmpl;
+                  specs[count++].specific = 0;
+                }
+            }
+        }
+      else
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_DBR: /* four or more registers */
+      if (note == 3)
+        {
+          if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
+            {
+              int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
+              if (regno >= 0 && regno < NELEMS(gr_values)
+                  && KNOWN(regno))
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = gr_values[regno].value & 0xFF;
+                }
+              else
+                {
+                  specs[count] = tmpl;
+                  specs[count++].specific = 0;
+                }
+            }
+        }
+      else if (note == 0 && !rsrc_write)
+        {
+          specs[count] = tmpl;
+          specs[count++].specific = 0;
+        }
+      else
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_IBR: /* four or more registers */
+      if (note == 3)
+        {
+          if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
+            {
+              int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
+              if (regno >= 0 && regno < NELEMS(gr_values)
+                  && KNOWN(regno))
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = gr_values[regno].value & 0xFF;
+                }
+              else
+                {
+                  specs[count] = tmpl;
+                  specs[count++].specific = 0;
+                }
+            }
+        }
+      else
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_MSR:
+      if (note == 5)
+	{
+	  /* These are implementation specific.  Force all references to
+	     conflict with all other references.  */
+	  specs[count] = tmpl;
+	  specs[count++].specific = 0;
+	}
+      else
+	{
+	  UNHANDLED;
+	}
+      break;
+
+    case IA64_RS_PKR: /* 16 or more registers */
+      if (note == 3 || note == 4)
+        {
+          if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
+            {
+              int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
+              if (regno >= 0 && regno < NELEMS(gr_values)
+                  && KNOWN(regno))
+                {
+                  if (note == 3)
+                    {
+                      specs[count] = tmpl;
+                      specs[count++].index = gr_values[regno].value & 0xFF;
+                    }
+                  else for (i=0;i < NELEMS(gr_values);i++)
+                    {
+                      /* uses all registers *except* the one in R3 */
+                      if (i != (gr_values[regno].value & 0xFF))
+                        {
+                          specs[count] = tmpl;
+                          specs[count++].index = i;
+                        }
+                    }
+                }
+              else
+                {
+                  specs[count] = tmpl;
+                  specs[count++].specific = 0;
+                }
+            }
+        }
+      else if (note == 0)
+        {
+          /* probe et al. */
+          specs[count] = tmpl;
+          specs[count++].specific = 0;
+        }
+      break;
+
+    case IA64_RS_PMC: /* four or more registers */
+      if (note == 3)
+        {
+          if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
+              || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
+            
+            {
+              int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
+                           ? 1 : !rsrc_write);
+              int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
+              if (regno >= 0 && regno < NELEMS(gr_values)
+                  && KNOWN(regno))
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = gr_values[regno].value & 0xFF;
+                }
+              else
+                {
+                  specs[count] = tmpl;
+                  specs[count++].specific = 0;
+                }
+            }
+        }
+      else
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_PMD: /* four or more registers */
+      if (note == 3)
+        {
+          if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
+            {
+              int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
+              if (regno >= 0 && regno < NELEMS(gr_values)
+                  && KNOWN(regno))
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = gr_values[regno].value & 0xFF;
+                }
+              else
+                {
+                  specs[count] = tmpl;
+                  specs[count++].specific = 0;
+                }
+            }
+        }
+      else
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_RR: /* eight registers */
+      if (note == 6)
+        {
+          if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
+            {
+              int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
+              if (regno >= 0 && regno < NELEMS(gr_values)
+                  && KNOWN(regno))
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
+                }
+              else
+                {
+                  specs[count] = tmpl;
+                  specs[count++].specific = 0;
+                }
+            }
+        }
+      else if (note == 0 && !rsrc_write)
+        {
+          specs[count] = tmpl;
+          specs[count++].specific = 0;
+        }
+      else 
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_CR_IRR:
+      if (note == 0) 
+        {
+          /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
+          int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
+          if (rsrc_write 
+              && idesc->operands[1] == IA64_OPND_CR3
+              && regno == CR_IVR)
+            {
+              for(i=0;i < 4;i++)
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = CR_IRR0 + i;
+                }
+            }
+        }
+      else if (note == 1)
+        {
+          int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
+          if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
+              && regno >= CR_IRR0
+              && regno <= CR_IRR3)
+            {
+              specs[count] = tmpl;
+              specs[count++].index = regno;
+            }
+        }
+      else
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_CR_LRR:
+      if (note != 1)
+        {
+          UNHANDLED;
+        }
+      else 
+        {
+          int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
+          if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
+              && (regno == CR_LRR0 || regno == CR_LRR1))
+            {
+              specs[count] = tmpl;
+              specs[count++].index = regno;
+            }
+        }
+      break;
+
+    case IA64_RS_CR:
+      if (note == 1)
+        {
+          if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
+            {
+              specs[count] = tmpl;
+              specs[count++].index = 
+                CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
+            }
+        }
+      else
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_FR:
+    case IA64_RS_FRb:
+      if (note != 1)
+        {
+          UNHANDLED;
+        }
+      else if (rsrc_write)
+        {
+          if (dep->specifier == IA64_RS_FRb
+              && idesc->operands[0] == IA64_OPND_F1)
+            {
+              specs[count] = tmpl;
+              specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
+            }
+        }
+      else
+        {
+          for (i=idesc->num_outputs;i < NELEMS(idesc->operands);i++)
+            {
+              if (idesc->operands[i] == IA64_OPND_F2
+                  || idesc->operands[i] == IA64_OPND_F3
+                  || idesc->operands[i] == IA64_OPND_F4)
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = 
+                    CURR_SLOT.opnd[i].X_add_number - REG_FR;
+                }
+            }
+        }
+      break;
+
+    case IA64_RS_GR:
+      if (note == 13)
+        {
+          /* This reference applies only to the GR whose value is loaded with
+             data returned from memory */
+          specs[count] = tmpl;
+          specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
+        }
+      else if (note == 1)
+        {
+          if (rsrc_write)
+            {
+              for (i=0;i < idesc->num_outputs;i++)
+                {
+                  if (idesc->operands[i] == IA64_OPND_R1
+                      || idesc->operands[i] == IA64_OPND_R2
+                      || idesc->operands[i] == IA64_OPND_R3)
+                    {
+                      specs[count] = tmpl;
+                      specs[count++].index = 
+                        CURR_SLOT.opnd[i].X_add_number - REG_GR;
+                    }
+                }
+            }
+          else 
+            {
+              /* Look for anything that reads a GR */
+              for (i=0;i < NELEMS(idesc->operands);i++)
+                {
+                  if (idesc->operands[i] == IA64_OPND_MR3
+                      || idesc->operands[i] == IA64_OPND_CPUID_R3
+                      || idesc->operands[i] == IA64_OPND_DBR_R3
+                      || idesc->operands[i] == IA64_OPND_IBR_R3
+		      || idesc->operands[i] == IA64_OPND_MSR_R3
+                      || idesc->operands[i] == IA64_OPND_PKR_R3
+                      || idesc->operands[i] == IA64_OPND_PMC_R3
+                      || idesc->operands[i] == IA64_OPND_PMD_R3
+                      || idesc->operands[i] == IA64_OPND_RR_R3
+                      || ((i >= idesc->num_outputs)
+                          && (idesc->operands[i] == IA64_OPND_R1
+                              || idesc->operands[i] == IA64_OPND_R2
+                              || idesc->operands[i] == IA64_OPND_R3)))
+                    {
+                      specs[count] = tmpl;
+                      specs[count++].index = 
+                        CURR_SLOT.opnd[i].X_add_number - REG_GR;
+                    }
+                }
+            }
+        }
+      else 
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_PR:
+      if (note == 0)
+        {
+          if (idesc->operands[0] == IA64_OPND_PR_ROT)
+            {
+              for (i=16;i < 63;i++)
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = i;
+                }
+            }
+          else
+            {
+              for (i=1;i < 63;i++)
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = i;
+                }
+            }
+        }
+      else if (note == 7)
+        {
+          valueT mask = 0;
+          /* mark only those registers indicated by the mask */
+          if (rsrc_write
+              && idesc->operands[0] == IA64_OPND_PR)
+            {
+              mask = CURR_SLOT.opnd[2].X_add_number;
+              if (mask & ((valueT)1<<16))
+                mask |= ~(valueT)0xffff;
+              for (i=1;i < 63;i++)
+                {
+                  if (mask & ((valueT)1<<i))
+                    {
+                      specs[count] = tmpl;
+                      specs[count++].index = i;
+                    }
+                }
+            }
+          else if (rsrc_write
+                   && idesc->operands[0] == IA64_OPND_PR_ROT)
+            {
+              for (i=16;i < 63;i++)
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = i;
+                }
+            }
+          else
+            {
+              UNHANDLED;
+            }
+        }
+      else if (note == 11) /* note 11 implies note 1 as well */
+        {
+          if (rsrc_write)
+            {
+              for (i=0;i < idesc->num_outputs;i++)
+                {
+                  if (idesc->operands[i] == IA64_OPND_P1
+                      || idesc->operands[i] == IA64_OPND_P2)
+                    {
+                      int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
+                      if (regno != 0)
+                        {
+                          specs[count] = tmpl;
+                          specs[count++].index = regno;
+                        }
+                    }
+                }
+            }
+          else
+            {
+              UNHANDLED;
+            }
+        }
+      else if (note == 12)
+        {
+          if (CURR_SLOT.qp_regno != 0)
+            {
+              specs[count] = tmpl;
+              specs[count++].index = CURR_SLOT.qp_regno;
+            }
+        }
+      else if (note == 1)
+        {
+          if (rsrc_write)
+            {
+              int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
+              int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
+              if ((idesc->operands[0] == IA64_OPND_P1
+                   || idesc->operands[0] == IA64_OPND_P2)
+                  && p1 != 0 && p1 != 63)
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = p1;
+                }
+              if ((idesc->operands[1] == IA64_OPND_P1
+                   || idesc->operands[1] == IA64_OPND_P2)
+                  && p2 != 0 && p2 != 63)
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = p2;
+                }
+            }
+          else
+            {
+              if (CURR_SLOT.qp_regno != 0)
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = CURR_SLOT.qp_regno;
+                }
+              if (idesc->operands[1] == IA64_OPND_PR)
+                {
+                  for (i=1;i < 63;i++)
+                    {
+                      specs[count] = tmpl;
+                      specs[count++].index = i;
+                    }
+                }
+            }
+        }
+      else 
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_PSR:
+      /* Verify that the instruction is using the PSR bit indicated in 
+         dep->regindex */
+      if (note == 0)
+        {
+          if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
+            {
+              if (dep->regindex < 6)
+                {
+                  specs[count++] = tmpl;
+                }
+            }
+          else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
+            {
+              if (dep->regindex < 32
+                  || dep->regindex == 35
+                  || dep->regindex == 36
+                  || (!rsrc_write && dep->regindex == PSR_CPL))
+                {
+                  specs[count++] = tmpl;
+                }
+            }
+          else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
+            {
+              if (dep->regindex < 32
+                  || dep->regindex == 35
+                  || dep->regindex == 36
+                  || (rsrc_write && dep->regindex == PSR_CPL))
+                {
+                  specs[count++] = tmpl;
+                }
+            }
+          else 
+            {
+              /* Several PSR bits have very specific dependencies. */
+              switch (dep->regindex)
+                {
+                default:
+                  specs[count++] = tmpl;
+                  break;
+                case PSR_IC:
+                  if (rsrc_write)
+                    {
+                      specs[count++] = tmpl;
+                    }
+                  else
+                    {
+                      /* Only certain CR accesses use PSR.ic */
+                      if (idesc->operands[0] == IA64_OPND_CR3
+                          || idesc->operands[1] == IA64_OPND_CR3)
+                        {
+                          int index = 
+                            ((idesc->operands[0] == IA64_OPND_CR3)
+                             ? 0 : 1);
+                          int regno = 
+                            CURR_SLOT.opnd[index].X_add_number - REG_CR;
+
+                          switch (regno)
+                            {
+                            default:
+                              break;
+                            case CR_ITIR:
+                            case CR_IFS:
+                            case CR_IIM:
+                            case CR_IIP:
+                            case CR_IPSR:
+                            case CR_ISR:
+                            case CR_IFA:
+                            case CR_IHA:
+                            case CR_IIPA:
+                              specs[count++] = tmpl;
+                              break;
+                            }
+                        }
+                    }
+                  break;
+                case PSR_CPL:
+                  if (rsrc_write)
+                    {
+                      specs[count++] = tmpl;
+                    }
+                  else 
+                    {
+                      /* Only some AR accesses use cpl */
+                      if (idesc->operands[0] == IA64_OPND_AR3
+                          || idesc->operands[1] == IA64_OPND_AR3)
+                        {
+                          int index = 
+                            ((idesc->operands[0] == IA64_OPND_AR3)
+                             ? 0 : 1);
+                          int regno = 
+                            CURR_SLOT.opnd[index].X_add_number - REG_AR;
+                          
+                          if (regno == AR_ITC
+                              || (index == 0
+                                  && (regno == AR_ITC 
+                                      || regno == AR_RSC 
+                                      || (regno >= AR_K0
+                                          && regno <= AR_K7))))
+                            {
+                              specs[count++] = tmpl;
+                            }                  
+                        }
+                      else
+                        {
+                          specs[count++] = tmpl;
+                        }
+                      break;
+                    }
+                }
+            }
+        }
+      else if (note == 7)
+        {
+          valueT mask = 0;
+          if (idesc->operands[0] == IA64_OPND_IMMU24)
+            {
+              mask = CURR_SLOT.opnd[0].X_add_number;
+            }
+          else 
+            {
+              UNHANDLED;
+            }
+          if (mask & ((valueT)1<<dep->regindex))
+            {
+              specs[count++] = tmpl;
+            }
+        }
+      else if (note == 8)
+        {
+          int min = dep->regindex == PSR_DFL ? 2 : 32;
+          int max = dep->regindex == PSR_DFL ? 31 : 127;
+          /* dfh is read on FR32-127; dfl is read on FR2-31 */
+          for (i=0;i < NELEMS(idesc->operands);i++)
+            {
+              if (idesc->operands[i] == IA64_OPND_F1
+                  || idesc->operands[i] == IA64_OPND_F2
+                  || idesc->operands[i] == IA64_OPND_F3
+                  || idesc->operands[i] == IA64_OPND_F4)
+                {
+                  int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
+                  if (reg >= min && reg <= max)
+                    {
+                      specs[count++] = tmpl;
+                    }
+                }
+            }
+        }
+      else if (note == 9)
+        {
+          int min = dep->regindex == PSR_MFL ? 2 : 32;
+          int max = dep->regindex == PSR_MFL ? 31 : 127;
+          /* mfh is read on writes to FR32-127; mfl is read on writes to
+             FR2-31 */ 
+          for (i=0;i < idesc->num_outputs;i++)
+            {
+              if (idesc->operands[i] == IA64_OPND_F1)
+                {
+                  int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
+                  if (reg >= min && reg <= max)
+                    {
+                      specs[count++] = tmpl;
+                    }
+                }
+            }
+        }
+      else if (note == 10)
+        {
+          for (i=0;i < NELEMS(idesc->operands);i++)
+            {
+              if (idesc->operands[i] == IA64_OPND_R1
+                  || idesc->operands[i] == IA64_OPND_R2
+                  || idesc->operands[i] == IA64_OPND_R3)
+                {
+                  int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
+                  if (regno >= 16 && regno <= 31)
+                    {
+                      specs[count++] = tmpl;
+                    }
+                }
+            }
+        }
+      else
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_AR_FPSR:
+      if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
+        {
+          int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
+          if (regno == AR_FPSR)
+            {
+              specs[count++] = tmpl;
+            }
+        }
+      else
+        {
+          specs[count++] = tmpl;
+        }
+      break;
+
+    case IA64_RS_ARX: 
+      /* Handle all AR[REG] resources */
+      if (note == 0 || note == 1)
+        {
+          int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
+          if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
+              && regno == dep->regindex)
+            {
+              specs[count++] = tmpl;
+            }
+          /* other AR[REG] resources may be affected by AR accesses */
+          else if (idesc->operands[0] == IA64_OPND_AR3)
+            {
+              /* AR[] writes */
+              regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
+              switch (dep->regindex)
+                {
+                default:
+                  break;
+                case AR_BSP:
+                case AR_RNAT:
+                  if (regno == AR_BSPSTORE)
+                    {
+                      specs[count++] = tmpl;
+                    }
+                case AR_RSC:
+                  if (!rsrc_write &&
+                      (regno == AR_BSPSTORE 
+                       || regno == AR_RNAT))
+                    {
+                      specs[count++] = tmpl;
+                    }
+                  break;
+                }
+            }
+          else if (idesc->operands[1] == IA64_OPND_AR3)
+            {
+              /* AR[] reads */
+              regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
+              switch (dep->regindex)
+                {
+                default:
+                  break;
+                case AR_RSC:
+                  if (regno == AR_BSPSTORE || regno == AR_RNAT)
+                    {
+                      specs[count++] = tmpl;
+                    }
+                  break;
+                }
+            }
+          else 
+            {
+              specs[count++] = tmpl;
+            }
+        }
+      else
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_CRX:
+      /* Handle all CR[REG] resources */
+      if (note == 0 || note == 1)
+        {
+          if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
+            {
+              int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
+              if (regno == dep->regindex)
+                {
+                  specs[count++] = tmpl;
+                }
+              else if (!rsrc_write)
+                {
+                  /* Reads from CR[IVR] affect other resources. */
+                  if (regno == CR_IVR)
+                    {
+                      if ((dep->regindex >= CR_IRR0
+                           && dep->regindex <= CR_IRR3)
+                          || dep->regindex == CR_TPR)
+                        {
+                          specs[count++] = tmpl;
+                        }
+                    }
+                }
+            }
+          else
+            {
+              specs[count++] = tmpl;
+            }
+        }
+      else
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_INSERVICE:
+      /* look for write of EOI (67) or read of IVR (65) */
+      if ((idesc->operands[0] == IA64_OPND_CR3
+           && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
+          || (idesc->operands[1] == IA64_OPND_CR3
+              && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
+        {
+          specs[count++] = tmpl;
+        }
+      break;
+
+    case IA64_RS_GR0:
+      if (note == 1)
+        {
+          specs[count++] = tmpl;
+        }
+      else
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_CFM:
+      if (note != 2)
+        {
+          specs[count++] = tmpl;
+        }
+      else
+        {
+          /* Check if any of the registers accessed are in the rotating region.
+             mov to/from pr accesses CFM only when qp_regno is in the rotating
+             region */
+          for (i=0;i < NELEMS(idesc->operands);i++)
+            {
+              if (idesc->operands[i] == IA64_OPND_R1
+                  || idesc->operands[i] == IA64_OPND_R2
+                  || idesc->operands[i] == IA64_OPND_R3)
+                {
+                  int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
+                  /* Assumes that md.rot.num_regs is always valid */
+                  if (md.rot.num_regs > 0
+                      && num > 31
+                      && num < 31 + md.rot.num_regs)
+                    {
+                      specs[count] = tmpl;
+                      specs[count++].specific = 0;
+                    }
+                }
+              else if (idesc->operands[i] == IA64_OPND_F1
+                       || idesc->operands[i] == IA64_OPND_F2
+                       || idesc->operands[i] == IA64_OPND_F3
+                       || idesc->operands[i] == IA64_OPND_F4)
+                {
+                  int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
+                  if (num > 31)
+                    {
+                      specs[count] = tmpl;
+                      specs[count++].specific = 0;
+                    }
+                }
+              else if (idesc->operands[i] == IA64_OPND_P1
+                       || idesc->operands[i] == IA64_OPND_P2)
+                {
+                  int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
+                  if (num > 15)
+                    {
+                      specs[count] = tmpl;
+                      specs[count++].specific = 0;
+                    }
+                }
+            }
+          if (CURR_SLOT.qp_regno > 15)
+            {
+              specs[count] = tmpl;
+              specs[count++].specific = 0;
+            }
+        }
+      break;
+
+    case IA64_RS_PR63:
+      if (note == 0)
+        {
+          specs[count++] = tmpl;
+        }
+      else if (note == 11)
+        {
+          if ((idesc->operands[0] == IA64_OPND_P1
+               && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
+              || (idesc->operands[1] == IA64_OPND_P2
+                  && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
+            {
+              specs[count++] = tmpl;
+            }
+        }
+      else if (note == 12)
+        {
+          if (CURR_SLOT.qp_regno == 63)
+            {
+              specs[count++] = tmpl;
+            }
+        }
+      else if (note == 7)
+        {
+          valueT mask = 0;
+          if (idesc->operands[2] == IA64_OPND_IMM17)
+            mask = CURR_SLOT.opnd[2].X_add_number;
+          if (mask & ((valueT)1<<63))
+            {
+              specs[count++] = tmpl;
+            }
+        }
+      else if (note == 1)
+        {
+          if (rsrc_write)
+            {
+              for (i=0;i < idesc->num_outputs;i++)
+                if ((idesc->operands[i] == IA64_OPND_P1
+                     || idesc->operands[i] == IA64_OPND_P2)
+                    && CURR_SLOT.opnd[i].X_add_number - REG_P == 63)
+                  {
+                    specs[count++] = tmpl;
+                  }
+            }
+          else
+            {
+              if (CURR_SLOT.qp_regno == 63)
+                {
+                  specs[count++] = tmpl;
+                }
+            }
+        }
+      else
+        {
+          UNHANDLED;
+        }
+      break;
+
+    case IA64_RS_RSE:
+      /* FIXME we can identify some individual RSE written resources, but RSE
+         read resources have not yet been completely identified, so for now
+         treat RSE as a single resource */
+      if (strncmp (idesc->name, "mov", 3) == 0)
+        {
+          if (rsrc_write)
+            {
+              if (idesc->operands[0] == IA64_OPND_AR3
+                  && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
+                {
+                  specs[count] = tmpl;
+                  specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
+                }
+            }
+          else
+            {
+              if (idesc->operands[0] == IA64_OPND_AR3)
+                {
+                  if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
+                      || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
+                    {
+                      specs[count++] = tmpl;
+                    }
+                }
+              else if (idesc->operands[1] == IA64_OPND_AR3)
+                {
+                  if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
+                      || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
+                      || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
+                    {
+                      specs[count++] = tmpl;
+                    }
+                }
+            }
+        }
+      else 
+        {
+          specs[count++] = tmpl;
+        }
+      break;
+
+    case IA64_RS_ANY:
+      /* FIXME -- do any of these need to be non-specific? */
+      specs[count++] = tmpl;
+      break;
+
+    default:
+      as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
+      break;
+    }
+
+  return count;
+}
+
+/* Clear branch flags on marked resources.  This breaks the link between the
+   QP of the marking instruction and a subsequent branch on the same QP. 
+*/
+static void
+clear_qp_branch_flag (mask)
+  valueT mask;
+{
+  int i;
+  for (i = 0;i < regdepslen;i++)
+    {
+      valueT bit = ((valueT)1 << regdeps[i].qp_regno);
+      if ((bit & mask) != 0)
+        {
+          regdeps[i].link_to_qp_branch = 0;
+        }
+    }
+}
+
+/* Remove any mutexes which contain any of the PRs indicated in the mask. 
+
+   Any changes to a PR clears the mutex relations which include that PR.
+*/ 
+static void
+clear_qp_mutex (mask)
+  valueT mask;
+{
+  int i;
+
+  i = 0;
+  while (i < qp_mutexeslen)
+    {
+      if ((qp_mutexes[i].prmask & mask) != 0)
+        {
+          if (md.debug_dv)
+            {
+              fprintf (stderr, "  Clearing mutex relation");
+              print_prmask (qp_mutexes[i].prmask);
+              fprintf (stderr, "\n");
+            }
+          qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
+        }
+      else
+        ++i;
+    }
+}
+
+/* Clear implies relations which contain PRs in the given masks.
+   P1_MASK indicates the source of the implies relation, while P2_MASK
+   indicates the implied PR.
+*/
+static void
+clear_qp_implies (p1_mask, p2_mask)
+  valueT p1_mask;
+  valueT p2_mask;
+{
+  int i;
+
+  i = 0;
+  while (i < qp_implieslen)
+    {
+      if ((((valueT)1 << qp_implies[i].p1) & p1_mask) != 0
+          || (((valueT)1 << qp_implies[i].p2) & p2_mask) != 0)
+        {
+          if (md.debug_dv)
+            fprintf (stderr, "Clearing implied relation PR%d->PR%d\n", 
+                     qp_implies[i].p1, qp_implies[i].p2);
+          qp_implies[i] = qp_implies[--qp_implieslen];
+        }
+      else 
+        ++i;
+    }
+}
+
+/* add the PRs specified to the list of implied relations */
+static void
+add_qp_imply (p1, p2)
+  int p1, p2;
+{
+  valueT mask;
+  valueT bit;
+  int i;
+
+  /* p0 is not meaningful here */
+  if (p1 == 0 || p2 == 0)
+    abort ();
+
+  if (p1 == p2)
+    return;
+
+  /* if it exists already, ignore it */
+  for (i=0;i < qp_implieslen;i++)
+    {
+      if (qp_implies[i].p1 == p1 
+          && qp_implies[i].p2 == p2
+          && qp_implies[i].path == md.path
+          && !qp_implies[i].p2_branched)
+        return;
+    }
+
+  if (qp_implieslen == qp_impliestotlen)
+    {
+      qp_impliestotlen += 20;
+      qp_implies = (struct qp_imply *)
+        xrealloc ((void *)qp_implies, 
+                  qp_impliestotlen * sizeof (struct qp_imply));
+    }
+  if (md.debug_dv)
+    fprintf (stderr, "  Registering PR%d implies PR%d\n", p1, p2);
+  qp_implies[qp_implieslen].p1 = p1;
+  qp_implies[qp_implieslen].p2 = p2;
+  qp_implies[qp_implieslen].path = md.path;
+  qp_implies[qp_implieslen++].p2_branched = 0;
+
+  /* Add in the implied transitive relations; for everything that p2 implies,
+     make p1 imply that, too; for everything that implies p1, make it imply p2
+     as well. */
+  for (i=0;i < qp_implieslen;i++)
+    {
+      if (qp_implies[i].p1 == p2)
+        add_qp_imply (p1, qp_implies[i].p2);
+      if (qp_implies[i].p2 == p1)
+        add_qp_imply (qp_implies[i].p1, p2);
+    }
+  /* Add in mutex relations implied by this implies relation; for each mutex
+     relation containing p2, duplicate it and replace p2 with p1. */
+  bit = (valueT)1 << p1;
+  mask = (valueT)1 << p2;
+  for (i=0;i < qp_mutexeslen;i++)
+    {
+      if (qp_mutexes[i].prmask & mask)
+        add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
+    }
+}
+
+
+/* Add the PRs specified in the mask to the mutex list; this means that only
+   one of the PRs can be true at any time.  PR0 should never be included in
+   the mask.  */
+static void
+add_qp_mutex (mask)
+  valueT mask;
+{
+  if (mask & 0x1)
+    abort ();
+
+  if (qp_mutexeslen == qp_mutexestotlen)
+    {
+      qp_mutexestotlen += 20;
+      qp_mutexes = (struct qpmutex *)
+        xrealloc ((void *)qp_mutexes, 
+                  qp_mutexestotlen * sizeof (struct qpmutex));
+    }
+  if (md.debug_dv)
+    {
+      fprintf (stderr, "  Registering mutex on");
+      print_prmask (mask);
+      fprintf (stderr, "\n");
+    }
+  qp_mutexes[qp_mutexeslen].path = md.path;
+  qp_mutexes[qp_mutexeslen++].prmask = mask;
+}
+
+static void
+clear_register_values ()
+{
+  int i;
+  if (md.debug_dv)
+    fprintf (stderr, "  Clearing register values\n");
+  for (i=1;i < NELEMS(gr_values);i++)
+    gr_values[i].known = 0;
+}
+
+/* Keep track of register values/changes which affect DV tracking.
+
+   optimization note: should add a flag to classes of insns where otherwise we
+   have to examine a group of strings to identify them.
+
+ */
+static void
+note_register_values (idesc)
+  struct ia64_opcode *idesc;
+{
+  valueT qp_changemask = 0;
+  int i;
+
+  /* invalidate values for registers being written to */
+  for (i=0;i < idesc->num_outputs;i++)
+    {
+      if (idesc->operands[i] == IA64_OPND_R1 
+          || idesc->operands[i] == IA64_OPND_R2
+          || idesc->operands[i] == IA64_OPND_R3)
+        {
+          int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
+          if (regno > 0 && regno < NELEMS(gr_values))
+            gr_values[regno].known = 0;
+        }
+      else if (idesc->operands[i] == IA64_OPND_P1 
+               || idesc->operands[i] == IA64_OPND_P2)
+        {
+          int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
+          qp_changemask |= (valueT)1 << regno;
+        }
+      else if (idesc->operands[i] == IA64_OPND_PR)
+        {
+          if (idesc->operands[2] & (valueT)0x10000)
+            qp_changemask = ~(valueT)0x1FFFF | idesc->operands[2];
+          else 
+            qp_changemask = idesc->operands[2];
+          break;
+        }
+      else if (idesc->operands[i] == IA64_OPND_PR_ROT)
+        {
+          if (idesc->operands[1] & ((valueT)1 << 43))
+            qp_changemask = ~(valueT)0xFFFFFFFFFFF | idesc->operands[1];
+          else
+            qp_changemask = idesc->operands[1];
+          qp_changemask &= ~(valueT)0xFFFF;
+          break;
+        }
+    }
+
+  /* Always clear qp branch flags on any PR change */
+  /* FIXME there may be exceptions for certain compares */
+  clear_qp_branch_flag (qp_changemask);
+
+  /* invalidate rotating registers on insns which affect RRBs in CFM */
+  if (idesc->flags & IA64_OPCODE_MOD_RRBS)
+    {
+      qp_changemask |= ~(valueT)0xFFFF;
+      if (strcmp (idesc->name, "clrrrb.pr") != 0)
+        {
+          for (i=32;i < 32+md.rot.num_regs;i++)
+            gr_values[i].known = 0;
+        }
+      clear_qp_mutex (qp_changemask);
+      clear_qp_implies (qp_changemask, qp_changemask);
+    }
+  /* after a call, all register values are undefined, except those marked
+     as "safe" */
+  else if (strncmp (idesc->name, "br.call", 6) == 0
+           || strncmp (idesc->name, "brl.call", 7) == 0)
+    {
+      // FIXME keep GR values which are marked as "safe_across_calls"
+      clear_register_values ();
+      clear_qp_mutex (~qp_safe_across_calls);
+      clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
+      clear_qp_branch_flag (~qp_safe_across_calls);
+    }
+  /* Look for mutex and implies relations */
+  else if ((idesc->operands[0] == IA64_OPND_P1 
+            || idesc->operands[0] == IA64_OPND_P2)
+           && (idesc->operands[1] == IA64_OPND_P1
+               || idesc->operands[1] == IA64_OPND_P2))
+    {
+      int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
+      int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 
+      valueT p1mask = (valueT)1 << p1;
+      valueT p2mask = (valueT)1 << p2;
+
+      /* if one of the PRs is PR0, we can't really do anything */
+      if (p1 == 0 || p2 == 0)
+        {
+          if (md.debug_dv)
+            fprintf (stderr, "  Ignoring PRs due to inclusion of p0\n");
+        }
+      /* In general, clear mutexes and implies which include P1 or P2,
+         with the following exceptions */
+      else if (strstr (idesc->name, ".or.andcm") != NULL)
+        {
+          add_qp_mutex (p1mask | p2mask);
+          clear_qp_implies (p2mask, p1mask);
+        }
+      else if (strstr (idesc->name, ".and.orcm") != NULL)
+        {
+          add_qp_mutex (p1mask | p2mask);
+          clear_qp_implies (p1mask, p2mask);
+        }
+      else if (strstr (idesc->name, ".and") != NULL)
+        {
+          clear_qp_implies (0, p1mask | p2mask);
+        }
+      else if (strstr (idesc->name, ".or") != NULL)
+        {
+          clear_qp_mutex (p1mask | p2mask);
+          clear_qp_implies (p1mask | p2mask, 0);
+        }
+      else
+        {
+          clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
+          if (strstr (idesc->name, ".unc") != NULL)
+            {
+              add_qp_mutex (p1mask | p2mask);
+              if (CURR_SLOT.qp_regno != 0)
+                {
+                  add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P, 
+                                CURR_SLOT.qp_regno);
+                  add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P, 
+                                CURR_SLOT.qp_regno);
+                }
+            }
+          else if (CURR_SLOT.qp_regno == 0)
+            {
+              add_qp_mutex (p1mask | p2mask);
+            }
+          else 
+            {
+              clear_qp_mutex (p1mask | p2mask);
+            }
+        }
+    }
+  /* Look for mov imm insns into GRs */
+  else if (idesc->operands[0] == IA64_OPND_R1
+      && (idesc->operands[1] == IA64_OPND_IMM22
+          || idesc->operands[1] == IA64_OPND_IMMU64)
+      && (strcmp(idesc->name, "mov") == 0
+          || strcmp(idesc->name, "movl") == 0))
+    {
+      int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
+      if (regno > 0 && regno < NELEMS(gr_values))
+        {
+          gr_values[regno].known = 1;
+          gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
+          gr_values[regno].path = md.path;
+          if (md.debug_dv)
+            fprintf (stderr, "  Know gr%d = 0x%llx\n", 
+                     regno, gr_values[regno].value);
+        }
+    }
+  else 
+    {
+      clear_qp_mutex (qp_changemask);
+      clear_qp_implies (qp_changemask, qp_changemask);
+    }
+}
+
+/* Return whether the given predicate registers are currently mutex */
+static int
+qp_mutex (p1, p2, path)
+  int p1;
+  int p2;
+  int path;
+{
+  int i;
+  valueT mask;
+
+  if (p1 != p2)
+    {
+      mask = ((valueT)1<<p1) | (valueT)1<<p2;
+      for (i=0;i < qp_mutexeslen;i++)
+        {
+          if (qp_mutexes[i].path >= path
+              && (qp_mutexes[i].prmask & mask) == mask)
+            return 1;
+        }
+    }
+  return 0;
+}
+
+/* Return whether the given resource is in the given insn's list of chks
+   Return 1 if the conflict is absolutely determined, 2 if it's a potential
+   conflict. 
+ */ 
+static int
+resources_match (rs, idesc, note, qp_regno, path)
+  struct rsrc *rs;
+  struct ia64_opcode *idesc;
+  int note;
+  int qp_regno;
+  int path;
+{
+  struct rsrc specs[MAX_SPECS];
+  int count;
+
+  /* If the marked resource's qp_regno and the given qp_regno are mutex,
+     we don't need to check.  One exception is note 11, which indicates that
+     target predicates are written regardless of PR[qp].  */
+  if (qp_mutex (rs->qp_regno, qp_regno, path) 
+      && note != 11)
+    return 0;
+
+  count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
+  while (count-- > 0)
+    {
+      /* UNAT checking is a bit more specific than other resources */
+      if (rs->dependency->specifier == IA64_RS_AR_UNAT
+          && specs[count].mem_offset.hint
+          && rs->mem_offset.hint)
+        {
+          if (rs->mem_offset.base == specs[count].mem_offset.base)
+            {
+              if (((rs->mem_offset.offset >> 3) & 0x3F) == 
+                  ((specs[count].mem_offset.offset >> 3) & 0x3F))
+                return 1;
+              else
+                continue;
+            }
+        }
+
+      /* If either resource is not specific, conservatively assume a conflict
+       */ 
+      if (!specs[count].specific || !rs->specific)
+        return 2;
+      else if (specs[count].index == rs->index)
+        return 1;
+    }
+#if 0
+  if (md.debug_dv)
+    fprintf (stderr, "  No %s conflicts\n", rs->dependency->name);
+#endif
+
+  return 0;
+}
+
+/* Indicate an instruction group break; if INSERT_STOP is non-zero, then
+   insert a stop to create the break.  Update all resource dependencies
+   appropriately.  If QP_REGNO is non-zero, only apply the break to resources
+   which use the same QP_REGNO and have the link_to_qp_branch flag set.
+   If SAVE_CURRENT is non-zero, don't affect resources marked by the current
+   instruction. 
+*/ 
+
+static void
+insn_group_break (insert_stop, qp_regno, save_current)
+  int insert_stop;
+  int qp_regno;
+  int save_current;
+{
+  int i;
+
+  if (insert_stop && md.num_slots_in_use > 0)
+    PREV_SLOT.end_of_insn_group = 1;
+
+  if (md.debug_dv)
+    {
+      fprintf (stderr, "  Insn group break%s", 
+               (insert_stop ? " (w/stop)" : ""));
+      if (qp_regno != 0)
+        fprintf (stderr, " effective for QP=%d", qp_regno);
+      fprintf (stderr, "\n");
+    }
+
+  i = 0;
+  while (i < regdepslen)
+    {
+      const struct ia64_dependency *dep = regdeps[i].dependency;
+
+      if (qp_regno != 0
+          && regdeps[i].qp_regno != qp_regno)
+        {
+          ++i;
+          continue;
+        }
+
+      if (save_current
+          && CURR_SLOT.src_file == regdeps[i].file
+          && CURR_SLOT.src_line == regdeps[i].line)
+        {
+          ++i;
+          continue;
+        }
+
+      /* clear dependencies which are automatically cleared by a stop, or
+         those that have reached the appropriate state of insn serialization */
+      if (dep->semantics == IA64_DVS_IMPLIED
+          || dep->semantics == IA64_DVS_IMPLIEDF
+          || regdeps[i].insn_srlz == STATE_SRLZ)
+        {
+          print_dependency ("Removing", i);
+          regdeps[i] = regdeps[--regdepslen];
+        }
+      else
+        {
+          if (dep->semantics == IA64_DVS_DATA
+              || dep->semantics == IA64_DVS_INSTR
+	      || dep->semantics == IA64_DVS_SPECIFIC)
+            {
+              if (regdeps[i].insn_srlz == STATE_NONE)
+                regdeps[i].insn_srlz = STATE_STOP;
+              if (regdeps[i].data_srlz == STATE_NONE)
+                regdeps[i].data_srlz = STATE_STOP;
+            }
+          ++i;
+        }
+    }
+}
+
+/* Add the given resource usage spec to the list of active dependencies */
+static void 
+mark_resource (idesc, dep, spec, depind, path)
+  struct ia64_opcode *idesc;
+  const struct ia64_dependency *dep;
+  struct rsrc *spec;
+  int depind;
+  int path;
+{
+  if (regdepslen == regdepstotlen)
+    {
+      regdepstotlen += 20;
+      regdeps = (struct rsrc *)
+        xrealloc ((void *)regdeps, 
+                  regdepstotlen * sizeof(struct rsrc));
+    }
+
+  regdeps[regdepslen] = *spec;
+  regdeps[regdepslen].depind = depind;
+  regdeps[regdepslen].path = path;
+  regdeps[regdepslen].file = CURR_SLOT.src_file;
+  regdeps[regdepslen].line = CURR_SLOT.src_line;
+
+  print_dependency ("Adding", regdepslen);
+
+  ++regdepslen;
+}
+
+static void
+print_dependency (action, depind)
+  const char *action;
+  int depind;
+{
+  if (md.debug_dv)
+    {
+      fprintf (stderr, "  %s %s '%s'", 
+               action, dv_mode[(regdeps[depind].dependency)->mode],
+               (regdeps[depind].dependency)->name);
+      if (regdeps[depind].specific && regdeps[depind].index != 0)
+        fprintf (stderr, " (%d)", regdeps[depind].index);
+      if (regdeps[depind].mem_offset.hint)
+        fprintf (stderr, " 0x%llx+0x%llx",
+                 regdeps[depind].mem_offset.base,
+                 regdeps[depind].mem_offset.offset);
+      fprintf (stderr, "\n");
+    }
+}
+
+static void
+instruction_serialization ()
+{
+  int i;
+  if (md.debug_dv)
+    fprintf (stderr, "  Instruction serialization\n");
+  for (i=0;i < regdepslen;i++)
+    if (regdeps[i].insn_srlz == STATE_STOP)
+      regdeps[i].insn_srlz = STATE_SRLZ;
+}
+
+static void
+data_serialization ()
+{
+  int i = 0;
+  if (md.debug_dv)
+    fprintf (stderr, "  Data serialization\n");
+  while (i < regdepslen)
+    {
+      if (regdeps[i].data_srlz == STATE_STOP
+          /* Note: as of 991210, all "other" dependencies are cleared by a
+             data serialization.  This might change with new tables */
+          || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
+        {
+          print_dependency ("Removing", i);
+          regdeps[i] = regdeps[--regdepslen];
+        }
+      else
+        ++i;
+    }
+}
+
+/* Insert stops and serializations as needed to avoid DVs */
+static void
+remove_marked_resource (rs)
+  struct rsrc *rs;
+{
+  switch (rs->dependency->semantics)
+    {
+    case IA64_DVS_SPECIFIC:
+      if (md.debug_dv)
+	fprintf (stderr, "Implementation-specific, assume worst case...\n");
+      /* ...fall through... */
+    case IA64_DVS_INSTR:
+      if (md.debug_dv)
+        fprintf (stderr, "Inserting instr serialization\n");
+      if (rs->insn_srlz < STATE_STOP)
+        insn_group_break (1, 0, 0);
+      if (rs->insn_srlz < STATE_SRLZ)
+        {
+          int oldqp = CURR_SLOT.qp_regno;
+          struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
+          /* Manually jam a srlz.i insn into the stream */
+          CURR_SLOT.qp_regno = 0;
+          CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
+          instruction_serialization ();
+          md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
+          if (++md.num_slots_in_use >= NUM_SLOTS)
+            emit_one_bundle ();
+          CURR_SLOT.qp_regno = oldqp;
+          CURR_SLOT.idesc = oldidesc;
+        }
+      insn_group_break (1, 0, 0);
+      break;
+    case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
+                            "other" types of DV are eliminated
+                            by a data serialization */
+    case IA64_DVS_DATA:
+      if (md.debug_dv)
+        fprintf (stderr, "Inserting data serialization\n");
+      if (rs->data_srlz < STATE_STOP)
+        insn_group_break (1, 0, 0);
+      {
+        int oldqp = CURR_SLOT.qp_regno;
+        struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
+        /* Manually jam a srlz.d insn into the stream */
+        CURR_SLOT.qp_regno = 0;
+        CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
+        data_serialization ();
+        md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
+        if (++md.num_slots_in_use >= NUM_SLOTS)
+          emit_one_bundle ();
+        CURR_SLOT.qp_regno = oldqp;
+        CURR_SLOT.idesc = oldidesc;
+      }
+      break;
+    case IA64_DVS_IMPLIED:
+    case IA64_DVS_IMPLIEDF:
+      if (md.debug_dv)
+        fprintf (stderr, "Inserting stop\n");
+      insn_group_break (1, 0, 0);
+      break;
+    default:
+      break;
+    }
+}
+
+/* Check the resources used by the given opcode against the current dependency
+   list.  
+
+   The check is run once for each execution path encountered.  In this case,
+   a unique execution path is the sequence of instructions following a code
+   entry point, e.g. the following has three execution paths, one starting
+   at L0, one at L1, and one at L2.
+   
+   L0:     nop
+   L1:     add
+   L2:     add
+   br.ret        
+*/
+static void
+check_dependencies (idesc)
+  struct ia64_opcode *idesc;
+{
+  const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
+  int path;
+  int i;
+
+  /* Note that the number of marked resources may change within the
+     loop if in auto mode. */
+  i = 0;
+  while (i < regdepslen)
+    {
+      struct rsrc *rs = &regdeps[i];
+      const struct ia64_dependency *dep = rs->dependency;
+      int chkind;
+      int note;
+      int start_over = 0;
+
+      if (dep->semantics == IA64_DVS_NONE
+          || (chkind = depends_on (rs->depind, idesc)) == -1)
+        {
+          ++i; continue;
+        }
+
+      note = NOTE(opdeps->chks[chkind]);
+
+      /* Check this resource against each execution path seen thus far */
+      for (path=0;path <= md.path;path++)
+        {
+          int matchtype;
+
+          /* If the dependency wasn't on the path being checked, ignore it */
+          if (rs->path < path)
+            continue;
+
+          /* If the QP for this insn implies a QP which has branched, don't
+             bother checking.  Ed. NOTE: I don't think this check is terribly
+             useful; what's the point of generating code which will only be
+             reached if its QP is zero? 
+             This code was specifically inserted to handle the following code,
+             based on notes from Intel's DV checking code, where p1 implies p2.
+
+                  mov r4 = 2
+             (p2) br.cond L
+             (p1) mov r4 = 7
+
+          */  
+          if (CURR_SLOT.qp_regno != 0) 
+            {
+              int skip = 0;
+              int implies;
+              for (implies=0;implies < qp_implieslen;implies++)
+                {
+                  if (qp_implies[implies].path >= path
+                      && qp_implies[implies].p1 == CURR_SLOT.qp_regno
+                      && qp_implies[implies].p2_branched)
+                    {
+                      skip = 1;
+                      break;
+                    }
+                }
+              if (skip)
+                continue;
+            }
+
+          if ((matchtype = resources_match (rs, idesc, note, 
+                                            CURR_SLOT.qp_regno, path)) != 0)
+            {
+              char msg[1024];
+              char pathmsg[256] = "";
+              char indexmsg[256] = "";
+              int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
+
+              if (path != 0)
+                sprintf (pathmsg, " when entry is at label '%s'",
+                         md.entry_labels[path-1]);
+              if (rs->specific && rs->index != 0)
+                sprintf (indexmsg, ", specific resource number is %d", 
+                         rs->index);
+              sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
+                       idesc->name, 
+                       (certain ? "violates" : "may violate"),
+                       dv_mode[dep->mode], dep->name, 
+                       dv_sem[dep->semantics],
+                       pathmsg, indexmsg);
+
+              if (md.explicit_mode)
+                {
+                  as_warn ("%s", msg);
+                  if (path < md.path)
+                    as_warn (_("Only the first path encountering the conflict "
+                               "is reported"));
+                  as_warn_where (rs->file, rs->line,
+                                 _("This is the location of the "
+                                   "conflicting usage"));
+                  /* Don't bother checking other paths, to avoid duplicating
+                     the same warning */
+                  break;
+                }
+              else
+                {
+                  if (md.debug_dv)
+                    fprintf(stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
+                  
+                  remove_marked_resource (rs);
+                  
+                  /* since the set of dependencies has changed, start over */
+                  /* FIXME -- since we're removing dvs as we go, we
+                     probably don't really need to start over... */
+                  start_over = 1;
+                  break;
+                }
+            }
+        }
+      if (start_over)
+        i = 0;
+      else
+        ++i;
+    }
+}
+
+/* register new dependencies based on the given opcode */
+static void
+mark_resources (idesc)
+  struct ia64_opcode *idesc;
+{
+  int i;
+  const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
+  int add_only_qp_reads = 0;
+
+  /* A conditional branch only uses its resources if it is taken; if it is
+     taken, we stop following that path.  The other branch types effectively
+     *always* write their resources.  If it's not taken, register only QP
+     reads.  */ 
+  if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
+    {
+      add_only_qp_reads = 1;
+    }
+
+  if (md.debug_dv)
+    fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
+
+  for (i=0;i < opdeps->nregs;i++)
+    {
+      const struct ia64_dependency *dep;
+      struct rsrc specs[MAX_SPECS];
+      int note;
+      int path;
+      int count;
+      
+      dep = ia64_find_dependency (opdeps->regs[i]);
+      note = NOTE(opdeps->regs[i]);
+
+      if (add_only_qp_reads
+          && !(dep->mode == IA64_DV_WAR
+               && (dep->specifier == IA64_RS_PR
+                   || dep->specifier == IA64_RS_PR63)))
+        continue;
+
+      count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
+
+#if 0
+      if (md.debug_dv && !count)
+        fprintf (stderr, "  No %s %s usage found (path %d)\n", 
+                 dv_mode[dep->mode], dep->name, md.path);
+#endif
+      
+      while (count-- > 0)
+        {
+          mark_resource (idesc, dep, &specs[count], 
+                         DEP(opdeps->regs[i]), md.path);
+        }
+
+      /* The execution path may affect register values, which may in turn
+         affect which indirect-access resources are accessed. */
+      switch (dep->specifier)
+        {
+        default:
+          break;
+        case IA64_RS_CPUID:
+        case IA64_RS_DBR:
+        case IA64_RS_IBR:
+	case IA64_RS_MSR:
+        case IA64_RS_PKR:
+        case IA64_RS_PMC:
+        case IA64_RS_PMD:
+        case IA64_RS_RR:
+          for (path=0;path < md.path;path++)
+            {
+              count = specify_resource (dep, idesc, DV_REG, specs, note, path);
+              while (count-- > 0)
+                mark_resource (idesc, dep, &specs[count], 
+                               DEP(opdeps->regs[i]), path);
+            }
+          break;
+        }
+    }
+}
+
+/* remove dependencies when they no longer apply */
+static void
+update_dependencies (idesc)
+  struct ia64_opcode *idesc;
+{
+  int i;
+
+  if (strcmp (idesc->name, "srlz.i") == 0)
+    {
+      instruction_serialization ();
+    }
+  else if (strcmp (idesc->name, "srlz.d") == 0)
+    {
+      data_serialization ();
+    }
+  else if (is_interruption_or_rfi (idesc)
+           || is_taken_branch (idesc))
+    {
+      /* although technically the taken branch doesn't clear dependencies
+         which require a srlz.[id], we don't follow the branch; the next
+         instruction is assumed to start with a clean slate */
+      regdepslen = 0;
+      clear_register_values ();
+      clear_qp_mutex (~(valueT)0);
+      clear_qp_implies (~(valueT)0, ~(valueT)0);
+      md.path = 0;
+    }
+  else if (is_conditional_branch (idesc)
+           && CURR_SLOT.qp_regno != 0)
+    {
+      int is_call = strstr (idesc->name, ".call") != NULL;
+
+      for (i=0;i < qp_implieslen;i++)
+        {
+          /* if the conditional branch's predicate is implied by the predicate
+             in an existing dependency, remove that dependency */
+          if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
+            {
+              int depind = 0;
+              /* note that this implied predicate takes a branch so that if
+                 a later insn generates a DV but its predicate implies this
+                 one, we can avoid the false DV warning */
+              qp_implies[i].p2_branched = 1;
+              while (depind < regdepslen)
+                {
+                  if (regdeps[depind].qp_regno == qp_implies[i].p1)
+                    {
+                      print_dependency ("Removing", depind);
+                      regdeps[depind] = regdeps[--regdepslen];
+                    }
+                  else
+                    ++depind;
+                }
+            }
+        }
+      /* Any marked resources which have this same predicate should be
+         cleared, provided that the QP hasn't been modified between the
+         marking instruction and the branch.  
+      */
+      if (is_call)
+        {
+          insn_group_break (0, CURR_SLOT.qp_regno, 1);
+        }
+      else
+        {
+          i = 0;
+          while (i < regdepslen)
+            {
+              if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
+                  && regdeps[i].link_to_qp_branch
+                  && (regdeps[i].file != CURR_SLOT.src_file 
+                      || regdeps[i].line != CURR_SLOT.src_line))
+                {
+                  /* Treat like a taken branch */
+                  print_dependency ("Removing", i);
+                  regdeps[i] = regdeps[--regdepslen];
+                }
+              else
+                ++i;
+            }
+        }
+    }
+}
+
+/* Examine the current instruction for dependency violations.  */
+static int
+check_dv (idesc)
+  struct ia64_opcode *idesc;
+{
+  if (md.debug_dv)
+    {
+      fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n", 
+               idesc->name, CURR_SLOT.src_line, 
+               idesc->dependencies->nchks, 
+               idesc->dependencies->nregs);
+    }
+
+  /* Look through the list of currently marked resources; if the current 
+     instruction has the dependency in its chks list which uses that resource,
+     check against the specific resources used.  
+  */
+  check_dependencies (idesc);
+
+  /*
+    Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
+    then add them to the list of marked resources.
+  */
+  mark_resources (idesc);
+
+  /* There are several types of dependency semantics, and each has its own
+     requirements for being cleared 
+     
+     Instruction serialization (insns separated by interruption, rfi, or
+     writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
+
+     Data serialization (instruction serialization, or writer + srlz.d +
+     reader, where writer and srlz.d are in separate groups) clears
+     DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
+     always be the case).
+
+     Instruction group break (groups separated by stop, taken branch,
+     interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
+   */
+  update_dependencies (idesc);
+
+  /* Sometimes, knowing a register value allows us to avoid giving a false DV
+     warning.  Keep track of as many as possible that are useful. */
+  note_register_values (idesc);
+
+  /* We don't need or want this anymore. */
+  md.mem_offset.hint = 0;
+
+  return 0;
+}
+
+/* Translate one line of assembly.  Pseudo ops and labels do not show
+   here.  */
+void
+md_assemble (str)
+     char *str;
+{
+  char *saved_input_line_pointer, *mnemonic;
+  const struct pseudo_opcode *pdesc;
+  struct ia64_opcode *idesc;
+  unsigned char qp_regno;
+  unsigned int flags;
+  int ch;
+
+  saved_input_line_pointer = input_line_pointer;
+  input_line_pointer = str;
+
+  /* extract the opcode (mnemonic): */
+
+  mnemonic = input_line_pointer;
+  ch = get_symbol_end ();
+  pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
+  if (pdesc)
+    {
+      *input_line_pointer = ch;
+      (*pdesc->handler) (pdesc->arg);
+      goto done;
+    }
+
+  /* find the instruction descriptor matching the arguments: */
+
+  idesc = ia64_find_opcode (mnemonic);
+  *input_line_pointer = ch;
+  if (!idesc)
+    {
+      as_bad ("Unknown opcode `%s'", mnemonic);
+      goto done;
+    }
+
+  idesc = parse_operands (idesc);
+  if (!idesc)
+    goto done;
+
+  /* Handle the dynamic ops we can handle now: */
+  if (idesc->type == IA64_TYPE_DYN)
+    {
+      if (strcmp (idesc->name, "add") == 0)
+	{
+	  if (CURR_SLOT.opnd[2].X_op == O_register
+	      && CURR_SLOT.opnd[2].X_add_number < 4)
+	    mnemonic = "addl";
+	  else
+	    mnemonic = "adds";
+	  idesc = ia64_find_opcode (mnemonic);
+#if 0
+	  know (!idesc->next);
+#endif
+	}
+      else if (strcmp (idesc->name, "mov") == 0)
+	{
+	  enum ia64_opnd opnd1, opnd2;
+	  int rop;
+
+	  opnd1 = idesc->operands[0];
+	  opnd2 = idesc->operands[1];
+	  if (opnd1 == IA64_OPND_AR3)
+	    rop = 0;
+	  else if (opnd2 == IA64_OPND_AR3)
+	    rop = 1;
+	  else
+	    abort ();
+	  if (CURR_SLOT.opnd[rop].X_op == O_register
+	      && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
+	    mnemonic = "mov.i";
+	  else
+	    mnemonic = "mov.m";
+	  idesc = ia64_find_opcode (mnemonic);
+	  while (idesc != NULL
+		 && (idesc->operands[0] != opnd1
+		     || idesc->operands[1] != opnd2))
+	    idesc = get_next_opcode (idesc);
+	}
+    }
+
+  qp_regno = 0;
+  if (md.qp.X_op == O_register)
+    qp_regno = md.qp.X_add_number - REG_P;
+
+  flags = idesc->flags;
+
+  if ((flags & IA64_OPCODE_FIRST) != 0)
+    insn_group_break (1, 0, 0);
+
+  if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
+    {
+      as_bad ("`%s' cannot be predicated", idesc->name);
+      goto done;
+    }
+
+  /* build the instruction: */
+  CURR_SLOT.qp_regno = qp_regno;
+  CURR_SLOT.idesc = idesc;
+  as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
+  if (debug_type == DEBUG_DWARF2)
+    dwarf2_where (&CURR_SLOT.debug_line);
+
+  /* Add unwind entry, if there is one.  */
+  if (current_unwind_entry)
+    {
+      CURR_SLOT.unwind_record = current_unwind_entry;
+      current_unwind_entry = NULL;
+    }
+
+  /* check for dependency violations */
+  if (md.detect_dv)
+    check_dv(idesc);
+
+  md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
+  if (++md.num_slots_in_use >= NUM_SLOTS)
+    emit_one_bundle ();
+
+  if ((flags & IA64_OPCODE_LAST) != 0)
+    insn_group_break (1, 0, 0);
+
+  md.last_text_seg = now_seg;
+
+ done:
+  input_line_pointer = saved_input_line_pointer;
+}
+
+/* Called when symbol NAME cannot be found in the symbol table.
+   Should be used for dynamic valued symbols only.  */
+symbolS*
+md_undefined_symbol (name)
+     char *name;
+{
+  return 0;
+}
+
+/* Called for any expression that can not be recognized.  When the
+   function is called, `input_line_pointer' will point to the start of
+   the expression.  */
+void
+md_operand (e)
+     expressionS *e;
+{
+  enum pseudo_type pseudo_type;
+  size_t len;
+  int ch, i;
+
+  switch (*input_line_pointer)
+    {
+    case '@':
+      /* find what relocation pseudo-function we're dealing with: */
+      pseudo_type = 0;
+      ch = *++input_line_pointer;
+      for (i = 0; i < NELEMS (pseudo_func); ++i)
+	if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
+	  {
+	    len = strlen (pseudo_func[i].name);
+	    if (strncmp (pseudo_func[i].name + 1,
+			 input_line_pointer + 1, len - 1) == 0
+		&& !is_part_of_name (input_line_pointer[len]))
+	      {
+		input_line_pointer += len;
+		pseudo_type = pseudo_func[i].type;
+		break;
+	      }
+	  }
+      switch (pseudo_type)
+	{
+	case PSEUDO_FUNC_RELOC:
+	  SKIP_WHITESPACE ();
+	  if (*input_line_pointer != '(')
+	    {
+	      as_bad ("Expected '('");
+	      goto err;
+	    }
+	  ++input_line_pointer;	/* skip '(' */
+	  expression (e);
+	  if (*input_line_pointer++ != ')')
+	    {
+	      as_bad ("Missing ')'");
+	      goto err;
+	    }
+	  if (e->X_op != O_symbol)
+	    {
+	      if (e->X_op != O_pseudo_fixup)
+		{
+		  as_bad ("Not a symbolic expression");
+		  goto err;
+		}
+	      if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE
+		  && i == FUNC_LT_RELATIVE)
+		i = FUNC_LT_FPTR_RELATIVE;
+	      else
+		{
+		  as_bad ("Illegal combination of relocation functions");
+		  goto err;
+		}
+	    }
+	  /* make sure gas doesn't get rid of local symbols that are used
+	     in relocs: */
+	  e->X_op = O_pseudo_fixup;
+	  e->X_op_symbol = pseudo_func[i].u.sym;
+	  break;
+
+	case PSEUDO_FUNC_CONST:
+	  e->X_op = O_constant;
+	  e->X_add_number = pseudo_func[i].u.ival;
+	  break;
+
+	default:
+	  as_bad ("Unknown pseudo function `%s'", input_line_pointer - 1);
+	  goto err;
+	}
+      break;
+
+    case '[':
+      ++input_line_pointer;
+      expression (e);
+      if (*input_line_pointer != ']')
+	{
+	  as_bad ("Closing bracket misssing");
+	  goto err;
+	}
+      else
+	{
+	  if (e->X_op != O_register)
+	    as_bad ("Register expected as index");
+
+	  ++input_line_pointer;
+	  e->X_op = O_index;
+	}
+      break;
+
+    default:
+      break;
+    }
+  return;
+
+ err:
+  ignore_rest_of_line ();
+}
+
+/* Return 1 if it's OK to adjust a reloc by replacing the symbol with
+   a section symbol plus some offset.  For relocs involving @fptr(),
+   directives we don't want such adjustments since we need to have the
+   original symbol's name in the reloc.  */
+int
+ia64_fix_adjustable (fix)
+     fixS *fix;
+{
+  /* Prevent all adjustments to global symbols */
+  if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
+    return 0;
+
+  switch (fix->fx_r_type)
+    {
+    case BFD_RELOC_IA64_FPTR64I:
+    case BFD_RELOC_IA64_FPTR32MSB:
+    case BFD_RELOC_IA64_FPTR32LSB:
+    case BFD_RELOC_IA64_FPTR64MSB:
+    case BFD_RELOC_IA64_FPTR64LSB:
+    case BFD_RELOC_IA64_LTOFF_FPTR22:
+    case BFD_RELOC_IA64_LTOFF_FPTR64I:
+      return 0;
+    default:
+      break;
+    }
+
+  return 1;
+}
+
+int
+ia64_force_relocation (fix)
+     fixS *fix;
+{
+  switch (fix->fx_r_type)
+    {
+    case BFD_RELOC_IA64_FPTR64I:
+    case BFD_RELOC_IA64_FPTR32MSB:
+    case BFD_RELOC_IA64_FPTR32LSB:
+    case BFD_RELOC_IA64_FPTR64MSB:
+    case BFD_RELOC_IA64_FPTR64LSB:
+
+    case BFD_RELOC_IA64_LTOFF22:
+    case BFD_RELOC_IA64_LTOFF64I:
+    case BFD_RELOC_IA64_LTOFF_FPTR22:
+    case BFD_RELOC_IA64_LTOFF_FPTR64I:
+    case BFD_RELOC_IA64_PLTOFF22:
+    case BFD_RELOC_IA64_PLTOFF64I:
+    case BFD_RELOC_IA64_PLTOFF64MSB:
+    case BFD_RELOC_IA64_PLTOFF64LSB:
+      return 1;
+
+    default:
+      return 0;
+    }
+  return 0;
+}
+
+/* Decide from what point a pc-relative relocation is relative to,
+   relative to the pc-relative fixup.  Er, relatively speaking.  */
+long
+ia64_pcrel_from_section (fix, sec)
+     fixS *fix;
+     segT sec;
+{
+  unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
+  
+  if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
+    off &= ~0xfUL;
+
+  return off;
+}
+
+/* This is called whenever some data item (not an instruction) needs a
+   fixup.  We pick the right reloc code depending on the byteorder
+   currently in effect.  */
+void
+ia64_cons_fix_new (f, where, nbytes, exp)
+     fragS *f;
+     int where;
+     int nbytes;
+     expressionS *exp;
+{
+  bfd_reloc_code_real_type code;
+  fixS *fix;
+
+  switch (nbytes)
+    {
+      /* There are no reloc for 8 and 16 bit quantities, but we allow
+	 them here since they will work fine as long as the expression
+	 is fully defined at the end of the pass over the source file.  */
+    case 1: code = BFD_RELOC_8; break;
+    case 2: code = BFD_RELOC_16; break;
+    case 4:
+      if (target_big_endian)
+	code = BFD_RELOC_IA64_DIR32MSB;
+      else
+	code = BFD_RELOC_IA64_DIR32LSB;
+      break;
+
+    case 8:
+      if (target_big_endian)
+	code = BFD_RELOC_IA64_DIR64MSB;
+      else
+	code = BFD_RELOC_IA64_DIR64LSB;
+      break;
+
+    default:
+      as_bad ("Unsupported fixup size %d", nbytes);
+      ignore_rest_of_line ();
+      return;
+    }
+  if (exp->X_op == O_pseudo_fixup)
+    {
+      /* ??? */
+      exp->X_op = O_symbol;
+      code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
+    }
+  fix = fix_new_exp (f, where, nbytes, exp, 0, code);
+  /* We need to store the byte order in effect in case we're going
+     to fix an 8 or 16 bit relocation (for which there no real
+     relocs available).  See md_apply_fix().  */
+  fix->tc_fix_data.bigendian = target_big_endian;
+}
+
+/* Return the actual relocation we wish to associate with the pseudo
+   reloc described by SYM and R_TYPE.  SYM should be one of the
+   symbols in the pseudo_func array, or NULL. */
+
+static bfd_reloc_code_real_type
+ia64_gen_real_reloc_type (sym, r_type)
+     struct symbol *sym;
+     bfd_reloc_code_real_type r_type;
+{
+  bfd_reloc_code_real_type new = 0;
+
+  if (sym == NULL)
+    {
+      return r_type;
+    }
+
+  switch (S_GET_VALUE (sym))
+    {
+    case FUNC_FPTR_RELATIVE:
+      switch (r_type)
+	{
+	case BFD_RELOC_IA64_IMM64:	new = BFD_RELOC_IA64_FPTR64I; break;
+	case BFD_RELOC_IA64_DIR32MSB:	new = BFD_RELOC_IA64_FPTR32MSB; break;
+	case BFD_RELOC_IA64_DIR32LSB:	new = BFD_RELOC_IA64_FPTR32LSB; break;
+	case BFD_RELOC_IA64_DIR64MSB:	new = BFD_RELOC_IA64_FPTR64MSB; break;
+	case BFD_RELOC_IA64_DIR64LSB:	new = BFD_RELOC_IA64_FPTR64LSB; break;
+	default:			break;
+	}
+      break;
+
+    case FUNC_GP_RELATIVE:
+      switch (r_type)
+	{
+	case BFD_RELOC_IA64_IMM22:	new = BFD_RELOC_IA64_GPREL22; break;
+	case BFD_RELOC_IA64_IMM64:	new = BFD_RELOC_IA64_GPREL64I; break;
+	case BFD_RELOC_IA64_DIR32MSB:	new = BFD_RELOC_IA64_GPREL32MSB; break;
+	case BFD_RELOC_IA64_DIR32LSB:	new = BFD_RELOC_IA64_GPREL32LSB; break;
+	case BFD_RELOC_IA64_DIR64MSB:	new = BFD_RELOC_IA64_GPREL64MSB; break;
+	case BFD_RELOC_IA64_DIR64LSB:	new = BFD_RELOC_IA64_GPREL64LSB; break;
+	default:			break;
+	}
+      break;
+
+    case FUNC_LT_RELATIVE:
+      switch (r_type)
+	{
+	case BFD_RELOC_IA64_IMM22:	new = BFD_RELOC_IA64_LTOFF22; break;
+	case BFD_RELOC_IA64_IMM64:	new = BFD_RELOC_IA64_LTOFF64I; break;
+	default:			break;
+	}
+      break;
+
+    case FUNC_PLT_RELATIVE:
+      switch (r_type)
+	{
+	case BFD_RELOC_IA64_IMM22:	new = BFD_RELOC_IA64_PLTOFF22; break;
+	case BFD_RELOC_IA64_IMM64:	new = BFD_RELOC_IA64_PLTOFF64I; break;
+	case BFD_RELOC_IA64_DIR64MSB:	new = BFD_RELOC_IA64_PLTOFF64MSB;break;
+	case BFD_RELOC_IA64_DIR64LSB:	new = BFD_RELOC_IA64_PLTOFF64LSB;break;
+	default:			break;
+	}
+      break;
+
+    case FUNC_SEC_RELATIVE:
+      switch (r_type)
+	{
+	case BFD_RELOC_IA64_DIR32MSB:	new = BFD_RELOC_IA64_SECREL32MSB;break;
+	case BFD_RELOC_IA64_DIR32LSB:	new = BFD_RELOC_IA64_SECREL32LSB;break;
+	case BFD_RELOC_IA64_DIR64MSB:	new = BFD_RELOC_IA64_SECREL64MSB;break;
+	case BFD_RELOC_IA64_DIR64LSB:	new = BFD_RELOC_IA64_SECREL64LSB;break;
+	default:			break;
+	}
+      break;
+
+    case FUNC_SEG_RELATIVE:
+      switch (r_type)
+	{
+	case BFD_RELOC_IA64_DIR32MSB:	new = BFD_RELOC_IA64_SEGREL32MSB;break;
+	case BFD_RELOC_IA64_DIR32LSB:	new = BFD_RELOC_IA64_SEGREL32LSB;break;
+	case BFD_RELOC_IA64_DIR64MSB:	new = BFD_RELOC_IA64_SEGREL64MSB;break;
+	case BFD_RELOC_IA64_DIR64LSB:	new = BFD_RELOC_IA64_SEGREL64LSB;break;
+	default:			break;
+	}
+      break;
+
+    case FUNC_LTV_RELATIVE:
+      switch (r_type)
+	{
+	case BFD_RELOC_IA64_DIR32MSB:	new = BFD_RELOC_IA64_LTV32MSB; break;
+	case BFD_RELOC_IA64_DIR32LSB:	new = BFD_RELOC_IA64_LTV32LSB; break;
+	case BFD_RELOC_IA64_DIR64MSB:	new = BFD_RELOC_IA64_LTV64MSB; break;
+	case BFD_RELOC_IA64_DIR64LSB:	new = BFD_RELOC_IA64_LTV64LSB; break;
+	default:			break;
+	}
+      break;
+
+    case FUNC_LT_FPTR_RELATIVE:
+      switch (r_type)
+	{
+	case BFD_RELOC_IA64_IMM22:
+	  new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
+	case BFD_RELOC_IA64_IMM64:
+	  new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
+	default:
+	  break;
+	}
+      break;
+    default:
+      abort ();
+    }
+  /* Hmmmm.  Should this ever occur?  */
+  if (new)
+    return new;
+  else
+    return r_type;
+}
+
+/* Here is where generate the appropriate reloc for pseudo relocation
+   functions.  */
+void
+ia64_validate_fix (fix)
+     fixS *fix;
+{
+  switch (fix->fx_r_type)
+    {
+    case BFD_RELOC_IA64_FPTR64I:
+    case BFD_RELOC_IA64_FPTR32MSB:
+    case BFD_RELOC_IA64_FPTR64LSB:
+    case BFD_RELOC_IA64_LTOFF_FPTR22:
+    case BFD_RELOC_IA64_LTOFF_FPTR64I:
+      if (fix->fx_offset != 0)
+	as_bad_where (fix->fx_file, fix->fx_line,
+		      "No addend allowed in @fptr() relocation");
+      break;
+    default:
+      break;
+    }
+
+  return;
+}
+
+static void
+fix_insn (fix, odesc, value)
+     fixS *fix;
+     const struct ia64_operand *odesc;
+     valueT value;
+{
+  bfd_vma insn[3], t0, t1, control_bits;
+  const char *err;
+  char *fixpos;
+  long slot;
+
+  slot = fix->fx_where & 0x3;
+  fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
+
+  /* bundles are always in little-endian byte order */
+  t0 = bfd_getl64 (fixpos);
+  t1 = bfd_getl64 (fixpos + 8);
+  control_bits = t0 & 0x1f;
+  insn[0] = (t0 >>  5) & 0x1ffffffffffLL;
+  insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
+  insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
+
+  err = (*odesc->insert) (odesc, value, insn + slot);
+  if (err)
+    {
+      as_bad_where (fix->fx_file, fix->fx_line, err);
+      return;
+    }
+
+  t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
+  t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
+  md_number_to_chars (fixpos + 0, t0, 8);
+  md_number_to_chars (fixpos + 8, t1, 8);
+  
+}
+
+/* Attempt to simplify or even eliminate a fixup.  The return value is
+   ignored; perhaps it was once meaningful, but now it is historical.
+   To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
+
+   If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
+   (if possible). */
+int
+md_apply_fix3 (fix, valuep, seg)
+     fixS *fix;
+     valueT *valuep;
+     segT seg;
+{
+  char *fixpos;
+  valueT value = *valuep;
+  int adjust = 0;
+
+  fixpos = fix->fx_frag->fr_literal + fix->fx_where;
+
+  if (fix->fx_pcrel)
+    {
+      switch (fix->fx_r_type)
+	{
+	case BFD_RELOC_IA64_DIR32MSB:
+	  fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
+	  adjust = 1;
+	  break;
+
+	case BFD_RELOC_IA64_DIR32LSB:
+	  fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
+	  adjust = 1;
+	  break;
+
+	case BFD_RELOC_IA64_DIR64MSB:
+	  fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
+	  adjust = 1;
+	  break;
+
+	case BFD_RELOC_IA64_DIR64LSB:
+	  fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
+	  adjust = 1;
+	  break;
+
+	default:
+	  break;
+	}
+    }
+  if (fix->fx_addsy)
+    {
+      switch (fix->fx_r_type)
+	{
+	case 0:
+	  as_bad_where (fix->fx_file, fix->fx_line,
+			"%s must have a constant value",
+			elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
+	  break;
+
+	default:
+	  break;
+	}
+
+      /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
+         work.  There should be a better way to handle this.  */
+      if (adjust)
+	fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address;
+    }
+  else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
+    {
+      if (fix->tc_fix_data.bigendian)
+	number_to_chars_bigendian (fixpos, value, fix->fx_size);
+      else
+	number_to_chars_littleendian (fixpos, value, fix->fx_size);
+      fix->fx_done = 1;
+      return 1;
+    }
+  else
+    {
+      fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
+      fix->fx_done = 1;
+      return 1;
+    }
+  return 1;
+}
+
+/* Generate the BFD reloc to be stuck in the object file from the
+   fixup used internally in the assembler.  */
+arelent*
+tc_gen_reloc (sec, fixp)
+     asection *sec;
+     fixS *fixp;
+{
+  arelent *reloc;
+
+  reloc = xmalloc (sizeof (*reloc));
+  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
+  reloc->addend = fixp->fx_offset;
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
+
+  if (!reloc->howto)
+    {
+      as_bad_where (fixp->fx_file, fixp->fx_line,
+		    "Cannot represent %s relocation in object file",
+		    bfd_get_reloc_code_name (fixp->fx_r_type));
+    }
+  return reloc;
+}
+
+/* Turn a string in input_line_pointer into a floating point constant
+   of type type, and store the appropriate bytes in *lit.  The number
+   of LITTLENUMS emitted is stored in *size.  An error message is
+   returned, or NULL on OK.  */
+
+#define MAX_LITTLENUMS 5
+
+char*
+md_atof (type, lit, size)
+     int type;
+     char *lit;
+     int *size;
+{
+  LITTLENUM_TYPE words[MAX_LITTLENUMS];
+  LITTLENUM_TYPE *word;
+  char *t;
+  int prec;
+
+  switch (type)
+    {
+      /* IEEE floats */
+    case 'f':
+    case 'F':
+    case 's':
+    case 'S':
+      prec = 2;
+      break;
+
+    case 'd':
+    case 'D':
+    case 'r':
+    case 'R':
+      prec = 4;
+      break;
+
+    case 'x':
+    case 'X':
+    case 'p':
+    case 'P':
+      prec = 5;
+      break;
+
+    default:
+      *size = 0;
+      return "Bad call to MD_ATOF()";
+    }
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+  *size = prec * sizeof (LITTLENUM_TYPE);
+
+  for (word = words + prec - 1; prec--;)
+    {
+      md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
+      lit += sizeof (LITTLENUM_TYPE);
+    }
+  return 0;
+}
+
+/* Round up a section's size to the appropriate boundary.  */
+valueT
+md_section_align (seg, size)
+     segT seg;
+     valueT size;
+{
+  int align = bfd_get_section_alignment (stdoutput, seg);
+  valueT mask = ((valueT)1 << align) - 1;
+
+  return (size + mask) & ~mask;
+}
+
+/* Handle ia64 specific semantics of the align directive.  */
+
+int
+ia64_md_do_align (n, fill, len, max)
+     int n;
+     const char *fill;
+     int len;
+     int max;
+{
+  /* Fill any pending bundle with nops.  */
+  if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
+    ia64_flush_insns ();
+
+  /* When we align code in a text section, emit a bundle of 3 nops instead of
+     zero bytes.  We can only do this if a multiple of 16 bytes was requested.
+     N is log base 2 of the requested alignment.  */
+  if (fill == NULL
+      && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE
+      && n > 4)
+    {
+      /* Use mfi bundle of nops with no stop bits.  */
+      static const unsigned char be_nop[]
+	= { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+	    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
+      static const unsigned char le_nop[]
+	= { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+	    0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
+	    
+      /* Make sure we are on a 16-byte boundary, in case someone has been
+	 putting data into a text section.  */
+      frag_align (4, 0, 0);
+
+      if (target_big_endian)
+	frag_align_pattern (n, be_nop, 16, max);
+      else
+	frag_align_pattern (n, le_nop, 16, max);
+      return 1;
+    }
+
+  return 0;
+}
diff --git a/gas/config/tc-ia64.h b/gas/config/tc-ia64.h
new file mode 100644
index 0000000..db8d7a4
--- /dev/null
+++ b/gas/config/tc-ia64.h
@@ -0,0 +1,218 @@
+/* tc-ia64.h -- Header file for tc-ia64.c.
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA. */
+
+#include <opcode/ia64.h>
+#include <elf/ia64.h>
+
+#define TC_IA64
+
+#define TARGET_FORMAT (OUTPUT_FLAVOR == bfd_target_elf_flavour		\
+		       ? "elf64-ia64-little"				\
+		       : "unknown-format")
+
+#define TARGET_ARCH			bfd_arch_ia64
+#define TARGET_BYTES_BIG_ENDIAN		0
+#define DOUBLESLASH_LINE_COMMENTS	/* allow //-style comments */
+#define md_number_to_chars		number_to_chars_littleendian
+#define TC_HANDLES_FX_DONE
+
+#define NEED_LITERAL_POOL		/* need gp literal pool */
+#define RELOC_REQUIRES_SYMBOL
+#define DIFF_EXPR_OK   /* foo-. gets turned into PC relative relocs */
+#define NEED_INDEX_OPERATOR		/* [ ] is index operator */
+
+#define QUOTES_IN_INSN			/* allow `string "foo;bar"' */
+#define LEX_AT		LEX_NAME	/* allow `@' inside name */
+#define LEX_QM		LEX_NAME	/* allow `?' inside name */
+#define LEX_HASH	LEX_END_NAME	/* allow `#' ending a name */
+
+struct ia64_fix
+  {
+    int bigendian;			/* byte order at fix location */
+    enum ia64_opnd opnd;
+  };
+
+extern void ia64_do_align PARAMS((int n));
+extern void ia64_end_of_source PARAMS((void));
+extern void ia64_start_line PARAMS((void));
+extern int ia64_unrecognized_line PARAMS((int ch));
+extern void ia64_frob_label PARAMS((struct symbol *sym));
+extern void ia64_flush_pending_output PARAMS((void));
+extern int ia64_parse_name (char *name, expressionS *e);
+extern int ia64_optimize_expr PARAMS((expressionS *l, operatorT op,
+				      expressionS *r));
+extern void ia64_cons_align PARAMS((int));
+extern void ia64_flush_insns PARAMS((void));
+extern int ia64_fix_adjustable PARAMS((struct fix *fix));
+extern int ia64_force_relocation PARAMS((struct fix *));
+extern void ia64_cons_fix_new PARAMS ((fragS *f, int where, int nbytes,
+				       expressionS *exp));
+extern void ia64_validate_fix PARAMS ((struct fix *fix));
+extern char * ia64_canonicalize_symbol_name PARAMS ((char *));
+extern flagword ia64_elf_section_flags PARAMS ((flagword, int, int));
+extern long ia64_pcrel_from_section PARAMS ((struct fix *fix, segT sec));
+extern int ia64_md_do_align PARAMS ((int, const char *, int, int));
+
+#define md_end()       			ia64_end_of_source ()
+#define md_start_line_hook()		ia64_start_line ()
+#define tc_unrecognized_line(ch)	ia64_unrecognized_line (ch)
+#define tc_frob_label(s)		ia64_frob_label (s)
+#define md_flush_pending_output()	ia64_flush_pending_output ()
+#define md_parse_name(s,e)		ia64_parse_name (s, e)
+#define tc_canonicalize_symbol_name(s)	ia64_canonicalize_symbol_name (s)
+#define md_optimize_expr(l,o,r)		ia64_optimize_expr (l, o, r)
+#define md_cons_align(n)		ia64_cons_align (n)
+#define TC_FORCE_RELOCATION(f)		ia64_force_relocation (f)
+#define tc_fix_adjustable(f)		ia64_fix_adjustable (f)
+#define md_convert_frag(b,s,f)		as_fatal ("ia64_convert_frag")
+#define md_create_long_jump(p,f,t,fr,s)	as_fatal("ia64_create_long_jump")
+#define md_create_short_jump(p,f,t,fr,s) \
+					as_fatal("ia64_create_short_jump")
+#define md_estimate_size_before_relax(f,s) \
+			(as_fatal ("ia64_estimate_size_before_relax"), 1)
+#define md_elf_section_flags		ia64_elf_section_flags
+#define TC_FIX_TYPE			struct ia64_fix
+#define TC_INIT_FIX_DATA(f)		{ f->tc_fix_data.opnd = 0; }
+#define TC_CONS_FIX_NEW(f,o,l,e)	ia64_cons_fix_new (f, o, l, e)
+#define TC_VALIDATE_FIX(fix,seg,skip)	ia64_validate_fix (fix)
+#define MD_PCREL_FROM_SECTION(fix,sec)	ia64_pcrel_from_section (fix, sec)
+#define md_do_align(n,f,l,m,j)		if (ia64_md_do_align (n,f,l,m)) goto j
+
+/* Call md_apply_fix3 with segment instead of md_apply_fix.  */
+#define MD_APPLY_FIX3
+
+#define WORKING_DOT_WORD	/* don't do broken word processing for now */
+
+#define ELF_TC_SPECIAL_SECTIONS						   \
+{ ".sbss",	SHT_NOBITS,	SHF_ALLOC + SHF_WRITE + SHF_IA_64_SHORT }, \
+{ ".sdata",	SHT_PROGBITS,	SHF_ALLOC + SHF_WRITE + SHF_IA_64_SHORT }, \
+{ ".IA_64.unwind",	SHT_IA_64_UNWIND,	SHF_ALLOC }, \
+{ ".IA_64.unwind_info",	SHT_PROGBITS,		SHF_ALLOC },
+
+#define DWARF2_LINE_MIN_INSN_LENGTH 1	/* so slot-multipliers can be 1 */
+
+/* This is the information required for unwind records in an ia64
+   object file. This is required by GAS and the compiler runtime. */
+
+/* These are the starting point masks for the various types of
+   unwind records. To create a record of type R3 for instance, one
+   starts by using the value UNW_R3 and or-ing in any other required values. 
+   These values are also unique (in context), so they can be used to identify 
+   the various record types as well. UNW_Bx and some UNW_Px do have the
+   same value, but Px can only occur in a prologue context, and Bx in
+   a body context.  */
+
+#define UNW_R1	0x00
+#define UNW_R2	0x40
+#define UNW_R3	0x60
+#define UNW_P1	0x80
+#define UNW_P2	0xA0
+#define UNW_P3	0xB0
+#define UNW_P4	0xB8
+#define UNW_P5	0xB9
+#define UNW_P6	0xC0
+#define UNW_P7	0xE0
+#define UNW_P8	0xF0
+#define UNW_P9	0xF1
+#define UNW_P10	0xFF
+#define UNW_X1	0xF9
+#define UNW_X2	0xFA
+#define UNW_X3	0xFB
+#define UNW_X4	0xFC
+#define UNW_B1	0x80
+#define UNW_B2	0xC0
+#define UNW_B3	0xE0
+#define UNW_B4	0xF0
+
+/* These are all the various types of unwind records.  */
+
+typedef enum
+{
+  prologue, prologue_gr, body, mem_stack_f, mem_stack_v, psp_gr, psp_sprel,
+  rp_when, rp_gr, rp_br, rp_psprel, rp_sprel, pfs_when, pfs_gr, pfs_psprel,
+  pfs_sprel, preds_when, preds_gr, preds_psprel, preds_sprel,
+  fr_mem, frgr_mem, gr_gr, gr_mem, br_mem, br_gr, spill_base, spill_mask,
+  unat_when, unat_gr, unat_psprel, unat_sprel, lc_when, lc_gr, lc_psprel,
+  lc_sprel, fpsr_when, fpsr_gr, fpsr_psprel, fpsr_sprel, 
+  priunat_when_gr, priunat_when_mem, priunat_gr, priunat_psprel, 
+  priunat_sprel, bsp_when, bsp_gr, bsp_psprel, bsp_sprel, bspstore_when,
+  bspstore_gr, bspstore_psprel, bspstore_sprel, rnat_when, rnat_gr,
+  rnat_psprel, rnat_sprel, epilogue, label_state, copy_state,
+  spill_psprel, spill_sprel, spill_reg, spill_psprel_p, spill_sprel_p,
+  spill_reg_p
+} unw_record_type;
+
+
+/* These structures declare the fields that can be used in each of the 
+   4 record formats, R, P, B and X.  */
+
+typedef struct unw_r_record
+{
+  unsigned long rlen;
+  unsigned short mask;
+  unsigned short grsave;
+} unw_r_record;
+
+typedef struct unw_p_record
+{
+  void *imask;
+  unsigned long t;
+  unsigned long size;
+  unsigned long spoff;
+  unsigned long br;
+  unsigned long pspoff;
+  unsigned short gr;
+  unsigned short rmask;
+  unsigned short grmask;
+  unsigned long frmask;
+  unsigned short brmask;
+} unw_p_record;
+
+typedef struct unw_b_record
+{
+  unsigned long t;
+  unsigned long label;
+  unsigned short ecount;
+} unw_b_record;
+
+typedef struct unw_x_record
+{
+  unsigned long t;
+  unsigned long spoff;
+  unsigned long pspoff;
+  unsigned short reg;
+  unsigned short treg;
+  unsigned short qp;
+  unsigned short xy;   /* Value of the XY field..  */
+} unw_x_record;
+
+/* This structure is used to determine the specific record type and 
+   its fields.  */
+typedef struct unwind_record
+{
+  unw_record_type type;
+  union {
+    unw_r_record r;
+    unw_p_record p;
+    unw_b_record b;
+    unw_x_record x;
+  } record;
+} unwind_record;
diff --git a/gas/configure b/gas/configure
index 04e8870..1904b6c 100755
--- a/gas/configure
+++ b/gas/configure
@@ -1659,6 +1659,7 @@ for this_target in $target $canon_targets ; do
       thumb*)		cpu_type=arm endian=little ;;
       hppa*)		cpu_type=hppa ;;
       i[456]86)		cpu_type=i386 ;;
+      ia64)		cpu_type=ia64 ;;
       m680[012346]0)	cpu_type=m68k ;;
       m68008)		cpu_type=m68k ;;
       m683??)		cpu_type=m68k ;;
@@ -1797,6 +1798,9 @@ EOF
       i960-*-vxworks*)      fmt=bout ;;
       i960-*-elf*)	    fmt=elf ;;
 
+      ia64-*-elf*)	    fmt=elf ;;
+      ia64-*-linux-gnu*)    fmt=elf em=linux ;;
+
       m32r-*-*)		    fmt=elf bfd_gas=yes ;;
 
       m68k-*-vxworks* | m68k-ericsson-ose | m68k-*-sunos*)
@@ -1963,6 +1967,7 @@ EOF
       arm-*)	bfd_gas=yes ;;
     # not yet
     # i386-aout)	bfd_gas=preferred ;;
+      ia64*-*)	bfd_gas=yes ;;
       mips-*)	bfd_gas=yes ;;
       ns32k-*)	bfd_gas=yes ;;
       ppc-*)	bfd_gas=yes ;;
diff --git a/gas/configure.in b/gas/configure.in
index 01fd0c5..9802bcd 100644
--- a/gas/configure.in
+++ b/gas/configure.in
@@ -121,6 +121,7 @@ changequote([,])dnl
       hppa*)		cpu_type=hppa ;;
 changequote(,)dnl
       i[456]86)		cpu_type=i386 ;;
+      ia64)		cpu_type=ia64 ;;
       m680[012346]0)	cpu_type=m68k ;;
 changequote([,])dnl
       m68008)		cpu_type=m68k ;;
@@ -258,6 +259,9 @@ changequote([,])dnl
       i960-*-vxworks*)      fmt=bout ;;
       i960-*-elf*)	    fmt=elf ;;
 
+      ia64-*-elf*)	    fmt=elf ;;
+      ia64-*-linux-gnu*)    fmt=elf em=linux ;;
+
       m32r-*-*)		    fmt=elf bfd_gas=yes ;;
 
       m68k-*-vxworks* | m68k-ericsson-ose | m68k-*-sunos*)
@@ -418,6 +422,7 @@ changequote([,])dnl
       arm-*)	bfd_gas=yes ;;
     # not yet
     # i386-aout)	bfd_gas=preferred ;;
+      ia64*-*)	bfd_gas=yes ;;
       mips-*)	bfd_gas=yes ;;
       ns32k-*)	bfd_gas=yes ;;
       ppc-*)	bfd_gas=yes ;;
diff --git a/gas/expr.c b/gas/expr.c
index 7cca437..851a406 100644
--- a/gas/expr.c
+++ b/gas/expr.c
@@ -1744,6 +1744,13 @@ expr (rankarg, resultP)
 	}
 
       /* Optimize common cases.  */
+#ifdef md_optimize_expr
+      if (md_optimize_expr (resultP, op_left, &right))
+	{
+	  /* skip */;
+	}
+      else
+#endif
       if (op_left == O_add && right.X_op == O_constant)
 	{
 	  /* X + constant.  */
diff --git a/gas/read.c b/gas/read.c
index 1522842..2ea5e2b 100644
--- a/gas/read.c
+++ b/gas/read.c
@@ -105,6 +105,8 @@ die horribly;
 #endif
 
 #ifndef LEX_HASH
+/* The IA-64 assembler uses # as a suffix designating a symbol.  We include
+   it in the symbol and strip it out in tc_canonicalize_symbol_name.  */
 #define LEX_HASH 0
 #endif
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 5337849..ee01f3b 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
+			  David Mosberger  <davidm@hpl.hp.com>
+			  Timothy Wall <twall@cygnus.com>
+			  Jim Wilson  <wilson@cygnus.com>
+
+	* gas/vtable/vtable.exp: Disable for ia64.
+	* gas/testsuite/gas/ia64: New testsuite directory.
+	
 2000-04-03  Alan Modra  <alan@linuxcare.com.au>
 
 	* gas/i386/general.s: Check 16-bit immediates, and move call/jump
diff --git a/gas/testsuite/gas/ia64/dv-branch.d b/gas/testsuite/gas/ia64/dv-branch.d
new file mode 100644
index 0000000..f334d8d
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-branch.d
@@ -0,0 +1,15 @@
+# as: -xexplicit
+# objdump: -d
+# name ia64 dv-branch
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <\.text>:
+   0:	d0 08 00 10 18 90 	\[MIB\] \(p06\) ld8 r1=\[r8\]
+   6:	61 10 04 80 03 03 	      \(p06\) mov b6=r2
+   c:	68 00 00 10       	      \(p06\) br\.call\.sptk\.many b0=b6
+  10:	11 08 00 3c 00 21 	\[MIB\]       mov r1=r30
+  16:	00 00 00 02 00 03 	            nop\.i 0x0
+  1c:	f0 ff ff 48       	      \(p06\) br\.cond\.sptk\.few 0x0;;
diff --git a/gas/testsuite/gas/ia64/dv-branch.s b/gas/testsuite/gas/ia64/dv-branch.s
new file mode 100644
index 0000000..09c5141
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-branch.s
@@ -0,0 +1,16 @@
+//
+// Verify DV detection on branch variations
+//			
+.text
+	.explicit
+	// example from rth
+3:		
+	{ .mib
+(p6)	  ld8 gp = [ret0]
+(p6)	  mov b6 = r2
+(p6)	  br.call.sptk.many b0 = b6 // if taken, clears b6/r2 usage
+	}
+	{ .mib
+	  mov gp = r30
+(p6)	  br.sptk.few 3b
+	}  
diff --git a/gas/testsuite/gas/ia64/dv-entry-err.l b/gas/testsuite/gas/ia64/dv-entry-err.l
new file mode 100644
index 0000000..f7b1f72
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-entry-err.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:14: Warning: Use of 'mov' .* WAW dependency 'GR%, % in 1 - 127' \(impliedf\) when entry is at label 'L', specific resource number is 5
+.*:13: Warning: This is the location of the conflicting usage
diff --git a/gas/testsuite/gas/ia64/dv-entry-err.s b/gas/testsuite/gas/ia64/dv-entry-err.s
new file mode 100644
index 0000000..7eee7ae
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-entry-err.s
@@ -0,0 +1,15 @@
+//
+// Verify DV detection on multiple paths
+//			
+.text
+	.explicit
+// RAW on r4 is avoided on both paths
+// RAW on r5 is avoided on path 0 (from top) but not path 1 (from L)
+	cmp.eq	p1, p2 = r1, r2
+	cmp.eq	p3, p4 = r3, r0
+(p1)	mov	r4 = 2
+L:	
+(p2)	mov	r4 = 5
+(p3)	mov	r5 = r7
+(p4)	mov	r5 = r8
+
diff --git a/gas/testsuite/gas/ia64/dv-imply.d b/gas/testsuite/gas/ia64/dv-imply.d
new file mode 100644
index 0000000..45ad833
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-imply.d
@@ -0,0 +1,42 @@
+# as: -xexplicit
+# objdump: -d
+# name ia64 dv-mutex
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <L-0xb0>:
+   0:	30 20 08 00 00 21 	\[MIB\] \(p01\) mov r4=2
+   6:	00 00 00 02 00 01 	            nop\.i 0x0
+   c:	b0 00 00 40       	      \(p02\) br\.cond\.sptk\.few b0 <L>
+  10:	11 20 1c 00 00 21 	\[MIB\]       mov r4=7
+  16:	00 00 00 02 00 00 	            nop\.i 0x0
+  1c:	00 00 20 00       	            rfi;;
+  20:	10 20 08 00 00 21 	\[MIB\]       mov r4=2
+  26:	00 00 00 02 00 01 	            nop\.i 0x0
+  2c:	90 00 00 40       	      \(p02\) br\.cond\.sptk\.few b0 <L>
+  30:	31 20 1c 00 00 21 	\[MIB\] \(p01\) mov r4=7
+  36:	00 00 00 02 00 00 	            nop\.i 0x0
+  3c:	00 00 20 00       	            rfi;;
+  40:	70 08 06 04 02 78 	\[MIB\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2
+  46:	40 10 00 00 c2 01 	      \(p01\) mov r4=2
+  4c:	70 00 00 40       	      \(p03\) br\.cond\.sptk\.few b0 <L>
+  50:	11 20 1c 00 00 21 	\[MIB\]       mov r4=7
+  56:	00 00 00 02 00 00 	            nop\.i 0x0
+  5c:	00 00 20 00       	            rfi;;
+  60:	60 08 06 04 02 38 	\[MII\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2
+  66:	30 28 18 88 e8 80 	            cmp\.eq\.or p3,p4=r5,r6
+  6c:	20 00 00 84       	      \(p01\) mov r4=2
+  70:	10 00 00 00 01 00 	\[MIB\]       nop\.m 0x0
+  76:	00 00 00 02 80 01 	            nop\.i 0x0
+  7c:	40 00 00 40       	      \(p03\) br\.cond\.sptk\.few b0 <L>
+  80:	11 20 1c 00 00 21 	\[MIB\]       mov r4=7
+  86:	00 00 00 02 00 00 	            nop\.i 0x0
+  8c:	00 00 20 00       	            rfi;;
+  90:	10 08 16 0c 42 70 	\[MIB\]       cmp\.ne\.and p1,p2=r5,r6
+  96:	40 10 00 00 c2 01 	      \(p01\) mov r4=2
+  9c:	20 00 00 40       	      \(p03\) br\.cond\.sptk\.few b0 <L>
+  a0:	11 20 1c 00 00 21 	\[MIB\]       mov r4=7
+  a6:	00 00 00 02 00 00 	            nop\.i 0x0
+  ac:	00 00 20 00       	            rfi;;
diff --git a/gas/testsuite/gas/ia64/dv-imply.s b/gas/testsuite/gas/ia64/dv-imply.s
new file mode 100644
index 0000000..b12bf7e
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-imply.s
@@ -0,0 +1,44 @@
+//	
+// Test various implies relations	
+//	
+.text
+// User-supplied hint	
+	.pred.rel.imply p1, p2
+(p1)	mov		r4 = 2
+(p2)	br.cond.sptk		L
+	mov		r4 = 7
+	rfi	
+	
+// Symmetric to previous example
+	.pred.rel.imply p1, p2
+	mov		r4 = 2
+(p2)	br.cond.sptk	L
+(p1)	mov		r4 = 7	
+	rfi
+
+// Verify that the implies relationship caused by the unconditional compare 
+// prevents RAW on r4.  
+(p3)	cmp.eq.unc	p1, p2 = r1, r2		// p1,p2 imply p3
+(p1)	mov		r4 = 2
+(p3)	br.cond.sptk	L	
+	mov		r4 = 7
+	rfi
+	
+// An instance of cmp.rel.or should not affect an implies relation.
+(p3)	cmp.eq.unc	p1, p2 = r1, r2		// p1,p2 imply p3
+	cmp.eq.or	p3, p4 = r5, r6		// doesn't affect implies rel
+(p1)	mov		r4 = 2
+(p3)	br.cond.sptk	L	
+	mov		r4 = 7
+	rfi
+	
+// An instance of cmp.rel.and only affects imply targets
+	.pred.rel.imply p1,p3
+	cmp.ne.and	p1, p2 = r5, r6		// doesn't affect imply source
+(p1)	mov		r4 = 2
+(p3)	br.cond.sptk	L	
+	mov		r4 = 7
+	rfi
+	
+// FIXME -- add tests for and.orcm and or.andcm	
+L:	
diff --git a/gas/testsuite/gas/ia64/dv-mutex-err.l b/gas/testsuite/gas/ia64/dv-mutex-err.l
new file mode 100644
index 0000000..a6df710
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-mutex-err.l
@@ -0,0 +1,4 @@
+.*: Assembler messages:
+.*:9: Warning: Use of 'ld8' .* RAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 26
+.*:9: Warning: Only the first path encountering the conflict is reported
+.*:8: Warning: This is the location of the conflicting usage
diff --git a/gas/testsuite/gas/ia64/dv-mutex-err.s b/gas/testsuite/gas/ia64/dv-mutex-err.s
new file mode 100644
index 0000000..e6eaaaa
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-mutex-err.s
@@ -0,0 +1,9 @@
+//	
+// Test mutex relation handling	
+//	
+.text
+	.explicit
+start:	
+	cmp.eq	p6, p0 = r29, r0
+	add	r26 = r26, r29
+	ld8	r29 = [r26]
diff --git a/gas/testsuite/gas/ia64/dv-mutex.d b/gas/testsuite/gas/ia64/dv-mutex.d
new file mode 100644
index 0000000..af84da6
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-mutex.d
@@ -0,0 +1,27 @@
+# as: -xexplicit
+# objdump: -d
+# name ia64 dv-mutex
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <start>:
+   0:	20 20 08 00 00 a1 	\[MII\] \(p01\) mov r4=2
+   6:	40 28 00 00 c2 81 	      \(p02\) mov r4=5
+   c:	70 00 00 84       	      \(p03\) mov r4=7
+  10:	11 00 00 00 01 00 	\[MIB\]       nop\.m 0x0
+  16:	00 00 00 02 00 00 	            nop\.i 0x0
+  1c:	00 00 20 00       	            rfi;;
+  20:	00 08 04 04 02 78 	\[MII\]       cmp\.eq p1,p2=r1,r2
+  26:	40 10 00 00 42 81 	      \(p01\) mov r4=2
+  2c:	40 00 00 84       	      \(p02\) mov r4=4
+  30:	11 00 00 00 01 00 	\[MIB\]       nop\.m 0x0
+  36:	00 00 00 02 00 00 	            nop\.i 0x0
+  3c:	00 00 20 00       	            rfi;;
+  40:	60 08 06 04 02 78 	\[MII\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2
+  46:	40 10 00 00 42 81 	      \(p01\) mov r4=2
+  4c:	40 00 00 84       	      \(p02\) mov r4=4
+  50:	11 00 00 00 01 00 	\[MIB\]       nop\.m 0x0
+  56:	00 00 00 02 00 00 	            nop\.i 0x0
+  5c:	00 00 20 00       	            rfi;;
diff --git a/gas/testsuite/gas/ia64/dv-mutex.s b/gas/testsuite/gas/ia64/dv-mutex.s
new file mode 100644
index 0000000..c62ae10
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-mutex.s
@@ -0,0 +1,24 @@
+//	
+// Test mutex relation handling	
+//	
+.text
+start:	
+// user annotation	
+	.pred.rel.mutex p1, p2, p3
+(p1)	mov r4 = 2
+(p2)	mov r4 = 5
+(p3)	mov r4 = 7
+	rfi
+
+// non-predicated compares generate a mutex
+	cmp.eq	p1, p2 = r1, r2
+(p1)	mov r4 = 2
+(p2)	mov r4 = 4
+	rfi
+
+// unconditional compares generate a mutex
+(p3)	cmp.eq.unc p1, p2 = r1, r2
+(p1)	mov r4 = 2
+(p2)	mov r4 = 4
+	rfi
+L:	
diff --git a/gas/testsuite/gas/ia64/dv-raw-err.l b/gas/testsuite/gas/ia64/dv-raw-err.l
new file mode 100644
index 0000000..9993418
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-raw-err.l
@@ -0,0 +1,267 @@
+.*: Assembler messages:
+.*:10: Warning: Use of 'mov\.m' .* RAW dependency 'AR\[BSP\]' \(impliedf\)
+.*:9: Warning: This is the location of the conflicting usage
+.*:10: Warning: Use of 'mov\.m' .* RAW dependency 'RSE' \(impliedf\)
+.*:9: Warning: This is the location of the conflicting usage
+.*:15: Warning: Use of 'mov\.m' .* RAW dependency 'AR\[BSPSTORE\]' \(impliedf\)
+.*:14: Warning: This is the location of the conflicting usage
+.*:15: Warning: Use of 'mov\.m' .* RAW dependency 'RSE' \(impliedf\)
+.*:14: Warning: This is the location of the conflicting usage
+.*:20: Warning: Use of 'cmpxchg8\.acq' .* RAW dependency 'AR\[CCV\]' \(impliedf\)
+.*:19: Warning: This is the location of the conflicting usage
+.*:25: Warning: Use of 'mov\.i' .* RAW dependency 'AR\[EC\]' \(impliedf\)
+.*:24: Warning: This is the location of the conflicting usage
+.*:30: Warning: Use of 'fpcmp\.eq\.s0' .* RAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\)
+.*:29: Warning: This is the location of the conflicting usage
+.*:35: Warning: Use of 'fpcmp\.eq\.s1' .* RAW dependency 'AR\[FPSR\]\.sf1\.controls' \(impliedf\)
+.*:34: Warning: This is the location of the conflicting usage
+.*:40: Warning: Use of 'fpcmp\.eq\.s2' .* RAW dependency 'AR\[FPSR\]\.sf2\.controls' \(impliedf\)
+.*:39: Warning: This is the location of the conflicting usage
+.*:45: Warning: Use of 'fpcmp\.eq\.s3' .* RAW dependency 'AR\[FPSR\]\.sf3\.controls' \(impliedf\)
+.*:44: Warning: This is the location of the conflicting usage
+.*:50: Warning: Use of 'fchkf\.s0' .* RAW dependency 'AR\[FPSR\]\.sf0\.flags' \(impliedf\)
+.*:49: Warning: This is the location of the conflicting usage
+.*:55: Warning: Use of 'fchkf\.s1' .* RAW dependency 'AR\[FPSR\]\.sf1\.flags' \(impliedf\)
+.*:54: Warning: This is the location of the conflicting usage
+.*:60: Warning: Use of 'fchkf\.s2' .* RAW dependency 'AR\[FPSR\]\.sf2\.flags' \(impliedf\)
+.*:59: Warning: This is the location of the conflicting usage
+.*:65: Warning: Use of 'fchkf\.s3' .* RAW dependency 'AR\[FPSR\]\.sf3\.flags' \(impliedf\)
+.*:64: Warning: This is the location of the conflicting usage
+.*:70: Warning: Use of 'fcmp\.eq\.s3' .* RAW dependency 'AR\[FPSR\]\.sf3\.controls' \(impliedf\)
+.*:69: Warning: This is the location of the conflicting usage
+.*:70: Warning: Use of 'fcmp\.eq\.s3' .* RAW dependency 'AR\[FPSR\]\.traps' \(impliedf\)
+.*:69: Warning: This is the location of the conflicting usage
+.*:70: Warning: Use of 'fcmp\.eq\.s3' .* RAW dependency 'AR\[FPSR\]\.rv' \(impliedf\)
+.*:69: Warning: This is the location of the conflicting usage
+.*:70: Warning: Use of 'fcmp\.eq\.s3' .* WAW dependency 'AR\[FPSR\]\.sf3\.flags' \(impliedf\)
+.*:69: Warning: This is the location of the conflicting usage
+.*:75: Warning: Use of 'mov\.m' .* RAW dependency 'AR\[ITC\]' \(impliedf\)
+.*:74: Warning: This is the location of the conflicting usage
+.*:80: Warning: Use of 'br\.ia\.sptk' .* RAW dependency 'AR\[K%\], % in 0 - 7' \(impliedf\), specific resource number is 1
+.*:79: Warning: This is the location of the conflicting usage
+.*:85: Warning: Use of 'mov\.i' .* RAW dependency 'AR\[LC\]' \(impliedf\)
+.*:84: Warning: This is the location of the conflicting usage
+.*:90: Warning: Use of 'epc' .* RAW dependency 'AR\[PFS\]' \(impliedf\)
+.*:89: Warning: This is the location of the conflicting usage
+.*:94: Warning: Use of 'mov\.m' .* RAW dependency 'AR\[RNAT\]' \(impliedf\)
+.*:93: Warning: This is the location of the conflicting usage
+.*:94: Warning: Use of 'mov\.m' .* RAW dependency 'RSE' \(impliedf\)
+.*:93: Warning: This is the location of the conflicting usage
+.*:99: Warning: Use of 'mov\.m' .* RAW dependency 'AR\[RSC\]' \(impliedf\)
+.*:98: Warning: This is the location of the conflicting usage
+.*:104: Warning: Use of 'ld8\.fill' .* RAW dependency 'AR\[UNAT\]{%}, % in 0 - 63' \(impliedf\)
+.*:103: Warning: This is the location of the conflicting usage
+.*:111: Warning: Use of 'mov' .* RAW dependency 'BR%, % in 0 - 7' \(impliedf\)
+.*:110: Warning: This is the location of the conflicting usage
+.*:116: Warning: Use of 'fadd' .* RAW dependency 'CFM' \(impliedf\)
+.*:115: Warning: This is the location of the conflicting usage
+.*:121: Warning: Use of 'mov' .* RAW dependency 'CR\[CMCV\]' \(data\)
+.*:120: Warning: This is the location of the conflicting usage
+.*:126: Warning: Use of 'ld8\.s' .* RAW dependency 'CR\[DCR\]' \(data\)
+.*:125: Warning: This is the location of the conflicting usage
+.*:133: Warning: Use of 'thash' .* RAW dependency 'CR\[GPTA\]' \(data\)
+.*:132: Warning: This is the location of the conflicting usage
+.*:139: Warning: Use of 'itc\.i' .* RAW dependency 'CR\[IFA\]' \(implied\)
+.*:138: Warning: This is the location of the conflicting usage
+.*:144: Warning: Use of 'mov' .* RAW dependency 'CR\[IFS\]' \(data\)
+.*:143: Warning: This is the location of the conflicting usage
+.*:149: Warning: Use of 'mov' .* RAW dependency 'CR\[IHA\]' \(data\)
+.*:148: Warning: This is the location of the conflicting usage
+.*:154: Warning: Use of 'mov' .* RAW dependency 'CR\[IIM\]' \(data\)
+.*:153: Warning: This is the location of the conflicting usage
+.*:159: Warning: Use of 'rfi' .* RAW dependency 'CR\[IIP\]' \(implied\)
+.*:158: Warning: This is the location of the conflicting usage
+.*:164: Warning: Use of 'mov' .* RAW dependency 'CR\[IIPA\]' \(data\)
+.*:163: Warning: This is the location of the conflicting usage
+.*:169: Warning: Use of 'rfi' .* RAW dependency 'CR\[IPSR\]' \(implied\)
+.*:168: Warning: This is the location of the conflicting usage
+.*:174: Warning: Use of 'mov' .* RAW dependency 'CR\[IRR%\], % in 0 - 3' \(data\), specific resource number is 68
+.*:173: Warning: This is the location of the conflicting usage
+.*:179: Warning: Use of 'mov' .* RAW dependency 'CR\[ISR\]' \(data\)
+.*:178: Warning: This is the location of the conflicting usage
+.*:184: Warning: Use of 'itc\.d' .* RAW dependency 'CR\[ITIR\]' \(implied\)
+.*:183: Warning: This is the location of the conflicting usage
+.*:189: Warning: Use of 'mov' .* RAW dependency 'CR\[ITM\]' \(data\)
+.*:188: Warning: This is the location of the conflicting usage
+.*:194: Warning: Use of 'mov' .* RAW dependency 'CR\[ITV\]' \(data\)
+.*:193: Warning: This is the location of the conflicting usage
+.*:201: Warning: Use of 'mov' .* RAW dependency 'CR\[IVA\]' \(instr\)
+.*:200: Warning: This is the location of the conflicting usage
+.*:206: Warning: Use of 'mov' .* RAW dependency 'CR\[LID\]' \(other\)
+.*:205: Warning: This is the location of the conflicting usage
+.*:212: Warning: Use of 'mov' .* RAW dependency 'CR\[LRR%\], % in 0 - 1' \(data\), specific resource number is 80
+.*:211: Warning: This is the location of the conflicting usage
+.*:217: Warning: Use of 'mov' .* RAW dependency 'CR\[PMV\]' \(data\)
+.*:216: Warning: This is the location of the conflicting usage
+.*:222: Warning: Use of 'thash' .* RAW dependency 'CR\[PTA\]' \(data\)
+.*:221: Warning: This is the location of the conflicting usage
+.*:227: Warning: Use of 'mov' .* RAW dependency 'CR\[TPR\]' \(data\)
+.*:226: Warning: This is the location of the conflicting usage
+.*:231: Warning: Use of 'mov' .* RAW dependency 'CR\[TPR\]' \(other\)
+.*:230: Warning: This is the location of the conflicting usage
+.*:237: Warning: Use of 'mov' .* RAW dependency 'DBR#' \(impliedf\)
+.*:236: Warning: This is the location of the conflicting usage
+.*:241: Warning: Use of 'probe\.r' .* RAW dependency 'DBR#' \(data\)
+.*:240: Warning: This is the location of the conflicting usage
+.*:247: Warning: Use of 'fc' .* RAW dependency 'DTC' \(data\)
+.*:246: Warning: This is the location of the conflicting usage
+.*:251: Warning: Use of 'ptc\.e' .* RAW dependency 'DTC' \(impliedf\)
+.*:250: Warning: This is the location of the conflicting usage
+.*:251: Warning: Use of 'ptc\.e' .* WAW dependency 'DTC' \(impliedf\)
+.*:250: Warning: This is the location of the conflicting usage
+.*:251: Warning: Use of 'ptc\.e' .* WAW dependency 'ITC' \(impliedf\)
+.*:250: Warning: This is the location of the conflicting usage
+.*:262: Warning: Use of 'tak' .* RAW dependency 'DTC' \(data\)
+.*:261: Warning: This is the location of the conflicting usage
+.*:262: Warning: Use of 'tak' .* RAW dependency 'DTR' \(data\)
+.*:261: Warning: This is the location of the conflicting usage
+.*:266: Warning: Use of 'tpa' .* RAW dependency 'DTC' \(data\)
+.*:265: Warning: This is the location of the conflicting usage
+.*:266: Warning: Use of 'tpa' .* RAW dependency 'DTR' \(data\)
+.*:265: Warning: This is the location of the conflicting usage
+.*:275: Warning: Use of 'mov' .* RAW dependency 'FR%, % in 2 - 127' \(impliedf\), specific resource number is 4
+.*:274: Warning: This is the location of the conflicting usage
+.*:283: Warning: Use of 'mov' .* RAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 3
+.*:282: Warning: This is the location of the conflicting usage
+.*:288: Warning: Use of 'mov' .* RAW dependency 'IBR#' \(impliedf\)
+.*:287: Warning: This is the location of the conflicting usage
+.*:293: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(data\)
+.*:292: Warning: This is the location of the conflicting usage
+.*:293: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
+.*:292: Warning: This is the location of the conflicting usage
+.*:297: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(impliedf\)
+.*:296: Warning: This is the location of the conflicting usage
+.*:297: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 71
+.*:296: Warning: This is the location of the conflicting usage
+.*:297: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 70
+.*:296: Warning: This is the location of the conflicting usage
+.*:297: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 69
+.*:296: Warning: This is the location of the conflicting usage
+.*:297: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 68
+.*:296: Warning: This is the location of the conflicting usage
+.*:297: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
+.*:296: Warning: This is the location of the conflicting usage
+.*:299: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
+.*:297: Warning: This is the location of the conflicting usage
+.*:299: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
+.*:296: Warning: This is the location of the conflicting usage
+.*:300: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
+.*:297: Warning: This is the location of the conflicting usage
+.*:300: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
+.*:296: Warning: This is the location of the conflicting usage
+.*:300: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(impliedf\)
+.*:299: Warning: This is the location of the conflicting usage
+.*:300: Warning: Use of 'mov' .* WAW dependency 'CR\[EOI\]' \(other\)
+.*:299: Warning: This is the location of the conflicting usage
+.*:300: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
+.*:299: Warning: This is the location of the conflicting usage
+.*:305: Warning: Use of 'epc' .* RAW dependency 'ITC' \(instr\)
+.*:304: Warning: This is the location of the conflicting usage
+.*:314: Warning: Use of 'epc' .* RAW dependency 'ITC' \(instr\)
+.*:313: Warning: This is the location of the conflicting usage
+.*:314: Warning: Use of 'epc' .* RAW dependency 'ITR' \(instr\)
+.*:313: Warning: This is the location of the conflicting usage
+.*:321: Warning: Use of 'probe\.r' .* RAW dependency 'PKR#' \(data\)
+.*:320: Warning: This is the location of the conflicting usage
+.*:325: Warning: Use of 'mov' .* RAW dependency 'PKR#' \(data\)
+.*:324: Warning: This is the location of the conflicting usage
+.*:325: Warning: Use of 'mov' .* RAW dependency 'PKR#' \(impliedf\)
+.*:324: Warning: This is the location of the conflicting usage
+.*:331: Warning: Use of 'mov' .* RAW dependency 'PMC#' \(impliedf\)
+.*:330: Warning: This is the location of the conflicting usage
+.*:335: Warning: Use of 'mov' .* RAW dependency 'PMC#' \(other\)
+.*:334: Warning: This is the location of the conflicting usage
+.*:341: Warning: Use of 'mov' .* RAW dependency 'PMD#' \(impliedf\)
+.*:340: Warning: This is the location of the conflicting usage
+.*:346: Warning: Use of 'add' .* RAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1
+.*:345: Warning: This is the location of the conflicting usage
+.*:349: Warning: Use of 'add' .* RAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 2
+.*:348: Warning: This is the location of the conflicting usage
+.*:352: Warning: Use of 'br\.cond\.sptk' .* RAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 5
+.*:351: Warning: This is the location of the conflicting usage
+.*:360: Warning: Use of 'add' .* RAW dependency 'CFM' \(impliedf\)
+.*:359: Warning: This is the location of the conflicting usage
+.*:360: Warning: Use of 'add' .* RAW dependency 'PR63' \(impliedf\)
+.*:359: Warning: This is the location of the conflicting usage
+.*:363: Warning: Use of 'add' .* RAW dependency 'PR63' \(impliedf\)
+.*:362: Warning: This is the location of the conflicting usage
+.*:371: Warning: Use of 'ld8' .* RAW dependency 'PSR\.ac' \(implied\)
+.*:370: Warning: This is the location of the conflicting usage
+.*:376: Warning: Use of 'ld8' .* RAW dependency 'PSR\.be' \(implied\)
+.*:375: Warning: This is the location of the conflicting usage
+.*:389: Warning: Use of 'st8' .* RAW dependency 'PSR\.cpl' \(implied\)
+.*:388: Warning: This is the location of the conflicting usage
+.*:392: Warning: Use of 'mov\.m' .* RAW dependency 'PSR\.cpl' \(implied\)
+.*:391: Warning: This is the location of the conflicting usage
+.*:395: Warning: Use of 'mov\.m' .* RAW dependency 'PSR\.cpl' \(implied\)
+.*:394: Warning: This is the location of the conflicting usage
+.*:398: Warning: Use of 'mov\.m' .* RAW dependency 'PSR\.cpl' \(implied\)
+.*:397: Warning: This is the location of the conflicting usage
+.*:401: Warning: Use of 'mov\.m' .* RAW dependency 'PSR\.cpl' \(implied\)
+.*:400: Warning: This is the location of the conflicting usage
+.*:404: Warning: Use of 'mov' .* RAW dependency 'PSR\.cpl' \(implied\)
+.*:403: Warning: This is the location of the conflicting usage
+.*:413: Warning: Use of 'mov' .* RAW dependency 'PSR\.cpl' \(implied\)
+.*:412: Warning: This is the location of the conflicting usage
+.*:416: Warning: Use of 'mov' .* RAW dependency 'PSR\.cpl' \(implied\)
+.*:415: Warning: This is the location of the conflicting usage
+.*:422: Warning: Use of 'ld8' .* RAW dependency 'PSR\.ac' \(data\)
+.*:421: Warning: This is the location of the conflicting usage
+.*:422: Warning: Use of 'ld8' .* RAW dependency 'PSR\.be' \(data\)
+.*:421: Warning: This is the location of the conflicting usage
+.*:422: Warning: Use of 'ld8' .* RAW dependency 'PSR\.db' \(data\)
+.*:421: Warning: This is the location of the conflicting usage
+.*:422: Warning: Use of 'ld8' .* RAW dependency 'PSR\.dt' \(data\)
+.*:421: Warning: This is the location of the conflicting usage
+.*:422: Warning: Use of 'ld8' .* RAW dependency 'PSR\.pk' \(data\)
+.*:421: Warning: This is the location of the conflicting usage
+.*:430: Warning: Use of 'mov' .* RAW dependency 'PSR\.dfh' \(data\)
+.*:429: Warning: This is the location of the conflicting usage
+.*:430: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfh' \(impliedf\)
+.*:429: Warning: This is the location of the conflicting usage
+.*:436: Warning: Use of 'mov' .* RAW dependency 'PSR\.dfl' \(data\)
+.*:435: Warning: This is the location of the conflicting usage
+.*:436: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfl' \(impliedf\)
+.*:435: Warning: This is the location of the conflicting usage
+.*:442: Warning: Use of 'mov' .* RAW dependency 'PSR\.di' \(impliedf\)
+.*:441: Warning: This is the location of the conflicting usage
+.*:447: Warning: Use of 'ld8' .* RAW dependency 'PSR\.dt' \(data\)
+.*:446: Warning: This is the location of the conflicting usage
+.*:453: Warning: Use of 'mov' .* RAW dependency 'PSR\.i' \(impliedf\)
+.*:452: Warning: This is the location of the conflicting usage
+.*:459: Warning: Use of 'mov' .* RAW dependency 'PSR\.ic' \(impliedf\)
+.*:458: Warning: This is the location of the conflicting usage
+.*:463: Warning: Use of 'mov' .* RAW dependency 'PSR\.ic' \(data\)
+.*:462: Warning: This is the location of the conflicting usage
+.*:476: Warning: Use of 'br\.ret\.sptk' .* RAW dependency 'PSR\.lp' \(data\)
+.*:475: Warning: This is the location of the conflicting usage
+.*:476: Warning: Use of 'br\.ret\.sptk' .* RAW dependency 'PSR\.tb' \(data\)
+.*:475: Warning: This is the location of the conflicting usage
+.*:482: Warning: Use of 'mov' .* RAW dependency 'PSR\.mfh' \(impliedf\)
+.*:481: Warning: This is the location of the conflicting usage
+.*:487: Warning: Use of 'mov' .* RAW dependency 'PSR\.mfl' \(impliedf\)
+.*:486: Warning: This is the location of the conflicting usage
+.*:492: Warning: Use of 'ld8' .* RAW dependency 'PSR\.pk' \(data\)
+.*:491: Warning: This is the location of the conflicting usage
+.*:495: Warning: Use of 'mov' .* RAW dependency 'PSR\.pk' \(impliedf\)
+.*:494: Warning: This is the location of the conflicting usage
+.*:500: Warning: Use of 'mov' .* RAW dependency 'PSR\.pp' \(impliedf\)
+.*:499: Warning: This is the location of the conflicting usage
+.*:506: Warning: Use of 'flushrs' .* RAW dependency 'PSR\.rt' \(data\)
+.*:505: Warning: This is the location of the conflicting usage
+.*:512: Warning: Use of 'mov\.m' .* RAW dependency 'PSR\.si' \(data\)
+.*:511: Warning: This is the location of the conflicting usage
+.*:520: Warning: Use of 'mov' .* RAW dependency 'PSR\.sp' \(data\)
+.*:519: Warning: This is the location of the conflicting usage
+.*:523: Warning: Use of 'rum' .* RAW dependency 'PSR\.sp' \(data\)
+.*:519: Warning: This is the location of the conflicting usage
+.*:523: Warning: Use of 'rum' .* RAW dependency 'PSR\.sp' \(data\)
+.*:522: Warning: This is the location of the conflicting usage
+.*:532: Warning: Use of 'chk\.s' .* RAW dependency 'PSR\.tb' \(data\)
+.*:531: Warning: This is the location of the conflicting usage
+.*:537: Warning: Use of 'mov' .* RAW dependency 'PSR\.up' \(impliedf\)
+.*:536: Warning: This is the location of the conflicting usage
+.*:543: Warning: Use of 'ld8' .* RAW dependency 'RR#' \(data\)
+.*:542: Warning: This is the location of the conflicting usage
+.*:546: Warning: Use of 'mov' .* RAW dependency 'RR#' \(impliedf\)
+.*:545: Warning: This is the location of the conflicting usage
diff --git a/gas/testsuite/gas/ia64/dv-raw-err.s b/gas/testsuite/gas/ia64/dv-raw-err.s
new file mode 100644
index 0000000..fde8a69
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-raw-err.s
@@ -0,0 +1,549 @@
+//	
+// Detect RAW violations.  Cases taken from DV tables.
+// This test is by no means complete but tries to hit the things that are 
+// likely to be missed.
+//	
+.text
+	.explicit
+// AR[BSP]
+	mov	ar.bspstore = r1
+	mov	r0 = ar.bsp
+	;;
+
+// AR[BSPSTORE]	
+	mov	ar.bspstore = r2
+	mov	r3 = ar.bspstore
+	;;
+	
+// AR[CCV]
+	mov	ar.ccv = r4
+	cmpxchg8.acq r5 = [r6],r7,ar.ccv
+	;;
+	
+// AR[EC]	
+	br.wtop.sptk	L
+	mov	r8 = ar.ec
+	;;
+
+// AR[FPSR].sf0.controls 
+	fsetc.s0	0x7f, 0x0f
+	fpcmp.eq.s0	f2 = f3, f4
+	;;
+
+// AR[FPSR].sf1.controls
+	fsetc.s1	0x7f, 0x0f
+	fpcmp.eq.s1	f2 = f3, f4
+	;;
+
+// AR[FPSR].sf2.controls
+	fsetc.s2	0x7f, 0x0f
+	fpcmp.eq.s2	f2 = f3, f4
+	;;
+
+// AR[FPSR].sf3.controls
+	fsetc.s3	0x7f, 0x0f
+	fpcmp.eq.s3	f2 = f3, f4
+	;;
+
+// AR[FPSR].sf0.flags
+	fpcmp.eq.s0	f2 = f3, f4
+	fchkf.s0	L
+	;;
+
+// AR[FPSR].sf1.flags
+	fpcmp.eq.s1	f2 = f3, f4
+	fchkf.s1	L
+	;;
+
+// AR[FPSR].sf2.flags
+	fpcmp.eq.s2	f2 = f3, f4
+	fchkf.s2	L
+	;;
+
+// AR[FPSR].sf3.flags
+	fpcmp.eq.s3	f2 = f3, f4
+	fchkf.s3	L
+	;;
+
+// AR[FPSR].traps/rv
+	mov	ar.fpsr = r0
+	fcmp.eq.s3	p1, p2 = f5, f6
+	;;
+
+// AR[ITC]
+	mov	ar.itc = r1
+	mov	r2 = ar.itc
+	;;
+
+// AR[K]
+	mov	ar.k1 = r3
+	br.ia.sptk	b0
+	;;
+	
+// AR[LC]
+	br.cloop.sptk	L
+	mov	r4 = ar.lc
+	;;
+	
+// AR[PFS]
+	mov	ar.pfs = r5
+	epc
+
+// AR[RNAT]	
+	mov	ar.bspstore = r8
+	mov	r9 = ar.rnat	
+	;;
+	
+// AR[RSC]
+	mov	ar.rsc = r10
+	mov	r11 = ar.rnat
+	;;	
+	
+// AR[UNAT]	
+	mov	ar.unat = r12
+	ld8.fill r13 = [r14]
+	;;
+	
+// AR%
+
+// BR%
+	mov	b0 = r0
+	mov	r0 = b0
+	;;
+	
+// CFM	
+	br.wtop.sptk	L
+	fadd	f0 = f1, f32	// read from rotating register region
+	;;
+	
+// CR[CMCV]
+	mov	cr.cmcv = r1
+	mov	r2 = cr.cmcv	
+	;;
+
+// CR[DCR]
+	mov	cr.dcr = r3
+	ld8.s	r4 = [r5]
+	;;
+
+// CR[EOI]
+	
+// CR[GPTA]
+	mov	cr.gpta = r6
+	thash	r7 = r8
+	;;
+	srlz.d
+
+// CR[IFA]
+	mov	cr.ifa = r9
+	itc.i	r10
+	;;
+
+// CR[IFS]
+	mov	cr.ifs = r11
+	mov	r12 = cr.ifs
+	;;
+
+// CR[IHA]
+	mov	cr.iha = r13
+	mov	r14 = cr.iha
+	;;
+
+// CR[IIM]
+	mov	cr.iim = r15
+	mov	r16 = cr.iim
+	;;
+
+// CR[IIP] 
+	mov	cr.iip = r17
+	rfi
+	;;
+
+// CR[IIPA]
+	mov	cr.iipa = r19
+	mov	r20 = cr.iipa
+	;;
+
+// CR[IPSR]
+	mov	cr.ipsr = r21
+	rfi
+	;;
+
+// CR[IRR%]
+	mov	r22 = cr.ivr
+	mov	r23 = cr.irr0
+	;;
+	
+// CR[ISR]
+	mov	cr.isr = r24
+	mov	r25 = cr.isr
+	;;	
+	
+// CR[ITIR]
+	mov	cr.itir = r26
+	itc.d	r27
+	;;	
+	
+// CR[ITM]
+	mov	cr.itm = r28
+	mov	r29 = cr.itm
+	;;	
+	
+// CR[ITV]
+	mov	cr.itv = r0
+	mov	r1 = cr.itv
+	;;	
+	
+// CR[IVR] (all writes are implicit in other resource usage)
+	
+// CR[IVA]
+	mov	cr.iva = r0
+	mov	r1 = cr.iva
+	;;	
+	
+// CR[LID]
+	mov	cr.lid = r0
+	mov	r1 = cr.lid
+	;;	
+	srlz.d
+	
+// CR[LRR%]
+	mov	cr.lrr0 = r0
+	mov	r1 = cr.lrr0
+	;;
+	
+// CR[PMV]
+	mov	cr.pmv = r0
+	mov	r1 = cr.pmv
+	;;
+	
+// CR[PTA]
+	mov	cr.pta = r0
+	thash	r1 = r2
+	;;
+	
+// CR[TPR]
+	mov	cr.tpr = r0
+	mov	r1 = cr.ivr	// data
+	;;
+	srlz.d
+	mov	cr.tpr = r2
+	mov	psr.l = r3	// other
+	;;
+	srlz.d
+	
+// DBR# 
+	mov	dbr[r0] = r1
+	mov	r2 = dbr[r3]
+	;;	
+	srlz.d
+	mov	dbr[r4] = r5
+	probe.r	r6 = r7, r8
+	;;
+	srlz.d
+	
+// DTC
+	ptc.e	r0
+	fc	r1
+	;;
+	srlz.d
+	itr.i	itr[r2] = r3
+	ptc.e	r4
+	;;
+	
+// DTC_LIMIT/ITC_LIMIT 
+	ptc.g	r0, r1		// NOTE: GAS automatically emits stops after 
+	ptc.ga	r2, r3		//  ptc.g/ptc.ga, so this conflict is no     
+	;;			//  longer possible in GAS-generated assembly
+	srlz.d
+
+// DTR
+	itr.d	dtr[r0] = r1
+	tak	r2 = r3
+	;;
+	srlz.d
+	ptr.d	r4, r5
+	tpa	r6 = r7
+	;;
+	srlz.d
+	
+// FR%
+	ldfs.c.clr	f2 = [r1]
+	mov		f3 = f2		// no DV here
+	;;
+	mov		f4 = f5
+	mov		f6 = f4
+	;;
+
+// GR%
+	ld8.c.clr	r0 = [r1]	// no DV here
+	mov		r2 = r0		
+	;;
+	mov		r3 = r4
+	mov		r5 = r3
+	;;
+
+// IBR#
+	mov	ibr[r0] = r1
+	mov	r2 = ibr[r3]
+	;;
+
+// InService		
+	mov	cr.eoi = r0
+	mov	r1 = cr.ivr
+	;;
+	srlz.d
+	mov	r2 = cr.ivr
+	mov	r3 = cr.ivr	// several DVs
+	;;
+	mov	cr.eoi = r4
+	mov	cr.eoi = r5
+	;;
+	
+// ITC		
+	ptc.e	r0
+	epc
+	;;
+	srlz.i
+	;;
+	
+// ITC_LIMIT (see DTC_LIMIT)
+	
+// ITR	
+	itr.i	itr[r0] = r1
+	epc
+	;;
+	srlz.i
+	;;
+	
+// PKR#
+	mov	pkr[r0] = r1
+	probe.r	r2 = r3, r4
+	;;
+	srlz.d
+	mov	pkr[r5] = r6
+	mov	r7 = pkr[r8]
+	;;
+	srlz.d
+	
+// PMC#
+	mov	pmc[r0] = r1
+	mov	r2 = pmc[r3]
+	;;
+	srlz.d
+	mov	pmc[r4] = r5
+	mov	r6 = pmd[r7]
+	;;
+	srlz.d
+	
+// PMD#
+	mov	pmd[r0] = r1
+	mov	r2 = pmd[r3]
+	;;
+	
+// PR%
+	cmp.eq	p1, p2 = r0, r1	// pr-writer/pr-reader-nobr-nomovpr
+(p1)	add	r2 = r3, r4	
+	;;
+	mov	pr = r5, 0xffff // mov-to-pr-allreg/pr-reader-nobr-nomovpr
+(p2)	add	r6 = r7, r8	
+	;;
+	fcmp.eq p5, p6 = f2, f3 // pr-writer-fp/pr-reader-br
+(p5)	br.cond.sptk	b0
+	;;
+	cmp.eq	p7, p8 = r11, r12
+(p7)	br.cond.sptk	b1	// no DV here
+	;;
+	
+// PR63
+	br.wtop.sptk	L
+(p63)	add	r0 = r1, r2
+	;;
+	fcmp.eq p62, p63 = f2, f3
+(p63)	add	r3 = r4, r5	
+	;;
+	cmp.eq p62, p63 = r6, r7 // no DV here
+(p63)	br.cond.sptk	b0
+	;;	
+
+// PSR.ac
+	rum	(1<<3)
+	ld8	r0 = [r1]
+	;;
+
+// PSR.be
+	rum	(1<<1)
+	ld8	r0 = [r1]
+	;;
+	
+// PSR.bn
+	bsw.0
+	mov	r0 = r15	// no DV here, since gr < 16
+	;;
+	bsw.1			// GAS automatically emits a stop after bsw.n
+	mov	r1 = r16	// so this conflict is avoided               
+	;;
+	
+// PSR.cpl
+	epc
+	st8	[r0] = r1
+	;;
+	epc
+	mov	r2 = ar.itc
+	;;
+	epc
+	mov	ar.itc = r3
+	;;
+	epc
+	mov	ar.rsc = r4
+	;;
+	epc
+	mov	ar.k0 = r5
+	;;
+	epc
+	mov	r6 = pmd[r7]
+	;;
+	epc
+	mov	ar.bsp = r8	// no DV here
+	;;
+	epc
+	mov	r9 = ar.bsp	// no DV here
+	;;
+	epc
+	mov	cr.ifa = r10	// any mov-to/from-cr is a DV
+	;;
+	epc
+	mov	r11 = cr.eoi	// any mov-to/from-cr is a DV
+	;;
+
+// PSR.da (rfi is the only writer)
+// PSR.db (also ac,be,dt,pk)
+	mov	psr.l = r0
+	ld8	r1 = [r2]
+	;;
+	srlz.d
+
+// PSR.dd (rfi is the only writer)
+	
+// PSR.dfh
+	mov	psr.l = r0
+	mov	f64 = f65
+	;;
+	srlz.d
+
+// PSR.dfl
+	mov	psr.l = r0
+	mov	f3 = f4	
+	;;
+	srlz.d
+	
+// PSR.di
+	rsm	(1<<22)
+	mov	r0 = psr
+	;;
+
+// PSR.dt
+	rsm	(1<<17)
+	ld8	r0 = [r1]
+	;;
+	
+// PSR.ed (rfi is the only writer)
+// PSR.i
+	ssm	(1<<14)
+	mov	r0 = psr
+	;;
+	
+// PSR.ia (no DV semantics)
+// PSR.ic
+	ssm	(1<<13)
+	mov	r0 = psr
+	;;
+	srlz.d
+	rsm	(1<<13)
+	mov	r1 = cr.itir
+	;;
+	srlz.d
+	rsm	(1<<13)
+	mov	r1 = cr.irr0	// no DV here
+	;;
+	srlz.d
+
+// PSR.id (rfi is the only writer)
+// PSR.is (br.ia and rfi are the only writers)
+// PSR.it (rfi is the only writer)
+// PSR.lp
+	mov	psr.l = r0
+	br.ret.sptk	b0
+	;;
+
+// PSR.mc (rfi is the only writer)
+// PSR.mfh
+	mov	f32 = f33
+	mov	r0 = psr
+	;;
+
+// PSR.mfl
+	mov	f2 = f3
+	mov	r0 = psr
+	;;
+
+// PSR.pk
+	rsm	(1<<15)
+	ld8	r0 = [r1]
+	;;
+	rsm	(1<<15)
+	mov	r2 = psr
+	;;
+
+// PSR.pp
+	rsm	(1<<21)
+	mov	r0 = psr
+	;;
+
+// PSR.ri (no DV semantics)
+// PSR.rt
+	mov	psr.l = r0
+	flushrs
+	;;
+	srlz.d
+
+// PSR.si
+	rsm	(1<<23)
+	mov	r0 = ar.itc
+	;;
+	ssm	(1<<23)
+	mov	r1 = ar.ec	// no DV here
+	;;
+
+// PSR.sp
+	ssm	(1<<20)
+	mov	r0 = pmd[r1]
+	;;
+	ssm	(1<<20)
+	rum	0xff
+	;;
+	ssm	(1<<20)
+	mov	r0 = rr[r1]
+	;;
+
+// PSR.ss (rfi is the only writer)
+// PSR.tb
+	mov	psr.l = r0
+	chk.s	r0, L
+	;;
+
+// PSR.up
+	rsm	(1<<2)
+	mov	r0 = psr.um
+	;;
+	srlz.d
+
+// RR#
+	mov	rr[r0] = r1
+	ld8	r2 = [r0]	// data
+	;;
+	mov	rr[r4] = r5
+	mov	r6 = rr[r7]	// impliedf
+	;;
+// RSE
+L:	
diff --git a/gas/testsuite/gas/ia64/dv-safe.d b/gas/testsuite/gas/ia64/dv-safe.d
new file mode 100644
index 0000000..32254f2
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-safe.d
@@ -0,0 +1,21 @@
+# as: -xexplicit
+# objdump: -d
+# name ia64 dv-safe
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <start>:
+   0:	02 08 04 04 02 38 	\[MII\]       cmp\.eq p1,p2=r1,r2
+   6:	30 18 10 08 70 00 	            cmp\.eq p3,p4=r3,r4;;
+   c:	00 00 04 00       	            nop\.i 0x0
+  10:	10 00 00 00 01 00 	\[MIB\]       nop\.m 0x0
+  16:	00 00 00 02 80 21 	            nop\.i 0x0
+  1c:	30 00 00 50       	      \(p03\) br\.call\.sptk\.few b1=40 <L>
+  20:	20 20 08 00 00 a1 	\[MII\] \(p01\) mov r4=2
+  26:	40 28 00 00 c2 a1 	      \(p02\) mov r4=5
+  2c:	00 30 00 84       	      \(p03\) mov r5=r6
+  30:	81 28 00 0e 00 21 	\[MII\] \(p04\) mov r5=r7
+  36:	00 00 00 02 00 00 	            nop\.i 0x0
+  3c:	00 00 04 00       	            nop\.i 0x0;;
diff --git a/gas/testsuite/gas/ia64/dv-safe.s b/gas/testsuite/gas/ia64/dv-safe.s
new file mode 100644
index 0000000..5d92e63
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-safe.s
@@ -0,0 +1,19 @@
+//	
+// Test predicate safety across calls
+//	
+.text
+start:	
+// user annotation	
+	.pred.safe_across_calls p1-p4
+	.pred.safe_across_calls p1,p2,p3,p4
+	.pred.safe_across_calls p1-p2,p3-p4
+	.pred.safe_across_calls p1-p3,p4
+	cmp.eq	p1, p2 = r1, r2
+	cmp.eq	p3, p4 = r3, r4 ;;
+	
+(p3)	br.call.sptk	b1 = L
+(p1)	mov	r4 = 2
+(p2)	mov	r4 = 5
+(p3)	mov	r5 = r6
+(p4)	mov	r5 = r7
+L:	
diff --git a/gas/testsuite/gas/ia64/dv-srlz.d b/gas/testsuite/gas/ia64/dv-srlz.d
new file mode 100644
index 0000000..c332a47
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-srlz.d
@@ -0,0 +1,24 @@
+# as: -xauto
+# objdump: -d
+# name ia64 dv-srlz
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <start>:
+   0:	0a 00 00 02 34 04 	\[MMI\]       ptc\.e r1;;
+   6:	00 00 00 60 00 00 	            srlz\.d
+   c:	00 00 04 00       	            nop\.i 0x0
+  10:	11 00 00 00 18 10 	\[MIB\]       ld8 r0=\[r0\]
+  16:	00 00 00 02 00 00 	            nop\.i 0x0
+  1c:	00 00 20 00       	            rfi;;
+  20:	0b 00 00 02 34 04 	\[MMI\]       ptc\.e r1;;
+  26:	00 00 00 62 00 00 	            srlz\.i
+  2c:	00 00 04 00       	            nop\.i 0x0;;
+  30:	13 00 00 00 01 00 	\[MBB\]       nop\.m 0x0
+  36:	00 00 00 20 00 00 	            epc
+  3c:	00 00 00 20       	            nop\.b 0x0;;
+  40:	11 00 00 00 01 00 	\[MIB\]       nop\.m 0x0
+  46:	00 00 00 02 00 00 	            nop\.i 0x0
+  4c:	00 00 20 00       	            rfi;;
diff --git a/gas/testsuite/gas/ia64/dv-srlz.s b/gas/testsuite/gas/ia64/dv-srlz.s
new file mode 100644
index 0000000..273e51b
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-srlz.s
@@ -0,0 +1,13 @@
+//
+// Auto-insertion of instruction and data serialization
+//			
+.text
+start:		
+// Requires data serialization	
+	ptc.e	r1
+	ld8	r1 = [r2]
+	rfi
+// Requires instruction serialization
+	ptc.e	r1
+	epc
+	rfi
diff --git a/gas/testsuite/gas/ia64/dv-war-err.l b/gas/testsuite/gas/ia64/dv-war-err.l
new file mode 100644
index 0000000..0f186c0
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-war-err.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:8: Warning: Use of 'br.wtop.sptk' .* WAR dependency 'PR63' \(impliedf\)
+.*:7: Warning: This is the location of the conflicting usage
diff --git a/gas/testsuite/gas/ia64/dv-war-err.s b/gas/testsuite/gas/ia64/dv-war-err.s
new file mode 100644
index 0000000..a226e96
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-war-err.s
@@ -0,0 +1,9 @@
+//	
+// Detect WAR violations.  Cases taken from DV tables.
+//	
+.text
+	.explicit
+// PR63
+(p63)	br.cond.sptk	b0
+	br.wtop.sptk	L	
+L:	
diff --git a/gas/testsuite/gas/ia64/dv-waw-err.l b/gas/testsuite/gas/ia64/dv-waw-err.l
new file mode 100644
index 0000000..e446757
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-waw-err.l
@@ -0,0 +1,353 @@
+.*: Assembler messages:
+.*:8: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[BSP\]' \(impliedf\)
+.*:7: Warning: This is the location of the conflicting usage
+.*:12: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[BSP\]' \(impliedf\)
+.*:11: Warning: This is the location of the conflicting usage
+.*:12: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[BSPSTORE\]' \(impliedf\)
+.*:11: Warning: This is the location of the conflicting usage
+.*:12: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[RNAT\]' \(impliedf\)
+.*:11: Warning: This is the location of the conflicting usage
+.*:12: Warning: Use of 'mov\.m' .* RAW dependency 'RSE' \(impliedf\)
+.*:11: Warning: This is the location of the conflicting usage
+.*:12: Warning: Use of 'mov\.m' .* WAW dependency 'RSE' \(impliedf\)
+.*:11: Warning: This is the location of the conflicting usage
+.*:17: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[CCV\]' \(impliedf\)
+.*:16: Warning: This is the location of the conflicting usage
+.*:22: Warning: Use of 'mov\.i' .* WAW dependency 'AR\[EC\]' \(impliedf\)
+.*:21: Warning: This is the location of the conflicting usage
+.*:27: Warning: Use of 'fsetc\.s0' .* RAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\)
+.*:26: Warning: This is the location of the conflicting usage
+.*:27: Warning: Use of 'fsetc\.s0' .* WAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\)
+.*:26: Warning: This is the location of the conflicting usage
+.*:32: Warning: Use of 'fsetc\.s1' .* RAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\)
+.*:31: Warning: This is the location of the conflicting usage
+.*:32: Warning: Use of 'fsetc\.s1' .* WAW dependency 'AR\[FPSR\]\.sf1\.controls' \(impliedf\)
+.*:31: Warning: This is the location of the conflicting usage
+.*:37: Warning: Use of 'fsetc\.s2' .* RAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\)
+.*:36: Warning: This is the location of the conflicting usage
+.*:37: Warning: Use of 'fsetc\.s2' .* WAW dependency 'AR\[FPSR\]\.sf2\.controls' \(impliedf\)
+.*:36: Warning: This is the location of the conflicting usage
+.*:42: Warning: Use of 'fsetc\.s3' .* RAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\)
+.*:41: Warning: This is the location of the conflicting usage
+.*:42: Warning: Use of 'fsetc\.s3' .* WAW dependency 'AR\[FPSR\]\.sf3\.controls' \(impliedf\)
+.*:41: Warning: This is the location of the conflicting usage
+.*:50: Warning: Use of 'fclrf\.s0' .* WAW dependency 'AR\[FPSR\]\.sf0\.flags' \(impliedf\)
+.*:49: Warning: This is the location of the conflicting usage
+.*:58: Warning: Use of 'fclrf\.s1' .* WAW dependency 'AR\[FPSR\]\.sf1\.flags' \(impliedf\)
+.*:57: Warning: This is the location of the conflicting usage
+.*:66: Warning: Use of 'fclrf\.s2' .* WAW dependency 'AR\[FPSR\]\.sf2\.flags' \(impliedf\)
+.*:65: Warning: This is the location of the conflicting usage
+.*:74: Warning: Use of 'fclrf\.s3' .* WAW dependency 'AR\[FPSR\]\.sf3\.flags' \(impliedf\)
+.*:73: Warning: This is the location of the conflicting usage
+.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\)
+.*:78: Warning: This is the location of the conflicting usage
+.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf1\.controls' \(impliedf\)
+.*:78: Warning: This is the location of the conflicting usage
+.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf2\.controls' \(impliedf\)
+.*:78: Warning: This is the location of the conflicting usage
+.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf3\.controls' \(impliedf\)
+.*:78: Warning: This is the location of the conflicting usage
+.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf0\.flags' \(impliedf\)
+.*:78: Warning: This is the location of the conflicting usage
+.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf0\.flags' \(impliedf\)
+.*:78: Warning: This is the location of the conflicting usage
+.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf1\.flags' \(impliedf\)
+.*:78: Warning: This is the location of the conflicting usage
+.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf1\.flags' \(impliedf\)
+.*:78: Warning: This is the location of the conflicting usage
+.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf2\.flags' \(impliedf\)
+.*:78: Warning: This is the location of the conflicting usage
+.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf2\.flags' \(impliedf\)
+.*:78: Warning: This is the location of the conflicting usage
+.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf3\.flags' \(impliedf\)
+.*:78: Warning: This is the location of the conflicting usage
+.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf3\.flags' \(impliedf\)
+.*:78: Warning: This is the location of the conflicting usage
+.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.rv' \(impliedf\)
+.*:78: Warning: This is the location of the conflicting usage
+.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.traps' \(impliedf\)
+.*:78: Warning: This is the location of the conflicting usage
+.*:84: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[ITC\]' \(impliedf\)
+.*:83: Warning: This is the location of the conflicting usage
+.*:89: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[K%\], % in 0 - 7' \(impliedf\), specific resource number is 2
+.*:88: Warning: This is the location of the conflicting usage
+.*:94: Warning: Use of 'mov\.i' .* WAW dependency 'AR\[LC\]' \(impliedf\)
+.*:93: Warning: This is the location of the conflicting usage
+.*:99: Warning: Use of 'br\.call\.sptk' .* WAW dependency 'AR\[PFS\]' \(impliedf\)
+.*:98: Warning: This is the location of the conflicting usage
+.*:104: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[RNAT\]' \(impliedf\)
+.*:103: Warning: This is the location of the conflicting usage
+.*:109: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[RSC\]' \(impliedf\)
+.*:108: Warning: This is the location of the conflicting usage
+.*:114: Warning: Use of 'st8\.spill' .* WAW dependency 'AR\[UNAT\]{%}, % in 0 - 63' \(impliedf\)
+.*:113: Warning: This is the location of the conflicting usage
+.*:119: Warning: Use of 'mov\.m' .* WAW dependency 'AR%, % in 48 - 63, 112-127' \(impliedf\), specific resource number is 48
+.*:118: Warning: This is the location of the conflicting usage
+.*:124: Warning: Use of 'mov' .* WAW dependency 'BR%, % in 0 - 7' \(impliedf\), specific resource number is 1
+.*:123: Warning: This is the location of the conflicting usage
+.*:129: Warning: Use of 'br\.wtop\.sptk' .* RAW dependency 'AR\[EC\]' \(impliedf\)
+.*:128: Warning: This is the location of the conflicting usage
+.*:129: Warning: Use of 'br\.wtop\.sptk' .* RAW dependency 'CFM' \(impliedf\)
+.*:128: Warning: This is the location of the conflicting usage
+.*:129: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'AR\[EC\]' \(impliedf\)
+.*:128: Warning: This is the location of the conflicting usage
+.*:129: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'CFM' \(impliedf\)
+.*:128: Warning: This is the location of the conflicting usage
+.*:129: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'PR63' \(impliedf\)
+.*:128: Warning: This is the location of the conflicting usage
+.*:129: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'PR63' \(impliedf\)
+.*:128: Warning: This is the location of the conflicting usage
+.*:134: Warning: Use of 'mov' .* WAW dependency 'CR\[CMCV\]' \(impliedf\)
+.*:133: Warning: This is the location of the conflicting usage
+.*:139: Warning: Use of 'mov' .* WAW dependency 'CR\[DCR\]' \(impliedf\)
+.*:138: Warning: This is the location of the conflicting usage
+.*:144: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(impliedf\)
+.*:143: Warning: This is the location of the conflicting usage
+.*:144: Warning: Use of 'mov' .* WAW dependency 'CR\[EOI\]' \(other\)
+.*:143: Warning: This is the location of the conflicting usage
+.*:144: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
+.*:143: Warning: This is the location of the conflicting usage
+.*:150: Warning: Use of 'mov' .* WAW dependency 'CR\[GPTA\]' \(impliedf\)
+.*:149: Warning: This is the location of the conflicting usage
+.*:155: Warning: Use of 'mov' .* WAW dependency 'CR\[IFA\]' \(impliedf\)
+.*:154: Warning: This is the location of the conflicting usage
+.*:160: Warning: Use of 'cover' .* WAW dependency 'CR\[IFS\]' \(impliedf\)
+.*:159: Warning: This is the location of the conflicting usage
+.*:165: Warning: Use of 'mov' .* WAW dependency 'CR\[IHA\]' \(impliedf\)
+.*:164: Warning: This is the location of the conflicting usage
+.*:170: Warning: Use of 'mov' .* WAW dependency 'CR\[IIM\]' \(impliedf\)
+.*:169: Warning: This is the location of the conflicting usage
+.*:175: Warning: Use of 'mov' .* WAW dependency 'CR\[IIP\]' \(impliedf\)
+.*:174: Warning: This is the location of the conflicting usage
+.*:180: Warning: Use of 'mov' .* WAW dependency 'CR\[IIPA\]' \(impliedf\)
+.*:179: Warning: This is the location of the conflicting usage
+.*:185: Warning: Use of 'mov' .* WAW dependency 'CR\[IPSR\]' \(impliedf\)
+.*:184: Warning: This is the location of the conflicting usage
+.*:190: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(impliedf\)
+.*:189: Warning: This is the location of the conflicting usage
+.*:190: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 71
+.*:189: Warning: This is the location of the conflicting usage
+.*:190: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 70
+.*:189: Warning: This is the location of the conflicting usage
+.*:190: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 69
+.*:189: Warning: This is the location of the conflicting usage
+.*:190: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 68
+.*:189: Warning: This is the location of the conflicting usage
+.*:190: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
+.*:189: Warning: This is the location of the conflicting usage
+.*:195: Warning: Use of 'mov' .* WAW dependency 'CR\[ISR\]' \(impliedf\)
+.*:194: Warning: This is the location of the conflicting usage
+.*:200: Warning: Use of 'mov' .* WAW dependency 'CR\[ITIR\]' \(impliedf\)
+.*:199: Warning: This is the location of the conflicting usage
+.*:205: Warning: Use of 'mov' .* WAW dependency 'CR\[ITM\]' \(impliedf\)
+.*:204: Warning: This is the location of the conflicting usage
+.*:210: Warning: Use of 'mov' .* WAW dependency 'CR\[ITV\]' \(impliedf\)
+.*:209: Warning: This is the location of the conflicting usage
+.*:215: Warning: Use of 'mov' .* WAW dependency 'CR\[IVA\]' \(impliedf\)
+.*:214: Warning: This is the location of the conflicting usage
+.*:222: Warning: Use of 'mov' .* WAW dependency 'CR\[LID\]' \(other\)
+.*:221: Warning: This is the location of the conflicting usage
+.*:230: Warning: Use of 'mov' .* WAW dependency 'CR\[LRR%\], % in 0 - 1' \(impliedf\), specific resource number is 80
+.*:229: Warning: This is the location of the conflicting usage
+.*:235: Warning: Use of 'mov' .* WAW dependency 'CR\[PMV\]' \(impliedf\)
+.*:234: Warning: This is the location of the conflicting usage
+.*:240: Warning: Use of 'mov' .* WAW dependency 'CR\[PTA\]' \(impliedf\)
+.*:239: Warning: This is the location of the conflicting usage
+.*:245: Warning: Use of 'mov' .* WAW dependency 'CR\[TPR\]' \(impliedf\)
+.*:244: Warning: This is the location of the conflicting usage
+.*:250: Warning: Use of 'mov' .* WAW dependency 'DBR#' \(impliedf\)
+.*:249: Warning: This is the location of the conflicting usage
+.*:259: Warning: Use of 'itc\.i' .* RAW dependency 'DTC' \(impliedf\)
+.*:258: Warning: This is the location of the conflicting usage
+.*:259: Warning: Use of 'itc\.i' .* RAW dependency 'ITC' \(impliedf\)
+.*:258: Warning: This is the location of the conflicting usage
+.*:259: Warning: Use of 'itc\.i' .* WAW dependency 'DTC' \(impliedf\)
+.*:258: Warning: This is the location of the conflicting usage
+.*:259: Warning: Use of 'itc\.i' .* WAW dependency 'ITC' \(impliedf\)
+.*:258: Warning: This is the location of the conflicting usage
+.*:271: Warning: Use of 'ptr\.d' .* RAW dependency 'DTC' \(impliedf\)
+.*:270: Warning: This is the location of the conflicting usage
+.*:271: Warning: Use of 'ptr\.d' .* RAW dependency 'DTR' \(impliedf\)
+.*:270: Warning: This is the location of the conflicting usage
+.*:271: Warning: Use of 'ptr\.d' .* RAW dependency 'ITC' \(impliedf\)
+.*:270: Warning: This is the location of the conflicting usage
+.*:271: Warning: Use of 'ptr\.d' .* WAW dependency 'DTC' \(impliedf\)
+.*:270: Warning: This is the location of the conflicting usage
+.*:271: Warning: Use of 'ptr\.d' .* WAW dependency 'DTR' \(impliedf\)
+.*:270: Warning: This is the location of the conflicting usage
+.*:271: Warning: Use of 'ptr\.d' .* WAW dependency 'ITC' \(impliedf\)
+.*:270: Warning: This is the location of the conflicting usage
+.*:277: Warning: Use of 'ldfs\.c\.clr' .* WAW dependency 'FR%, % in 2 - 127' \(impliedf\), specific resource number is 3
+.*:276: Warning: This is the location of the conflicting usage
+.*:282: Warning: Use of 'ld8\.c\.clr' .* WAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 2
+.*:281: Warning: This is the location of the conflicting usage
+.*:287: Warning: Use of 'mov' .* WAW dependency 'IBR#' \(impliedf\)
+.*:286: Warning: This is the location of the conflicting usage
+.*:292: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(data\)
+.*:291: Warning: This is the location of the conflicting usage
+.*:292: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
+.*:291: Warning: This is the location of the conflicting usage
+.*:298: Warning: Use of 'itc\.i' .* RAW dependency 'DTC' \(impliedf\)
+.*:297: Warning: This is the location of the conflicting usage
+.*:298: Warning: Use of 'itc\.i' .* RAW dependency 'ITC' \(impliedf\)
+.*:297: Warning: This is the location of the conflicting usage
+.*:298: Warning: Use of 'itc\.i' .* WAW dependency 'DTC' \(impliedf\)
+.*:297: Warning: This is the location of the conflicting usage
+.*:298: Warning: Use of 'itc\.i' .* WAW dependency 'ITC' \(impliedf\)
+.*:297: Warning: This is the location of the conflicting usage
+.*:305: Warning: Use of 'ptr\.i' .* RAW dependency 'DTC' \(impliedf\)
+.*:304: Warning: This is the location of the conflicting usage
+.*:305: Warning: Use of 'ptr\.i' .* RAW dependency 'ITC' \(impliedf\)
+.*:304: Warning: This is the location of the conflicting usage
+.*:305: Warning: Use of 'ptr\.i' .* RAW dependency 'ITR' \(impliedf\)
+.*:304: Warning: This is the location of the conflicting usage
+.*:305: Warning: Use of 'ptr\.i' .* WAW dependency 'DTC' \(impliedf\)
+.*:304: Warning: This is the location of the conflicting usage
+.*:305: Warning: Use of 'ptr\.i' .* WAW dependency 'ITC' \(impliedf\)
+.*:304: Warning: This is the location of the conflicting usage
+.*:305: Warning: Use of 'ptr\.i' .* WAW dependency 'ITR' \(impliedf\)
+.*:304: Warning: This is the location of the conflicting usage
+.*:317: Warning: Use of 'mov' .* WAW dependency 'PKR#' \(impliedf\), specific resource number is 1
+.*:316: Warning: This is the location of the conflicting usage
+.*:322: Warning: Use of 'mov' .* WAW dependency 'PMC#' \(impliedf\)
+.*:321: Warning: This is the location of the conflicting usage
+.*:327: Warning: Use of 'mov' .* WAW dependency 'PMD#' \(impliedf\)
+.*:326: Warning: This is the location of the conflicting usage
+.*:332: Warning: Use of 'cmp\.eq' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1
+.*:331: Warning: This is the location of the conflicting usage
+.*:332: Warning: Use of 'cmp\.eq' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1
+.*:331: Warning: This is the location of the conflicting usage
+.*:335: Warning: Use of 'fcmp\.eq' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1
+.*:334: Warning: This is the location of the conflicting usage
+.*:335: Warning: Use of 'fcmp\.eq' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1
+.*:334: Warning: This is the location of the conflicting usage
+.*:338: Warning: Use of 'cmp\.eq\.or' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1
+.*:337: Warning: This is the location of the conflicting usage
+.*:341: Warning: Use of 'cmp\.eq\.and' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1
+.*:340: Warning: This is the location of the conflicting usage
+.*:352: Warning: Use of 'br\.wtop\.sptk' .* RAW dependency 'AR\[EC\]' \(impliedf\)
+.*:351: Warning: This is the location of the conflicting usage
+.*:352: Warning: Use of 'br\.wtop\.sptk' .* RAW dependency 'CFM' \(impliedf\)
+.*:351: Warning: This is the location of the conflicting usage
+.*:352: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'AR\[EC\]' \(impliedf\)
+.*:351: Warning: This is the location of the conflicting usage
+.*:352: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'CFM' \(impliedf\)
+.*:351: Warning: This is the location of the conflicting usage
+.*:352: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'PR63' \(impliedf\)
+.*:351: Warning: This is the location of the conflicting usage
+.*:352: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'PR63' \(impliedf\)
+.*:351: Warning: This is the location of the conflicting usage
+.*:355: Warning: Use of 'cmp\.eq' .* WAW dependency 'PR63' \(impliedf\)
+.*:354: Warning: This is the location of the conflicting usage
+.*:355: Warning: Use of 'cmp\.eq' .* WAW dependency 'PR63' \(impliedf\)
+.*:354: Warning: This is the location of the conflicting usage
+.*:358: Warning: Use of 'fcmp\.eq' .* WAW dependency 'PR63' \(impliedf\)
+.*:357: Warning: This is the location of the conflicting usage
+.*:358: Warning: Use of 'fcmp\.eq' .* WAW dependency 'PR63' \(impliedf\)
+.*:357: Warning: This is the location of the conflicting usage
+.*:361: Warning: Use of 'cmp\.eq\.or' .* WAW dependency 'PR63' \(impliedf\)
+.*:360: Warning: This is the location of the conflicting usage
+.*:364: Warning: Use of 'cmp\.eq\.and' .* WAW dependency 'PR63' \(impliedf\)
+.*:363: Warning: This is the location of the conflicting usage
+.*:375: Warning: Use of 'rum' .* WAW dependency 'PSR\.ac' \(impliedf\)
+.*:374: Warning: This is the location of the conflicting usage
+.*:380: Warning: Use of 'rum' .* WAW dependency 'PSR\.be' \(impliedf\)
+.*:379: Warning: This is the location of the conflicting usage
+.*:390: Warning: Use of 'br\.ret\.sptk' .* WAW dependency 'PSR\.cpl' \(impliedf\)
+.*:389: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.ac' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.be' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.db' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.dfh' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.dfl' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.di' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.dt' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.i' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.ic' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.lp' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfh' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfh' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfl' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfl' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.pk' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.pp' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.rt' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.si' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.sp' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.tb' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.up' \(impliedf\)
+.*:395: Warning: This is the location of the conflicting usage
+.*:404: Warning: Use of 'ssm' .* WAW dependency 'PSR\.dfh' \(impliedf\)
+.*:403: Warning: This is the location of the conflicting usage
+.*:410: Warning: Use of 'ssm' .* WAW dependency 'PSR\.dfl' \(impliedf\)
+.*:409: Warning: This is the location of the conflicting usage
+.*:416: Warning: Use of 'rsm' .* WAW dependency 'PSR\.di' \(impliedf\)
+.*:415: Warning: This is the location of the conflicting usage
+.*:421: Warning: Use of 'rsm' .* WAW dependency 'PSR\.dt' \(impliedf\)
+.*:420: Warning: This is the location of the conflicting usage
+.*:427: Warning: Use of 'ssm' .* WAW dependency 'PSR\.i' \(impliedf\)
+.*:426: Warning: This is the location of the conflicting usage
+.*:433: Warning: Use of 'ssm' .* WAW dependency 'PSR\.ic' \(impliedf\)
+.*:432: Warning: This is the location of the conflicting usage
+.*:444: Warning: Use of 'mov' .* RAW dependency 'PSR\.mfh' \(impliedf\)
+.*:443: Warning: This is the location of the conflicting usage
+.*:447: Warning: Use of 'ssm' .* WAW dependency 'PSR\.mfh' \(impliedf\)
+.*:446: Warning: This is the location of the conflicting usage
+.*:447: Warning: Use of 'ssm' .* WAW dependency 'PSR\.mfh' \(impliedf\)
+.*:446: Warning: This is the location of the conflicting usage
+.*:450: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfh' \(impliedf\)
+.*:449: Warning: This is the location of the conflicting usage
+.*:450: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfh' \(impliedf\)
+.*:449: Warning: This is the location of the conflicting usage
+.*:453: Warning: Use of 'rum' .* WAW dependency 'PSR\.mfh' \(impliedf\)
+.*:452: Warning: This is the location of the conflicting usage
+.*:453: Warning: Use of 'rum' .* WAW dependency 'PSR\.mfh' \(impliedf\)
+.*:452: Warning: This is the location of the conflicting usage
+.*:461: Warning: Use of 'mov' .* RAW dependency 'PSR\.mfl' \(impliedf\)
+.*:460: Warning: This is the location of the conflicting usage
+.*:464: Warning: Use of 'ssm' .* WAW dependency 'PSR\.mfl' \(impliedf\)
+.*:463: Warning: This is the location of the conflicting usage
+.*:464: Warning: Use of 'ssm' .* WAW dependency 'PSR\.mfl' \(impliedf\)
+.*:463: Warning: This is the location of the conflicting usage
+.*:467: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfl' \(impliedf\)
+.*:466: Warning: This is the location of the conflicting usage
+.*:467: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfl' \(impliedf\)
+.*:466: Warning: This is the location of the conflicting usage
+.*:470: Warning: Use of 'rum' .* WAW dependency 'PSR\.mfl' \(impliedf\)
+.*:469: Warning: This is the location of the conflicting usage
+.*:470: Warning: Use of 'rum' .* WAW dependency 'PSR\.mfl' \(impliedf\)
+.*:469: Warning: This is the location of the conflicting usage
+.*:478: Warning: Use of 'rsm' .* WAW dependency 'PSR\.pk' \(impliedf\)
+.*:477: Warning: This is the location of the conflicting usage
+.*:483: Warning: Use of 'rsm' .* WAW dependency 'PSR\.pp' \(impliedf\)
+.*:482: Warning: This is the location of the conflicting usage
+.*:491: Warning: Use of 'ssm' .* WAW dependency 'PSR\.si' \(impliedf\)
+.*:490: Warning: This is the location of the conflicting usage
+.*:496: Warning: Use of 'rsm' .* WAW dependency 'PSR\.sp' \(impliedf\)
+.*:495: Warning: This is the location of the conflicting usage
+.*:505: Warning: Use of 'rsm' .* WAW dependency 'PSR\.up' \(impliedf\)
+.*:504: Warning: This is the location of the conflicting usage
+.*:508: Warning: Use of 'mov' .* WAW dependency 'PSR\.up' \(impliedf\)
+.*:507: Warning: This is the location of the conflicting usage
+.*:513: Warning: Use of 'mov' .* WAW dependency 'RR#' \(impliedf\)
+.*:512: Warning: This is the location of the conflicting usage
diff --git a/gas/testsuite/gas/ia64/dv-waw-err.s b/gas/testsuite/gas/ia64/dv-waw-err.s
new file mode 100644
index 0000000..c6f4fe0
--- /dev/null
+++ b/gas/testsuite/gas/ia64/dv-waw-err.s
@@ -0,0 +1,516 @@
+//	
+// Detect WAW violations.  Cases taken from DV tables.
+//	
+.text
+	.explicit
+// AR[BSP]
+	mov	ar.bsp = r0
+	mov	ar.bsp = r1
+	;;
+// AR[BSPSTORE]	
+	mov	ar.bspstore = r2
+	mov	ar.bspstore = r3
+	;;
+	
+// AR[CCV]
+	mov	ar.ccv = r4
+	mov	ar.ccv = r4
+	;;
+	
+// AR[EC]	
+	br.wtop.sptk	L
+	mov	ar.ec = r0
+	;;
+
+// AR[FPSR].sf0.controls 
+	mov		ar.fpsr = r0
+	fsetc.s0	0x7f, 0x0f
+	;;
+
+// AR[FPSR].sf1.controls
+	mov		ar.fpsr = r0
+	fsetc.s1	0x7f, 0x0f
+	;;
+
+// AR[FPSR].sf2.controls
+	mov		ar.fpsr = r0
+	fsetc.s2	0x7f, 0x0f
+	;;
+
+// AR[FPSR].sf3.controls
+	mov		ar.fpsr = r0
+	fsetc.s3	0x7f, 0x0f
+	;;
+
+// AR[FPSR].sf0.flags
+	fcmp.eq.s0	p1, p2 = f3, f4
+	fcmp.eq.s0	p3, p4 = f3, f4	// no DV here
+	;;
+	fcmp.eq.s0	p1, p2 = f3, f4
+	fclrf.s0
+	;;
+
+// AR[FPSR].sf1.flags
+	fcmp.eq.s1	p1, p2 = f3, f4
+	fcmp.eq.s1	p3, p4 = f3, f4	// no DV here
+	;;
+	fcmp.eq.s1	p1, p2 = f3, f4
+	fclrf.s1
+	;;
+
+// AR[FPSR].sf2.flags
+	fcmp.eq.s2	p1, p2 = f3, f4
+	fcmp.eq.s2	p3, p4 = f3, f4	// no DV here
+	;;
+	fcmp.eq.s2	p1, p2 = f3, f4
+	fclrf.s2
+	;;
+
+// AR[FPSR].sf3.flags
+	fcmp.eq.s3	p1, p2 = f3, f4
+	fcmp.eq.s3	p3, p4 = f3, f4	// no DV here
+	;;
+	fcmp.eq.s3	p1, p2 = f3, f4
+	fclrf.s3
+	;;
+
+// AR[FPSR].traps/rv plus all controls/flags
+	mov	ar.fpsr = r0
+	mov	ar.fpsr = r0
+	;;
+
+// AR[ITC]
+	mov	ar.itc = r1
+	mov	ar.itc = r1
+	;;
+
+// AR[K]
+	mov	ar.k2 = r3
+	mov	ar.k2 = r3
+	;;
+	
+// AR[LC]
+	br.cloop.sptk	L
+	mov	ar.lc = r0
+	;;
+	
+// AR[PFS]
+	mov	ar.pfs = r0
+	br.call.sptk	b0 = L
+	;;
+
+// AR[RNAT] (see also AR[BSPSTORE])
+	mov	ar.rnat = r8
+	mov	ar.rnat = r8
+	;;
+	
+// AR[RSC]
+	mov	ar.rsc = r10
+	mov	ar.rsc = r10
+	;;	
+	
+// AR[UNAT]	
+	mov	ar.unat = r12
+	st8.spill	[r0] = r1
+	;;
+	
+// AR%
+	mov	ar48 = r0
+	mov	ar48 = r0
+	;;
+
+// BR%
+	mov	b1 = r0
+	mov	b1 = r1
+	;;
+	
+// CFM (and others)
+	br.wtop.sptk	L
+	br.wtop.sptk	L
+	;;
+	
+// CR[CMCV]
+	mov	cr.cmcv = r1
+	mov	cr.cmcv = r2
+	;;
+
+// CR[DCR]
+	mov	cr.dcr = r3
+	mov	cr.dcr = r3
+	;;
+
+// CR[EOI] (and InService)
+	mov	cr.eoi = r0
+	mov	cr.eoi = r0
+	;;
+	srlz.d
+	
+// CR[GPTA]
+	mov	cr.gpta = r6
+	mov	cr.gpta = r7
+	;;
+
+// CR[IFA]
+	mov	cr.ifa = r9
+	mov	cr.ifa = r10
+	;;
+
+// CR[IFS]
+	mov	cr.ifs = r11
+	cover
+	;;
+
+// CR[IHA]
+	mov	cr.iha = r13
+	mov	cr.iha = r14
+	;;
+
+// CR[IIM]
+	mov	cr.iim = r15
+	mov	cr.iim = r16
+	;;
+
+// CR[IIP] 
+	mov	cr.iip = r17
+	mov	cr.iip = r17
+	;;
+
+// CR[IIPA]
+	mov	cr.iipa = r19
+	mov	cr.iipa = r20
+	;;
+
+// CR[IPSR]
+	mov	cr.ipsr = r21
+	mov	cr.ipsr = r22
+	;;
+
+// CR[IRR%] (and others)
+	mov	r0 = cr.ivr
+	mov	r1 = cr.ivr
+	;;
+	
+// CR[ISR]
+	mov	cr.isr = r24
+	mov	cr.isr = r25
+	;;	
+	
+// CR[ITIR]
+	mov	cr.itir = r26
+	mov	cr.itir = r27
+	;;	
+	
+// CR[ITM]
+	mov	cr.itm = r28
+	mov	cr.itm = r29
+	;;	
+	
+// CR[ITV]
+	mov	cr.itv = r0
+	mov	cr.itv = r1
+	;;	
+	
+// CR[IVA]
+	mov	cr.iva = r0
+	mov	cr.iva = r1
+	;;	
+	
+// CR[IVR] (no explicit writers)
+	
+// CR[LID]
+	mov	cr.lid = r0
+	mov	cr.lid = r1
+	;;
+	
+// CR[LRR%]
+	mov	cr.lrr0 = r0
+	mov	cr.lrr1 = r0 // no DV here
+	;;
+	mov	cr.lrr0 = r0
+	mov	cr.lrr0 = r0
+	;;
+	
+// CR[PMV]
+	mov	cr.pmv = r0
+	mov	cr.pmv = r1
+	;;
+	
+// CR[PTA]
+	mov	cr.pta = r0
+	mov	cr.pta = r1
+	;;
+	
+// CR[TPR]
+	mov	cr.tpr = r0
+	mov	cr.tpr = r1
+	;;
+	
+// DBR# 
+	mov	dbr[r1] = r1
+	mov	dbr[r1] = r2
+	;;
+	srlz.d
+	
+// DTC
+	ptc.e	r0
+	ptc.e	r1	// no DVs here
+	;;
+	ptc.e	r0	// (and others)
+	itc.i	r0
+	;;
+	srlz.d
+	
+// DTC_LIMIT
+	ptc.g	r0, r1		// NOTE: GAS automatically emits stops after 
+	ptc.ga	r2, r3		//  ptc.g/ptc.ga, so this conflict is no     
+	;;			//  longer possible in GAS-generated assembly
+	srlz.d
+	
+// DTR 
+	itr.d	dtr[r0] = r1	// (and others)
+	ptr.d	r2, r3
+	;;
+	srlz.d
+	
+// FR%
+	mov		f3 = f2
+	ldfs.c.clr	f3 = [r1]
+	;;
+
+// GR%
+	mov		r2 = r0		
+	ld8.c.clr	r2 = [r1]
+	;;
+
+// IBR#
+	mov	ibr[r0] = r2
+	mov	ibr[r1] = r2
+	;;
+
+// InService		
+	mov	cr.eoi = r0
+	mov	r1 = cr.ivr
+	;;
+	srlz.d
+	
+// ITC		
+	ptc.e	r0
+	itc.i	r1
+	;;
+	srlz.i
+	;;
+	
+// ITR	
+	itr.i	itr[r0] = r1
+	ptr.i	r2, r3
+	;;
+	srlz.i
+	;;
+	
+// PKR#
+	.reg.val r1, 0x1
+	.reg.val r2, ~0x1
+	mov	pkr[r1] = r1
+	mov	pkr[r2] = r1	// no DV here
+	;;
+	mov	pkr[r1] = r1
+	mov	pkr[r1] = r1
+	;;
+	
+// PMC#
+	mov	pmc[r3] = r1
+	mov	pmc[r4] = r1
+	;;
+	
+// PMD#
+	mov	pmd[r3] = r1
+	mov	pmd[r4] = r1
+	;;
+	
+// PR%
+	cmp.eq	p1, p0 = r0, r1
+	cmp.eq	p1, p0 = r2, r3
+	;;
+	fcmp.eq p1, p2 = f2, f3
+	fcmp.eq p1, p3 = f2, f3
+	;;
+	cmp.eq.and p1, p2 = r0, r1
+	cmp.eq.or  p1, p3 = r2, r3
+	;;
+	cmp.eq.or  p1, p3 = r2, r3
+	cmp.eq.and p1, p2 = r0, r1
+	;;
+	cmp.eq.and p1, p2 = r0, r1
+	cmp.eq.and p1, p3 = r2, r3 // no DV here
+	;;
+	cmp.eq.or p1, p2 = r0, r1
+	cmp.eq.or p1, p3 = r2, r3 // no DV here
+	;;
+	
+// PR63
+	br.wtop.sptk	L
+	br.wtop.sptk	L
+	;;
+	cmp.eq	p63, p0 = r0, r1
+	cmp.eq	p63, p0 = r2, r3
+	;;
+	fcmp.eq p63, p2 = f2, f3
+	fcmp.eq p63, p3 = f2, f3
+	;;
+	cmp.eq.and p63, p2 = r0, r1
+	cmp.eq.or  p63, p3 = r2, r3
+	;;
+	cmp.eq.or  p63, p3 = r2, r3
+	cmp.eq.and p63, p2 = r0, r1
+	;;
+	cmp.eq.and p63, p2 = r0, r1
+	cmp.eq.and p63, p3 = r2, r3 // no DV here
+	;;
+	cmp.eq.or p63, p2 = r0, r1
+	cmp.eq.or p63, p3 = r2, r3 // no DV here
+	;;
+
+// PSR.ac
+	rum	(1<<3)
+	rum	(1<<3)
+	;;
+
+// PSR.be
+	rum	(1<<1)
+	rum	(1<<1)
+	;;
+	
+// PSR.bn
+	bsw.0			// GAS automatically emits a stop after bsw.n
+	bsw.0			// so this conflict is avoided               
+	;;
+
+// PSR.cpl
+	epc
+	br.ret.sptk	b0
+	;;
+
+// PSR.da (rfi is the only writer)
+// PSR.db (and others)
+	mov	psr.l = r0
+	mov	psr.l = r1
+	;;
+	srlz.d
+
+// PSR.dd (rfi is the only writer)
+	
+// PSR.dfh
+	ssm	(1<<19)
+	ssm	(1<<19)
+	;;
+	srlz.d
+
+// PSR.dfl
+	ssm	(1<<18)
+	ssm	(1<<18)
+	;;
+	srlz.d
+	
+// PSR.di
+	rsm	(1<<22)
+	rsm	(1<<22)
+	;;
+
+// PSR.dt
+	rsm	(1<<17)
+	rsm	(1<<17)
+	;;
+	
+// PSR.ed (rfi is the only writer)
+// PSR.i
+	ssm	(1<<14)
+	ssm	(1<<14)
+	;;
+	
+// PSR.ia (no DV semantics)
+// PSR.ic
+	ssm	(1<<13)
+	ssm	(1<<13)
+	;;
+
+// PSR.id (rfi is the only writer)
+// PSR.is (br.ia and rfi are the only writers)
+// PSR.it (rfi is the only writer)
+// PSR.lp (see PSR.db)
+
+// PSR.mc (rfi is the only writer)
+// PSR.mfh
+	mov	f32 = f33
+	mov	r0 = psr
+	;;
+	ssm	(1<<5)
+	ssm	(1<<5)
+	;;
+	ssm	(1<<5)
+	mov	psr.um = r0
+	;;
+	rum	(1<<5)
+	rum	(1<<5)
+	;;
+	mov	f32 = f33
+	mov	f34 = f35	// no DV here
+	;;
+
+// PSR.mfl
+	mov	f2 = f3
+	mov	r0 = psr
+	;;
+	ssm	(1<<4)
+	ssm	(1<<4)
+	;;
+	ssm	(1<<4)
+	mov	psr.um = r0
+	;;
+	rum	(1<<4)
+	rum	(1<<4)
+	;;
+	mov	f2 = f3
+	mov	f4 = f5	// no DV here
+	;;
+
+// PSR.pk
+	rsm	(1<<15)
+	rsm	(1<<15)
+	;;
+
+// PSR.pp
+	rsm	(1<<21)
+	rsm	(1<<21)
+	;;
+
+// PSR.ri (no DV semantics)
+// PSR.rt (see PSR.db)
+
+// PSR.si
+	rsm	(1<<23)
+	ssm	(1<<23)
+	;;
+
+// PSR.sp
+	ssm	(1<<20)
+	rsm	(1<<20)
+	;;
+	srlz.d
+
+// PSR.ss (rfi is the only writer)
+// PSR.tb (see PSR.db)
+
+// PSR.up
+	rsm	(1<<2)
+	rsm	(1<<2)
+	;;
+	rum	(1<<2)
+	mov	psr.um = r0
+	;;
+
+// RR#
+	mov	rr[r2] = r1
+	mov	rr[r2] = r3
+	;;
+// RSE
+L:	
diff --git a/gas/testsuite/gas/ia64/fixup-dump.pl b/gas/testsuite/gas/ia64/fixup-dump.pl
new file mode 100644
index 0000000..73c218b
--- /dev/null
+++ b/gas/testsuite/gas/ia64/fixup-dump.pl
@@ -0,0 +1,12 @@
+print "# objdump: -d\n";
+print "# name: ia64 $ARGV[0]\n";
+shift;
+
+while (<>) {
+  if (/.*file format.*/) {
+    $_ = ".*: +file format .*\n";
+  } else {
+    s/([][().])/\\$1/g;
+  }
+  print;
+}
diff --git a/gas/testsuite/gas/ia64/ia64.exp b/gas/testsuite/gas/ia64/ia64.exp
new file mode 100644
index 0000000..5c6db40
--- /dev/null
+++ b/gas/testsuite/gas/ia64/ia64.exp
@@ -0,0 +1,38 @@
+#
+# ia64 tests
+#
+proc run_list_test { name opts } {
+    global srcdir subdir
+    set testname "ia64 $name"
+    set file $srcdir/$subdir/$name
+    gas_run ${name}.s $opts ">&dump.out"
+    if { [regexp_diff "dump.out" "${file}.l"] } then {
+	fail $testname
+	verbose "output is [file_contents "dump.out"]" 2
+	return
+    }
+    pass $testname
+}
+
+if [istarget "ia64-*"] then {
+
+    run_dump_test "regs"
+    run_dump_test "opc-a"
+    run_list_test "opc-a-err" ""
+    run_dump_test "opc-b"
+    run_dump_test "opc-f"
+    run_dump_test "opc-i"
+    run_dump_test "opc-m"
+    run_dump_test "opc-x"
+
+    run_list_test "dv-raw-err" ""
+    run_list_test "dv-waw-err" ""
+    run_list_test "dv-war-err" ""
+    run_list_test "dv-entry-err" ""
+    run_list_test "dv-mutex-err" ""
+    run_dump_test "dv-branch"
+    run_dump_test "dv-imply"
+    run_dump_test "dv-mutex"
+    run_dump_test "dv-safe"
+    run_dump_test "dv-srlz"
+}
diff --git a/gas/testsuite/gas/ia64/opc-a-err.l b/gas/testsuite/gas/ia64/opc-a-err.l
new file mode 100644
index 0000000..571a825
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-a-err.l
@@ -0,0 +1,18 @@
+.*: Assembler messages:
+.*:1: Error: Operand 2 of `adds' should be a 14-bit .*
+.*:2: Error: Operand 2 of `adds' should be a 14-bit .*
+.*:4: Error: Operand 2 of `addl' should be a 22-bit .*
+.*:5: Error: Operand 2 of `addl' should be a 22-bit .*
+.*:6: Error: Operand 3 of `addl' should be a general register r0-r3
+.*:8: Error: Operand 2 of `sub' should be .*
+.*:9: Error: Operand 2 of `sub' should be .*
+.*:11: Error: Operand 2 of `and' should be .*
+.*:12: Error: Operand 2 of `and' should be .*
+.*:14: Error: Operand 2 of `or' should be .*
+.*:15: Error: Operand 2 of `or' should be .*
+.*:17: Error: Operand 2 of `xor' should be .*
+.*:18: Error: Operand 2 of `xor' should be .*
+.*:20: Error: Operand 2 of `andcm' should be .*
+.*:21: Error: Operand 2 of `andcm' should be .*
+.*:23: Error: Operand 3 of `cmp4.lt.or' should be r0
+.*:24: Error: Operand 3 of `cmp4.lt.or' should be r0
diff --git a/gas/testsuite/gas/ia64/opc-a-err.s b/gas/testsuite/gas/ia64/opc-a-err.s
new file mode 100644
index 0000000..136fb26
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-a-err.s
@@ -0,0 +1,24 @@
+	adds r25 = -0x2001, r10
+	adds r26 = 0x2000, r10
+
+	addl r37 = -0x200001, r1
+	addl r38 = 0x200000, r1
+	addl r30 = 0, r10
+
+	sub r2 = 128, r3
+	sub r3 = -129, r4
+
+	and r8 = 129, r9
+	and r3 = -129, r4
+	
+	or r8 = 129, r9
+	or r3 = -129, r4
+	
+	xor r8 = 129, r9
+	xor r3 = -129, r4
+	
+	andcm r8 = 129, r9
+	andcm r3 = -129, r4
+
+        cmp4.lt.or p2, p3 = r1, r4
+        cmp4.lt.or p2, p3 = 1, r4
diff --git a/gas/testsuite/gas/ia64/opc-a.d b/gas/testsuite/gas/ia64/opc-a.d
new file mode 100644
index 0000000..132900b
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-a.d
@@ -0,0 +1,290 @@
+# objdump: -d
+# name: ia64 opc-a
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <_start>:
+   0:	00 28 9b cf 00 60 	\[MII\]       add r101=r102,r103
+   6:	80 4e ab 01 40 60 	      \(p01\) add r104=r105,r106
+   c:	cd 6e 07 80       	            add r107=r108,r109,1
+  10:	40 70 bf e1 01 20 	\[MII\] \(p02\) add r110=r111,r112,1
+  16:	40 01 28 00 c2 a0 	            mov r20=r10
+  1c:	12 50 00 84       	      \(p01\) adds r21=1,r10
+  20:	00 b0 fc 15 3f 23 	\[MII\]       adds r22=-1,r10
+  26:	70 01 28 00 46 01 	            adds r23=-8192,r10
+  2c:	f3 57 fc 84       	      \(p02\) adds r24=8191,r10
+  30:	00 f0 00 02 00 24 	\[MII\]       addl r30=0,r1
+  36:	f0 09 04 00 c8 00 	            addl r31=1,r1
+  3c:	f4 ef ff 9f       	      \(p01\) addl r32=-1,r1
+  40:	00 08 01 fa c0 27 	\[MII\]       addl r33=-8192,r1
+  46:	20 fa 07 7e 48 60 	            addl r34=8191,r1
+  4c:	04 08 00 98       	            addl r35=-2097152,r1
+  50:	00 20 fd fb ff 25 	\[MII\]       addl r36=2097151,r1
+  56:	b0 00 28 00 42 80 	            mov r11=r10
+  5c:	41 53 90 84       	            adds r12=4660,r10
+  60:	00 68 d0 02 24 24 	\[MII\]       addl r13=4660,r1
+  66:	e0 28 16 8c 48 80 	            addl r14=74565,r1
+  6c:	32 50 20 80       	            addp4 r20=r3,r10
+  70:	20 a8 04 14 80 21 	\[MII\] \(p01\) addp4 r21=1,r10
+  76:	60 f9 2b 7e 47 a0 	            addp4 r22=-1,r10
+  7c:	6c 3e 17 80       	            sub r101=r102,r103
+  80:	40 70 bf e1 04 20 	\[MII\] \(p02\) sub r110=r111,r112,1
+  86:	80 07 0c 4a 40 20 	            sub r120=0,r3
+  8c:	1f 18 94 80       	            sub r121=1,r3
+  90:	00 d0 ff 07 25 22 	\[MII\]       sub r122=-1,r3
+  96:	b0 07 0c 4a 44 80 	            sub r123=-128,r3
+  9c:	ff 1f 94 80       	            sub r124=127,r3
+  a0:	00 40 24 14 0c e0 	\[MII\]       and r8=r9,r10
+  a6:	b0 00 30 58 44 02 	      \(p03\) and r11=-128,r12
+  ac:	91 50 38 80       	      \(p04\) or r8=r9,r10
+  b0:	00 58 00 18 2e 22 	\[MII\]       or r11=-128,r12
+  b6:	80 48 28 1e 40 60 	            xor r8=r9,r10
+  bc:	01 60 bc 88       	            xor r11=-128,r12
+  c0:	00 40 24 14 0d 20 	\[MII\]       andcm r8=r9,r10
+  c6:	b0 00 30 5a 44 00 	            andcm r11=-128,r12
+  cc:	e1 f9 40 80       	            shladd r8=r30,1,r31
+  d0:	00 48 78 3e 11 20 	\[MII\]       shladd r9=r30,2,r31
+  d6:	a0 f0 7c 24 40 60 	            shladd r10=r30,3,r31
+  dc:	e1 f9 4c 80       	            shladd r11=r30,4,r31
+  e0:	00 40 78 3e 18 20 	\[MII\]       shladdp4 r8=r30,1,r31
+  e6:	90 f0 7c 32 40 40 	            shladdp4 r9=r30,2,r31
+  ec:	e1 f9 68 80       	            shladdp4 r10=r30,3,r31
+  f0:	00 58 78 3e 1b 20 	\[MII\]       shladdp4 r11=r30,4,r31
+  f6:	a0 f0 7c 00 41 60 	            padd1 r10=r30,r31
+  fc:	e1 f9 04 82       	            padd1\.sss r11=r30,r31
+ 100:	00 60 78 3e 83 20 	\[MII\]       padd1\.uus r12=r30,r31
+ 106:	d0 f0 7c 04 41 c0 	            padd1\.uuu r13=r30,r31
+ 10c:	e1 f9 00 83       	            padd2 r14=r30,r31
+ 110:	00 78 78 3e c1 20 	\[MII\]       padd2\.sss r15=r30,r31
+ 116:	00 f1 7c 86 41 20 	            padd2\.uus r16=r30,r31
+ 11c:	e2 f9 08 83       	            padd2\.uuu r17=r30,r31
+ 120:	00 90 78 3e 80 22 	\[MII\]       padd4 r18=r30,r31
+ 126:	a0 f0 7c 08 41 60 	            psub1 r10=r30,r31
+ 12c:	e1 f9 14 82       	            psub1\.sss r11=r30,r31
+ 130:	00 60 78 3e 87 20 	\[MII\]       psub1\.uus r12=r30,r31
+ 136:	d0 f0 7c 0c 41 c0 	            psub1\.uuu r13=r30,r31
+ 13c:	e1 f9 10 83       	            psub2 r14=r30,r31
+ 140:	00 78 78 3e c5 20 	\[MII\]       psub2\.sss r15=r30,r31
+ 146:	00 f1 7c 8e 41 20 	            psub2\.uus r16=r30,r31
+ 14c:	e2 f9 18 83       	            psub2\.uuu r17=r30,r31
+ 150:	00 90 78 3e 84 22 	\[MII\]       psub4 r18=r30,r31
+ 156:	a0 f0 7c 14 41 40 	            pavg1 r10=r30,r31
+ 15c:	e1 f9 2c 82       	            pavg1\.raz r10=r30,r31
+ 160:	00 50 78 3e ca 20 	\[MII\]       pavg2 r10=r30,r31
+ 166:	a0 f0 7c 96 41 40 	            pavg2\.raz r10=r30,r31
+ 16c:	e1 f9 38 82       	            pavgsub1 r10=r30,r31
+ 170:	00 50 78 3e ce 20 	\[MII\]       pavgsub2 r10=r30,r31
+ 176:	a0 f0 7c 48 41 40 	            pcmp1\.eq r10=r30,r31
+ 17c:	e1 f9 90 83       	            pcmp2\.eq r10=r30,r31
+ 180:	00 50 78 3e a4 22 	\[MII\]       pcmp4\.eq r10=r30,r31
+ 186:	a0 f0 7c 4a 41 40 	            pcmp1\.gt r10=r30,r31
+ 18c:	e1 f9 94 83       	            pcmp2\.gt r10=r30,r31
+ 190:	00 50 78 3e a5 22 	\[MII\]       pcmp4\.gt r10=r30,r31
+ 196:	a0 58 30 a0 41 40 	            pshladd2 r10=r11,1,r12
+ 19c:	b1 60 48 83       	            pshladd2 r10=r11,3,r12
+ 1a0:	00 50 2c 18 d8 20 	\[MII\]       pshradd2 r10=r11,1,r12
+ 1a6:	a0 58 30 b2 41 40 	            pshradd2 r10=r11,2,r12
+ 1ac:	30 20 0c e0       	            cmp\.eq p2,p3=r3,r4
+ 1b0:	00 10 0c 08 03 39 	\[MII\]       cmp\.eq p2,p3=3,r4
+ 1b6:	30 18 10 04 70 60 	            cmp\.eq p3,p2=r3,r4
+ 1bc:	30 20 08 e4       	            cmp\.eq p3,p2=3,r4
+ 1c0:	00 10 0c 08 03 30 	\[MII\]       cmp\.lt p2,p3=r3,r4
+ 1c6:	20 18 10 06 62 60 	            cmp\.lt p2,p3=3,r4
+ 1cc:	40 18 08 c0       	            cmp\.lt p3,p2=r4,r3
+ 1d0:	00 10 08 08 03 31 	\[MII\]       cmp\.lt p2,p3=2,r4
+ 1d6:	20 20 0c 06 60 60 	            cmp\.lt p2,p3=r4,r3
+ 1dc:	20 20 08 c4       	            cmp\.lt p3,p2=2,r4
+ 1e0:	00 18 0c 08 02 30 	\[MII\]       cmp\.lt p3,p2=r3,r4
+ 1e6:	30 18 10 04 62 40 	            cmp\.lt p3,p2=3,r4
+ 1ec:	30 20 0c d0       	            cmp\.ltu p2,p3=r3,r4
+ 1f0:	00 10 0c 08 03 35 	\[MII\]       cmp\.ltu p2,p3=3,r4
+ 1f6:	30 20 0c 04 68 40 	            cmp\.ltu p3,p2=r4,r3
+ 1fc:	20 20 0c d4       	            cmp\.ltu p2,p3=2,r4
+ 200:	00 10 10 06 03 34 	\[MII\]       cmp\.ltu p2,p3=r4,r3
+ 206:	30 10 10 04 6a 60 	            cmp\.ltu p3,p2=2,r4
+ 20c:	30 20 08 d0       	            cmp\.ltu p3,p2=r3,r4
+ 210:	00 18 0c 08 02 35 	\[MII\]       cmp\.ltu p3,p2=3,r4
+ 216:	20 1c 10 06 70 40 	            cmp\.eq\.unc p2,p3=r3,r4
+ 21c:	38 20 0c e4       	            cmp\.eq\.unc p2,p3=3,r4
+ 220:	00 18 0e 08 02 38 	\[MII\]       cmp\.eq\.unc p3,p2=r3,r4
+ 226:	30 1c 10 04 72 40 	            cmp\.eq\.unc p3,p2=3,r4
+ 22c:	38 20 0c c0       	            cmp\.lt\.unc p2,p3=r3,r4
+ 230:	00 10 0e 08 03 31 	\[MII\]       cmp\.lt\.unc p2,p3=3,r4
+ 236:	30 24 0c 04 60 40 	            cmp\.lt\.unc p3,p2=r4,r3
+ 23c:	28 20 0c c4       	            cmp\.lt\.unc p2,p3=2,r4
+ 240:	00 10 12 06 03 30 	\[MII\]       cmp\.lt\.unc p2,p3=r4,r3
+ 246:	30 14 10 04 62 60 	            cmp\.lt\.unc p3,p2=2,r4
+ 24c:	38 20 08 c0       	            cmp\.lt\.unc p3,p2=r3,r4
+ 250:	00 18 0e 08 02 31 	\[MII\]       cmp\.lt\.unc p3,p2=3,r4
+ 256:	20 1c 10 06 68 40 	            cmp\.ltu\.unc p2,p3=r3,r4
+ 25c:	38 20 0c d4       	            cmp\.ltu\.unc p2,p3=3,r4
+ 260:	00 18 12 06 02 34 	\[MII\]       cmp\.ltu\.unc p3,p2=r4,r3
+ 266:	20 14 10 06 6a 40 	            cmp\.ltu\.unc p2,p3=2,r4
+ 26c:	48 18 0c d0       	            cmp\.ltu\.unc p2,p3=r4,r3
+ 270:	00 18 0a 08 02 35 	\[MII\]       cmp\.ltu\.unc p3,p2=2,r4
+ 276:	30 1c 10 04 68 60 	            cmp\.ltu\.unc p3,p2=r3,r4
+ 27c:	38 20 08 d4       	            cmp\.ltu\.unc p3,p2=3,r4
+ 280:	00 10 0c 08 43 30 	\[MII\]       cmp\.eq\.and p2,p3=r3,r4
+ 286:	20 18 10 86 62 40 	            cmp\.eq\.and p2,p3=3,r4
+ 28c:	30 20 0c d1       	            cmp\.eq\.or p2,p3=r3,r4
+ 290:	00 10 0c 08 43 35 	\[MII\]       cmp\.eq\.or p2,p3=3,r4
+ 296:	20 18 10 86 70 40 	            cmp\.eq\.or\.andcm p2,p3=r3,r4
+ 29c:	30 20 0c e5       	            cmp\.eq\.or\.andcm p2,p3=3,r4
+ 2a0:	00 10 0e 08 43 34 	\[MII\]       cmp\.ne\.or p2,p3=r3,r4
+ 2a6:	20 1c 10 86 6a 40 	            cmp\.ne\.or p2,p3=3,r4
+ 2ac:	38 20 0c c1       	            cmp\.ne\.and p2,p3=r3,r4
+ 2b0:	00 10 0e 08 43 31 	\[MII\]       cmp\.ne\.and p2,p3=3,r4
+ 2b6:	30 1c 10 84 70 60 	            cmp\.ne\.or\.andcm p3,p2=r3,r4
+ 2bc:	38 20 08 e5       	            cmp\.ne\.or\.andcm p3,p2=3,r4
+ 2c0:	00 10 0e 08 43 30 	\[MII\]       cmp\.ne\.and p2,p3=r3,r4
+ 2c6:	20 1c 10 86 62 40 	            cmp\.ne\.and p2,p3=3,r4
+ 2cc:	38 20 0c d1       	            cmp\.ne\.or p2,p3=r3,r4
+ 2d0:	00 10 0e 08 43 35 	\[MII\]       cmp\.ne\.or p2,p3=3,r4
+ 2d6:	20 1c 10 86 70 40 	            cmp\.ne\.or\.andcm p2,p3=r3,r4
+ 2dc:	38 20 0c e5       	            cmp\.ne\.or\.andcm p2,p3=3,r4
+ 2e0:	00 10 0c 08 43 34 	\[MII\]       cmp\.eq\.or p2,p3=r3,r4
+ 2e6:	20 18 10 86 6a 40 	            cmp\.eq\.or p2,p3=3,r4
+ 2ec:	30 20 0c c1       	            cmp\.eq\.and p2,p3=r3,r4
+ 2f0:	00 10 0c 08 43 31 	\[MII\]       cmp\.eq\.and p2,p3=3,r4
+ 2f6:	30 18 10 84 70 60 	            cmp\.eq\.or\.andcm p3,p2=r3,r4
+ 2fc:	30 20 08 e5       	            cmp\.eq\.or\.andcm p3,p2=3,r4
+ 300:	00 10 00 08 43 30 	\[MII\]       cmp\.eq\.and p2,p3=r0,r4
+ 306:	20 00 10 86 68 40 	            cmp\.eq\.or p2,p3=r0,r4
+ 30c:	00 20 0c e1       	            cmp\.eq\.or\.andcm p2,p3=r0,r4
+ 310:	00 10 02 08 43 34 	\[MII\]       cmp\.ne\.or p2,p3=r0,r4
+ 316:	20 04 10 86 60 60 	            cmp\.ne\.and p2,p3=r0,r4
+ 31c:	08 20 08 e1       	            cmp\.ne\.or\.andcm p3,p2=r0,r4
+ 320:	00 10 02 08 43 30 	\[MII\]       cmp\.ne\.and p2,p3=r0,r4
+ 326:	20 04 10 86 68 40 	            cmp\.ne\.or p2,p3=r0,r4
+ 32c:	08 20 0c e1       	            cmp\.ne\.or\.andcm p2,p3=r0,r4
+ 330:	00 10 00 08 43 34 	\[MII\]       cmp\.eq\.or p2,p3=r0,r4
+ 336:	20 00 10 86 60 60 	            cmp\.eq\.and p2,p3=r0,r4
+ 33c:	00 20 08 e1       	            cmp\.eq\.or\.andcm p3,p2=r0,r4
+ 340:	00 10 02 08 43 32 	\[MII\]       cmp\.lt\.and p2,p3=r0,r4
+ 346:	20 04 10 86 6c 40 	            cmp\.lt\.or p2,p3=r0,r4
+ 34c:	08 20 0c e9       	            cmp\.lt\.or\.andcm p2,p3=r0,r4
+ 350:	00 10 00 08 43 36 	\[MII\]       cmp\.ge\.or p2,p3=r0,r4
+ 356:	20 00 10 86 64 60 	            cmp\.ge\.and p2,p3=r0,r4
+ 35c:	00 20 08 e9       	            cmp\.ge\.or\.andcm p3,p2=r0,r4
+ 360:	00 10 02 08 03 32 	\[MII\]       cmp\.le\.and p2,p3=r0,r4
+ 366:	20 04 10 06 6c 40 	            cmp\.le\.or p2,p3=r0,r4
+ 36c:	08 20 0c e8       	            cmp\.le\.or\.andcm p2,p3=r0,r4
+ 370:	00 10 00 08 03 36 	\[MII\]       cmp\.gt\.or p2,p3=r0,r4
+ 376:	20 00 10 06 64 60 	            cmp\.gt\.and p2,p3=r0,r4
+ 37c:	00 20 08 e8       	            cmp\.gt\.or\.andcm p3,p2=r0,r4
+ 380:	00 10 00 08 03 32 	\[MII\]       cmp\.gt\.and p2,p3=r0,r4
+ 386:	20 00 10 06 6c 40 	            cmp\.gt\.or p2,p3=r0,r4
+ 38c:	00 20 0c e8       	            cmp\.gt\.or\.andcm p2,p3=r0,r4
+ 390:	00 10 02 08 03 36 	\[MII\]       cmp\.le\.or p2,p3=r0,r4
+ 396:	20 04 10 06 64 60 	            cmp\.le\.and p2,p3=r0,r4
+ 39c:	08 20 08 e8       	            cmp\.le\.or\.andcm p3,p2=r0,r4
+ 3a0:	00 10 00 08 43 32 	\[MII\]       cmp\.ge\.and p2,p3=r0,r4
+ 3a6:	20 00 10 86 6c 40 	            cmp\.ge\.or p2,p3=r0,r4
+ 3ac:	00 20 0c e9       	            cmp\.ge\.or\.andcm p2,p3=r0,r4
+ 3b0:	00 10 02 08 43 36 	\[MII\]       cmp\.lt\.or p2,p3=r0,r4
+ 3b6:	20 04 10 86 64 60 	            cmp\.lt\.and p2,p3=r0,r4
+ 3bc:	08 20 08 e9       	            cmp\.lt\.or\.andcm p3,p2=r0,r4
+ 3c0:	00 10 0c 08 83 38 	\[MII\]       cmp4\.eq p2,p3=r3,r4
+ 3c6:	20 18 10 06 73 60 	            cmp4\.eq p2,p3=3,r4
+ 3cc:	30 20 08 e2       	            cmp4\.eq p3,p2=r3,r4
+ 3d0:	00 18 0c 08 82 39 	\[MII\]       cmp4\.eq p3,p2=3,r4
+ 3d6:	20 18 10 06 61 40 	            cmp4\.lt p2,p3=r3,r4
+ 3dc:	30 20 0c c6       	            cmp4\.lt p2,p3=3,r4
+ 3e0:	00 18 10 06 82 30 	\[MII\]       cmp4\.lt p3,p2=r4,r3
+ 3e6:	20 10 10 06 63 40 	            cmp4\.lt p2,p3=2,r4
+ 3ec:	40 18 0c c2       	            cmp4\.lt p2,p3=r4,r3
+ 3f0:	00 18 08 08 82 31 	\[MII\]       cmp4\.lt p3,p2=2,r4
+ 3f6:	30 18 10 04 61 60 	            cmp4\.lt p3,p2=r3,r4
+ 3fc:	30 20 08 c6       	            cmp4\.lt p3,p2=3,r4
+ 400:	00 10 0c 08 83 34 	\[MII\]       cmp4\.ltu p2,p3=r3,r4
+ 406:	20 18 10 06 6b 60 	            cmp4\.ltu p2,p3=3,r4
+ 40c:	40 18 08 d2       	            cmp4\.ltu p3,p2=r4,r3
+ 410:	00 10 08 08 83 35 	\[MII\]       cmp4\.ltu p2,p3=2,r4
+ 416:	20 20 0c 06 69 60 	            cmp4\.ltu p2,p3=r4,r3
+ 41c:	20 20 08 d6       	            cmp4\.ltu p3,p2=2,r4
+ 420:	00 18 0c 08 82 34 	\[MII\]       cmp4\.ltu p3,p2=r3,r4
+ 426:	30 18 10 04 6b 40 	            cmp4\.ltu p3,p2=3,r4
+ 42c:	38 20 0c e2       	            cmp4\.eq\.unc p2,p3=r3,r4
+ 430:	00 10 0e 08 83 39 	\[MII\]       cmp4\.eq\.unc p2,p3=3,r4
+ 436:	30 1c 10 04 71 60 	            cmp4\.eq\.unc p3,p2=r3,r4
+ 43c:	38 20 08 e6       	            cmp4\.eq\.unc p3,p2=3,r4
+ 440:	00 10 0e 08 83 30 	\[MII\]       cmp4\.lt\.unc p2,p3=r3,r4
+ 446:	20 1c 10 06 63 60 	            cmp4\.lt\.unc p2,p3=3,r4
+ 44c:	48 18 08 c2       	            cmp4\.lt\.unc p3,p2=r4,r3
+ 450:	00 10 0a 08 83 31 	\[MII\]       cmp4\.lt\.unc p2,p3=2,r4
+ 456:	20 24 0c 06 61 60 	            cmp4\.lt\.unc p2,p3=r4,r3
+ 45c:	28 20 08 c6       	            cmp4\.lt\.unc p3,p2=2,r4
+ 460:	00 18 0e 08 82 30 	\[MII\]       cmp4\.lt\.unc p3,p2=r3,r4
+ 466:	30 1c 10 04 63 40 	            cmp4\.lt\.unc p3,p2=3,r4
+ 46c:	38 20 0c d2       	            cmp4\.ltu\.unc p2,p3=r3,r4
+ 470:	00 10 0e 08 83 35 	\[MII\]       cmp4\.ltu\.unc p2,p3=3,r4
+ 476:	30 24 0c 04 69 40 	            cmp4\.ltu\.unc p3,p2=r4,r3
+ 47c:	28 20 0c d6       	            cmp4\.ltu\.unc p2,p3=2,r4
+ 480:	00 10 12 06 83 34 	\[MII\]       cmp4\.ltu\.unc p2,p3=r4,r3
+ 486:	30 14 10 04 6b 60 	            cmp4\.ltu\.unc p3,p2=2,r4
+ 48c:	38 20 08 d2       	            cmp4\.ltu\.unc p3,p2=r3,r4
+ 490:	00 18 0e 08 82 35 	\[MII\]       cmp4\.ltu\.unc p3,p2=3,r4
+ 496:	20 18 10 86 61 40 	            cmp4\.eq\.and p2,p3=r3,r4
+ 49c:	30 20 0c c7       	            cmp4\.eq\.and p2,p3=3,r4
+ 4a0:	00 10 0c 08 c3 34 	\[MII\]       cmp4\.eq\.or p2,p3=r3,r4
+ 4a6:	20 18 10 86 6b 40 	            cmp4\.eq\.or p2,p3=3,r4
+ 4ac:	30 20 0c e3       	            cmp4\.eq\.or\.andcm p2,p3=r3,r4
+ 4b0:	00 10 0c 08 c3 39 	\[MII\]       cmp4\.eq\.or\.andcm p2,p3=3,r4
+ 4b6:	20 1c 10 86 69 40 	            cmp4\.ne\.or p2,p3=r3,r4
+ 4bc:	38 20 0c d7       	            cmp4\.ne\.or p2,p3=3,r4
+ 4c0:	00 10 0e 08 c3 30 	\[MII\]       cmp4\.ne\.and p2,p3=r3,r4
+ 4c6:	20 1c 10 86 63 60 	            cmp4\.ne\.and p2,p3=3,r4
+ 4cc:	38 20 08 e3       	            cmp4\.ne\.or\.andcm p3,p2=r3,r4
+ 4d0:	00 18 0e 08 c2 39 	\[MII\]       cmp4\.ne\.or\.andcm p3,p2=3,r4
+ 4d6:	20 1c 10 86 61 40 	            cmp4\.ne\.and p2,p3=r3,r4
+ 4dc:	38 20 0c c7       	            cmp4\.ne\.and p2,p3=3,r4
+ 4e0:	00 10 0e 08 c3 34 	\[MII\]       cmp4\.ne\.or p2,p3=r3,r4
+ 4e6:	20 1c 10 86 6b 40 	            cmp4\.ne\.or p2,p3=3,r4
+ 4ec:	38 20 0c e3       	            cmp4\.ne\.or\.andcm p2,p3=r3,r4
+ 4f0:	00 10 0e 08 c3 39 	\[MII\]       cmp4\.ne\.or\.andcm p2,p3=3,r4
+ 4f6:	20 18 10 86 69 40 	            cmp4\.eq\.or p2,p3=r3,r4
+ 4fc:	30 20 0c d7       	            cmp4\.eq\.or p2,p3=3,r4
+ 500:	00 10 0c 08 c3 30 	\[MII\]       cmp4\.eq\.and p2,p3=r3,r4
+ 506:	20 18 10 86 63 60 	            cmp4\.eq\.and p2,p3=3,r4
+ 50c:	30 20 08 e3       	            cmp4\.eq\.or\.andcm p3,p2=r3,r4
+ 510:	00 18 0c 08 c2 39 	\[MII\]       cmp4\.eq\.or\.andcm p3,p2=3,r4
+ 516:	20 00 10 86 61 40 	            cmp4\.eq\.and p2,p3=r0,r4
+ 51c:	00 20 0c d3       	            cmp4\.eq\.or p2,p3=r0,r4
+ 520:	00 10 00 08 c3 38 	\[MII\]       cmp4\.eq\.or\.andcm p2,p3=r0,r4
+ 526:	20 04 10 86 69 40 	            cmp4\.ne\.or p2,p3=r0,r4
+ 52c:	08 20 0c c3       	            cmp4\.ne\.and p2,p3=r0,r4
+ 530:	00 18 02 08 c2 38 	\[MII\]       cmp4\.ne\.or\.andcm p3,p2=r0,r4
+ 536:	20 04 10 86 61 40 	            cmp4\.ne\.and p2,p3=r0,r4
+ 53c:	08 20 0c d3       	            cmp4\.ne\.or p2,p3=r0,r4
+ 540:	00 10 02 08 c3 38 	\[MII\]       cmp4\.ne\.or\.andcm p2,p3=r0,r4
+ 546:	20 00 10 86 69 40 	            cmp4\.eq\.or p2,p3=r0,r4
+ 54c:	00 20 0c c3       	            cmp4\.eq\.and p2,p3=r0,r4
+ 550:	00 18 00 08 c2 38 	\[MII\]       cmp4\.eq\.or\.andcm p3,p2=r0,r4
+ 556:	20 04 10 86 65 40 	            cmp4\.lt\.and p2,p3=r0,r4
+ 55c:	08 20 0c db       	            cmp4\.lt\.or p2,p3=r0,r4
+ 560:	00 10 02 08 c3 3a 	\[MII\]       cmp4\.lt\.or\.andcm p2,p3=r0,r4
+ 566:	20 00 10 86 6d 40 	            cmp4\.ge\.or p2,p3=r0,r4
+ 56c:	00 20 0c cb       	            cmp4\.ge\.and p2,p3=r0,r4
+ 570:	00 18 00 08 c2 3a 	\[MII\]       cmp4\.ge\.or\.andcm p3,p2=r0,r4
+ 576:	20 04 10 06 65 40 	            cmp4\.le\.and p2,p3=r0,r4
+ 57c:	08 20 0c da       	            cmp4\.le\.or p2,p3=r0,r4
+ 580:	00 10 02 08 83 3a 	\[MII\]       cmp4\.le\.or\.andcm p2,p3=r0,r4
+ 586:	20 00 10 06 6d 40 	            cmp4\.gt\.or p2,p3=r0,r4
+ 58c:	00 20 0c ca       	            cmp4\.gt\.and p2,p3=r0,r4
+ 590:	00 18 00 08 82 3a 	\[MII\]       cmp4\.gt\.or\.andcm p3,p2=r0,r4
+ 596:	20 00 10 06 65 40 	            cmp4\.gt\.and p2,p3=r0,r4
+ 59c:	00 20 0c da       	            cmp4\.gt\.or p2,p3=r0,r4
+ 5a0:	00 10 00 08 83 3a 	\[MII\]       cmp4\.gt\.or\.andcm p2,p3=r0,r4
+ 5a6:	20 04 10 06 6d 40 	            cmp4\.le\.or p2,p3=r0,r4
+ 5ac:	08 20 0c ca       	            cmp4\.le\.and p2,p3=r0,r4
+ 5b0:	00 18 02 08 82 3a 	\[MII\]       cmp4\.le\.or\.andcm p3,p2=r0,r4
+ 5b6:	20 00 10 86 65 40 	            cmp4\.ge\.and p2,p3=r0,r4
+ 5bc:	00 20 0c db       	            cmp4\.ge\.or p2,p3=r0,r4
+ 5c0:	00 10 00 08 c3 3a 	\[MII\]       cmp4\.ge\.or\.andcm p2,p3=r0,r4
+ 5c6:	20 04 10 86 6d 40 	            cmp4\.lt\.or p2,p3=r0,r4
+ 5cc:	08 20 0c cb       	            cmp4\.lt\.and p2,p3=r0,r4
+ 5d0:	01 18 02 08 c2 3a 	\[MII\]       cmp4\.lt\.or\.andcm p3,p2=r0,r4
+ 5d6:	00 00 00 02 00 00 	            nop\.i 0x0
+ 5dc:	00 00 04 00       	            nop\.i 0x0;;
diff --git a/gas/testsuite/gas/ia64/opc-a.pl b/gas/testsuite/gas/ia64/opc-a.pl
new file mode 100644
index 0000000..afddf06
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-a.pl
@@ -0,0 +1,141 @@
+$AT = '@';
+print <<END
+.text
+	.type _start,${AT}function
+_start:
+
+	add r101 = r102, r103
+(p1)	add r104 = r105, r106
+	add r107 = r108, r109, 1
+(p2)	add r110 = r111, r112, 1
+
+	adds r20 = 0, r10
+(p1)	adds r21 = 1, r10
+	adds r22 = -1, r10
+	adds r23 = -0x2000, r10
+(p2)	adds r24 = 0x1FFF, r10
+
+	addl r30 = 0, r1
+	addl r31 = 1, r1
+(p1)	addl r32 = -1, r1
+	addl r33 = -0x2000, r1
+	addl r34 = 0x1FFF, r1
+	addl r35 = -0x200000, r1
+	addl r36 = 0x1FFFFF, r1
+
+	add r11 = 0, r10
+	add r12 = 0x1234, r10
+	add r13 = 0x1234, r1
+	add r14 = 0x12345, r1
+
+	addp4 r20 = r3, r10
+(p1)	addp4 r21 = 1, r10
+	addp4 r22 = -1, r10
+
+	sub r101 = r102, r103
+(p2)	sub r110 = r111, r112, 1
+	sub r120 = 0, r3
+	sub r121 = 1, r3
+	sub r122 = -1, r3
+	sub r123 = -128, r3
+	sub r124 = 127, r3
+
+	and r8 = r9, r10
+(p3)	and r11 = -128, r12
+
+(p4)	or r8 = r9, r10
+	or r11 = -128, r12
+
+	xor r8 = r9, r10
+	xor r11 = -128, r12
+
+	andcm r8 = r9, r10
+	andcm r11 = -128, r12
+
+	shladd r8 = r30, 1, r31
+	shladd r9 = r30, 2, r31
+	shladd r10 = r30, 3, r31
+	shladd r11 = r30, 4, r31
+
+	shladdp4 r8 = r30, 1, r31
+	shladdp4 r9 = r30, 2, r31
+	shladdp4 r10 = r30, 3, r31
+	shladdp4 r11 = r30, 4, r31
+
+	padd1 r10 = r30, r31
+	padd1.sss r11 = r30, r31
+	padd1.uus r12 = r30, r31
+	padd1.uuu r13 = r30, r31
+	padd2 r14 = r30, r31
+	padd2.sss r15 = r30, r31
+	padd2.uus r16 = r30, r31
+	padd2.uuu r17 = r30, r31
+	padd4 r18 = r30, r31
+
+	psub1 r10 = r30, r31
+	psub1.sss r11 = r30, r31
+	psub1.uus r12 = r30, r31
+	psub1.uuu r13 = r30, r31
+	psub2 r14 = r30, r31
+	psub2.sss r15 = r30, r31
+	psub2.uus r16 = r30, r31
+	psub2.uuu r17 = r30, r31
+	psub4 r18 = r30, r31
+
+	pavg1 r10 = r30, r31
+	pavg1.raz r10 = r30, r31
+	pavg2 r10 = r30, r31
+	pavg2.raz r10 = r30, r31
+
+	pavgsub1 r10 = r30, r31
+	pavgsub2 r10 = r30, r31
+
+	pcmp1.eq r10 = r30, r31
+	pcmp2.eq r10 = r30, r31
+	pcmp4.eq r10 = r30, r31
+	pcmp1.gt r10 = r30, r31
+	pcmp2.gt r10 = r30, r31
+	pcmp4.gt r10 = r30, r31
+
+	pshladd2 r10 = r11, 1, r12
+	pshladd2 r10 = r11, 3, r12
+
+	pshradd2 r10 = r11, 1, r12
+	pshradd2 r10 = r11, 2, r12
+
+END
+;
+
+@cmp2 = ( ".eq", ".ne" );
+@cmp6 = ( @cmp2, ".lt", ".le", ".gt", ".ge" );
+@cmp10 = ( @cmp6, ".ltu", ".leu", ".gtu", ".geu" );
+
+@ctype = ( ".and", ".or", ".or.andcm", ".orcm", ".andcm", ".and.orcm" );
+
+foreach $C ( "cmp", "cmp4" ) {
+  foreach $u ( "", ".unc" ) {
+    foreach $i (@cmp10) {
+      print "\t${C}${i}${u} p2, p3 = r3, r4\n";
+      print "\t${C}${i}${u} p2, p3 = 3, r4\n";
+    }
+    print "\n";
+  }
+  
+  foreach $i (@cmp2) {
+    foreach $c (@ctype) {
+      print "\t${C}${i}${c} p2, p3 = r3, r4\n";
+      print "\t${C}${i}${c} p2, p3 = 3, r4\n";
+    }
+    print "\n";
+  }
+      
+  foreach $i (@cmp6) {
+    foreach $c (@ctype) {
+      print "\t${C}${i}${c} p2, p3 = r0, r4\n";
+    }
+    print "\n";
+  }
+}
+
+# Pad to a bundle boundary with known nops.
+print "nop.i 0; nop.i 0\n";
diff --git a/gas/testsuite/gas/ia64/opc-a.s b/gas/testsuite/gas/ia64/opc-a.s
new file mode 100644
index 0000000..0074d9e
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-a.s
@@ -0,0 +1,324 @@
+.text
+	.type _start,@function
+_start:
+
+	add r101 = r102, r103
+(p1)	add r104 = r105, r106
+	add r107 = r108, r109, 1
+(p2)	add r110 = r111, r112, 1
+
+	adds r20 = 0, r10
+(p1)	adds r21 = 1, r10
+	adds r22 = -1, r10
+	adds r23 = -0x2000, r10
+(p2)	adds r24 = 0x1FFF, r10
+
+	addl r30 = 0, r1
+	addl r31 = 1, r1
+(p1)	addl r32 = -1, r1
+	addl r33 = -0x2000, r1
+	addl r34 = 0x1FFF, r1
+	addl r35 = -0x200000, r1
+	addl r36 = 0x1FFFFF, r1
+
+	add r11 = 0, r10
+	add r12 = 0x1234, r10
+	add r13 = 0x1234, r1
+	add r14 = 0x12345, r1
+
+	addp4 r20 = r3, r10
+(p1)	addp4 r21 = 1, r10
+	addp4 r22 = -1, r10
+
+	sub r101 = r102, r103
+(p2)	sub r110 = r111, r112, 1
+	sub r120 = 0, r3
+	sub r121 = 1, r3
+	sub r122 = -1, r3
+	sub r123 = -128, r3
+	sub r124 = 127, r3
+
+	and r8 = r9, r10
+(p3)	and r11 = -128, r12
+
+(p4)	or r8 = r9, r10
+	or r11 = -128, r12
+
+	xor r8 = r9, r10
+	xor r11 = -128, r12
+
+	andcm r8 = r9, r10
+	andcm r11 = -128, r12
+
+	shladd r8 = r30, 1, r31
+	shladd r9 = r30, 2, r31
+	shladd r10 = r30, 3, r31
+	shladd r11 = r30, 4, r31
+
+	shladdp4 r8 = r30, 1, r31
+	shladdp4 r9 = r30, 2, r31
+	shladdp4 r10 = r30, 3, r31
+	shladdp4 r11 = r30, 4, r31
+
+	padd1 r10 = r30, r31
+	padd1.sss r11 = r30, r31
+	padd1.uus r12 = r30, r31
+	padd1.uuu r13 = r30, r31
+	padd2 r14 = r30, r31
+	padd2.sss r15 = r30, r31
+	padd2.uus r16 = r30, r31
+	padd2.uuu r17 = r30, r31
+	padd4 r18 = r30, r31
+
+	psub1 r10 = r30, r31
+	psub1.sss r11 = r30, r31
+	psub1.uus r12 = r30, r31
+	psub1.uuu r13 = r30, r31
+	psub2 r14 = r30, r31
+	psub2.sss r15 = r30, r31
+	psub2.uus r16 = r30, r31
+	psub2.uuu r17 = r30, r31
+	psub4 r18 = r30, r31
+
+	pavg1 r10 = r30, r31
+	pavg1.raz r10 = r30, r31
+	pavg2 r10 = r30, r31
+	pavg2.raz r10 = r30, r31
+
+	pavgsub1 r10 = r30, r31
+	pavgsub2 r10 = r30, r31
+
+	pcmp1.eq r10 = r30, r31
+	pcmp2.eq r10 = r30, r31
+	pcmp4.eq r10 = r30, r31
+	pcmp1.gt r10 = r30, r31
+	pcmp2.gt r10 = r30, r31
+	pcmp4.gt r10 = r30, r31
+
+	pshladd2 r10 = r11, 1, r12
+	pshladd2 r10 = r11, 3, r12
+
+	pshradd2 r10 = r11, 1, r12
+	pshradd2 r10 = r11, 2, r12
+
+	cmp.eq p2, p3 = r3, r4
+	cmp.eq p2, p3 = 3, r4
+	cmp.ne p2, p3 = r3, r4
+	cmp.ne p2, p3 = 3, r4
+	cmp.lt p2, p3 = r3, r4
+	cmp.lt p2, p3 = 3, r4
+	cmp.le p2, p3 = r3, r4
+	cmp.le p2, p3 = 3, r4
+	cmp.gt p2, p3 = r3, r4
+	cmp.gt p2, p3 = 3, r4
+	cmp.ge p2, p3 = r3, r4
+	cmp.ge p2, p3 = 3, r4
+	cmp.ltu p2, p3 = r3, r4
+	cmp.ltu p2, p3 = 3, r4
+	cmp.leu p2, p3 = r3, r4
+	cmp.leu p2, p3 = 3, r4
+	cmp.gtu p2, p3 = r3, r4
+	cmp.gtu p2, p3 = 3, r4
+	cmp.geu p2, p3 = r3, r4
+	cmp.geu p2, p3 = 3, r4
+
+	cmp.eq.unc p2, p3 = r3, r4
+	cmp.eq.unc p2, p3 = 3, r4
+	cmp.ne.unc p2, p3 = r3, r4
+	cmp.ne.unc p2, p3 = 3, r4
+	cmp.lt.unc p2, p3 = r3, r4
+	cmp.lt.unc p2, p3 = 3, r4
+	cmp.le.unc p2, p3 = r3, r4
+	cmp.le.unc p2, p3 = 3, r4
+	cmp.gt.unc p2, p3 = r3, r4
+	cmp.gt.unc p2, p3 = 3, r4
+	cmp.ge.unc p2, p3 = r3, r4
+	cmp.ge.unc p2, p3 = 3, r4
+	cmp.ltu.unc p2, p3 = r3, r4
+	cmp.ltu.unc p2, p3 = 3, r4
+	cmp.leu.unc p2, p3 = r3, r4
+	cmp.leu.unc p2, p3 = 3, r4
+	cmp.gtu.unc p2, p3 = r3, r4
+	cmp.gtu.unc p2, p3 = 3, r4
+	cmp.geu.unc p2, p3 = r3, r4
+	cmp.geu.unc p2, p3 = 3, r4
+
+	cmp.eq.and p2, p3 = r3, r4
+	cmp.eq.and p2, p3 = 3, r4
+	cmp.eq.or p2, p3 = r3, r4
+	cmp.eq.or p2, p3 = 3, r4
+	cmp.eq.or.andcm p2, p3 = r3, r4
+	cmp.eq.or.andcm p2, p3 = 3, r4
+	cmp.eq.orcm p2, p3 = r3, r4
+	cmp.eq.orcm p2, p3 = 3, r4
+	cmp.eq.andcm p2, p3 = r3, r4
+	cmp.eq.andcm p2, p3 = 3, r4
+	cmp.eq.and.orcm p2, p3 = r3, r4
+	cmp.eq.and.orcm p2, p3 = 3, r4
+
+	cmp.ne.and p2, p3 = r3, r4
+	cmp.ne.and p2, p3 = 3, r4
+	cmp.ne.or p2, p3 = r3, r4
+	cmp.ne.or p2, p3 = 3, r4
+	cmp.ne.or.andcm p2, p3 = r3, r4
+	cmp.ne.or.andcm p2, p3 = 3, r4
+	cmp.ne.orcm p2, p3 = r3, r4
+	cmp.ne.orcm p2, p3 = 3, r4
+	cmp.ne.andcm p2, p3 = r3, r4
+	cmp.ne.andcm p2, p3 = 3, r4
+	cmp.ne.and.orcm p2, p3 = r3, r4
+	cmp.ne.and.orcm p2, p3 = 3, r4
+
+	cmp.eq.and p2, p3 = r0, r4
+	cmp.eq.or p2, p3 = r0, r4
+	cmp.eq.or.andcm p2, p3 = r0, r4
+	cmp.eq.orcm p2, p3 = r0, r4
+	cmp.eq.andcm p2, p3 = r0, r4
+	cmp.eq.and.orcm p2, p3 = r0, r4
+
+	cmp.ne.and p2, p3 = r0, r4
+	cmp.ne.or p2, p3 = r0, r4
+	cmp.ne.or.andcm p2, p3 = r0, r4
+	cmp.ne.orcm p2, p3 = r0, r4
+	cmp.ne.andcm p2, p3 = r0, r4
+	cmp.ne.and.orcm p2, p3 = r0, r4
+
+	cmp.lt.and p2, p3 = r0, r4
+	cmp.lt.or p2, p3 = r0, r4
+	cmp.lt.or.andcm p2, p3 = r0, r4
+	cmp.lt.orcm p2, p3 = r0, r4
+	cmp.lt.andcm p2, p3 = r0, r4
+	cmp.lt.and.orcm p2, p3 = r0, r4
+
+	cmp.le.and p2, p3 = r0, r4
+	cmp.le.or p2, p3 = r0, r4
+	cmp.le.or.andcm p2, p3 = r0, r4
+	cmp.le.orcm p2, p3 = r0, r4
+	cmp.le.andcm p2, p3 = r0, r4
+	cmp.le.and.orcm p2, p3 = r0, r4
+
+	cmp.gt.and p2, p3 = r0, r4
+	cmp.gt.or p2, p3 = r0, r4
+	cmp.gt.or.andcm p2, p3 = r0, r4
+	cmp.gt.orcm p2, p3 = r0, r4
+	cmp.gt.andcm p2, p3 = r0, r4
+	cmp.gt.and.orcm p2, p3 = r0, r4
+
+	cmp.ge.and p2, p3 = r0, r4
+	cmp.ge.or p2, p3 = r0, r4
+	cmp.ge.or.andcm p2, p3 = r0, r4
+	cmp.ge.orcm p2, p3 = r0, r4
+	cmp.ge.andcm p2, p3 = r0, r4
+	cmp.ge.and.orcm p2, p3 = r0, r4
+
+	cmp4.eq p2, p3 = r3, r4
+	cmp4.eq p2, p3 = 3, r4
+	cmp4.ne p2, p3 = r3, r4
+	cmp4.ne p2, p3 = 3, r4
+	cmp4.lt p2, p3 = r3, r4
+	cmp4.lt p2, p3 = 3, r4
+	cmp4.le p2, p3 = r3, r4
+	cmp4.le p2, p3 = 3, r4
+	cmp4.gt p2, p3 = r3, r4
+	cmp4.gt p2, p3 = 3, r4
+	cmp4.ge p2, p3 = r3, r4
+	cmp4.ge p2, p3 = 3, r4
+	cmp4.ltu p2, p3 = r3, r4
+	cmp4.ltu p2, p3 = 3, r4
+	cmp4.leu p2, p3 = r3, r4
+	cmp4.leu p2, p3 = 3, r4
+	cmp4.gtu p2, p3 = r3, r4
+	cmp4.gtu p2, p3 = 3, r4
+	cmp4.geu p2, p3 = r3, r4
+	cmp4.geu p2, p3 = 3, r4
+
+	cmp4.eq.unc p2, p3 = r3, r4
+	cmp4.eq.unc p2, p3 = 3, r4
+	cmp4.ne.unc p2, p3 = r3, r4
+	cmp4.ne.unc p2, p3 = 3, r4
+	cmp4.lt.unc p2, p3 = r3, r4
+	cmp4.lt.unc p2, p3 = 3, r4
+	cmp4.le.unc p2, p3 = r3, r4
+	cmp4.le.unc p2, p3 = 3, r4
+	cmp4.gt.unc p2, p3 = r3, r4
+	cmp4.gt.unc p2, p3 = 3, r4
+	cmp4.ge.unc p2, p3 = r3, r4
+	cmp4.ge.unc p2, p3 = 3, r4
+	cmp4.ltu.unc p2, p3 = r3, r4
+	cmp4.ltu.unc p2, p3 = 3, r4
+	cmp4.leu.unc p2, p3 = r3, r4
+	cmp4.leu.unc p2, p3 = 3, r4
+	cmp4.gtu.unc p2, p3 = r3, r4
+	cmp4.gtu.unc p2, p3 = 3, r4
+	cmp4.geu.unc p2, p3 = r3, r4
+	cmp4.geu.unc p2, p3 = 3, r4
+
+	cmp4.eq.and p2, p3 = r3, r4
+	cmp4.eq.and p2, p3 = 3, r4
+	cmp4.eq.or p2, p3 = r3, r4
+	cmp4.eq.or p2, p3 = 3, r4
+	cmp4.eq.or.andcm p2, p3 = r3, r4
+	cmp4.eq.or.andcm p2, p3 = 3, r4
+	cmp4.eq.orcm p2, p3 = r3, r4
+	cmp4.eq.orcm p2, p3 = 3, r4
+	cmp4.eq.andcm p2, p3 = r3, r4
+	cmp4.eq.andcm p2, p3 = 3, r4
+	cmp4.eq.and.orcm p2, p3 = r3, r4
+	cmp4.eq.and.orcm p2, p3 = 3, r4
+
+	cmp4.ne.and p2, p3 = r3, r4
+	cmp4.ne.and p2, p3 = 3, r4
+	cmp4.ne.or p2, p3 = r3, r4
+	cmp4.ne.or p2, p3 = 3, r4
+	cmp4.ne.or.andcm p2, p3 = r3, r4
+	cmp4.ne.or.andcm p2, p3 = 3, r4
+	cmp4.ne.orcm p2, p3 = r3, r4
+	cmp4.ne.orcm p2, p3 = 3, r4
+	cmp4.ne.andcm p2, p3 = r3, r4
+	cmp4.ne.andcm p2, p3 = 3, r4
+	cmp4.ne.and.orcm p2, p3 = r3, r4
+	cmp4.ne.and.orcm p2, p3 = 3, r4
+
+	cmp4.eq.and p2, p3 = r0, r4
+	cmp4.eq.or p2, p3 = r0, r4
+	cmp4.eq.or.andcm p2, p3 = r0, r4
+	cmp4.eq.orcm p2, p3 = r0, r4
+	cmp4.eq.andcm p2, p3 = r0, r4
+	cmp4.eq.and.orcm p2, p3 = r0, r4
+
+	cmp4.ne.and p2, p3 = r0, r4
+	cmp4.ne.or p2, p3 = r0, r4
+	cmp4.ne.or.andcm p2, p3 = r0, r4
+	cmp4.ne.orcm p2, p3 = r0, r4
+	cmp4.ne.andcm p2, p3 = r0, r4
+	cmp4.ne.and.orcm p2, p3 = r0, r4
+
+	cmp4.lt.and p2, p3 = r0, r4
+	cmp4.lt.or p2, p3 = r0, r4
+	cmp4.lt.or.andcm p2, p3 = r0, r4
+	cmp4.lt.orcm p2, p3 = r0, r4
+	cmp4.lt.andcm p2, p3 = r0, r4
+	cmp4.lt.and.orcm p2, p3 = r0, r4
+
+	cmp4.le.and p2, p3 = r0, r4
+	cmp4.le.or p2, p3 = r0, r4
+	cmp4.le.or.andcm p2, p3 = r0, r4
+	cmp4.le.orcm p2, p3 = r0, r4
+	cmp4.le.andcm p2, p3 = r0, r4
+	cmp4.le.and.orcm p2, p3 = r0, r4
+
+	cmp4.gt.and p2, p3 = r0, r4
+	cmp4.gt.or p2, p3 = r0, r4
+	cmp4.gt.or.andcm p2, p3 = r0, r4
+	cmp4.gt.orcm p2, p3 = r0, r4
+	cmp4.gt.andcm p2, p3 = r0, r4
+	cmp4.gt.and.orcm p2, p3 = r0, r4
+
+	cmp4.ge.and p2, p3 = r0, r4
+	cmp4.ge.or p2, p3 = r0, r4
+	cmp4.ge.or.andcm p2, p3 = r0, r4
+	cmp4.ge.orcm p2, p3 = r0, r4
+	cmp4.ge.andcm p2, p3 = r0, r4
+	cmp4.ge.and.orcm p2, p3 = r0, r4
+
+nop.i 0; nop.i 0
diff --git a/gas/testsuite/gas/ia64/opc-b.d b/gas/testsuite/gas/ia64/opc-b.d
new file mode 100644
index 0000000..80fcfff
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-b.d
@@ -0,0 +1,1014 @@
+#objdump: -d
+#name: ia64 opc-b
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0000000000000000 <.text>:
+       0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+       6:	00 f8 15 00 20 00 	      \(p02\) br\.cond\.sptk\.few 0x2bf0
+       c:	00 00 00 40       	            br\.few 0x0;;
+      10:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+      16:	00 f0 15 00 22 00 	      \(p02\) br\.cond\.sptk\.few\.clr 0x2bf0
+      1c:	f0 ff ff 4c       	            br\.few\.clr 0x0;;
+      20:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+      26:	00 e8 15 00 20 00 	      \(p02\) br\.cond\.sptk\.few 0x2bf0
+      2c:	e0 ff ff 48       	            br\.few 0x0;;
+      30:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+      36:	00 e0 15 00 22 00 	      \(p02\) br\.cond\.sptk\.few\.clr 0x2bf0
+      3c:	d0 ff ff 4c       	            br\.few\.clr 0x0;;
+      40:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+      46:	00 dc 15 00 20 00 	      \(p02\) br\.cond\.sptk\.many 0x2bf0
+      4c:	c8 ff ff 48       	            br\.many 0x0;;
+      50:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+      56:	00 d4 15 00 22 00 	      \(p02\) br\.cond\.sptk\.many\.clr 0x2bf0
+      5c:	b8 ff ff 4c       	            br\.many\.clr 0x0;;
+      60:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+      66:	00 c8 15 80 20 00 	      \(p02\) br\.cond\.spnt\.few 0x2bf0
+      6c:	a0 ff ff 49       	            br\.cond\.spnt\.few 0x0;;
+      70:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+      76:	00 c0 15 80 22 00 	      \(p02\) br\.cond\.spnt\.few\.clr 0x2bf0
+      7c:	90 ff ff 4d       	            br\.cond\.spnt\.few\.clr 0x0;;
+      80:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+      86:	00 b8 15 80 20 00 	      \(p02\) br\.cond\.spnt\.few 0x2bf0
+      8c:	80 ff ff 49       	            br\.cond\.spnt\.few 0x0;;
+      90:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+      96:	00 b0 15 80 22 00 	      \(p02\) br\.cond\.spnt\.few\.clr 0x2bf0
+      9c:	70 ff ff 4d       	            br\.cond\.spnt\.few\.clr 0x0;;
+      a0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+      a6:	00 ac 15 80 20 00 	      \(p02\) br\.cond\.spnt\.many 0x2bf0
+      ac:	68 ff ff 49       	            br\.cond\.spnt\.many 0x0;;
+      b0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+      b6:	00 a4 15 80 22 00 	      \(p02\) br\.cond\.spnt\.many\.clr 0x2bf0
+      bc:	58 ff ff 4d       	            br\.cond\.spnt\.many\.clr 0x0;;
+      c0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+      c6:	00 98 15 00 21 00 	      \(p02\) br\.cond\.dptk\.few 0x2bf0
+      cc:	40 ff ff 4a       	            br\.cond\.dptk\.few 0x0;;
+      d0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+      d6:	00 90 15 00 23 00 	      \(p02\) br\.cond\.dptk\.few\.clr 0x2bf0
+      dc:	30 ff ff 4e       	            br\.cond\.dptk\.few\.clr 0x0;;
+      e0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+      e6:	00 88 15 00 21 00 	      \(p02\) br\.cond\.dptk\.few 0x2bf0
+      ec:	20 ff ff 4a       	            br\.cond\.dptk\.few 0x0;;
+      f0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+      f6:	00 80 15 00 23 00 	      \(p02\) br\.cond\.dptk\.few\.clr 0x2bf0
+      fc:	10 ff ff 4e       	            br\.cond\.dptk\.few\.clr 0x0;;
+     100:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     106:	00 7c 15 00 21 00 	      \(p02\) br\.cond\.dptk\.many 0x2bf0
+     10c:	08 ff ff 4a       	            br\.cond\.dptk\.many 0x0;;
+     110:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     116:	00 74 15 00 23 00 	      \(p02\) br\.cond\.dptk\.many\.clr 0x2bf0
+     11c:	f8 fe ff 4e       	            br\.cond\.dptk\.many\.clr 0x0;;
+     120:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     126:	00 68 15 80 21 00 	      \(p02\) br\.cond\.dpnt\.few 0x2bf0
+     12c:	e0 fe ff 4b       	            br\.cond\.dpnt\.few 0x0;;
+     130:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     136:	00 60 15 80 23 00 	      \(p02\) br\.cond\.dpnt\.few\.clr 0x2bf0
+     13c:	d0 fe ff 4f       	            br\.cond\.dpnt\.few\.clr 0x0;;
+     140:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     146:	00 58 15 80 21 00 	      \(p02\) br\.cond\.dpnt\.few 0x2bf0
+     14c:	c0 fe ff 4b       	            br\.cond\.dpnt\.few 0x0;;
+     150:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     156:	00 50 15 80 23 00 	      \(p02\) br\.cond\.dpnt\.few\.clr 0x2bf0
+     15c:	b0 fe ff 4f       	            br\.cond\.dpnt\.few\.clr 0x0;;
+     160:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     166:	00 4c 15 80 21 00 	      \(p02\) br\.cond\.dpnt\.many 0x2bf0
+     16c:	a8 fe ff 4b       	            br\.cond\.dpnt\.many 0x0;;
+     170:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     176:	00 44 15 80 23 00 	      \(p02\) br\.cond\.dpnt\.many\.clr 0x2bf0
+     17c:	98 fe ff 4f       	            br\.cond\.dpnt\.many\.clr 0x0;;
+     180:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     186:	00 00 00 00 10 41 	            nop\.b 0x0
+     18c:	70 2a 00 40       	      \(p02\) br\.wexit\.sptk\.few 0x2bf0;;
+     190:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     196:	00 00 00 00 10 40 	            nop\.b 0x0
+     19c:	60 2a 00 40       	            br\.wexit\.sptk\.few 0x2bf0;;
+     1a0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     1a6:	00 00 00 00 10 41 	            nop\.b 0x0
+     1ac:	50 2a 00 44       	      \(p02\) br\.wexit\.sptk\.few\.clr 0x2bf0;;
+     1b0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     1b6:	00 00 00 00 10 40 	            nop\.b 0x0
+     1bc:	40 2a 00 44       	            br\.wexit\.sptk\.few\.clr 0x2bf0;;
+     1c0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     1c6:	00 00 00 00 10 41 	            nop\.b 0x0
+     1cc:	30 2a 00 40       	      \(p02\) br\.wexit\.sptk\.few 0x2bf0;;
+     1d0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     1d6:	00 00 00 00 10 40 	            nop\.b 0x0
+     1dc:	20 2a 00 40       	            br\.wexit\.sptk\.few 0x2bf0;;
+     1e0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     1e6:	00 00 00 00 10 41 	            nop\.b 0x0
+     1ec:	10 2a 00 44       	      \(p02\) br\.wexit\.sptk\.few\.clr 0x2bf0;;
+     1f0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     1f6:	00 00 00 00 10 40 	            nop\.b 0x0
+     1fc:	00 2a 00 44       	            br\.wexit\.sptk\.few\.clr 0x2bf0;;
+     200:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     206:	00 00 00 00 10 41 	            nop\.b 0x0
+     20c:	f8 29 00 40       	      \(p02\) br\.wexit\.sptk\.many 0x2bf0;;
+     210:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     216:	00 00 00 00 10 40 	            nop\.b 0x0
+     21c:	e8 29 00 40       	            br\.wexit\.sptk\.many 0x2bf0;;
+     220:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     226:	00 00 00 00 10 41 	            nop\.b 0x0
+     22c:	d8 29 00 44       	      \(p02\) br\.wexit\.sptk\.many\.clr 0x2bf0;;
+     230:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     236:	00 00 00 00 10 40 	            nop\.b 0x0
+     23c:	c8 29 00 44       	            br\.wexit\.sptk\.many\.clr 0x2bf0;;
+     240:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     246:	00 00 00 00 10 41 	            nop\.b 0x0
+     24c:	b0 29 00 41       	      \(p02\) br\.wexit\.spnt\.few 0x2bf0;;
+     250:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     256:	00 00 00 00 10 40 	            nop\.b 0x0
+     25c:	a0 29 00 41       	            br\.wexit\.spnt\.few 0x2bf0;;
+     260:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     266:	00 00 00 00 10 41 	            nop\.b 0x0
+     26c:	90 29 00 45       	      \(p02\) br\.wexit\.spnt\.few\.clr 0x2bf0;;
+     270:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     276:	00 00 00 00 10 40 	            nop\.b 0x0
+     27c:	80 29 00 45       	            br\.wexit\.spnt\.few\.clr 0x2bf0;;
+     280:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     286:	00 00 00 00 10 41 	            nop\.b 0x0
+     28c:	70 29 00 41       	      \(p02\) br\.wexit\.spnt\.few 0x2bf0;;
+     290:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     296:	00 00 00 00 10 40 	            nop\.b 0x0
+     29c:	60 29 00 41       	            br\.wexit\.spnt\.few 0x2bf0;;
+     2a0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     2a6:	00 00 00 00 10 41 	            nop\.b 0x0
+     2ac:	50 29 00 45       	      \(p02\) br\.wexit\.spnt\.few\.clr 0x2bf0;;
+     2b0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     2b6:	00 00 00 00 10 40 	            nop\.b 0x0
+     2bc:	40 29 00 45       	            br\.wexit\.spnt\.few\.clr 0x2bf0;;
+     2c0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     2c6:	00 00 00 00 10 41 	            nop\.b 0x0
+     2cc:	38 29 00 41       	      \(p02\) br\.wexit\.spnt\.many 0x2bf0;;
+     2d0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     2d6:	00 00 00 00 10 40 	            nop\.b 0x0
+     2dc:	28 29 00 41       	            br\.wexit\.spnt\.many 0x2bf0;;
+     2e0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     2e6:	00 00 00 00 10 41 	            nop\.b 0x0
+     2ec:	18 29 00 45       	      \(p02\) br\.wexit\.spnt\.many\.clr 0x2bf0;;
+     2f0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     2f6:	00 00 00 00 10 40 	            nop\.b 0x0
+     2fc:	08 29 00 45       	            br\.wexit\.spnt\.many\.clr 0x2bf0;;
+     300:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     306:	00 00 00 00 10 41 	            nop\.b 0x0
+     30c:	f0 28 00 42       	      \(p02\) br\.wexit\.dptk\.few 0x2bf0;;
+     310:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     316:	00 00 00 00 10 40 	            nop\.b 0x0
+     31c:	e0 28 00 42       	            br\.wexit\.dptk\.few 0x2bf0;;
+     320:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     326:	00 00 00 00 10 41 	            nop\.b 0x0
+     32c:	d0 28 00 46       	      \(p02\) br\.wexit\.dptk\.few\.clr 0x2bf0;;
+     330:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     336:	00 00 00 00 10 40 	            nop\.b 0x0
+     33c:	c0 28 00 46       	            br\.wexit\.dptk\.few\.clr 0x2bf0;;
+     340:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     346:	00 00 00 00 10 41 	            nop\.b 0x0
+     34c:	b0 28 00 42       	      \(p02\) br\.wexit\.dptk\.few 0x2bf0;;
+     350:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     356:	00 00 00 00 10 40 	            nop\.b 0x0
+     35c:	a0 28 00 42       	            br\.wexit\.dptk\.few 0x2bf0;;
+     360:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     366:	00 00 00 00 10 41 	            nop\.b 0x0
+     36c:	90 28 00 46       	      \(p02\) br\.wexit\.dptk\.few\.clr 0x2bf0;;
+     370:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     376:	00 00 00 00 10 40 	            nop\.b 0x0
+     37c:	80 28 00 46       	            br\.wexit\.dptk\.few\.clr 0x2bf0;;
+     380:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     386:	00 00 00 00 10 41 	            nop\.b 0x0
+     38c:	78 28 00 42       	      \(p02\) br\.wexit\.dptk\.many 0x2bf0;;
+     390:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     396:	00 00 00 00 10 40 	            nop\.b 0x0
+     39c:	68 28 00 42       	            br\.wexit\.dptk\.many 0x2bf0;;
+     3a0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     3a6:	00 00 00 00 10 41 	            nop\.b 0x0
+     3ac:	58 28 00 46       	      \(p02\) br\.wexit\.dptk\.many\.clr 0x2bf0;;
+     3b0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     3b6:	00 00 00 00 10 40 	            nop\.b 0x0
+     3bc:	48 28 00 46       	            br\.wexit\.dptk\.many\.clr 0x2bf0;;
+     3c0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     3c6:	00 00 00 00 10 41 	            nop\.b 0x0
+     3cc:	30 28 00 43       	      \(p02\) br\.wexit\.dpnt\.few 0x2bf0;;
+     3d0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     3d6:	00 00 00 00 10 40 	            nop\.b 0x0
+     3dc:	20 28 00 43       	            br\.wexit\.dpnt\.few 0x2bf0;;
+     3e0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     3e6:	00 00 00 00 10 41 	            nop\.b 0x0
+     3ec:	10 28 00 47       	      \(p02\) br\.wexit\.dpnt\.few\.clr 0x2bf0;;
+     3f0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     3f6:	00 00 00 00 10 40 	            nop\.b 0x0
+     3fc:	00 28 00 47       	            br\.wexit\.dpnt\.few\.clr 0x2bf0;;
+     400:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     406:	00 00 00 00 10 41 	            nop\.b 0x0
+     40c:	f0 27 00 43       	      \(p02\) br\.wexit\.dpnt\.few 0x2bf0;;
+     410:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     416:	00 00 00 00 10 40 	            nop\.b 0x0
+     41c:	e0 27 00 43       	            br\.wexit\.dpnt\.few 0x2bf0;;
+     420:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     426:	00 00 00 00 10 41 	            nop\.b 0x0
+     42c:	d0 27 00 47       	      \(p02\) br\.wexit\.dpnt\.few\.clr 0x2bf0;;
+     430:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     436:	00 00 00 00 10 40 	            nop\.b 0x0
+     43c:	c0 27 00 47       	            br\.wexit\.dpnt\.few\.clr 0x2bf0;;
+     440:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     446:	00 00 00 00 10 41 	            nop\.b 0x0
+     44c:	b8 27 00 43       	      \(p02\) br\.wexit\.dpnt\.many 0x2bf0;;
+     450:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     456:	00 00 00 00 10 40 	            nop\.b 0x0
+     45c:	a8 27 00 43       	            br\.wexit\.dpnt\.many 0x2bf0;;
+     460:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     466:	00 00 00 00 10 41 	            nop\.b 0x0
+     46c:	98 27 00 47       	      \(p02\) br\.wexit\.dpnt\.many\.clr 0x2bf0;;
+     470:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     476:	00 00 00 00 10 40 	            nop\.b 0x0
+     47c:	88 27 00 47       	            br\.wexit\.dpnt\.many\.clr 0x2bf0;;
+     480:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     486:	00 00 00 00 10 61 	            nop\.b 0x0
+     48c:	70 27 00 40       	      \(p02\) br\.wtop\.sptk\.few 0x2bf0;;
+     490:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     496:	00 00 00 00 10 60 	            nop\.b 0x0
+     49c:	60 27 00 40       	            br\.wtop\.sptk\.few 0x2bf0;;
+     4a0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     4a6:	00 00 00 00 10 61 	            nop\.b 0x0
+     4ac:	50 27 00 44       	      \(p02\) br\.wtop\.sptk\.few\.clr 0x2bf0;;
+     4b0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     4b6:	00 00 00 00 10 60 	            nop\.b 0x0
+     4bc:	40 27 00 44       	            br\.wtop\.sptk\.few\.clr 0x2bf0;;
+     4c0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     4c6:	00 00 00 00 10 61 	            nop\.b 0x0
+     4cc:	30 27 00 40       	      \(p02\) br\.wtop\.sptk\.few 0x2bf0;;
+     4d0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     4d6:	00 00 00 00 10 60 	            nop\.b 0x0
+     4dc:	20 27 00 40       	            br\.wtop\.sptk\.few 0x2bf0;;
+     4e0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     4e6:	00 00 00 00 10 61 	            nop\.b 0x0
+     4ec:	10 27 00 44       	      \(p02\) br\.wtop\.sptk\.few\.clr 0x2bf0;;
+     4f0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     4f6:	00 00 00 00 10 60 	            nop\.b 0x0
+     4fc:	00 27 00 44       	            br\.wtop\.sptk\.few\.clr 0x2bf0;;
+     500:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     506:	00 00 00 00 10 61 	            nop\.b 0x0
+     50c:	f8 26 00 40       	      \(p02\) br\.wtop\.sptk\.many 0x2bf0;;
+     510:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     516:	00 00 00 00 10 60 	            nop\.b 0x0
+     51c:	e8 26 00 40       	            br\.wtop\.sptk\.many 0x2bf0;;
+     520:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     526:	00 00 00 00 10 61 	            nop\.b 0x0
+     52c:	d8 26 00 44       	      \(p02\) br\.wtop\.sptk\.many\.clr 0x2bf0;;
+     530:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     536:	00 00 00 00 10 60 	            nop\.b 0x0
+     53c:	c8 26 00 44       	            br\.wtop\.sptk\.many\.clr 0x2bf0;;
+     540:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     546:	00 00 00 00 10 61 	            nop\.b 0x0
+     54c:	b0 26 00 41       	      \(p02\) br\.wtop\.spnt\.few 0x2bf0;;
+     550:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     556:	00 00 00 00 10 60 	            nop\.b 0x0
+     55c:	a0 26 00 41       	            br\.wtop\.spnt\.few 0x2bf0;;
+     560:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     566:	00 00 00 00 10 61 	            nop\.b 0x0
+     56c:	90 26 00 45       	      \(p02\) br\.wtop\.spnt\.few\.clr 0x2bf0;;
+     570:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     576:	00 00 00 00 10 60 	            nop\.b 0x0
+     57c:	80 26 00 45       	            br\.wtop\.spnt\.few\.clr 0x2bf0;;
+     580:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     586:	00 00 00 00 10 61 	            nop\.b 0x0
+     58c:	70 26 00 41       	      \(p02\) br\.wtop\.spnt\.few 0x2bf0;;
+     590:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     596:	00 00 00 00 10 60 	            nop\.b 0x0
+     59c:	60 26 00 41       	            br\.wtop\.spnt\.few 0x2bf0;;
+     5a0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     5a6:	00 00 00 00 10 61 	            nop\.b 0x0
+     5ac:	50 26 00 45       	      \(p02\) br\.wtop\.spnt\.few\.clr 0x2bf0;;
+     5b0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     5b6:	00 00 00 00 10 60 	            nop\.b 0x0
+     5bc:	40 26 00 45       	            br\.wtop\.spnt\.few\.clr 0x2bf0;;
+     5c0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     5c6:	00 00 00 00 10 61 	            nop\.b 0x0
+     5cc:	38 26 00 41       	      \(p02\) br\.wtop\.spnt\.many 0x2bf0;;
+     5d0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     5d6:	00 00 00 00 10 60 	            nop\.b 0x0
+     5dc:	28 26 00 41       	            br\.wtop\.spnt\.many 0x2bf0;;
+     5e0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     5e6:	00 00 00 00 10 61 	            nop\.b 0x0
+     5ec:	18 26 00 45       	      \(p02\) br\.wtop\.spnt\.many\.clr 0x2bf0;;
+     5f0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     5f6:	00 00 00 00 10 60 	            nop\.b 0x0
+     5fc:	08 26 00 45       	            br\.wtop\.spnt\.many\.clr 0x2bf0;;
+     600:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     606:	00 00 00 00 10 61 	            nop\.b 0x0
+     60c:	f0 25 00 42       	      \(p02\) br\.wtop\.dptk\.few 0x2bf0;;
+     610:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     616:	00 00 00 00 10 60 	            nop\.b 0x0
+     61c:	e0 25 00 42       	            br\.wtop\.dptk\.few 0x2bf0;;
+     620:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     626:	00 00 00 00 10 61 	            nop\.b 0x0
+     62c:	d0 25 00 46       	      \(p02\) br\.wtop\.dptk\.few\.clr 0x2bf0;;
+     630:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     636:	00 00 00 00 10 60 	            nop\.b 0x0
+     63c:	c0 25 00 46       	            br\.wtop\.dptk\.few\.clr 0x2bf0;;
+     640:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     646:	00 00 00 00 10 61 	            nop\.b 0x0
+     64c:	b0 25 00 42       	      \(p02\) br\.wtop\.dptk\.few 0x2bf0;;
+     650:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     656:	00 00 00 00 10 60 	            nop\.b 0x0
+     65c:	a0 25 00 42       	            br\.wtop\.dptk\.few 0x2bf0;;
+     660:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     666:	00 00 00 00 10 61 	            nop\.b 0x0
+     66c:	90 25 00 46       	      \(p02\) br\.wtop\.dptk\.few\.clr 0x2bf0;;
+     670:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     676:	00 00 00 00 10 60 	            nop\.b 0x0
+     67c:	80 25 00 46       	            br\.wtop\.dptk\.few\.clr 0x2bf0;;
+     680:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     686:	00 00 00 00 10 61 	            nop\.b 0x0
+     68c:	78 25 00 42       	      \(p02\) br\.wtop\.dptk\.many 0x2bf0;;
+     690:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     696:	00 00 00 00 10 60 	            nop\.b 0x0
+     69c:	68 25 00 42       	            br\.wtop\.dptk\.many 0x2bf0;;
+     6a0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     6a6:	00 00 00 00 10 61 	            nop\.b 0x0
+     6ac:	58 25 00 46       	      \(p02\) br\.wtop\.dptk\.many\.clr 0x2bf0;;
+     6b0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     6b6:	00 00 00 00 10 60 	            nop\.b 0x0
+     6bc:	48 25 00 46       	            br\.wtop\.dptk\.many\.clr 0x2bf0;;
+     6c0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     6c6:	00 00 00 00 10 61 	            nop\.b 0x0
+     6cc:	30 25 00 43       	      \(p02\) br\.wtop\.dpnt\.few 0x2bf0;;
+     6d0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     6d6:	00 00 00 00 10 60 	            nop\.b 0x0
+     6dc:	20 25 00 43       	            br\.wtop\.dpnt\.few 0x2bf0;;
+     6e0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     6e6:	00 00 00 00 10 61 	            nop\.b 0x0
+     6ec:	10 25 00 47       	      \(p02\) br\.wtop\.dpnt\.few\.clr 0x2bf0;;
+     6f0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     6f6:	00 00 00 00 10 60 	            nop\.b 0x0
+     6fc:	00 25 00 47       	            br\.wtop\.dpnt\.few\.clr 0x2bf0;;
+     700:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     706:	00 00 00 00 10 61 	            nop\.b 0x0
+     70c:	f0 24 00 43       	      \(p02\) br\.wtop\.dpnt\.few 0x2bf0;;
+     710:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     716:	00 00 00 00 10 60 	            nop\.b 0x0
+     71c:	e0 24 00 43       	            br\.wtop\.dpnt\.few 0x2bf0;;
+     720:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     726:	00 00 00 00 10 61 	            nop\.b 0x0
+     72c:	d0 24 00 47       	      \(p02\) br\.wtop\.dpnt\.few\.clr 0x2bf0;;
+     730:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     736:	00 00 00 00 10 60 	            nop\.b 0x0
+     73c:	c0 24 00 47       	            br\.wtop\.dpnt\.few\.clr 0x2bf0;;
+     740:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     746:	00 00 00 00 10 61 	            nop\.b 0x0
+     74c:	b8 24 00 43       	      \(p02\) br\.wtop\.dpnt\.many 0x2bf0;;
+     750:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     756:	00 00 00 00 10 60 	            nop\.b 0x0
+     75c:	a8 24 00 43       	            br\.wtop\.dpnt\.many 0x2bf0;;
+     760:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     766:	00 00 00 00 10 61 	            nop\.b 0x0
+     76c:	98 24 00 47       	      \(p02\) br\.wtop\.dpnt\.many\.clr 0x2bf0;;
+     770:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     776:	00 00 00 00 10 60 	            nop\.b 0x0
+     77c:	88 24 00 47       	            br\.wtop\.dpnt\.many\.clr 0x2bf0;;
+     780:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     786:	00 00 00 00 10 a0 	            nop\.b 0x0
+     78c:	70 24 00 40       	            br\.cloop\.sptk\.few 0x2bf0;;
+     790:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     796:	00 00 00 00 10 a0 	            nop\.b 0x0
+     79c:	60 24 00 44       	            br\.cloop\.sptk\.few\.clr 0x2bf0;;
+     7a0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     7a6:	00 00 00 00 10 a0 	            nop\.b 0x0
+     7ac:	50 24 00 40       	            br\.cloop\.sptk\.few 0x2bf0;;
+     7b0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     7b6:	00 00 00 00 10 a0 	            nop\.b 0x0
+     7bc:	40 24 00 44       	            br\.cloop\.sptk\.few\.clr 0x2bf0;;
+     7c0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     7c6:	00 00 00 00 10 a0 	            nop\.b 0x0
+     7cc:	38 24 00 40       	            br\.cloop\.sptk\.many 0x2bf0;;
+     7d0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     7d6:	00 00 00 00 10 a0 	            nop\.b 0x0
+     7dc:	28 24 00 44       	            br\.cloop\.sptk\.many\.clr 0x2bf0;;
+     7e0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     7e6:	00 00 00 00 10 a0 	            nop\.b 0x0
+     7ec:	10 24 00 41       	            br\.cloop\.spnt\.few 0x2bf0;;
+     7f0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     7f6:	00 00 00 00 10 a0 	            nop\.b 0x0
+     7fc:	00 24 00 45       	            br\.cloop\.spnt\.few\.clr 0x2bf0;;
+     800:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     806:	00 00 00 00 10 a0 	            nop\.b 0x0
+     80c:	f0 23 00 41       	            br\.cloop\.spnt\.few 0x2bf0;;
+     810:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     816:	00 00 00 00 10 a0 	            nop\.b 0x0
+     81c:	e0 23 00 45       	            br\.cloop\.spnt\.few\.clr 0x2bf0;;
+     820:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     826:	00 00 00 00 10 a0 	            nop\.b 0x0
+     82c:	d8 23 00 41       	            br\.cloop\.spnt\.many 0x2bf0;;
+     830:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     836:	00 00 00 00 10 a0 	            nop\.b 0x0
+     83c:	c8 23 00 45       	            br\.cloop\.spnt\.many\.clr 0x2bf0;;
+     840:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     846:	00 00 00 00 10 a0 	            nop\.b 0x0
+     84c:	b0 23 00 42       	            br\.cloop\.dptk\.few 0x2bf0;;
+     850:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     856:	00 00 00 00 10 a0 	            nop\.b 0x0
+     85c:	a0 23 00 46       	            br\.cloop\.dptk\.few\.clr 0x2bf0;;
+     860:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     866:	00 00 00 00 10 a0 	            nop\.b 0x0
+     86c:	90 23 00 42       	            br\.cloop\.dptk\.few 0x2bf0;;
+     870:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     876:	00 00 00 00 10 a0 	            nop\.b 0x0
+     87c:	80 23 00 46       	            br\.cloop\.dptk\.few\.clr 0x2bf0;;
+     880:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     886:	00 00 00 00 10 a0 	            nop\.b 0x0
+     88c:	78 23 00 42       	            br\.cloop\.dptk\.many 0x2bf0;;
+     890:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     896:	00 00 00 00 10 a0 	            nop\.b 0x0
+     89c:	68 23 00 46       	            br\.cloop\.dptk\.many\.clr 0x2bf0;;
+     8a0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     8a6:	00 00 00 00 10 a0 	            nop\.b 0x0
+     8ac:	50 23 00 43       	            br\.cloop\.dpnt\.few 0x2bf0;;
+     8b0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     8b6:	00 00 00 00 10 a0 	            nop\.b 0x0
+     8bc:	40 23 00 47       	            br\.cloop\.dpnt\.few\.clr 0x2bf0;;
+     8c0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     8c6:	00 00 00 00 10 a0 	            nop\.b 0x0
+     8cc:	30 23 00 43       	            br\.cloop\.dpnt\.few 0x2bf0;;
+     8d0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     8d6:	00 00 00 00 10 a0 	            nop\.b 0x0
+     8dc:	20 23 00 47       	            br\.cloop\.dpnt\.few\.clr 0x2bf0;;
+     8e0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     8e6:	00 00 00 00 10 a0 	            nop\.b 0x0
+     8ec:	18 23 00 43       	            br\.cloop\.dpnt\.many 0x2bf0;;
+     8f0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     8f6:	00 00 00 00 10 a0 	            nop\.b 0x0
+     8fc:	08 23 00 47       	            br\.cloop\.dpnt\.many\.clr 0x2bf0;;
+     900:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     906:	00 00 00 00 10 c0 	            nop\.b 0x0
+     90c:	f0 22 00 40       	            br\.cexit\.sptk\.few 0x2bf0;;
+     910:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     916:	00 00 00 00 10 c0 	            nop\.b 0x0
+     91c:	e0 22 00 44       	            br\.cexit\.sptk\.few\.clr 0x2bf0;;
+     920:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     926:	00 00 00 00 10 c0 	            nop\.b 0x0
+     92c:	d0 22 00 40       	            br\.cexit\.sptk\.few 0x2bf0;;
+     930:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     936:	00 00 00 00 10 c0 	            nop\.b 0x0
+     93c:	c0 22 00 44       	            br\.cexit\.sptk\.few\.clr 0x2bf0;;
+     940:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     946:	00 00 00 00 10 c0 	            nop\.b 0x0
+     94c:	b8 22 00 40       	            br\.cexit\.sptk\.many 0x2bf0;;
+     950:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     956:	00 00 00 00 10 c0 	            nop\.b 0x0
+     95c:	a8 22 00 44       	            br\.cexit\.sptk\.many\.clr 0x2bf0;;
+     960:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     966:	00 00 00 00 10 c0 	            nop\.b 0x0
+     96c:	90 22 00 41       	            br\.cexit\.spnt\.few 0x2bf0;;
+     970:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     976:	00 00 00 00 10 c0 	            nop\.b 0x0
+     97c:	80 22 00 45       	            br\.cexit\.spnt\.few\.clr 0x2bf0;;
+     980:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     986:	00 00 00 00 10 c0 	            nop\.b 0x0
+     98c:	70 22 00 41       	            br\.cexit\.spnt\.few 0x2bf0;;
+     990:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     996:	00 00 00 00 10 c0 	            nop\.b 0x0
+     99c:	60 22 00 45       	            br\.cexit\.spnt\.few\.clr 0x2bf0;;
+     9a0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     9a6:	00 00 00 00 10 c0 	            nop\.b 0x0
+     9ac:	58 22 00 41       	            br\.cexit\.spnt\.many 0x2bf0;;
+     9b0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     9b6:	00 00 00 00 10 c0 	            nop\.b 0x0
+     9bc:	48 22 00 45       	            br\.cexit\.spnt\.many\.clr 0x2bf0;;
+     9c0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     9c6:	00 00 00 00 10 c0 	            nop\.b 0x0
+     9cc:	30 22 00 42       	            br\.cexit\.dptk\.few 0x2bf0;;
+     9d0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     9d6:	00 00 00 00 10 c0 	            nop\.b 0x0
+     9dc:	20 22 00 46       	            br\.cexit\.dptk\.few\.clr 0x2bf0;;
+     9e0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     9e6:	00 00 00 00 10 c0 	            nop\.b 0x0
+     9ec:	10 22 00 42       	            br\.cexit\.dptk\.few 0x2bf0;;
+     9f0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     9f6:	00 00 00 00 10 c0 	            nop\.b 0x0
+     9fc:	00 22 00 46       	            br\.cexit\.dptk\.few\.clr 0x2bf0;;
+     a00:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     a06:	00 00 00 00 10 c0 	            nop\.b 0x0
+     a0c:	f8 21 00 42       	            br\.cexit\.dptk\.many 0x2bf0;;
+     a10:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     a16:	00 00 00 00 10 c0 	            nop\.b 0x0
+     a1c:	e8 21 00 46       	            br\.cexit\.dptk\.many\.clr 0x2bf0;;
+     a20:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     a26:	00 00 00 00 10 c0 	            nop\.b 0x0
+     a2c:	d0 21 00 43       	            br\.cexit\.dpnt\.few 0x2bf0;;
+     a30:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     a36:	00 00 00 00 10 c0 	            nop\.b 0x0
+     a3c:	c0 21 00 47       	            br\.cexit\.dpnt\.few\.clr 0x2bf0;;
+     a40:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     a46:	00 00 00 00 10 c0 	            nop\.b 0x0
+     a4c:	b0 21 00 43       	            br\.cexit\.dpnt\.few 0x2bf0;;
+     a50:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     a56:	00 00 00 00 10 c0 	            nop\.b 0x0
+     a5c:	a0 21 00 47       	            br\.cexit\.dpnt\.few\.clr 0x2bf0;;
+     a60:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     a66:	00 00 00 00 10 c0 	            nop\.b 0x0
+     a6c:	98 21 00 43       	            br\.cexit\.dpnt\.many 0x2bf0;;
+     a70:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     a76:	00 00 00 00 10 c0 	            nop\.b 0x0
+     a7c:	88 21 00 47       	            br\.cexit\.dpnt\.many\.clr 0x2bf0;;
+     a80:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     a86:	00 00 00 00 10 e0 	            nop\.b 0x0
+     a8c:	70 21 00 40       	            br\.ctop\.sptk\.few 0x2bf0;;
+     a90:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     a96:	00 00 00 00 10 e0 	            nop\.b 0x0
+     a9c:	60 21 00 44       	            br\.ctop\.sptk\.few\.clr 0x2bf0;;
+     aa0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     aa6:	00 00 00 00 10 e0 	            nop\.b 0x0
+     aac:	50 21 00 40       	            br\.ctop\.sptk\.few 0x2bf0;;
+     ab0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     ab6:	00 00 00 00 10 e0 	            nop\.b 0x0
+     abc:	40 21 00 44       	            br\.ctop\.sptk\.few\.clr 0x2bf0;;
+     ac0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     ac6:	00 00 00 00 10 e0 	            nop\.b 0x0
+     acc:	38 21 00 40       	            br\.ctop\.sptk\.many 0x2bf0;;
+     ad0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     ad6:	00 00 00 00 10 e0 	            nop\.b 0x0
+     adc:	28 21 00 44       	            br\.ctop\.sptk\.many\.clr 0x2bf0;;
+     ae0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     ae6:	00 00 00 00 10 e0 	            nop\.b 0x0
+     aec:	10 21 00 41       	            br\.ctop\.spnt\.few 0x2bf0;;
+     af0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     af6:	00 00 00 00 10 e0 	            nop\.b 0x0
+     afc:	00 21 00 45       	            br\.ctop\.spnt\.few\.clr 0x2bf0;;
+     b00:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     b06:	00 00 00 00 10 e0 	            nop\.b 0x0
+     b0c:	f0 20 00 41       	            br\.ctop\.spnt\.few 0x2bf0;;
+     b10:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     b16:	00 00 00 00 10 e0 	            nop\.b 0x0
+     b1c:	e0 20 00 45       	            br\.ctop\.spnt\.few\.clr 0x2bf0;;
+     b20:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     b26:	00 00 00 00 10 e0 	            nop\.b 0x0
+     b2c:	d8 20 00 41       	            br\.ctop\.spnt\.many 0x2bf0;;
+     b30:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     b36:	00 00 00 00 10 e0 	            nop\.b 0x0
+     b3c:	c8 20 00 45       	            br\.ctop\.spnt\.many\.clr 0x2bf0;;
+     b40:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     b46:	00 00 00 00 10 e0 	            nop\.b 0x0
+     b4c:	b0 20 00 42       	            br\.ctop\.dptk\.few 0x2bf0;;
+     b50:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     b56:	00 00 00 00 10 e0 	            nop\.b 0x0
+     b5c:	a0 20 00 46       	            br\.ctop\.dptk\.few\.clr 0x2bf0;;
+     b60:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     b66:	00 00 00 00 10 e0 	            nop\.b 0x0
+     b6c:	90 20 00 42       	            br\.ctop\.dptk\.few 0x2bf0;;
+     b70:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     b76:	00 00 00 00 10 e0 	            nop\.b 0x0
+     b7c:	80 20 00 46       	            br\.ctop\.dptk\.few\.clr 0x2bf0;;
+     b80:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     b86:	00 00 00 00 10 e0 	            nop\.b 0x0
+     b8c:	78 20 00 42       	            br\.ctop\.dptk\.many 0x2bf0;;
+     b90:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     b96:	00 00 00 00 10 e0 	            nop\.b 0x0
+     b9c:	68 20 00 46       	            br\.ctop\.dptk\.many\.clr 0x2bf0;;
+     ba0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     ba6:	00 00 00 00 10 e0 	            nop\.b 0x0
+     bac:	50 20 00 43       	            br\.ctop\.dpnt\.few 0x2bf0;;
+     bb0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     bb6:	00 00 00 00 10 e0 	            nop\.b 0x0
+     bbc:	40 20 00 47       	            br\.ctop\.dpnt\.few\.clr 0x2bf0;;
+     bc0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     bc6:	00 00 00 00 10 e0 	            nop\.b 0x0
+     bcc:	30 20 00 43       	            br\.ctop\.dpnt\.few 0x2bf0;;
+     bd0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     bd6:	00 00 00 00 10 e0 	            nop\.b 0x0
+     bdc:	20 20 00 47       	            br\.ctop\.dpnt\.few\.clr 0x2bf0;;
+     be0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     be6:	00 00 00 00 10 e0 	            nop\.b 0x0
+     bec:	18 20 00 43       	            br\.ctop\.dpnt\.many 0x2bf0;;
+     bf0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     bf6:	00 00 00 00 10 e0 	            nop\.b 0x0
+     bfc:	08 20 00 47       	            br\.ctop\.dpnt\.many\.clr 0x2bf0;;
+     c00:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     c06:	00 f8 0f 00 28 00 	      \(p02\) br\.call\.sptk\.few b0=0x2bf0
+     c0c:	00 f4 ff 58       	            br\.call\.sptk\.few b0=0x0;;
+     c10:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     c16:	00 f0 0f 00 2a 00 	      \(p02\) br\.call\.sptk\.few\.clr b0=0x2bf0
+     c1c:	f0 f3 ff 5c       	            br\.call\.sptk\.few\.clr b0=0x0;;
+     c20:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     c26:	00 e8 0f 00 28 00 	      \(p02\) br\.call\.sptk\.few b0=0x2bf0
+     c2c:	e0 f3 ff 58       	            br\.call\.sptk\.few b0=0x0;;
+     c30:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     c36:	00 e0 0f 00 2a 00 	      \(p02\) br\.call\.sptk\.few\.clr b0=0x2bf0
+     c3c:	d0 f3 ff 5c       	            br\.call\.sptk\.few\.clr b0=0x0;;
+     c40:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     c46:	00 dc 0f 00 28 00 	      \(p02\) br\.call\.sptk\.many b0=0x2bf0
+     c4c:	c8 f3 ff 58       	            br\.call\.sptk\.many b0=0x0;;
+     c50:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     c56:	00 d4 0f 00 2a 00 	      \(p02\) br\.call\.sptk\.many\.clr b0=0x2bf0
+     c5c:	b8 f3 ff 5c       	            br\.call\.sptk\.many\.clr b0=0x0;;
+     c60:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     c66:	00 c8 0f 80 28 00 	      \(p02\) br\.call\.spnt\.few b0=0x2bf0
+     c6c:	a0 f3 ff 59       	            br\.call\.spnt\.few b0=0x0;;
+     c70:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     c76:	00 c0 0f 80 2a 00 	      \(p02\) br\.call\.spnt\.few\.clr b0=0x2bf0
+     c7c:	90 f3 ff 5d       	            br\.call\.spnt\.few\.clr b0=0x0;;
+     c80:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     c86:	00 b8 0f 80 28 00 	      \(p02\) br\.call\.spnt\.few b0=0x2bf0
+     c8c:	80 f3 ff 59       	            br\.call\.spnt\.few b0=0x0;;
+     c90:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     c96:	00 b0 0f 80 2a 00 	      \(p02\) br\.call\.spnt\.few\.clr b0=0x2bf0
+     c9c:	70 f3 ff 5d       	            br\.call\.spnt\.few\.clr b0=0x0;;
+     ca0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     ca6:	00 ac 0f 80 28 00 	      \(p02\) br\.call\.spnt\.many b0=0x2bf0
+     cac:	68 f3 ff 59       	            br\.call\.spnt\.many b0=0x0;;
+     cb0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     cb6:	00 a4 0f 80 2a 00 	      \(p02\) br\.call\.spnt\.many\.clr b0=0x2bf0
+     cbc:	58 f3 ff 5d       	            br\.call\.spnt\.many\.clr b0=0x0;;
+     cc0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     cc6:	00 98 0f 00 29 00 	      \(p02\) br\.call\.dptk\.few b0=0x2bf0
+     ccc:	40 f3 ff 5a       	            br\.call\.dptk\.few b0=0x0;;
+     cd0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     cd6:	00 90 0f 00 2b 00 	      \(p02\) br\.call\.dptk\.few\.clr b0=0x2bf0
+     cdc:	30 f3 ff 5e       	            br\.call\.dptk\.few\.clr b0=0x0;;
+     ce0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     ce6:	00 88 0f 00 29 00 	      \(p02\) br\.call\.dptk\.few b0=0x2bf0
+     cec:	20 f3 ff 5a       	            br\.call\.dptk\.few b0=0x0;;
+     cf0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     cf6:	00 80 0f 00 2b 00 	      \(p02\) br\.call\.dptk\.few\.clr b0=0x2bf0
+     cfc:	10 f3 ff 5e       	            br\.call\.dptk\.few\.clr b0=0x0;;
+     d00:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     d06:	00 7c 0f 00 29 00 	      \(p02\) br\.call\.dptk\.many b0=0x2bf0
+     d0c:	08 f3 ff 5a       	            br\.call\.dptk\.many b0=0x0;;
+     d10:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     d16:	00 74 0f 00 2b 00 	      \(p02\) br\.call\.dptk\.many\.clr b0=0x2bf0
+     d1c:	f8 f2 ff 5e       	            br\.call\.dptk\.many\.clr b0=0x0;;
+     d20:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     d26:	00 68 0f 80 29 00 	      \(p02\) br\.call\.dpnt\.few b0=0x2bf0
+     d2c:	e0 f2 ff 5b       	            br\.call\.dpnt\.few b0=0x0;;
+     d30:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     d36:	00 60 0f 80 2b 00 	      \(p02\) br\.call\.dpnt\.few\.clr b0=0x2bf0
+     d3c:	d0 f2 ff 5f       	            br\.call\.dpnt\.few\.clr b0=0x0;;
+     d40:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     d46:	00 58 0f 80 29 00 	      \(p02\) br\.call\.dpnt\.few b0=0x2bf0
+     d4c:	c0 f2 ff 5b       	            br\.call\.dpnt\.few b0=0x0;;
+     d50:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     d56:	00 50 0f 80 2b 00 	      \(p02\) br\.call\.dpnt\.few\.clr b0=0x2bf0
+     d5c:	b0 f2 ff 5f       	            br\.call\.dpnt\.few\.clr b0=0x0;;
+     d60:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     d66:	00 4c 0f 80 29 00 	      \(p02\) br\.call\.dpnt\.many b0=0x2bf0
+     d6c:	a8 f2 ff 5b       	            br\.call\.dpnt\.many b0=0x0;;
+     d70:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     d76:	00 44 0f 80 2b 00 	      \(p02\) br\.call\.dpnt\.many\.clr b0=0x2bf0
+     d7c:	98 f2 ff 5f       	            br\.call\.dpnt\.many\.clr b0=0x0;;
+     d80:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     d86:	00 10 00 40 00 00 	      \(p02\) br\.cond\.sptk\.few b2
+     d8c:	20 00 80 00       	            br\.few b2;;
+     d90:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     d96:	00 10 00 40 02 00 	      \(p02\) br\.cond\.sptk\.few\.clr b2
+     d9c:	20 00 80 04       	            br\.few\.clr b2;;
+     da0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     da6:	00 10 00 40 00 00 	      \(p02\) br\.cond\.sptk\.few b2
+     dac:	20 00 80 00       	            br\.few b2;;
+     db0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     db6:	00 10 00 40 02 00 	      \(p02\) br\.cond\.sptk\.few\.clr b2
+     dbc:	20 00 80 04       	            br\.few\.clr b2;;
+     dc0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     dc6:	00 14 00 40 00 00 	      \(p02\) br\.cond\.sptk\.many b2
+     dcc:	28 00 80 00       	            br\.many b2;;
+     dd0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     dd6:	00 14 00 40 02 00 	      \(p02\) br\.cond\.sptk\.many\.clr b2
+     ddc:	28 00 80 04       	            br\.many\.clr b2;;
+     de0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     de6:	00 10 00 c0 00 00 	      \(p02\) br\.cond\.spnt\.few b2
+     dec:	20 00 80 01       	            br\.cond\.spnt\.few b2;;
+     df0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     df6:	00 10 00 c0 02 00 	      \(p02\) br\.cond\.spnt\.few\.clr b2
+     dfc:	20 00 80 05       	            br\.cond\.spnt\.few\.clr b2;;
+     e00:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     e06:	00 10 00 c0 00 00 	      \(p02\) br\.cond\.spnt\.few b2
+     e0c:	20 00 80 01       	            br\.cond\.spnt\.few b2;;
+     e10:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     e16:	00 10 00 c0 02 00 	      \(p02\) br\.cond\.spnt\.few\.clr b2
+     e1c:	20 00 80 05       	            br\.cond\.spnt\.few\.clr b2;;
+     e20:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     e26:	00 14 00 c0 00 00 	      \(p02\) br\.cond\.spnt\.many b2
+     e2c:	28 00 80 01       	            br\.cond\.spnt\.many b2;;
+     e30:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     e36:	00 14 00 c0 02 00 	      \(p02\) br\.cond\.spnt\.many\.clr b2
+     e3c:	28 00 80 05       	            br\.cond\.spnt\.many\.clr b2;;
+     e40:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     e46:	00 10 00 40 01 00 	      \(p02\) br\.cond\.dptk\.few b2
+     e4c:	20 00 80 02       	            br\.cond\.dptk\.few b2;;
+     e50:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     e56:	00 10 00 40 03 00 	      \(p02\) br\.cond\.dptk\.few\.clr b2
+     e5c:	20 00 80 06       	            br\.cond\.dptk\.few\.clr b2;;
+     e60:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     e66:	00 10 00 40 01 00 	      \(p02\) br\.cond\.dptk\.few b2
+     e6c:	20 00 80 02       	            br\.cond\.dptk\.few b2;;
+     e70:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     e76:	00 10 00 40 03 00 	      \(p02\) br\.cond\.dptk\.few\.clr b2
+     e7c:	20 00 80 06       	            br\.cond\.dptk\.few\.clr b2;;
+     e80:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     e86:	00 14 00 40 01 00 	      \(p02\) br\.cond\.dptk\.many b2
+     e8c:	28 00 80 02       	            br\.cond\.dptk\.many b2;;
+     e90:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     e96:	00 14 00 40 03 00 	      \(p02\) br\.cond\.dptk\.many\.clr b2
+     e9c:	28 00 80 06       	            br\.cond\.dptk\.many\.clr b2;;
+     ea0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     ea6:	00 10 00 c0 01 00 	      \(p02\) br\.cond\.dpnt\.few b2
+     eac:	20 00 80 03       	            br\.cond\.dpnt\.few b2;;
+     eb0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     eb6:	00 10 00 c0 03 00 	      \(p02\) br\.cond\.dpnt\.few\.clr b2
+     ebc:	20 00 80 07       	            br\.cond\.dpnt\.few\.clr b2;;
+     ec0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     ec6:	00 10 00 c0 01 00 	      \(p02\) br\.cond\.dpnt\.few b2
+     ecc:	20 00 80 03       	            br\.cond\.dpnt\.few b2;;
+     ed0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     ed6:	00 10 00 c0 03 00 	      \(p02\) br\.cond\.dpnt\.few\.clr b2
+     edc:	20 00 80 07       	            br\.cond\.dpnt\.few\.clr b2;;
+     ee0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     ee6:	00 14 00 c0 01 00 	      \(p02\) br\.cond\.dpnt\.many b2
+     eec:	28 00 80 03       	            br\.cond\.dpnt\.many b2;;
+     ef0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+     ef6:	00 14 00 c0 03 00 	      \(p02\) br\.cond\.dpnt\.many\.clr b2
+     efc:	28 00 80 07       	            br\.cond\.dpnt\.many\.clr b2;;
+     f00:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     f06:	00 00 00 00 10 20 	            nop\.b 0x0
+     f0c:	20 00 80 00       	            br\.ia\.sptk\.few b2;;
+     f10:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     f16:	00 00 00 00 10 20 	            nop\.b 0x0
+     f1c:	20 00 80 04       	            br\.ia\.sptk\.few\.clr b2;;
+     f20:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     f26:	00 00 00 00 10 20 	            nop\.b 0x0
+     f2c:	20 00 80 00       	            br\.ia\.sptk\.few b2;;
+     f30:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     f36:	00 00 00 00 10 20 	            nop\.b 0x0
+     f3c:	20 00 80 04       	            br\.ia\.sptk\.few\.clr b2;;
+     f40:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     f46:	00 00 00 00 10 20 	            nop\.b 0x0
+     f4c:	28 00 80 00       	            br\.ia\.sptk\.many b2;;
+     f50:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     f56:	00 00 00 00 10 20 	            nop\.b 0x0
+     f5c:	28 00 80 04       	            br\.ia\.sptk\.many\.clr b2;;
+     f60:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     f66:	00 00 00 00 10 20 	            nop\.b 0x0
+     f6c:	20 00 80 01       	            br\.ia\.spnt\.few b2;;
+     f70:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     f76:	00 00 00 00 10 20 	            nop\.b 0x0
+     f7c:	20 00 80 05       	            br\.ia\.spnt\.few\.clr b2;;
+     f80:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     f86:	00 00 00 00 10 20 	            nop\.b 0x0
+     f8c:	20 00 80 01       	            br\.ia\.spnt\.few b2;;
+     f90:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     f96:	00 00 00 00 10 20 	            nop\.b 0x0
+     f9c:	20 00 80 05       	            br\.ia\.spnt\.few\.clr b2;;
+     fa0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     fa6:	00 00 00 00 10 20 	            nop\.b 0x0
+     fac:	28 00 80 01       	            br\.ia\.spnt\.many b2;;
+     fb0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     fb6:	00 00 00 00 10 20 	            nop\.b 0x0
+     fbc:	28 00 80 05       	            br\.ia\.spnt\.many\.clr b2;;
+     fc0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     fc6:	00 00 00 00 10 20 	            nop\.b 0x0
+     fcc:	20 00 80 02       	            br\.ia\.dptk\.few b2;;
+     fd0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     fd6:	00 00 00 00 10 20 	            nop\.b 0x0
+     fdc:	20 00 80 06       	            br\.ia\.dptk\.few\.clr b2;;
+     fe0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     fe6:	00 00 00 00 10 20 	            nop\.b 0x0
+     fec:	20 00 80 02       	            br\.ia\.dptk\.few b2;;
+     ff0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+     ff6:	00 00 00 00 10 20 	            nop\.b 0x0
+     ffc:	20 00 80 06       	            br\.ia\.dptk\.few\.clr b2;;
+    1000:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+    1006:	00 00 00 00 10 20 	            nop\.b 0x0
+    100c:	28 00 80 02       	            br\.ia\.dptk\.many b2;;
+    1010:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+    1016:	00 00 00 00 10 20 	            nop\.b 0x0
+    101c:	28 00 80 06       	            br\.ia\.dptk\.many\.clr b2;;
+    1020:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+    1026:	00 00 00 00 10 20 	            nop\.b 0x0
+    102c:	20 00 80 03       	            br\.ia\.dpnt\.few b2;;
+    1030:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+    1036:	00 00 00 00 10 20 	            nop\.b 0x0
+    103c:	20 00 80 07       	            br\.ia\.dpnt\.few\.clr b2;;
+    1040:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+    1046:	00 00 00 00 10 20 	            nop\.b 0x0
+    104c:	20 00 80 03       	            br\.ia\.dpnt\.few b2;;
+    1050:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+    1056:	00 00 00 00 10 20 	            nop\.b 0x0
+    105c:	20 00 80 07       	            br\.ia\.dpnt\.few\.clr b2;;
+    1060:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+    1066:	00 00 00 00 10 20 	            nop\.b 0x0
+    106c:	28 00 80 03       	            br\.ia\.dpnt\.many b2;;
+    1070:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+    1076:	00 00 00 00 10 20 	            nop\.b 0x0
+    107c:	28 00 80 07       	            br\.ia\.dpnt\.many\.clr b2;;
+    1080:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1086:	40 10 00 42 00 80 	      \(p02\) br\.ret\.sptk\.few b2
+    108c:	20 00 84 00       	            br\.ret\.sptk\.few b2;;
+    1090:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1096:	40 10 00 42 02 80 	      \(p02\) br\.ret\.sptk\.few\.clr b2
+    109c:	20 00 84 04       	            br\.ret\.sptk\.few\.clr b2;;
+    10a0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    10a6:	40 10 00 42 00 80 	      \(p02\) br\.ret\.sptk\.few b2
+    10ac:	20 00 84 00       	            br\.ret\.sptk\.few b2;;
+    10b0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    10b6:	40 10 00 42 02 80 	      \(p02\) br\.ret\.sptk\.few\.clr b2
+    10bc:	20 00 84 04       	            br\.ret\.sptk\.few\.clr b2;;
+    10c0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    10c6:	40 14 00 42 00 80 	      \(p02\) br\.ret\.sptk\.many b2
+    10cc:	28 00 84 00       	            br\.ret\.sptk\.many b2;;
+    10d0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    10d6:	40 14 00 42 02 80 	      \(p02\) br\.ret\.sptk\.many\.clr b2
+    10dc:	28 00 84 04       	            br\.ret\.sptk\.many\.clr b2;;
+    10e0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    10e6:	40 10 00 c2 00 80 	      \(p02\) br\.ret\.spnt\.few b2
+    10ec:	20 00 84 01       	            br\.ret\.spnt\.few b2;;
+    10f0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    10f6:	40 10 00 c2 02 80 	      \(p02\) br\.ret\.spnt\.few\.clr b2
+    10fc:	20 00 84 05       	            br\.ret\.spnt\.few\.clr b2;;
+    1100:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1106:	40 10 00 c2 00 80 	      \(p02\) br\.ret\.spnt\.few b2
+    110c:	20 00 84 01       	            br\.ret\.spnt\.few b2;;
+    1110:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1116:	40 10 00 c2 02 80 	      \(p02\) br\.ret\.spnt\.few\.clr b2
+    111c:	20 00 84 05       	            br\.ret\.spnt\.few\.clr b2;;
+    1120:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1126:	40 14 00 c2 00 80 	      \(p02\) br\.ret\.spnt\.many b2
+    112c:	28 00 84 01       	            br\.ret\.spnt\.many b2;;
+    1130:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1136:	40 14 00 c2 02 80 	      \(p02\) br\.ret\.spnt\.many\.clr b2
+    113c:	28 00 84 05       	            br\.ret\.spnt\.many\.clr b2;;
+    1140:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1146:	40 10 00 42 01 80 	      \(p02\) br\.ret\.dptk\.few b2
+    114c:	20 00 84 02       	            br\.ret\.dptk\.few b2;;
+    1150:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1156:	40 10 00 42 03 80 	      \(p02\) br\.ret\.dptk\.few\.clr b2
+    115c:	20 00 84 06       	            br\.ret\.dptk\.few\.clr b2;;
+    1160:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1166:	40 10 00 42 01 80 	      \(p02\) br\.ret\.dptk\.few b2
+    116c:	20 00 84 02       	            br\.ret\.dptk\.few b2;;
+    1170:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1176:	40 10 00 42 03 80 	      \(p02\) br\.ret\.dptk\.few\.clr b2
+    117c:	20 00 84 06       	            br\.ret\.dptk\.few\.clr b2;;
+    1180:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1186:	40 14 00 42 01 80 	      \(p02\) br\.ret\.dptk\.many b2
+    118c:	28 00 84 02       	            br\.ret\.dptk\.many b2;;
+    1190:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1196:	40 14 00 42 03 80 	      \(p02\) br\.ret\.dptk\.many\.clr b2
+    119c:	28 00 84 06       	            br\.ret\.dptk\.many\.clr b2;;
+    11a0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    11a6:	40 10 00 c2 01 80 	      \(p02\) br\.ret\.dpnt\.few b2
+    11ac:	20 00 84 03       	            br\.ret\.dpnt\.few b2;;
+    11b0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    11b6:	40 10 00 c2 03 80 	      \(p02\) br\.ret\.dpnt\.few\.clr b2
+    11bc:	20 00 84 07       	            br\.ret\.dpnt\.few\.clr b2;;
+    11c0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    11c6:	40 10 00 c2 01 80 	      \(p02\) br\.ret\.dpnt\.few b2
+    11cc:	20 00 84 03       	            br\.ret\.dpnt\.few b2;;
+    11d0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    11d6:	40 10 00 c2 03 80 	      \(p02\) br\.ret\.dpnt\.few\.clr b2
+    11dc:	20 00 84 07       	            br\.ret\.dpnt\.few\.clr b2;;
+    11e0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    11e6:	40 14 00 c2 01 80 	      \(p02\) br\.ret\.dpnt\.many b2
+    11ec:	28 00 84 03       	            br\.ret\.dpnt\.many b2;;
+    11f0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    11f6:	40 14 00 c2 03 80 	      \(p02\) br\.ret\.dpnt\.many\.clr b2
+    11fc:	28 00 84 07       	            br\.ret\.dpnt\.many\.clr b2;;
+    1200:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1206:	00 10 00 00 08 00 	      \(p02\) br\.call\.sptk\.few b0=b2
+    120c:	20 00 00 10       	            br\.call\.sptk\.few b0=b2;;
+    1210:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1216:	00 10 00 00 0a 00 	      \(p02\) br\.call\.sptk\.few\.clr b0=b2
+    121c:	20 00 00 14       	            br\.call\.sptk\.few\.clr b0=b2;;
+    1220:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1226:	00 10 00 00 08 00 	      \(p02\) br\.call\.sptk\.few b0=b2
+    122c:	20 00 00 10       	            br\.call\.sptk\.few b0=b2;;
+    1230:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1236:	00 10 00 00 0a 00 	      \(p02\) br\.call\.sptk\.few\.clr b0=b2
+    123c:	20 00 00 14       	            br\.call\.sptk\.few\.clr b0=b2;;
+    1240:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1246:	00 14 00 00 08 00 	      \(p02\) br\.call\.sptk\.many b0=b2
+    124c:	28 00 00 10       	            br\.call\.sptk\.many b0=b2;;
+    1250:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1256:	00 14 00 00 0a 00 	      \(p02\) br\.call\.sptk\.many\.clr b0=b2
+    125c:	28 00 00 14       	            br\.call\.sptk\.many\.clr b0=b2;;
+    1260:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1266:	00 10 00 80 08 00 	      \(p02\) br\.call\.spnt\.few b0=b2
+    126c:	20 00 00 11       	            br\.call\.spnt\.few b0=b2;;
+    1270:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1276:	00 10 00 80 0a 00 	      \(p02\) br\.call\.spnt\.few\.clr b0=b2
+    127c:	20 00 00 15       	            br\.call\.spnt\.few\.clr b0=b2;;
+    1280:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1286:	00 10 00 80 08 00 	      \(p02\) br\.call\.spnt\.few b0=b2
+    128c:	20 00 00 11       	            br\.call\.spnt\.few b0=b2;;
+    1290:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1296:	00 10 00 80 0a 00 	      \(p02\) br\.call\.spnt\.few\.clr b0=b2
+    129c:	20 00 00 15       	            br\.call\.spnt\.few\.clr b0=b2;;
+    12a0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    12a6:	00 14 00 80 08 00 	      \(p02\) br\.call\.spnt\.many b0=b2
+    12ac:	28 00 00 11       	            br\.call\.spnt\.many b0=b2;;
+    12b0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    12b6:	00 14 00 80 0a 00 	      \(p02\) br\.call\.spnt\.many\.clr b0=b2
+    12bc:	28 00 00 15       	            br\.call\.spnt\.many\.clr b0=b2;;
+    12c0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    12c6:	00 10 00 00 09 00 	      \(p02\) br\.call\.dptk\.few b0=b2
+    12cc:	20 00 00 12       	            br\.call\.dptk\.few b0=b2;;
+    12d0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    12d6:	00 10 00 00 0b 00 	      \(p02\) br\.call\.dptk\.few\.clr b0=b2
+    12dc:	20 00 00 16       	            br\.call\.dptk\.few\.clr b0=b2;;
+    12e0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    12e6:	00 10 00 00 09 00 	      \(p02\) br\.call\.dptk\.few b0=b2
+    12ec:	20 00 00 12       	            br\.call\.dptk\.few b0=b2;;
+    12f0:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    12f6:	00 10 00 00 0b 00 	      \(p02\) br\.call\.dptk\.few\.clr b0=b2
+    12fc:	20 00 00 16       	            br\.call\.dptk\.few\.clr b0=b2;;
+    1300:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1306:	00 14 00 00 09 00 	      \(p02\) br\.call\.dptk\.many b0=b2
+    130c:	28 00 00 12       	            br\.call\.dptk\.many b0=b2;;
+    1310:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1316:	00 14 00 00 0b 00 	      \(p02\) br\.call\.dptk\.many\.clr b0=b2
+    131c:	28 00 00 16       	            br\.call\.dptk\.many\.clr b0=b2;;
+    1320:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1326:	00 10 00 80 09 00 	      \(p02\) br\.call\.dpnt\.few b0=b2
+    132c:	20 00 00 13       	            br\.call\.dpnt\.few b0=b2;;
+    1330:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1336:	00 10 00 80 0b 00 	      \(p02\) br\.call\.dpnt\.few\.clr b0=b2
+    133c:	20 00 00 17       	            br\.call\.dpnt\.few\.clr b0=b2;;
+    1340:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1346:	00 10 00 80 09 00 	      \(p02\) br\.call\.dpnt\.few b0=b2
+    134c:	20 00 00 13       	            br\.call\.dpnt\.few b0=b2;;
+    1350:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1356:	00 10 00 80 0b 00 	      \(p02\) br\.call\.dpnt\.few\.clr b0=b2
+    135c:	20 00 00 17       	            br\.call\.dpnt\.few\.clr b0=b2;;
+    1360:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1366:	00 14 00 80 09 00 	      \(p02\) br\.call\.dpnt\.many b0=b2
+    136c:	28 00 00 13       	            br\.call\.dpnt\.many b0=b2;;
+    1370:	17 00 00 00 00 88 	\[BBB\]       nop\.b 0x0
+    1376:	00 14 00 80 0b 00 	      \(p02\) br\.call\.dpnt\.many\.clr b0=b2
+    137c:	28 00 00 17       	            br\.call\.dpnt\.many\.clr b0=b2;;
+    1380:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    1386:	00 00 00 00 10 40 	            nop\.b 0x0
+    138c:	80 ec ff 78       	            brp\.sptk 0x0,0x13a0;;
+    1390:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    1396:	00 00 00 00 10 20 	            nop\.b 0x0
+    139c:	70 ec ff 7c       	            brp\.sptk\.imp 0x0,0x13a0;;
+    13a0:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    13a6:	00 00 00 00 10 44 	            nop\.b 0x0
+    13ac:	60 ec ff 78       	            brp\.loop 0x0,0x13c0;;
+    13b0:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    13b6:	00 00 00 00 10 24 	            nop\.b 0x0
+    13bc:	50 ec ff 7c       	            brp\.loop\.imp 0x0,0x13c0;;
+    13c0:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    13c6:	00 00 00 00 10 48 	            nop\.b 0x0
+    13cc:	40 ec ff 78       	            brp\.dptk 0x0,0x13e0;;
+    13d0:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    13d6:	00 00 00 00 10 28 	            nop\.b 0x0
+    13dc:	30 ec ff 7c       	            brp\.dptk\.imp 0x0,0x13e0;;
+    13e0:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    13e6:	00 00 00 00 10 4c 	            nop\.b 0x0
+    13ec:	20 ec ff 78       	            brp\.exit 0x0,0x1400;;
+    13f0:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    13f6:	00 00 00 00 10 2c 	            nop\.b 0x0
+    13fc:	10 ec ff 7c       	            brp\.exit\.imp 0x0,0x1400;;
+    1400:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    1406:	00 00 00 00 10 40 	            nop\.b 0x0
+    140c:	30 00 40 20       	            brp\.sptk b3,0x1420;;
+    1410:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    1416:	00 00 00 00 10 20 	            nop\.b 0x0
+    141c:	30 00 40 24       	            brp\.sptk\.imp b3,0x1420;;
+    1420:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    1426:	00 00 00 00 10 48 	            nop\.b 0x0
+    142c:	30 00 40 20       	            brp\.dptk b3,0x1440;;
+    1430:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    1436:	00 00 00 00 10 28 	            nop\.b 0x0
+    143c:	30 00 40 24       	            brp\.dptk.imp b3,0x1440;;
+    1440:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    1446:	00 00 00 00 10 40 	            nop\.b 0x0
+    144c:	30 00 44 20       	            brp\.ret\.sptk b3,0x1460;;
+    1450:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    1456:	00 00 00 00 10 20 	            nop\.b 0x0
+    145c:	30 00 44 24       	            brp\.ret\.sptk\.imp b3,0x1460;;
+    1460:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    1466:	00 00 00 00 10 48 	            nop\.b 0x0
+    146c:	30 00 44 20       	            brp\.ret\.dptk b3,0x1480;;
+    1470:	17 00 00 00 00 00 	\[BBB\]       break\.b 0x0
+    1476:	00 00 00 00 10 28 	            nop\.b 0x0
+    147c:	30 00 44 24       	            brp\.ret\.dptk.imp b3,0x1480;;
+	\.\.\.
+    2b80:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+    2b86:	00 00 00 00 10 00 	            nop\.b 0x0
+    2b8c:	00 00 08 00       	            cover;;
+    2b90:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+    2b96:	00 00 00 00 10 00 	            nop\.b 0x0
+    2b9c:	00 00 10 00       	            clrrrb;;
+    2ba0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+    2ba6:	00 00 00 00 10 00 	            nop\.b 0x0
+    2bac:	00 00 14 00       	            clrrrb\.pr;;
+    2bb0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+    2bb6:	00 00 00 00 10 00 	            nop\.b 0x0
+    2bbc:	00 00 20 00       	            rfi;;
+    2bc0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+    2bc6:	00 00 00 00 10 00 	            nop\.b 0x0
+    2bcc:	00 00 30 00       	            bsw\.0;;
+    2bd0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+    2bd6:	00 00 00 00 10 00 	            nop\.b 0x0
+    2bdc:	00 00 34 00       	            bsw\.1;;
+    2be0:	17 00 00 00 00 08 	\[BBB\]       nop\.b 0x0
+    2be6:	00 00 00 00 10 00 	            nop\.b 0x0
+    2bec:	00 00 40 00       	            epc;;
diff --git a/gas/testsuite/gas/ia64/opc-b.pl b/gas/testsuite/gas/ia64/opc-b.pl
new file mode 100644
index 0000000..bdfdd36
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-b.pl
@@ -0,0 +1,95 @@
+@ph = ( "", ".few", ".many" );
+@bwh = ( ".sptk", ".spnt", ".dptk", ".dpnt" );
+@dh = ( "", ".clr" );
+
+@iprel = ( ".cond", ".wexit", ".wtop", ".cloop", ".cexit", ".ctop", ".call" );
+@indir = ( ".cond", ".ia", ".ret", ".call" );
+%noqual = ( ".ia", 1, ".cloop", 1, ".ctop", 1, ".cexit", 1 );
+%slottwo = ( ".cloop", 1, ".ctop", 1, ".cexit", 1, ".wtop", 1, ".wexit", 1 );
+
+print ".L0:\n\n";
+
+foreach $i (@iprel) {
+  $call = ($i eq ".call" ? "b0 = " : "");
+  foreach $b (@bwh) {
+    foreach $p (@ph) {
+      foreach $d (@dh) {
+	if ($slottwo{$i}) {
+	  if (!$noqual{$i}) {
+	    print ("\t{ .bbb; (p2) br${i}${b}${p}${d} ${call}.L1 ;; }\n");
+	  }
+	  print ("\t{ .bbb; br${i}${b}${p}${d} ${call}.L1 ;; }\n");
+	} else {
+	  print ("\t{ .bbb; nop.b 0\n");
+	  if (!$noqual{$i}) {
+	    print ("(p2)\tbr${i}${b}${p}${d} ${call}.L1\n");
+	  } else {
+	    print ("\tnop.b 0\n");
+	  }
+	  print ("\tbr${i}${b}${p}${d} ${call}.L0\n");
+	  print ("\t;; }\n");
+	}
+      }
+    }
+  }
+  print "\n";
+}
+
+foreach $i (@indir) {
+  $call = ($i eq ".call" ? "b0 = " : "");
+  foreach $b (@bwh) {
+    foreach $p (@ph) {
+      foreach $d (@dh) {
+	print ("\t{ .bbb; nop.b 0;\n");
+	if (!$noqual{$i}) {
+	  print ("(p2)\tbr${i}${b}${p}${d} ${call}b2\n");
+	} else {
+	  print ("\tnop.b 0\n");
+	}
+	print ("\tbr${i}${b}${p}${d} ${call}b2\n");
+	print ("\t;; }\n");
+      }
+    }
+  }
+  print "\n";
+}
+
+@ih = ( "", ".imp" );
+@ipwh = ( ".sptk", ".loop", ".dptk", ".exit" );
+@indwh = ( ".sptk", ".dptk" );
+
+$CTR = 2;
+
+foreach $w (@ipwh) {
+  foreach $i (@ih) {
+    print ("\t{ .bbb; break.b 0; nop.b 0\n");
+    print ("\tbrp${w}${i} .L0, .L${CTR}\n");
+    print ("\t;; }\n");
+  }
+  print (".L${CTR}:\n");
+  ++$CTR;
+}
+
+print "\n";
+
+foreach $b ("", ".ret") {
+  foreach $w (@indwh) {
+    foreach $i (@ih) {
+      print ("\t{ .bbb; break.b 0; nop.b 0\n");
+      print ("\tbrp${b}${w}${i} b3, .L${CTR}\n");
+      print ("\t;; }\n");
+    }
+    print (".L${CTR}:\n");
+    ++$CTR;
+  }
+  print "\n";
+}
+
+print ".space 5888\n";
+
+@last = ( "cover", "clrrrb", "clrrrb.pr", "rfi", "bsw.0", "bsw.1", "epc" );
+foreach $i (@last) {
+  print "\t{ .bbb; nop.b 0; nop.b 0; $i ;; }\n";
+}
+
+print "\n.L1:\n";
diff --git a/gas/testsuite/gas/ia64/opc-b.s b/gas/testsuite/gas/ia64/opc-b.s
new file mode 100644
index 0000000..00c7769
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-b.s
@@ -0,0 +1,826 @@
+.L0:
+
+	{ .bbb; nop.b 0
+(p2)	br.cond.sptk .L1
+	br.cond.sptk .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.sptk.clr .L1
+	br.cond.sptk.clr .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.sptk.few .L1
+	br.cond.sptk.few .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.sptk.few.clr .L1
+	br.cond.sptk.few.clr .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.sptk.many .L1
+	br.cond.sptk.many .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.sptk.many.clr .L1
+	br.cond.sptk.many.clr .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.spnt .L1
+	br.cond.spnt .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.spnt.clr .L1
+	br.cond.spnt.clr .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.spnt.few .L1
+	br.cond.spnt.few .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.spnt.few.clr .L1
+	br.cond.spnt.few.clr .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.spnt.many .L1
+	br.cond.spnt.many .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.spnt.many.clr .L1
+	br.cond.spnt.many.clr .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.dptk .L1
+	br.cond.dptk .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.dptk.clr .L1
+	br.cond.dptk.clr .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.dptk.few .L1
+	br.cond.dptk.few .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.dptk.few.clr .L1
+	br.cond.dptk.few.clr .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.dptk.many .L1
+	br.cond.dptk.many .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.dptk.many.clr .L1
+	br.cond.dptk.many.clr .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.dpnt .L1
+	br.cond.dpnt .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.dpnt.clr .L1
+	br.cond.dpnt.clr .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.dpnt.few .L1
+	br.cond.dpnt.few .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.dpnt.few.clr .L1
+	br.cond.dpnt.few.clr .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.dpnt.many .L1
+	br.cond.dpnt.many .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.cond.dpnt.many.clr .L1
+	br.cond.dpnt.many.clr .L0
+	;; }
+
+	{ .bbb; (p2) br.wexit.sptk .L1 ;; }
+	{ .bbb; br.wexit.sptk .L1 ;; }
+	{ .bbb; (p2) br.wexit.sptk.clr .L1 ;; }
+	{ .bbb; br.wexit.sptk.clr .L1 ;; }
+	{ .bbb; (p2) br.wexit.sptk.few .L1 ;; }
+	{ .bbb; br.wexit.sptk.few .L1 ;; }
+	{ .bbb; (p2) br.wexit.sptk.few.clr .L1 ;; }
+	{ .bbb; br.wexit.sptk.few.clr .L1 ;; }
+	{ .bbb; (p2) br.wexit.sptk.many .L1 ;; }
+	{ .bbb; br.wexit.sptk.many .L1 ;; }
+	{ .bbb; (p2) br.wexit.sptk.many.clr .L1 ;; }
+	{ .bbb; br.wexit.sptk.many.clr .L1 ;; }
+	{ .bbb; (p2) br.wexit.spnt .L1 ;; }
+	{ .bbb; br.wexit.spnt .L1 ;; }
+	{ .bbb; (p2) br.wexit.spnt.clr .L1 ;; }
+	{ .bbb; br.wexit.spnt.clr .L1 ;; }
+	{ .bbb; (p2) br.wexit.spnt.few .L1 ;; }
+	{ .bbb; br.wexit.spnt.few .L1 ;; }
+	{ .bbb; (p2) br.wexit.spnt.few.clr .L1 ;; }
+	{ .bbb; br.wexit.spnt.few.clr .L1 ;; }
+	{ .bbb; (p2) br.wexit.spnt.many .L1 ;; }
+	{ .bbb; br.wexit.spnt.many .L1 ;; }
+	{ .bbb; (p2) br.wexit.spnt.many.clr .L1 ;; }
+	{ .bbb; br.wexit.spnt.many.clr .L1 ;; }
+	{ .bbb; (p2) br.wexit.dptk .L1 ;; }
+	{ .bbb; br.wexit.dptk .L1 ;; }
+	{ .bbb; (p2) br.wexit.dptk.clr .L1 ;; }
+	{ .bbb; br.wexit.dptk.clr .L1 ;; }
+	{ .bbb; (p2) br.wexit.dptk.few .L1 ;; }
+	{ .bbb; br.wexit.dptk.few .L1 ;; }
+	{ .bbb; (p2) br.wexit.dptk.few.clr .L1 ;; }
+	{ .bbb; br.wexit.dptk.few.clr .L1 ;; }
+	{ .bbb; (p2) br.wexit.dptk.many .L1 ;; }
+	{ .bbb; br.wexit.dptk.many .L1 ;; }
+	{ .bbb; (p2) br.wexit.dptk.many.clr .L1 ;; }
+	{ .bbb; br.wexit.dptk.many.clr .L1 ;; }
+	{ .bbb; (p2) br.wexit.dpnt .L1 ;; }
+	{ .bbb; br.wexit.dpnt .L1 ;; }
+	{ .bbb; (p2) br.wexit.dpnt.clr .L1 ;; }
+	{ .bbb; br.wexit.dpnt.clr .L1 ;; }
+	{ .bbb; (p2) br.wexit.dpnt.few .L1 ;; }
+	{ .bbb; br.wexit.dpnt.few .L1 ;; }
+	{ .bbb; (p2) br.wexit.dpnt.few.clr .L1 ;; }
+	{ .bbb; br.wexit.dpnt.few.clr .L1 ;; }
+	{ .bbb; (p2) br.wexit.dpnt.many .L1 ;; }
+	{ .bbb; br.wexit.dpnt.many .L1 ;; }
+	{ .bbb; (p2) br.wexit.dpnt.many.clr .L1 ;; }
+	{ .bbb; br.wexit.dpnt.many.clr .L1 ;; }
+
+	{ .bbb; (p2) br.wtop.sptk .L1 ;; }
+	{ .bbb; br.wtop.sptk .L1 ;; }
+	{ .bbb; (p2) br.wtop.sptk.clr .L1 ;; }
+	{ .bbb; br.wtop.sptk.clr .L1 ;; }
+	{ .bbb; (p2) br.wtop.sptk.few .L1 ;; }
+	{ .bbb; br.wtop.sptk.few .L1 ;; }
+	{ .bbb; (p2) br.wtop.sptk.few.clr .L1 ;; }
+	{ .bbb; br.wtop.sptk.few.clr .L1 ;; }
+	{ .bbb; (p2) br.wtop.sptk.many .L1 ;; }
+	{ .bbb; br.wtop.sptk.many .L1 ;; }
+	{ .bbb; (p2) br.wtop.sptk.many.clr .L1 ;; }
+	{ .bbb; br.wtop.sptk.many.clr .L1 ;; }
+	{ .bbb; (p2) br.wtop.spnt .L1 ;; }
+	{ .bbb; br.wtop.spnt .L1 ;; }
+	{ .bbb; (p2) br.wtop.spnt.clr .L1 ;; }
+	{ .bbb; br.wtop.spnt.clr .L1 ;; }
+	{ .bbb; (p2) br.wtop.spnt.few .L1 ;; }
+	{ .bbb; br.wtop.spnt.few .L1 ;; }
+	{ .bbb; (p2) br.wtop.spnt.few.clr .L1 ;; }
+	{ .bbb; br.wtop.spnt.few.clr .L1 ;; }
+	{ .bbb; (p2) br.wtop.spnt.many .L1 ;; }
+	{ .bbb; br.wtop.spnt.many .L1 ;; }
+	{ .bbb; (p2) br.wtop.spnt.many.clr .L1 ;; }
+	{ .bbb; br.wtop.spnt.many.clr .L1 ;; }
+	{ .bbb; (p2) br.wtop.dptk .L1 ;; }
+	{ .bbb; br.wtop.dptk .L1 ;; }
+	{ .bbb; (p2) br.wtop.dptk.clr .L1 ;; }
+	{ .bbb; br.wtop.dptk.clr .L1 ;; }
+	{ .bbb; (p2) br.wtop.dptk.few .L1 ;; }
+	{ .bbb; br.wtop.dptk.few .L1 ;; }
+	{ .bbb; (p2) br.wtop.dptk.few.clr .L1 ;; }
+	{ .bbb; br.wtop.dptk.few.clr .L1 ;; }
+	{ .bbb; (p2) br.wtop.dptk.many .L1 ;; }
+	{ .bbb; br.wtop.dptk.many .L1 ;; }
+	{ .bbb; (p2) br.wtop.dptk.many.clr .L1 ;; }
+	{ .bbb; br.wtop.dptk.many.clr .L1 ;; }
+	{ .bbb; (p2) br.wtop.dpnt .L1 ;; }
+	{ .bbb; br.wtop.dpnt .L1 ;; }
+	{ .bbb; (p2) br.wtop.dpnt.clr .L1 ;; }
+	{ .bbb; br.wtop.dpnt.clr .L1 ;; }
+	{ .bbb; (p2) br.wtop.dpnt.few .L1 ;; }
+	{ .bbb; br.wtop.dpnt.few .L1 ;; }
+	{ .bbb; (p2) br.wtop.dpnt.few.clr .L1 ;; }
+	{ .bbb; br.wtop.dpnt.few.clr .L1 ;; }
+	{ .bbb; (p2) br.wtop.dpnt.many .L1 ;; }
+	{ .bbb; br.wtop.dpnt.many .L1 ;; }
+	{ .bbb; (p2) br.wtop.dpnt.many.clr .L1 ;; }
+	{ .bbb; br.wtop.dpnt.many.clr .L1 ;; }
+
+	{ .bbb; br.cloop.sptk .L1 ;; }
+	{ .bbb; br.cloop.sptk.clr .L1 ;; }
+	{ .bbb; br.cloop.sptk.few .L1 ;; }
+	{ .bbb; br.cloop.sptk.few.clr .L1 ;; }
+	{ .bbb; br.cloop.sptk.many .L1 ;; }
+	{ .bbb; br.cloop.sptk.many.clr .L1 ;; }
+	{ .bbb; br.cloop.spnt .L1 ;; }
+	{ .bbb; br.cloop.spnt.clr .L1 ;; }
+	{ .bbb; br.cloop.spnt.few .L1 ;; }
+	{ .bbb; br.cloop.spnt.few.clr .L1 ;; }
+	{ .bbb; br.cloop.spnt.many .L1 ;; }
+	{ .bbb; br.cloop.spnt.many.clr .L1 ;; }
+	{ .bbb; br.cloop.dptk .L1 ;; }
+	{ .bbb; br.cloop.dptk.clr .L1 ;; }
+	{ .bbb; br.cloop.dptk.few .L1 ;; }
+	{ .bbb; br.cloop.dptk.few.clr .L1 ;; }
+	{ .bbb; br.cloop.dptk.many .L1 ;; }
+	{ .bbb; br.cloop.dptk.many.clr .L1 ;; }
+	{ .bbb; br.cloop.dpnt .L1 ;; }
+	{ .bbb; br.cloop.dpnt.clr .L1 ;; }
+	{ .bbb; br.cloop.dpnt.few .L1 ;; }
+	{ .bbb; br.cloop.dpnt.few.clr .L1 ;; }
+	{ .bbb; br.cloop.dpnt.many .L1 ;; }
+	{ .bbb; br.cloop.dpnt.many.clr .L1 ;; }
+
+	{ .bbb; br.cexit.sptk .L1 ;; }
+	{ .bbb; br.cexit.sptk.clr .L1 ;; }
+	{ .bbb; br.cexit.sptk.few .L1 ;; }
+	{ .bbb; br.cexit.sptk.few.clr .L1 ;; }
+	{ .bbb; br.cexit.sptk.many .L1 ;; }
+	{ .bbb; br.cexit.sptk.many.clr .L1 ;; }
+	{ .bbb; br.cexit.spnt .L1 ;; }
+	{ .bbb; br.cexit.spnt.clr .L1 ;; }
+	{ .bbb; br.cexit.spnt.few .L1 ;; }
+	{ .bbb; br.cexit.spnt.few.clr .L1 ;; }
+	{ .bbb; br.cexit.spnt.many .L1 ;; }
+	{ .bbb; br.cexit.spnt.many.clr .L1 ;; }
+	{ .bbb; br.cexit.dptk .L1 ;; }
+	{ .bbb; br.cexit.dptk.clr .L1 ;; }
+	{ .bbb; br.cexit.dptk.few .L1 ;; }
+	{ .bbb; br.cexit.dptk.few.clr .L1 ;; }
+	{ .bbb; br.cexit.dptk.many .L1 ;; }
+	{ .bbb; br.cexit.dptk.many.clr .L1 ;; }
+	{ .bbb; br.cexit.dpnt .L1 ;; }
+	{ .bbb; br.cexit.dpnt.clr .L1 ;; }
+	{ .bbb; br.cexit.dpnt.few .L1 ;; }
+	{ .bbb; br.cexit.dpnt.few.clr .L1 ;; }
+	{ .bbb; br.cexit.dpnt.many .L1 ;; }
+	{ .bbb; br.cexit.dpnt.many.clr .L1 ;; }
+
+	{ .bbb; br.ctop.sptk .L1 ;; }
+	{ .bbb; br.ctop.sptk.clr .L1 ;; }
+	{ .bbb; br.ctop.sptk.few .L1 ;; }
+	{ .bbb; br.ctop.sptk.few.clr .L1 ;; }
+	{ .bbb; br.ctop.sptk.many .L1 ;; }
+	{ .bbb; br.ctop.sptk.many.clr .L1 ;; }
+	{ .bbb; br.ctop.spnt .L1 ;; }
+	{ .bbb; br.ctop.spnt.clr .L1 ;; }
+	{ .bbb; br.ctop.spnt.few .L1 ;; }
+	{ .bbb; br.ctop.spnt.few.clr .L1 ;; }
+	{ .bbb; br.ctop.spnt.many .L1 ;; }
+	{ .bbb; br.ctop.spnt.many.clr .L1 ;; }
+	{ .bbb; br.ctop.dptk .L1 ;; }
+	{ .bbb; br.ctop.dptk.clr .L1 ;; }
+	{ .bbb; br.ctop.dptk.few .L1 ;; }
+	{ .bbb; br.ctop.dptk.few.clr .L1 ;; }
+	{ .bbb; br.ctop.dptk.many .L1 ;; }
+	{ .bbb; br.ctop.dptk.many.clr .L1 ;; }
+	{ .bbb; br.ctop.dpnt .L1 ;; }
+	{ .bbb; br.ctop.dpnt.clr .L1 ;; }
+	{ .bbb; br.ctop.dpnt.few .L1 ;; }
+	{ .bbb; br.ctop.dpnt.few.clr .L1 ;; }
+	{ .bbb; br.ctop.dpnt.many .L1 ;; }
+	{ .bbb; br.ctop.dpnt.many.clr .L1 ;; }
+
+	{ .bbb; nop.b 0
+(p2)	br.call.sptk b0 = .L1
+	br.call.sptk b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.sptk.clr b0 = .L1
+	br.call.sptk.clr b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.sptk.few b0 = .L1
+	br.call.sptk.few b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.sptk.few.clr b0 = .L1
+	br.call.sptk.few.clr b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.sptk.many b0 = .L1
+	br.call.sptk.many b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.sptk.many.clr b0 = .L1
+	br.call.sptk.many.clr b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.spnt b0 = .L1
+	br.call.spnt b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.spnt.clr b0 = .L1
+	br.call.spnt.clr b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.spnt.few b0 = .L1
+	br.call.spnt.few b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.spnt.few.clr b0 = .L1
+	br.call.spnt.few.clr b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.spnt.many b0 = .L1
+	br.call.spnt.many b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.spnt.many.clr b0 = .L1
+	br.call.spnt.many.clr b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.dptk b0 = .L1
+	br.call.dptk b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.dptk.clr b0 = .L1
+	br.call.dptk.clr b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.dptk.few b0 = .L1
+	br.call.dptk.few b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.dptk.few.clr b0 = .L1
+	br.call.dptk.few.clr b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.dptk.many b0 = .L1
+	br.call.dptk.many b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.dptk.many.clr b0 = .L1
+	br.call.dptk.many.clr b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.dpnt b0 = .L1
+	br.call.dpnt b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.dpnt.clr b0 = .L1
+	br.call.dpnt.clr b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.dpnt.few b0 = .L1
+	br.call.dpnt.few b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.dpnt.few.clr b0 = .L1
+	br.call.dpnt.few.clr b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.dpnt.many b0 = .L1
+	br.call.dpnt.many b0 = .L0
+	;; }
+	{ .bbb; nop.b 0
+(p2)	br.call.dpnt.many.clr b0 = .L1
+	br.call.dpnt.many.clr b0 = .L0
+	;; }
+
+	{ .bbb; nop.b 0;
+(p2)	br.cond.sptk b2
+	br.cond.sptk b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.sptk.clr b2
+	br.cond.sptk.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.sptk.few b2
+	br.cond.sptk.few b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.sptk.few.clr b2
+	br.cond.sptk.few.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.sptk.many b2
+	br.cond.sptk.many b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.sptk.many.clr b2
+	br.cond.sptk.many.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.spnt b2
+	br.cond.spnt b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.spnt.clr b2
+	br.cond.spnt.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.spnt.few b2
+	br.cond.spnt.few b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.spnt.few.clr b2
+	br.cond.spnt.few.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.spnt.many b2
+	br.cond.spnt.many b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.spnt.many.clr b2
+	br.cond.spnt.many.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.dptk b2
+	br.cond.dptk b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.dptk.clr b2
+	br.cond.dptk.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.dptk.few b2
+	br.cond.dptk.few b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.dptk.few.clr b2
+	br.cond.dptk.few.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.dptk.many b2
+	br.cond.dptk.many b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.dptk.many.clr b2
+	br.cond.dptk.many.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.dpnt b2
+	br.cond.dpnt b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.dpnt.clr b2
+	br.cond.dpnt.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.dpnt.few b2
+	br.cond.dpnt.few b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.dpnt.few.clr b2
+	br.cond.dpnt.few.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.dpnt.many b2
+	br.cond.dpnt.many b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.cond.dpnt.many.clr b2
+	br.cond.dpnt.many.clr b2
+	;; }
+
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.sptk b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.sptk.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.sptk.few b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.sptk.few.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.sptk.many b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.sptk.many.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.spnt b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.spnt.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.spnt.few b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.spnt.few.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.spnt.many b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.spnt.many.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.dptk b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.dptk.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.dptk.few b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.dptk.few.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.dptk.many b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.dptk.many.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.dpnt b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.dpnt.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.dpnt.few b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.dpnt.few.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.dpnt.many b2
+	;; }
+	{ .bbb; nop.b 0;
+	nop.b 0
+	br.ia.dpnt.many.clr b2
+	;; }
+
+	{ .bbb; nop.b 0;
+(p2)	br.ret.sptk b2
+	br.ret.sptk b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.sptk.clr b2
+	br.ret.sptk.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.sptk.few b2
+	br.ret.sptk.few b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.sptk.few.clr b2
+	br.ret.sptk.few.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.sptk.many b2
+	br.ret.sptk.many b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.sptk.many.clr b2
+	br.ret.sptk.many.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.spnt b2
+	br.ret.spnt b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.spnt.clr b2
+	br.ret.spnt.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.spnt.few b2
+	br.ret.spnt.few b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.spnt.few.clr b2
+	br.ret.spnt.few.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.spnt.many b2
+	br.ret.spnt.many b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.spnt.many.clr b2
+	br.ret.spnt.many.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.dptk b2
+	br.ret.dptk b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.dptk.clr b2
+	br.ret.dptk.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.dptk.few b2
+	br.ret.dptk.few b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.dptk.few.clr b2
+	br.ret.dptk.few.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.dptk.many b2
+	br.ret.dptk.many b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.dptk.many.clr b2
+	br.ret.dptk.many.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.dpnt b2
+	br.ret.dpnt b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.dpnt.clr b2
+	br.ret.dpnt.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.dpnt.few b2
+	br.ret.dpnt.few b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.dpnt.few.clr b2
+	br.ret.dpnt.few.clr b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.dpnt.many b2
+	br.ret.dpnt.many b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.ret.dpnt.many.clr b2
+	br.ret.dpnt.many.clr b2
+	;; }
+
+	{ .bbb; nop.b 0;
+(p2)	br.call.sptk b0 = b2
+	br.call.sptk b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.sptk.clr b0 = b2
+	br.call.sptk.clr b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.sptk.few b0 = b2
+	br.call.sptk.few b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.sptk.few.clr b0 = b2
+	br.call.sptk.few.clr b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.sptk.many b0 = b2
+	br.call.sptk.many b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.sptk.many.clr b0 = b2
+	br.call.sptk.many.clr b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.spnt b0 = b2
+	br.call.spnt b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.spnt.clr b0 = b2
+	br.call.spnt.clr b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.spnt.few b0 = b2
+	br.call.spnt.few b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.spnt.few.clr b0 = b2
+	br.call.spnt.few.clr b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.spnt.many b0 = b2
+	br.call.spnt.many b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.spnt.many.clr b0 = b2
+	br.call.spnt.many.clr b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.dptk b0 = b2
+	br.call.dptk b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.dptk.clr b0 = b2
+	br.call.dptk.clr b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.dptk.few b0 = b2
+	br.call.dptk.few b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.dptk.few.clr b0 = b2
+	br.call.dptk.few.clr b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.dptk.many b0 = b2
+	br.call.dptk.many b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.dptk.many.clr b0 = b2
+	br.call.dptk.many.clr b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.dpnt b0 = b2
+	br.call.dpnt b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.dpnt.clr b0 = b2
+	br.call.dpnt.clr b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.dpnt.few b0 = b2
+	br.call.dpnt.few b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.dpnt.few.clr b0 = b2
+	br.call.dpnt.few.clr b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.dpnt.many b0 = b2
+	br.call.dpnt.many b0 = b2
+	;; }
+	{ .bbb; nop.b 0;
+(p2)	br.call.dpnt.many.clr b0 = b2
+	br.call.dpnt.many.clr b0 = b2
+	;; }
+
+	{ .bbb; break.b 0; nop.b 0
+	brp.sptk .L0, .L2
+	;; }
+	{ .bbb; break.b 0; nop.b 0
+	brp.sptk.imp .L0, .L2
+	;; }
+.L2:
+	{ .bbb; break.b 0; nop.b 0
+	brp.loop .L0, .L3
+	;; }
+	{ .bbb; break.b 0; nop.b 0
+	brp.loop.imp .L0, .L3
+	;; }
+.L3:
+	{ .bbb; break.b 0; nop.b 0
+	brp.dptk .L0, .L4
+	;; }
+	{ .bbb; break.b 0; nop.b 0
+	brp.dptk.imp .L0, .L4
+	;; }
+.L4:
+	{ .bbb; break.b 0; nop.b 0
+	brp.exit .L0, .L5
+	;; }
+	{ .bbb; break.b 0; nop.b 0
+	brp.exit.imp .L0, .L5
+	;; }
+.L5:
+
+	{ .bbb; break.b 0; nop.b 0
+	brp.sptk b3, .L6
+	;; }
+	{ .bbb; break.b 0; nop.b 0
+	brp.sptk.imp b3, .L6
+	;; }
+.L6:
+	{ .bbb; break.b 0; nop.b 0
+	brp.dptk b3, .L7
+	;; }
+	{ .bbb; break.b 0; nop.b 0
+	brp.dptk.imp b3, .L7
+	;; }
+.L7:
+
+	{ .bbb; break.b 0; nop.b 0
+	brp.ret.sptk b3, .L8
+	;; }
+	{ .bbb; break.b 0; nop.b 0
+	brp.ret.sptk.imp b3, .L8
+	;; }
+.L8:
+	{ .bbb; break.b 0; nop.b 0
+	brp.ret.dptk b3, .L9
+	;; }
+	{ .bbb; break.b 0; nop.b 0
+	brp.ret.dptk.imp b3, .L9
+	;; }
+.L9:
+
+.space 5888
+	{ .bbb; nop.b 0; nop.b 0; cover ;; }
+	{ .bbb; nop.b 0; nop.b 0; clrrrb ;; }
+	{ .bbb; nop.b 0; nop.b 0; clrrrb.pr ;; }
+	{ .bbb; nop.b 0; nop.b 0; rfi ;; }
+	{ .bbb; nop.b 0; nop.b 0; bsw.0 ;; }
+	{ .bbb; nop.b 0; nop.b 0; bsw.1 ;; }
+	{ .bbb; nop.b 0; nop.b 0; epc ;; }
+
+.L1:
diff --git a/gas/testsuite/gas/ia64/opc-f.d b/gas/testsuite/gas/ia64/opc-f.d
new file mode 100644
index 0000000..0e69d3f
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-f.d
@@ -0,0 +1,1217 @@
+# objdump: -d
+# name: ia64 opc-f
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <_start>:
+       0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+       6:	40 38 14 0c 40 00 	            fma\.s0 f4=f5,f6,f7
+       c:	00 00 04 00       	            nop\.i 0x0
+      10:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+      16:	40 38 14 0c 40 00 	            fma\.s0 f4=f5,f6,f7
+      1c:	00 00 04 00       	            nop\.i 0x0
+      20:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+      26:	40 38 14 0c 41 00 	            fma\.s1 f4=f5,f6,f7
+      2c:	00 00 04 00       	            nop\.i 0x0
+      30:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+      36:	40 38 14 0c 42 00 	            fma\.s2 f4=f5,f6,f7
+      3c:	00 00 04 00       	            nop\.i 0x0
+      40:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+      46:	40 38 14 0c 43 00 	            fma\.s3 f4=f5,f6,f7
+      4c:	00 00 04 00       	            nop\.i 0x0
+      50:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+      56:	40 38 14 0c 44 00 	            fma\.s\.s0 f4=f5,f6,f7
+      5c:	00 00 04 00       	            nop\.i 0x0
+      60:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+      66:	40 38 14 0c 44 00 	            fma\.s\.s0 f4=f5,f6,f7
+      6c:	00 00 04 00       	            nop\.i 0x0
+      70:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+      76:	40 38 14 0c 45 00 	            fma\.s\.s1 f4=f5,f6,f7
+      7c:	00 00 04 00       	            nop\.i 0x0
+      80:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+      86:	40 38 14 0c 46 00 	            fma\.s\.s2 f4=f5,f6,f7
+      8c:	00 00 04 00       	            nop\.i 0x0
+      90:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+      96:	40 38 14 0c 47 00 	            fma\.s\.s3 f4=f5,f6,f7
+      9c:	00 00 04 00       	            nop\.i 0x0
+      a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+      a6:	40 38 14 0c 48 00 	            fma\.d\.s0 f4=f5,f6,f7
+      ac:	00 00 04 00       	            nop\.i 0x0
+      b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+      b6:	40 38 14 0c 48 00 	            fma\.d\.s0 f4=f5,f6,f7
+      bc:	00 00 04 00       	            nop\.i 0x0
+      c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+      c6:	40 38 14 0c 49 00 	            fma\.d\.s1 f4=f5,f6,f7
+      cc:	00 00 04 00       	            nop\.i 0x0
+      d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+      d6:	40 38 14 0c 4a 00 	            fma\.d\.s2 f4=f5,f6,f7
+      dc:	00 00 04 00       	            nop\.i 0x0
+      e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+      e6:	40 38 14 0c 4b 00 	            fma\.d\.s3 f4=f5,f6,f7
+      ec:	00 00 04 00       	            nop\.i 0x0
+      f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+      f6:	40 38 14 0c 4c 00 	            fpma\.s0 f4=f5,f6,f7
+      fc:	00 00 04 00       	            nop\.i 0x0
+     100:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     106:	40 38 14 0c 4c 00 	            fpma\.s0 f4=f5,f6,f7
+     10c:	00 00 04 00       	            nop\.i 0x0
+     110:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     116:	40 38 14 0c 4d 00 	            fpma\.s1 f4=f5,f6,f7
+     11c:	00 00 04 00       	            nop\.i 0x0
+     120:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     126:	40 38 14 0c 4e 00 	            fpma\.s2 f4=f5,f6,f7
+     12c:	00 00 04 00       	            nop\.i 0x0
+     130:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     136:	40 38 14 0c 4f 00 	            fpma\.s3 f4=f5,f6,f7
+     13c:	00 00 04 00       	            nop\.i 0x0
+     140:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     146:	40 38 14 0c 50 00 	            fms\.s0 f4=f5,f6,f7
+     14c:	00 00 04 00       	            nop\.i 0x0
+     150:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     156:	40 38 14 0c 50 00 	            fms\.s0 f4=f5,f6,f7
+     15c:	00 00 04 00       	            nop\.i 0x0
+     160:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     166:	40 38 14 0c 51 00 	            fms\.s1 f4=f5,f6,f7
+     16c:	00 00 04 00       	            nop\.i 0x0
+     170:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     176:	40 38 14 0c 52 00 	            fms\.s2 f4=f5,f6,f7
+     17c:	00 00 04 00       	            nop\.i 0x0
+     180:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     186:	40 38 14 0c 53 00 	            fms\.s3 f4=f5,f6,f7
+     18c:	00 00 04 00       	            nop\.i 0x0
+     190:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     196:	40 38 14 0c 54 00 	            fms\.s\.s0 f4=f5,f6,f7
+     19c:	00 00 04 00       	            nop\.i 0x0
+     1a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     1a6:	40 38 14 0c 54 00 	            fms\.s\.s0 f4=f5,f6,f7
+     1ac:	00 00 04 00       	            nop\.i 0x0
+     1b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     1b6:	40 38 14 0c 55 00 	            fms\.s\.s1 f4=f5,f6,f7
+     1bc:	00 00 04 00       	            nop\.i 0x0
+     1c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     1c6:	40 38 14 0c 56 00 	            fms\.s\.s2 f4=f5,f6,f7
+     1cc:	00 00 04 00       	            nop\.i 0x0
+     1d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     1d6:	40 38 14 0c 57 00 	            fms\.s\.s3 f4=f5,f6,f7
+     1dc:	00 00 04 00       	            nop\.i 0x0
+     1e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     1e6:	40 38 14 0c 58 00 	            fms\.d\.s0 f4=f5,f6,f7
+     1ec:	00 00 04 00       	            nop\.i 0x0
+     1f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     1f6:	40 38 14 0c 58 00 	            fms\.d\.s0 f4=f5,f6,f7
+     1fc:	00 00 04 00       	            nop\.i 0x0
+     200:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     206:	40 38 14 0c 59 00 	            fms\.d\.s1 f4=f5,f6,f7
+     20c:	00 00 04 00       	            nop\.i 0x0
+     210:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     216:	40 38 14 0c 5a 00 	            fms\.d\.s2 f4=f5,f6,f7
+     21c:	00 00 04 00       	            nop\.i 0x0
+     220:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     226:	40 38 14 0c 5b 00 	            fms\.d\.s3 f4=f5,f6,f7
+     22c:	00 00 04 00       	            nop\.i 0x0
+     230:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     236:	40 38 14 0c 5c 00 	            fpms\.s0 f4=f5,f6,f7
+     23c:	00 00 04 00       	            nop\.i 0x0
+     240:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     246:	40 38 14 0c 5c 00 	            fpms\.s0 f4=f5,f6,f7
+     24c:	00 00 04 00       	            nop\.i 0x0
+     250:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     256:	40 38 14 0c 5d 00 	            fpms\.s1 f4=f5,f6,f7
+     25c:	00 00 04 00       	            nop\.i 0x0
+     260:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     266:	40 38 14 0c 5e 00 	            fpms\.s2 f4=f5,f6,f7
+     26c:	00 00 04 00       	            nop\.i 0x0
+     270:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     276:	40 38 14 0c 5f 00 	            fpms\.s3 f4=f5,f6,f7
+     27c:	00 00 04 00       	            nop\.i 0x0
+     280:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     286:	40 38 14 0c 60 00 	            fnma\.s0 f4=f5,f6,f7
+     28c:	00 00 04 00       	            nop\.i 0x0
+     290:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     296:	40 38 14 0c 60 00 	            fnma\.s0 f4=f5,f6,f7
+     29c:	00 00 04 00       	            nop\.i 0x0
+     2a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     2a6:	40 38 14 0c 61 00 	            fnma\.s1 f4=f5,f6,f7
+     2ac:	00 00 04 00       	            nop\.i 0x0
+     2b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     2b6:	40 38 14 0c 62 00 	            fnma\.s2 f4=f5,f6,f7
+     2bc:	00 00 04 00       	            nop\.i 0x0
+     2c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     2c6:	40 38 14 0c 63 00 	            fnma\.s3 f4=f5,f6,f7
+     2cc:	00 00 04 00       	            nop\.i 0x0
+     2d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     2d6:	40 38 14 0c 64 00 	            fnma\.s\.s0 f4=f5,f6,f7
+     2dc:	00 00 04 00       	            nop\.i 0x0
+     2e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     2e6:	40 38 14 0c 64 00 	            fnma\.s\.s0 f4=f5,f6,f7
+     2ec:	00 00 04 00       	            nop\.i 0x0
+     2f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     2f6:	40 38 14 0c 65 00 	            fnma\.s\.s1 f4=f5,f6,f7
+     2fc:	00 00 04 00       	            nop\.i 0x0
+     300:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     306:	40 38 14 0c 66 00 	            fnma\.s\.s2 f4=f5,f6,f7
+     30c:	00 00 04 00       	            nop\.i 0x0
+     310:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     316:	40 38 14 0c 67 00 	            fnma\.s\.s3 f4=f5,f6,f7
+     31c:	00 00 04 00       	            nop\.i 0x0
+     320:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     326:	40 38 14 0c 68 00 	            fnma\.d\.s0 f4=f5,f6,f7
+     32c:	00 00 04 00       	            nop\.i 0x0
+     330:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     336:	40 38 14 0c 68 00 	            fnma\.d\.s0 f4=f5,f6,f7
+     33c:	00 00 04 00       	            nop\.i 0x0
+     340:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     346:	40 38 14 0c 69 00 	            fnma\.d\.s1 f4=f5,f6,f7
+     34c:	00 00 04 00       	            nop\.i 0x0
+     350:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     356:	40 38 14 0c 6a 00 	            fnma\.d\.s2 f4=f5,f6,f7
+     35c:	00 00 04 00       	            nop\.i 0x0
+     360:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     366:	40 38 14 0c 6b 00 	            fnma\.d\.s3 f4=f5,f6,f7
+     36c:	00 00 04 00       	            nop\.i 0x0
+     370:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     376:	40 38 14 0c 6c 00 	            fpnma\.s0 f4=f5,f6,f7
+     37c:	00 00 04 00       	            nop\.i 0x0
+     380:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     386:	40 38 14 0c 6c 00 	            fpnma\.s0 f4=f5,f6,f7
+     38c:	00 00 04 00       	            nop\.i 0x0
+     390:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     396:	40 38 14 0c 6d 00 	            fpnma\.s1 f4=f5,f6,f7
+     39c:	00 00 04 00       	            nop\.i 0x0
+     3a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     3a6:	40 38 14 0c 6e 00 	            fpnma\.s2 f4=f5,f6,f7
+     3ac:	00 00 04 00       	            nop\.i 0x0
+     3b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     3b6:	40 38 14 0c 6f 00 	            fpnma\.s3 f4=f5,f6,f7
+     3bc:	00 00 04 00       	            nop\.i 0x0
+     3c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     3c6:	40 00 14 0c 40 00 	            fmpy\.s0 f4=f5,f6
+     3cc:	00 00 04 00       	            nop\.i 0x0
+     3d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     3d6:	40 00 14 0c 40 00 	            fmpy\.s0 f4=f5,f6
+     3dc:	00 00 04 00       	            nop\.i 0x0
+     3e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     3e6:	40 00 14 0c 41 00 	            fmpy\.s1 f4=f5,f6
+     3ec:	00 00 04 00       	            nop\.i 0x0
+     3f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     3f6:	40 00 14 0c 42 00 	            fmpy\.s2 f4=f5,f6
+     3fc:	00 00 04 00       	            nop\.i 0x0
+     400:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     406:	40 00 14 0c 43 00 	            fmpy\.s3 f4=f5,f6
+     40c:	00 00 04 00       	            nop\.i 0x0
+     410:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     416:	40 00 14 0c 44 00 	            fmpy\.s\.s0 f4=f5,f6
+     41c:	00 00 04 00       	            nop\.i 0x0
+     420:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     426:	40 00 14 0c 44 00 	            fmpy\.s\.s0 f4=f5,f6
+     42c:	00 00 04 00       	            nop\.i 0x0
+     430:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     436:	40 00 14 0c 45 00 	            fmpy\.s\.s1 f4=f5,f6
+     43c:	00 00 04 00       	            nop\.i 0x0
+     440:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     446:	40 00 14 0c 46 00 	            fmpy\.s\.s2 f4=f5,f6
+     44c:	00 00 04 00       	            nop\.i 0x0
+     450:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     456:	40 00 14 0c 47 00 	            fmpy\.s\.s3 f4=f5,f6
+     45c:	00 00 04 00       	            nop\.i 0x0
+     460:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     466:	40 00 14 0c 48 00 	            fmpy\.d\.s0 f4=f5,f6
+     46c:	00 00 04 00       	            nop\.i 0x0
+     470:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     476:	40 00 14 0c 48 00 	            fmpy\.d\.s0 f4=f5,f6
+     47c:	00 00 04 00       	            nop\.i 0x0
+     480:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     486:	40 00 14 0c 49 00 	            fmpy\.d\.s1 f4=f5,f6
+     48c:	00 00 04 00       	            nop\.i 0x0
+     490:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     496:	40 00 14 0c 4a 00 	            fmpy\.d\.s2 f4=f5,f6
+     49c:	00 00 04 00       	            nop\.i 0x0
+     4a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     4a6:	40 00 14 0c 4b 00 	            fmpy\.d\.s3 f4=f5,f6
+     4ac:	00 00 04 00       	            nop\.i 0x0
+     4b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     4b6:	40 00 14 0c 4c 00 	            fpmpy\.s0 f4=f5,f6
+     4bc:	00 00 04 00       	            nop\.i 0x0
+     4c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     4c6:	40 00 14 0c 4c 00 	            fpmpy\.s0 f4=f5,f6
+     4cc:	00 00 04 00       	            nop\.i 0x0
+     4d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     4d6:	40 00 14 0c 4d 00 	            fpmpy\.s1 f4=f5,f6
+     4dc:	00 00 04 00       	            nop\.i 0x0
+     4e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     4e6:	40 00 14 0c 4e 00 	            fpmpy\.s2 f4=f5,f6
+     4ec:	00 00 04 00       	            nop\.i 0x0
+     4f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     4f6:	40 00 14 0c 4f 00 	            fpmpy\.s3 f4=f5,f6
+     4fc:	00 00 04 00       	            nop\.i 0x0
+     500:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     506:	40 30 14 02 40 00 	            fadd\.s0 f4=f5,f6
+     50c:	00 00 04 00       	            nop\.i 0x0
+     510:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     516:	40 30 14 02 40 00 	            fadd\.s0 f4=f5,f6
+     51c:	00 00 04 00       	            nop\.i 0x0
+     520:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     526:	40 30 14 02 41 00 	            fadd\.s1 f4=f5,f6
+     52c:	00 00 04 00       	            nop\.i 0x0
+     530:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     536:	40 30 14 02 42 00 	            fadd\.s2 f4=f5,f6
+     53c:	00 00 04 00       	            nop\.i 0x0
+     540:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     546:	40 30 14 02 43 00 	            fadd\.s3 f4=f5,f6
+     54c:	00 00 04 00       	            nop\.i 0x0
+     550:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     556:	40 30 14 02 44 00 	            fadd\.s\.s0 f4=f5,f6
+     55c:	00 00 04 00       	            nop\.i 0x0
+     560:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     566:	40 30 14 02 44 00 	            fadd\.s\.s0 f4=f5,f6
+     56c:	00 00 04 00       	            nop\.i 0x0
+     570:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     576:	40 30 14 02 45 00 	            fadd\.s\.s1 f4=f5,f6
+     57c:	00 00 04 00       	            nop\.i 0x0
+     580:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     586:	40 30 14 02 46 00 	            fadd\.s\.s2 f4=f5,f6
+     58c:	00 00 04 00       	            nop\.i 0x0
+     590:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     596:	40 30 14 02 47 00 	            fadd\.s\.s3 f4=f5,f6
+     59c:	00 00 04 00       	            nop\.i 0x0
+     5a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     5a6:	40 30 14 02 48 00 	            fadd\.d\.s0 f4=f5,f6
+     5ac:	00 00 04 00       	            nop\.i 0x0
+     5b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     5b6:	40 30 14 02 48 00 	            fadd\.d\.s0 f4=f5,f6
+     5bc:	00 00 04 00       	            nop\.i 0x0
+     5c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     5c6:	40 30 14 02 49 00 	            fadd\.d\.s1 f4=f5,f6
+     5cc:	00 00 04 00       	            nop\.i 0x0
+     5d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     5d6:	40 30 14 02 4a 00 	            fadd\.d\.s2 f4=f5,f6
+     5dc:	00 00 04 00       	            nop\.i 0x0
+     5e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     5e6:	40 30 14 02 4b 00 	            fadd\.d\.s3 f4=f5,f6
+     5ec:	00 00 04 00       	            nop\.i 0x0
+     5f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     5f6:	40 30 14 02 50 00 	            fsub\.s0 f4=f5,f6
+     5fc:	00 00 04 00       	            nop\.i 0x0
+     600:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     606:	40 30 14 02 50 00 	            fsub\.s0 f4=f5,f6
+     60c:	00 00 04 00       	            nop\.i 0x0
+     610:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     616:	40 30 14 02 51 00 	            fsub\.s1 f4=f5,f6
+     61c:	00 00 04 00       	            nop\.i 0x0
+     620:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     626:	40 30 14 02 52 00 	            fsub\.s2 f4=f5,f6
+     62c:	00 00 04 00       	            nop\.i 0x0
+     630:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     636:	40 30 14 02 53 00 	            fsub\.s3 f4=f5,f6
+     63c:	00 00 04 00       	            nop\.i 0x0
+     640:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     646:	40 30 14 02 54 00 	            fsub\.s\.s0 f4=f5,f6
+     64c:	00 00 04 00       	            nop\.i 0x0
+     650:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     656:	40 30 14 02 54 00 	            fsub\.s\.s0 f4=f5,f6
+     65c:	00 00 04 00       	            nop\.i 0x0
+     660:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     666:	40 30 14 02 55 00 	            fsub\.s\.s1 f4=f5,f6
+     66c:	00 00 04 00       	            nop\.i 0x0
+     670:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     676:	40 30 14 02 56 00 	            fsub\.s\.s2 f4=f5,f6
+     67c:	00 00 04 00       	            nop\.i 0x0
+     680:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     686:	40 30 14 02 57 00 	            fsub\.s\.s3 f4=f5,f6
+     68c:	00 00 04 00       	            nop\.i 0x0
+     690:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     696:	40 30 14 02 58 00 	            fsub\.d\.s0 f4=f5,f6
+     69c:	00 00 04 00       	            nop\.i 0x0
+     6a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     6a6:	40 30 14 02 58 00 	            fsub\.d\.s0 f4=f5,f6
+     6ac:	00 00 04 00       	            nop\.i 0x0
+     6b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     6b6:	40 30 14 02 59 00 	            fsub\.d\.s1 f4=f5,f6
+     6bc:	00 00 04 00       	            nop\.i 0x0
+     6c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     6c6:	40 30 14 02 5a 00 	            fsub\.d\.s2 f4=f5,f6
+     6cc:	00 00 04 00       	            nop\.i 0x0
+     6d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     6d6:	40 30 14 02 5b 00 	            fsub\.d\.s3 f4=f5,f6
+     6dc:	00 00 04 00       	            nop\.i 0x0
+     6e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     6e6:	40 30 14 02 5c 00 	            fpms\.s0 f4=f5,f1,f6
+     6ec:	00 00 04 00       	            nop\.i 0x0
+     6f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     6f6:	40 30 14 02 5c 00 	            fpms\.s0 f4=f5,f1,f6
+     6fc:	00 00 04 00       	            nop\.i 0x0
+     700:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     706:	40 30 14 02 5d 00 	            fpms\.s1 f4=f5,f1,f6
+     70c:	00 00 04 00       	            nop\.i 0x0
+     710:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     716:	40 30 14 02 5e 00 	            fpms\.s2 f4=f5,f1,f6
+     71c:	00 00 04 00       	            nop\.i 0x0
+     720:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     726:	40 30 14 02 5f 00 	            fpms\.s3 f4=f5,f1,f6
+     72c:	00 00 04 00       	            nop\.i 0x0
+     730:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     736:	40 00 14 0c 60 00 	            fnmpy\.s0 f4=f5,f6
+     73c:	00 00 04 00       	            nop\.i 0x0
+     740:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     746:	40 00 14 0c 60 00 	            fnmpy\.s0 f4=f5,f6
+     74c:	00 00 04 00       	            nop\.i 0x0
+     750:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     756:	40 00 14 0c 61 00 	            fnmpy\.s1 f4=f5,f6
+     75c:	00 00 04 00       	            nop\.i 0x0
+     760:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     766:	40 00 14 0c 62 00 	            fnmpy\.s2 f4=f5,f6
+     76c:	00 00 04 00       	            nop\.i 0x0
+     770:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     776:	40 00 14 0c 63 00 	            fnmpy\.s3 f4=f5,f6
+     77c:	00 00 04 00       	            nop\.i 0x0
+     780:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     786:	40 00 14 0c 64 00 	            fnmpy\.s\.s0 f4=f5,f6
+     78c:	00 00 04 00       	            nop\.i 0x0
+     790:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     796:	40 00 14 0c 64 00 	            fnmpy\.s\.s0 f4=f5,f6
+     79c:	00 00 04 00       	            nop\.i 0x0
+     7a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     7a6:	40 00 14 0c 65 00 	            fnmpy\.s\.s1 f4=f5,f6
+     7ac:	00 00 04 00       	            nop\.i 0x0
+     7b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     7b6:	40 00 14 0c 66 00 	            fnmpy\.s\.s2 f4=f5,f6
+     7bc:	00 00 04 00       	            nop\.i 0x0
+     7c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     7c6:	40 00 14 0c 67 00 	            fnmpy\.s\.s3 f4=f5,f6
+     7cc:	00 00 04 00       	            nop\.i 0x0
+     7d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     7d6:	40 00 14 0c 68 00 	            fnmpy\.d\.s0 f4=f5,f6
+     7dc:	00 00 04 00       	            nop\.i 0x0
+     7e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     7e6:	40 00 14 0c 68 00 	            fnmpy\.d\.s0 f4=f5,f6
+     7ec:	00 00 04 00       	            nop\.i 0x0
+     7f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     7f6:	40 00 14 0c 69 00 	            fnmpy\.d\.s1 f4=f5,f6
+     7fc:	00 00 04 00       	            nop\.i 0x0
+     800:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     806:	40 00 14 0c 6a 00 	            fnmpy\.d\.s2 f4=f5,f6
+     80c:	00 00 04 00       	            nop\.i 0x0
+     810:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     816:	40 00 14 0c 6b 00 	            fnmpy\.d\.s3 f4=f5,f6
+     81c:	00 00 04 00       	            nop\.i 0x0
+     820:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     826:	40 00 14 0c 6c 00 	            fpnmpy\.s0 f4=f5,f6
+     82c:	00 00 04 00       	            nop\.i 0x0
+     830:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     836:	40 00 14 0c 6c 00 	            fpnmpy\.s0 f4=f5,f6
+     83c:	00 00 04 00       	            nop\.i 0x0
+     840:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     846:	40 00 14 0c 6d 00 	            fpnmpy\.s1 f4=f5,f6
+     84c:	00 00 04 00       	            nop\.i 0x0
+     850:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     856:	40 00 14 0c 6e 00 	            fpnmpy\.s2 f4=f5,f6
+     85c:	00 00 04 00       	            nop\.i 0x0
+     860:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     866:	40 00 14 0c 6f 00 	            fpnmpy\.s3 f4=f5,f6
+     86c:	00 00 04 00       	            nop\.i 0x0
+     870:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     876:	40 00 14 02 40 00 	            fnorm\.s0 f4=f5
+     87c:	00 00 04 00       	            nop\.i 0x0
+     880:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     886:	40 00 14 02 40 00 	            fnorm\.s0 f4=f5
+     88c:	00 00 04 00       	            nop\.i 0x0
+     890:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     896:	40 00 14 02 41 00 	            fnorm\.s1 f4=f5
+     89c:	00 00 04 00       	            nop\.i 0x0
+     8a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     8a6:	40 00 14 02 42 00 	            fnorm\.s2 f4=f5
+     8ac:	00 00 04 00       	            nop\.i 0x0
+     8b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     8b6:	40 00 14 02 43 00 	            fnorm\.s3 f4=f5
+     8bc:	00 00 04 00       	            nop\.i 0x0
+     8c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     8c6:	40 00 14 02 44 00 	            fnorm\.s\.s0 f4=f5
+     8cc:	00 00 04 00       	            nop\.i 0x0
+     8d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     8d6:	40 00 14 02 44 00 	            fnorm\.s\.s0 f4=f5
+     8dc:	00 00 04 00       	            nop\.i 0x0
+     8e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     8e6:	40 00 14 02 45 00 	            fnorm\.s\.s1 f4=f5
+     8ec:	00 00 04 00       	            nop\.i 0x0
+     8f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     8f6:	40 00 14 02 46 00 	            fnorm\.s\.s2 f4=f5
+     8fc:	00 00 04 00       	            nop\.i 0x0
+     900:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     906:	40 00 14 02 47 00 	            fnorm\.s\.s3 f4=f5
+     90c:	00 00 04 00       	            nop\.i 0x0
+     910:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     916:	40 00 14 02 48 00 	            fnorm\.d\.s0 f4=f5
+     91c:	00 00 04 00       	            nop\.i 0x0
+     920:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     926:	40 00 14 02 48 00 	            fnorm\.d\.s0 f4=f5
+     92c:	00 00 04 00       	            nop\.i 0x0
+     930:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     936:	40 00 14 02 49 00 	            fnorm\.d\.s1 f4=f5
+     93c:	00 00 04 00       	            nop\.i 0x0
+     940:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     946:	40 00 14 02 4a 00 	            fnorm\.d\.s2 f4=f5
+     94c:	00 00 04 00       	            nop\.i 0x0
+     950:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     956:	40 00 14 02 4b 00 	            fnorm\.d\.s3 f4=f5
+     95c:	00 00 04 00       	            nop\.i 0x0
+     960:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     966:	40 38 14 0c 74 00 	            xma\.l f4=f5,f6,f7
+     96c:	00 00 04 00       	            nop\.i 0x0
+     970:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     976:	40 38 14 0c 74 00 	            xma\.l f4=f5,f6,f7
+     97c:	00 00 04 00       	            nop\.i 0x0
+     980:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     986:	40 38 14 0c 77 00 	            xma\.h f4=f5,f6,f7
+     98c:	00 00 04 00       	            nop\.i 0x0
+     990:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     996:	40 38 14 0c 76 00 	            xma\.hu f4=f5,f6,f7
+     99c:	00 00 04 00       	            nop\.i 0x0
+     9a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     9a6:	40 00 14 0c 74 00 	            xma\.l f4=f5,f6,f0
+     9ac:	00 00 04 00       	            nop\.i 0x0
+     9b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     9b6:	40 00 14 0c 74 00 	            xma\.l f4=f5,f6,f0
+     9bc:	00 00 04 00       	            nop\.i 0x0
+     9c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     9c6:	40 00 14 0c 77 00 	            xma\.h f4=f5,f6,f0
+     9cc:	00 00 04 00       	            nop\.i 0x0
+     9d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     9d6:	40 00 14 0c 76 00 	            xma\.hu f4=f5,f6,f0
+     9dc:	00 00 04 00       	            nop\.i 0x0
+     9e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     9e6:	40 38 14 0c 70 00 	            fselect f4=f5,f6,f7
+     9ec:	00 00 04 00       	            nop\.i 0x0
+     9f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     9f6:	30 20 00 09 28 00 	            fclass\.m p3,p4=f4,0x100
+     9fc:	00 00 04 00       	            nop\.i 0x0
+     a00:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     a06:	40 20 00 07 28 00 	            fclass\.m p4,p3=f4,0x100
+     a0c:	00 00 04 00       	            nop\.i 0x0
+     a10:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     a16:	30 20 80 08 28 00 	            fclass\.m p3,p4=f4,0x80
+     a1c:	00 00 04 00       	            nop\.i 0x0
+     a20:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     a26:	40 20 80 06 28 00 	            fclass\.m p4,p3=f4,0x80
+     a2c:	00 00 04 00       	            nop\.i 0x0
+     a30:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     a36:	30 20 40 08 28 00 	            fclass\.m p3,p4=f4,0x40
+     a3c:	00 00 04 00       	            nop\.i 0x0
+     a40:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     a46:	40 20 40 06 28 00 	            fclass\.m p4,p3=f4,0x40
+     a4c:	00 00 04 00       	            nop\.i 0x0
+     a50:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     a56:	30 20 00 88 28 00 	            fclass\.m p3,p4=f4,0x1
+     a5c:	00 00 04 00       	            nop\.i 0x0
+     a60:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     a66:	40 20 00 86 28 00 	            fclass\.m p4,p3=f4,0x1
+     a6c:	00 00 04 00       	            nop\.i 0x0
+     a70:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     a76:	30 20 00 08 29 00 	            fclass\.m p3,p4=f4,0x2
+     a7c:	00 00 04 00       	            nop\.i 0x0
+     a80:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     a86:	40 20 00 06 29 00 	            fclass\.m p4,p3=f4,0x2
+     a8c:	00 00 04 00       	            nop\.i 0x0
+     a90:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     a96:	30 20 08 88 29 00 	            fclass\.m p3,p4=f4,0xb
+     a9c:	00 00 04 00       	            nop\.i 0x0
+     aa0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     aa6:	40 20 08 86 29 00 	            fclass\.m p4,p3=f4,0xb
+     aac:	00 00 04 00       	            nop\.i 0x0
+     ab0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     ab6:	30 20 10 88 29 00 	            fclass\.m p3,p4=f4,0x13
+     abc:	00 00 04 00       	            nop\.i 0x0
+     ac0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     ac6:	40 20 10 86 29 00 	            fclass\.m p4,p3=f4,0x13
+     acc:	00 00 04 00       	            nop\.i 0x0
+     ad0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     ad6:	30 20 20 88 29 00 	            fclass\.m p3,p4=f4,0x23
+     adc:	00 00 04 00       	            nop\.i 0x0
+     ae0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     ae6:	40 20 20 86 29 00 	            fclass\.m p4,p3=f4,0x23
+     aec:	00 00 04 00       	            nop\.i 0x0
+     af0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     af6:	30 20 fc 89 29 00 	            fclass\.m p3,p4=f4,0x1ff
+     afc:	00 00 04 00       	            nop\.i 0x0
+     b00:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     b06:	40 20 fc 87 29 00 	            fclass\.m p4,p3=f4,0x1ff
+     b0c:	00 00 04 00       	            nop\.i 0x0
+     b10:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     b16:	30 24 00 09 28 00 	            fclass\.m\.unc p3,p4=f4,0x100
+     b1c:	00 00 04 00       	            nop\.i 0x0
+     b20:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     b26:	40 24 00 07 28 00 	            fclass\.m\.unc p4,p3=f4,0x100
+     b2c:	00 00 04 00       	            nop\.i 0x0
+     b30:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     b36:	30 24 80 08 28 00 	            fclass\.m\.unc p3,p4=f4,0x80
+     b3c:	00 00 04 00       	            nop\.i 0x0
+     b40:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     b46:	40 24 80 06 28 00 	            fclass\.m\.unc p4,p3=f4,0x80
+     b4c:	00 00 04 00       	            nop\.i 0x0
+     b50:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     b56:	30 24 40 08 28 00 	            fclass\.m\.unc p3,p4=f4,0x40
+     b5c:	00 00 04 00       	            nop\.i 0x0
+     b60:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     b66:	40 24 40 06 28 00 	            fclass\.m\.unc p4,p3=f4,0x40
+     b6c:	00 00 04 00       	            nop\.i 0x0
+     b70:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     b76:	30 24 00 88 28 00 	            fclass\.m\.unc p3,p4=f4,0x1
+     b7c:	00 00 04 00       	            nop\.i 0x0
+     b80:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     b86:	40 24 00 86 28 00 	            fclass\.m\.unc p4,p3=f4,0x1
+     b8c:	00 00 04 00       	            nop\.i 0x0
+     b90:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     b96:	30 24 00 08 29 00 	            fclass\.m\.unc p3,p4=f4,0x2
+     b9c:	00 00 04 00       	            nop\.i 0x0
+     ba0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     ba6:	40 24 00 06 29 00 	            fclass\.m\.unc p4,p3=f4,0x2
+     bac:	00 00 04 00       	            nop\.i 0x0
+     bb0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     bb6:	30 24 08 88 29 00 	            fclass\.m\.unc p3,p4=f4,0xb
+     bbc:	00 00 04 00       	            nop\.i 0x0
+     bc0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     bc6:	40 24 08 86 29 00 	            fclass\.m\.unc p4,p3=f4,0xb
+     bcc:	00 00 04 00       	            nop\.i 0x0
+     bd0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     bd6:	30 24 10 88 29 00 	            fclass\.m\.unc p3,p4=f4,0x13
+     bdc:	00 00 04 00       	            nop\.i 0x0
+     be0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     be6:	40 24 10 86 29 00 	            fclass\.m\.unc p4,p3=f4,0x13
+     bec:	00 00 04 00       	            nop\.i 0x0
+     bf0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     bf6:	30 24 20 88 29 00 	            fclass\.m\.unc p3,p4=f4,0x23
+     bfc:	00 00 04 00       	            nop\.i 0x0
+     c00:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     c06:	40 24 20 86 29 00 	            fclass\.m\.unc p4,p3=f4,0x23
+     c0c:	00 00 04 00       	            nop\.i 0x0
+     c10:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     c16:	30 24 fc 89 29 00 	            fclass\.m\.unc p3,p4=f4,0x1ff
+     c1c:	00 00 04 00       	            nop\.i 0x0
+     c20:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     c26:	40 24 fc 87 29 00 	            fclass\.m\.unc p4,p3=f4,0x1ff
+     c2c:	00 00 04 00       	            nop\.i 0x0
+     c30:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     c36:	40 30 1c 8a 00 00 	            frcpa\.s0 f4,p5=f6,f7
+     c3c:	00 00 04 00       	            nop\.i 0x0
+     c40:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     c46:	40 30 1c 8a 00 00 	            frcpa\.s0 f4,p5=f6,f7
+     c4c:	00 00 04 00       	            nop\.i 0x0
+     c50:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     c56:	40 30 1c 8a 01 00 	            frcpa\.s1 f4,p5=f6,f7
+     c5c:	00 00 04 00       	            nop\.i 0x0
+     c60:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     c66:	40 30 1c 8a 02 00 	            frcpa\.s2 f4,p5=f6,f7
+     c6c:	00 00 04 00       	            nop\.i 0x0
+     c70:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     c76:	40 30 1c 8a 03 00 	            frcpa\.s3 f4,p5=f6,f7
+     c7c:	00 00 04 00       	            nop\.i 0x0
+     c80:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     c86:	40 30 1c 8a 08 00 	            fprcpa\.s0 f4,p5=f6,f7
+     c8c:	00 00 04 00       	            nop\.i 0x0
+     c90:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     c96:	40 30 1c 8a 08 00 	            fprcpa\.s0 f4,p5=f6,f7
+     c9c:	00 00 04 00       	            nop\.i 0x0
+     ca0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     ca6:	40 30 1c 8a 09 00 	            fprcpa\.s1 f4,p5=f6,f7
+     cac:	00 00 04 00       	            nop\.i 0x0
+     cb0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     cb6:	40 30 1c 8a 0a 00 	            fprcpa\.s2 f4,p5=f6,f7
+     cbc:	00 00 04 00       	            nop\.i 0x0
+     cc0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     cc6:	40 30 1c 8a 0b 00 	            fprcpa\.s3 f4,p5=f6,f7
+     ccc:	00 00 04 00       	            nop\.i 0x0
+     cd0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     cd6:	40 00 18 8a 04 00 	            frsqrta\.s0 f4,p5=f6
+     cdc:	00 00 04 00       	            nop\.i 0x0
+     ce0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     ce6:	40 00 18 8a 04 00 	            frsqrta\.s0 f4,p5=f6
+     cec:	00 00 04 00       	            nop\.i 0x0
+     cf0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     cf6:	40 00 18 8a 05 00 	            frsqrta\.s1 f4,p5=f6
+     cfc:	00 00 04 00       	            nop\.i 0x0
+     d00:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     d06:	40 00 18 8a 06 00 	            frsqrta\.s2 f4,p5=f6
+     d0c:	00 00 04 00       	            nop\.i 0x0
+     d10:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     d16:	40 00 18 8a 07 00 	            frsqrta\.s3 f4,p5=f6
+     d1c:	00 00 04 00       	            nop\.i 0x0
+     d20:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     d26:	40 00 18 8a 0c 00 	            fprsqrta\.s0 f4,p5=f6
+     d2c:	00 00 04 00       	            nop\.i 0x0
+     d30:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     d36:	40 00 18 8a 0c 00 	            fprsqrta\.s0 f4,p5=f6
+     d3c:	00 00 04 00       	            nop\.i 0x0
+     d40:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     d46:	40 00 18 8a 0d 00 	            fprsqrta\.s1 f4,p5=f6
+     d4c:	00 00 04 00       	            nop\.i 0x0
+     d50:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     d56:	40 00 18 8a 0e 00 	            fprsqrta\.s2 f4,p5=f6
+     d5c:	00 00 04 00       	            nop\.i 0x0
+     d60:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     d66:	40 00 18 8a 0f 00 	            fprsqrta\.s3 f4,p5=f6
+     d6c:	00 00 04 00       	            nop\.i 0x0
+     d70:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     d76:	40 28 18 28 00 00 	            fmin\.s0 f4=f5,f6
+     d7c:	00 00 04 00       	            nop\.i 0x0
+     d80:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     d86:	40 28 18 28 00 00 	            fmin\.s0 f4=f5,f6
+     d8c:	00 00 04 00       	            nop\.i 0x0
+     d90:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     d96:	40 28 18 28 01 00 	            fmin\.s1 f4=f5,f6
+     d9c:	00 00 04 00       	            nop\.i 0x0
+     da0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     da6:	40 28 18 28 02 00 	            fmin\.s2 f4=f5,f6
+     dac:	00 00 04 00       	            nop\.i 0x0
+     db0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     db6:	40 28 18 28 03 00 	            fmin\.s3 f4=f5,f6
+     dbc:	00 00 04 00       	            nop\.i 0x0
+     dc0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     dc6:	40 28 18 2a 00 00 	            fmax\.s0 f4=f5,f6
+     dcc:	00 00 04 00       	            nop\.i 0x0
+     dd0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     dd6:	40 28 18 2a 00 00 	            fmax\.s0 f4=f5,f6
+     ddc:	00 00 04 00       	            nop\.i 0x0
+     de0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     de6:	40 28 18 2a 01 00 	            fmax\.s1 f4=f5,f6
+     dec:	00 00 04 00       	            nop\.i 0x0
+     df0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     df6:	40 28 18 2a 02 00 	            fmax\.s2 f4=f5,f6
+     dfc:	00 00 04 00       	            nop\.i 0x0
+     e00:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     e06:	40 28 18 2a 03 00 	            fmax\.s3 f4=f5,f6
+     e0c:	00 00 04 00       	            nop\.i 0x0
+     e10:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     e16:	40 28 18 2c 00 00 	            famin\.s0 f4=f5,f6
+     e1c:	00 00 04 00       	            nop\.i 0x0
+     e20:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     e26:	40 28 18 2c 00 00 	            famin\.s0 f4=f5,f6
+     e2c:	00 00 04 00       	            nop\.i 0x0
+     e30:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     e36:	40 28 18 2c 01 00 	            famin\.s1 f4=f5,f6
+     e3c:	00 00 04 00       	            nop\.i 0x0
+     e40:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     e46:	40 28 18 2c 02 00 	            famin\.s2 f4=f5,f6
+     e4c:	00 00 04 00       	            nop\.i 0x0
+     e50:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     e56:	40 28 18 2c 03 00 	            famin\.s3 f4=f5,f6
+     e5c:	00 00 04 00       	            nop\.i 0x0
+     e60:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     e66:	40 28 18 2e 00 00 	            famax\.s0 f4=f5,f6
+     e6c:	00 00 04 00       	            nop\.i 0x0
+     e70:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     e76:	40 28 18 2e 00 00 	            famax\.s0 f4=f5,f6
+     e7c:	00 00 04 00       	            nop\.i 0x0
+     e80:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     e86:	40 28 18 2e 01 00 	            famax\.s1 f4=f5,f6
+     e8c:	00 00 04 00       	            nop\.i 0x0
+     e90:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     e96:	40 28 18 2e 02 00 	            famax\.s2 f4=f5,f6
+     e9c:	00 00 04 00       	            nop\.i 0x0
+     ea0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     ea6:	40 28 18 2e 03 00 	            famax\.s3 f4=f5,f6
+     eac:	00 00 04 00       	            nop\.i 0x0
+     eb0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     eb6:	40 28 18 28 08 00 	            fpmin\.s0 f4=f5,f6
+     ebc:	00 00 04 00       	            nop\.i 0x0
+     ec0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     ec6:	40 28 18 28 08 00 	            fpmin\.s0 f4=f5,f6
+     ecc:	00 00 04 00       	            nop\.i 0x0
+     ed0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     ed6:	40 28 18 28 09 00 	            fpmin\.s1 f4=f5,f6
+     edc:	00 00 04 00       	            nop\.i 0x0
+     ee0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     ee6:	40 28 18 28 0a 00 	            fpmin\.s2 f4=f5,f6
+     eec:	00 00 04 00       	            nop\.i 0x0
+     ef0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     ef6:	40 28 18 28 0b 00 	            fpmin\.s3 f4=f5,f6
+     efc:	00 00 04 00       	            nop\.i 0x0
+     f00:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     f06:	40 28 18 2a 08 00 	            fpmax\.s0 f4=f5,f6
+     f0c:	00 00 04 00       	            nop\.i 0x0
+     f10:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     f16:	40 28 18 2a 08 00 	            fpmax\.s0 f4=f5,f6
+     f1c:	00 00 04 00       	            nop\.i 0x0
+     f20:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     f26:	40 28 18 2a 09 00 	            fpmax\.s1 f4=f5,f6
+     f2c:	00 00 04 00       	            nop\.i 0x0
+     f30:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     f36:	40 28 18 2a 0a 00 	            fpmax\.s2 f4=f5,f6
+     f3c:	00 00 04 00       	            nop\.i 0x0
+     f40:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     f46:	40 28 18 2a 0b 00 	            fpmax\.s3 f4=f5,f6
+     f4c:	00 00 04 00       	            nop\.i 0x0
+     f50:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     f56:	40 28 18 2c 08 00 	            fpamin\.s0 f4=f5,f6
+     f5c:	00 00 04 00       	            nop\.i 0x0
+     f60:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     f66:	40 28 18 2c 08 00 	            fpamin\.s0 f4=f5,f6
+     f6c:	00 00 04 00       	            nop\.i 0x0
+     f70:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     f76:	40 28 18 2c 09 00 	            fpamin\.s1 f4=f5,f6
+     f7c:	00 00 04 00       	            nop\.i 0x0
+     f80:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     f86:	40 28 18 2c 0a 00 	            fpamin\.s2 f4=f5,f6
+     f8c:	00 00 04 00       	            nop\.i 0x0
+     f90:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     f96:	40 28 18 2c 0b 00 	            fpamin\.s3 f4=f5,f6
+     f9c:	00 00 04 00       	            nop\.i 0x0
+     fa0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     fa6:	40 28 18 2e 08 00 	            fpamax\.s0 f4=f5,f6
+     fac:	00 00 04 00       	            nop\.i 0x0
+     fb0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     fb6:	40 28 18 2e 08 00 	            fpamax\.s0 f4=f5,f6
+     fbc:	00 00 04 00       	            nop\.i 0x0
+     fc0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     fc6:	40 28 18 2e 09 00 	            fpamax\.s1 f4=f5,f6
+     fcc:	00 00 04 00       	            nop\.i 0x0
+     fd0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     fd6:	40 28 18 2e 0a 00 	            fpamax\.s2 f4=f5,f6
+     fdc:	00 00 04 00       	            nop\.i 0x0
+     fe0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     fe6:	40 28 18 2e 0b 00 	            fpamax\.s3 f4=f5,f6
+     fec:	00 00 04 00       	            nop\.i 0x0
+     ff0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+     ff6:	30 20 14 08 20 00 	            fcmp\.eq\.s0 p3,p4=f4,f5
+     ffc:	00 00 04 00       	            nop\.i 0x0
+    1000:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1006:	30 20 14 08 20 00 	            fcmp\.eq\.s0 p3,p4=f4,f5
+    100c:	00 00 04 00       	            nop\.i 0x0
+    1010:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1016:	30 20 14 08 21 00 	            fcmp\.eq\.s1 p3,p4=f4,f5
+    101c:	00 00 04 00       	            nop\.i 0x0
+    1020:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1026:	30 20 14 08 22 00 	            fcmp\.eq\.s2 p3,p4=f4,f5
+    102c:	00 00 04 00       	            nop\.i 0x0
+    1030:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1036:	30 20 14 08 23 00 	            fcmp\.eq\.s3 p3,p4=f4,f5
+    103c:	00 00 04 00       	            nop\.i 0x0
+    1040:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1046:	30 20 14 08 24 00 	            fcmp\.lt\.s0 p3,p4=f4,f5
+    104c:	00 00 04 00       	            nop\.i 0x0
+    1050:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1056:	30 20 14 08 24 00 	            fcmp\.lt\.s0 p3,p4=f4,f5
+    105c:	00 00 04 00       	            nop\.i 0x0
+    1060:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1066:	30 20 14 08 25 00 	            fcmp\.lt\.s1 p3,p4=f4,f5
+    106c:	00 00 04 00       	            nop\.i 0x0
+    1070:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1076:	30 20 14 08 26 00 	            fcmp\.lt\.s2 p3,p4=f4,f5
+    107c:	00 00 04 00       	            nop\.i 0x0
+    1080:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1086:	30 20 14 08 27 00 	            fcmp\.lt\.s3 p3,p4=f4,f5
+    108c:	00 00 04 00       	            nop\.i 0x0
+    1090:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1096:	30 20 14 88 20 00 	            fcmp\.le\.s0 p3,p4=f4,f5
+    109c:	00 00 04 00       	            nop\.i 0x0
+    10a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    10a6:	30 20 14 88 20 00 	            fcmp\.le\.s0 p3,p4=f4,f5
+    10ac:	00 00 04 00       	            nop\.i 0x0
+    10b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    10b6:	30 20 14 88 21 00 	            fcmp\.le\.s1 p3,p4=f4,f5
+    10bc:	00 00 04 00       	            nop\.i 0x0
+    10c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    10c6:	30 20 14 88 22 00 	            fcmp\.le\.s2 p3,p4=f4,f5
+    10cc:	00 00 04 00       	            nop\.i 0x0
+    10d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    10d6:	30 20 14 88 23 00 	            fcmp\.le\.s3 p3,p4=f4,f5
+    10dc:	00 00 04 00       	            nop\.i 0x0
+    10e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    10e6:	30 20 14 88 24 00 	            fcmp\.unord\.s0 p3,p4=f4,f5
+    10ec:	00 00 04 00       	            nop\.i 0x0
+    10f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    10f6:	30 20 14 88 24 00 	            fcmp\.unord\.s0 p3,p4=f4,f5
+    10fc:	00 00 04 00       	            nop\.i 0x0
+    1100:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1106:	30 20 14 88 25 00 	            fcmp\.unord\.s1 p3,p4=f4,f5
+    110c:	00 00 04 00       	            nop\.i 0x0
+    1110:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1116:	30 20 14 88 26 00 	            fcmp\.unord\.s2 p3,p4=f4,f5
+    111c:	00 00 04 00       	            nop\.i 0x0
+    1120:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1126:	30 20 14 88 27 00 	            fcmp\.unord\.s3 p3,p4=f4,f5
+    112c:	00 00 04 00       	            nop\.i 0x0
+    1130:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1136:	30 28 10 08 24 00 	            fcmp\.lt\.s0 p3,p4=f5,f4
+    113c:	00 00 04 00       	            nop\.i 0x0
+    1140:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1146:	30 28 10 08 24 00 	            fcmp\.lt\.s0 p3,p4=f5,f4
+    114c:	00 00 04 00       	            nop\.i 0x0
+    1150:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1156:	30 28 10 08 25 00 	            fcmp\.lt\.s1 p3,p4=f5,f4
+    115c:	00 00 04 00       	            nop\.i 0x0
+    1160:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1166:	30 28 10 08 26 00 	            fcmp\.lt\.s2 p3,p4=f5,f4
+    116c:	00 00 04 00       	            nop\.i 0x0
+    1170:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1176:	30 28 10 08 27 00 	            fcmp\.lt\.s3 p3,p4=f5,f4
+    117c:	00 00 04 00       	            nop\.i 0x0
+    1180:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1186:	30 28 10 88 20 00 	            fcmp\.le\.s0 p3,p4=f5,f4
+    118c:	00 00 04 00       	            nop\.i 0x0
+    1190:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1196:	30 28 10 88 20 00 	            fcmp\.le\.s0 p3,p4=f5,f4
+    119c:	00 00 04 00       	            nop\.i 0x0
+    11a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    11a6:	30 28 10 88 21 00 	            fcmp\.le\.s1 p3,p4=f5,f4
+    11ac:	00 00 04 00       	            nop\.i 0x0
+    11b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    11b6:	30 28 10 88 22 00 	            fcmp\.le\.s2 p3,p4=f5,f4
+    11bc:	00 00 04 00       	            nop\.i 0x0
+    11c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    11c6:	30 28 10 88 23 00 	            fcmp\.le\.s3 p3,p4=f5,f4
+    11cc:	00 00 04 00       	            nop\.i 0x0
+    11d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    11d6:	40 20 14 06 20 00 	            fcmp\.eq\.s0 p4,p3=f4,f5
+    11dc:	00 00 04 00       	            nop\.i 0x0
+    11e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    11e6:	40 20 14 06 20 00 	            fcmp\.eq\.s0 p4,p3=f4,f5
+    11ec:	00 00 04 00       	            nop\.i 0x0
+    11f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    11f6:	40 20 14 06 21 00 	            fcmp\.eq\.s1 p4,p3=f4,f5
+    11fc:	00 00 04 00       	            nop\.i 0x0
+    1200:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1206:	40 20 14 06 22 00 	            fcmp\.eq\.s2 p4,p3=f4,f5
+    120c:	00 00 04 00       	            nop\.i 0x0
+    1210:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1216:	40 20 14 06 23 00 	            fcmp\.eq\.s3 p4,p3=f4,f5
+    121c:	00 00 04 00       	            nop\.i 0x0
+    1220:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1226:	40 20 14 06 24 00 	            fcmp\.lt\.s0 p4,p3=f4,f5
+    122c:	00 00 04 00       	            nop\.i 0x0
+    1230:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1236:	40 20 14 06 24 00 	            fcmp\.lt\.s0 p4,p3=f4,f5
+    123c:	00 00 04 00       	            nop\.i 0x0
+    1240:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1246:	40 20 14 06 25 00 	            fcmp\.lt\.s1 p4,p3=f4,f5
+    124c:	00 00 04 00       	            nop\.i 0x0
+    1250:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1256:	40 20 14 06 26 00 	            fcmp\.lt\.s2 p4,p3=f4,f5
+    125c:	00 00 04 00       	            nop\.i 0x0
+    1260:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1266:	40 20 14 06 27 00 	            fcmp\.lt\.s3 p4,p3=f4,f5
+    126c:	00 00 04 00       	            nop\.i 0x0
+    1270:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1276:	40 20 14 86 20 00 	            fcmp\.le\.s0 p4,p3=f4,f5
+    127c:	00 00 04 00       	            nop\.i 0x0
+    1280:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1286:	40 20 14 86 20 00 	            fcmp\.le\.s0 p4,p3=f4,f5
+    128c:	00 00 04 00       	            nop\.i 0x0
+    1290:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1296:	40 20 14 86 21 00 	            fcmp\.le\.s1 p4,p3=f4,f5
+    129c:	00 00 04 00       	            nop\.i 0x0
+    12a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    12a6:	40 20 14 86 22 00 	            fcmp\.le\.s2 p4,p3=f4,f5
+    12ac:	00 00 04 00       	            nop\.i 0x0
+    12b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    12b6:	40 20 14 86 23 00 	            fcmp\.le\.s3 p4,p3=f4,f5
+    12bc:	00 00 04 00       	            nop\.i 0x0
+    12c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    12c6:	40 28 10 06 24 00 	            fcmp\.lt\.s0 p4,p3=f5,f4
+    12cc:	00 00 04 00       	            nop\.i 0x0
+    12d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    12d6:	40 28 10 06 24 00 	            fcmp\.lt\.s0 p4,p3=f5,f4
+    12dc:	00 00 04 00       	            nop\.i 0x0
+    12e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    12e6:	40 28 10 06 25 00 	            fcmp\.lt\.s1 p4,p3=f5,f4
+    12ec:	00 00 04 00       	            nop\.i 0x0
+    12f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    12f6:	40 28 10 06 26 00 	            fcmp\.lt\.s2 p4,p3=f5,f4
+    12fc:	00 00 04 00       	            nop\.i 0x0
+    1300:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1306:	40 28 10 06 27 00 	            fcmp\.lt\.s3 p4,p3=f5,f4
+    130c:	00 00 04 00       	            nop\.i 0x0
+    1310:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1316:	40 28 10 86 20 00 	            fcmp\.le\.s0 p4,p3=f5,f4
+    131c:	00 00 04 00       	            nop\.i 0x0
+    1320:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1326:	40 28 10 86 20 00 	            fcmp\.le\.s0 p4,p3=f5,f4
+    132c:	00 00 04 00       	            nop\.i 0x0
+    1330:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1336:	40 28 10 86 21 00 	            fcmp\.le\.s1 p4,p3=f5,f4
+    133c:	00 00 04 00       	            nop\.i 0x0
+    1340:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1346:	40 28 10 86 22 00 	            fcmp\.le\.s2 p4,p3=f5,f4
+    134c:	00 00 04 00       	            nop\.i 0x0
+    1350:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1356:	40 28 10 86 23 00 	            fcmp\.le\.s3 p4,p3=f5,f4
+    135c:	00 00 04 00       	            nop\.i 0x0
+    1360:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1366:	40 20 14 86 24 00 	            fcmp\.unord\.s0 p4,p3=f4,f5
+    136c:	00 00 04 00       	            nop\.i 0x0
+    1370:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1376:	40 20 14 86 24 00 	            fcmp\.unord\.s0 p4,p3=f4,f5
+    137c:	00 00 04 00       	            nop\.i 0x0
+    1380:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1386:	40 20 14 86 25 00 	            fcmp\.unord\.s1 p4,p3=f4,f5
+    138c:	00 00 04 00       	            nop\.i 0x0
+    1390:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1396:	40 20 14 86 26 00 	            fcmp\.unord\.s2 p4,p3=f4,f5
+    139c:	00 00 04 00       	            nop\.i 0x0
+    13a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    13a6:	40 20 14 86 27 00 	            fcmp\.unord\.s3 p4,p3=f4,f5
+    13ac:	00 00 04 00       	            nop\.i 0x0
+    13b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    13b6:	40 28 18 20 00 00 	            fmerge\.s f4=f5,f6
+    13bc:	00 00 04 00       	            nop\.i 0x0
+    13c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    13c6:	40 28 18 22 00 00 	            fmerge\.ns f4=f5,f6
+    13cc:	00 00 04 00       	            nop\.i 0x0
+    13d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    13d6:	40 28 18 24 00 00 	            fmerge\.se f4=f5,f6
+    13dc:	00 00 04 00       	            nop\.i 0x0
+    13e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    13e6:	40 28 18 72 00 00 	            fmix\.lr f4=f5,f6
+    13ec:	00 00 04 00       	            nop\.i 0x0
+    13f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    13f6:	40 28 18 74 00 00 	            fmix\.r f4=f5,f6
+    13fc:	00 00 04 00       	            nop\.i 0x0
+    1400:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1406:	40 28 18 76 00 00 	            fmix\.l f4=f5,f6
+    140c:	00 00 04 00       	            nop\.i 0x0
+    1410:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1416:	40 28 18 7a 00 00 	            fsxt\.l f4=f5,f6
+    141c:	00 00 04 00       	            nop\.i 0x0
+    1420:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1426:	40 28 18 50 00 00 	            fpack f4=f5,f6
+    142c:	00 00 04 00       	            nop\.i 0x0
+    1430:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1436:	40 28 18 68 00 00 	            fswap f4=f5,f6
+    143c:	00 00 04 00       	            nop\.i 0x0
+    1440:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1446:	40 28 18 6a 00 00 	            fswap\.nl f4=f5,f6
+    144c:	00 00 04 00       	            nop\.i 0x0
+    1450:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1456:	40 28 18 6c 00 00 	            fswap\.nr f4=f5,f6
+    145c:	00 00 04 00       	            nop\.i 0x0
+    1460:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1466:	40 28 18 58 00 00 	            fand f4=f5,f6
+    146c:	00 00 04 00       	            nop\.i 0x0
+    1470:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1476:	40 28 18 5a 00 00 	            fandcm f4=f5,f6
+    147c:	00 00 04 00       	            nop\.i 0x0
+    1480:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1486:	40 28 18 5c 00 00 	            for f4=f5,f6
+    148c:	00 00 04 00       	            nop\.i 0x0
+    1490:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1496:	40 28 18 5e 00 00 	            fxor f4=f5,f6
+    149c:	00 00 04 00       	            nop\.i 0x0
+    14a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    14a6:	40 28 18 20 08 00 	            fpmerge\.s f4=f5,f6
+    14ac:	00 00 04 00       	            nop\.i 0x0
+    14b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    14b6:	40 28 18 22 08 00 	            fpmerge\.ns f4=f5,f6
+    14bc:	00 00 04 00       	            nop\.i 0x0
+    14c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    14c6:	40 28 18 24 08 00 	            fpmerge\.se f4=f5,f6
+    14cc:	00 00 04 00       	            nop\.i 0x0
+    14d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    14d6:	40 00 14 20 00 00 	            fabs f4=f5
+    14dc:	00 00 04 00       	            nop\.i 0x0
+    14e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    14e6:	40 28 14 22 00 00 	            fneg f4=f5
+    14ec:	00 00 04 00       	            nop\.i 0x0
+    14f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    14f6:	40 00 14 22 00 00 	            fnegabs f4=f5
+    14fc:	00 00 04 00       	            nop\.i 0x0
+    1500:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1506:	40 00 14 20 08 00 	            fpabs f4=f5
+    150c:	00 00 04 00       	            nop\.i 0x0
+    1510:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1516:	40 28 14 22 08 00 	            fpneg f4=f5
+    151c:	00 00 04 00       	            nop\.i 0x0
+    1520:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1526:	40 00 14 22 08 00 	            fpnegabs f4=f5
+    152c:	00 00 04 00       	            nop\.i 0x0
+    1530:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1536:	40 28 00 30 00 00 	            fcvt\.fx\.s0 f4=f5
+    153c:	00 00 04 00       	            nop\.i 0x0
+    1540:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1546:	40 28 00 30 00 00 	            fcvt\.fx\.s0 f4=f5
+    154c:	00 00 04 00       	            nop\.i 0x0
+    1550:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1556:	40 28 00 30 01 00 	            fcvt\.fx\.s1 f4=f5
+    155c:	00 00 04 00       	            nop\.i 0x0
+    1560:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1566:	40 28 00 30 02 00 	            fcvt\.fx\.s2 f4=f5
+    156c:	00 00 04 00       	            nop\.i 0x0
+    1570:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1576:	40 28 00 30 03 00 	            fcvt\.fx\.s3 f4=f5
+    157c:	00 00 04 00       	            nop\.i 0x0
+    1580:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1586:	40 28 00 34 00 00 	            fcvt\.fx\.trunc\.s0 f4=f5
+    158c:	00 00 04 00       	            nop\.i 0x0
+    1590:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1596:	40 28 00 34 00 00 	            fcvt\.fx\.trunc\.s0 f4=f5
+    159c:	00 00 04 00       	            nop\.i 0x0
+    15a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    15a6:	40 28 00 34 01 00 	            fcvt\.fx\.trunc\.s1 f4=f5
+    15ac:	00 00 04 00       	            nop\.i 0x0
+    15b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    15b6:	40 28 00 34 02 00 	            fcvt\.fx\.trunc\.s2 f4=f5
+    15bc:	00 00 04 00       	            nop\.i 0x0
+    15c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    15c6:	40 28 00 34 03 00 	            fcvt\.fx\.trunc\.s3 f4=f5
+    15cc:	00 00 04 00       	            nop\.i 0x0
+    15d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    15d6:	40 28 00 32 00 00 	            fcvt\.fxu\.s0 f4=f5
+    15dc:	00 00 04 00       	            nop\.i 0x0
+    15e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    15e6:	40 28 00 32 00 00 	            fcvt\.fxu\.s0 f4=f5
+    15ec:	00 00 04 00       	            nop\.i 0x0
+    15f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    15f6:	40 28 00 32 01 00 	            fcvt\.fxu\.s1 f4=f5
+    15fc:	00 00 04 00       	            nop\.i 0x0
+    1600:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1606:	40 28 00 32 02 00 	            fcvt\.fxu\.s2 f4=f5
+    160c:	00 00 04 00       	            nop\.i 0x0
+    1610:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1616:	40 28 00 32 03 00 	            fcvt\.fxu\.s3 f4=f5
+    161c:	00 00 04 00       	            nop\.i 0x0
+    1620:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1626:	40 28 00 36 00 00 	            fcvt\.fxu\.trunc\.s0 f4=f5
+    162c:	00 00 04 00       	            nop\.i 0x0
+    1630:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1636:	40 28 00 36 00 00 	            fcvt\.fxu\.trunc\.s0 f4=f5
+    163c:	00 00 04 00       	            nop\.i 0x0
+    1640:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1646:	40 28 00 36 01 00 	            fcvt\.fxu\.trunc\.s1 f4=f5
+    164c:	00 00 04 00       	            nop\.i 0x0
+    1650:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1656:	40 28 00 36 02 00 	            fcvt\.fxu\.trunc\.s2 f4=f5
+    165c:	00 00 04 00       	            nop\.i 0x0
+    1660:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1666:	40 28 00 36 03 00 	            fcvt\.fxu\.trunc\.s3 f4=f5
+    166c:	00 00 04 00       	            nop\.i 0x0
+    1670:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1676:	40 28 00 30 08 00 	            fpcvt\.fx\.s0 f4=f5
+    167c:	00 00 04 00       	            nop\.i 0x0
+    1680:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1686:	40 28 00 30 08 00 	            fpcvt\.fx\.s0 f4=f5
+    168c:	00 00 04 00       	            nop\.i 0x0
+    1690:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1696:	40 28 00 30 09 00 	            fpcvt\.fx\.s1 f4=f5
+    169c:	00 00 04 00       	            nop\.i 0x0
+    16a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    16a6:	40 28 00 30 0a 00 	            fpcvt\.fx\.s2 f4=f5
+    16ac:	00 00 04 00       	            nop\.i 0x0
+    16b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    16b6:	40 28 00 30 0b 00 	            fpcvt\.fx\.s3 f4=f5
+    16bc:	00 00 04 00       	            nop\.i 0x0
+    16c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    16c6:	40 28 00 34 08 00 	            fpcvt\.fx\.trunc\.s0 f4=f5
+    16cc:	00 00 04 00       	            nop\.i 0x0
+    16d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    16d6:	40 28 00 34 08 00 	            fpcvt\.fx\.trunc\.s0 f4=f5
+    16dc:	00 00 04 00       	            nop\.i 0x0
+    16e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    16e6:	40 28 00 34 09 00 	            fpcvt\.fx\.trunc\.s1 f4=f5
+    16ec:	00 00 04 00       	            nop\.i 0x0
+    16f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    16f6:	40 28 00 34 0a 00 	            fpcvt\.fx\.trunc\.s2 f4=f5
+    16fc:	00 00 04 00       	            nop\.i 0x0
+    1700:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1706:	40 28 00 34 0b 00 	            fpcvt\.fx\.trunc\.s3 f4=f5
+    170c:	00 00 04 00       	            nop\.i 0x0
+    1710:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1716:	40 28 00 32 08 00 	            fpcvt\.fxu\.s0 f4=f5
+    171c:	00 00 04 00       	            nop\.i 0x0
+    1720:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1726:	40 28 00 32 08 00 	            fpcvt\.fxu\.s0 f4=f5
+    172c:	00 00 04 00       	            nop\.i 0x0
+    1730:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1736:	40 28 00 32 09 00 	            fpcvt\.fxu\.s1 f4=f5
+    173c:	00 00 04 00       	            nop\.i 0x0
+    1740:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1746:	40 28 00 32 0a 00 	            fpcvt\.fxu\.s2 f4=f5
+    174c:	00 00 04 00       	            nop\.i 0x0
+    1750:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1756:	40 28 00 32 0b 00 	            fpcvt\.fxu\.s3 f4=f5
+    175c:	00 00 04 00       	            nop\.i 0x0
+    1760:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1766:	40 28 00 36 08 00 	            fpcvt\.fxu\.trunc\.s0 f4=f5
+    176c:	00 00 04 00       	            nop\.i 0x0
+    1770:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1776:	40 28 00 36 08 00 	            fpcvt\.fxu\.trunc\.s0 f4=f5
+    177c:	00 00 04 00       	            nop\.i 0x0
+    1780:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1786:	40 28 00 36 09 00 	            fpcvt\.fxu\.trunc\.s1 f4=f5
+    178c:	00 00 04 00       	            nop\.i 0x0
+    1790:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1796:	40 28 00 36 0a 00 	            fpcvt\.fxu\.trunc\.s2 f4=f5
+    179c:	00 00 04 00       	            nop\.i 0x0
+    17a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    17a6:	40 28 00 36 0b 00 	            fpcvt\.fxu\.trunc\.s3 f4=f5
+    17ac:	00 00 04 00       	            nop\.i 0x0
+    17b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    17b6:	40 28 00 38 00 00 	            fcvt\.xf f4=f5
+    17bc:	00 00 04 00       	            nop\.i 0x0
+    17c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    17c6:	40 00 14 02 40 00 	            fnorm\.s0 f4=f5
+    17cc:	00 00 04 00       	            nop\.i 0x0
+    17d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    17d6:	00 00 00 08 00 00 	            fsetc\.s0 0x0,0x0
+    17dc:	00 00 04 00       	            nop\.i 0x0
+    17e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    17e6:	00 f8 fd 08 00 00 	            fsetc\.s0 0x3f,0x3f
+    17ec:	00 00 04 00       	            nop\.i 0x0
+    17f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    17f6:	00 00 00 08 00 00 	            fsetc\.s0 0x0,0x0
+    17fc:	00 00 04 00       	            nop\.i 0x0
+    1800:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1806:	00 f8 fd 08 00 00 	            fsetc\.s0 0x3f,0x3f
+    180c:	00 00 04 00       	            nop\.i 0x0
+    1810:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1816:	00 00 00 08 01 00 	            fsetc\.s1 0x0,0x0
+    181c:	00 00 04 00       	            nop\.i 0x0
+    1820:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1826:	00 f8 fd 08 01 00 	            fsetc\.s1 0x3f,0x3f
+    182c:	00 00 04 00       	            nop\.i 0x0
+    1830:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1836:	00 00 00 08 02 00 	            fsetc\.s2 0x0,0x0
+    183c:	00 00 04 00       	            nop\.i 0x0
+    1840:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1846:	00 f8 fd 08 02 00 	            fsetc\.s2 0x3f,0x3f
+    184c:	00 00 04 00       	            nop\.i 0x0
+    1850:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1856:	00 00 00 08 03 00 	            fsetc\.s3 0x0,0x0
+    185c:	00 00 04 00       	            nop\.i 0x0
+    1860:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1866:	00 f8 fd 08 03 00 	            fsetc\.s3 0x3f,0x3f
+    186c:	00 00 04 00       	            nop\.i 0x0
+    1870:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1876:	00 00 00 0a 00 00 	            fclrf\.s0
+    187c:	00 00 04 00       	            nop\.i 0x0
+    1880:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1886:	00 00 00 0a 00 00 	            fclrf\.s0
+    188c:	00 00 04 00       	            nop\.i 0x0
+    1890:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1896:	00 00 00 0a 01 00 	            fclrf\.s1
+    189c:	00 00 04 00       	            nop\.i 0x0
+    18a0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    18a6:	00 00 00 0a 02 00 	            fclrf\.s2
+    18ac:	00 00 04 00       	            nop\.i 0x0
+    18b0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    18b6:	00 00 00 0a 03 00 	            fclrf\.s3
+    18bc:	00 00 04 00       	            nop\.i 0x0
+    18c0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    18c6:	40 e7 ff 10 04 00 	            fchkf\.s0 0 <_start>
+    18cc:	00 00 04 00       	            nop\.i 0x0
+    18d0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    18d6:	30 e7 ff 10 04 00 	            fchkf\.s0 0 <_start>
+    18dc:	00 00 04 00       	            nop\.i 0x0
+    18e0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    18e6:	20 e7 ff 10 05 00 	            fchkf\.s1 0 <_start>
+    18ec:	00 00 04 00       	            nop\.i 0x0
+    18f0:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    18f6:	10 e7 ff 10 06 00 	            fchkf\.s2 0 <_start>
+    18fc:	00 00 04 00       	            nop\.i 0x0
+    1900:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1906:	00 e7 ff 10 07 00 	            fchkf\.s3 0 <_start>
+    190c:	00 00 04 00       	            nop\.i 0x0
+    1910:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+	\.\.\.
+    191e:	04 00 0c 00       	            nop\.i 0x0
+    1922:	00 00 01 00 00 00 	\[MFI\]       nop\.m 0x0
+    1928:	00 02 00 00 00 00 	            nop\.f 0x0
+    192e:	04 00 00 00       	            nop\.i 0x0
diff --git a/gas/testsuite/gas/ia64/opc-f.pl b/gas/testsuite/gas/ia64/opc-f.pl
new file mode 100644
index 0000000..d1862c2
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-f.pl
@@ -0,0 +1,163 @@
+print ".text\n\t.type _start,@", "function\n_start:\n\n";
+
+@sf = ( "", ".s0", ".s1", ".s2", ".s3" );
+
+# Arithmetic
+
+foreach $i ( "fma", "fma.s", "fma.d", "fpma",
+	     "fms", "fms.s", "fms.d", "fpms",
+	     "fnma", "fnma.s", "fnma.d", "fpnma" ) {
+  foreach $s (@sf) {
+    print "\t${i}${s} f4 = f5, f6, f7\n";
+  }
+  print "\n";
+}
+
+foreach $i ( "fmpy", "fmpy.s", "fmpy.d", "fpmpy",
+	     "fadd", "fadd.s", "fadd.d", #"fpadd", ??? ias doesn't eat it
+	     "fsub", "fsub.s", "fsub.d", "fpsub",
+	     "fnmpy", "fnmpy.s", "fnmpy.d", "fpnmpy" ) {
+  foreach $s (@sf) {
+    print "\t${i}${s} f4 = f5, f6\n";
+  }
+  print "\n";
+}
+
+foreach $i ( "fnorm", "fnorm.s", "fnorm.d" ) { 
+  foreach $s (@sf) {
+    print "\t${i}${s} f4 = f5\n";
+  }
+  print "\n";
+}
+
+# Fixed Point Multiply Add
+
+foreach $s ( ".l", ".lu", ".h", ".hu" ) {
+  print "\txma${s} f4 = f5, f6, f7\n";
+}
+print "\n";
+
+foreach $s ( ".l", ".lu", ".h", ".hu" ) {
+  print "\txmpy${s} f4 = f5, f6\n";
+}
+print "\n";
+
+# Parallel Floating Point Select
+
+print "\tfselect f4 = f5, f6, f7\n\n";
+
+# Floating Point Compare
+
+@cmp = ( ".eq", ".lt", ".le", ".unord", ".gt", ".ge", ".neq", ".nlt", 
+	 ".nle", ".ngt", ".nge", ".ord" );
+
+# Floating Point Class
+
+foreach $u ( "", ".unc" ) {
+  foreach $c ( '@nat', '@qnan', '@snan', '@pos', '@neg', '@unorm',
+	       '@norm', '@inf', '0x1ff' ) {
+    foreach $m ( ".m", ".nm" ) {
+      print "\tfclass${m}${u} p3, p4 = f4, $c\n";
+    }
+  }
+  print "\n";
+}
+
+# Approximation
+
+foreach $i ( "frcpa", "fprcpa" ) {
+  foreach $s (@sf) {
+    print "\t${i}${s} f4, p5 = f6, f7\n";
+  }
+  print "\n";
+}
+
+foreach $i ( "frsqrta", "fprsqrta" ) {
+  foreach $s (@sf) {
+    print "\t${i}${s} f4, p5 = f6\n";
+  }
+  print "\n";
+}
+
+# Min/Max
+
+foreach $i ( "fmin", "fmax", "famin", "famax",
+	     "fpmin", "fpmax", "fpamin", "fpamax" ) {
+  foreach $s (@sf) {
+    print "\t${i}${s} f4 = f5, f6\n";
+  }
+  print "\n";
+}
+
+# Parallel Compare
+
+foreach $c (@cmp) {
+  foreach $s (@sf) {
+    print "\tfcmp${c}${u}${s} p3, p4 = f4, f5\n";
+  }
+  print "\n";
+}
+
+# Merge and Logical
+
+foreach $i ( "fmerge.s", "fmerge.ns", "fmerge.se", "fmix.lr", "fmix.r",
+	     "fmix.l", "fsxt.l", "fpack", "fswap", "fswap.nl", "fswap.nr",
+	     "fand", "fandcm", "for", "fxor", "fpmerge.s", "fpmerge.ns",
+	     "fpmerge.se" ) {
+  print "\t$i f4 = f5, f6\n";
+}
+print "\n";
+
+foreach $i ( "fabs", "fneg", "fnegabs", "fpabs", "fpneg", "fpnegabs" ) {
+  print "\t$i f4 = f5\n";
+}
+print "\n";
+
+# Convert Floating to Fixed
+
+foreach $b ( "fcvt", "fpcvt" ) {
+  foreach $f ( ".fx", ".fxu" ) {
+    foreach $t ( "", ".trunc" ) {
+      foreach $s (@sf) {
+	print "\t${b}${f}${t}${s} f4 = f5\n";
+      }
+      print "\n";
+    }
+  }
+}
+
+# Convert Fixed to Floating
+
+foreach $e ( ".xf", ".xuf" ) {
+  print "\tfcvt$e f4 = f5\n";
+}
+print "\n";
+
+# Set Controls
+
+foreach $s (@sf) {
+  print "\tfsetc$s 0, 0\n";
+  print "\tfsetc$s 0x3f, 0x3f\n";
+}
+print "\n";
+
+# Clear flags
+
+foreach $s (@sf) {
+  print "\tfclrf$s\n";
+}
+print "\n";
+
+# Check flags
+
+foreach $s (@sf) {
+  print "\tfchkf$s _start\n";
+}
+print "\n";
+
+# Misc
+
+print "\tbreak.f 0\n";
+print "\tnop.f 0\n";
+print "\n";
+
diff --git a/gas/testsuite/gas/ia64/opc-f.s b/gas/testsuite/gas/ia64/opc-f.s
new file mode 100644
index 0000000..8784bb9
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-f.s
@@ -0,0 +1,481 @@
+.text
+	.type _start,@function
+_start:
+
+	fma f4 = f5, f6, f7
+	fma.s0 f4 = f5, f6, f7
+	fma.s1 f4 = f5, f6, f7
+	fma.s2 f4 = f5, f6, f7
+	fma.s3 f4 = f5, f6, f7
+
+	fma.s f4 = f5, f6, f7
+	fma.s.s0 f4 = f5, f6, f7
+	fma.s.s1 f4 = f5, f6, f7
+	fma.s.s2 f4 = f5, f6, f7
+	fma.s.s3 f4 = f5, f6, f7
+
+	fma.d f4 = f5, f6, f7
+	fma.d.s0 f4 = f5, f6, f7
+	fma.d.s1 f4 = f5, f6, f7
+	fma.d.s2 f4 = f5, f6, f7
+	fma.d.s3 f4 = f5, f6, f7
+
+	fpma f4 = f5, f6, f7
+	fpma.s0 f4 = f5, f6, f7
+	fpma.s1 f4 = f5, f6, f7
+	fpma.s2 f4 = f5, f6, f7
+	fpma.s3 f4 = f5, f6, f7
+
+	fms f4 = f5, f6, f7
+	fms.s0 f4 = f5, f6, f7
+	fms.s1 f4 = f5, f6, f7
+	fms.s2 f4 = f5, f6, f7
+	fms.s3 f4 = f5, f6, f7
+
+	fms.s f4 = f5, f6, f7
+	fms.s.s0 f4 = f5, f6, f7
+	fms.s.s1 f4 = f5, f6, f7
+	fms.s.s2 f4 = f5, f6, f7
+	fms.s.s3 f4 = f5, f6, f7
+
+	fms.d f4 = f5, f6, f7
+	fms.d.s0 f4 = f5, f6, f7
+	fms.d.s1 f4 = f5, f6, f7
+	fms.d.s2 f4 = f5, f6, f7
+	fms.d.s3 f4 = f5, f6, f7
+
+	fpms f4 = f5, f6, f7
+	fpms.s0 f4 = f5, f6, f7
+	fpms.s1 f4 = f5, f6, f7
+	fpms.s2 f4 = f5, f6, f7
+	fpms.s3 f4 = f5, f6, f7
+
+	fnma f4 = f5, f6, f7
+	fnma.s0 f4 = f5, f6, f7
+	fnma.s1 f4 = f5, f6, f7
+	fnma.s2 f4 = f5, f6, f7
+	fnma.s3 f4 = f5, f6, f7
+
+	fnma.s f4 = f5, f6, f7
+	fnma.s.s0 f4 = f5, f6, f7
+	fnma.s.s1 f4 = f5, f6, f7
+	fnma.s.s2 f4 = f5, f6, f7
+	fnma.s.s3 f4 = f5, f6, f7
+
+	fnma.d f4 = f5, f6, f7
+	fnma.d.s0 f4 = f5, f6, f7
+	fnma.d.s1 f4 = f5, f6, f7
+	fnma.d.s2 f4 = f5, f6, f7
+	fnma.d.s3 f4 = f5, f6, f7
+
+	fpnma f4 = f5, f6, f7
+	fpnma.s0 f4 = f5, f6, f7
+	fpnma.s1 f4 = f5, f6, f7
+	fpnma.s2 f4 = f5, f6, f7
+	fpnma.s3 f4 = f5, f6, f7
+
+	fmpy f4 = f5, f6
+	fmpy.s0 f4 = f5, f6
+	fmpy.s1 f4 = f5, f6
+	fmpy.s2 f4 = f5, f6
+	fmpy.s3 f4 = f5, f6
+
+	fmpy.s f4 = f5, f6
+	fmpy.s.s0 f4 = f5, f6
+	fmpy.s.s1 f4 = f5, f6
+	fmpy.s.s2 f4 = f5, f6
+	fmpy.s.s3 f4 = f5, f6
+
+	fmpy.d f4 = f5, f6
+	fmpy.d.s0 f4 = f5, f6
+	fmpy.d.s1 f4 = f5, f6
+	fmpy.d.s2 f4 = f5, f6
+	fmpy.d.s3 f4 = f5, f6
+
+	fpmpy f4 = f5, f6
+	fpmpy.s0 f4 = f5, f6
+	fpmpy.s1 f4 = f5, f6
+	fpmpy.s2 f4 = f5, f6
+	fpmpy.s3 f4 = f5, f6
+
+	fadd f4 = f5, f6
+	fadd.s0 f4 = f5, f6
+	fadd.s1 f4 = f5, f6
+	fadd.s2 f4 = f5, f6
+	fadd.s3 f4 = f5, f6
+
+	fadd.s f4 = f5, f6
+	fadd.s.s0 f4 = f5, f6
+	fadd.s.s1 f4 = f5, f6
+	fadd.s.s2 f4 = f5, f6
+	fadd.s.s3 f4 = f5, f6
+
+	fadd.d f4 = f5, f6
+	fadd.d.s0 f4 = f5, f6
+	fadd.d.s1 f4 = f5, f6
+	fadd.d.s2 f4 = f5, f6
+	fadd.d.s3 f4 = f5, f6
+
+	fsub f4 = f5, f6
+	fsub.s0 f4 = f5, f6
+	fsub.s1 f4 = f5, f6
+	fsub.s2 f4 = f5, f6
+	fsub.s3 f4 = f5, f6
+
+	fsub.s f4 = f5, f6
+	fsub.s.s0 f4 = f5, f6
+	fsub.s.s1 f4 = f5, f6
+	fsub.s.s2 f4 = f5, f6
+	fsub.s.s3 f4 = f5, f6
+
+	fsub.d f4 = f5, f6
+	fsub.d.s0 f4 = f5, f6
+	fsub.d.s1 f4 = f5, f6
+	fsub.d.s2 f4 = f5, f6
+	fsub.d.s3 f4 = f5, f6
+
+	fpsub f4 = f5, f6
+	fpsub.s0 f4 = f5, f6
+	fpsub.s1 f4 = f5, f6
+	fpsub.s2 f4 = f5, f6
+	fpsub.s3 f4 = f5, f6
+
+	fnmpy f4 = f5, f6
+	fnmpy.s0 f4 = f5, f6
+	fnmpy.s1 f4 = f5, f6
+	fnmpy.s2 f4 = f5, f6
+	fnmpy.s3 f4 = f5, f6
+
+	fnmpy.s f4 = f5, f6
+	fnmpy.s.s0 f4 = f5, f6
+	fnmpy.s.s1 f4 = f5, f6
+	fnmpy.s.s2 f4 = f5, f6
+	fnmpy.s.s3 f4 = f5, f6
+
+	fnmpy.d f4 = f5, f6
+	fnmpy.d.s0 f4 = f5, f6
+	fnmpy.d.s1 f4 = f5, f6
+	fnmpy.d.s2 f4 = f5, f6
+	fnmpy.d.s3 f4 = f5, f6
+
+	fpnmpy f4 = f5, f6
+	fpnmpy.s0 f4 = f5, f6
+	fpnmpy.s1 f4 = f5, f6
+	fpnmpy.s2 f4 = f5, f6
+	fpnmpy.s3 f4 = f5, f6
+
+	fnorm f4 = f5
+	fnorm.s0 f4 = f5
+	fnorm.s1 f4 = f5
+	fnorm.s2 f4 = f5
+	fnorm.s3 f4 = f5
+
+	fnorm.s f4 = f5
+	fnorm.s.s0 f4 = f5
+	fnorm.s.s1 f4 = f5
+	fnorm.s.s2 f4 = f5
+	fnorm.s.s3 f4 = f5
+
+	fnorm.d f4 = f5
+	fnorm.d.s0 f4 = f5
+	fnorm.d.s1 f4 = f5
+	fnorm.d.s2 f4 = f5
+	fnorm.d.s3 f4 = f5
+
+	xma.l f4 = f5, f6, f7
+	xma.lu f4 = f5, f6, f7
+	xma.h f4 = f5, f6, f7
+	xma.hu f4 = f5, f6, f7
+
+	xmpy.l f4 = f5, f6
+	xmpy.lu f4 = f5, f6
+	xmpy.h f4 = f5, f6
+	xmpy.hu f4 = f5, f6
+
+	fselect f4 = f5, f6, f7
+
+	fclass.m p3, p4 = f4, @nat
+	fclass.nm p3, p4 = f4, @nat
+	fclass.m p3, p4 = f4, @qnan
+	fclass.nm p3, p4 = f4, @qnan
+	fclass.m p3, p4 = f4, @snan
+	fclass.nm p3, p4 = f4, @snan
+	fclass.m p3, p4 = f4, @pos
+	fclass.nm p3, p4 = f4, @pos
+	fclass.m p3, p4 = f4, @neg
+	fclass.nm p3, p4 = f4, @neg
+	fclass.m p3, p4 = f4, @unorm
+	fclass.nm p3, p4 = f4, @unorm
+	fclass.m p3, p4 = f4, @norm
+	fclass.nm p3, p4 = f4, @norm
+	fclass.m p3, p4 = f4, @inf
+	fclass.nm p3, p4 = f4, @inf
+	fclass.m p3, p4 = f4, 0x1ff
+	fclass.nm p3, p4 = f4, 0x1ff
+
+	fclass.m.unc p3, p4 = f4, @nat
+	fclass.nm.unc p3, p4 = f4, @nat
+	fclass.m.unc p3, p4 = f4, @qnan
+	fclass.nm.unc p3, p4 = f4, @qnan
+	fclass.m.unc p3, p4 = f4, @snan
+	fclass.nm.unc p3, p4 = f4, @snan
+	fclass.m.unc p3, p4 = f4, @pos
+	fclass.nm.unc p3, p4 = f4, @pos
+	fclass.m.unc p3, p4 = f4, @neg
+	fclass.nm.unc p3, p4 = f4, @neg
+	fclass.m.unc p3, p4 = f4, @unorm
+	fclass.nm.unc p3, p4 = f4, @unorm
+	fclass.m.unc p3, p4 = f4, @norm
+	fclass.nm.unc p3, p4 = f4, @norm
+	fclass.m.unc p3, p4 = f4, @inf
+	fclass.nm.unc p3, p4 = f4, @inf
+	fclass.m.unc p3, p4 = f4, 0x1ff
+	fclass.nm.unc p3, p4 = f4, 0x1ff
+
+	frcpa f4, p5 = f6, f7
+	frcpa.s0 f4, p5 = f6, f7
+	frcpa.s1 f4, p5 = f6, f7
+	frcpa.s2 f4, p5 = f6, f7
+	frcpa.s3 f4, p5 = f6, f7
+
+	fprcpa f4, p5 = f6, f7
+	fprcpa.s0 f4, p5 = f6, f7
+	fprcpa.s1 f4, p5 = f6, f7
+	fprcpa.s2 f4, p5 = f6, f7
+	fprcpa.s3 f4, p5 = f6, f7
+
+	frsqrta f4, p5 = f6
+	frsqrta.s0 f4, p5 = f6
+	frsqrta.s1 f4, p5 = f6
+	frsqrta.s2 f4, p5 = f6
+	frsqrta.s3 f4, p5 = f6
+
+	fprsqrta f4, p5 = f6
+	fprsqrta.s0 f4, p5 = f6
+	fprsqrta.s1 f4, p5 = f6
+	fprsqrta.s2 f4, p5 = f6
+	fprsqrta.s3 f4, p5 = f6
+
+	fmin f4 = f5, f6
+	fmin.s0 f4 = f5, f6
+	fmin.s1 f4 = f5, f6
+	fmin.s2 f4 = f5, f6
+	fmin.s3 f4 = f5, f6
+
+	fmax f4 = f5, f6
+	fmax.s0 f4 = f5, f6
+	fmax.s1 f4 = f5, f6
+	fmax.s2 f4 = f5, f6
+	fmax.s3 f4 = f5, f6
+
+	famin f4 = f5, f6
+	famin.s0 f4 = f5, f6
+	famin.s1 f4 = f5, f6
+	famin.s2 f4 = f5, f6
+	famin.s3 f4 = f5, f6
+
+	famax f4 = f5, f6
+	famax.s0 f4 = f5, f6
+	famax.s1 f4 = f5, f6
+	famax.s2 f4 = f5, f6
+	famax.s3 f4 = f5, f6
+
+	fpmin f4 = f5, f6
+	fpmin.s0 f4 = f5, f6
+	fpmin.s1 f4 = f5, f6
+	fpmin.s2 f4 = f5, f6
+	fpmin.s3 f4 = f5, f6
+
+	fpmax f4 = f5, f6
+	fpmax.s0 f4 = f5, f6
+	fpmax.s1 f4 = f5, f6
+	fpmax.s2 f4 = f5, f6
+	fpmax.s3 f4 = f5, f6
+
+	fpamin f4 = f5, f6
+	fpamin.s0 f4 = f5, f6
+	fpamin.s1 f4 = f5, f6
+	fpamin.s2 f4 = f5, f6
+	fpamin.s3 f4 = f5, f6
+
+	fpamax f4 = f5, f6
+	fpamax.s0 f4 = f5, f6
+	fpamax.s1 f4 = f5, f6
+	fpamax.s2 f4 = f5, f6
+	fpamax.s3 f4 = f5, f6
+
+	fcmp.eq p3, p4 = f4, f5
+	fcmp.eq.s0 p3, p4 = f4, f5
+	fcmp.eq.s1 p3, p4 = f4, f5
+	fcmp.eq.s2 p3, p4 = f4, f5
+	fcmp.eq.s3 p3, p4 = f4, f5
+
+	fcmp.lt p3, p4 = f4, f5
+	fcmp.lt.s0 p3, p4 = f4, f5
+	fcmp.lt.s1 p3, p4 = f4, f5
+	fcmp.lt.s2 p3, p4 = f4, f5
+	fcmp.lt.s3 p3, p4 = f4, f5
+
+	fcmp.le p3, p4 = f4, f5
+	fcmp.le.s0 p3, p4 = f4, f5
+	fcmp.le.s1 p3, p4 = f4, f5
+	fcmp.le.s2 p3, p4 = f4, f5
+	fcmp.le.s3 p3, p4 = f4, f5
+
+	fcmp.unord p3, p4 = f4, f5
+	fcmp.unord.s0 p3, p4 = f4, f5
+	fcmp.unord.s1 p3, p4 = f4, f5
+	fcmp.unord.s2 p3, p4 = f4, f5
+	fcmp.unord.s3 p3, p4 = f4, f5
+
+	fcmp.gt p3, p4 = f4, f5
+	fcmp.gt.s0 p3, p4 = f4, f5
+	fcmp.gt.s1 p3, p4 = f4, f5
+	fcmp.gt.s2 p3, p4 = f4, f5
+	fcmp.gt.s3 p3, p4 = f4, f5
+
+	fcmp.ge p3, p4 = f4, f5
+	fcmp.ge.s0 p3, p4 = f4, f5
+	fcmp.ge.s1 p3, p4 = f4, f5
+	fcmp.ge.s2 p3, p4 = f4, f5
+	fcmp.ge.s3 p3, p4 = f4, f5
+
+	fcmp.neq p3, p4 = f4, f5
+	fcmp.neq.s0 p3, p4 = f4, f5
+	fcmp.neq.s1 p3, p4 = f4, f5
+	fcmp.neq.s2 p3, p4 = f4, f5
+	fcmp.neq.s3 p3, p4 = f4, f5
+
+	fcmp.nlt p3, p4 = f4, f5
+	fcmp.nlt.s0 p3, p4 = f4, f5
+	fcmp.nlt.s1 p3, p4 = f4, f5
+	fcmp.nlt.s2 p3, p4 = f4, f5
+	fcmp.nlt.s3 p3, p4 = f4, f5
+
+	fcmp.nle p3, p4 = f4, f5
+	fcmp.nle.s0 p3, p4 = f4, f5
+	fcmp.nle.s1 p3, p4 = f4, f5
+	fcmp.nle.s2 p3, p4 = f4, f5
+	fcmp.nle.s3 p3, p4 = f4, f5
+
+	fcmp.ngt p3, p4 = f4, f5
+	fcmp.ngt.s0 p3, p4 = f4, f5
+	fcmp.ngt.s1 p3, p4 = f4, f5
+	fcmp.ngt.s2 p3, p4 = f4, f5
+	fcmp.ngt.s3 p3, p4 = f4, f5
+
+	fcmp.nge p3, p4 = f4, f5
+	fcmp.nge.s0 p3, p4 = f4, f5
+	fcmp.nge.s1 p3, p4 = f4, f5
+	fcmp.nge.s2 p3, p4 = f4, f5
+	fcmp.nge.s3 p3, p4 = f4, f5
+
+	fcmp.ord p3, p4 = f4, f5
+	fcmp.ord.s0 p3, p4 = f4, f5
+	fcmp.ord.s1 p3, p4 = f4, f5
+	fcmp.ord.s2 p3, p4 = f4, f5
+	fcmp.ord.s3 p3, p4 = f4, f5
+
+	fmerge.s f4 = f5, f6
+	fmerge.ns f4 = f5, f6
+	fmerge.se f4 = f5, f6
+	fmix.lr f4 = f5, f6
+	fmix.r f4 = f5, f6
+	fmix.l f4 = f5, f6
+	fsxt.l f4 = f5, f6
+	fpack f4 = f5, f6
+	fswap f4 = f5, f6
+	fswap.nl f4 = f5, f6
+	fswap.nr f4 = f5, f6
+	fand f4 = f5, f6
+	fandcm f4 = f5, f6
+	for f4 = f5, f6
+	fxor f4 = f5, f6
+	fpmerge.s f4 = f5, f6
+	fpmerge.ns f4 = f5, f6
+	fpmerge.se f4 = f5, f6
+
+	fabs f4 = f5
+	fneg f4 = f5
+	fnegabs f4 = f5
+	fpabs f4 = f5
+	fpneg f4 = f5
+	fpnegabs f4 = f5
+
+	fcvt.fx f4 = f5
+	fcvt.fx.s0 f4 = f5
+	fcvt.fx.s1 f4 = f5
+	fcvt.fx.s2 f4 = f5
+	fcvt.fx.s3 f4 = f5
+
+	fcvt.fx.trunc f4 = f5
+	fcvt.fx.trunc.s0 f4 = f5
+	fcvt.fx.trunc.s1 f4 = f5
+	fcvt.fx.trunc.s2 f4 = f5
+	fcvt.fx.trunc.s3 f4 = f5
+
+	fcvt.fxu f4 = f5
+	fcvt.fxu.s0 f4 = f5
+	fcvt.fxu.s1 f4 = f5
+	fcvt.fxu.s2 f4 = f5
+	fcvt.fxu.s3 f4 = f5
+
+	fcvt.fxu.trunc f4 = f5
+	fcvt.fxu.trunc.s0 f4 = f5
+	fcvt.fxu.trunc.s1 f4 = f5
+	fcvt.fxu.trunc.s2 f4 = f5
+	fcvt.fxu.trunc.s3 f4 = f5
+
+	fpcvt.fx f4 = f5
+	fpcvt.fx.s0 f4 = f5
+	fpcvt.fx.s1 f4 = f5
+	fpcvt.fx.s2 f4 = f5
+	fpcvt.fx.s3 f4 = f5
+
+	fpcvt.fx.trunc f4 = f5
+	fpcvt.fx.trunc.s0 f4 = f5
+	fpcvt.fx.trunc.s1 f4 = f5
+	fpcvt.fx.trunc.s2 f4 = f5
+	fpcvt.fx.trunc.s3 f4 = f5
+
+	fpcvt.fxu f4 = f5
+	fpcvt.fxu.s0 f4 = f5
+	fpcvt.fxu.s1 f4 = f5
+	fpcvt.fxu.s2 f4 = f5
+	fpcvt.fxu.s3 f4 = f5
+
+	fpcvt.fxu.trunc f4 = f5
+	fpcvt.fxu.trunc.s0 f4 = f5
+	fpcvt.fxu.trunc.s1 f4 = f5
+	fpcvt.fxu.trunc.s2 f4 = f5
+	fpcvt.fxu.trunc.s3 f4 = f5
+
+	fcvt.xf f4 = f5
+	fcvt.xuf f4 = f5
+
+	fsetc 0, 0
+	fsetc 0x3f, 0x3f
+	fsetc.s0 0, 0
+	fsetc.s0 0x3f, 0x3f
+	fsetc.s1 0, 0
+	fsetc.s1 0x3f, 0x3f
+	fsetc.s2 0, 0
+	fsetc.s2 0x3f, 0x3f
+	fsetc.s3 0, 0
+	fsetc.s3 0x3f, 0x3f
+
+	fclrf
+	fclrf.s0
+	fclrf.s1
+	fclrf.s2
+	fclrf.s3
+
+	fchkf _start
+	fchkf.s0 _start
+	fchkf.s1 _start
+	fchkf.s2 _start
+	fchkf.s3 _start
+
+	break.f 0
+	nop.f 0
+
diff --git a/gas/testsuite/gas/ia64/opc-i.d b/gas/testsuite/gas/ia64/opc-i.d
new file mode 100644
index 0000000..5b108fe
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-i.d
@@ -0,0 +1,245 @@
+# objdump: -d
+# name: ia64 opc-i
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <_start>:
+   0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+   6:	40 28 18 8c 38 80 	            pmpyshr2 r4=r5,r6,0
+   c:	50 30 68 71       	            pmpyshr2\.u r4=r5,r6,16
+  10:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+  16:	40 28 18 b4 3a 80 	            pmpy2\.r r4=r5,r6
+  1c:	50 30 78 75       	            pmpy2\.l r4=r5,r6
+  20:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+  26:	40 28 18 20 3a 80 	            mix1\.r r4=r5,r6
+  2c:	50 30 40 75       	            mix2\.r r4=r5,r6
+  30:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+  36:	40 28 18 20 3e 80 	            mix4\.r r4=r5,r6
+  3c:	50 30 50 74       	            mix1\.l r4=r5,r6
+  40:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+  46:	40 28 18 a8 3a 80 	            mix2\.l r4=r5,r6
+  4c:	50 30 50 7c       	            mix4\.l r4=r5,r6
+  50:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+  56:	40 28 18 80 3a 80 	            pack2\.uss r4=r5,r6
+  5c:	50 30 10 75       	            pack2\.sss r4=r5,r6
+  60:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+  66:	40 28 18 08 3e 80 	            pack4\.sss r4=r5,r6
+  6c:	50 30 20 74       	            unpack1\.h r4=r5,r6
+  70:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+  76:	40 28 18 90 3a 80 	            unpack2\.h r4=r5,r6
+  7c:	50 30 20 7c       	            unpack4\.h r4=r5,r6
+  80:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+  86:	40 28 18 18 3a 80 	            unpack1\.l r4=r5,r6
+  8c:	50 30 30 75       	            unpack2\.l r4=r5,r6
+  90:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+  96:	40 28 18 18 3e 80 	            unpack4\.l r4=r5,r6
+  9c:	50 30 08 74       	            pmin1\.u r4=r5,r6
+  a0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+  a6:	40 28 18 14 3a 80 	            pmax1\.u r4=r5,r6
+  ac:	50 30 18 75       	            pmin2\.u r4=r5,r6
+  b0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+  b6:	40 28 18 9c 3a 80 	            pmax2\.u r4=r5,r6
+  bc:	50 30 58 74       	            psad1 r4=r5,r6
+  c0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+  c6:	40 28 2c 28 3b 80 	            mux1 r4=r5,@rev
+  cc:	50 40 50 76       	            mux1 r4=r5,@mix
+  d0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+  d6:	40 28 24 28 3b 80 	            mux1 r4=r5,@shuf
+  dc:	50 50 50 76       	            mux1 r4=r5,@alt
+  e0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+  e6:	40 28 00 28 3b 80 	            mux1 r4=r5,@brcst
+  ec:	50 00 50 77       	            mux2 r4=r5,0x0
+  f0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+  f6:	40 28 fc ab 3b 80 	            mux2 r4=r5,0xff
+  fc:	50 50 55 77       	            mux2 r4=r5,0xaa
+ 100:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 106:	40 30 14 88 38 80 	            pshr2 r4=r5,r6
+ 10c:	00 28 18 73       	            pshr2 r4=r5,0
+ 110:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 116:	40 80 14 8c 39 80 	            pshr2 r4=r5,8
+ 11c:	e0 2b 18 73       	            pshr2 r4=r5,31
+ 120:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 126:	40 30 14 08 3c 80 	            pshr4 r4=r5,r6
+ 12c:	00 28 18 7a       	            pshr4 r4=r5,0
+ 130:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 136:	40 80 14 0c 3d 80 	            pshr4 r4=r5,8
+ 13c:	e0 2b 18 7a       	            pshr4 r4=r5,31
+ 140:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 146:	40 30 14 80 38 80 	            pshr2\.u r4=r5,r6
+ 14c:	00 28 08 73       	            pshr2\.u r4=r5,0
+ 150:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 156:	40 80 14 84 39 80 	            pshr2\.u r4=r5,8
+ 15c:	e0 2b 08 73       	            pshr2\.u r4=r5,31
+ 160:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 166:	40 30 14 00 3c 80 	            pshr4\.u r4=r5,r6
+ 16c:	00 28 08 7a       	            pshr4\.u r4=r5,0
+ 170:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 176:	40 80 14 04 3d 80 	            pshr4\.u r4=r5,8
+ 17c:	e0 2b 08 7a       	            pshr4\.u r4=r5,31
+ 180:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 186:	40 30 14 88 3c 80 	            shr r4=r5,r6
+ 18c:	60 28 00 79       	            shr\.u r4=r5,r6
+ 190:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 196:	40 28 18 90 38 80 	            pshl2 r4=r5,r6
+ 19c:	50 f8 28 77       	            pshl2 r4=r5,0
+ 1a0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 1a6:	40 28 5c 94 3b 80 	            pshl2 r4=r5,8
+ 1ac:	50 00 28 77       	            pshl2 r4=r5,31
+ 1b0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 1b6:	40 28 18 10 3c 80 	            pshl4 r4=r5,r6
+ 1bc:	50 f8 28 7e       	            pshl4 r4=r5,0
+ 1c0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 1c6:	40 28 5c 14 3f 80 	            pshl4 r4=r5,8
+ 1cc:	50 00 28 7e       	            pshl4 r4=r5,31
+ 1d0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 1d6:	40 28 18 90 3c 80 	            shl r4=r5,r6
+ 1dc:	00 28 48 73       	            popcnt r4=r5
+ 1e0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 1e6:	40 28 18 00 2b 80 	            shrp r4=r5,r6,0
+ 1ec:	50 30 30 56       	            shrp r4=r5,r6,12
+ 1f0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 1f6:	40 28 18 7e 2b 80 	            shrp r4=r5,r6,63
+ 1fc:	10 28 3c 52       	            extr r4=r5,0,16
+ 200:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 206:	40 08 14 7c 29 80 	            extr r4=r5,0,63
+ 20c:	50 29 9c 52       	            extr r4=r5,10,40
+ 210:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 216:	40 00 14 1e 29 80 	            extr\.u r4=r5,0,16
+ 21c:	00 28 f8 52       	            extr\.u r4=r5,0,63
+ 220:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 226:	40 a0 14 4e 29 80 	            extr\.u r4=r5,10,40
+ 22c:	50 f8 3d 53       	            dep\.z r4=r5,0,16
+ 230:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 236:	40 28 fc fc 29 80 	            dep\.z r4=r5,0,63
+ 23c:	50 a8 9d 53       	            dep\.z r4=r5,10,40
+ 240:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 246:	40 00 fc 9f 29 80 	            dep\.z r4=0,0,16
+ 24c:	f0 ff fb 53       	            dep\.z r4=127,0,63
+ 250:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 256:	40 00 e8 e3 2d 80 	            dep\.z r4=-128,5,50
+ 25c:	50 ad 9f 53       	            dep\.z r4=85,10,40
+ 260:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 266:	40 f0 17 9e 2b 80 	            dep r4=0,r5,0,16
+ 26c:	e0 2f f8 5f       	            dep r4=-1,r5,0,63
+ 270:	0c 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+ 276:	00 00 00 02 00 80 	            nop\.f 0x0
+ 27c:	50 30 58 4d       	            dep r4=r5,r6,10,7
+ 280:	04 00 00 00 01 00 	\[MLI\]       nop\.m 0x0
+ 286:	00 00 00 00 00 80 	            movl r4=0x0
+ 28c:	00 00 00 60 
+ 290:	04 00 00 00 01 c0 	\[MLI\]       nop\.m 0x0
+ 296:	ff ff ff ff 7f 80 	            movl r4=0xffffffffffffffff
+ 29c:	f0 f7 ff 6f 
+ 2a0:	04 00 00 00 01 80 	\[MLI\]       nop\.m 0x0
+ 2a6:	90 78 56 34 12 80 	            movl r4=0x1234567890abcdef
+ 2ac:	f0 76 6d 66 
+ 2b0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 2b6:	00 00 00 00 00 e0 	            break\.i 0x0
+ 2bc:	ff ff 01 08       	            break\.i 0x1fffff
+ 2c0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 2c6:	00 00 00 02 00 e0 	            nop\.i 0x0
+ 2cc:	ff ff 05 08       	            nop\.i 0x1fffff
+ 2d0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 2d6:	30 25 fc ff 04 80 	            chk\.s\.i r4,0 <_start>
+ 2dc:	00 00 c4 00       	            mov r4=b0
+ 2e0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 2e6:	00 20 04 80 03 00 	            mov b0=r4
+ 2ec:	40 00 00 03       	            mov pr=r4,0x0
+ 2f0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 2f6:	a0 21 80 84 01 e0 	            mov pr=r4,0x1234
+ 2fc:	4f 80 7f 0b       	            mov pr=r4,0xfffffffffffffffe
+ 300:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 306:	00 00 00 00 01 e0 	            mov pr\.rot=0x0
+ 30c:	7f 00 00 02       	            mov pr\.rot=0x3ff0000
+ 310:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 316:	00 c0 ff 7f 05 80 	            mov pr\.rot=0xfffffffffc000000
+ 31c:	00 28 40 00       	            zxt1 r4=r5
+ 320:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 326:	40 00 14 22 00 80 	            zxt2 r4=r5
+ 32c:	00 28 48 00       	            zxt4 r4=r5
+ 330:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 336:	40 00 14 28 00 80 	            sxt1 r4=r5
+ 33c:	00 28 54 00       	            sxt2 r4=r5
+ 340:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 346:	40 00 14 2c 00 80 	            sxt4 r4=r5
+ 34c:	00 28 60 00       	            czx1\.l r4=r5
+ 350:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 356:	40 00 14 32 00 80 	            czx2\.l r4=r5
+ 35c:	00 28 70 00       	            czx1\.r r4=r5
+ 360:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 366:	40 00 14 3a 00 40 	            czx2\.r r4=r5
+ 36c:	00 20 0c 50       	            tbit\.z p2,p3=r4,0
+ 370:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 376:	20 14 10 06 28 40 	            tbit\.z\.unc p2,p3=r4,1
+ 37c:	40 20 0c 58       	            tbit\.z\.and p2,p3=r4,2
+ 380:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 386:	20 30 10 86 28 40 	            tbit\.z\.or p2,p3=r4,3
+ 38c:	80 20 0c 59       	            tbit\.z\.or\.andcm p2,p3=r4,4
+ 390:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 396:	20 54 10 86 28 40 	            tbit\.nz\.or p2,p3=r4,5
+ 39c:	c8 20 0c 58       	            tbit\.nz\.and p2,p3=r4,6
+ 3a0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 3a6:	30 74 10 84 2c 60 	            tbit\.nz\.or\.andcm p3,p2=r4,7
+ 3ac:	00 21 08 50       	            tbit\.z p3,p2=r4,8
+ 3b0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 3b6:	30 94 10 04 28 40 	            tbit\.z\.unc p3,p2=r4,9
+ 3bc:	48 21 0c 58       	            tbit\.nz\.and p2,p3=r4,10
+ 3c0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 3c6:	20 b4 10 86 28 40 	            tbit\.nz\.or p2,p3=r4,11
+ 3cc:	88 21 0c 59       	            tbit\.nz\.or\.andcm p2,p3=r4,12
+ 3d0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 3d6:	20 d0 10 86 28 40 	            tbit\.z\.or p2,p3=r4,13
+ 3dc:	c0 21 0c 58       	            tbit\.z\.and p2,p3=r4,14
+ 3e0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 3e6:	30 f0 10 84 2c 40 	            tbit\.z\.or\.andcm p3,p2=r4,15
+ 3ec:	10 20 0c 50       	            tnat\.z p2,p3=r4
+ 3f0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 3f6:	20 0c 10 06 28 40 	            tnat\.z\.unc p2,p3=r4
+ 3fc:	10 20 0c 58       	            tnat\.z\.and p2,p3=r4
+ 400:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 406:	20 08 10 86 28 40 	            tnat\.z\.or p2,p3=r4
+ 40c:	10 20 0c 59       	            tnat\.z\.or\.andcm p2,p3=r4
+ 410:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 416:	20 0c 10 86 28 40 	            tnat\.nz\.or p2,p3=r4
+ 41c:	18 20 0c 58       	            tnat\.nz\.and p2,p3=r4
+ 420:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 426:	30 0c 10 84 2c 60 	            tnat\.nz\.or\.andcm p3,p2=r4
+ 42c:	10 20 08 50       	            tnat\.z p3,p2=r4
+ 430:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 436:	30 0c 10 04 28 40 	            tnat\.z\.unc p3,p2=r4
+ 43c:	18 20 0c 58       	            tnat\.nz\.and p2,p3=r4
+ 440:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 446:	20 0c 10 86 28 40 	            tnat\.nz\.or p2,p3=r4
+ 44c:	18 20 0c 59       	            tnat\.nz\.or\.andcm p2,p3=r4
+ 450:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 456:	20 08 10 86 28 40 	            tnat\.z\.or p2,p3=r4
+ 45c:	10 20 0c 58       	            tnat\.z\.and p2,p3=r4
+ 460:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 466:	30 08 10 84 2c 60 	            tnat\.z\.or\.andcm p3,p2=r4
+ 46c:	40 88 04 07       	            mov b3=r4
+ 470:	01 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 476:	30 20 24 84 03 00 	            mov\.imp b3=r4,570 <_start\+0x570>
+ 47c:	00 00 04 00       	            nop\.i 0x0;;
+	\.\.\.
+ 570:	01 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 576:	30 20 00 84 03 60 	            mov\.sptk b3=r4,670 <_start\+0x670>
+ 57c:	40 40 08 07       	            mov\.sptk\.imp b3=r4,670 <_start\+0x670>;;
+	\.\.\.
+ 670:	01 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 676:	30 20 08 84 03 60 	            mov\.dptk b3=r4,770 <_start\+0x770>
+ 67c:	40 50 08 07       	            mov\.dptk\.imp b3=r4,770 <_start\+0x770>;;
+	\.\.\.
+ 770:	01 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 776:	30 20 14 84 03 60 	            mov\.ret b3=r4,870 <_start\+0x870>
+ 77c:	40 68 08 07       	            mov\.ret\.imp b3=r4,870 <_start\+0x870>;;
+	\.\.\.
+ 870:	01 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 876:	30 20 10 84 03 60 	            mov\.ret\.sptk b3=r4,970 <_start\+0x970>
+ 87c:	40 60 08 07       	            mov\.ret\.sptk\.imp b3=r4,970 <_start\+0x970>;;
+	\.\.\.
+ 970:	01 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ 976:	30 20 18 84 03 60 	            mov\.ret\.dptk b3=r4,a70 <_start\+0xa70>
+ 97c:	40 70 08 07       	            mov\.ret\.dptk\.imp b3=r4,a70 <_start\+0xa70>;;
+	\.\.\.
diff --git a/gas/testsuite/gas/ia64/opc-i.pl b/gas/testsuite/gas/ia64/opc-i.pl
new file mode 100644
index 0000000..ad2f7e8
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-i.pl
@@ -0,0 +1,186 @@
+$AT = '@';
+print <<END
+.text
+	.type _start,${AT}function
+_start:
+
+	pmpyshr2 r4 = r5, r6, 0
+	pmpyshr2.u r4 = r5, r6, 16
+
+	pmpy2.r r4 = r5, r6
+	pmpy2.l r4 = r5, r6
+
+	mix1.r r4 = r5, r6
+	mix2.r r4 = r5, r6
+	mix4.r r4 = r5, r6
+	mix1.l r4 = r5, r6
+	mix2.l r4 = r5, r6
+	mix4.l r4 = r5, r6
+
+	pack2.uss r4 = r5, r6
+	pack2.sss r4 = r5, r6
+	pack4.sss r4 = r5, r6
+
+	unpack1.h r4 = r5, r6
+	unpack2.h r4 = r5, r6
+	unpack4.h r4 = r5, r6
+	unpack1.l r4 = r5, r6
+	unpack2.l r4 = r5, r6
+	unpack4.l r4 = r5, r6
+
+	pmin1.u r4 = r5, r6
+	pmax1.u r4 = r5, r6
+
+	pmin2 r4 = r5, r6
+	pmax2 r4 = r5, r6
+
+	psad1 r4 = r5, r6
+
+	mux1 r4 = r5, ${AT}rev
+	mux1 r4 = r5, ${AT}mix
+	mux1 r4 = r5, ${AT}shuf
+	mux1 r4 = r5, ${AT}alt
+	mux1 r4 = r5, ${AT}brcst
+
+	mux2 r4 = r5, 0
+	mux2 r4 = r5, 0xff
+	mux2 r4 = r5, 0xaa
+
+	pshr2 r4 = r5, r6
+	pshr2 r4 = r5, 0
+	pshr2 r4 = r5, 8
+	pshr2 r4 = r5, 31
+
+	pshr4 r4 = r5, r6
+	pshr4 r4 = r5, 0
+	pshr4 r4 = r5, 8
+	pshr4 r4 = r5, 31
+
+	pshr2.u r4 = r5, r6
+	pshr2.u r4 = r5, 0
+	pshr2.u r4 = r5, 8
+	pshr2.u r4 = r5, 31
+
+	pshr4.u r4 = r5, r6
+	pshr4.u r4 = r5, 0
+	pshr4.u r4 = r5, 8
+	pshr4.u r4 = r5, 31
+
+	shr r4 = r5, r6
+	shr.u r4 = r5, r6
+
+	pshl2 r4 = r5, r6
+	pshl2 r4 = r5, 0
+	pshl2 r4 = r5, 8
+	pshl2 r4 = r5, 31
+
+	pshl4 r4 = r5, r6
+	pshl4 r4 = r5, 0
+	pshl4 r4 = r5, 8
+	pshl4 r4 = r5, 31
+
+	shl r4 = r5, r6
+
+	popcnt r4 = r5
+
+	shrp r4 = r5, r6, 0
+	shrp r4 = r5, r6, 12
+	shrp r4 = r5, r6, 63
+
+	extr r4 = r5, 0, 16
+	extr r4 = r5, 0, 63
+	extr r4 = r5, 10, 40
+	
+	extr.u r4 = r5, 0, 16
+	extr.u r4 = r5, 0, 63
+	extr.u r4 = r5, 10, 40
+	
+	dep.z r4 = r5, 0, 16
+	dep.z r4 = r5, 0, 63
+	dep.z r4 = r5, 10, 40
+	dep.z r4 = 0, 0, 16
+	dep.z r4 = 127, 0, 63
+	dep.z r4 = -128, 5, 50
+	dep.z r4 = 0x55, 10, 40
+
+	dep r4 = 0, r5, 0, 16
+	dep r4 = -1, r5, 0, 63
+	dep r4 = r5, r6, 10, 7
+
+	movl r4 = 0
+	movl r4 = 0xffffffffffffffff
+	movl r4 = 0x1234567890abcdef
+
+	break.i 0
+	break.i 0x1fffff
+
+	nop.i 0
+	nop.i 0x1fffff
+
+	chk.s.i r4, _start
+
+	mov r4 = b0
+	mov b0 = r4
+
+	mov pr = r4, 0
+	mov pr = r4, 0x1234
+	mov pr = r4, 0x1ffff
+
+	mov pr.rot = 0
+// ??? This was originally 0x3ffffff, but that generates an assembler warning
+// that the testsuite infrastructure isn't set up to ignore.
+	mov pr.rot = 0x3ff0000
+	mov pr.rot = -0x4000000
+
+	zxt1 r4 = r5
+	zxt2 r4 = r5
+	zxt4 r4 = r5
+
+	sxt1 r4 = r5
+	sxt2 r4 = r5
+	sxt4 r4 = r5
+
+	czx1.l r4 = r5
+	czx2.l r4 = r5
+	czx1.r r4 = r5
+	czx2.r r4 = r5
+
+END
+;
+
+@ctype = ( "", ".unc", ".and", ".or", ".or.andcm", ".orcm",
+	   ".andcm", ".and.orcm" );
+
+$i = 0;
+foreach $z ( ".z", ".nz" ) {
+  foreach $c (@ctype) {
+    print "\ttbit${z}${c} p2, p3 = r4, $i\n";
+    ++$i;
+  }
+}
+print "\n";
+
+foreach $z ( ".z", ".nz" ) {
+  foreach $c (@ctype) {
+    print "\ttnat${z}${c} p2, p3 = r4\n";
+  }
+}
+print "\n";
+
+
+@mwh = ( "", ".sptk", ".dptk" );
+@ih = ( "", ".imp" );
+
+$LAB = 1;
+
+foreach $b ("", ".ret") {
+  foreach $w (@mwh) {
+    foreach $i (@ih) {
+      print "\tmov${b}${w}${i} b3 = r4, .L${LAB}\n";
+    }
+    print ".space 240\n";
+    print ".L${LAB}:\n";
+    ++$LAB;
+  }
+  print "\n";
+}
diff --git a/gas/testsuite/gas/ia64/opc-i.s b/gas/testsuite/gas/ia64/opc-i.s
new file mode 100644
index 0000000..8be5a57
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-i.s
@@ -0,0 +1,383 @@
+.text
+	.type _start,@function
+_start:
+
+	pmpyshr2 r4 = r5, r6, 0
+	pmpyshr2.u r4 = r5, r6, 16
+
+	pmpy2.r r4 = r5, r6
+	pmpy2.l r4 = r5, r6
+
+	mix1.r r4 = r5, r6
+	mix2.r r4 = r5, r6
+	mix4.r r4 = r5, r6
+	mix1.l r4 = r5, r6
+	mix2.l r4 = r5, r6
+	mix4.l r4 = r5, r6
+
+	pack2.uss r4 = r5, r6
+	pack2.sss r4 = r5, r6
+	pack4.sss r4 = r5, r6
+
+	unpack1.h r4 = r5, r6
+	unpack2.h r4 = r5, r6
+	unpack4.h r4 = r5, r6
+	unpack1.l r4 = r5, r6
+	unpack2.l r4 = r5, r6
+	unpack4.l r4 = r5, r6
+
+	pmin1.u r4 = r5, r6
+	pmax1.u r4 = r5, r6
+
+	pmin2 r4 = r5, r6
+	pmax2 r4 = r5, r6
+
+	psad1 r4 = r5, r6
+
+	mux1 r4 = r5, @rev
+	mux1 r4 = r5, @mix
+	mux1 r4 = r5, @shuf
+	mux1 r4 = r5, @alt
+	mux1 r4 = r5, @brcst
+
+	mux2 r4 = r5, 0
+	mux2 r4 = r5, 0xff
+	mux2 r4 = r5, 0xaa
+
+	pshr2 r4 = r5, r6
+	pshr2 r4 = r5, 0
+	pshr2 r4 = r5, 8
+	pshr2 r4 = r5, 31
+
+	pshr4 r4 = r5, r6
+	pshr4 r4 = r5, 0
+	pshr4 r4 = r5, 8
+	pshr4 r4 = r5, 31
+
+	pshr2.u r4 = r5, r6
+	pshr2.u r4 = r5, 0
+	pshr2.u r4 = r5, 8
+	pshr2.u r4 = r5, 31
+
+	pshr4.u r4 = r5, r6
+	pshr4.u r4 = r5, 0
+	pshr4.u r4 = r5, 8
+	pshr4.u r4 = r5, 31
+
+	shr r4 = r5, r6
+	shr.u r4 = r5, r6
+
+	pshl2 r4 = r5, r6
+	pshl2 r4 = r5, 0
+	pshl2 r4 = r5, 8
+	pshl2 r4 = r5, 31
+
+	pshl4 r4 = r5, r6
+	pshl4 r4 = r5, 0
+	pshl4 r4 = r5, 8
+	pshl4 r4 = r5, 31
+
+	shl r4 = r5, r6
+
+	popcnt r4 = r5
+
+	shrp r4 = r5, r6, 0
+	shrp r4 = r5, r6, 12
+	shrp r4 = r5, r6, 63
+
+	extr r4 = r5, 0, 16
+	extr r4 = r5, 0, 63
+	extr r4 = r5, 10, 40
+	
+	extr.u r4 = r5, 0, 16
+	extr.u r4 = r5, 0, 63
+	extr.u r4 = r5, 10, 40
+	
+	dep.z r4 = r5, 0, 16
+	dep.z r4 = r5, 0, 63
+	dep.z r4 = r5, 10, 40
+	dep.z r4 = 0, 0, 16
+	dep.z r4 = 127, 0, 63
+	dep.z r4 = -128, 5, 50
+	dep.z r4 = 0x55, 10, 40
+
+	dep r4 = 0, r5, 0, 16
+	dep r4 = -1, r5, 0, 63
+	dep r4 = r5, r6, 10, 7
+
+	movl r4 = 0
+	movl r4 = 0xffffffffffffffff
+	movl r4 = 0x1234567890abcdef
+
+	break.i 0
+	break.i 0x1fffff
+
+	nop.i 0
+	nop.i 0x1fffff
+
+	chk.s.i r4, _start
+
+	mov r4 = b0
+	mov b0 = r4
+
+	mov pr = r4, 0
+	mov pr = r4, 0x1234
+	mov pr = r4, 0x1ffff
+
+	mov pr.rot = 0
+	mov pr.rot = 0x3ff0000
+	mov pr.rot = -0x4000000
+
+	zxt1 r4 = r5
+	zxt2 r4 = r5
+	zxt4 r4 = r5
+
+	sxt1 r4 = r5
+	sxt2 r4 = r5
+	sxt4 r4 = r5
+
+	czx1.l r4 = r5
+	czx2.l r4 = r5
+	czx1.r r4 = r5
+	czx2.r r4 = r5
+
+	tbit.z p2, p3 = r4, 0
+	tbit.z.unc p2, p3 = r4, 1
+	tbit.z.and p2, p3 = r4, 2
+	tbit.z.or p2, p3 = r4, 3
+	tbit.z.or.andcm p2, p3 = r4, 4
+	tbit.z.orcm p2, p3 = r4, 5
+	tbit.z.andcm p2, p3 = r4, 6
+	tbit.z.and.orcm p2, p3 = r4, 7
+	tbit.nz p2, p3 = r4, 8
+	tbit.nz.unc p2, p3 = r4, 9
+	tbit.nz.and p2, p3 = r4, 10
+	tbit.nz.or p2, p3 = r4, 11
+	tbit.nz.or.andcm p2, p3 = r4, 12
+	tbit.nz.orcm p2, p3 = r4, 13
+	tbit.nz.andcm p2, p3 = r4, 14
+	tbit.nz.and.orcm p2, p3 = r4, 15
+
+	tnat.z p2, p3 = r4
+	tnat.z.unc p2, p3 = r4
+	tnat.z.and p2, p3 = r4
+	tnat.z.or p2, p3 = r4
+	tnat.z.or.andcm p2, p3 = r4
+	tnat.z.orcm p2, p3 = r4
+	tnat.z.andcm p2, p3 = r4
+	tnat.z.and.orcm p2, p3 = r4
+	tnat.nz p2, p3 = r4
+	tnat.nz.unc p2, p3 = r4
+	tnat.nz.and p2, p3 = r4
+	tnat.nz.or p2, p3 = r4
+	tnat.nz.or.andcm p2, p3 = r4
+	tnat.nz.orcm p2, p3 = r4
+	tnat.nz.andcm p2, p3 = r4
+	tnat.nz.and.orcm p2, p3 = r4
+
+	mov.few.dc.dc b3 = r4, .L1
+	mov.few.dc.dc.imp b3 = r4, .L1
+	mov.few.dc.nt b3 = r4, .L1
+	mov.few.dc.nt.imp b3 = r4, .L1
+	mov.few.tk.dc b3 = r4, .L1
+	mov.few.tk.dc.imp b3 = r4, .L1
+	mov.few.tk.tk b3 = r4, .L1
+	mov.few.tk.tk.imp b3 = r4, .L1
+	mov.few.tk.nt b3 = r4, .L1
+	mov.few.tk.nt.imp b3 = r4, .L1
+	mov.few.nt.dc b3 = r4, .L1
+	mov.few.nt.dc.imp b3 = r4, .L1
+	mov.few.nt.tk b3 = r4, .L1
+	mov.few.nt.tk.imp b3 = r4, .L1
+	mov.few.nt.nt b3 = r4, .L1
+	mov.few.nt.nt.imp b3 = r4, .L1
+.L1:
+	mov.many.dc.dc b3 = r4, .L2
+	mov.many.dc.dc.imp b3 = r4, .L2
+	mov.many.dc.nt b3 = r4, .L2
+	mov.many.dc.nt.imp b3 = r4, .L2
+	mov.many.tk.dc b3 = r4, .L2
+	mov.many.tk.dc.imp b3 = r4, .L2
+	mov.many.tk.tk b3 = r4, .L2
+	mov.many.tk.tk.imp b3 = r4, .L2
+	mov.many.tk.nt b3 = r4, .L2
+	mov.many.tk.nt.imp b3 = r4, .L2
+	mov.many.nt.dc b3 = r4, .L2
+	mov.many.nt.dc.imp b3 = r4, .L2
+	mov.many.nt.tk b3 = r4, .L2
+	mov.many.nt.tk.imp b3 = r4, .L2
+	mov.many.nt.nt b3 = r4, .L2
+	mov.many.nt.nt.imp b3 = r4, .L2
+.L2:
+	mov.sptk.few.dc.dc b3 = r4, .L3
+	mov.sptk.few.dc.dc.imp b3 = r4, .L3
+	mov.sptk.few.dc.nt b3 = r4, .L3
+	mov.sptk.few.dc.nt.imp b3 = r4, .L3
+	mov.sptk.few.tk.dc b3 = r4, .L3
+	mov.sptk.few.tk.dc.imp b3 = r4, .L3
+	mov.sptk.few.tk.tk b3 = r4, .L3
+	mov.sptk.few.tk.tk.imp b3 = r4, .L3
+	mov.sptk.few.tk.nt b3 = r4, .L3
+	mov.sptk.few.tk.nt.imp b3 = r4, .L3
+	mov.sptk.few.nt.dc b3 = r4, .L3
+	mov.sptk.few.nt.dc.imp b3 = r4, .L3
+	mov.sptk.few.nt.tk b3 = r4, .L3
+	mov.sptk.few.nt.tk.imp b3 = r4, .L3
+	mov.sptk.few.nt.nt b3 = r4, .L3
+	mov.sptk.few.nt.nt.imp b3 = r4, .L3
+.L3:
+	mov.sptk.many.dc.dc b3 = r4, .L4
+	mov.sptk.many.dc.dc.imp b3 = r4, .L4
+	mov.sptk.many.dc.nt b3 = r4, .L4
+	mov.sptk.many.dc.nt.imp b3 = r4, .L4
+	mov.sptk.many.tk.dc b3 = r4, .L4
+	mov.sptk.many.tk.dc.imp b3 = r4, .L4
+	mov.sptk.many.tk.tk b3 = r4, .L4
+	mov.sptk.many.tk.tk.imp b3 = r4, .L4
+	mov.sptk.many.tk.nt b3 = r4, .L4
+	mov.sptk.many.tk.nt.imp b3 = r4, .L4
+	mov.sptk.many.nt.dc b3 = r4, .L4
+	mov.sptk.many.nt.dc.imp b3 = r4, .L4
+	mov.sptk.many.nt.tk b3 = r4, .L4
+	mov.sptk.many.nt.tk.imp b3 = r4, .L4
+	mov.sptk.many.nt.nt b3 = r4, .L4
+	mov.sptk.many.nt.nt.imp b3 = r4, .L4
+.L4:
+	mov.dptk.few.dc.dc b3 = r4, .L5
+	mov.dptk.few.dc.dc.imp b3 = r4, .L5
+	mov.dptk.few.dc.nt b3 = r4, .L5
+	mov.dptk.few.dc.nt.imp b3 = r4, .L5
+	mov.dptk.few.tk.dc b3 = r4, .L5
+	mov.dptk.few.tk.dc.imp b3 = r4, .L5
+	mov.dptk.few.tk.tk b3 = r4, .L5
+	mov.dptk.few.tk.tk.imp b3 = r4, .L5
+	mov.dptk.few.tk.nt b3 = r4, .L5
+	mov.dptk.few.tk.nt.imp b3 = r4, .L5
+	mov.dptk.few.nt.dc b3 = r4, .L5
+	mov.dptk.few.nt.dc.imp b3 = r4, .L5
+	mov.dptk.few.nt.tk b3 = r4, .L5
+	mov.dptk.few.nt.tk.imp b3 = r4, .L5
+	mov.dptk.few.nt.nt b3 = r4, .L5
+	mov.dptk.few.nt.nt.imp b3 = r4, .L5
+.L5:
+	mov.dptk.many.dc.dc b3 = r4, .L6
+	mov.dptk.many.dc.dc.imp b3 = r4, .L6
+	mov.dptk.many.dc.nt b3 = r4, .L6
+	mov.dptk.many.dc.nt.imp b3 = r4, .L6
+	mov.dptk.many.tk.dc b3 = r4, .L6
+	mov.dptk.many.tk.dc.imp b3 = r4, .L6
+	mov.dptk.many.tk.tk b3 = r4, .L6
+	mov.dptk.many.tk.tk.imp b3 = r4, .L6
+	mov.dptk.many.tk.nt b3 = r4, .L6
+	mov.dptk.many.tk.nt.imp b3 = r4, .L6
+	mov.dptk.many.nt.dc b3 = r4, .L6
+	mov.dptk.many.nt.dc.imp b3 = r4, .L6
+	mov.dptk.many.nt.tk b3 = r4, .L6
+	mov.dptk.many.nt.tk.imp b3 = r4, .L6
+	mov.dptk.many.nt.nt b3 = r4, .L6
+	mov.dptk.many.nt.nt.imp b3 = r4, .L6
+.L6:
+
+	mov.ret.few.dc.dc b3 = r4, .L7
+	mov.ret.few.dc.dc.imp b3 = r4, .L7
+	mov.ret.few.dc.nt b3 = r4, .L7
+	mov.ret.few.dc.nt.imp b3 = r4, .L7
+	mov.ret.few.tk.dc b3 = r4, .L7
+	mov.ret.few.tk.dc.imp b3 = r4, .L7
+	mov.ret.few.tk.tk b3 = r4, .L7
+	mov.ret.few.tk.tk.imp b3 = r4, .L7
+	mov.ret.few.tk.nt b3 = r4, .L7
+	mov.ret.few.tk.nt.imp b3 = r4, .L7
+	mov.ret.few.nt.dc b3 = r4, .L7
+	mov.ret.few.nt.dc.imp b3 = r4, .L7
+	mov.ret.few.nt.tk b3 = r4, .L7
+	mov.ret.few.nt.tk.imp b3 = r4, .L7
+	mov.ret.few.nt.nt b3 = r4, .L7
+	mov.ret.few.nt.nt.imp b3 = r4, .L7
+.L7:
+	mov.ret.many.dc.dc b3 = r4, .L8
+	mov.ret.many.dc.dc.imp b3 = r4, .L8
+	mov.ret.many.dc.nt b3 = r4, .L8
+	mov.ret.many.dc.nt.imp b3 = r4, .L8
+	mov.ret.many.tk.dc b3 = r4, .L8
+	mov.ret.many.tk.dc.imp b3 = r4, .L8
+	mov.ret.many.tk.tk b3 = r4, .L8
+	mov.ret.many.tk.tk.imp b3 = r4, .L8
+	mov.ret.many.tk.nt b3 = r4, .L8
+	mov.ret.many.tk.nt.imp b3 = r4, .L8
+	mov.ret.many.nt.dc b3 = r4, .L8
+	mov.ret.many.nt.dc.imp b3 = r4, .L8
+	mov.ret.many.nt.tk b3 = r4, .L8
+	mov.ret.many.nt.tk.imp b3 = r4, .L8
+	mov.ret.many.nt.nt b3 = r4, .L8
+	mov.ret.many.nt.nt.imp b3 = r4, .L8
+.L8:
+	mov.ret.sptk.few.dc.dc b3 = r4, .L9
+	mov.ret.sptk.few.dc.dc.imp b3 = r4, .L9
+	mov.ret.sptk.few.dc.nt b3 = r4, .L9
+	mov.ret.sptk.few.dc.nt.imp b3 = r4, .L9
+	mov.ret.sptk.few.tk.dc b3 = r4, .L9
+	mov.ret.sptk.few.tk.dc.imp b3 = r4, .L9
+	mov.ret.sptk.few.tk.tk b3 = r4, .L9
+	mov.ret.sptk.few.tk.tk.imp b3 = r4, .L9
+	mov.ret.sptk.few.tk.nt b3 = r4, .L9
+	mov.ret.sptk.few.tk.nt.imp b3 = r4, .L9
+	mov.ret.sptk.few.nt.dc b3 = r4, .L9
+	mov.ret.sptk.few.nt.dc.imp b3 = r4, .L9
+	mov.ret.sptk.few.nt.tk b3 = r4, .L9
+	mov.ret.sptk.few.nt.tk.imp b3 = r4, .L9
+	mov.ret.sptk.few.nt.nt b3 = r4, .L9
+	mov.ret.sptk.few.nt.nt.imp b3 = r4, .L9
+.L9:
+	mov.ret.sptk.many.dc.dc b3 = r4, .L10
+	mov.ret.sptk.many.dc.dc.imp b3 = r4, .L10
+	mov.ret.sptk.many.dc.nt b3 = r4, .L10
+	mov.ret.sptk.many.dc.nt.imp b3 = r4, .L10
+	mov.ret.sptk.many.tk.dc b3 = r4, .L10
+	mov.ret.sptk.many.tk.dc.imp b3 = r4, .L10
+	mov.ret.sptk.many.tk.tk b3 = r4, .L10
+	mov.ret.sptk.many.tk.tk.imp b3 = r4, .L10
+	mov.ret.sptk.many.tk.nt b3 = r4, .L10
+	mov.ret.sptk.many.tk.nt.imp b3 = r4, .L10
+	mov.ret.sptk.many.nt.dc b3 = r4, .L10
+	mov.ret.sptk.many.nt.dc.imp b3 = r4, .L10
+	mov.ret.sptk.many.nt.tk b3 = r4, .L10
+	mov.ret.sptk.many.nt.tk.imp b3 = r4, .L10
+	mov.ret.sptk.many.nt.nt b3 = r4, .L10
+	mov.ret.sptk.many.nt.nt.imp b3 = r4, .L10
+.L10:
+	mov.ret.dptk.few.dc.dc b3 = r4, .L11
+	mov.ret.dptk.few.dc.dc.imp b3 = r4, .L11
+	mov.ret.dptk.few.dc.nt b3 = r4, .L11
+	mov.ret.dptk.few.dc.nt.imp b3 = r4, .L11
+	mov.ret.dptk.few.tk.dc b3 = r4, .L11
+	mov.ret.dptk.few.tk.dc.imp b3 = r4, .L11
+	mov.ret.dptk.few.tk.tk b3 = r4, .L11
+	mov.ret.dptk.few.tk.tk.imp b3 = r4, .L11
+	mov.ret.dptk.few.tk.nt b3 = r4, .L11
+	mov.ret.dptk.few.tk.nt.imp b3 = r4, .L11
+	mov.ret.dptk.few.nt.dc b3 = r4, .L11
+	mov.ret.dptk.few.nt.dc.imp b3 = r4, .L11
+	mov.ret.dptk.few.nt.tk b3 = r4, .L11
+	mov.ret.dptk.few.nt.tk.imp b3 = r4, .L11
+	mov.ret.dptk.few.nt.nt b3 = r4, .L11
+	mov.ret.dptk.few.nt.nt.imp b3 = r4, .L11
+.L11:
+	mov.ret.dptk.many.dc.dc b3 = r4, .L12
+	mov.ret.dptk.many.dc.dc.imp b3 = r4, .L12
+	mov.ret.dptk.many.dc.nt b3 = r4, .L12
+	mov.ret.dptk.many.dc.nt.imp b3 = r4, .L12
+	mov.ret.dptk.many.tk.dc b3 = r4, .L12
+	mov.ret.dptk.many.tk.dc.imp b3 = r4, .L12
+	mov.ret.dptk.many.tk.tk b3 = r4, .L12
+	mov.ret.dptk.many.tk.tk.imp b3 = r4, .L12
+	mov.ret.dptk.many.tk.nt b3 = r4, .L12
+	mov.ret.dptk.many.tk.nt.imp b3 = r4, .L12
+	mov.ret.dptk.many.nt.dc b3 = r4, .L12
+	mov.ret.dptk.many.nt.dc.imp b3 = r4, .L12
+	mov.ret.dptk.many.nt.tk b3 = r4, .L12
+	mov.ret.dptk.many.nt.tk.imp b3 = r4, .L12
+	mov.ret.dptk.many.nt.nt b3 = r4, .L12
+	mov.ret.dptk.many.nt.nt.imp b3 = r4, .L12
+.L12:
+
diff --git a/gas/testsuite/gas/ia64/opc-m.d b/gas/testsuite/gas/ia64/opc-m.d
new file mode 100644
index 0000000..f38bab1
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-m.d
@@ -0,0 +1,1328 @@
+# objdump: -d
+# name: ia64 opc-m
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <_start>:
+       0:	08 20 00 0a 00 10 	\[MMI\]       ld1 r4=\[r5\]
+       6:	40 30 14 00 24 00 	            ld1 r4=\[r5\],r6
+       c:	00 00 04 00       	            nop\.i 0x0
+      10:	08 20 00 0a 00 16 	\[MMI\]       ld1 r4=\[r5\],-256
+      16:	40 00 14 04 20 00 	            ld1\.nt1 r4=\[r5\]
+      1c:	00 00 04 00       	            nop\.i 0x0
+      20:	08 20 18 0a 02 12 	\[MMI\]       ld1\.nt1 r4=\[r5\],r6
+      26:	40 68 14 04 2c 00 	            ld1\.nt1 r4=\[r5\],-243
+      2c:	00 00 04 00       	            nop\.i 0x0
+      30:	08 20 00 0a 06 10 	\[MMI\]       ld1\.nta r4=\[r5\]
+      36:	40 30 14 0c 24 00 	            ld1\.nta r4=\[r5\],r6
+      3c:	00 00 04 00       	            nop\.i 0x0
+      40:	08 20 68 0a 06 16 	\[MMI\]       ld1\.nta r4=\[r5\],-230
+      46:	40 00 14 40 20 00 	            ld1\.s r4=\[r5\]
+      4c:	00 00 04 00       	            nop\.i 0x0
+      50:	08 20 18 0a 20 12 	\[MMI\]       ld1\.s r4=\[r5\],r6
+      56:	40 38 15 40 2c 00 	            ld1\.s r4=\[r5\],-217
+      5c:	00 00 04 00       	            nop\.i 0x0
+      60:	08 20 00 0a 22 10 	\[MMI\]       ld1\.s\.nt1 r4=\[r5\]
+      66:	40 30 14 44 24 00 	            ld1\.s\.nt1 r4=\[r5\],r6
+      6c:	00 00 04 00       	            nop\.i 0x0
+      70:	08 20 d0 0a 22 16 	\[MMI\]       ld1\.s\.nt1 r4=\[r5\],-204
+      76:	40 00 14 4c 20 00 	            ld1\.s\.nta r4=\[r5\]
+      7c:	00 00 04 00       	            nop\.i 0x0
+      80:	08 20 18 0a 26 12 	\[MMI\]       ld1\.s\.nta r4=\[r5\],r6
+      86:	40 08 16 4c 2c 00 	            ld1\.s\.nta r4=\[r5\],-191
+      8c:	00 00 04 00       	            nop\.i 0x0
+      90:	08 20 00 0a 40 10 	\[MMI\]       ld1\.a r4=\[r5\]
+      96:	40 30 14 80 24 00 	            ld1\.a r4=\[r5\],r6
+      9c:	00 00 04 00       	            nop\.i 0x0
+      a0:	08 20 38 0b 40 16 	\[MMI\]       ld1\.a r4=\[r5\],-178
+      a6:	40 00 14 84 20 00 	            ld1\.a\.nt1 r4=\[r5\]
+      ac:	00 00 04 00       	            nop\.i 0x0
+      b0:	08 20 18 0a 42 12 	\[MMI\]       ld1\.a\.nt1 r4=\[r5\],r6
+      b6:	40 d8 16 84 2c 00 	            ld1\.a\.nt1 r4=\[r5\],-165
+      bc:	00 00 04 00       	            nop\.i 0x0
+      c0:	08 20 00 0a 46 10 	\[MMI\]       ld1\.a\.nta r4=\[r5\]
+      c6:	40 30 14 8c 24 00 	            ld1\.a\.nta r4=\[r5\],r6
+      cc:	00 00 04 00       	            nop\.i 0x0
+      d0:	08 20 a0 0b 46 16 	\[MMI\]       ld1\.a\.nta r4=\[r5\],-152
+      d6:	40 00 14 c0 20 00 	            ld1\.sa r4=\[r5\]
+      dc:	00 00 04 00       	            nop\.i 0x0
+      e0:	08 20 18 0a 60 12 	\[MMI\]       ld1\.sa r4=\[r5\],r6
+      e6:	40 a8 17 c0 2c 00 	            ld1\.sa r4=\[r5\],-139
+      ec:	00 00 04 00       	            nop\.i 0x0
+      f0:	08 20 00 0a 62 10 	\[MMI\]       ld1\.sa\.nt1 r4=\[r5\]
+      f6:	40 30 14 c4 24 00 	            ld1\.sa\.nt1 r4=\[r5\],r6
+      fc:	00 00 04 00       	            nop\.i 0x0
+     100:	08 20 08 0a 63 16 	\[MMI\]       ld1\.sa\.nt1 r4=\[r5\],-126
+     106:	40 00 14 cc 20 00 	            ld1\.sa\.nta r4=\[r5\]
+     10c:	00 00 04 00       	            nop\.i 0x0
+     110:	08 20 18 0a 66 12 	\[MMI\]       ld1\.sa\.nta r4=\[r5\],r6
+     116:	40 78 14 ce 2c 00 	            ld1\.sa\.nta r4=\[r5\],-113
+     11c:	00 00 04 00       	            nop\.i 0x0
+     120:	08 20 00 0a 00 11 	\[MMI\]       ld1\.c\.clr r4=\[r5\]
+     126:	40 30 14 00 26 00 	            ld1\.c\.clr r4=\[r5\],r6
+     12c:	00 00 04 00       	            nop\.i 0x0
+     130:	08 20 70 0a 01 17 	\[MMI\]       ld1\.c\.clr r4=\[r5\],-100
+     136:	40 00 14 04 22 00 	            ld1\.c\.clr\.nt1 r4=\[r5\]
+     13c:	00 00 04 00       	            nop\.i 0x0
+     140:	08 20 18 0a 02 13 	\[MMI\]       ld1\.c\.clr\.nt1 r4=\[r5\],r6
+     146:	40 48 15 06 2e 00 	            ld1\.c\.clr\.nt1 r4=\[r5\],-87
+     14c:	00 00 04 00       	            nop\.i 0x0
+     150:	08 20 00 0a 06 11 	\[MMI\]       ld1\.c\.clr\.nta r4=\[r5\]
+     156:	40 30 14 0c 26 00 	            ld1\.c\.clr\.nta r4=\[r5\],r6
+     15c:	00 00 04 00       	            nop\.i 0x0
+     160:	08 20 d8 0a 07 17 	\[MMI\]       ld1\.c\.clr\.nta r4=\[r5\],-74
+     166:	40 00 14 40 22 00 	            ld1\.c\.nc r4=\[r5\]
+     16c:	00 00 04 00       	            nop\.i 0x0
+     170:	08 20 18 0a 20 13 	\[MMI\]       ld1\.c\.nc r4=\[r5\],r6
+     176:	40 18 16 42 2e 00 	            ld1\.c\.nc r4=\[r5\],-61
+     17c:	00 00 04 00       	            nop\.i 0x0
+     180:	08 20 00 0a 22 11 	\[MMI\]       ld1\.c\.nc\.nt1 r4=\[r5\]
+     186:	40 30 14 44 26 00 	            ld1\.c\.nc\.nt1 r4=\[r5\],r6
+     18c:	00 00 04 00       	            nop\.i 0x0
+     190:	08 20 40 0b 23 17 	\[MMI\]       ld1\.c\.nc\.nt1 r4=\[r5\],-48
+     196:	40 00 14 4c 22 00 	            ld1\.c\.nc\.nta r4=\[r5\]
+     19c:	00 00 04 00       	            nop\.i 0x0
+     1a0:	08 20 18 0a 26 13 	\[MMI\]       ld1\.c\.nc\.nta r4=\[r5\],r6
+     1a6:	40 e8 16 4e 2e 00 	            ld1\.c\.nc\.nta r4=\[r5\],-35
+     1ac:	00 00 04 00       	            nop\.i 0x0
+     1b0:	08 20 00 0a 80 10 	\[MMI\]       ld1\.bias r4=\[r5\]
+     1b6:	40 30 14 00 25 00 	            ld1\.bias r4=\[r5\],r6
+     1bc:	00 00 04 00       	            nop\.i 0x0
+     1c0:	08 20 a8 0b 81 16 	\[MMI\]       ld1\.bias r4=\[r5\],-22
+     1c6:	40 00 14 04 21 00 	            ld1\.bias\.nt1 r4=\[r5\]
+     1cc:	00 00 04 00       	            nop\.i 0x0
+     1d0:	08 20 18 0a 82 12 	\[MMI\]       ld1\.bias\.nt1 r4=\[r5\],r6
+     1d6:	40 b8 17 06 2d 00 	            ld1\.bias\.nt1 r4=\[r5\],-9
+     1dc:	00 00 04 00       	            nop\.i 0x0
+     1e0:	08 20 00 0a 86 10 	\[MMI\]       ld1\.bias\.nta r4=\[r5\]
+     1e6:	40 30 14 0c 25 00 	            ld1\.bias\.nta r4=\[r5\],r6
+     1ec:	00 00 04 00       	            nop\.i 0x0
+     1f0:	08 20 10 0a 86 14 	\[MMI\]       ld1\.bias\.nta r4=\[r5\],4
+     1f6:	40 00 14 40 21 00 	            ld1\.acq r4=\[r5\]
+     1fc:	00 00 04 00       	            nop\.i 0x0
+     200:	08 20 18 0a a0 12 	\[MMI\]       ld1\.acq r4=\[r5\],r6
+     206:	40 88 14 40 29 00 	            ld1\.acq r4=\[r5\],17
+     20c:	00 00 04 00       	            nop\.i 0x0
+     210:	08 20 00 0a a2 10 	\[MMI\]       ld1\.acq\.nt1 r4=\[r5\]
+     216:	40 30 14 44 25 00 	            ld1\.acq\.nt1 r4=\[r5\],r6
+     21c:	00 00 04 00       	            nop\.i 0x0
+     220:	08 20 78 0a a2 14 	\[MMI\]       ld1\.acq\.nt1 r4=\[r5\],30
+     226:	40 00 14 4c 21 00 	            ld1\.acq\.nta r4=\[r5\]
+     22c:	00 00 04 00       	            nop\.i 0x0
+     230:	08 20 18 0a a6 12 	\[MMI\]       ld1\.acq\.nta r4=\[r5\],r6
+     236:	40 58 15 4c 29 00 	            ld1\.acq\.nta r4=\[r5\],43
+     23c:	00 00 04 00       	            nop\.i 0x0
+     240:	08 20 00 0a 40 11 	\[MMI\]       ld1\.c\.clr\.acq r4=\[r5\]
+     246:	40 30 14 80 26 00 	            ld1\.c\.clr\.acq r4=\[r5\],r6
+     24c:	00 00 04 00       	            nop\.i 0x0
+     250:	08 20 e0 0a 40 15 	\[MMI\]       ld1\.c\.clr\.acq r4=\[r5\],56
+     256:	40 00 14 84 22 00 	            ld1\.c\.clr\.acq\.nt1 r4=\[r5\]
+     25c:	00 00 04 00       	            nop\.i 0x0
+     260:	08 20 18 0a 42 13 	\[MMI\]       ld1\.c\.clr\.acq\.nt1 r4=\[r5\],r6
+     266:	40 28 16 84 2a 00 	            ld1\.c\.clr\.acq\.nt1 r4=\[r5\],69
+     26c:	00 00 04 00       	            nop\.i 0x0
+     270:	08 20 00 0a 46 11 	\[MMI\]       ld1\.c\.clr\.acq\.nta r4=\[r5\]
+     276:	40 30 14 8c 26 00 	            ld1\.c\.clr\.acq\.nta r4=\[r5\],r6
+     27c:	00 00 04 00       	            nop\.i 0x0
+     280:	08 20 48 0b 46 15 	\[MMI\]       ld1\.c\.clr\.acq\.nta r4=\[r5\],82
+     286:	40 00 14 10 20 00 	            ld2 r4=\[r5\]
+     28c:	00 00 04 00       	            nop\.i 0x0
+     290:	08 20 18 0a 08 12 	\[MMI\]       ld2 r4=\[r5\],r6
+     296:	40 f8 16 10 28 00 	            ld2 r4=\[r5\],95
+     29c:	00 00 04 00       	            nop\.i 0x0
+     2a0:	08 20 00 0a 0a 10 	\[MMI\]       ld2\.nt1 r4=\[r5\]
+     2a6:	40 30 14 14 24 00 	            ld2\.nt1 r4=\[r5\],r6
+     2ac:	00 00 04 00       	            nop\.i 0x0
+     2b0:	08 20 b0 0b 0a 14 	\[MMI\]       ld2\.nt1 r4=\[r5\],108
+     2b6:	40 00 14 1c 20 00 	            ld2\.nta r4=\[r5\]
+     2bc:	00 00 04 00       	            nop\.i 0x0
+     2c0:	08 20 18 0a 0e 12 	\[MMI\]       ld2\.nta r4=\[r5\],r6
+     2c6:	40 c8 17 1c 28 00 	            ld2\.nta r4=\[r5\],121
+     2cc:	00 00 04 00       	            nop\.i 0x0
+     2d0:	08 20 00 0a 28 10 	\[MMI\]       ld2\.s r4=\[r5\]
+     2d6:	40 30 14 50 24 00 	            ld2\.s r4=\[r5\],r6
+     2dc:	00 00 04 00       	            nop\.i 0x0
+     2e0:	08 20 18 0a 29 14 	\[MMI\]       ld2\.s r4=\[r5\],134
+     2e6:	40 00 14 54 20 00 	            ld2\.s\.nt1 r4=\[r5\]
+     2ec:	00 00 04 00       	            nop\.i 0x0
+     2f0:	08 20 18 0a 2a 12 	\[MMI\]       ld2\.s\.nt1 r4=\[r5\],r6
+     2f6:	40 98 14 56 28 00 	            ld2\.s\.nt1 r4=\[r5\],147
+     2fc:	00 00 04 00       	            nop\.i 0x0
+     300:	08 20 00 0a 2e 10 	\[MMI\]       ld2\.s\.nta r4=\[r5\]
+     306:	40 30 14 5c 24 00 	            ld2\.s\.nta r4=\[r5\],r6
+     30c:	00 00 04 00       	            nop\.i 0x0
+     310:	08 20 80 0a 2f 14 	\[MMI\]       ld2\.s\.nta r4=\[r5\],160
+     316:	40 00 14 90 20 00 	            ld2\.a r4=\[r5\]
+     31c:	00 00 04 00       	            nop\.i 0x0
+     320:	08 20 18 0a 48 12 	\[MMI\]       ld2\.a r4=\[r5\],r6
+     326:	40 68 15 92 28 00 	            ld2\.a r4=\[r5\],173
+     32c:	00 00 04 00       	            nop\.i 0x0
+     330:	08 20 00 0a 4a 10 	\[MMI\]       ld2\.a\.nt1 r4=\[r5\]
+     336:	40 30 14 94 24 00 	            ld2\.a\.nt1 r4=\[r5\],r6
+     33c:	00 00 04 00       	            nop\.i 0x0
+     340:	08 20 e8 0a 4b 14 	\[MMI\]       ld2\.a\.nt1 r4=\[r5\],186
+     346:	40 00 14 9c 20 00 	            ld2\.a\.nta r4=\[r5\]
+     34c:	00 00 04 00       	            nop\.i 0x0
+     350:	08 20 18 0a 4e 12 	\[MMI\]       ld2\.a\.nta r4=\[r5\],r6
+     356:	40 38 16 9e 28 00 	            ld2\.a\.nta r4=\[r5\],199
+     35c:	00 00 04 00       	            nop\.i 0x0
+     360:	08 20 00 0a 68 10 	\[MMI\]       ld2\.sa r4=\[r5\]
+     366:	40 30 14 d0 24 00 	            ld2\.sa r4=\[r5\],r6
+     36c:	00 00 04 00       	            nop\.i 0x0
+     370:	08 20 50 0b 69 14 	\[MMI\]       ld2\.sa r4=\[r5\],212
+     376:	40 00 14 d4 20 00 	            ld2\.sa\.nt1 r4=\[r5\]
+     37c:	00 00 04 00       	            nop\.i 0x0
+     380:	08 20 18 0a 6a 12 	\[MMI\]       ld2\.sa\.nt1 r4=\[r5\],r6
+     386:	40 08 17 d6 28 00 	            ld2\.sa\.nt1 r4=\[r5\],225
+     38c:	00 00 04 00       	            nop\.i 0x0
+     390:	08 20 00 0a 6e 10 	\[MMI\]       ld2\.sa\.nta r4=\[r5\]
+     396:	40 30 14 dc 24 00 	            ld2\.sa\.nta r4=\[r5\],r6
+     39c:	00 00 04 00       	            nop\.i 0x0
+     3a0:	08 20 b8 0b 6f 14 	\[MMI\]       ld2\.sa\.nta r4=\[r5\],238
+     3a6:	40 00 14 10 22 00 	            ld2\.c\.clr r4=\[r5\]
+     3ac:	00 00 04 00       	            nop\.i 0x0
+     3b0:	08 20 18 0a 08 13 	\[MMI\]       ld2\.c\.clr r4=\[r5\],r6
+     3b6:	40 d8 17 12 2a 00 	            ld2\.c\.clr r4=\[r5\],251
+     3bc:	00 00 04 00       	            nop\.i 0x0
+     3c0:	08 20 00 0a 0a 11 	\[MMI\]       ld2\.c\.clr\.nt1 r4=\[r5\]
+     3c6:	40 30 14 14 26 00 	            ld2\.c\.clr\.nt1 r4=\[r5\],r6
+     3cc:	00 00 04 00       	            nop\.i 0x0
+     3d0:	08 20 20 0a 0a 17 	\[MMI\]       ld2\.c\.clr\.nt1 r4=\[r5\],-248
+     3d6:	40 00 14 1c 22 00 	            ld2\.c\.clr\.nta r4=\[r5\]
+     3dc:	00 00 04 00       	            nop\.i 0x0
+     3e0:	08 20 18 0a 0e 13 	\[MMI\]       ld2\.c\.clr\.nta r4=\[r5\],r6
+     3e6:	40 a8 14 1c 2e 00 	            ld2\.c\.clr\.nta r4=\[r5\],-235
+     3ec:	00 00 04 00       	            nop\.i 0x0
+     3f0:	08 20 00 0a 28 11 	\[MMI\]       ld2\.c\.nc r4=\[r5\]
+     3f6:	40 30 14 50 26 00 	            ld2\.c\.nc r4=\[r5\],r6
+     3fc:	00 00 04 00       	            nop\.i 0x0
+     400:	08 20 88 0a 28 17 	\[MMI\]       ld2\.c\.nc r4=\[r5\],-222
+     406:	40 00 14 54 22 00 	            ld2\.c\.nc\.nt1 r4=\[r5\]
+     40c:	00 00 04 00       	            nop\.i 0x0
+     410:	08 20 18 0a 2a 13 	\[MMI\]       ld2\.c\.nc\.nt1 r4=\[r5\],r6
+     416:	40 78 15 54 2e 00 	            ld2\.c\.nc\.nt1 r4=\[r5\],-209
+     41c:	00 00 04 00       	            nop\.i 0x0
+     420:	08 20 00 0a 2e 11 	\[MMI\]       ld2\.c\.nc\.nta r4=\[r5\]
+     426:	40 30 14 5c 26 00 	            ld2\.c\.nc\.nta r4=\[r5\],r6
+     42c:	00 00 04 00       	            nop\.i 0x0
+     430:	08 20 f0 0a 2e 17 	\[MMI\]       ld2\.c\.nc\.nta r4=\[r5\],-196
+     436:	40 00 14 10 21 00 	            ld2\.bias r4=\[r5\]
+     43c:	00 00 04 00       	            nop\.i 0x0
+     440:	08 20 18 0a 88 12 	\[MMI\]       ld2\.bias r4=\[r5\],r6
+     446:	40 48 16 10 2d 00 	            ld2\.bias r4=\[r5\],-183
+     44c:	00 00 04 00       	            nop\.i 0x0
+     450:	08 20 00 0a 8a 10 	\[MMI\]       ld2\.bias\.nt1 r4=\[r5\]
+     456:	40 30 14 14 25 00 	            ld2\.bias\.nt1 r4=\[r5\],r6
+     45c:	00 00 04 00       	            nop\.i 0x0
+     460:	08 20 58 0b 8a 16 	\[MMI\]       ld2\.bias\.nt1 r4=\[r5\],-170
+     466:	40 00 14 1c 21 00 	            ld2\.bias\.nta r4=\[r5\]
+     46c:	00 00 04 00       	            nop\.i 0x0
+     470:	08 20 18 0a 8e 12 	\[MMI\]       ld2\.bias\.nta r4=\[r5\],r6
+     476:	40 18 17 1c 2d 00 	            ld2\.bias\.nta r4=\[r5\],-157
+     47c:	00 00 04 00       	            nop\.i 0x0
+     480:	08 20 00 0a a8 10 	\[MMI\]       ld2\.acq r4=\[r5\]
+     486:	40 30 14 50 25 00 	            ld2\.acq r4=\[r5\],r6
+     48c:	00 00 04 00       	            nop\.i 0x0
+     490:	08 20 c0 0b a8 16 	\[MMI\]       ld2\.acq r4=\[r5\],-144
+     496:	40 00 14 54 21 00 	            ld2\.acq\.nt1 r4=\[r5\]
+     49c:	00 00 04 00       	            nop\.i 0x0
+     4a0:	08 20 18 0a aa 12 	\[MMI\]       ld2\.acq\.nt1 r4=\[r5\],r6
+     4a6:	40 e8 17 54 2d 00 	            ld2\.acq\.nt1 r4=\[r5\],-131
+     4ac:	00 00 04 00       	            nop\.i 0x0
+     4b0:	08 20 00 0a ae 10 	\[MMI\]       ld2\.acq\.nta r4=\[r5\]
+     4b6:	40 30 14 5c 25 00 	            ld2\.acq\.nta r4=\[r5\],r6
+     4bc:	00 00 04 00       	            nop\.i 0x0
+     4c0:	08 20 28 0a af 16 	\[MMI\]       ld2\.acq\.nta r4=\[r5\],-118
+     4c6:	40 00 14 90 22 00 	            ld2\.c\.clr\.acq r4=\[r5\]
+     4cc:	00 00 04 00       	            nop\.i 0x0
+     4d0:	08 20 18 0a 48 13 	\[MMI\]       ld2\.c\.clr\.acq r4=\[r5\],r6
+     4d6:	40 b8 14 92 2e 00 	            ld2\.c\.clr\.acq r4=\[r5\],-105
+     4dc:	00 00 04 00       	            nop\.i 0x0
+     4e0:	08 20 00 0a 4a 11 	\[MMI\]       ld2\.c\.clr\.acq\.nt1 r4=\[r5\]
+     4e6:	40 30 14 94 26 00 	            ld2\.c\.clr\.acq\.nt1 r4=\[r5\],r6
+     4ec:	00 00 04 00       	            nop\.i 0x0
+     4f0:	08 20 90 0a 4b 17 	\[MMI\]       ld2\.c\.clr\.acq\.nt1 r4=\[r5\],-92
+     4f6:	40 00 14 9c 22 00 	            ld2\.c\.clr\.acq\.nta r4=\[r5\]
+     4fc:	00 00 04 00       	            nop\.i 0x0
+     500:	08 20 18 0a 4e 13 	\[MMI\]       ld2\.c\.clr\.acq\.nta r4=\[r5\],r6
+     506:	40 88 15 9e 2e 00 	            ld2\.c\.clr\.acq\.nta r4=\[r5\],-79
+     50c:	00 00 04 00       	            nop\.i 0x0
+     510:	08 20 00 0a 10 10 	\[MMI\]       ld4 r4=\[r5\]
+     516:	40 30 14 20 24 00 	            ld4 r4=\[r5\],r6
+     51c:	00 00 04 00       	            nop\.i 0x0
+     520:	08 20 f8 0a 11 16 	\[MMI\]       ld4 r4=\[r5\],-66
+     526:	40 00 14 24 20 00 	            ld4\.nt1 r4=\[r5\]
+     52c:	00 00 04 00       	            nop\.i 0x0
+     530:	08 20 18 0a 12 12 	\[MMI\]       ld4\.nt1 r4=\[r5\],r6
+     536:	40 58 16 26 2c 00 	            ld4\.nt1 r4=\[r5\],-53
+     53c:	00 00 04 00       	            nop\.i 0x0
+     540:	08 20 00 0a 16 10 	\[MMI\]       ld4\.nta r4=\[r5\]
+     546:	40 30 14 2c 24 00 	            ld4\.nta r4=\[r5\],r6
+     54c:	00 00 04 00       	            nop\.i 0x0
+     550:	08 20 60 0b 17 16 	\[MMI\]       ld4\.nta r4=\[r5\],-40
+     556:	40 00 14 60 20 00 	            ld4\.s r4=\[r5\]
+     55c:	00 00 04 00       	            nop\.i 0x0
+     560:	08 20 18 0a 30 12 	\[MMI\]       ld4\.s r4=\[r5\],r6
+     566:	40 28 17 62 2c 00 	            ld4\.s r4=\[r5\],-27
+     56c:	00 00 04 00       	            nop\.i 0x0
+     570:	08 20 00 0a 32 10 	\[MMI\]       ld4\.s\.nt1 r4=\[r5\]
+     576:	40 30 14 64 24 00 	            ld4\.s\.nt1 r4=\[r5\],r6
+     57c:	00 00 04 00       	            nop\.i 0x0
+     580:	08 20 c8 0b 33 16 	\[MMI\]       ld4\.s\.nt1 r4=\[r5\],-14
+     586:	40 00 14 6c 20 00 	            ld4\.s\.nta r4=\[r5\]
+     58c:	00 00 04 00       	            nop\.i 0x0
+     590:	08 20 18 0a 36 12 	\[MMI\]       ld4\.s\.nta r4=\[r5\],r6
+     596:	40 f8 17 6e 2c 00 	            ld4\.s\.nta r4=\[r5\],-1
+     59c:	00 00 04 00       	            nop\.i 0x0
+     5a0:	08 20 00 0a 50 10 	\[MMI\]       ld4\.a r4=\[r5\]
+     5a6:	40 30 14 a0 24 00 	            ld4\.a r4=\[r5\],r6
+     5ac:	00 00 04 00       	            nop\.i 0x0
+     5b0:	08 20 30 0a 50 14 	\[MMI\]       ld4\.a r4=\[r5\],12
+     5b6:	40 00 14 a4 20 00 	            ld4\.a\.nt1 r4=\[r5\]
+     5bc:	00 00 04 00       	            nop\.i 0x0
+     5c0:	08 20 18 0a 52 12 	\[MMI\]       ld4\.a\.nt1 r4=\[r5\],r6
+     5c6:	40 c8 14 a4 28 00 	            ld4\.a\.nt1 r4=\[r5\],25
+     5cc:	00 00 04 00       	            nop\.i 0x0
+     5d0:	08 20 00 0a 56 10 	\[MMI\]       ld4\.a\.nta r4=\[r5\]
+     5d6:	40 30 14 ac 24 00 	            ld4\.a\.nta r4=\[r5\],r6
+     5dc:	00 00 04 00       	            nop\.i 0x0
+     5e0:	08 20 98 0a 56 14 	\[MMI\]       ld4\.a\.nta r4=\[r5\],38
+     5e6:	40 00 14 e0 20 00 	            ld4\.sa r4=\[r5\]
+     5ec:	00 00 04 00       	            nop\.i 0x0
+     5f0:	08 20 18 0a 70 12 	\[MMI\]       ld4\.sa r4=\[r5\],r6
+     5f6:	40 98 15 e0 28 00 	            ld4\.sa r4=\[r5\],51
+     5fc:	00 00 04 00       	            nop\.i 0x0
+     600:	08 20 00 0a 72 10 	\[MMI\]       ld4\.sa\.nt1 r4=\[r5\]
+     606:	40 30 14 e4 24 00 	            ld4\.sa\.nt1 r4=\[r5\],r6
+     60c:	00 00 04 00       	            nop\.i 0x0
+     610:	08 20 00 0b 72 14 	\[MMI\]       ld4\.sa\.nt1 r4=\[r5\],64
+     616:	40 00 14 ec 20 00 	            ld4\.sa\.nta r4=\[r5\]
+     61c:	00 00 04 00       	            nop\.i 0x0
+     620:	08 20 18 0a 76 12 	\[MMI\]       ld4\.sa\.nta r4=\[r5\],r6
+     626:	40 68 16 ec 28 00 	            ld4\.sa\.nta r4=\[r5\],77
+     62c:	00 00 04 00       	            nop\.i 0x0
+     630:	08 20 00 0a 10 11 	\[MMI\]       ld4\.c\.clr r4=\[r5\]
+     636:	40 30 14 20 26 00 	            ld4\.c\.clr r4=\[r5\],r6
+     63c:	00 00 04 00       	            nop\.i 0x0
+     640:	08 20 68 0b 10 15 	\[MMI\]       ld4\.c\.clr r4=\[r5\],90
+     646:	40 00 14 24 22 00 	            ld4\.c\.clr\.nt1 r4=\[r5\]
+     64c:	00 00 04 00       	            nop\.i 0x0
+     650:	08 20 18 0a 12 13 	\[MMI\]       ld4\.c\.clr\.nt1 r4=\[r5\],r6
+     656:	40 38 17 24 2a 00 	            ld4\.c\.clr\.nt1 r4=\[r5\],103
+     65c:	00 00 04 00       	            nop\.i 0x0
+     660:	08 20 00 0a 16 11 	\[MMI\]       ld4\.c\.clr\.nta r4=\[r5\]
+     666:	40 30 14 2c 26 00 	            ld4\.c\.clr\.nta r4=\[r5\],r6
+     66c:	00 00 04 00       	            nop\.i 0x0
+     670:	08 20 d0 0b 16 15 	\[MMI\]       ld4\.c\.clr\.nta r4=\[r5\],116
+     676:	40 00 14 60 22 00 	            ld4\.c\.nc r4=\[r5\]
+     67c:	00 00 04 00       	            nop\.i 0x0
+     680:	08 20 18 0a 30 13 	\[MMI\]       ld4\.c\.nc r4=\[r5\],r6
+     686:	40 08 14 62 2a 00 	            ld4\.c\.nc r4=\[r5\],129
+     68c:	00 00 04 00       	            nop\.i 0x0
+     690:	08 20 00 0a 32 11 	\[MMI\]       ld4\.c\.nc\.nt1 r4=\[r5\]
+     696:	40 30 14 64 26 00 	            ld4\.c\.nc\.nt1 r4=\[r5\],r6
+     69c:	00 00 04 00       	            nop\.i 0x0
+     6a0:	08 20 38 0a 33 15 	\[MMI\]       ld4\.c\.nc\.nt1 r4=\[r5\],142
+     6a6:	40 00 14 6c 22 00 	            ld4\.c\.nc\.nta r4=\[r5\]
+     6ac:	00 00 04 00       	            nop\.i 0x0
+     6b0:	08 20 18 0a 36 13 	\[MMI\]       ld4\.c\.nc\.nta r4=\[r5\],r6
+     6b6:	40 d8 14 6e 2a 00 	            ld4\.c\.nc\.nta r4=\[r5\],155
+     6bc:	00 00 04 00       	            nop\.i 0x0
+     6c0:	08 20 00 0a 90 10 	\[MMI\]       ld4\.bias r4=\[r5\]
+     6c6:	40 30 14 20 25 00 	            ld4\.bias r4=\[r5\],r6
+     6cc:	00 00 04 00       	            nop\.i 0x0
+     6d0:	08 20 a0 0a 91 14 	\[MMI\]       ld4\.bias r4=\[r5\],168
+     6d6:	40 00 14 24 21 00 	            ld4\.bias\.nt1 r4=\[r5\]
+     6dc:	00 00 04 00       	            nop\.i 0x0
+     6e0:	08 20 18 0a 92 12 	\[MMI\]       ld4\.bias\.nt1 r4=\[r5\],r6
+     6e6:	40 a8 15 26 29 00 	            ld4\.bias\.nt1 r4=\[r5\],181
+     6ec:	00 00 04 00       	            nop\.i 0x0
+     6f0:	08 20 00 0a 96 10 	\[MMI\]       ld4\.bias\.nta r4=\[r5\]
+     6f6:	40 30 14 2c 25 00 	            ld4\.bias\.nta r4=\[r5\],r6
+     6fc:	00 00 04 00       	            nop\.i 0x0
+     700:	08 20 08 0b 97 14 	\[MMI\]       ld4\.bias\.nta r4=\[r5\],194
+     706:	40 00 14 60 21 00 	            ld4\.acq r4=\[r5\]
+     70c:	00 00 04 00       	            nop\.i 0x0
+     710:	08 20 18 0a b0 12 	\[MMI\]       ld4\.acq r4=\[r5\],r6
+     716:	40 78 16 62 29 00 	            ld4\.acq r4=\[r5\],207
+     71c:	00 00 04 00       	            nop\.i 0x0
+     720:	08 20 00 0a b2 10 	\[MMI\]       ld4\.acq\.nt1 r4=\[r5\]
+     726:	40 30 14 64 25 00 	            ld4\.acq\.nt1 r4=\[r5\],r6
+     72c:	00 00 04 00       	            nop\.i 0x0
+     730:	08 20 70 0b b3 14 	\[MMI\]       ld4\.acq\.nt1 r4=\[r5\],220
+     736:	40 00 14 6c 21 00 	            ld4\.acq\.nta r4=\[r5\]
+     73c:	00 00 04 00       	            nop\.i 0x0
+     740:	08 20 18 0a b6 12 	\[MMI\]       ld4\.acq\.nta r4=\[r5\],r6
+     746:	40 48 17 6e 29 00 	            ld4\.acq\.nta r4=\[r5\],233
+     74c:	00 00 04 00       	            nop\.i 0x0
+     750:	08 20 00 0a 50 11 	\[MMI\]       ld4\.c\.clr\.acq r4=\[r5\]
+     756:	40 30 14 a0 26 00 	            ld4\.c\.clr\.acq r4=\[r5\],r6
+     75c:	00 00 04 00       	            nop\.i 0x0
+     760:	08 20 d8 0b 51 15 	\[MMI\]       ld4\.c\.clr\.acq r4=\[r5\],246
+     766:	40 00 14 a4 22 00 	            ld4\.c\.clr\.acq\.nt1 r4=\[r5\]
+     76c:	00 00 04 00       	            nop\.i 0x0
+     770:	08 20 18 0a 52 13 	\[MMI\]       ld4\.c\.clr\.acq\.nt1 r4=\[r5\],r6
+     776:	40 18 14 a4 2e 00 	            ld4\.c\.clr\.acq\.nt1 r4=\[r5\],-253
+     77c:	00 00 04 00       	            nop\.i 0x0
+     780:	08 20 00 0a 56 11 	\[MMI\]       ld4\.c\.clr\.acq\.nta r4=\[r5\]
+     786:	40 30 14 ac 26 00 	            ld4\.c\.clr\.acq\.nta r4=\[r5\],r6
+     78c:	00 00 04 00       	            nop\.i 0x0
+     790:	08 20 40 0a 56 17 	\[MMI\]       ld4\.c\.clr\.acq\.nta r4=\[r5\],-240
+     796:	40 00 14 30 20 00 	            ld8 r4=\[r5\]
+     79c:	00 00 04 00       	            nop\.i 0x0
+     7a0:	08 20 18 0a 18 12 	\[MMI\]       ld8 r4=\[r5\],r6
+     7a6:	40 e8 14 30 2c 00 	            ld8 r4=\[r5\],-227
+     7ac:	00 00 04 00       	            nop\.i 0x0
+     7b0:	08 20 00 0a 1a 10 	\[MMI\]       ld8\.nt1 r4=\[r5\]
+     7b6:	40 30 14 34 24 00 	            ld8\.nt1 r4=\[r5\],r6
+     7bc:	00 00 04 00       	            nop\.i 0x0
+     7c0:	08 20 a8 0a 1a 16 	\[MMI\]       ld8\.nt1 r4=\[r5\],-214
+     7c6:	40 00 14 3c 20 00 	            ld8\.nta r4=\[r5\]
+     7cc:	00 00 04 00       	            nop\.i 0x0
+     7d0:	08 20 18 0a 1e 12 	\[MMI\]       ld8\.nta r4=\[r5\],r6
+     7d6:	40 b8 15 3c 2c 00 	            ld8\.nta r4=\[r5\],-201
+     7dc:	00 00 04 00       	            nop\.i 0x0
+     7e0:	08 20 00 0a 38 10 	\[MMI\]       ld8\.s r4=\[r5\]
+     7e6:	40 30 14 70 24 00 	            ld8\.s r4=\[r5\],r6
+     7ec:	00 00 04 00       	            nop\.i 0x0
+     7f0:	08 20 10 0b 38 16 	\[MMI\]       ld8\.s r4=\[r5\],-188
+     7f6:	40 00 14 74 20 00 	            ld8\.s\.nt1 r4=\[r5\]
+     7fc:	00 00 04 00       	            nop\.i 0x0
+     800:	08 20 18 0a 3a 12 	\[MMI\]       ld8\.s\.nt1 r4=\[r5\],r6
+     806:	40 88 16 74 2c 00 	            ld8\.s\.nt1 r4=\[r5\],-175
+     80c:	00 00 04 00       	            nop\.i 0x0
+     810:	08 20 00 0a 3e 10 	\[MMI\]       ld8\.s\.nta r4=\[r5\]
+     816:	40 30 14 7c 24 00 	            ld8\.s\.nta r4=\[r5\],r6
+     81c:	00 00 04 00       	            nop\.i 0x0
+     820:	08 20 78 0b 3e 16 	\[MMI\]       ld8\.s\.nta r4=\[r5\],-162
+     826:	40 00 14 b0 20 00 	            ld8\.a r4=\[r5\]
+     82c:	00 00 04 00       	            nop\.i 0x0
+     830:	08 20 18 0a 58 12 	\[MMI\]       ld8\.a r4=\[r5\],r6
+     836:	40 58 17 b0 2c 00 	            ld8\.a r4=\[r5\],-149
+     83c:	00 00 04 00       	            nop\.i 0x0
+     840:	08 20 00 0a 5a 10 	\[MMI\]       ld8\.a\.nt1 r4=\[r5\]
+     846:	40 30 14 b4 24 00 	            ld8\.a\.nt1 r4=\[r5\],r6
+     84c:	00 00 04 00       	            nop\.i 0x0
+     850:	08 20 e0 0b 5a 16 	\[MMI\]       ld8\.a\.nt1 r4=\[r5\],-136
+     856:	40 00 14 bc 20 00 	            ld8\.a\.nta r4=\[r5\]
+     85c:	00 00 04 00       	            nop\.i 0x0
+     860:	08 20 18 0a 5e 12 	\[MMI\]       ld8\.a\.nta r4=\[r5\],r6
+     866:	40 28 14 be 2c 00 	            ld8\.a\.nta r4=\[r5\],-123
+     86c:	00 00 04 00       	            nop\.i 0x0
+     870:	08 20 00 0a 78 10 	\[MMI\]       ld8\.sa r4=\[r5\]
+     876:	40 30 14 f0 24 00 	            ld8\.sa r4=\[r5\],r6
+     87c:	00 00 04 00       	            nop\.i 0x0
+     880:	08 20 48 0a 79 16 	\[MMI\]       ld8\.sa r4=\[r5\],-110
+     886:	40 00 14 f4 20 00 	            ld8\.sa\.nt1 r4=\[r5\]
+     88c:	00 00 04 00       	            nop\.i 0x0
+     890:	08 20 18 0a 7a 12 	\[MMI\]       ld8\.sa\.nt1 r4=\[r5\],r6
+     896:	40 f8 14 f6 2c 00 	            ld8\.sa\.nt1 r4=\[r5\],-97
+     89c:	00 00 04 00       	            nop\.i 0x0
+     8a0:	08 20 00 0a 7e 10 	\[MMI\]       ld8\.sa\.nta r4=\[r5\]
+     8a6:	40 30 14 fc 24 00 	            ld8\.sa\.nta r4=\[r5\],r6
+     8ac:	00 00 04 00       	            nop\.i 0x0
+     8b0:	08 20 b0 0a 7f 16 	\[MMI\]       ld8\.sa\.nta r4=\[r5\],-84
+     8b6:	40 00 14 30 22 00 	            ld8\.c\.clr r4=\[r5\]
+     8bc:	00 00 04 00       	            nop\.i 0x0
+     8c0:	08 20 18 0a 18 13 	\[MMI\]       ld8\.c\.clr r4=\[r5\],r6
+     8c6:	40 c8 15 32 2e 00 	            ld8\.c\.clr r4=\[r5\],-71
+     8cc:	00 00 04 00       	            nop\.i 0x0
+     8d0:	08 20 00 0a 1a 11 	\[MMI\]       ld8\.c\.clr\.nt1 r4=\[r5\]
+     8d6:	40 30 14 34 26 00 	            ld8\.c\.clr\.nt1 r4=\[r5\],r6
+     8dc:	00 00 04 00       	            nop\.i 0x0
+     8e0:	08 20 18 0b 1b 17 	\[MMI\]       ld8\.c\.clr\.nt1 r4=\[r5\],-58
+     8e6:	40 00 14 3c 22 00 	            ld8\.c\.clr\.nta r4=\[r5\]
+     8ec:	00 00 04 00       	            nop\.i 0x0
+     8f0:	08 20 18 0a 1e 13 	\[MMI\]       ld8\.c\.clr\.nta r4=\[r5\],r6
+     8f6:	40 98 16 3e 2e 00 	            ld8\.c\.clr\.nta r4=\[r5\],-45
+     8fc:	00 00 04 00       	            nop\.i 0x0
+     900:	08 20 00 0a 38 11 	\[MMI\]       ld8\.c\.nc r4=\[r5\]
+     906:	40 30 14 70 26 00 	            ld8\.c\.nc r4=\[r5\],r6
+     90c:	00 00 04 00       	            nop\.i 0x0
+     910:	08 20 80 0b 39 17 	\[MMI\]       ld8\.c\.nc r4=\[r5\],-32
+     916:	40 00 14 74 22 00 	            ld8\.c\.nc\.nt1 r4=\[r5\]
+     91c:	00 00 04 00       	            nop\.i 0x0
+     920:	08 20 18 0a 3a 13 	\[MMI\]       ld8\.c\.nc\.nt1 r4=\[r5\],r6
+     926:	40 68 17 76 2e 00 	            ld8\.c\.nc\.nt1 r4=\[r5\],-19
+     92c:	00 00 04 00       	            nop\.i 0x0
+     930:	08 20 00 0a 3e 11 	\[MMI\]       ld8\.c\.nc\.nta r4=\[r5\]
+     936:	40 30 14 7c 26 00 	            ld8\.c\.nc\.nta r4=\[r5\],r6
+     93c:	00 00 04 00       	            nop\.i 0x0
+     940:	08 20 e8 0b 3f 17 	\[MMI\]       ld8\.c\.nc\.nta r4=\[r5\],-6
+     946:	40 00 14 30 21 00 	            ld8\.bias r4=\[r5\]
+     94c:	00 00 04 00       	            nop\.i 0x0
+     950:	08 20 18 0a 98 12 	\[MMI\]       ld8\.bias r4=\[r5\],r6
+     956:	40 38 14 30 29 00 	            ld8\.bias r4=\[r5\],7
+     95c:	00 00 04 00       	            nop\.i 0x0
+     960:	08 20 00 0a 9a 10 	\[MMI\]       ld8\.bias\.nt1 r4=\[r5\]
+     966:	40 30 14 34 25 00 	            ld8\.bias\.nt1 r4=\[r5\],r6
+     96c:	00 00 04 00       	            nop\.i 0x0
+     970:	08 20 50 0a 9a 14 	\[MMI\]       ld8\.bias\.nt1 r4=\[r5\],20
+     976:	40 00 14 3c 21 00 	            ld8\.bias\.nta r4=\[r5\]
+     97c:	00 00 04 00       	            nop\.i 0x0
+     980:	08 20 18 0a 9e 12 	\[MMI\]       ld8\.bias\.nta r4=\[r5\],r6
+     986:	40 08 15 3c 29 00 	            ld8\.bias\.nta r4=\[r5\],33
+     98c:	00 00 04 00       	            nop\.i 0x0
+     990:	08 20 00 0a b8 10 	\[MMI\]       ld8\.acq r4=\[r5\]
+     996:	40 30 14 70 25 00 	            ld8\.acq r4=\[r5\],r6
+     99c:	00 00 04 00       	            nop\.i 0x0
+     9a0:	08 20 b8 0a b8 14 	\[MMI\]       ld8\.acq r4=\[r5\],46
+     9a6:	40 00 14 74 21 00 	            ld8\.acq\.nt1 r4=\[r5\]
+     9ac:	00 00 04 00       	            nop\.i 0x0
+     9b0:	08 20 18 0a ba 12 	\[MMI\]       ld8\.acq\.nt1 r4=\[r5\],r6
+     9b6:	40 d8 15 74 29 00 	            ld8\.acq\.nt1 r4=\[r5\],59
+     9bc:	00 00 04 00       	            nop\.i 0x0
+     9c0:	08 20 00 0a be 10 	\[MMI\]       ld8\.acq\.nta r4=\[r5\]
+     9c6:	40 30 14 7c 25 00 	            ld8\.acq\.nta r4=\[r5\],r6
+     9cc:	00 00 04 00       	            nop\.i 0x0
+     9d0:	08 20 20 0b be 14 	\[MMI\]       ld8\.acq\.nta r4=\[r5\],72
+     9d6:	40 00 14 b0 22 00 	            ld8\.c\.clr\.acq r4=\[r5\]
+     9dc:	00 00 04 00       	            nop\.i 0x0
+     9e0:	08 20 18 0a 58 13 	\[MMI\]       ld8\.c\.clr\.acq r4=\[r5\],r6
+     9e6:	40 a8 16 b0 2a 00 	            ld8\.c\.clr\.acq r4=\[r5\],85
+     9ec:	00 00 04 00       	            nop\.i 0x0
+     9f0:	08 20 00 0a 5a 11 	\[MMI\]       ld8\.c\.clr\.acq\.nt1 r4=\[r5\]
+     9f6:	40 30 14 b4 26 00 	            ld8\.c\.clr\.acq\.nt1 r4=\[r5\],r6
+     9fc:	00 00 04 00       	            nop\.i 0x0
+     a00:	08 20 88 0b 5a 15 	\[MMI\]       ld8\.c\.clr\.acq\.nt1 r4=\[r5\],98
+     a06:	40 00 14 bc 22 00 	            ld8\.c\.clr\.acq\.nta r4=\[r5\]
+     a0c:	00 00 04 00       	            nop\.i 0x0
+     a10:	08 20 18 0a 5e 13 	\[MMI\]       ld8\.c\.clr\.acq\.nta r4=\[r5\],r6
+     a16:	40 78 17 bc 2a 00 	            ld8\.c\.clr\.acq\.nta r4=\[r5\],111
+     a1c:	00 00 04 00       	            nop\.i 0x0
+     a20:	08 20 00 0a d8 10 	\[MMI\]       ld8\.fill r4=\[r5\]
+     a26:	40 30 14 b0 25 00 	            ld8\.fill r4=\[r5\],r6
+     a2c:	00 00 04 00       	            nop\.i 0x0
+     a30:	08 20 f0 0b d8 14 	\[MMI\]       ld8\.fill r4=\[r5\],124
+     a36:	40 00 14 b4 21 00 	            ld8\.fill\.nt1 r4=\[r5\]
+     a3c:	00 00 04 00       	            nop\.i 0x0
+     a40:	08 20 18 0a da 12 	\[MMI\]       ld8\.fill\.nt1 r4=\[r5\],r6
+     a46:	40 48 14 b6 29 00 	            ld8\.fill\.nt1 r4=\[r5\],137
+     a4c:	00 00 04 00       	            nop\.i 0x0
+     a50:	08 20 00 0a de 10 	\[MMI\]       ld8\.fill\.nta r4=\[r5\]
+     a56:	40 30 14 bc 25 00 	            ld8\.fill\.nta r4=\[r5\],r6
+     a5c:	00 00 04 00       	            nop\.i 0x0
+     a60:	08 20 58 0a df 14 	\[MMI\]       ld8\.fill\.nta r4=\[r5\],150
+     a66:	00 28 10 00 23 00 	            st1 \[r4\]=r5
+     a6c:	00 00 04 00       	            nop\.i 0x0
+     a70:	08 18 15 08 81 15 	\[MMI\]       st1 \[r4\]=r5,163
+     a76:	00 28 10 0c 23 00 	            st1\.nta \[r4\]=r5
+     a7c:	00 00 04 00       	            nop\.i 0x0
+     a80:	08 80 15 08 87 15 	\[MMI\]       st1\.nta \[r4\]=r5,176
+     a86:	00 28 10 10 23 00 	            st2 \[r4\]=r5
+     a8c:	00 00 04 00       	            nop\.i 0x0
+     a90:	08 e8 15 08 89 15 	\[MMI\]       st2 \[r4\]=r5,189
+     a96:	00 28 10 1c 23 00 	            st2\.nta \[r4\]=r5
+     a9c:	00 00 04 00       	            nop\.i 0x0
+     aa0:	08 50 16 08 8f 15 	\[MMI\]       st2\.nta \[r4\]=r5,202
+     aa6:	00 28 10 20 23 00 	            st4 \[r4\]=r5
+     aac:	00 00 04 00       	            nop\.i 0x0
+     ab0:	08 b8 16 08 91 15 	\[MMI\]       st4 \[r4\]=r5,215
+     ab6:	00 28 10 2c 23 00 	            st4\.nta \[r4\]=r5
+     abc:	00 00 04 00       	            nop\.i 0x0
+     ac0:	08 20 17 08 97 15 	\[MMI\]       st4\.nta \[r4\]=r5,228
+     ac6:	00 28 10 30 23 00 	            st8 \[r4\]=r5
+     acc:	00 00 04 00       	            nop\.i 0x0
+     ad0:	08 88 17 08 99 15 	\[MMI\]       st8 \[r4\]=r5,241
+     ad6:	00 28 10 3c 23 00 	            st8\.nta \[r4\]=r5
+     adc:	00 00 04 00       	            nop\.i 0x0
+     ae0:	08 f0 17 08 9f 15 	\[MMI\]       st8\.nta \[r4\]=r5,254
+     ae6:	00 28 10 40 23 00 	            st1\.rel \[r4\]=r5
+     aec:	00 00 04 00       	            nop\.i 0x0
+     af0:	08 58 14 08 a0 17 	\[MMI\]       st1\.rel \[r4\]=r5,-245
+     af6:	00 28 10 4c 23 00 	            st1\.rel\.nta \[r4\]=r5
+     afc:	00 00 04 00       	            nop\.i 0x0
+     b00:	08 c0 14 08 a6 17 	\[MMI\]       st1\.rel\.nta \[r4\]=r5,-232
+     b06:	00 28 10 50 23 00 	            st2\.rel \[r4\]=r5
+     b0c:	00 00 04 00       	            nop\.i 0x0
+     b10:	08 28 15 08 a8 17 	\[MMI\]       st2\.rel \[r4\]=r5,-219
+     b16:	00 28 10 5c 23 00 	            st2\.rel\.nta \[r4\]=r5
+     b1c:	00 00 04 00       	            nop\.i 0x0
+     b20:	08 90 15 08 ae 17 	\[MMI\]       st2\.rel\.nta \[r4\]=r5,-206
+     b26:	00 28 10 60 23 00 	            st4\.rel \[r4\]=r5
+     b2c:	00 00 04 00       	            nop\.i 0x0
+     b30:	08 f8 15 08 b0 17 	\[MMI\]       st4\.rel \[r4\]=r5,-193
+     b36:	00 28 10 6c 23 00 	            st4\.rel\.nta \[r4\]=r5
+     b3c:	00 00 04 00       	            nop\.i 0x0
+     b40:	08 60 16 08 b6 17 	\[MMI\]       st4\.rel\.nta \[r4\]=r5,-180
+     b46:	00 28 10 70 23 00 	            st8\.rel \[r4\]=r5
+     b4c:	00 00 04 00       	            nop\.i 0x0
+     b50:	08 c8 16 08 b8 17 	\[MMI\]       st8\.rel \[r4\]=r5,-167
+     b56:	00 28 10 7c 23 00 	            st8\.rel\.nta \[r4\]=r5
+     b5c:	00 00 04 00       	            nop\.i 0x0
+     b60:	08 30 17 08 be 17 	\[MMI\]       st8\.rel\.nta \[r4\]=r5,-154
+     b66:	00 28 10 b0 23 00 	            st8\.spill \[r4\]=r5
+     b6c:	00 00 04 00       	            nop\.i 0x0
+     b70:	08 98 17 08 d8 17 	\[MMI\]       st8\.spill \[r4\]=r5,-141
+     b76:	00 28 10 bc 23 00 	            st8\.spill\.nta \[r4\]=r5
+     b7c:	00 00 04 00       	            nop\.i 0x0
+     b80:	08 00 14 08 df 17 	\[MMI\]       st8\.spill\.nta \[r4\]=r5,-128
+     b86:	40 00 14 20 30 00 	            ldfs f4=\[r5\]
+     b8c:	00 00 04 00       	            nop\.i 0x0
+     b90:	08 20 18 0a 10 1a 	\[MMI\]       ldfs f4=\[r5\],r6
+     b96:	40 68 14 22 3c 00 	            ldfs f4=\[r5\],-115
+     b9c:	00 00 04 00       	            nop\.i 0x0
+     ba0:	08 20 00 0a 12 18 	\[MMI\]       ldfs\.nt1 f4=\[r5\]
+     ba6:	40 30 14 24 34 00 	            ldfs\.nt1 f4=\[r5\],r6
+     bac:	00 00 04 00       	            nop\.i 0x0
+     bb0:	08 20 68 0a 13 1e 	\[MMI\]       ldfs\.nt1 f4=\[r5\],-102
+     bb6:	40 00 14 2c 30 00 	            ldfs\.nta f4=\[r5\]
+     bbc:	00 00 04 00       	            nop\.i 0x0
+     bc0:	08 20 18 0a 16 1a 	\[MMI\]       ldfs\.nta f4=\[r5\],r6
+     bc6:	40 38 15 2e 3c 00 	            ldfs\.nta f4=\[r5\],-89
+     bcc:	00 00 04 00       	            nop\.i 0x0
+     bd0:	08 20 00 0a 30 18 	\[MMI\]       ldfs\.s f4=\[r5\]
+     bd6:	40 30 14 60 34 00 	            ldfs\.s f4=\[r5\],r6
+     bdc:	00 00 04 00       	            nop\.i 0x0
+     be0:	08 20 d0 0a 31 1e 	\[MMI\]       ldfs\.s f4=\[r5\],-76
+     be6:	40 00 14 64 30 00 	            ldfs\.s\.nt1 f4=\[r5\]
+     bec:	00 00 04 00       	            nop\.i 0x0
+     bf0:	08 20 18 0a 32 1a 	\[MMI\]       ldfs\.s\.nt1 f4=\[r5\],r6
+     bf6:	40 08 16 66 3c 00 	            ldfs\.s\.nt1 f4=\[r5\],-63
+     bfc:	00 00 04 00       	            nop\.i 0x0
+     c00:	08 20 00 0a 36 18 	\[MMI\]       ldfs\.s\.nta f4=\[r5\]
+     c06:	40 30 14 6c 34 00 	            ldfs\.s\.nta f4=\[r5\],r6
+     c0c:	00 00 04 00       	            nop\.i 0x0
+     c10:	08 20 38 0b 37 1e 	\[MMI\]       ldfs\.s\.nta f4=\[r5\],-50
+     c16:	40 00 14 a0 30 00 	            ldfs\.a f4=\[r5\]
+     c1c:	00 00 04 00       	            nop\.i 0x0
+     c20:	08 20 18 0a 50 1a 	\[MMI\]       ldfs\.a f4=\[r5\],r6
+     c26:	40 d8 16 a2 3c 00 	            ldfs\.a f4=\[r5\],-37
+     c2c:	00 00 04 00       	            nop\.i 0x0
+     c30:	08 20 00 0a 52 18 	\[MMI\]       ldfs\.a\.nt1 f4=\[r5\]
+     c36:	40 30 14 a4 34 00 	            ldfs\.a\.nt1 f4=\[r5\],r6
+     c3c:	00 00 04 00       	            nop\.i 0x0
+     c40:	08 20 a0 0b 53 1e 	\[MMI\]       ldfs\.a\.nt1 f4=\[r5\],-24
+     c46:	40 00 14 ac 30 00 	            ldfs\.a\.nta f4=\[r5\]
+     c4c:	00 00 04 00       	            nop\.i 0x0
+     c50:	08 20 18 0a 56 1a 	\[MMI\]       ldfs\.a\.nta f4=\[r5\],r6
+     c56:	40 a8 17 ae 3c 00 	            ldfs\.a\.nta f4=\[r5\],-11
+     c5c:	00 00 04 00       	            nop\.i 0x0
+     c60:	08 20 00 0a 70 18 	\[MMI\]       ldfs\.sa f4=\[r5\]
+     c66:	40 30 14 e0 34 00 	            ldfs\.sa f4=\[r5\],r6
+     c6c:	00 00 04 00       	            nop\.i 0x0
+     c70:	08 20 08 0a 70 1c 	\[MMI\]       ldfs\.sa f4=\[r5\],2
+     c76:	40 00 14 e4 30 00 	            ldfs\.sa\.nt1 f4=\[r5\]
+     c7c:	00 00 04 00       	            nop\.i 0x0
+     c80:	08 20 18 0a 72 1a 	\[MMI\]       ldfs\.sa\.nt1 f4=\[r5\],r6
+     c86:	40 78 14 e4 38 00 	            ldfs\.sa\.nt1 f4=\[r5\],15
+     c8c:	00 00 04 00       	            nop\.i 0x0
+     c90:	08 20 00 0a 76 18 	\[MMI\]       ldfs\.sa\.nta f4=\[r5\]
+     c96:	40 30 14 ec 34 00 	            ldfs\.sa\.nta f4=\[r5\],r6
+     c9c:	00 00 04 00       	            nop\.i 0x0
+     ca0:	08 20 70 0a 76 1c 	\[MMI\]       ldfs\.sa\.nta f4=\[r5\],28
+     ca6:	40 00 14 20 32 00 	            ldfs\.c\.clr f4=\[r5\]
+     cac:	00 00 04 00       	            nop\.i 0x0
+     cb0:	08 20 18 0a 10 1b 	\[MMI\]       ldfs\.c\.clr f4=\[r5\],r6
+     cb6:	40 48 15 20 3a 00 	            ldfs\.c\.clr f4=\[r5\],41
+     cbc:	00 00 04 00       	            nop\.i 0x0
+     cc0:	08 20 00 0a 12 19 	\[MMI\]       ldfs\.c\.clr\.nt1 f4=\[r5\]
+     cc6:	40 30 14 24 36 00 	            ldfs\.c\.clr\.nt1 f4=\[r5\],r6
+     ccc:	00 00 04 00       	            nop\.i 0x0
+     cd0:	08 20 d8 0a 12 1d 	\[MMI\]       ldfs\.c\.clr\.nt1 f4=\[r5\],54
+     cd6:	40 00 14 2c 32 00 	            ldfs\.c\.clr\.nta f4=\[r5\]
+     cdc:	00 00 04 00       	            nop\.i 0x0
+     ce0:	08 20 18 0a 16 1b 	\[MMI\]       ldfs\.c\.clr\.nta f4=\[r5\],r6
+     ce6:	40 18 16 2c 3a 00 	            ldfs\.c\.clr\.nta f4=\[r5\],67
+     cec:	00 00 04 00       	            nop\.i 0x0
+     cf0:	08 20 00 0a 30 19 	\[MMI\]       ldfs\.c\.nc f4=\[r5\]
+     cf6:	40 30 14 60 36 00 	            ldfs\.c\.nc f4=\[r5\],r6
+     cfc:	00 00 04 00       	            nop\.i 0x0
+     d00:	08 20 40 0b 30 1d 	\[MMI\]       ldfs\.c\.nc f4=\[r5\],80
+     d06:	40 00 14 64 32 00 	            ldfs\.c\.nc\.nt1 f4=\[r5\]
+     d0c:	00 00 04 00       	            nop\.i 0x0
+     d10:	08 20 18 0a 32 1b 	\[MMI\]       ldfs\.c\.nc\.nt1 f4=\[r5\],r6
+     d16:	40 e8 16 64 3a 00 	            ldfs\.c\.nc\.nt1 f4=\[r5\],93
+     d1c:	00 00 04 00       	            nop\.i 0x0
+     d20:	08 20 00 0a 36 19 	\[MMI\]       ldfs\.c\.nc\.nta f4=\[r5\]
+     d26:	40 30 14 6c 36 00 	            ldfs\.c\.nc\.nta f4=\[r5\],r6
+     d2c:	00 00 04 00       	            nop\.i 0x0
+     d30:	08 20 a8 0b 36 1d 	\[MMI\]       ldfs\.c\.nc\.nta f4=\[r5\],106
+     d36:	40 00 14 30 30 00 	            ldfd f4=\[r5\]
+     d3c:	00 00 04 00       	            nop\.i 0x0
+     d40:	08 20 18 0a 18 1a 	\[MMI\]       ldfd f4=\[r5\],r6
+     d46:	40 b8 17 30 38 00 	            ldfd f4=\[r5\],119
+     d4c:	00 00 04 00       	            nop\.i 0x0
+     d50:	08 20 00 0a 1a 18 	\[MMI\]       ldfd\.nt1 f4=\[r5\]
+     d56:	40 30 14 34 34 00 	            ldfd\.nt1 f4=\[r5\],r6
+     d5c:	00 00 04 00       	            nop\.i 0x0
+     d60:	08 20 10 0a 1b 1c 	\[MMI\]       ldfd\.nt1 f4=\[r5\],132
+     d66:	40 00 14 3c 30 00 	            ldfd\.nta f4=\[r5\]
+     d6c:	00 00 04 00       	            nop\.i 0x0
+     d70:	08 20 18 0a 1e 1a 	\[MMI\]       ldfd\.nta f4=\[r5\],r6
+     d76:	40 88 14 3e 38 00 	            ldfd\.nta f4=\[r5\],145
+     d7c:	00 00 04 00       	            nop\.i 0x0
+     d80:	08 20 00 0a 38 18 	\[MMI\]       ldfd\.s f4=\[r5\]
+     d86:	40 30 14 70 34 00 	            ldfd\.s f4=\[r5\],r6
+     d8c:	00 00 04 00       	            nop\.i 0x0
+     d90:	08 20 78 0a 39 1c 	\[MMI\]       ldfd\.s f4=\[r5\],158
+     d96:	40 00 14 74 30 00 	            ldfd\.s\.nt1 f4=\[r5\]
+     d9c:	00 00 04 00       	            nop\.i 0x0
+     da0:	08 20 18 0a 3a 1a 	\[MMI\]       ldfd\.s\.nt1 f4=\[r5\],r6
+     da6:	40 58 15 76 38 00 	            ldfd\.s\.nt1 f4=\[r5\],171
+     dac:	00 00 04 00       	            nop\.i 0x0
+     db0:	08 20 00 0a 3e 18 	\[MMI\]       ldfd\.s\.nta f4=\[r5\]
+     db6:	40 30 14 7c 34 00 	            ldfd\.s\.nta f4=\[r5\],r6
+     dbc:	00 00 04 00       	            nop\.i 0x0
+     dc0:	08 20 e0 0a 3f 1c 	\[MMI\]       ldfd\.s\.nta f4=\[r5\],184
+     dc6:	40 00 14 b0 30 00 	            ldfd\.a f4=\[r5\]
+     dcc:	00 00 04 00       	            nop\.i 0x0
+     dd0:	08 20 18 0a 58 1a 	\[MMI\]       ldfd\.a f4=\[r5\],r6
+     dd6:	40 28 16 b2 38 00 	            ldfd\.a f4=\[r5\],197
+     ddc:	00 00 04 00       	            nop\.i 0x0
+     de0:	08 20 00 0a 5a 18 	\[MMI\]       ldfd\.a\.nt1 f4=\[r5\]
+     de6:	40 30 14 b4 34 00 	            ldfd\.a\.nt1 f4=\[r5\],r6
+     dec:	00 00 04 00       	            nop\.i 0x0
+     df0:	08 20 48 0b 5b 1c 	\[MMI\]       ldfd\.a\.nt1 f4=\[r5\],210
+     df6:	40 00 14 bc 30 00 	            ldfd\.a\.nta f4=\[r5\]
+     dfc:	00 00 04 00       	            nop\.i 0x0
+     e00:	08 20 18 0a 5e 1a 	\[MMI\]       ldfd\.a\.nta f4=\[r5\],r6
+     e06:	40 f8 16 be 38 00 	            ldfd\.a\.nta f4=\[r5\],223
+     e0c:	00 00 04 00       	            nop\.i 0x0
+     e10:	08 20 00 0a 78 18 	\[MMI\]       ldfd\.sa f4=\[r5\]
+     e16:	40 30 14 f0 34 00 	            ldfd\.sa f4=\[r5\],r6
+     e1c:	00 00 04 00       	            nop\.i 0x0
+     e20:	08 20 b0 0b 79 1c 	\[MMI\]       ldfd\.sa f4=\[r5\],236
+     e26:	40 00 14 f4 30 00 	            ldfd\.sa\.nt1 f4=\[r5\]
+     e2c:	00 00 04 00       	            nop\.i 0x0
+     e30:	08 20 18 0a 7a 1a 	\[MMI\]       ldfd\.sa\.nt1 f4=\[r5\],r6
+     e36:	40 c8 17 f6 38 00 	            ldfd\.sa\.nt1 f4=\[r5\],249
+     e3c:	00 00 04 00       	            nop\.i 0x0
+     e40:	08 20 00 0a 7e 18 	\[MMI\]       ldfd\.sa\.nta f4=\[r5\]
+     e46:	40 30 14 fc 34 00 	            ldfd\.sa\.nta f4=\[r5\],r6
+     e4c:	00 00 04 00       	            nop\.i 0x0
+     e50:	08 20 18 0a 7e 1e 	\[MMI\]       ldfd\.sa\.nta f4=\[r5\],-250
+     e56:	40 00 14 30 32 00 	            ldfd\.c\.clr f4=\[r5\]
+     e5c:	00 00 04 00       	            nop\.i 0x0
+     e60:	08 20 18 0a 18 1b 	\[MMI\]       ldfd\.c\.clr f4=\[r5\],r6
+     e66:	40 98 14 30 3e 00 	            ldfd\.c\.clr f4=\[r5\],-237
+     e6c:	00 00 04 00       	            nop\.i 0x0
+     e70:	08 20 00 0a 1a 19 	\[MMI\]       ldfd\.c\.clr\.nt1 f4=\[r5\]
+     e76:	40 30 14 34 36 00 	            ldfd\.c\.clr\.nt1 f4=\[r5\],r6
+     e7c:	00 00 04 00       	            nop\.i 0x0
+     e80:	08 20 80 0a 1a 1f 	\[MMI\]       ldfd\.c\.clr\.nt1 f4=\[r5\],-224
+     e86:	40 00 14 3c 32 00 	            ldfd\.c\.clr\.nta f4=\[r5\]
+     e8c:	00 00 04 00       	            nop\.i 0x0
+     e90:	08 20 18 0a 1e 1b 	\[MMI\]       ldfd\.c\.clr\.nta f4=\[r5\],r6
+     e96:	40 68 15 3c 3e 00 	            ldfd\.c\.clr\.nta f4=\[r5\],-211
+     e9c:	00 00 04 00       	            nop\.i 0x0
+     ea0:	08 20 00 0a 38 19 	\[MMI\]       ldfd\.c\.nc f4=\[r5\]
+     ea6:	40 30 14 70 36 00 	            ldfd\.c\.nc f4=\[r5\],r6
+     eac:	00 00 04 00       	            nop\.i 0x0
+     eb0:	08 20 e8 0a 38 1f 	\[MMI\]       ldfd\.c\.nc f4=\[r5\],-198
+     eb6:	40 00 14 74 32 00 	            ldfd\.c\.nc\.nt1 f4=\[r5\]
+     ebc:	00 00 04 00       	            nop\.i 0x0
+     ec0:	08 20 18 0a 3a 1b 	\[MMI\]       ldfd\.c\.nc\.nt1 f4=\[r5\],r6
+     ec6:	40 38 16 74 3e 00 	            ldfd\.c\.nc\.nt1 f4=\[r5\],-185
+     ecc:	00 00 04 00       	            nop\.i 0x0
+     ed0:	08 20 00 0a 3e 19 	\[MMI\]       ldfd\.c\.nc\.nta f4=\[r5\]
+     ed6:	40 30 14 7c 36 00 	            ldfd\.c\.nc\.nta f4=\[r5\],r6
+     edc:	00 00 04 00       	            nop\.i 0x0
+     ee0:	08 20 50 0b 3e 1f 	\[MMI\]       ldfd\.c\.nc\.nta f4=\[r5\],-172
+     ee6:	40 00 14 10 30 00 	            ldf8 f4=\[r5\]
+     eec:	00 00 04 00       	            nop\.i 0x0
+     ef0:	08 20 18 0a 08 1a 	\[MMI\]       ldf8 f4=\[r5\],r6
+     ef6:	40 08 17 10 3c 00 	            ldf8 f4=\[r5\],-159
+     efc:	00 00 04 00       	            nop\.i 0x0
+     f00:	08 20 00 0a 0a 18 	\[MMI\]       ldf8\.nt1 f4=\[r5\]
+     f06:	40 30 14 14 34 00 	            ldf8\.nt1 f4=\[r5\],r6
+     f0c:	00 00 04 00       	            nop\.i 0x0
+     f10:	08 20 b8 0b 0a 1e 	\[MMI\]       ldf8\.nt1 f4=\[r5\],-146
+     f16:	40 00 14 1c 30 00 	            ldf8\.nta f4=\[r5\]
+     f1c:	00 00 04 00       	            nop\.i 0x0
+     f20:	08 20 18 0a 0e 1a 	\[MMI\]       ldf8\.nta f4=\[r5\],r6
+     f26:	40 d8 17 1c 3c 00 	            ldf8\.nta f4=\[r5\],-133
+     f2c:	00 00 04 00       	            nop\.i 0x0
+     f30:	08 20 00 0a 28 18 	\[MMI\]       ldf8\.s f4=\[r5\]
+     f36:	40 30 14 50 34 00 	            ldf8\.s f4=\[r5\],r6
+     f3c:	00 00 04 00       	            nop\.i 0x0
+     f40:	08 20 20 0a 29 1e 	\[MMI\]       ldf8\.s f4=\[r5\],-120
+     f46:	40 00 14 54 30 00 	            ldf8\.s\.nt1 f4=\[r5\]
+     f4c:	00 00 04 00       	            nop\.i 0x0
+     f50:	08 20 18 0a 2a 1a 	\[MMI\]       ldf8\.s\.nt1 f4=\[r5\],r6
+     f56:	40 a8 14 56 3c 00 	            ldf8\.s\.nt1 f4=\[r5\],-107
+     f5c:	00 00 04 00       	            nop\.i 0x0
+     f60:	08 20 00 0a 2e 18 	\[MMI\]       ldf8\.s\.nta f4=\[r5\]
+     f66:	40 30 14 5c 34 00 	            ldf8\.s\.nta f4=\[r5\],r6
+     f6c:	00 00 04 00       	            nop\.i 0x0
+     f70:	08 20 88 0a 2f 1e 	\[MMI\]       ldf8\.s\.nta f4=\[r5\],-94
+     f76:	40 00 14 90 30 00 	            ldf8\.a f4=\[r5\]
+     f7c:	00 00 04 00       	            nop\.i 0x0
+     f80:	08 20 18 0a 48 1a 	\[MMI\]       ldf8\.a f4=\[r5\],r6
+     f86:	40 78 15 92 3c 00 	            ldf8\.a f4=\[r5\],-81
+     f8c:	00 00 04 00       	            nop\.i 0x0
+     f90:	08 20 00 0a 4a 18 	\[MMI\]       ldf8\.a\.nt1 f4=\[r5\]
+     f96:	40 30 14 94 34 00 	            ldf8\.a\.nt1 f4=\[r5\],r6
+     f9c:	00 00 04 00       	            nop\.i 0x0
+     fa0:	08 20 f0 0a 4b 1e 	\[MMI\]       ldf8\.a\.nt1 f4=\[r5\],-68
+     fa6:	40 00 14 9c 30 00 	            ldf8\.a\.nta f4=\[r5\]
+     fac:	00 00 04 00       	            nop\.i 0x0
+     fb0:	08 20 18 0a 4e 1a 	\[MMI\]       ldf8\.a\.nta f4=\[r5\],r6
+     fb6:	40 48 16 9e 3c 00 	            ldf8\.a\.nta f4=\[r5\],-55
+     fbc:	00 00 04 00       	            nop\.i 0x0
+     fc0:	08 20 00 0a 68 18 	\[MMI\]       ldf8\.sa f4=\[r5\]
+     fc6:	40 30 14 d0 34 00 	            ldf8\.sa f4=\[r5\],r6
+     fcc:	00 00 04 00       	            nop\.i 0x0
+     fd0:	08 20 58 0b 69 1e 	\[MMI\]       ldf8\.sa f4=\[r5\],-42
+     fd6:	40 00 14 d4 30 00 	            ldf8\.sa\.nt1 f4=\[r5\]
+     fdc:	00 00 04 00       	            nop\.i 0x0
+     fe0:	08 20 18 0a 6a 1a 	\[MMI\]       ldf8\.sa\.nt1 f4=\[r5\],r6
+     fe6:	40 18 17 d6 3c 00 	            ldf8\.sa\.nt1 f4=\[r5\],-29
+     fec:	00 00 04 00       	            nop\.i 0x0
+     ff0:	08 20 00 0a 6e 18 	\[MMI\]       ldf8\.sa\.nta f4=\[r5\]
+     ff6:	40 30 14 dc 34 00 	            ldf8\.sa\.nta f4=\[r5\],r6
+     ffc:	00 00 04 00       	            nop\.i 0x0
+    1000:	08 20 c0 0b 6f 1e 	\[MMI\]       ldf8\.sa\.nta f4=\[r5\],-16
+    1006:	40 00 14 10 32 00 	            ldf8\.c\.clr f4=\[r5\]
+    100c:	00 00 04 00       	            nop\.i 0x0
+    1010:	08 20 18 0a 08 1b 	\[MMI\]       ldf8\.c\.clr f4=\[r5\],r6
+    1016:	40 e8 17 12 3e 00 	            ldf8\.c\.clr f4=\[r5\],-3
+    101c:	00 00 04 00       	            nop\.i 0x0
+    1020:	08 20 00 0a 0a 19 	\[MMI\]       ldf8\.c\.clr\.nt1 f4=\[r5\]
+    1026:	40 30 14 14 36 00 	            ldf8\.c\.clr\.nt1 f4=\[r5\],r6
+    102c:	00 00 04 00       	            nop\.i 0x0
+    1030:	08 20 28 0a 0a 1d 	\[MMI\]       ldf8\.c\.clr\.nt1 f4=\[r5\],10
+    1036:	40 00 14 1c 32 00 	            ldf8\.c\.clr\.nta f4=\[r5\]
+    103c:	00 00 04 00       	            nop\.i 0x0
+    1040:	08 20 18 0a 0e 1b 	\[MMI\]       ldf8\.c\.clr\.nta f4=\[r5\],r6
+    1046:	40 b8 14 1c 3a 00 	            ldf8\.c\.clr\.nta f4=\[r5\],23
+    104c:	00 00 04 00       	            nop\.i 0x0
+    1050:	08 20 00 0a 28 19 	\[MMI\]       ldf8\.c\.nc f4=\[r5\]
+    1056:	40 30 14 50 36 00 	            ldf8\.c\.nc f4=\[r5\],r6
+    105c:	00 00 04 00       	            nop\.i 0x0
+    1060:	08 20 90 0a 28 1d 	\[MMI\]       ldf8\.c\.nc f4=\[r5\],36
+    1066:	40 00 14 54 32 00 	            ldf8\.c\.nc\.nt1 f4=\[r5\]
+    106c:	00 00 04 00       	            nop\.i 0x0
+    1070:	08 20 18 0a 2a 1b 	\[MMI\]       ldf8\.c\.nc\.nt1 f4=\[r5\],r6
+    1076:	40 88 15 54 3a 00 	            ldf8\.c\.nc\.nt1 f4=\[r5\],49
+    107c:	00 00 04 00       	            nop\.i 0x0
+    1080:	08 20 00 0a 2e 19 	\[MMI\]       ldf8\.c\.nc\.nta f4=\[r5\]
+    1086:	40 30 14 5c 36 00 	            ldf8\.c\.nc\.nta f4=\[r5\],r6
+    108c:	00 00 04 00       	            nop\.i 0x0
+    1090:	08 20 f8 0a 2e 1d 	\[MMI\]       ldf8\.c\.nc\.nta f4=\[r5\],62
+    1096:	40 00 14 00 30 00 	            ldfe f4=\[r5\]
+    109c:	00 00 04 00       	            nop\.i 0x0
+    10a0:	08 20 18 0a 00 1a 	\[MMI\]       ldfe f4=\[r5\],r6
+    10a6:	40 58 16 00 38 00 	            ldfe f4=\[r5\],75
+    10ac:	00 00 04 00       	            nop\.i 0x0
+    10b0:	08 20 00 0a 02 18 	\[MMI\]       ldfe\.nt1 f4=\[r5\]
+    10b6:	40 30 14 04 34 00 	            ldfe\.nt1 f4=\[r5\],r6
+    10bc:	00 00 04 00       	            nop\.i 0x0
+    10c0:	08 20 60 0b 02 1c 	\[MMI\]       ldfe\.nt1 f4=\[r5\],88
+    10c6:	40 00 14 0c 30 00 	            ldfe\.nta f4=\[r5\]
+    10cc:	00 00 04 00       	            nop\.i 0x0
+    10d0:	08 20 18 0a 06 1a 	\[MMI\]       ldfe\.nta f4=\[r5\],r6
+    10d6:	40 28 17 0c 38 00 	            ldfe\.nta f4=\[r5\],101
+    10dc:	00 00 04 00       	            nop\.i 0x0
+    10e0:	08 20 00 0a 20 18 	\[MMI\]       ldfe\.s f4=\[r5\]
+    10e6:	40 30 14 40 34 00 	            ldfe\.s f4=\[r5\],r6
+    10ec:	00 00 04 00       	            nop\.i 0x0
+    10f0:	08 20 c8 0b 20 1c 	\[MMI\]       ldfe\.s f4=\[r5\],114
+    10f6:	40 00 14 44 30 00 	            ldfe\.s\.nt1 f4=\[r5\]
+    10fc:	00 00 04 00       	            nop\.i 0x0
+    1100:	08 20 18 0a 22 1a 	\[MMI\]       ldfe\.s\.nt1 f4=\[r5\],r6
+    1106:	40 f8 17 44 38 00 	            ldfe\.s\.nt1 f4=\[r5\],127
+    110c:	00 00 04 00       	            nop\.i 0x0
+    1110:	08 20 00 0a 26 18 	\[MMI\]       ldfe\.s\.nta f4=\[r5\]
+    1116:	40 30 14 4c 34 00 	            ldfe\.s\.nta f4=\[r5\],r6
+    111c:	00 00 04 00       	            nop\.i 0x0
+    1120:	08 20 30 0a 27 1c 	\[MMI\]       ldfe\.s\.nta f4=\[r5\],140
+    1126:	40 00 14 80 30 00 	            ldfe\.a f4=\[r5\]
+    112c:	00 00 04 00       	            nop\.i 0x0
+    1130:	08 20 18 0a 40 1a 	\[MMI\]       ldfe\.a f4=\[r5\],r6
+    1136:	40 c8 14 82 38 00 	            ldfe\.a f4=\[r5\],153
+    113c:	00 00 04 00       	            nop\.i 0x0
+    1140:	08 20 00 0a 42 18 	\[MMI\]       ldfe\.a\.nt1 f4=\[r5\]
+    1146:	40 30 14 84 34 00 	            ldfe\.a\.nt1 f4=\[r5\],r6
+    114c:	00 00 04 00       	            nop\.i 0x0
+    1150:	08 20 98 0a 43 1c 	\[MMI\]       ldfe\.a\.nt1 f4=\[r5\],166
+    1156:	40 00 14 8c 30 00 	            ldfe\.a\.nta f4=\[r5\]
+    115c:	00 00 04 00       	            nop\.i 0x0
+    1160:	08 20 18 0a 46 1a 	\[MMI\]       ldfe\.a\.nta f4=\[r5\],r6
+    1166:	40 98 15 8e 38 00 	            ldfe\.a\.nta f4=\[r5\],179
+    116c:	00 00 04 00       	            nop\.i 0x0
+    1170:	08 20 00 0a 60 18 	\[MMI\]       ldfe\.sa f4=\[r5\]
+    1176:	40 30 14 c0 34 00 	            ldfe\.sa f4=\[r5\],r6
+    117c:	00 00 04 00       	            nop\.i 0x0
+    1180:	08 20 00 0b 61 1c 	\[MMI\]       ldfe\.sa f4=\[r5\],192
+    1186:	40 00 14 c4 30 00 	            ldfe\.sa\.nt1 f4=\[r5\]
+    118c:	00 00 04 00       	            nop\.i 0x0
+    1190:	08 20 18 0a 62 1a 	\[MMI\]       ldfe\.sa\.nt1 f4=\[r5\],r6
+    1196:	40 68 16 c6 38 00 	            ldfe\.sa\.nt1 f4=\[r5\],205
+    119c:	00 00 04 00       	            nop\.i 0x0
+    11a0:	08 20 00 0a 66 18 	\[MMI\]       ldfe\.sa\.nta f4=\[r5\]
+    11a6:	40 30 14 cc 34 00 	            ldfe\.sa\.nta f4=\[r5\],r6
+    11ac:	00 00 04 00       	            nop\.i 0x0
+    11b0:	08 20 68 0b 67 1c 	\[MMI\]       ldfe\.sa\.nta f4=\[r5\],218
+    11b6:	40 00 14 00 32 00 	            ldfe\.c\.clr f4=\[r5\]
+    11bc:	00 00 04 00       	            nop\.i 0x0
+    11c0:	08 20 18 0a 00 1b 	\[MMI\]       ldfe\.c\.clr f4=\[r5\],r6
+    11c6:	40 38 17 02 3a 00 	            ldfe\.c\.clr f4=\[r5\],231
+    11cc:	00 00 04 00       	            nop\.i 0x0
+    11d0:	08 20 00 0a 02 19 	\[MMI\]       ldfe\.c\.clr\.nt1 f4=\[r5\]
+    11d6:	40 30 14 04 36 00 	            ldfe\.c\.clr\.nt1 f4=\[r5\],r6
+    11dc:	00 00 04 00       	            nop\.i 0x0
+    11e0:	08 20 d0 0b 03 1d 	\[MMI\]       ldfe\.c\.clr\.nt1 f4=\[r5\],244
+    11e6:	40 00 14 0c 32 00 	            ldfe\.c\.clr\.nta f4=\[r5\]
+    11ec:	00 00 04 00       	            nop\.i 0x0
+    11f0:	08 20 18 0a 06 1b 	\[MMI\]       ldfe\.c\.clr\.nta f4=\[r5\],r6
+    11f6:	40 08 14 0c 3e 00 	            ldfe\.c\.clr\.nta f4=\[r5\],-255
+    11fc:	00 00 04 00       	            nop\.i 0x0
+    1200:	08 20 00 0a 20 19 	\[MMI\]       ldfe\.c\.nc f4=\[r5\]
+    1206:	40 30 14 40 36 00 	            ldfe\.c\.nc f4=\[r5\],r6
+    120c:	00 00 04 00       	            nop\.i 0x0
+    1210:	08 20 38 0a 20 1f 	\[MMI\]       ldfe\.c\.nc f4=\[r5\],-242
+    1216:	40 00 14 44 32 00 	            ldfe\.c\.nc\.nt1 f4=\[r5\]
+    121c:	00 00 04 00       	            nop\.i 0x0
+    1220:	08 20 18 0a 22 1b 	\[MMI\]       ldfe\.c\.nc\.nt1 f4=\[r5\],r6
+    1226:	40 d8 14 44 3e 00 	            ldfe\.c\.nc\.nt1 f4=\[r5\],-229
+    122c:	00 00 04 00       	            nop\.i 0x0
+    1230:	08 20 00 0a 26 19 	\[MMI\]       ldfe\.c\.nc\.nta f4=\[r5\]
+    1236:	40 30 14 4c 36 00 	            ldfe\.c\.nc\.nta f4=\[r5\],r6
+    123c:	00 00 04 00       	            nop\.i 0x0
+    1240:	08 20 a0 0a 26 1f 	\[MMI\]       ldfe\.c\.nc\.nta f4=\[r5\],-216
+    1246:	40 00 14 b0 31 00 	            ldf\.fill f4=\[r5\]
+    124c:	00 00 04 00       	            nop\.i 0x0
+    1250:	08 20 18 0a d8 1a 	\[MMI\]       ldf\.fill f4=\[r5\],r6
+    1256:	40 a8 15 b0 3d 00 	            ldf\.fill f4=\[r5\],-203
+    125c:	00 00 04 00       	            nop\.i 0x0
+    1260:	08 20 00 0a da 18 	\[MMI\]       ldf\.fill\.nt1 f4=\[r5\]
+    1266:	40 30 14 b4 35 00 	            ldf\.fill\.nt1 f4=\[r5\],r6
+    126c:	00 00 04 00       	            nop\.i 0x0
+    1270:	08 20 08 0b da 1e 	\[MMI\]       ldf\.fill\.nt1 f4=\[r5\],-190
+    1276:	40 00 14 bc 31 00 	            ldf\.fill\.nta f4=\[r5\]
+    127c:	00 00 04 00       	            nop\.i 0x0
+    1280:	08 20 18 0a de 1a 	\[MMI\]       ldf\.fill\.nta f4=\[r5\],r6
+    1286:	40 78 16 bc 3d 00 	            ldf\.fill\.nta f4=\[r5\],-177
+    128c:	00 00 04 00       	            nop\.i 0x0
+    1290:	08 00 14 08 90 19 	\[MMI\]       stfs \[r4\]=f5
+    1296:	c0 2d 10 20 3f 00 	            stfs \[r4\]=f5,-164
+    129c:	00 00 04 00       	            nop\.i 0x0
+    12a0:	08 00 14 08 96 19 	\[MMI\]       stfs\.nta \[r4\]=f5
+    12a6:	90 2e 10 2c 3f 00 	            stfs\.nta \[r4\]=f5,-151
+    12ac:	00 00 04 00       	            nop\.i 0x0
+    12b0:	08 00 14 08 98 19 	\[MMI\]       stfd \[r4\]=f5
+    12b6:	60 2f 10 30 3f 00 	            stfd \[r4\]=f5,-138
+    12bc:	00 00 04 00       	            nop\.i 0x0
+    12c0:	08 00 14 08 9e 19 	\[MMI\]       stfd\.nta \[r4\]=f5
+    12c6:	30 28 10 3e 3f 00 	            stfd\.nta \[r4\]=f5,-125
+    12cc:	00 00 04 00       	            nop\.i 0x0
+    12d0:	08 00 14 08 88 19 	\[MMI\]       stf8 \[r4\]=f5
+    12d6:	00 29 10 12 3f 00 	            stf8 \[r4\]=f5,-112
+    12dc:	00 00 04 00       	            nop\.i 0x0
+    12e0:	08 00 14 08 8e 19 	\[MMI\]       stf8\.nta \[r4\]=f5
+    12e6:	d0 29 10 1e 3f 00 	            stf8\.nta \[r4\]=f5,-99
+    12ec:	00 00 04 00       	            nop\.i 0x0
+    12f0:	08 00 14 08 80 19 	\[MMI\]       stfe \[r4\]=f5
+    12f6:	a0 2a 10 02 3f 00 	            stfe \[r4\]=f5,-86
+    12fc:	00 00 04 00       	            nop\.i 0x0
+    1300:	08 00 14 08 86 19 	\[MMI\]       stfe\.nta \[r4\]=f5
+    1306:	70 2b 10 0e 3f 00 	            stfe\.nta \[r4\]=f5,-73
+    130c:	00 00 04 00       	            nop\.i 0x0
+    1310:	08 00 14 08 d8 19 	\[MMI\]       stf\.spill \[r4\]=f5
+    1316:	40 2c 10 b2 3f 00 	            stf\.spill \[r4\]=f5,-60
+    131c:	00 00 04 00       	            nop\.i 0x0
+    1320:	08 00 14 08 de 19 	\[MMI\]       stf\.spill\.nta \[r4\]=f5
+    1326:	10 2d 10 be 3f 00 	            stf\.spill\.nta \[r4\]=f5,-47
+    132c:	00 00 04 00       	            nop\.i 0x0
+    1330:	08 20 14 0a 11 18 	\[MMI\]       ldfps f4,f5=\[r5\]
+    1336:	40 28 14 22 34 00 	            ldfps f4,f5=\[r5\],8
+    133c:	00 00 04 00       	            nop\.i 0x0
+    1340:	08 20 14 0a 13 18 	\[MMI\]       ldfps\.nt1 f4,f5=\[r5\]
+    1346:	40 28 14 26 34 00 	            ldfps\.nt1 f4,f5=\[r5\],8
+    134c:	00 00 04 00       	            nop\.i 0x0
+    1350:	08 20 14 0a 17 18 	\[MMI\]       ldfps\.nta f4,f5=\[r5\]
+    1356:	40 28 14 2e 34 00 	            ldfps\.nta f4,f5=\[r5\],8
+    135c:	00 00 04 00       	            nop\.i 0x0
+    1360:	08 20 14 0a 31 18 	\[MMI\]       ldfps\.s f4,f5=\[r5\]
+    1366:	40 28 14 62 34 00 	            ldfps\.s f4,f5=\[r5\],8
+    136c:	00 00 04 00       	            nop\.i 0x0
+    1370:	08 20 14 0a 33 18 	\[MMI\]       ldfps\.s\.nt1 f4,f5=\[r5\]
+    1376:	40 28 14 66 34 00 	            ldfps\.s\.nt1 f4,f5=\[r5\],8
+    137c:	00 00 04 00       	            nop\.i 0x0
+    1380:	08 20 14 0a 37 18 	\[MMI\]       ldfps\.s\.nta f4,f5=\[r5\]
+    1386:	40 28 14 6e 34 00 	            ldfps\.s\.nta f4,f5=\[r5\],8
+    138c:	00 00 04 00       	            nop\.i 0x0
+    1390:	08 20 14 0a 51 18 	\[MMI\]       ldfps\.a f4,f5=\[r5\]
+    1396:	40 28 14 a2 34 00 	            ldfps\.a f4,f5=\[r5\],8
+    139c:	00 00 04 00       	            nop\.i 0x0
+    13a0:	08 20 14 0a 53 18 	\[MMI\]       ldfps\.a\.nt1 f4,f5=\[r5\]
+    13a6:	40 28 14 a6 34 00 	            ldfps\.a\.nt1 f4,f5=\[r5\],8
+    13ac:	00 00 04 00       	            nop\.i 0x0
+    13b0:	08 20 14 0a 57 18 	\[MMI\]       ldfps\.a\.nta f4,f5=\[r5\]
+    13b6:	40 28 14 ae 34 00 	            ldfps\.a\.nta f4,f5=\[r5\],8
+    13bc:	00 00 04 00       	            nop\.i 0x0
+    13c0:	08 20 14 0a 71 18 	\[MMI\]       ldfps\.sa f4,f5=\[r5\]
+    13c6:	40 28 14 e2 34 00 	            ldfps\.sa f4,f5=\[r5\],8
+    13cc:	00 00 04 00       	            nop\.i 0x0
+    13d0:	08 20 14 0a 73 18 	\[MMI\]       ldfps\.sa\.nt1 f4,f5=\[r5\]
+    13d6:	40 28 14 e6 34 00 	            ldfps\.sa\.nt1 f4,f5=\[r5\],8
+    13dc:	00 00 04 00       	            nop\.i 0x0
+    13e0:	08 20 14 0a 77 18 	\[MMI\]       ldfps\.sa\.nta f4,f5=\[r5\]
+    13e6:	40 28 14 ee 34 00 	            ldfps\.sa\.nta f4,f5=\[r5\],8
+    13ec:	00 00 04 00       	            nop\.i 0x0
+    13f0:	08 20 14 0a 11 19 	\[MMI\]       ldfps\.c\.clr f4,f5=\[r5\]
+    13f6:	40 28 14 22 36 00 	            ldfps\.c\.clr f4,f5=\[r5\],8
+    13fc:	00 00 04 00       	            nop\.i 0x0
+    1400:	08 20 14 0a 13 19 	\[MMI\]       ldfps\.c\.clr\.nt1 f4,f5=\[r5\]
+    1406:	40 28 14 26 36 00 	            ldfps\.c\.clr\.nt1 f4,f5=\[r5\],8
+    140c:	00 00 04 00       	            nop\.i 0x0
+    1410:	08 20 14 0a 17 19 	\[MMI\]       ldfps\.c\.clr\.nta f4,f5=\[r5\]
+    1416:	40 28 14 2e 36 00 	            ldfps\.c\.clr\.nta f4,f5=\[r5\],8
+    141c:	00 00 04 00       	            nop\.i 0x0
+    1420:	08 20 14 0a 31 19 	\[MMI\]       ldfps\.c\.nc f4,f5=\[r5\]
+    1426:	40 28 14 62 36 00 	            ldfps\.c\.nc f4,f5=\[r5\],8
+    142c:	00 00 04 00       	            nop\.i 0x0
+    1430:	08 20 14 0a 33 19 	\[MMI\]       ldfps\.c\.nc\.nt1 f4,f5=\[r5\]
+    1436:	40 28 14 66 36 00 	            ldfps\.c\.nc\.nt1 f4,f5=\[r5\],8
+    143c:	00 00 04 00       	            nop\.i 0x0
+    1440:	08 20 14 0a 37 19 	\[MMI\]       ldfps\.c\.nc\.nta f4,f5=\[r5\]
+    1446:	40 28 14 6e 36 00 	            ldfps\.c\.nc\.nta f4,f5=\[r5\],8
+    144c:	00 00 04 00       	            nop\.i 0x0
+    1450:	08 20 14 0a 19 18 	\[MMI\]       ldfpd f4,f5=\[r5\]
+    1456:	40 28 14 32 34 00 	            ldfpd f4,f5=\[r5\],16
+    145c:	00 00 04 00       	            nop\.i 0x0
+    1460:	08 20 14 0a 1b 18 	\[MMI\]       ldfpd\.nt1 f4,f5=\[r5\]
+    1466:	40 28 14 36 34 00 	            ldfpd\.nt1 f4,f5=\[r5\],16
+    146c:	00 00 04 00       	            nop\.i 0x0
+    1470:	08 20 14 0a 1f 18 	\[MMI\]       ldfpd\.nta f4,f5=\[r5\]
+    1476:	40 28 14 3e 34 00 	            ldfpd\.nta f4,f5=\[r5\],16
+    147c:	00 00 04 00       	            nop\.i 0x0
+    1480:	08 20 14 0a 39 18 	\[MMI\]       ldfpd\.s f4,f5=\[r5\]
+    1486:	40 28 14 72 34 00 	            ldfpd\.s f4,f5=\[r5\],16
+    148c:	00 00 04 00       	            nop\.i 0x0
+    1490:	08 20 14 0a 3b 18 	\[MMI\]       ldfpd\.s\.nt1 f4,f5=\[r5\]
+    1496:	40 28 14 76 34 00 	            ldfpd\.s\.nt1 f4,f5=\[r5\],16
+    149c:	00 00 04 00       	            nop\.i 0x0
+    14a0:	08 20 14 0a 3f 18 	\[MMI\]       ldfpd\.s\.nta f4,f5=\[r5\]
+    14a6:	40 28 14 7e 34 00 	            ldfpd\.s\.nta f4,f5=\[r5\],16
+    14ac:	00 00 04 00       	            nop\.i 0x0
+    14b0:	08 20 14 0a 59 18 	\[MMI\]       ldfpd\.a f4,f5=\[r5\]
+    14b6:	40 28 14 b2 34 00 	            ldfpd\.a f4,f5=\[r5\],16
+    14bc:	00 00 04 00       	            nop\.i 0x0
+    14c0:	08 20 14 0a 5b 18 	\[MMI\]       ldfpd\.a\.nt1 f4,f5=\[r5\]
+    14c6:	40 28 14 b6 34 00 	            ldfpd\.a\.nt1 f4,f5=\[r5\],16
+    14cc:	00 00 04 00       	            nop\.i 0x0
+    14d0:	08 20 14 0a 5f 18 	\[MMI\]       ldfpd\.a\.nta f4,f5=\[r5\]
+    14d6:	40 28 14 be 34 00 	            ldfpd\.a\.nta f4,f5=\[r5\],16
+    14dc:	00 00 04 00       	            nop\.i 0x0
+    14e0:	08 20 14 0a 79 18 	\[MMI\]       ldfpd\.sa f4,f5=\[r5\]
+    14e6:	40 28 14 f2 34 00 	            ldfpd\.sa f4,f5=\[r5\],16
+    14ec:	00 00 04 00       	            nop\.i 0x0
+    14f0:	08 20 14 0a 7b 18 	\[MMI\]       ldfpd\.sa\.nt1 f4,f5=\[r5\]
+    14f6:	40 28 14 f6 34 00 	            ldfpd\.sa\.nt1 f4,f5=\[r5\],16
+    14fc:	00 00 04 00       	            nop\.i 0x0
+    1500:	08 20 14 0a 7f 18 	\[MMI\]       ldfpd\.sa\.nta f4,f5=\[r5\]
+    1506:	40 28 14 fe 34 00 	            ldfpd\.sa\.nta f4,f5=\[r5\],16
+    150c:	00 00 04 00       	            nop\.i 0x0
+    1510:	08 20 14 0a 19 19 	\[MMI\]       ldfpd\.c\.clr f4,f5=\[r5\]
+    1516:	40 28 14 32 36 00 	            ldfpd\.c\.clr f4,f5=\[r5\],16
+    151c:	00 00 04 00       	            nop\.i 0x0
+    1520:	08 20 14 0a 1b 19 	\[MMI\]       ldfpd\.c\.clr\.nt1 f4,f5=\[r5\]
+    1526:	40 28 14 36 36 00 	            ldfpd\.c\.clr\.nt1 f4,f5=\[r5\],16
+    152c:	00 00 04 00       	            nop\.i 0x0
+    1530:	08 20 14 0a 1f 19 	\[MMI\]       ldfpd\.c\.clr\.nta f4,f5=\[r5\]
+    1536:	40 28 14 3e 36 00 	            ldfpd\.c\.clr\.nta f4,f5=\[r5\],16
+    153c:	00 00 04 00       	            nop\.i 0x0
+    1540:	08 20 14 0a 39 19 	\[MMI\]       ldfpd\.c\.nc f4,f5=\[r5\]
+    1546:	40 28 14 72 36 00 	            ldfpd\.c\.nc f4,f5=\[r5\],16
+    154c:	00 00 04 00       	            nop\.i 0x0
+    1550:	08 20 14 0a 3b 19 	\[MMI\]       ldfpd\.c\.nc\.nt1 f4,f5=\[r5\]
+    1556:	40 28 14 76 36 00 	            ldfpd\.c\.nc\.nt1 f4,f5=\[r5\],16
+    155c:	00 00 04 00       	            nop\.i 0x0
+    1560:	08 20 14 0a 3f 19 	\[MMI\]       ldfpd\.c\.nc\.nta f4,f5=\[r5\]
+    1566:	40 28 14 7e 36 00 	            ldfpd\.c\.nc\.nta f4,f5=\[r5\],16
+    156c:	00 00 04 00       	            nop\.i 0x0
+    1570:	08 20 14 0a 09 18 	\[MMI\]       ldfp8 f4,f5=\[r5\]
+    1576:	40 28 14 12 34 00 	            ldfp8 f4,f5=\[r5\],16
+    157c:	00 00 04 00       	            nop\.i 0x0
+    1580:	08 20 14 0a 0b 18 	\[MMI\]       ldfp8\.nt1 f4,f5=\[r5\]
+    1586:	40 28 14 16 34 00 	            ldfp8\.nt1 f4,f5=\[r5\],16
+    158c:	00 00 04 00       	            nop\.i 0x0
+    1590:	08 20 14 0a 0f 18 	\[MMI\]       ldfp8\.nta f4,f5=\[r5\]
+    1596:	40 28 14 1e 34 00 	            ldfp8\.nta f4,f5=\[r5\],16
+    159c:	00 00 04 00       	            nop\.i 0x0
+    15a0:	08 20 14 0a 29 18 	\[MMI\]       ldfp8\.s f4,f5=\[r5\]
+    15a6:	40 28 14 52 34 00 	            ldfp8\.s f4,f5=\[r5\],16
+    15ac:	00 00 04 00       	            nop\.i 0x0
+    15b0:	08 20 14 0a 2b 18 	\[MMI\]       ldfp8\.s\.nt1 f4,f5=\[r5\]
+    15b6:	40 28 14 56 34 00 	            ldfp8\.s\.nt1 f4,f5=\[r5\],16
+    15bc:	00 00 04 00       	            nop\.i 0x0
+    15c0:	08 20 14 0a 2f 18 	\[MMI\]       ldfp8\.s\.nta f4,f5=\[r5\]
+    15c6:	40 28 14 5e 34 00 	            ldfp8\.s\.nta f4,f5=\[r5\],16
+    15cc:	00 00 04 00       	            nop\.i 0x0
+    15d0:	08 20 14 0a 49 18 	\[MMI\]       ldfp8\.a f4,f5=\[r5\]
+    15d6:	40 28 14 92 34 00 	            ldfp8\.a f4,f5=\[r5\],16
+    15dc:	00 00 04 00       	            nop\.i 0x0
+    15e0:	08 20 14 0a 4b 18 	\[MMI\]       ldfp8\.a\.nt1 f4,f5=\[r5\]
+    15e6:	40 28 14 96 34 00 	            ldfp8\.a\.nt1 f4,f5=\[r5\],16
+    15ec:	00 00 04 00       	            nop\.i 0x0
+    15f0:	08 20 14 0a 4f 18 	\[MMI\]       ldfp8\.a\.nta f4,f5=\[r5\]
+    15f6:	40 28 14 9e 34 00 	            ldfp8\.a\.nta f4,f5=\[r5\],16
+    15fc:	00 00 04 00       	            nop\.i 0x0
+    1600:	08 20 14 0a 69 18 	\[MMI\]       ldfp8\.sa f4,f5=\[r5\]
+    1606:	40 28 14 d2 34 00 	            ldfp8\.sa f4,f5=\[r5\],16
+    160c:	00 00 04 00       	            nop\.i 0x0
+    1610:	08 20 14 0a 6b 18 	\[MMI\]       ldfp8\.sa\.nt1 f4,f5=\[r5\]
+    1616:	40 28 14 d6 34 00 	            ldfp8\.sa\.nt1 f4,f5=\[r5\],16
+    161c:	00 00 04 00       	            nop\.i 0x0
+    1620:	08 20 14 0a 6f 18 	\[MMI\]       ldfp8\.sa\.nta f4,f5=\[r5\]
+    1626:	40 28 14 de 34 00 	            ldfp8\.sa\.nta f4,f5=\[r5\],16
+    162c:	00 00 04 00       	            nop\.i 0x0
+    1630:	08 20 14 0a 09 19 	\[MMI\]       ldfp8\.c\.clr f4,f5=\[r5\]
+    1636:	40 28 14 12 36 00 	            ldfp8\.c\.clr f4,f5=\[r5\],16
+    163c:	00 00 04 00       	            nop\.i 0x0
+    1640:	08 20 14 0a 0b 19 	\[MMI\]       ldfp8\.c\.clr\.nt1 f4,f5=\[r5\]
+    1646:	40 28 14 16 36 00 	            ldfp8\.c\.clr\.nt1 f4,f5=\[r5\],16
+    164c:	00 00 04 00       	            nop\.i 0x0
+    1650:	08 20 14 0a 0f 19 	\[MMI\]       ldfp8\.c\.clr\.nta f4,f5=\[r5\]
+    1656:	40 28 14 1e 36 00 	            ldfp8\.c\.clr\.nta f4,f5=\[r5\],16
+    165c:	00 00 04 00       	            nop\.i 0x0
+    1660:	08 20 14 0a 29 19 	\[MMI\]       ldfp8\.c\.nc f4,f5=\[r5\]
+    1666:	40 28 14 52 36 00 	            ldfp8\.c\.nc f4,f5=\[r5\],16
+    166c:	00 00 04 00       	            nop\.i 0x0
+    1670:	08 20 14 0a 2b 19 	\[MMI\]       ldfp8\.c\.nc\.nt1 f4,f5=\[r5\]
+    1676:	40 28 14 56 36 00 	            ldfp8\.c\.nc\.nt1 f4,f5=\[r5\],16
+    167c:	00 00 04 00       	            nop\.i 0x0
+    1680:	08 20 14 0a 2f 19 	\[MMI\]       ldfp8\.c\.nc\.nta f4,f5=\[r5\]
+    1686:	40 28 14 5e 36 00 	            ldfp8\.c\.nc\.nta f4,f5=\[r5\],16
+    168c:	00 00 04 00       	            nop\.i 0x0
+    1690:	08 00 00 08 60 19 	\[MMI\]       lfetch \[r4\]
+    1696:	00 28 10 c0 36 00 	            lfetch \[r4\],r5
+    169c:	00 00 04 00       	            nop\.i 0x0
+    16a0:	08 00 78 09 61 1f 	\[MMI\]       lfetch \[r4\],-34
+    16a6:	00 00 10 c4 32 00 	            lfetch\.nt1 \[r4\]
+    16ac:	00 00 04 00       	            nop\.i 0x0
+    16b0:	08 00 14 08 62 1b 	\[MMI\]       lfetch\.nt1 \[r4\],r5
+    16b6:	00 58 13 c6 3e 00 	            lfetch\.nt1 \[r4\],-21
+    16bc:	00 00 04 00       	            nop\.i 0x0
+    16c0:	08 00 00 08 64 19 	\[MMI\]       lfetch\.nt2 \[r4\]
+    16c6:	00 28 10 c8 36 00 	            lfetch\.nt2 \[r4\],r5
+    16cc:	00 00 04 00       	            nop\.i 0x0
+    16d0:	08 00 e0 09 65 1f 	\[MMI\]       lfetch\.nt2 \[r4\],-8
+    16d6:	00 00 10 cc 32 00 	            lfetch\.nta \[r4\]
+    16dc:	00 00 04 00       	            nop\.i 0x0
+    16e0:	08 00 14 08 66 1b 	\[MMI\]       lfetch\.nta \[r4\],r5
+    16e6:	00 28 10 cc 3a 00 	            lfetch\.nta \[r4\],5
+    16ec:	00 00 04 00       	            nop\.i 0x0
+    16f0:	08 00 00 08 70 19 	\[MMI\]       lfetch\.fault \[r4\]
+    16f6:	00 28 10 e0 36 00 	            lfetch\.fault \[r4\],r5
+    16fc:	00 00 04 00       	            nop\.i 0x0
+    1700:	08 00 48 08 70 1d 	\[MMI\]       lfetch\.fault \[r4\],18
+    1706:	00 00 10 e4 32 00 	            lfetch\.fault\.nt1 \[r4\]
+    170c:	00 00 04 00       	            nop\.i 0x0
+    1710:	08 00 14 08 72 1b 	\[MMI\]       lfetch\.fault\.nt1 \[r4\],r5
+    1716:	00 f8 10 e4 3a 00 	            lfetch\.fault\.nt1 \[r4\],31
+    171c:	00 00 04 00       	            nop\.i 0x0
+    1720:	08 00 00 08 74 19 	\[MMI\]       lfetch\.fault\.nt2 \[r4\]
+    1726:	00 28 10 e8 36 00 	            lfetch\.fault\.nt2 \[r4\],r5
+    172c:	00 00 04 00       	            nop\.i 0x0
+    1730:	08 00 b0 08 74 1d 	\[MMI\]       lfetch\.fault\.nt2 \[r4\],44
+    1736:	00 00 10 ec 32 00 	            lfetch\.fault\.nta \[r4\]
+    173c:	00 00 04 00       	            nop\.i 0x0
+    1740:	08 00 14 08 76 1b 	\[MMI\]       lfetch\.fault\.nta \[r4\],r5
+    1746:	00 c8 11 ec 3a 00 	            lfetch\.fault\.nta \[r4\],57
+    174c:	00 00 04 00       	            nop\.i 0x0
+    1750:	08 00 00 08 68 19 	\[MMI\]       lfetch\.excl \[r4\]
+    1756:	00 28 10 d0 36 00 	            lfetch\.excl \[r4\],r5
+    175c:	00 00 04 00       	            nop\.i 0x0
+    1760:	08 00 18 09 68 1d 	\[MMI\]       lfetch\.excl \[r4\],70
+    1766:	00 00 10 d4 32 00 	            lfetch\.excl\.nt1 \[r4\]
+    176c:	00 00 04 00       	            nop\.i 0x0
+    1770:	08 00 14 08 6a 1b 	\[MMI\]       lfetch\.excl\.nt1 \[r4\],r5
+    1776:	00 98 12 d4 3a 00 	            lfetch\.excl\.nt1 \[r4\],83
+    177c:	00 00 04 00       	            nop\.i 0x0
+    1780:	08 00 00 08 6c 19 	\[MMI\]       lfetch\.excl\.nt2 \[r4\]
+    1786:	00 28 10 d8 36 00 	            lfetch\.excl\.nt2 \[r4\],r5
+    178c:	00 00 04 00       	            nop\.i 0x0
+    1790:	08 00 80 09 6c 1d 	\[MMI\]       lfetch\.excl\.nt2 \[r4\],96
+    1796:	00 00 10 dc 32 00 	            lfetch\.excl\.nta \[r4\]
+    179c:	00 00 04 00       	            nop\.i 0x0
+    17a0:	08 00 14 08 6e 1b 	\[MMI\]       lfetch\.excl\.nta \[r4\],r5
+    17a6:	00 68 13 dc 3a 00 	            lfetch\.excl\.nta \[r4\],109
+    17ac:	00 00 04 00       	            nop\.i 0x0
+    17b0:	08 00 00 08 78 19 	\[MMI\]       lfetch\.fault\.excl \[r4\]
+    17b6:	00 28 10 f0 36 00 	            lfetch\.fault\.excl \[r4\],r5
+    17bc:	00 00 04 00       	            nop\.i 0x0
+    17c0:	08 00 e8 09 78 1d 	\[MMI\]       lfetch\.fault\.excl \[r4\],122
+    17c6:	00 00 10 f4 32 00 	            lfetch\.fault\.excl\.nt1 \[r4\]
+    17cc:	00 00 04 00       	            nop\.i 0x0
+    17d0:	08 00 14 08 7a 1b 	\[MMI\]       lfetch\.fault\.excl\.nt1 \[r4\],r5
+    17d6:	00 38 10 f6 3a 00 	            lfetch\.fault\.excl\.nt1 \[r4\],135
+    17dc:	00 00 04 00       	            nop\.i 0x0
+    17e0:	08 00 00 08 7c 19 	\[MMI\]       lfetch\.fault\.excl\.nt2 \[r4\]
+    17e6:	00 28 10 f8 36 00 	            lfetch\.fault\.excl\.nt2 \[r4\],r5
+    17ec:	00 00 04 00       	            nop\.i 0x0
+    17f0:	08 00 50 08 7d 1d 	\[MMI\]       lfetch\.fault\.excl\.nt2 \[r4\],148
+    17f6:	00 00 10 fc 32 00 	            lfetch\.fault\.excl\.nta \[r4\]
+    17fc:	00 00 04 00       	            nop\.i 0x0
+    1800:	08 00 14 08 7e 1b 	\[MMI\]       lfetch\.fault\.excl\.nta \[r4\],r5
+    1806:	00 08 11 fe 3a 00 	            lfetch\.fault\.excl\.nta \[r4\],161
+    180c:	00 00 04 00       	            nop\.i 0x0
+    1810:	08 20 18 0a 01 10 	\[MMI\]       cmpxchg1\.acq r4=\[r5\],r6,ar\.ccv
+    1816:	40 30 14 06 20 00 	            cmpxchg1\.acq\.nt1 r4=\[r5\],r6,ar\.ccv
+    181c:	00 00 04 00       	            nop\.i 0x0
+    1820:	08 20 18 0a 07 10 	\[MMI\]       cmpxchg1\.acq\.nta r4=\[r5\],r6,ar\.ccv
+    1826:	40 30 14 42 20 00 	            cmpxchg1\.rel r4=\[r5\],r6,ar\.ccv
+    182c:	00 00 04 00       	            nop\.i 0x0
+    1830:	08 20 18 0a 23 10 	\[MMI\]       cmpxchg1\.rel\.nt1 r4=\[r5\],r6,ar\.ccv
+    1836:	40 30 14 4e 20 00 	            cmpxchg1\.rel\.nta r4=\[r5\],r6,ar\.ccv
+    183c:	00 00 04 00       	            nop\.i 0x0
+    1840:	08 20 18 0a 09 10 	\[MMI\]       cmpxchg2\.acq r4=\[r5\],r6,ar\.ccv
+    1846:	40 30 14 16 20 00 	            cmpxchg2\.acq\.nt1 r4=\[r5\],r6,ar\.ccv
+    184c:	00 00 04 00       	            nop\.i 0x0
+    1850:	08 20 18 0a 0f 10 	\[MMI\]       cmpxchg2\.acq\.nta r4=\[r5\],r6,ar\.ccv
+    1856:	40 30 14 52 20 00 	            cmpxchg2\.rel r4=\[r5\],r6,ar\.ccv
+    185c:	00 00 04 00       	            nop\.i 0x0
+    1860:	08 20 18 0a 2b 10 	\[MMI\]       cmpxchg2\.rel\.nt1 r4=\[r5\],r6,ar\.ccv
+    1866:	40 30 14 5e 20 00 	            cmpxchg2\.rel\.nta r4=\[r5\],r6,ar\.ccv
+    186c:	00 00 04 00       	            nop\.i 0x0
+    1870:	08 20 18 0a 11 10 	\[MMI\]       cmpxchg4\.acq r4=\[r5\],r6,ar\.ccv
+    1876:	40 30 14 26 20 00 	            cmpxchg4\.acq\.nt1 r4=\[r5\],r6,ar\.ccv
+    187c:	00 00 04 00       	            nop\.i 0x0
+    1880:	08 20 18 0a 17 10 	\[MMI\]       cmpxchg4\.acq\.nta r4=\[r5\],r6,ar\.ccv
+    1886:	40 30 14 62 20 00 	            cmpxchg4\.rel r4=\[r5\],r6,ar\.ccv
+    188c:	00 00 04 00       	            nop\.i 0x0
+    1890:	08 20 18 0a 33 10 	\[MMI\]       cmpxchg4\.rel\.nt1 r4=\[r5\],r6,ar\.ccv
+    1896:	40 30 14 6e 20 00 	            cmpxchg4\.rel\.nta r4=\[r5\],r6,ar\.ccv
+    189c:	00 00 04 00       	            nop\.i 0x0
+    18a0:	08 20 18 0a 19 10 	\[MMI\]       cmpxchg8\.acq r4=\[r5\],r6,ar\.ccv
+    18a6:	40 30 14 36 20 00 	            cmpxchg8\.acq\.nt1 r4=\[r5\],r6,ar\.ccv
+    18ac:	00 00 04 00       	            nop\.i 0x0
+    18b0:	08 20 18 0a 1f 10 	\[MMI\]       cmpxchg8\.acq\.nta r4=\[r5\],r6,ar\.ccv
+    18b6:	40 30 14 72 20 00 	            cmpxchg8\.rel r4=\[r5\],r6,ar\.ccv
+    18bc:	00 00 04 00       	            nop\.i 0x0
+    18c0:	08 20 18 0a 3b 10 	\[MMI\]       cmpxchg8\.rel\.nt1 r4=\[r5\],r6,ar\.ccv
+    18c6:	40 30 14 7e 20 00 	            cmpxchg8\.rel\.nta r4=\[r5\],r6,ar\.ccv
+    18cc:	00 00 04 00       	            nop\.i 0x0
+    18d0:	08 20 18 0a 41 10 	\[MMI\]       xchg1 r4=\[r5\],r6
+    18d6:	40 30 14 86 20 00 	            xchg1\.nt1 r4=\[r5\],r6
+    18dc:	00 00 04 00       	            nop\.i 0x0
+    18e0:	08 20 18 0a 47 10 	\[MMI\]       xchg1\.nta r4=\[r5\],r6
+    18e6:	40 30 14 92 20 00 	            xchg2 r4=\[r5\],r6
+    18ec:	00 00 04 00       	            nop\.i 0x0
+    18f0:	08 20 18 0a 4b 10 	\[MMI\]       xchg2\.nt1 r4=\[r5\],r6
+    18f6:	40 30 14 9e 20 00 	            xchg2\.nta r4=\[r5\],r6
+    18fc:	00 00 04 00       	            nop\.i 0x0
+    1900:	08 20 18 0a 51 10 	\[MMI\]       xchg4 r4=\[r5\],r6
+    1906:	40 30 14 a6 20 00 	            xchg4\.nt1 r4=\[r5\],r6
+    190c:	00 00 04 00       	            nop\.i 0x0
+    1910:	08 20 18 0a 57 10 	\[MMI\]       xchg4\.nta r4=\[r5\],r6
+    1916:	40 30 14 b2 20 00 	            xchg8 r4=\[r5\],r6
+    191c:	00 00 04 00       	            nop\.i 0x0
+    1920:	08 20 18 0a 5b 10 	\[MMI\]       xchg8\.nt1 r4=\[r5\],r6
+    1926:	40 30 14 be 20 00 	            xchg8\.nta r4=\[r5\],r6
+    192c:	00 00 04 00       	            nop\.i 0x0
+    1930:	08 20 10 0a 91 10 	\[MMI\]       fetchadd4\.acq r4=\[r5\],-16
+    1936:	40 28 14 26 21 00 	            fetchadd4\.acq\.nt1 r4=\[r5\],-8
+    193c:	00 00 04 00       	            nop\.i 0x0
+    1940:	08 20 18 0a 97 10 	\[MMI\]       fetchadd4\.acq\.nta r4=\[r5\],-4
+    1946:	40 38 14 32 21 00 	            fetchadd8\.acq r4=\[r5\],-1
+    194c:	00 00 04 00       	            nop\.i 0x0
+    1950:	08 20 0c 0a 9b 10 	\[MMI\]       fetchadd8\.acq\.nt1 r4=\[r5\],1
+    1956:	40 10 14 3e 21 00 	            fetchadd8\.acq\.nta r4=\[r5\],4
+    195c:	00 00 04 00       	            nop\.i 0x0
+    1960:	08 20 04 0a b1 10 	\[MMI\]       fetchadd4\.rel r4=\[r5\],8
+    1966:	40 00 14 66 21 00 	            fetchadd4\.rel\.nt1 r4=\[r5\],16
+    196c:	00 00 04 00       	            nop\.i 0x0
+    1970:	08 20 10 0a b7 10 	\[MMI\]       fetchadd4\.rel\.nta r4=\[r5\],-16
+    1976:	40 28 14 72 21 00 	            fetchadd8\.rel r4=\[r5\],-8
+    197c:	00 00 04 00       	            nop\.i 0x0
+    1980:	08 20 18 0a bb 10 	\[MMI\]       fetchadd8\.rel\.nt1 r4=\[r5\],-4
+    1986:	40 38 14 7e 21 00 	            fetchadd8\.rel\.nta r4=\[r5\],-1
+    198c:	00 00 04 00       	            nop\.i 0x0
+    1990:	08 20 14 00 e1 18 	\[MMI\]       setf\.sig f4=r5
+    1996:	40 28 00 d2 31 00 	            setf\.exp f4=r5
+    199c:	00 00 04 00       	            nop\.i 0x0
+    19a0:	08 20 14 00 f1 18 	\[MMI\]       setf\.s f4=r5
+    19a6:	40 28 00 f2 31 00 	            setf\.d f4=r5
+    19ac:	00 00 04 00       	            nop\.i 0x0
+    19b0:	08 20 14 00 e1 10 	\[MMI\]       getf\.sig r4=f5
+    19b6:	40 28 00 d2 21 00 	            getf\.exp r4=f5
+    19bc:	00 00 04 00       	            nop\.i 0x0
+    19c0:	08 20 14 00 f1 10 	\[MMI\]       getf\.s r4=f5
+    19c6:	40 28 00 f2 21 00 	            getf\.d r4=f5
+    19cc:	00 00 04 00       	            nop\.i 0x0
+    19d0:	08 18 13 f8 7f 06 	\[MMI\]       chk\.s\.m r4,0 <_start>
+    19d6:	30 26 f0 ff 0d 00 	            chk\.s f4,0 <_start>
+    19dc:	00 00 04 00       	            nop\.i 0x0
+    19e0:	08 20 88 f9 3f 03 	\[MMI\]       chk\.a\.nc r4,0 <_start>
+    19e6:	40 10 f3 ff 06 00 	            chk\.a\.clr r4,0 <_start>
+    19ec:	00 00 04 00       	            nop\.i 0x0
+    19f0:	08 20 84 f9 bf 03 	\[MMI\]       chk\.a\.nc f4,0 <_start>
+    19f6:	40 08 f3 ff 07 00 	            chk\.a\.clr f4,0 <_start>
+    19fc:	00 00 04 00       	            nop\.i 0x0
+    1a00:	08 00 00 00 10 00 	\[MMI\]       invala
+    1a06:	00 00 00 40 00 00 	            fwb
+    1a0c:	00 00 04 00       	            nop\.i 0x0
+    1a10:	08 00 00 00 22 00 	\[MMI\]       mf
+    1a16:	00 00 00 46 00 00 	            mf\.a
+    1a1c:	00 00 04 00       	            nop\.i 0x0
+    1a20:	08 00 00 00 30 00 	\[MMI\]       srlz\.d
+    1a26:	00 00 00 62 00 00 	            srlz\.i
+    1a2c:	00 00 04 00       	            nop\.i 0x0
+    1a30:	09 00 00 00 33 00 	\[MMI\]       sync\.i
+    1a36:	00 00 00 02 00 00 	            nop\.m 0x0
+    1a3c:	00 00 04 00       	            nop\.i 0x0;;
+    1a40:	01 20 70 18 82 05 	\[MII\]       alloc r4=ar\.pfs,28,12,16
+    1a46:	00 00 00 02 00 00 	            nop\.i 0x0
+    1a4c:	00 00 04 00       	            nop\.i 0x0;;
+    1a50:	01 00 00 00 0c 00 	\[MII\]       flushrs
+    1a56:	00 00 00 02 00 00 	            nop\.i 0x0
+    1a5c:	00 00 04 00       	            nop\.i 0x0;;
+    1a60:	00 00 00 00 0a 00 	\[MII\]       loadrs
+    1a66:	00 00 00 02 00 00 	            nop\.i 0x0
+    1a6c:	00 00 04 00       	            nop\.i 0x0
+    1a70:	08 20 00 00 12 00 	\[MMI\]       invala\.e r4
+    1a76:	40 00 00 26 00 00 	            invala\.e f4
+    1a7c:	00 00 04 00       	            nop\.i 0x0
+    1a80:	08 00 00 08 30 04 	\[MMI\]       fc r4
+    1a86:	00 00 10 68 08 00 	            ptc\.e r4
+    1a8c:	00 00 04 00       	            nop\.i 0x0
+    1a90:	08 00 00 00 00 00 	\[MMI\]       break\.m 0x0
+    1a96:	f0 ff 1f 00 00 00 	            break\.m 0x1ffff
+    1a9c:	00 00 04 00       	            nop\.i 0x0
+    1aa0:	08 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    1aa6:	f0 ff 1f 00 00 00 	            break\.m 0x1ffff
+    1aac:	00 00 04 00       	            nop\.i 0x0
+    1ab0:	08 20 18 0a 38 04 	\[MMI\]       probe\.r r4=r5,r6
+    1ab6:	40 30 14 72 08 00 	            probe\.w r4=r5,r6
+    1abc:	00 00 04 00       	            nop\.i 0x0
+    1ac0:	08 20 00 0a 18 04 	\[MMI\]       probe\.r r4=r5,0
+    1ac6:	40 08 14 32 08 00 	            probe\.w r4=r5,1
+    1acc:	00 00 04 00       	            nop\.i 0x0
+    1ad0:	08 00 08 06 32 04 	\[MMI\]       probe\.r\.fault r3,2
+    1ad6:	00 18 0c 66 08 00 	            probe\.w\.fault r3,3
+    1adc:	00 00 04 00       	            nop\.i 0x0
+    1ae0:	08 00 00 06 31 04 	\[MMI\]       probe\.rw\.fault r3,0
+    1ae6:	00 00 00 02 00 00 	            nop\.m 0x0
+    1aec:	00 00 04 00       	            nop\.i 0x0
+    1af0:	0b 00 20 00 2e 04 	\[MMI\]       itc\.d r8;;
+    1af6:	00 00 00 02 00 00 	            nop\.m 0x0
+    1afc:	00 00 04 00       	            nop\.i 0x0;;
+    1b00:	0a 00 24 00 2f 04 	\[MMI\]       itc\.i r9;;
+    1b06:	40 23 01 08 00 00 	            sum 0x1234
+    1b0c:	00 00 04 00       	            nop\.i 0x0
+    1b10:	08 50 55 d5 25 00 	\[MMI\]       rum 0x5aaaaa
+    1b16:	f0 ff ff 6d 04 00 	            ssm 0xffffff
+    1b1c:	00 00 04 00       	            nop\.i 0x0
+    1b20:	08 00 00 00 27 00 	\[MMI\]       rsm 0x400000
+    1b26:	00 28 10 12 08 00 	            ptc\.l r4,r5
+    1b2c:	00 00 04 00       	            nop\.i 0x0
+    1b30:	0a 00 14 08 0a 04 	\[MMI\]       ptc\.g r4,r5;;
+    1b36:	00 00 00 02 00 00 	            nop\.m 0x0
+    1b3c:	00 00 04 00       	            nop\.i 0x0
+    1b40:	0a 00 14 08 0b 04 	\[MMI\]       ptc\.ga r4,r5;;
+    1b46:	00 00 00 02 00 00 	            nop\.m 0x0
+    1b4c:	00 00 04 00       	            nop\.i 0x0
+    1b50:	08 00 14 08 0c 04 	\[MMI\]       ptr\.d r4,r5
+    1b56:	00 28 10 1a 08 00 	            ptr\.i r4,r5
+    1b5c:	00 00 04 00       	            nop\.i 0x0
+    1b60:	08 20 00 0a 1a 04 	\[MMI\]       thash r4=r5
+    1b66:	40 00 14 36 08 00 	            ttag r4=r5
+    1b6c:	00 00 04 00       	            nop\.i 0x0
+    1b70:	09 20 00 0a 1e 04 	\[MMI\]       tpa r4=r5
+    1b76:	40 00 14 3e 08 00 	            tak r4=r5
+    1b7c:	00 00 04 00       	            nop\.i 0x0;;
diff --git a/gas/testsuite/gas/ia64/opc-m.pl b/gas/testsuite/gas/ia64/opc-m.pl
new file mode 100644
index 0000000..93c7bc9
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-m.pl
@@ -0,0 +1,218 @@
+print ".text\n\t.type _start,@", "function\n_start:\n\n";
+
+@ldhint = ( "", ".nt1", ".nta" );
+@ldspec = ( "", ".s", ".a", ".sa", ".c.clr", ".c.nc" );
+@sthint = ( "", ".nta" );
+
+$i = 0;
+
+# Integer Load
+
+foreach $s ( "1", "2", "4", "8" ) {
+  foreach $e (@ldspec, ".bias", ".acq", ".c.clr.acq") {
+    foreach $l (@ldhint) {
+      print "\tld${s}${e}${l} r4 = [r5]\n";
+      print "\tld${s}${e}${l} r4 = [r5], r6\n";
+      print "\tld${s}${e}${l} r4 = [r5], ", $i - 256, "\n";
+      $i = ($i + 13) % 512;
+    }
+    print "\n";
+  }
+}
+
+# Integer Fill
+
+for $l (@ldhint) {
+  print "\tld8.fill${l} r4 = [r5]\n";
+  print "\tld8.fill${l} r4 = [r5], r6\n";
+  print "\tld8.fill${l} r4 = [r5], ", $i - 256, "\n";
+  $i = ($i + 13) % 512;
+}
+print "\n";
+
+# Integer Store
+
+foreach $s ("1", "2", "4", "8", "1.rel", "2.rel", "4.rel", "8.rel", "8.spill") {
+  for $l (@sthint) {
+    print "\tst${s}${l} [r4] = r5\n";
+    print "\tst${s}${l} [r4] = r5, ", $i - 256, "\n";
+    $i = ($i + 13) % 512;
+  }
+  print "\n";
+}
+
+# Floating Point Load
+
+foreach $s ( "fs", "fd", "f8", "fe" ) {
+  foreach $e (@ldspec) {
+    foreach $l (@ldhint) {
+      print "\tld${s}${e}${l} f4 = [r5]\n";
+      print "\tld${s}${e}${l} f4 = [r5], r6\n";
+      print "\tld${s}${e}${l} f4 = [r5], ", $i - 256, "\n";
+      $i = ($i + 13) % 512;
+    }
+    print "\n";
+  }
+}
+
+# Floating Point Fill
+
+for $l (@ldhint) {
+  print "\tldf.fill${l} f4 = [r5]\n";
+  print "\tldf.fill${l} f4 = [r5], r6\n";
+  print "\tldf.fill${l} f4 = [r5], ", $i - 256, "\n";
+  $i = ($i + 13) % 512;
+}
+print "\n";
+
+# Floating Point Store
+
+foreach $s ( "fs", "fd", "f8", "fe", "f.spill" ) {
+  for $l (@sthint) {
+    print "\tst${s}${l} [r4] = f5\n";
+    print "\tst${s}${l} [r4] = f5, ", $i - 256, "\n";
+    $i = ($i + 13) % 512;
+  }
+  print "\n";
+}
+
+# Floating Point Load Pair
+
+foreach $s ( "fps", "fpd", "fp8" ) {
+  foreach $e (@ldspec) {
+    foreach $l (@ldhint) {
+      print "\tld${s}${e}${l} f4, f5 = [r5]\n";
+      print "\tld${s}${e}${l} f4, f5 = [r5], ", ($s eq "fps" ? 8 : 16), "\n";
+    }
+    print "\n";
+  }
+}
+
+# Line Prefetch
+
+@lfhint = ( "", ".nt1", ".nt2", ".nta" );
+
+foreach $e ( "", ".excl" ) {
+  foreach $f ( "", ".fault" ) {
+    foreach $h (@lfhint) {
+      print "\tlfetch${f}${e}${h} [r4]\n";
+      print "\tlfetch${f}${e}${h} [r4], r5\n";
+      print "\tlfetch${f}${e}${h} [r4], ", $i - 256, "\n";
+      $i = ($i + 13) % 512;
+    }
+    print "\n";
+  }
+}
+
+# Compare and Exchange
+
+foreach $s ( "1", "2", "4", "8" ) {
+  foreach $e ( ".acq", ".rel" ) {
+    foreach $h (@ldhint) {
+      print "\tcmpxchg${s}${e}${h} r4 = [r5], r6, ar.ccv\n";
+    }
+    print "\n";
+  }
+}
+
+# Exchange
+
+foreach $s ( "1", "2", "4", "8" ) {
+  foreach $h (@ldhint) {
+    print "\txchg${s}${h} r4 = [r5], r6\n";
+  }
+  print "\n";
+}
+
+# Fetch and Add
+
+$i = 0;
+@inc3 = ( -16, -8, -4, -1, 1, 4, 8, 16 );
+foreach $s ( "4.acq", "8.acq", "4.rel", "8.rel" ) {
+  foreach $h (@ldhint) {
+    print "\tfetchadd${s}${h} r4 = [r5], ", $inc3[$i], "\n";
+    $i = ($i + 1) % 8;
+  }
+  print "\n";
+}
+
+# Get/Set FR
+
+foreach $e ( ".sig", ".exp", ".s", ".d" ) {
+  print "\tsetf${e} f4 = r5\n";
+}
+print "\n";
+
+foreach $e ( ".sig", ".exp", ".s", ".d" ) {
+  print "\tgetf${e} r4 = f5\n";
+}
+print "\n";
+
+# Speculation and Advanced Load Checkso
+
+print <<END
+	chk.s.m r4, _start
+	chk.s f4, _start
+	chk.a.nc r4, _start
+	chk.a.clr r4, _start
+	chk.a.nc f4, _start
+	chk.a.clr f4, _start
+
+	invala
+	fwb
+	mf
+	mf.a
+	srlz.d
+	srlz.i
+	sync.i
+	nop.m 0
+	nop.i 0
+
+	{ .mii; alloc r4 = ar.pfs, 2, 10, 16, 16 }
+
+	{ .mii; flushrs }
+	{ .mii; loadrs }
+
+	invala.e r4
+	invala.e f4
+
+	fc r4
+	ptc.e r4
+
+	break.m 0
+	break.m 0x1ffff
+
+	nop.m 0
+	break.m 0x1ffff
+
+	probe.r r4 = r5, r6
+	probe.w r4 = r5, r6
+
+	probe.r r4 = r5, 0
+	probe.w r4 = r5, 1
+
+	probe.r.fault r3, 2
+	probe.w.fault r3, 3
+	probe.rw.fault r3, 0
+
+	itc.d r8
+	itc.i r9
+
+	sum 0x1234
+	rum 0x5aaaaa
+	ssm 0xffffff
+	rsm 0x400000
+
+	ptc.l r4, r5
+	ptc.g r4, r5
+	ptc.ga r4, r5
+	ptr.d r4, r5
+	ptr.i r4, r5
+
+	thash r4 = r5
+	ttag r4 = r5
+	tpa r4 = r5
+	tak r4 = r5
+
+END
+;
diff --git a/gas/testsuite/gas/ia64/opc-m.s b/gas/testsuite/gas/ia64/opc-m.s
new file mode 100644
index 0000000..fa6e66a
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-m.s
@@ -0,0 +1,1009 @@
+.text
+	.type _start,@function
+_start:
+
+	ld1 r4 = [r5]
+	ld1 r4 = [r5], r6
+	ld1 r4 = [r5], -256
+	ld1.nt1 r4 = [r5]
+	ld1.nt1 r4 = [r5], r6
+	ld1.nt1 r4 = [r5], -243
+	ld1.nta r4 = [r5]
+	ld1.nta r4 = [r5], r6
+	ld1.nta r4 = [r5], -230
+
+	ld1.s r4 = [r5]
+	ld1.s r4 = [r5], r6
+	ld1.s r4 = [r5], -217
+	ld1.s.nt1 r4 = [r5]
+	ld1.s.nt1 r4 = [r5], r6
+	ld1.s.nt1 r4 = [r5], -204
+	ld1.s.nta r4 = [r5]
+	ld1.s.nta r4 = [r5], r6
+	ld1.s.nta r4 = [r5], -191
+
+	ld1.a r4 = [r5]
+	ld1.a r4 = [r5], r6
+	ld1.a r4 = [r5], -178
+	ld1.a.nt1 r4 = [r5]
+	ld1.a.nt1 r4 = [r5], r6
+	ld1.a.nt1 r4 = [r5], -165
+	ld1.a.nta r4 = [r5]
+	ld1.a.nta r4 = [r5], r6
+	ld1.a.nta r4 = [r5], -152
+
+	ld1.sa r4 = [r5]
+	ld1.sa r4 = [r5], r6
+	ld1.sa r4 = [r5], -139
+	ld1.sa.nt1 r4 = [r5]
+	ld1.sa.nt1 r4 = [r5], r6
+	ld1.sa.nt1 r4 = [r5], -126
+	ld1.sa.nta r4 = [r5]
+	ld1.sa.nta r4 = [r5], r6
+	ld1.sa.nta r4 = [r5], -113
+
+	ld1.c.clr r4 = [r5]
+	ld1.c.clr r4 = [r5], r6
+	ld1.c.clr r4 = [r5], -100
+	ld1.c.clr.nt1 r4 = [r5]
+	ld1.c.clr.nt1 r4 = [r5], r6
+	ld1.c.clr.nt1 r4 = [r5], -87
+	ld1.c.clr.nta r4 = [r5]
+	ld1.c.clr.nta r4 = [r5], r6
+	ld1.c.clr.nta r4 = [r5], -74
+
+	ld1.c.nc r4 = [r5]
+	ld1.c.nc r4 = [r5], r6
+	ld1.c.nc r4 = [r5], -61
+	ld1.c.nc.nt1 r4 = [r5]
+	ld1.c.nc.nt1 r4 = [r5], r6
+	ld1.c.nc.nt1 r4 = [r5], -48
+	ld1.c.nc.nta r4 = [r5]
+	ld1.c.nc.nta r4 = [r5], r6
+	ld1.c.nc.nta r4 = [r5], -35
+
+	ld1.bias r4 = [r5]
+	ld1.bias r4 = [r5], r6
+	ld1.bias r4 = [r5], -22
+	ld1.bias.nt1 r4 = [r5]
+	ld1.bias.nt1 r4 = [r5], r6
+	ld1.bias.nt1 r4 = [r5], -9
+	ld1.bias.nta r4 = [r5]
+	ld1.bias.nta r4 = [r5], r6
+	ld1.bias.nta r4 = [r5], 4
+
+	ld1.acq r4 = [r5]
+	ld1.acq r4 = [r5], r6
+	ld1.acq r4 = [r5], 17
+	ld1.acq.nt1 r4 = [r5]
+	ld1.acq.nt1 r4 = [r5], r6
+	ld1.acq.nt1 r4 = [r5], 30
+	ld1.acq.nta r4 = [r5]
+	ld1.acq.nta r4 = [r5], r6
+	ld1.acq.nta r4 = [r5], 43
+
+	ld1.c.clr.acq r4 = [r5]
+	ld1.c.clr.acq r4 = [r5], r6
+	ld1.c.clr.acq r4 = [r5], 56
+	ld1.c.clr.acq.nt1 r4 = [r5]
+	ld1.c.clr.acq.nt1 r4 = [r5], r6
+	ld1.c.clr.acq.nt1 r4 = [r5], 69
+	ld1.c.clr.acq.nta r4 = [r5]
+	ld1.c.clr.acq.nta r4 = [r5], r6
+	ld1.c.clr.acq.nta r4 = [r5], 82
+
+	ld2 r4 = [r5]
+	ld2 r4 = [r5], r6
+	ld2 r4 = [r5], 95
+	ld2.nt1 r4 = [r5]
+	ld2.nt1 r4 = [r5], r6
+	ld2.nt1 r4 = [r5], 108
+	ld2.nta r4 = [r5]
+	ld2.nta r4 = [r5], r6
+	ld2.nta r4 = [r5], 121
+
+	ld2.s r4 = [r5]
+	ld2.s r4 = [r5], r6
+	ld2.s r4 = [r5], 134
+	ld2.s.nt1 r4 = [r5]
+	ld2.s.nt1 r4 = [r5], r6
+	ld2.s.nt1 r4 = [r5], 147
+	ld2.s.nta r4 = [r5]
+	ld2.s.nta r4 = [r5], r6
+	ld2.s.nta r4 = [r5], 160
+
+	ld2.a r4 = [r5]
+	ld2.a r4 = [r5], r6
+	ld2.a r4 = [r5], 173
+	ld2.a.nt1 r4 = [r5]
+	ld2.a.nt1 r4 = [r5], r6
+	ld2.a.nt1 r4 = [r5], 186
+	ld2.a.nta r4 = [r5]
+	ld2.a.nta r4 = [r5], r6
+	ld2.a.nta r4 = [r5], 199
+
+	ld2.sa r4 = [r5]
+	ld2.sa r4 = [r5], r6
+	ld2.sa r4 = [r5], 212
+	ld2.sa.nt1 r4 = [r5]
+	ld2.sa.nt1 r4 = [r5], r6
+	ld2.sa.nt1 r4 = [r5], 225
+	ld2.sa.nta r4 = [r5]
+	ld2.sa.nta r4 = [r5], r6
+	ld2.sa.nta r4 = [r5], 238
+
+	ld2.c.clr r4 = [r5]
+	ld2.c.clr r4 = [r5], r6
+	ld2.c.clr r4 = [r5], 251
+	ld2.c.clr.nt1 r4 = [r5]
+	ld2.c.clr.nt1 r4 = [r5], r6
+	ld2.c.clr.nt1 r4 = [r5], -248
+	ld2.c.clr.nta r4 = [r5]
+	ld2.c.clr.nta r4 = [r5], r6
+	ld2.c.clr.nta r4 = [r5], -235
+
+	ld2.c.nc r4 = [r5]
+	ld2.c.nc r4 = [r5], r6
+	ld2.c.nc r4 = [r5], -222
+	ld2.c.nc.nt1 r4 = [r5]
+	ld2.c.nc.nt1 r4 = [r5], r6
+	ld2.c.nc.nt1 r4 = [r5], -209
+	ld2.c.nc.nta r4 = [r5]
+	ld2.c.nc.nta r4 = [r5], r6
+	ld2.c.nc.nta r4 = [r5], -196
+
+	ld2.bias r4 = [r5]
+	ld2.bias r4 = [r5], r6
+	ld2.bias r4 = [r5], -183
+	ld2.bias.nt1 r4 = [r5]
+	ld2.bias.nt1 r4 = [r5], r6
+	ld2.bias.nt1 r4 = [r5], -170
+	ld2.bias.nta r4 = [r5]
+	ld2.bias.nta r4 = [r5], r6
+	ld2.bias.nta r4 = [r5], -157
+
+	ld2.acq r4 = [r5]
+	ld2.acq r4 = [r5], r6
+	ld2.acq r4 = [r5], -144
+	ld2.acq.nt1 r4 = [r5]
+	ld2.acq.nt1 r4 = [r5], r6
+	ld2.acq.nt1 r4 = [r5], -131
+	ld2.acq.nta r4 = [r5]
+	ld2.acq.nta r4 = [r5], r6
+	ld2.acq.nta r4 = [r5], -118
+
+	ld2.c.clr.acq r4 = [r5]
+	ld2.c.clr.acq r4 = [r5], r6
+	ld2.c.clr.acq r4 = [r5], -105
+	ld2.c.clr.acq.nt1 r4 = [r5]
+	ld2.c.clr.acq.nt1 r4 = [r5], r6
+	ld2.c.clr.acq.nt1 r4 = [r5], -92
+	ld2.c.clr.acq.nta r4 = [r5]
+	ld2.c.clr.acq.nta r4 = [r5], r6
+	ld2.c.clr.acq.nta r4 = [r5], -79
+
+	ld4 r4 = [r5]
+	ld4 r4 = [r5], r6
+	ld4 r4 = [r5], -66
+	ld4.nt1 r4 = [r5]
+	ld4.nt1 r4 = [r5], r6
+	ld4.nt1 r4 = [r5], -53
+	ld4.nta r4 = [r5]
+	ld4.nta r4 = [r5], r6
+	ld4.nta r4 = [r5], -40
+
+	ld4.s r4 = [r5]
+	ld4.s r4 = [r5], r6
+	ld4.s r4 = [r5], -27
+	ld4.s.nt1 r4 = [r5]
+	ld4.s.nt1 r4 = [r5], r6
+	ld4.s.nt1 r4 = [r5], -14
+	ld4.s.nta r4 = [r5]
+	ld4.s.nta r4 = [r5], r6
+	ld4.s.nta r4 = [r5], -1
+
+	ld4.a r4 = [r5]
+	ld4.a r4 = [r5], r6
+	ld4.a r4 = [r5], 12
+	ld4.a.nt1 r4 = [r5]
+	ld4.a.nt1 r4 = [r5], r6
+	ld4.a.nt1 r4 = [r5], 25
+	ld4.a.nta r4 = [r5]
+	ld4.a.nta r4 = [r5], r6
+	ld4.a.nta r4 = [r5], 38
+
+	ld4.sa r4 = [r5]
+	ld4.sa r4 = [r5], r6
+	ld4.sa r4 = [r5], 51
+	ld4.sa.nt1 r4 = [r5]
+	ld4.sa.nt1 r4 = [r5], r6
+	ld4.sa.nt1 r4 = [r5], 64
+	ld4.sa.nta r4 = [r5]
+	ld4.sa.nta r4 = [r5], r6
+	ld4.sa.nta r4 = [r5], 77
+
+	ld4.c.clr r4 = [r5]
+	ld4.c.clr r4 = [r5], r6
+	ld4.c.clr r4 = [r5], 90
+	ld4.c.clr.nt1 r4 = [r5]
+	ld4.c.clr.nt1 r4 = [r5], r6
+	ld4.c.clr.nt1 r4 = [r5], 103
+	ld4.c.clr.nta r4 = [r5]
+	ld4.c.clr.nta r4 = [r5], r6
+	ld4.c.clr.nta r4 = [r5], 116
+
+	ld4.c.nc r4 = [r5]
+	ld4.c.nc r4 = [r5], r6
+	ld4.c.nc r4 = [r5], 129
+	ld4.c.nc.nt1 r4 = [r5]
+	ld4.c.nc.nt1 r4 = [r5], r6
+	ld4.c.nc.nt1 r4 = [r5], 142
+	ld4.c.nc.nta r4 = [r5]
+	ld4.c.nc.nta r4 = [r5], r6
+	ld4.c.nc.nta r4 = [r5], 155
+
+	ld4.bias r4 = [r5]
+	ld4.bias r4 = [r5], r6
+	ld4.bias r4 = [r5], 168
+	ld4.bias.nt1 r4 = [r5]
+	ld4.bias.nt1 r4 = [r5], r6
+	ld4.bias.nt1 r4 = [r5], 181
+	ld4.bias.nta r4 = [r5]
+	ld4.bias.nta r4 = [r5], r6
+	ld4.bias.nta r4 = [r5], 194
+
+	ld4.acq r4 = [r5]
+	ld4.acq r4 = [r5], r6
+	ld4.acq r4 = [r5], 207
+	ld4.acq.nt1 r4 = [r5]
+	ld4.acq.nt1 r4 = [r5], r6
+	ld4.acq.nt1 r4 = [r5], 220
+	ld4.acq.nta r4 = [r5]
+	ld4.acq.nta r4 = [r5], r6
+	ld4.acq.nta r4 = [r5], 233
+
+	ld4.c.clr.acq r4 = [r5]
+	ld4.c.clr.acq r4 = [r5], r6
+	ld4.c.clr.acq r4 = [r5], 246
+	ld4.c.clr.acq.nt1 r4 = [r5]
+	ld4.c.clr.acq.nt1 r4 = [r5], r6
+	ld4.c.clr.acq.nt1 r4 = [r5], -253
+	ld4.c.clr.acq.nta r4 = [r5]
+	ld4.c.clr.acq.nta r4 = [r5], r6
+	ld4.c.clr.acq.nta r4 = [r5], -240
+
+	ld8 r4 = [r5]
+	ld8 r4 = [r5], r6
+	ld8 r4 = [r5], -227
+	ld8.nt1 r4 = [r5]
+	ld8.nt1 r4 = [r5], r6
+	ld8.nt1 r4 = [r5], -214
+	ld8.nta r4 = [r5]
+	ld8.nta r4 = [r5], r6
+	ld8.nta r4 = [r5], -201
+
+	ld8.s r4 = [r5]
+	ld8.s r4 = [r5], r6
+	ld8.s r4 = [r5], -188
+	ld8.s.nt1 r4 = [r5]
+	ld8.s.nt1 r4 = [r5], r6
+	ld8.s.nt1 r4 = [r5], -175
+	ld8.s.nta r4 = [r5]
+	ld8.s.nta r4 = [r5], r6
+	ld8.s.nta r4 = [r5], -162
+
+	ld8.a r4 = [r5]
+	ld8.a r4 = [r5], r6
+	ld8.a r4 = [r5], -149
+	ld8.a.nt1 r4 = [r5]
+	ld8.a.nt1 r4 = [r5], r6
+	ld8.a.nt1 r4 = [r5], -136
+	ld8.a.nta r4 = [r5]
+	ld8.a.nta r4 = [r5], r6
+	ld8.a.nta r4 = [r5], -123
+
+	ld8.sa r4 = [r5]
+	ld8.sa r4 = [r5], r6
+	ld8.sa r4 = [r5], -110
+	ld8.sa.nt1 r4 = [r5]
+	ld8.sa.nt1 r4 = [r5], r6
+	ld8.sa.nt1 r4 = [r5], -97
+	ld8.sa.nta r4 = [r5]
+	ld8.sa.nta r4 = [r5], r6
+	ld8.sa.nta r4 = [r5], -84
+
+	ld8.c.clr r4 = [r5]
+	ld8.c.clr r4 = [r5], r6
+	ld8.c.clr r4 = [r5], -71
+	ld8.c.clr.nt1 r4 = [r5]
+	ld8.c.clr.nt1 r4 = [r5], r6
+	ld8.c.clr.nt1 r4 = [r5], -58
+	ld8.c.clr.nta r4 = [r5]
+	ld8.c.clr.nta r4 = [r5], r6
+	ld8.c.clr.nta r4 = [r5], -45
+
+	ld8.c.nc r4 = [r5]
+	ld8.c.nc r4 = [r5], r6
+	ld8.c.nc r4 = [r5], -32
+	ld8.c.nc.nt1 r4 = [r5]
+	ld8.c.nc.nt1 r4 = [r5], r6
+	ld8.c.nc.nt1 r4 = [r5], -19
+	ld8.c.nc.nta r4 = [r5]
+	ld8.c.nc.nta r4 = [r5], r6
+	ld8.c.nc.nta r4 = [r5], -6
+
+	ld8.bias r4 = [r5]
+	ld8.bias r4 = [r5], r6
+	ld8.bias r4 = [r5], 7
+	ld8.bias.nt1 r4 = [r5]
+	ld8.bias.nt1 r4 = [r5], r6
+	ld8.bias.nt1 r4 = [r5], 20
+	ld8.bias.nta r4 = [r5]
+	ld8.bias.nta r4 = [r5], r6
+	ld8.bias.nta r4 = [r5], 33
+
+	ld8.acq r4 = [r5]
+	ld8.acq r4 = [r5], r6
+	ld8.acq r4 = [r5], 46
+	ld8.acq.nt1 r4 = [r5]
+	ld8.acq.nt1 r4 = [r5], r6
+	ld8.acq.nt1 r4 = [r5], 59
+	ld8.acq.nta r4 = [r5]
+	ld8.acq.nta r4 = [r5], r6
+	ld8.acq.nta r4 = [r5], 72
+
+	ld8.c.clr.acq r4 = [r5]
+	ld8.c.clr.acq r4 = [r5], r6
+	ld8.c.clr.acq r4 = [r5], 85
+	ld8.c.clr.acq.nt1 r4 = [r5]
+	ld8.c.clr.acq.nt1 r4 = [r5], r6
+	ld8.c.clr.acq.nt1 r4 = [r5], 98
+	ld8.c.clr.acq.nta r4 = [r5]
+	ld8.c.clr.acq.nta r4 = [r5], r6
+	ld8.c.clr.acq.nta r4 = [r5], 111
+
+	ld8.fill r4 = [r5]
+	ld8.fill r4 = [r5], r6
+	ld8.fill r4 = [r5], 124
+	ld8.fill.nt1 r4 = [r5]
+	ld8.fill.nt1 r4 = [r5], r6
+	ld8.fill.nt1 r4 = [r5], 137
+	ld8.fill.nta r4 = [r5]
+	ld8.fill.nta r4 = [r5], r6
+	ld8.fill.nta r4 = [r5], 150
+
+	st1 [r4] = r5
+	st1 [r4] = r5, 163
+	st1.nta [r4] = r5
+	st1.nta [r4] = r5, 176
+
+	st2 [r4] = r5
+	st2 [r4] = r5, 189
+	st2.nta [r4] = r5
+	st2.nta [r4] = r5, 202
+
+	st4 [r4] = r5
+	st4 [r4] = r5, 215
+	st4.nta [r4] = r5
+	st4.nta [r4] = r5, 228
+
+	st8 [r4] = r5
+	st8 [r4] = r5, 241
+	st8.nta [r4] = r5
+	st8.nta [r4] = r5, 254
+
+	st1.rel [r4] = r5
+	st1.rel [r4] = r5, -245
+	st1.rel.nta [r4] = r5
+	st1.rel.nta [r4] = r5, -232
+
+	st2.rel [r4] = r5
+	st2.rel [r4] = r5, -219
+	st2.rel.nta [r4] = r5
+	st2.rel.nta [r4] = r5, -206
+
+	st4.rel [r4] = r5
+	st4.rel [r4] = r5, -193
+	st4.rel.nta [r4] = r5
+	st4.rel.nta [r4] = r5, -180
+
+	st8.rel [r4] = r5
+	st8.rel [r4] = r5, -167
+	st8.rel.nta [r4] = r5
+	st8.rel.nta [r4] = r5, -154
+
+	st8.spill [r4] = r5
+	st8.spill [r4] = r5, -141
+	st8.spill.nta [r4] = r5
+	st8.spill.nta [r4] = r5, -128
+
+	ldfs f4 = [r5]
+	ldfs f4 = [r5], r6
+	ldfs f4 = [r5], -115
+	ldfs.nt1 f4 = [r5]
+	ldfs.nt1 f4 = [r5], r6
+	ldfs.nt1 f4 = [r5], -102
+	ldfs.nta f4 = [r5]
+	ldfs.nta f4 = [r5], r6
+	ldfs.nta f4 = [r5], -89
+
+	ldfs.s f4 = [r5]
+	ldfs.s f4 = [r5], r6
+	ldfs.s f4 = [r5], -76
+	ldfs.s.nt1 f4 = [r5]
+	ldfs.s.nt1 f4 = [r5], r6
+	ldfs.s.nt1 f4 = [r5], -63
+	ldfs.s.nta f4 = [r5]
+	ldfs.s.nta f4 = [r5], r6
+	ldfs.s.nta f4 = [r5], -50
+
+	ldfs.a f4 = [r5]
+	ldfs.a f4 = [r5], r6
+	ldfs.a f4 = [r5], -37
+	ldfs.a.nt1 f4 = [r5]
+	ldfs.a.nt1 f4 = [r5], r6
+	ldfs.a.nt1 f4 = [r5], -24
+	ldfs.a.nta f4 = [r5]
+	ldfs.a.nta f4 = [r5], r6
+	ldfs.a.nta f4 = [r5], -11
+
+	ldfs.sa f4 = [r5]
+	ldfs.sa f4 = [r5], r6
+	ldfs.sa f4 = [r5], 2
+	ldfs.sa.nt1 f4 = [r5]
+	ldfs.sa.nt1 f4 = [r5], r6
+	ldfs.sa.nt1 f4 = [r5], 15
+	ldfs.sa.nta f4 = [r5]
+	ldfs.sa.nta f4 = [r5], r6
+	ldfs.sa.nta f4 = [r5], 28
+
+	ldfs.c.clr f4 = [r5]
+	ldfs.c.clr f4 = [r5], r6
+	ldfs.c.clr f4 = [r5], 41
+	ldfs.c.clr.nt1 f4 = [r5]
+	ldfs.c.clr.nt1 f4 = [r5], r6
+	ldfs.c.clr.nt1 f4 = [r5], 54
+	ldfs.c.clr.nta f4 = [r5]
+	ldfs.c.clr.nta f4 = [r5], r6
+	ldfs.c.clr.nta f4 = [r5], 67
+
+	ldfs.c.nc f4 = [r5]
+	ldfs.c.nc f4 = [r5], r6
+	ldfs.c.nc f4 = [r5], 80
+	ldfs.c.nc.nt1 f4 = [r5]
+	ldfs.c.nc.nt1 f4 = [r5], r6
+	ldfs.c.nc.nt1 f4 = [r5], 93
+	ldfs.c.nc.nta f4 = [r5]
+	ldfs.c.nc.nta f4 = [r5], r6
+	ldfs.c.nc.nta f4 = [r5], 106
+
+	ldfd f4 = [r5]
+	ldfd f4 = [r5], r6
+	ldfd f4 = [r5], 119
+	ldfd.nt1 f4 = [r5]
+	ldfd.nt1 f4 = [r5], r6
+	ldfd.nt1 f4 = [r5], 132
+	ldfd.nta f4 = [r5]
+	ldfd.nta f4 = [r5], r6
+	ldfd.nta f4 = [r5], 145
+
+	ldfd.s f4 = [r5]
+	ldfd.s f4 = [r5], r6
+	ldfd.s f4 = [r5], 158
+	ldfd.s.nt1 f4 = [r5]
+	ldfd.s.nt1 f4 = [r5], r6
+	ldfd.s.nt1 f4 = [r5], 171
+	ldfd.s.nta f4 = [r5]
+	ldfd.s.nta f4 = [r5], r6
+	ldfd.s.nta f4 = [r5], 184
+
+	ldfd.a f4 = [r5]
+	ldfd.a f4 = [r5], r6
+	ldfd.a f4 = [r5], 197
+	ldfd.a.nt1 f4 = [r5]
+	ldfd.a.nt1 f4 = [r5], r6
+	ldfd.a.nt1 f4 = [r5], 210
+	ldfd.a.nta f4 = [r5]
+	ldfd.a.nta f4 = [r5], r6
+	ldfd.a.nta f4 = [r5], 223
+
+	ldfd.sa f4 = [r5]
+	ldfd.sa f4 = [r5], r6
+	ldfd.sa f4 = [r5], 236
+	ldfd.sa.nt1 f4 = [r5]
+	ldfd.sa.nt1 f4 = [r5], r6
+	ldfd.sa.nt1 f4 = [r5], 249
+	ldfd.sa.nta f4 = [r5]
+	ldfd.sa.nta f4 = [r5], r6
+	ldfd.sa.nta f4 = [r5], -250
+
+	ldfd.c.clr f4 = [r5]
+	ldfd.c.clr f4 = [r5], r6
+	ldfd.c.clr f4 = [r5], -237
+	ldfd.c.clr.nt1 f4 = [r5]
+	ldfd.c.clr.nt1 f4 = [r5], r6
+	ldfd.c.clr.nt1 f4 = [r5], -224
+	ldfd.c.clr.nta f4 = [r5]
+	ldfd.c.clr.nta f4 = [r5], r6
+	ldfd.c.clr.nta f4 = [r5], -211
+
+	ldfd.c.nc f4 = [r5]
+	ldfd.c.nc f4 = [r5], r6
+	ldfd.c.nc f4 = [r5], -198
+	ldfd.c.nc.nt1 f4 = [r5]
+	ldfd.c.nc.nt1 f4 = [r5], r6
+	ldfd.c.nc.nt1 f4 = [r5], -185
+	ldfd.c.nc.nta f4 = [r5]
+	ldfd.c.nc.nta f4 = [r5], r6
+	ldfd.c.nc.nta f4 = [r5], -172
+
+	ldf8 f4 = [r5]
+	ldf8 f4 = [r5], r6
+	ldf8 f4 = [r5], -159
+	ldf8.nt1 f4 = [r5]
+	ldf8.nt1 f4 = [r5], r6
+	ldf8.nt1 f4 = [r5], -146
+	ldf8.nta f4 = [r5]
+	ldf8.nta f4 = [r5], r6
+	ldf8.nta f4 = [r5], -133
+
+	ldf8.s f4 = [r5]
+	ldf8.s f4 = [r5], r6
+	ldf8.s f4 = [r5], -120
+	ldf8.s.nt1 f4 = [r5]
+	ldf8.s.nt1 f4 = [r5], r6
+	ldf8.s.nt1 f4 = [r5], -107
+	ldf8.s.nta f4 = [r5]
+	ldf8.s.nta f4 = [r5], r6
+	ldf8.s.nta f4 = [r5], -94
+
+	ldf8.a f4 = [r5]
+	ldf8.a f4 = [r5], r6
+	ldf8.a f4 = [r5], -81
+	ldf8.a.nt1 f4 = [r5]
+	ldf8.a.nt1 f4 = [r5], r6
+	ldf8.a.nt1 f4 = [r5], -68
+	ldf8.a.nta f4 = [r5]
+	ldf8.a.nta f4 = [r5], r6
+	ldf8.a.nta f4 = [r5], -55
+
+	ldf8.sa f4 = [r5]
+	ldf8.sa f4 = [r5], r6
+	ldf8.sa f4 = [r5], -42
+	ldf8.sa.nt1 f4 = [r5]
+	ldf8.sa.nt1 f4 = [r5], r6
+	ldf8.sa.nt1 f4 = [r5], -29
+	ldf8.sa.nta f4 = [r5]
+	ldf8.sa.nta f4 = [r5], r6
+	ldf8.sa.nta f4 = [r5], -16
+
+	ldf8.c.clr f4 = [r5]
+	ldf8.c.clr f4 = [r5], r6
+	ldf8.c.clr f4 = [r5], -3
+	ldf8.c.clr.nt1 f4 = [r5]
+	ldf8.c.clr.nt1 f4 = [r5], r6
+	ldf8.c.clr.nt1 f4 = [r5], 10
+	ldf8.c.clr.nta f4 = [r5]
+	ldf8.c.clr.nta f4 = [r5], r6
+	ldf8.c.clr.nta f4 = [r5], 23
+
+	ldf8.c.nc f4 = [r5]
+	ldf8.c.nc f4 = [r5], r6
+	ldf8.c.nc f4 = [r5], 36
+	ldf8.c.nc.nt1 f4 = [r5]
+	ldf8.c.nc.nt1 f4 = [r5], r6
+	ldf8.c.nc.nt1 f4 = [r5], 49
+	ldf8.c.nc.nta f4 = [r5]
+	ldf8.c.nc.nta f4 = [r5], r6
+	ldf8.c.nc.nta f4 = [r5], 62
+
+	ldfe f4 = [r5]
+	ldfe f4 = [r5], r6
+	ldfe f4 = [r5], 75
+	ldfe.nt1 f4 = [r5]
+	ldfe.nt1 f4 = [r5], r6
+	ldfe.nt1 f4 = [r5], 88
+	ldfe.nta f4 = [r5]
+	ldfe.nta f4 = [r5], r6
+	ldfe.nta f4 = [r5], 101
+
+	ldfe.s f4 = [r5]
+	ldfe.s f4 = [r5], r6
+	ldfe.s f4 = [r5], 114
+	ldfe.s.nt1 f4 = [r5]
+	ldfe.s.nt1 f4 = [r5], r6
+	ldfe.s.nt1 f4 = [r5], 127
+	ldfe.s.nta f4 = [r5]
+	ldfe.s.nta f4 = [r5], r6
+	ldfe.s.nta f4 = [r5], 140
+
+	ldfe.a f4 = [r5]
+	ldfe.a f4 = [r5], r6
+	ldfe.a f4 = [r5], 153
+	ldfe.a.nt1 f4 = [r5]
+	ldfe.a.nt1 f4 = [r5], r6
+	ldfe.a.nt1 f4 = [r5], 166
+	ldfe.a.nta f4 = [r5]
+	ldfe.a.nta f4 = [r5], r6
+	ldfe.a.nta f4 = [r5], 179
+
+	ldfe.sa f4 = [r5]
+	ldfe.sa f4 = [r5], r6
+	ldfe.sa f4 = [r5], 192
+	ldfe.sa.nt1 f4 = [r5]
+	ldfe.sa.nt1 f4 = [r5], r6
+	ldfe.sa.nt1 f4 = [r5], 205
+	ldfe.sa.nta f4 = [r5]
+	ldfe.sa.nta f4 = [r5], r6
+	ldfe.sa.nta f4 = [r5], 218
+
+	ldfe.c.clr f4 = [r5]
+	ldfe.c.clr f4 = [r5], r6
+	ldfe.c.clr f4 = [r5], 231
+	ldfe.c.clr.nt1 f4 = [r5]
+	ldfe.c.clr.nt1 f4 = [r5], r6
+	ldfe.c.clr.nt1 f4 = [r5], 244
+	ldfe.c.clr.nta f4 = [r5]
+	ldfe.c.clr.nta f4 = [r5], r6
+	ldfe.c.clr.nta f4 = [r5], -255
+
+	ldfe.c.nc f4 = [r5]
+	ldfe.c.nc f4 = [r5], r6
+	ldfe.c.nc f4 = [r5], -242
+	ldfe.c.nc.nt1 f4 = [r5]
+	ldfe.c.nc.nt1 f4 = [r5], r6
+	ldfe.c.nc.nt1 f4 = [r5], -229
+	ldfe.c.nc.nta f4 = [r5]
+	ldfe.c.nc.nta f4 = [r5], r6
+	ldfe.c.nc.nta f4 = [r5], -216
+
+	ldf.fill f4 = [r5]
+	ldf.fill f4 = [r5], r6
+	ldf.fill f4 = [r5], -203
+	ldf.fill.nt1 f4 = [r5]
+	ldf.fill.nt1 f4 = [r5], r6
+	ldf.fill.nt1 f4 = [r5], -190
+	ldf.fill.nta f4 = [r5]
+	ldf.fill.nta f4 = [r5], r6
+	ldf.fill.nta f4 = [r5], -177
+
+	stfs [r4] = f5
+	stfs [r4] = f5, -164
+	stfs.nta [r4] = f5
+	stfs.nta [r4] = f5, -151
+
+	stfd [r4] = f5
+	stfd [r4] = f5, -138
+	stfd.nta [r4] = f5
+	stfd.nta [r4] = f5, -125
+
+	stf8 [r4] = f5
+	stf8 [r4] = f5, -112
+	stf8.nta [r4] = f5
+	stf8.nta [r4] = f5, -99
+
+	stfe [r4] = f5
+	stfe [r4] = f5, -86
+	stfe.nta [r4] = f5
+	stfe.nta [r4] = f5, -73
+
+	stf.spill [r4] = f5
+	stf.spill [r4] = f5, -60
+	stf.spill.nta [r4] = f5
+	stf.spill.nta [r4] = f5, -47
+
+	ldfps f4, f5 = [r5]
+	ldfps f4, f5 = [r5], 8
+	ldfps.nt1 f4, f5 = [r5]
+	ldfps.nt1 f4, f5 = [r5], 8
+	ldfps.nta f4, f5 = [r5]
+	ldfps.nta f4, f5 = [r5], 8
+
+	ldfps.s f4, f5 = [r5]
+	ldfps.s f4, f5 = [r5], 8
+	ldfps.s.nt1 f4, f5 = [r5]
+	ldfps.s.nt1 f4, f5 = [r5], 8
+	ldfps.s.nta f4, f5 = [r5]
+	ldfps.s.nta f4, f5 = [r5], 8
+
+	ldfps.a f4, f5 = [r5]
+	ldfps.a f4, f5 = [r5], 8
+	ldfps.a.nt1 f4, f5 = [r5]
+	ldfps.a.nt1 f4, f5 = [r5], 8
+	ldfps.a.nta f4, f5 = [r5]
+	ldfps.a.nta f4, f5 = [r5], 8
+
+	ldfps.sa f4, f5 = [r5]
+	ldfps.sa f4, f5 = [r5], 8
+	ldfps.sa.nt1 f4, f5 = [r5]
+	ldfps.sa.nt1 f4, f5 = [r5], 8
+	ldfps.sa.nta f4, f5 = [r5]
+	ldfps.sa.nta f4, f5 = [r5], 8
+
+	ldfps.c.clr f4, f5 = [r5]
+	ldfps.c.clr f4, f5 = [r5], 8
+	ldfps.c.clr.nt1 f4, f5 = [r5]
+	ldfps.c.clr.nt1 f4, f5 = [r5], 8
+	ldfps.c.clr.nta f4, f5 = [r5]
+	ldfps.c.clr.nta f4, f5 = [r5], 8
+
+	ldfps.c.nc f4, f5 = [r5]
+	ldfps.c.nc f4, f5 = [r5], 8
+	ldfps.c.nc.nt1 f4, f5 = [r5]
+	ldfps.c.nc.nt1 f4, f5 = [r5], 8
+	ldfps.c.nc.nta f4, f5 = [r5]
+	ldfps.c.nc.nta f4, f5 = [r5], 8
+
+	ldfpd f4, f5 = [r5]
+	ldfpd f4, f5 = [r5], 16
+	ldfpd.nt1 f4, f5 = [r5]
+	ldfpd.nt1 f4, f5 = [r5], 16
+	ldfpd.nta f4, f5 = [r5]
+	ldfpd.nta f4, f5 = [r5], 16
+
+	ldfpd.s f4, f5 = [r5]
+	ldfpd.s f4, f5 = [r5], 16
+	ldfpd.s.nt1 f4, f5 = [r5]
+	ldfpd.s.nt1 f4, f5 = [r5], 16
+	ldfpd.s.nta f4, f5 = [r5]
+	ldfpd.s.nta f4, f5 = [r5], 16
+
+	ldfpd.a f4, f5 = [r5]
+	ldfpd.a f4, f5 = [r5], 16
+	ldfpd.a.nt1 f4, f5 = [r5]
+	ldfpd.a.nt1 f4, f5 = [r5], 16
+	ldfpd.a.nta f4, f5 = [r5]
+	ldfpd.a.nta f4, f5 = [r5], 16
+
+	ldfpd.sa f4, f5 = [r5]
+	ldfpd.sa f4, f5 = [r5], 16
+	ldfpd.sa.nt1 f4, f5 = [r5]
+	ldfpd.sa.nt1 f4, f5 = [r5], 16
+	ldfpd.sa.nta f4, f5 = [r5]
+	ldfpd.sa.nta f4, f5 = [r5], 16
+
+	ldfpd.c.clr f4, f5 = [r5]
+	ldfpd.c.clr f4, f5 = [r5], 16
+	ldfpd.c.clr.nt1 f4, f5 = [r5]
+	ldfpd.c.clr.nt1 f4, f5 = [r5], 16
+	ldfpd.c.clr.nta f4, f5 = [r5]
+	ldfpd.c.clr.nta f4, f5 = [r5], 16
+
+	ldfpd.c.nc f4, f5 = [r5]
+	ldfpd.c.nc f4, f5 = [r5], 16
+	ldfpd.c.nc.nt1 f4, f5 = [r5]
+	ldfpd.c.nc.nt1 f4, f5 = [r5], 16
+	ldfpd.c.nc.nta f4, f5 = [r5]
+	ldfpd.c.nc.nta f4, f5 = [r5], 16
+
+	ldfp8 f4, f5 = [r5]
+	ldfp8 f4, f5 = [r5], 16
+	ldfp8.nt1 f4, f5 = [r5]
+	ldfp8.nt1 f4, f5 = [r5], 16
+	ldfp8.nta f4, f5 = [r5]
+	ldfp8.nta f4, f5 = [r5], 16
+
+	ldfp8.s f4, f5 = [r5]
+	ldfp8.s f4, f5 = [r5], 16
+	ldfp8.s.nt1 f4, f5 = [r5]
+	ldfp8.s.nt1 f4, f5 = [r5], 16
+	ldfp8.s.nta f4, f5 = [r5]
+	ldfp8.s.nta f4, f5 = [r5], 16
+
+	ldfp8.a f4, f5 = [r5]
+	ldfp8.a f4, f5 = [r5], 16
+	ldfp8.a.nt1 f4, f5 = [r5]
+	ldfp8.a.nt1 f4, f5 = [r5], 16
+	ldfp8.a.nta f4, f5 = [r5]
+	ldfp8.a.nta f4, f5 = [r5], 16
+
+	ldfp8.sa f4, f5 = [r5]
+	ldfp8.sa f4, f5 = [r5], 16
+	ldfp8.sa.nt1 f4, f5 = [r5]
+	ldfp8.sa.nt1 f4, f5 = [r5], 16
+	ldfp8.sa.nta f4, f5 = [r5]
+	ldfp8.sa.nta f4, f5 = [r5], 16
+
+	ldfp8.c.clr f4, f5 = [r5]
+	ldfp8.c.clr f4, f5 = [r5], 16
+	ldfp8.c.clr.nt1 f4, f5 = [r5]
+	ldfp8.c.clr.nt1 f4, f5 = [r5], 16
+	ldfp8.c.clr.nta f4, f5 = [r5]
+	ldfp8.c.clr.nta f4, f5 = [r5], 16
+
+	ldfp8.c.nc f4, f5 = [r5]
+	ldfp8.c.nc f4, f5 = [r5], 16
+	ldfp8.c.nc.nt1 f4, f5 = [r5]
+	ldfp8.c.nc.nt1 f4, f5 = [r5], 16
+	ldfp8.c.nc.nta f4, f5 = [r5]
+	ldfp8.c.nc.nta f4, f5 = [r5], 16
+
+	lfetch [r4]
+	lfetch [r4], r5
+	lfetch [r4], -34
+	lfetch.nt1 [r4]
+	lfetch.nt1 [r4], r5
+	lfetch.nt1 [r4], -21
+	lfetch.nt2 [r4]
+	lfetch.nt2 [r4], r5
+	lfetch.nt2 [r4], -8
+	lfetch.nta [r4]
+	lfetch.nta [r4], r5
+	lfetch.nta [r4], 5
+
+	lfetch.fault [r4]
+	lfetch.fault [r4], r5
+	lfetch.fault [r4], 18
+	lfetch.fault.nt1 [r4]
+	lfetch.fault.nt1 [r4], r5
+	lfetch.fault.nt1 [r4], 31
+	lfetch.fault.nt2 [r4]
+	lfetch.fault.nt2 [r4], r5
+	lfetch.fault.nt2 [r4], 44
+	lfetch.fault.nta [r4]
+	lfetch.fault.nta [r4], r5
+	lfetch.fault.nta [r4], 57
+
+	lfetch.excl [r4]
+	lfetch.excl [r4], r5
+	lfetch.excl [r4], 70
+	lfetch.excl.nt1 [r4]
+	lfetch.excl.nt1 [r4], r5
+	lfetch.excl.nt1 [r4], 83
+	lfetch.excl.nt2 [r4]
+	lfetch.excl.nt2 [r4], r5
+	lfetch.excl.nt2 [r4], 96
+	lfetch.excl.nta [r4]
+	lfetch.excl.nta [r4], r5
+	lfetch.excl.nta [r4], 109
+
+	lfetch.fault.excl [r4]
+	lfetch.fault.excl [r4], r5
+	lfetch.fault.excl [r4], 122
+	lfetch.fault.excl.nt1 [r4]
+	lfetch.fault.excl.nt1 [r4], r5
+	lfetch.fault.excl.nt1 [r4], 135
+	lfetch.fault.excl.nt2 [r4]
+	lfetch.fault.excl.nt2 [r4], r5
+	lfetch.fault.excl.nt2 [r4], 148
+	lfetch.fault.excl.nta [r4]
+	lfetch.fault.excl.nta [r4], r5
+	lfetch.fault.excl.nta [r4], 161
+
+	cmpxchg1.acq r4 = [r5], r6, ar.ccv
+	cmpxchg1.acq.nt1 r4 = [r5], r6, ar.ccv
+	cmpxchg1.acq.nta r4 = [r5], r6, ar.ccv
+
+	cmpxchg1.rel r4 = [r5], r6, ar.ccv
+	cmpxchg1.rel.nt1 r4 = [r5], r6, ar.ccv
+	cmpxchg1.rel.nta r4 = [r5], r6, ar.ccv
+
+	cmpxchg2.acq r4 = [r5], r6, ar.ccv
+	cmpxchg2.acq.nt1 r4 = [r5], r6, ar.ccv
+	cmpxchg2.acq.nta r4 = [r5], r6, ar.ccv
+
+	cmpxchg2.rel r4 = [r5], r6, ar.ccv
+	cmpxchg2.rel.nt1 r4 = [r5], r6, ar.ccv
+	cmpxchg2.rel.nta r4 = [r5], r6, ar.ccv
+
+	cmpxchg4.acq r4 = [r5], r6, ar.ccv
+	cmpxchg4.acq.nt1 r4 = [r5], r6, ar.ccv
+	cmpxchg4.acq.nta r4 = [r5], r6, ar.ccv
+
+	cmpxchg4.rel r4 = [r5], r6, ar.ccv
+	cmpxchg4.rel.nt1 r4 = [r5], r6, ar.ccv
+	cmpxchg4.rel.nta r4 = [r5], r6, ar.ccv
+
+	cmpxchg8.acq r4 = [r5], r6, ar.ccv
+	cmpxchg8.acq.nt1 r4 = [r5], r6, ar.ccv
+	cmpxchg8.acq.nta r4 = [r5], r6, ar.ccv
+
+	cmpxchg8.rel r4 = [r5], r6, ar.ccv
+	cmpxchg8.rel.nt1 r4 = [r5], r6, ar.ccv
+	cmpxchg8.rel.nta r4 = [r5], r6, ar.ccv
+
+	xchg1 r4 = [r5], r6
+	xchg1.nt1 r4 = [r5], r6
+	xchg1.nta r4 = [r5], r6
+
+	xchg2 r4 = [r5], r6
+	xchg2.nt1 r4 = [r5], r6
+	xchg2.nta r4 = [r5], r6
+
+	xchg4 r4 = [r5], r6
+	xchg4.nt1 r4 = [r5], r6
+	xchg4.nta r4 = [r5], r6
+
+	xchg8 r4 = [r5], r6
+	xchg8.nt1 r4 = [r5], r6
+	xchg8.nta r4 = [r5], r6
+
+	fetchadd4.acq r4 = [r5], -16
+	fetchadd4.acq.nt1 r4 = [r5], -8
+	fetchadd4.acq.nta r4 = [r5], -4
+
+	fetchadd8.acq r4 = [r5], -1
+	fetchadd8.acq.nt1 r4 = [r5], 1
+	fetchadd8.acq.nta r4 = [r5], 4
+
+	fetchadd4.rel r4 = [r5], 8
+	fetchadd4.rel.nt1 r4 = [r5], 16
+	fetchadd4.rel.nta r4 = [r5], -16
+
+	fetchadd8.rel r4 = [r5], -8
+	fetchadd8.rel.nt1 r4 = [r5], -4
+	fetchadd8.rel.nta r4 = [r5], -1
+
+	setf.sig f4 = r5
+	setf.exp f4 = r5
+	setf.s f4 = r5
+	setf.d f4 = r5
+
+	getf.sig r4 = f5
+	getf.exp r4 = f5
+	getf.s r4 = f5
+	getf.d r4 = f5
+
+	chk.s.m r4, _start
+	chk.s f4, _start
+	chk.a.nc r4, _start
+	chk.a.clr r4, _start
+	chk.a.nc f4, _start
+	chk.a.clr f4, _start
+
+	invala
+	fwb
+	mf
+	mf.a
+	srlz.d
+	srlz.i
+	sync.i
+	nop.m 0
+	nop.i 0;;
+
+	{ .mii; alloc r4 = ar.pfs, 2, 10, 16, 16;; }
+
+	{ .mii; flushrs;; }
+	{ .mii; loadrs }
+
+	invala.e r4
+	invala.e f4
+
+	fc r4
+	ptc.e r4
+
+	break.m 0
+	break.m 0x1ffff
+
+	nop.m 0
+	break.m 0x1ffff
+
+	probe.r r4 = r5, r6
+	probe.w r4 = r5, r6
+
+	probe.r r4 = r5, 0
+	probe.w r4 = r5, 1
+
+	probe.r.fault r3, 2
+	probe.w.fault r3, 3
+	probe.rw.fault r3, 0
+
+	{ .mmi; itc.d r8;; nop.m 0x0; nop.i 0x0;; }
+	itc.i r9;; 
+	
+	sum 0x1234
+	rum 0x5aaaaa
+	ssm 0xffffff
+	rsm 0x400000
+
+	ptc.l r4, r5
+	{ .mmi; ptc.g r4, r5;; nop.m 0x0; nop.i 0x0 }
+	{ .mmi; ptc.ga r4, r5;; nop.m 0x0; nop.i 0x0 }
+	ptr.d r4, r5
+	ptr.i r4, r5
+
+	thash r4 = r5
+	ttag r4 = r5
+	tpa r4 = r5
+	tak r4 = r5
+
diff --git a/gas/testsuite/gas/ia64/opc-x.d b/gas/testsuite/gas/ia64/opc-x.d
new file mode 100644
index 0000000..10d82fd
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-x.d
@@ -0,0 +1,29 @@
+#objdump: -d
+#name: ia64 opc-x
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0000000000000000 <_start>:
+   0:	04 00 00 00 01 00 	\[MLX\]       nop\.m 0x0
+	...
+   e:	00 00 04 00       	            break\.x 0x0
+  12:	00 00 01 c0 ff ff 	\[MLX\]       nop\.m 0x0
+  18:	ff ff 7f e0 ff ff 	            break\.x 0x3fffffffffffffff
+  1e:	01 08 04 00 
+  22:	00 00 01 00 00 00 	\[MLX\]       nop\.m 0x0
+  28:	00 00 00 00 00 00 	            nop\.x 0x0
+  2e:	04 00 04 00 
+  32:	00 00 01 c0 ff ff 	\[MLX\]       nop\.m 0x0
+  38:	ff ff 7f e0 ff ff 	            nop\.x 0x3fffffffffffffff
+  3e:	05 08 04 00 
+  42:	00 00 01 00 00 00 	\[MLX\]       nop\.m 0x0
+  48:	00 00 00 80 00 00 	            movl r4=0x0
+  4e:	00 60 04 00 
+  52:	00 00 01 c0 ff ff 	\[MLX\]       nop\.m 0x0
+  58:	ff ff 7f 80 f0 f7 	            movl r4=0xffffffffffffffff
+  5e:	ff 6f 05 00 
+  62:	00 00 01 80 90 78 	\[MLX\]       nop\.m 0x0
+  68:	56 34 12 80 f0 76 	            movl r4=0x1234567890abcdef;;
+  6e:	6d 66 00 00 
diff --git a/gas/testsuite/gas/ia64/opc-x.s b/gas/testsuite/gas/ia64/opc-x.s
new file mode 100644
index 0000000..ec1f5f2
--- /dev/null
+++ b/gas/testsuite/gas/ia64/opc-x.s
@@ -0,0 +1,14 @@
+.text
+	.type _start,@function
+_start:
+
+	break.x	0
+	break.x	0x3fffffffffffffff
+	
+	nop.x	0
+	nop.x	0x3fffffffffffffff
+
+	movl r4 = 0
+	movl r4 = 0xffffffffffffffff
+	movl r4 = 0x1234567890abcdef
+
diff --git a/gas/testsuite/gas/ia64/regs.d b/gas/testsuite/gas/ia64/regs.d
new file mode 100644
index 0000000..4687b68
--- /dev/null
+++ b/gas/testsuite/gas/ia64/regs.d
@@ -0,0 +1,2333 @@
+#objdump: -d
+#name: ia64 regs
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <_start>:
+       0:	01 08 00 00 00 21 	\[MII\]       mov r1=r0
+       6:	00 00 00 02 00 00 	            nop\.i 0x0
+       c:	00 00 04 00       	            nop\.i 0x0;;
+      10:	01 10 00 00 00 21 	\[MII\]       mov r2=r0
+      16:	00 00 00 02 00 00 	            nop\.i 0x0
+      1c:	00 00 04 00       	            nop\.i 0x0;;
+      20:	01 18 00 00 00 21 	\[MII\]       mov r3=r0
+      26:	00 00 00 02 00 00 	            nop\.i 0x0
+      2c:	00 00 04 00       	            nop\.i 0x0;;
+      30:	01 20 00 00 00 21 	\[MII\]       mov r4=r0
+      36:	00 00 00 02 00 00 	            nop\.i 0x0
+      3c:	00 00 04 00       	            nop\.i 0x0;;
+      40:	01 28 00 00 00 21 	\[MII\]       mov r5=r0
+      46:	00 00 00 02 00 00 	            nop\.i 0x0
+      4c:	00 00 04 00       	            nop\.i 0x0;;
+      50:	01 30 00 00 00 21 	\[MII\]       mov r6=r0
+      56:	00 00 00 02 00 00 	            nop\.i 0x0
+      5c:	00 00 04 00       	            nop\.i 0x0;;
+      60:	01 38 00 00 00 21 	\[MII\]       mov r7=r0
+      66:	00 00 00 02 00 00 	            nop\.i 0x0
+      6c:	00 00 04 00       	            nop\.i 0x0;;
+      70:	01 40 00 00 00 21 	\[MII\]       mov r8=r0
+      76:	00 00 00 02 00 00 	            nop\.i 0x0
+      7c:	00 00 04 00       	            nop\.i 0x0;;
+      80:	01 48 00 00 00 21 	\[MII\]       mov r9=r0
+      86:	00 00 00 02 00 00 	            nop\.i 0x0
+      8c:	00 00 04 00       	            nop\.i 0x0;;
+      90:	01 50 00 00 00 21 	\[MII\]       mov r10=r0
+      96:	00 00 00 02 00 00 	            nop\.i 0x0
+      9c:	00 00 04 00       	            nop\.i 0x0;;
+      a0:	01 58 00 00 00 21 	\[MII\]       mov r11=r0
+      a6:	00 00 00 02 00 00 	            nop\.i 0x0
+      ac:	00 00 04 00       	            nop\.i 0x0;;
+      b0:	01 60 00 00 00 21 	\[MII\]       mov r12=r0
+      b6:	00 00 00 02 00 00 	            nop\.i 0x0
+      bc:	00 00 04 00       	            nop\.i 0x0;;
+      c0:	01 68 00 00 00 21 	\[MII\]       mov r13=r0
+      c6:	00 00 00 02 00 00 	            nop\.i 0x0
+      cc:	00 00 04 00       	            nop\.i 0x0;;
+      d0:	01 70 00 00 00 21 	\[MII\]       mov r14=r0
+      d6:	00 00 00 02 00 00 	            nop\.i 0x0
+      dc:	00 00 04 00       	            nop\.i 0x0;;
+      e0:	01 78 00 00 00 21 	\[MII\]       mov r15=r0
+      e6:	00 00 00 02 00 00 	            nop\.i 0x0
+      ec:	00 00 04 00       	            nop\.i 0x0;;
+      f0:	01 80 00 00 00 21 	\[MII\]       mov r16=r0
+      f6:	00 00 00 02 00 00 	            nop\.i 0x0
+      fc:	00 00 04 00       	            nop\.i 0x0;;
+     100:	01 88 00 00 00 21 	\[MII\]       mov r17=r0
+     106:	00 00 00 02 00 00 	            nop\.i 0x0
+     10c:	00 00 04 00       	            nop\.i 0x0;;
+     110:	01 90 00 00 00 21 	\[MII\]       mov r18=r0
+     116:	00 00 00 02 00 00 	            nop\.i 0x0
+     11c:	00 00 04 00       	            nop\.i 0x0;;
+     120:	01 98 00 00 00 21 	\[MII\]       mov r19=r0
+     126:	00 00 00 02 00 00 	            nop\.i 0x0
+     12c:	00 00 04 00       	            nop\.i 0x0;;
+     130:	01 a0 00 00 00 21 	\[MII\]       mov r20=r0
+     136:	00 00 00 02 00 00 	            nop\.i 0x0
+     13c:	00 00 04 00       	            nop\.i 0x0;;
+     140:	01 a8 00 00 00 21 	\[MII\]       mov r21=r0
+     146:	00 00 00 02 00 00 	            nop\.i 0x0
+     14c:	00 00 04 00       	            nop\.i 0x0;;
+     150:	01 b0 00 00 00 21 	\[MII\]       mov r22=r0
+     156:	00 00 00 02 00 00 	            nop\.i 0x0
+     15c:	00 00 04 00       	            nop\.i 0x0;;
+     160:	01 b8 00 00 00 21 	\[MII\]       mov r23=r0
+     166:	00 00 00 02 00 00 	            nop\.i 0x0
+     16c:	00 00 04 00       	            nop\.i 0x0;;
+     170:	01 c0 00 00 00 21 	\[MII\]       mov r24=r0
+     176:	00 00 00 02 00 00 	            nop\.i 0x0
+     17c:	00 00 04 00       	            nop\.i 0x0;;
+     180:	01 c8 00 00 00 21 	\[MII\]       mov r25=r0
+     186:	00 00 00 02 00 00 	            nop\.i 0x0
+     18c:	00 00 04 00       	            nop\.i 0x0;;
+     190:	01 d0 00 00 00 21 	\[MII\]       mov r26=r0
+     196:	00 00 00 02 00 00 	            nop\.i 0x0
+     19c:	00 00 04 00       	            nop\.i 0x0;;
+     1a0:	01 d8 00 00 00 21 	\[MII\]       mov r27=r0
+     1a6:	00 00 00 02 00 00 	            nop\.i 0x0
+     1ac:	00 00 04 00       	            nop\.i 0x0;;
+     1b0:	01 e0 00 00 00 21 	\[MII\]       mov r28=r0
+     1b6:	00 00 00 02 00 00 	            nop\.i 0x0
+     1bc:	00 00 04 00       	            nop\.i 0x0;;
+     1c0:	01 e8 00 00 00 21 	\[MII\]       mov r29=r0
+     1c6:	00 00 00 02 00 00 	            nop\.i 0x0
+     1cc:	00 00 04 00       	            nop\.i 0x0;;
+     1d0:	01 f0 00 00 00 21 	\[MII\]       mov r30=r0
+     1d6:	00 00 00 02 00 00 	            nop\.i 0x0
+     1dc:	00 00 04 00       	            nop\.i 0x0;;
+     1e0:	01 f8 00 00 00 21 	\[MII\]       mov r31=r0
+     1e6:	00 00 00 02 00 00 	            nop\.i 0x0
+     1ec:	00 00 04 00       	            nop\.i 0x0;;
+     1f0:	01 00 01 00 00 21 	\[MII\]       mov r32=r0
+     1f6:	00 00 00 02 00 00 	            nop\.i 0x0
+     1fc:	00 00 04 00       	            nop\.i 0x0;;
+     200:	01 08 01 00 00 21 	\[MII\]       mov r33=r0
+     206:	00 00 00 02 00 00 	            nop\.i 0x0
+     20c:	00 00 04 00       	            nop\.i 0x0;;
+     210:	01 10 01 00 00 21 	\[MII\]       mov r34=r0
+     216:	00 00 00 02 00 00 	            nop\.i 0x0
+     21c:	00 00 04 00       	            nop\.i 0x0;;
+     220:	01 18 01 00 00 21 	\[MII\]       mov r35=r0
+     226:	00 00 00 02 00 00 	            nop\.i 0x0
+     22c:	00 00 04 00       	            nop\.i 0x0;;
+     230:	01 20 01 00 00 21 	\[MII\]       mov r36=r0
+     236:	00 00 00 02 00 00 	            nop\.i 0x0
+     23c:	00 00 04 00       	            nop\.i 0x0;;
+     240:	01 28 01 00 00 21 	\[MII\]       mov r37=r0
+     246:	00 00 00 02 00 00 	            nop\.i 0x0
+     24c:	00 00 04 00       	            nop\.i 0x0;;
+     250:	01 30 01 00 00 21 	\[MII\]       mov r38=r0
+     256:	00 00 00 02 00 00 	            nop\.i 0x0
+     25c:	00 00 04 00       	            nop\.i 0x0;;
+     260:	01 38 01 00 00 21 	\[MII\]       mov r39=r0
+     266:	00 00 00 02 00 00 	            nop\.i 0x0
+     26c:	00 00 04 00       	            nop\.i 0x0;;
+     270:	01 40 01 00 00 21 	\[MII\]       mov r40=r0
+     276:	00 00 00 02 00 00 	            nop\.i 0x0
+     27c:	00 00 04 00       	            nop\.i 0x0;;
+     280:	01 48 01 00 00 21 	\[MII\]       mov r41=r0
+     286:	00 00 00 02 00 00 	            nop\.i 0x0
+     28c:	00 00 04 00       	            nop\.i 0x0;;
+     290:	01 50 01 00 00 21 	\[MII\]       mov r42=r0
+     296:	00 00 00 02 00 00 	            nop\.i 0x0
+     29c:	00 00 04 00       	            nop\.i 0x0;;
+     2a0:	01 58 01 00 00 21 	\[MII\]       mov r43=r0
+     2a6:	00 00 00 02 00 00 	            nop\.i 0x0
+     2ac:	00 00 04 00       	            nop\.i 0x0;;
+     2b0:	01 60 01 00 00 21 	\[MII\]       mov r44=r0
+     2b6:	00 00 00 02 00 00 	            nop\.i 0x0
+     2bc:	00 00 04 00       	            nop\.i 0x0;;
+     2c0:	01 68 01 00 00 21 	\[MII\]       mov r45=r0
+     2c6:	00 00 00 02 00 00 	            nop\.i 0x0
+     2cc:	00 00 04 00       	            nop\.i 0x0;;
+     2d0:	01 70 01 00 00 21 	\[MII\]       mov r46=r0
+     2d6:	00 00 00 02 00 00 	            nop\.i 0x0
+     2dc:	00 00 04 00       	            nop\.i 0x0;;
+     2e0:	01 78 01 00 00 21 	\[MII\]       mov r47=r0
+     2e6:	00 00 00 02 00 00 	            nop\.i 0x0
+     2ec:	00 00 04 00       	            nop\.i 0x0;;
+     2f0:	01 80 01 00 00 21 	\[MII\]       mov r48=r0
+     2f6:	00 00 00 02 00 00 	            nop\.i 0x0
+     2fc:	00 00 04 00       	            nop\.i 0x0;;
+     300:	01 88 01 00 00 21 	\[MII\]       mov r49=r0
+     306:	00 00 00 02 00 00 	            nop\.i 0x0
+     30c:	00 00 04 00       	            nop\.i 0x0;;
+     310:	01 90 01 00 00 21 	\[MII\]       mov r50=r0
+     316:	00 00 00 02 00 00 	            nop\.i 0x0
+     31c:	00 00 04 00       	            nop\.i 0x0;;
+     320:	01 98 01 00 00 21 	\[MII\]       mov r51=r0
+     326:	00 00 00 02 00 00 	            nop\.i 0x0
+     32c:	00 00 04 00       	            nop\.i 0x0;;
+     330:	01 a0 01 00 00 21 	\[MII\]       mov r52=r0
+     336:	00 00 00 02 00 00 	            nop\.i 0x0
+     33c:	00 00 04 00       	            nop\.i 0x0;;
+     340:	01 a8 01 00 00 21 	\[MII\]       mov r53=r0
+     346:	00 00 00 02 00 00 	            nop\.i 0x0
+     34c:	00 00 04 00       	            nop\.i 0x0;;
+     350:	01 b0 01 00 00 21 	\[MII\]       mov r54=r0
+     356:	00 00 00 02 00 00 	            nop\.i 0x0
+     35c:	00 00 04 00       	            nop\.i 0x0;;
+     360:	01 b8 01 00 00 21 	\[MII\]       mov r55=r0
+     366:	00 00 00 02 00 00 	            nop\.i 0x0
+     36c:	00 00 04 00       	            nop\.i 0x0;;
+     370:	01 c0 01 00 00 21 	\[MII\]       mov r56=r0
+     376:	00 00 00 02 00 00 	            nop\.i 0x0
+     37c:	00 00 04 00       	            nop\.i 0x0;;
+     380:	01 c8 01 00 00 21 	\[MII\]       mov r57=r0
+     386:	00 00 00 02 00 00 	            nop\.i 0x0
+     38c:	00 00 04 00       	            nop\.i 0x0;;
+     390:	01 d0 01 00 00 21 	\[MII\]       mov r58=r0
+     396:	00 00 00 02 00 00 	            nop\.i 0x0
+     39c:	00 00 04 00       	            nop\.i 0x0;;
+     3a0:	01 d8 01 00 00 21 	\[MII\]       mov r59=r0
+     3a6:	00 00 00 02 00 00 	            nop\.i 0x0
+     3ac:	00 00 04 00       	            nop\.i 0x0;;
+     3b0:	01 e0 01 00 00 21 	\[MII\]       mov r60=r0
+     3b6:	00 00 00 02 00 00 	            nop\.i 0x0
+     3bc:	00 00 04 00       	            nop\.i 0x0;;
+     3c0:	01 e8 01 00 00 21 	\[MII\]       mov r61=r0
+     3c6:	00 00 00 02 00 00 	            nop\.i 0x0
+     3cc:	00 00 04 00       	            nop\.i 0x0;;
+     3d0:	01 f0 01 00 00 21 	\[MII\]       mov r62=r0
+     3d6:	00 00 00 02 00 00 	            nop\.i 0x0
+     3dc:	00 00 04 00       	            nop\.i 0x0;;
+     3e0:	01 f8 01 00 00 21 	\[MII\]       mov r63=r0
+     3e6:	00 00 00 02 00 00 	            nop\.i 0x0
+     3ec:	00 00 04 00       	            nop\.i 0x0;;
+     3f0:	01 00 02 00 00 21 	\[MII\]       mov r64=r0
+     3f6:	00 00 00 02 00 00 	            nop\.i 0x0
+     3fc:	00 00 04 00       	            nop\.i 0x0;;
+     400:	01 08 02 00 00 21 	\[MII\]       mov r65=r0
+     406:	00 00 00 02 00 00 	            nop\.i 0x0
+     40c:	00 00 04 00       	            nop\.i 0x0;;
+     410:	01 10 02 00 00 21 	\[MII\]       mov r66=r0
+     416:	00 00 00 02 00 00 	            nop\.i 0x0
+     41c:	00 00 04 00       	            nop\.i 0x0;;
+     420:	01 18 02 00 00 21 	\[MII\]       mov r67=r0
+     426:	00 00 00 02 00 00 	            nop\.i 0x0
+     42c:	00 00 04 00       	            nop\.i 0x0;;
+     430:	01 20 02 00 00 21 	\[MII\]       mov r68=r0
+     436:	00 00 00 02 00 00 	            nop\.i 0x0
+     43c:	00 00 04 00       	            nop\.i 0x0;;
+     440:	01 28 02 00 00 21 	\[MII\]       mov r69=r0
+     446:	00 00 00 02 00 00 	            nop\.i 0x0
+     44c:	00 00 04 00       	            nop\.i 0x0;;
+     450:	01 30 02 00 00 21 	\[MII\]       mov r70=r0
+     456:	00 00 00 02 00 00 	            nop\.i 0x0
+     45c:	00 00 04 00       	            nop\.i 0x0;;
+     460:	01 38 02 00 00 21 	\[MII\]       mov r71=r0
+     466:	00 00 00 02 00 00 	            nop\.i 0x0
+     46c:	00 00 04 00       	            nop\.i 0x0;;
+     470:	01 40 02 00 00 21 	\[MII\]       mov r72=r0
+     476:	00 00 00 02 00 00 	            nop\.i 0x0
+     47c:	00 00 04 00       	            nop\.i 0x0;;
+     480:	01 48 02 00 00 21 	\[MII\]       mov r73=r0
+     486:	00 00 00 02 00 00 	            nop\.i 0x0
+     48c:	00 00 04 00       	            nop\.i 0x0;;
+     490:	01 50 02 00 00 21 	\[MII\]       mov r74=r0
+     496:	00 00 00 02 00 00 	            nop\.i 0x0
+     49c:	00 00 04 00       	            nop\.i 0x0;;
+     4a0:	01 58 02 00 00 21 	\[MII\]       mov r75=r0
+     4a6:	00 00 00 02 00 00 	            nop\.i 0x0
+     4ac:	00 00 04 00       	            nop\.i 0x0;;
+     4b0:	01 60 02 00 00 21 	\[MII\]       mov r76=r0
+     4b6:	00 00 00 02 00 00 	            nop\.i 0x0
+     4bc:	00 00 04 00       	            nop\.i 0x0;;
+     4c0:	01 68 02 00 00 21 	\[MII\]       mov r77=r0
+     4c6:	00 00 00 02 00 00 	            nop\.i 0x0
+     4cc:	00 00 04 00       	            nop\.i 0x0;;
+     4d0:	01 70 02 00 00 21 	\[MII\]       mov r78=r0
+     4d6:	00 00 00 02 00 00 	            nop\.i 0x0
+     4dc:	00 00 04 00       	            nop\.i 0x0;;
+     4e0:	01 78 02 00 00 21 	\[MII\]       mov r79=r0
+     4e6:	00 00 00 02 00 00 	            nop\.i 0x0
+     4ec:	00 00 04 00       	            nop\.i 0x0;;
+     4f0:	01 80 02 00 00 21 	\[MII\]       mov r80=r0
+     4f6:	00 00 00 02 00 00 	            nop\.i 0x0
+     4fc:	00 00 04 00       	            nop\.i 0x0;;
+     500:	01 88 02 00 00 21 	\[MII\]       mov r81=r0
+     506:	00 00 00 02 00 00 	            nop\.i 0x0
+     50c:	00 00 04 00       	            nop\.i 0x0;;
+     510:	01 90 02 00 00 21 	\[MII\]       mov r82=r0
+     516:	00 00 00 02 00 00 	            nop\.i 0x0
+     51c:	00 00 04 00       	            nop\.i 0x0;;
+     520:	01 98 02 00 00 21 	\[MII\]       mov r83=r0
+     526:	00 00 00 02 00 00 	            nop\.i 0x0
+     52c:	00 00 04 00       	            nop\.i 0x0;;
+     530:	01 a0 02 00 00 21 	\[MII\]       mov r84=r0
+     536:	00 00 00 02 00 00 	            nop\.i 0x0
+     53c:	00 00 04 00       	            nop\.i 0x0;;
+     540:	01 a8 02 00 00 21 	\[MII\]       mov r85=r0
+     546:	00 00 00 02 00 00 	            nop\.i 0x0
+     54c:	00 00 04 00       	            nop\.i 0x0;;
+     550:	01 b0 02 00 00 21 	\[MII\]       mov r86=r0
+     556:	00 00 00 02 00 00 	            nop\.i 0x0
+     55c:	00 00 04 00       	            nop\.i 0x0;;
+     560:	01 b8 02 00 00 21 	\[MII\]       mov r87=r0
+     566:	00 00 00 02 00 00 	            nop\.i 0x0
+     56c:	00 00 04 00       	            nop\.i 0x0;;
+     570:	01 c0 02 00 00 21 	\[MII\]       mov r88=r0
+     576:	00 00 00 02 00 00 	            nop\.i 0x0
+     57c:	00 00 04 00       	            nop\.i 0x0;;
+     580:	01 c8 02 00 00 21 	\[MII\]       mov r89=r0
+     586:	00 00 00 02 00 00 	            nop\.i 0x0
+     58c:	00 00 04 00       	            nop\.i 0x0;;
+     590:	01 d0 02 00 00 21 	\[MII\]       mov r90=r0
+     596:	00 00 00 02 00 00 	            nop\.i 0x0
+     59c:	00 00 04 00       	            nop\.i 0x0;;
+     5a0:	01 d8 02 00 00 21 	\[MII\]       mov r91=r0
+     5a6:	00 00 00 02 00 00 	            nop\.i 0x0
+     5ac:	00 00 04 00       	            nop\.i 0x0;;
+     5b0:	01 e0 02 00 00 21 	\[MII\]       mov r92=r0
+     5b6:	00 00 00 02 00 00 	            nop\.i 0x0
+     5bc:	00 00 04 00       	            nop\.i 0x0;;
+     5c0:	01 e8 02 00 00 21 	\[MII\]       mov r93=r0
+     5c6:	00 00 00 02 00 00 	            nop\.i 0x0
+     5cc:	00 00 04 00       	            nop\.i 0x0;;
+     5d0:	01 f0 02 00 00 21 	\[MII\]       mov r94=r0
+     5d6:	00 00 00 02 00 00 	            nop\.i 0x0
+     5dc:	00 00 04 00       	            nop\.i 0x0;;
+     5e0:	01 f8 02 00 00 21 	\[MII\]       mov r95=r0
+     5e6:	00 00 00 02 00 00 	            nop\.i 0x0
+     5ec:	00 00 04 00       	            nop\.i 0x0;;
+     5f0:	01 00 03 00 00 21 	\[MII\]       mov r96=r0
+     5f6:	00 00 00 02 00 00 	            nop\.i 0x0
+     5fc:	00 00 04 00       	            nop\.i 0x0;;
+     600:	01 08 03 00 00 21 	\[MII\]       mov r97=r0
+     606:	00 00 00 02 00 00 	            nop\.i 0x0
+     60c:	00 00 04 00       	            nop\.i 0x0;;
+     610:	01 10 03 00 00 21 	\[MII\]       mov r98=r0
+     616:	00 00 00 02 00 00 	            nop\.i 0x0
+     61c:	00 00 04 00       	            nop\.i 0x0;;
+     620:	01 18 03 00 00 21 	\[MII\]       mov r99=r0
+     626:	00 00 00 02 00 00 	            nop\.i 0x0
+     62c:	00 00 04 00       	            nop\.i 0x0;;
+     630:	01 20 03 00 00 21 	\[MII\]       mov r100=r0
+     636:	00 00 00 02 00 00 	            nop\.i 0x0
+     63c:	00 00 04 00       	            nop\.i 0x0;;
+     640:	01 28 03 00 00 21 	\[MII\]       mov r101=r0
+     646:	00 00 00 02 00 00 	            nop\.i 0x0
+     64c:	00 00 04 00       	            nop\.i 0x0;;
+     650:	01 30 03 00 00 21 	\[MII\]       mov r102=r0
+     656:	00 00 00 02 00 00 	            nop\.i 0x0
+     65c:	00 00 04 00       	            nop\.i 0x0;;
+     660:	01 38 03 00 00 21 	\[MII\]       mov r103=r0
+     666:	00 00 00 02 00 00 	            nop\.i 0x0
+     66c:	00 00 04 00       	            nop\.i 0x0;;
+     670:	01 40 03 00 00 21 	\[MII\]       mov r104=r0
+     676:	00 00 00 02 00 00 	            nop\.i 0x0
+     67c:	00 00 04 00       	            nop\.i 0x0;;
+     680:	01 48 03 00 00 21 	\[MII\]       mov r105=r0
+     686:	00 00 00 02 00 00 	            nop\.i 0x0
+     68c:	00 00 04 00       	            nop\.i 0x0;;
+     690:	01 50 03 00 00 21 	\[MII\]       mov r106=r0
+     696:	00 00 00 02 00 00 	            nop\.i 0x0
+     69c:	00 00 04 00       	            nop\.i 0x0;;
+     6a0:	01 58 03 00 00 21 	\[MII\]       mov r107=r0
+     6a6:	00 00 00 02 00 00 	            nop\.i 0x0
+     6ac:	00 00 04 00       	            nop\.i 0x0;;
+     6b0:	01 60 03 00 00 21 	\[MII\]       mov r108=r0
+     6b6:	00 00 00 02 00 00 	            nop\.i 0x0
+     6bc:	00 00 04 00       	            nop\.i 0x0;;
+     6c0:	01 68 03 00 00 21 	\[MII\]       mov r109=r0
+     6c6:	00 00 00 02 00 00 	            nop\.i 0x0
+     6cc:	00 00 04 00       	            nop\.i 0x0;;
+     6d0:	01 70 03 00 00 21 	\[MII\]       mov r110=r0
+     6d6:	00 00 00 02 00 00 	            nop\.i 0x0
+     6dc:	00 00 04 00       	            nop\.i 0x0;;
+     6e0:	01 78 03 00 00 21 	\[MII\]       mov r111=r0
+     6e6:	00 00 00 02 00 00 	            nop\.i 0x0
+     6ec:	00 00 04 00       	            nop\.i 0x0;;
+     6f0:	01 80 03 00 00 21 	\[MII\]       mov r112=r0
+     6f6:	00 00 00 02 00 00 	            nop\.i 0x0
+     6fc:	00 00 04 00       	            nop\.i 0x0;;
+     700:	01 88 03 00 00 21 	\[MII\]       mov r113=r0
+     706:	00 00 00 02 00 00 	            nop\.i 0x0
+     70c:	00 00 04 00       	            nop\.i 0x0;;
+     710:	01 90 03 00 00 21 	\[MII\]       mov r114=r0
+     716:	00 00 00 02 00 00 	            nop\.i 0x0
+     71c:	00 00 04 00       	            nop\.i 0x0;;
+     720:	01 98 03 00 00 21 	\[MII\]       mov r115=r0
+     726:	00 00 00 02 00 00 	            nop\.i 0x0
+     72c:	00 00 04 00       	            nop\.i 0x0;;
+     730:	01 a0 03 00 00 21 	\[MII\]       mov r116=r0
+     736:	00 00 00 02 00 00 	            nop\.i 0x0
+     73c:	00 00 04 00       	            nop\.i 0x0;;
+     740:	01 a8 03 00 00 21 	\[MII\]       mov r117=r0
+     746:	00 00 00 02 00 00 	            nop\.i 0x0
+     74c:	00 00 04 00       	            nop\.i 0x0;;
+     750:	01 b0 03 00 00 21 	\[MII\]       mov r118=r0
+     756:	00 00 00 02 00 00 	            nop\.i 0x0
+     75c:	00 00 04 00       	            nop\.i 0x0;;
+     760:	01 b8 03 00 00 21 	\[MII\]       mov r119=r0
+     766:	00 00 00 02 00 00 	            nop\.i 0x0
+     76c:	00 00 04 00       	            nop\.i 0x0;;
+     770:	01 c0 03 00 00 21 	\[MII\]       mov r120=r0
+     776:	00 00 00 02 00 00 	            nop\.i 0x0
+     77c:	00 00 04 00       	            nop\.i 0x0;;
+     780:	01 c8 03 00 00 21 	\[MII\]       mov r121=r0
+     786:	00 00 00 02 00 00 	            nop\.i 0x0
+     78c:	00 00 04 00       	            nop\.i 0x0;;
+     790:	01 d0 03 00 00 21 	\[MII\]       mov r122=r0
+     796:	00 00 00 02 00 00 	            nop\.i 0x0
+     79c:	00 00 04 00       	            nop\.i 0x0;;
+     7a0:	01 d8 03 00 00 21 	\[MII\]       mov r123=r0
+     7a6:	00 00 00 02 00 00 	            nop\.i 0x0
+     7ac:	00 00 04 00       	            nop\.i 0x0;;
+     7b0:	01 e0 03 00 00 21 	\[MII\]       mov r124=r0
+     7b6:	00 00 00 02 00 00 	            nop\.i 0x0
+     7bc:	00 00 04 00       	            nop\.i 0x0;;
+     7c0:	01 e8 03 00 00 21 	\[MII\]       mov r125=r0
+     7c6:	00 00 00 02 00 00 	            nop\.i 0x0
+     7cc:	00 00 04 00       	            nop\.i 0x0;;
+     7d0:	01 f0 03 00 00 21 	\[MII\]       mov r126=r0
+     7d6:	00 00 00 02 00 00 	            nop\.i 0x0
+     7dc:	00 00 04 00       	            nop\.i 0x0;;
+     7e0:	01 f8 03 00 00 21 	\[MII\]       mov r127=r0
+     7e6:	00 00 00 02 00 00 	            nop\.i 0x0
+     7ec:	00 00 04 00       	            nop\.i 0x0;;
+     7f0:	01 00 01 00 00 21 	\[MII\]       mov r32=r0
+     7f6:	00 00 00 02 00 00 	            nop\.i 0x0
+     7fc:	00 00 04 00       	            nop\.i 0x0;;
+     800:	01 08 01 00 00 21 	\[MII\]       mov r33=r0
+     806:	00 00 00 02 00 00 	            nop\.i 0x0
+     80c:	00 00 04 00       	            nop\.i 0x0;;
+     810:	01 10 01 00 00 21 	\[MII\]       mov r34=r0
+     816:	00 00 00 02 00 00 	            nop\.i 0x0
+     81c:	00 00 04 00       	            nop\.i 0x0;;
+     820:	01 18 01 00 00 21 	\[MII\]       mov r35=r0
+     826:	00 00 00 02 00 00 	            nop\.i 0x0
+     82c:	00 00 04 00       	            nop\.i 0x0;;
+     830:	01 20 01 00 00 21 	\[MII\]       mov r36=r0
+     836:	00 00 00 02 00 00 	            nop\.i 0x0
+     83c:	00 00 04 00       	            nop\.i 0x0;;
+     840:	01 28 01 00 00 21 	\[MII\]       mov r37=r0
+     846:	00 00 00 02 00 00 	            nop\.i 0x0
+     84c:	00 00 04 00       	            nop\.i 0x0;;
+     850:	01 30 01 00 00 21 	\[MII\]       mov r38=r0
+     856:	00 00 00 02 00 00 	            nop\.i 0x0
+     85c:	00 00 04 00       	            nop\.i 0x0;;
+     860:	01 38 01 00 00 21 	\[MII\]       mov r39=r0
+     866:	00 00 00 02 00 00 	            nop\.i 0x0
+     86c:	00 00 04 00       	            nop\.i 0x0;;
+     870:	01 40 01 00 00 21 	\[MII\]       mov r40=r0
+     876:	00 00 00 02 00 00 	            nop\.i 0x0
+     87c:	00 00 04 00       	            nop\.i 0x0;;
+     880:	01 48 01 00 00 21 	\[MII\]       mov r41=r0
+     886:	00 00 00 02 00 00 	            nop\.i 0x0
+     88c:	00 00 04 00       	            nop\.i 0x0;;
+     890:	01 50 01 00 00 21 	\[MII\]       mov r42=r0
+     896:	00 00 00 02 00 00 	            nop\.i 0x0
+     89c:	00 00 04 00       	            nop\.i 0x0;;
+     8a0:	01 58 01 00 00 21 	\[MII\]       mov r43=r0
+     8a6:	00 00 00 02 00 00 	            nop\.i 0x0
+     8ac:	00 00 04 00       	            nop\.i 0x0;;
+     8b0:	01 60 01 00 00 21 	\[MII\]       mov r44=r0
+     8b6:	00 00 00 02 00 00 	            nop\.i 0x0
+     8bc:	00 00 04 00       	            nop\.i 0x0;;
+     8c0:	01 68 01 00 00 21 	\[MII\]       mov r45=r0
+     8c6:	00 00 00 02 00 00 	            nop\.i 0x0
+     8cc:	00 00 04 00       	            nop\.i 0x0;;
+     8d0:	01 70 01 00 00 21 	\[MII\]       mov r46=r0
+     8d6:	00 00 00 02 00 00 	            nop\.i 0x0
+     8dc:	00 00 04 00       	            nop\.i 0x0;;
+     8e0:	01 78 01 00 00 21 	\[MII\]       mov r47=r0
+     8e6:	00 00 00 02 00 00 	            nop\.i 0x0
+     8ec:	00 00 04 00       	            nop\.i 0x0;;
+     8f0:	01 80 01 00 00 21 	\[MII\]       mov r48=r0
+     8f6:	00 00 00 02 00 00 	            nop\.i 0x0
+     8fc:	00 00 04 00       	            nop\.i 0x0;;
+     900:	01 88 01 00 00 21 	\[MII\]       mov r49=r0
+     906:	00 00 00 02 00 00 	            nop\.i 0x0
+     90c:	00 00 04 00       	            nop\.i 0x0;;
+     910:	01 90 01 00 00 21 	\[MII\]       mov r50=r0
+     916:	00 00 00 02 00 00 	            nop\.i 0x0
+     91c:	00 00 04 00       	            nop\.i 0x0;;
+     920:	01 98 01 00 00 21 	\[MII\]       mov r51=r0
+     926:	00 00 00 02 00 00 	            nop\.i 0x0
+     92c:	00 00 04 00       	            nop\.i 0x0;;
+     930:	01 a0 01 00 00 21 	\[MII\]       mov r52=r0
+     936:	00 00 00 02 00 00 	            nop\.i 0x0
+     93c:	00 00 04 00       	            nop\.i 0x0;;
+     940:	01 a8 01 00 00 21 	\[MII\]       mov r53=r0
+     946:	00 00 00 02 00 00 	            nop\.i 0x0
+     94c:	00 00 04 00       	            nop\.i 0x0;;
+     950:	01 b0 01 00 00 21 	\[MII\]       mov r54=r0
+     956:	00 00 00 02 00 00 	            nop\.i 0x0
+     95c:	00 00 04 00       	            nop\.i 0x0;;
+     960:	01 b8 01 00 00 21 	\[MII\]       mov r55=r0
+     966:	00 00 00 02 00 00 	            nop\.i 0x0
+     96c:	00 00 04 00       	            nop\.i 0x0;;
+     970:	01 c0 01 00 00 21 	\[MII\]       mov r56=r0
+     976:	00 00 00 02 00 00 	            nop\.i 0x0
+     97c:	00 00 04 00       	            nop\.i 0x0;;
+     980:	01 c8 01 00 00 21 	\[MII\]       mov r57=r0
+     986:	00 00 00 02 00 00 	            nop\.i 0x0
+     98c:	00 00 04 00       	            nop\.i 0x0;;
+     990:	01 d0 01 00 00 21 	\[MII\]       mov r58=r0
+     996:	00 00 00 02 00 00 	            nop\.i 0x0
+     99c:	00 00 04 00       	            nop\.i 0x0;;
+     9a0:	01 d8 01 00 00 21 	\[MII\]       mov r59=r0
+     9a6:	00 00 00 02 00 00 	            nop\.i 0x0
+     9ac:	00 00 04 00       	            nop\.i 0x0;;
+     9b0:	01 e0 01 00 00 21 	\[MII\]       mov r60=r0
+     9b6:	00 00 00 02 00 00 	            nop\.i 0x0
+     9bc:	00 00 04 00       	            nop\.i 0x0;;
+     9c0:	01 e8 01 00 00 21 	\[MII\]       mov r61=r0
+     9c6:	00 00 00 02 00 00 	            nop\.i 0x0
+     9cc:	00 00 04 00       	            nop\.i 0x0;;
+     9d0:	01 f0 01 00 00 21 	\[MII\]       mov r62=r0
+     9d6:	00 00 00 02 00 00 	            nop\.i 0x0
+     9dc:	00 00 04 00       	            nop\.i 0x0;;
+     9e0:	01 f8 01 00 00 21 	\[MII\]       mov r63=r0
+     9e6:	00 00 00 02 00 00 	            nop\.i 0x0
+     9ec:	00 00 04 00       	            nop\.i 0x0;;
+     9f0:	01 00 02 00 00 21 	\[MII\]       mov r64=r0
+     9f6:	00 00 00 02 00 00 	            nop\.i 0x0
+     9fc:	00 00 04 00       	            nop\.i 0x0;;
+     a00:	01 08 02 00 00 21 	\[MII\]       mov r65=r0
+     a06:	00 00 00 02 00 00 	            nop\.i 0x0
+     a0c:	00 00 04 00       	            nop\.i 0x0;;
+     a10:	01 10 02 00 00 21 	\[MII\]       mov r66=r0
+     a16:	00 00 00 02 00 00 	            nop\.i 0x0
+     a1c:	00 00 04 00       	            nop\.i 0x0;;
+     a20:	01 18 02 00 00 21 	\[MII\]       mov r67=r0
+     a26:	00 00 00 02 00 00 	            nop\.i 0x0
+     a2c:	00 00 04 00       	            nop\.i 0x0;;
+     a30:	01 20 02 00 00 21 	\[MII\]       mov r68=r0
+     a36:	00 00 00 02 00 00 	            nop\.i 0x0
+     a3c:	00 00 04 00       	            nop\.i 0x0;;
+     a40:	01 28 02 00 00 21 	\[MII\]       mov r69=r0
+     a46:	00 00 00 02 00 00 	            nop\.i 0x0
+     a4c:	00 00 04 00       	            nop\.i 0x0;;
+     a50:	01 30 02 00 00 21 	\[MII\]       mov r70=r0
+     a56:	00 00 00 02 00 00 	            nop\.i 0x0
+     a5c:	00 00 04 00       	            nop\.i 0x0;;
+     a60:	01 38 02 00 00 21 	\[MII\]       mov r71=r0
+     a66:	00 00 00 02 00 00 	            nop\.i 0x0
+     a6c:	00 00 04 00       	            nop\.i 0x0;;
+     a70:	01 40 02 00 00 21 	\[MII\]       mov r72=r0
+     a76:	00 00 00 02 00 00 	            nop\.i 0x0
+     a7c:	00 00 04 00       	            nop\.i 0x0;;
+     a80:	01 48 02 00 00 21 	\[MII\]       mov r73=r0
+     a86:	00 00 00 02 00 00 	            nop\.i 0x0
+     a8c:	00 00 04 00       	            nop\.i 0x0;;
+     a90:	01 50 02 00 00 21 	\[MII\]       mov r74=r0
+     a96:	00 00 00 02 00 00 	            nop\.i 0x0
+     a9c:	00 00 04 00       	            nop\.i 0x0;;
+     aa0:	01 58 02 00 00 21 	\[MII\]       mov r75=r0
+     aa6:	00 00 00 02 00 00 	            nop\.i 0x0
+     aac:	00 00 04 00       	            nop\.i 0x0;;
+     ab0:	01 60 02 00 00 21 	\[MII\]       mov r76=r0
+     ab6:	00 00 00 02 00 00 	            nop\.i 0x0
+     abc:	00 00 04 00       	            nop\.i 0x0;;
+     ac0:	01 68 02 00 00 21 	\[MII\]       mov r77=r0
+     ac6:	00 00 00 02 00 00 	            nop\.i 0x0
+     acc:	00 00 04 00       	            nop\.i 0x0;;
+     ad0:	01 70 02 00 00 21 	\[MII\]       mov r78=r0
+     ad6:	00 00 00 02 00 00 	            nop\.i 0x0
+     adc:	00 00 04 00       	            nop\.i 0x0;;
+     ae0:	01 78 02 00 00 21 	\[MII\]       mov r79=r0
+     ae6:	00 00 00 02 00 00 	            nop\.i 0x0
+     aec:	00 00 04 00       	            nop\.i 0x0;;
+     af0:	01 80 02 00 00 21 	\[MII\]       mov r80=r0
+     af6:	00 00 00 02 00 00 	            nop\.i 0x0
+     afc:	00 00 04 00       	            nop\.i 0x0;;
+     b00:	01 88 02 00 00 21 	\[MII\]       mov r81=r0
+     b06:	00 00 00 02 00 00 	            nop\.i 0x0
+     b0c:	00 00 04 00       	            nop\.i 0x0;;
+     b10:	01 90 02 00 00 21 	\[MII\]       mov r82=r0
+     b16:	00 00 00 02 00 00 	            nop\.i 0x0
+     b1c:	00 00 04 00       	            nop\.i 0x0;;
+     b20:	01 98 02 00 00 21 	\[MII\]       mov r83=r0
+     b26:	00 00 00 02 00 00 	            nop\.i 0x0
+     b2c:	00 00 04 00       	            nop\.i 0x0;;
+     b30:	01 a0 02 00 00 21 	\[MII\]       mov r84=r0
+     b36:	00 00 00 02 00 00 	            nop\.i 0x0
+     b3c:	00 00 04 00       	            nop\.i 0x0;;
+     b40:	01 a8 02 00 00 21 	\[MII\]       mov r85=r0
+     b46:	00 00 00 02 00 00 	            nop\.i 0x0
+     b4c:	00 00 04 00       	            nop\.i 0x0;;
+     b50:	01 b0 02 00 00 21 	\[MII\]       mov r86=r0
+     b56:	00 00 00 02 00 00 	            nop\.i 0x0
+     b5c:	00 00 04 00       	            nop\.i 0x0;;
+     b60:	01 b8 02 00 00 21 	\[MII\]       mov r87=r0
+     b66:	00 00 00 02 00 00 	            nop\.i 0x0
+     b6c:	00 00 04 00       	            nop\.i 0x0;;
+     b70:	01 c0 02 00 00 21 	\[MII\]       mov r88=r0
+     b76:	00 00 00 02 00 00 	            nop\.i 0x0
+     b7c:	00 00 04 00       	            nop\.i 0x0;;
+     b80:	01 c8 02 00 00 21 	\[MII\]       mov r89=r0
+     b86:	00 00 00 02 00 00 	            nop\.i 0x0
+     b8c:	00 00 04 00       	            nop\.i 0x0;;
+     b90:	01 d0 02 00 00 21 	\[MII\]       mov r90=r0
+     b96:	00 00 00 02 00 00 	            nop\.i 0x0
+     b9c:	00 00 04 00       	            nop\.i 0x0;;
+     ba0:	01 d8 02 00 00 21 	\[MII\]       mov r91=r0
+     ba6:	00 00 00 02 00 00 	            nop\.i 0x0
+     bac:	00 00 04 00       	            nop\.i 0x0;;
+     bb0:	01 e0 02 00 00 21 	\[MII\]       mov r92=r0
+     bb6:	00 00 00 02 00 00 	            nop\.i 0x0
+     bbc:	00 00 04 00       	            nop\.i 0x0;;
+     bc0:	01 e8 02 00 00 21 	\[MII\]       mov r93=r0
+     bc6:	00 00 00 02 00 00 	            nop\.i 0x0
+     bcc:	00 00 04 00       	            nop\.i 0x0;;
+     bd0:	01 f0 02 00 00 21 	\[MII\]       mov r94=r0
+     bd6:	00 00 00 02 00 00 	            nop\.i 0x0
+     bdc:	00 00 04 00       	            nop\.i 0x0;;
+     be0:	01 f8 02 00 00 21 	\[MII\]       mov r95=r0
+     be6:	00 00 00 02 00 00 	            nop\.i 0x0
+     bec:	00 00 04 00       	            nop\.i 0x0;;
+     bf0:	01 00 03 00 00 21 	\[MII\]       mov r96=r0
+     bf6:	00 00 00 02 00 00 	            nop\.i 0x0
+     bfc:	00 00 04 00       	            nop\.i 0x0;;
+     c00:	01 08 03 00 00 21 	\[MII\]       mov r97=r0
+     c06:	00 00 00 02 00 00 	            nop\.i 0x0
+     c0c:	00 00 04 00       	            nop\.i 0x0;;
+     c10:	01 10 03 00 00 21 	\[MII\]       mov r98=r0
+     c16:	00 00 00 02 00 00 	            nop\.i 0x0
+     c1c:	00 00 04 00       	            nop\.i 0x0;;
+     c20:	01 18 03 00 00 21 	\[MII\]       mov r99=r0
+     c26:	00 00 00 02 00 00 	            nop\.i 0x0
+     c2c:	00 00 04 00       	            nop\.i 0x0;;
+     c30:	01 20 03 00 00 21 	\[MII\]       mov r100=r0
+     c36:	00 00 00 02 00 00 	            nop\.i 0x0
+     c3c:	00 00 04 00       	            nop\.i 0x0;;
+     c40:	01 28 03 00 00 21 	\[MII\]       mov r101=r0
+     c46:	00 00 00 02 00 00 	            nop\.i 0x0
+     c4c:	00 00 04 00       	            nop\.i 0x0;;
+     c50:	01 30 03 00 00 21 	\[MII\]       mov r102=r0
+     c56:	00 00 00 02 00 00 	            nop\.i 0x0
+     c5c:	00 00 04 00       	            nop\.i 0x0;;
+     c60:	01 38 03 00 00 21 	\[MII\]       mov r103=r0
+     c66:	00 00 00 02 00 00 	            nop\.i 0x0
+     c6c:	00 00 04 00       	            nop\.i 0x0;;
+     c70:	01 40 03 00 00 21 	\[MII\]       mov r104=r0
+     c76:	00 00 00 02 00 00 	            nop\.i 0x0
+     c7c:	00 00 04 00       	            nop\.i 0x0;;
+     c80:	01 48 03 00 00 21 	\[MII\]       mov r105=r0
+     c86:	00 00 00 02 00 00 	            nop\.i 0x0
+     c8c:	00 00 04 00       	            nop\.i 0x0;;
+     c90:	01 50 03 00 00 21 	\[MII\]       mov r106=r0
+     c96:	00 00 00 02 00 00 	            nop\.i 0x0
+     c9c:	00 00 04 00       	            nop\.i 0x0;;
+     ca0:	01 58 03 00 00 21 	\[MII\]       mov r107=r0
+     ca6:	00 00 00 02 00 00 	            nop\.i 0x0
+     cac:	00 00 04 00       	            nop\.i 0x0;;
+     cb0:	01 60 03 00 00 21 	\[MII\]       mov r108=r0
+     cb6:	00 00 00 02 00 00 	            nop\.i 0x0
+     cbc:	00 00 04 00       	            nop\.i 0x0;;
+     cc0:	01 68 03 00 00 21 	\[MII\]       mov r109=r0
+     cc6:	00 00 00 02 00 00 	            nop\.i 0x0
+     ccc:	00 00 04 00       	            nop\.i 0x0;;
+     cd0:	01 70 03 00 00 21 	\[MII\]       mov r110=r0
+     cd6:	00 00 00 02 00 00 	            nop\.i 0x0
+     cdc:	00 00 04 00       	            nop\.i 0x0;;
+     ce0:	01 78 03 00 00 21 	\[MII\]       mov r111=r0
+     ce6:	00 00 00 02 00 00 	            nop\.i 0x0
+     cec:	00 00 04 00       	            nop\.i 0x0;;
+     cf0:	01 80 03 00 00 21 	\[MII\]       mov r112=r0
+     cf6:	00 00 00 02 00 00 	            nop\.i 0x0
+     cfc:	00 00 04 00       	            nop\.i 0x0;;
+     d00:	01 88 03 00 00 21 	\[MII\]       mov r113=r0
+     d06:	00 00 00 02 00 00 	            nop\.i 0x0
+     d0c:	00 00 04 00       	            nop\.i 0x0;;
+     d10:	01 90 03 00 00 21 	\[MII\]       mov r114=r0
+     d16:	00 00 00 02 00 00 	            nop\.i 0x0
+     d1c:	00 00 04 00       	            nop\.i 0x0;;
+     d20:	01 98 03 00 00 21 	\[MII\]       mov r115=r0
+     d26:	00 00 00 02 00 00 	            nop\.i 0x0
+     d2c:	00 00 04 00       	            nop\.i 0x0;;
+     d30:	01 a0 03 00 00 21 	\[MII\]       mov r116=r0
+     d36:	00 00 00 02 00 00 	            nop\.i 0x0
+     d3c:	00 00 04 00       	            nop\.i 0x0;;
+     d40:	01 a8 03 00 00 21 	\[MII\]       mov r117=r0
+     d46:	00 00 00 02 00 00 	            nop\.i 0x0
+     d4c:	00 00 04 00       	            nop\.i 0x0;;
+     d50:	01 b0 03 00 00 21 	\[MII\]       mov r118=r0
+     d56:	00 00 00 02 00 00 	            nop\.i 0x0
+     d5c:	00 00 04 00       	            nop\.i 0x0;;
+     d60:	01 b8 03 00 00 21 	\[MII\]       mov r119=r0
+     d66:	00 00 00 02 00 00 	            nop\.i 0x0
+     d6c:	00 00 04 00       	            nop\.i 0x0;;
+     d70:	01 c0 03 00 00 21 	\[MII\]       mov r120=r0
+     d76:	00 00 00 02 00 00 	            nop\.i 0x0
+     d7c:	00 00 04 00       	            nop\.i 0x0;;
+     d80:	01 c8 03 00 00 21 	\[MII\]       mov r121=r0
+     d86:	00 00 00 02 00 00 	            nop\.i 0x0
+     d8c:	00 00 04 00       	            nop\.i 0x0;;
+     d90:	01 d0 03 00 00 21 	\[MII\]       mov r122=r0
+     d96:	00 00 00 02 00 00 	            nop\.i 0x0
+     d9c:	00 00 04 00       	            nop\.i 0x0;;
+     da0:	01 d8 03 00 00 21 	\[MII\]       mov r123=r0
+     da6:	00 00 00 02 00 00 	            nop\.i 0x0
+     dac:	00 00 04 00       	            nop\.i 0x0;;
+     db0:	01 e0 03 00 00 21 	\[MII\]       mov r124=r0
+     db6:	00 00 00 02 00 00 	            nop\.i 0x0
+     dbc:	00 00 04 00       	            nop\.i 0x0;;
+     dc0:	01 e8 03 00 00 21 	\[MII\]       mov r125=r0
+     dc6:	00 00 00 02 00 00 	            nop\.i 0x0
+     dcc:	00 00 04 00       	            nop\.i 0x0;;
+     dd0:	01 f0 03 00 00 21 	\[MII\]       mov r126=r0
+     dd6:	00 00 00 02 00 00 	            nop\.i 0x0
+     ddc:	00 00 04 00       	            nop\.i 0x0;;
+     de0:	01 f8 03 00 00 21 	\[MII\]       mov r127=r0
+     de6:	00 00 00 02 00 00 	            nop\.i 0x0
+     dec:	00 00 04 00       	            nop\.i 0x0;;
+     df0:	01 00 01 00 00 21 	\[MII\]       mov r32=r0
+     df6:	00 00 00 02 00 00 	            nop\.i 0x0
+     dfc:	00 00 04 00       	            nop\.i 0x0;;
+     e00:	01 08 01 00 00 21 	\[MII\]       mov r33=r0
+     e06:	00 00 00 02 00 00 	            nop\.i 0x0
+     e0c:	00 00 04 00       	            nop\.i 0x0;;
+     e10:	01 10 01 00 00 21 	\[MII\]       mov r34=r0
+     e16:	00 00 00 02 00 00 	            nop\.i 0x0
+     e1c:	00 00 04 00       	            nop\.i 0x0;;
+     e20:	01 18 01 00 00 21 	\[MII\]       mov r35=r0
+     e26:	00 00 00 02 00 00 	            nop\.i 0x0
+     e2c:	00 00 04 00       	            nop\.i 0x0;;
+     e30:	01 20 01 00 00 21 	\[MII\]       mov r36=r0
+     e36:	00 00 00 02 00 00 	            nop\.i 0x0
+     e3c:	00 00 04 00       	            nop\.i 0x0;;
+     e40:	01 28 01 00 00 21 	\[MII\]       mov r37=r0
+     e46:	00 00 00 02 00 00 	            nop\.i 0x0
+     e4c:	00 00 04 00       	            nop\.i 0x0;;
+     e50:	01 30 01 00 00 21 	\[MII\]       mov r38=r0
+     e56:	00 00 00 02 00 00 	            nop\.i 0x0
+     e5c:	00 00 04 00       	            nop\.i 0x0;;
+     e60:	01 38 01 00 00 21 	\[MII\]       mov r39=r0
+     e66:	00 00 00 02 00 00 	            nop\.i 0x0
+     e6c:	00 00 04 00       	            nop\.i 0x0;;
+     e70:	01 40 01 00 00 21 	\[MII\]       mov r40=r0
+     e76:	00 00 00 02 00 00 	            nop\.i 0x0
+     e7c:	00 00 04 00       	            nop\.i 0x0;;
+     e80:	01 48 01 00 00 21 	\[MII\]       mov r41=r0
+     e86:	00 00 00 02 00 00 	            nop\.i 0x0
+     e8c:	00 00 04 00       	            nop\.i 0x0;;
+     e90:	01 50 01 00 00 21 	\[MII\]       mov r42=r0
+     e96:	00 00 00 02 00 00 	            nop\.i 0x0
+     e9c:	00 00 04 00       	            nop\.i 0x0;;
+     ea0:	01 58 01 00 00 21 	\[MII\]       mov r43=r0
+     ea6:	00 00 00 02 00 00 	            nop\.i 0x0
+     eac:	00 00 04 00       	            nop\.i 0x0;;
+     eb0:	01 60 01 00 00 21 	\[MII\]       mov r44=r0
+     eb6:	00 00 00 02 00 00 	            nop\.i 0x0
+     ebc:	00 00 04 00       	            nop\.i 0x0;;
+     ec0:	01 68 01 00 00 21 	\[MII\]       mov r45=r0
+     ec6:	00 00 00 02 00 00 	            nop\.i 0x0
+     ecc:	00 00 04 00       	            nop\.i 0x0;;
+     ed0:	01 70 01 00 00 21 	\[MII\]       mov r46=r0
+     ed6:	00 00 00 02 00 00 	            nop\.i 0x0
+     edc:	00 00 04 00       	            nop\.i 0x0;;
+     ee0:	01 78 01 00 00 21 	\[MII\]       mov r47=r0
+     ee6:	00 00 00 02 00 00 	            nop\.i 0x0
+     eec:	00 00 04 00       	            nop\.i 0x0;;
+     ef0:	01 80 01 00 00 21 	\[MII\]       mov r48=r0
+     ef6:	00 00 00 02 00 00 	            nop\.i 0x0
+     efc:	00 00 04 00       	            nop\.i 0x0;;
+     f00:	01 88 01 00 00 21 	\[MII\]       mov r49=r0
+     f06:	00 00 00 02 00 00 	            nop\.i 0x0
+     f0c:	00 00 04 00       	            nop\.i 0x0;;
+     f10:	01 90 01 00 00 21 	\[MII\]       mov r50=r0
+     f16:	00 00 00 02 00 00 	            nop\.i 0x0
+     f1c:	00 00 04 00       	            nop\.i 0x0;;
+     f20:	01 98 01 00 00 21 	\[MII\]       mov r51=r0
+     f26:	00 00 00 02 00 00 	            nop\.i 0x0
+     f2c:	00 00 04 00       	            nop\.i 0x0;;
+     f30:	01 a0 01 00 00 21 	\[MII\]       mov r52=r0
+     f36:	00 00 00 02 00 00 	            nop\.i 0x0
+     f3c:	00 00 04 00       	            nop\.i 0x0;;
+     f40:	01 a8 01 00 00 21 	\[MII\]       mov r53=r0
+     f46:	00 00 00 02 00 00 	            nop\.i 0x0
+     f4c:	00 00 04 00       	            nop\.i 0x0;;
+     f50:	01 b0 01 00 00 21 	\[MII\]       mov r54=r0
+     f56:	00 00 00 02 00 00 	            nop\.i 0x0
+     f5c:	00 00 04 00       	            nop\.i 0x0;;
+     f60:	01 b8 01 00 00 21 	\[MII\]       mov r55=r0
+     f66:	00 00 00 02 00 00 	            nop\.i 0x0
+     f6c:	00 00 04 00       	            nop\.i 0x0;;
+     f70:	01 c0 01 00 00 21 	\[MII\]       mov r56=r0
+     f76:	00 00 00 02 00 00 	            nop\.i 0x0
+     f7c:	00 00 04 00       	            nop\.i 0x0;;
+     f80:	01 c8 01 00 00 21 	\[MII\]       mov r57=r0
+     f86:	00 00 00 02 00 00 	            nop\.i 0x0
+     f8c:	00 00 04 00       	            nop\.i 0x0;;
+     f90:	01 d0 01 00 00 21 	\[MII\]       mov r58=r0
+     f96:	00 00 00 02 00 00 	            nop\.i 0x0
+     f9c:	00 00 04 00       	            nop\.i 0x0;;
+     fa0:	01 d8 01 00 00 21 	\[MII\]       mov r59=r0
+     fa6:	00 00 00 02 00 00 	            nop\.i 0x0
+     fac:	00 00 04 00       	            nop\.i 0x0;;
+     fb0:	01 e0 01 00 00 21 	\[MII\]       mov r60=r0
+     fb6:	00 00 00 02 00 00 	            nop\.i 0x0
+     fbc:	00 00 04 00       	            nop\.i 0x0;;
+     fc0:	01 e8 01 00 00 21 	\[MII\]       mov r61=r0
+     fc6:	00 00 00 02 00 00 	            nop\.i 0x0
+     fcc:	00 00 04 00       	            nop\.i 0x0;;
+     fd0:	01 f0 01 00 00 21 	\[MII\]       mov r62=r0
+     fd6:	00 00 00 02 00 00 	            nop\.i 0x0
+     fdc:	00 00 04 00       	            nop\.i 0x0;;
+     fe0:	01 f8 01 00 00 21 	\[MII\]       mov r63=r0
+     fe6:	00 00 00 02 00 00 	            nop\.i 0x0
+     fec:	00 00 04 00       	            nop\.i 0x0;;
+     ff0:	01 00 02 00 00 21 	\[MII\]       mov r64=r0
+     ff6:	00 00 00 02 00 00 	            nop\.i 0x0
+     ffc:	00 00 04 00       	            nop\.i 0x0;;
+    1000:	01 08 02 00 00 21 	\[MII\]       mov r65=r0
+    1006:	00 00 00 02 00 00 	            nop\.i 0x0
+    100c:	00 00 04 00       	            nop\.i 0x0;;
+    1010:	01 10 02 00 00 21 	\[MII\]       mov r66=r0
+    1016:	00 00 00 02 00 00 	            nop\.i 0x0
+    101c:	00 00 04 00       	            nop\.i 0x0;;
+    1020:	01 18 02 00 00 21 	\[MII\]       mov r67=r0
+    1026:	00 00 00 02 00 00 	            nop\.i 0x0
+    102c:	00 00 04 00       	            nop\.i 0x0;;
+    1030:	01 20 02 00 00 21 	\[MII\]       mov r68=r0
+    1036:	00 00 00 02 00 00 	            nop\.i 0x0
+    103c:	00 00 04 00       	            nop\.i 0x0;;
+    1040:	01 28 02 00 00 21 	\[MII\]       mov r69=r0
+    1046:	00 00 00 02 00 00 	            nop\.i 0x0
+    104c:	00 00 04 00       	            nop\.i 0x0;;
+    1050:	01 30 02 00 00 21 	\[MII\]       mov r70=r0
+    1056:	00 00 00 02 00 00 	            nop\.i 0x0
+    105c:	00 00 04 00       	            nop\.i 0x0;;
+    1060:	01 38 02 00 00 21 	\[MII\]       mov r71=r0
+    1066:	00 00 00 02 00 00 	            nop\.i 0x0
+    106c:	00 00 04 00       	            nop\.i 0x0;;
+    1070:	01 40 02 00 00 21 	\[MII\]       mov r72=r0
+    1076:	00 00 00 02 00 00 	            nop\.i 0x0
+    107c:	00 00 04 00       	            nop\.i 0x0;;
+    1080:	01 48 02 00 00 21 	\[MII\]       mov r73=r0
+    1086:	00 00 00 02 00 00 	            nop\.i 0x0
+    108c:	00 00 04 00       	            nop\.i 0x0;;
+    1090:	01 50 02 00 00 21 	\[MII\]       mov r74=r0
+    1096:	00 00 00 02 00 00 	            nop\.i 0x0
+    109c:	00 00 04 00       	            nop\.i 0x0;;
+    10a0:	01 58 02 00 00 21 	\[MII\]       mov r75=r0
+    10a6:	00 00 00 02 00 00 	            nop\.i 0x0
+    10ac:	00 00 04 00       	            nop\.i 0x0;;
+    10b0:	01 60 02 00 00 21 	\[MII\]       mov r76=r0
+    10b6:	00 00 00 02 00 00 	            nop\.i 0x0
+    10bc:	00 00 04 00       	            nop\.i 0x0;;
+    10c0:	01 68 02 00 00 21 	\[MII\]       mov r77=r0
+    10c6:	00 00 00 02 00 00 	            nop\.i 0x0
+    10cc:	00 00 04 00       	            nop\.i 0x0;;
+    10d0:	01 70 02 00 00 21 	\[MII\]       mov r78=r0
+    10d6:	00 00 00 02 00 00 	            nop\.i 0x0
+    10dc:	00 00 04 00       	            nop\.i 0x0;;
+    10e0:	01 78 02 00 00 21 	\[MII\]       mov r79=r0
+    10e6:	00 00 00 02 00 00 	            nop\.i 0x0
+    10ec:	00 00 04 00       	            nop\.i 0x0;;
+    10f0:	01 80 02 00 00 21 	\[MII\]       mov r80=r0
+    10f6:	00 00 00 02 00 00 	            nop\.i 0x0
+    10fc:	00 00 04 00       	            nop\.i 0x0;;
+    1100:	01 88 02 00 00 21 	\[MII\]       mov r81=r0
+    1106:	00 00 00 02 00 00 	            nop\.i 0x0
+    110c:	00 00 04 00       	            nop\.i 0x0;;
+    1110:	01 90 02 00 00 21 	\[MII\]       mov r82=r0
+    1116:	00 00 00 02 00 00 	            nop\.i 0x0
+    111c:	00 00 04 00       	            nop\.i 0x0;;
+    1120:	01 98 02 00 00 21 	\[MII\]       mov r83=r0
+    1126:	00 00 00 02 00 00 	            nop\.i 0x0
+    112c:	00 00 04 00       	            nop\.i 0x0;;
+    1130:	01 a0 02 00 00 21 	\[MII\]       mov r84=r0
+    1136:	00 00 00 02 00 00 	            nop\.i 0x0
+    113c:	00 00 04 00       	            nop\.i 0x0;;
+    1140:	01 a8 02 00 00 21 	\[MII\]       mov r85=r0
+    1146:	00 00 00 02 00 00 	            nop\.i 0x0
+    114c:	00 00 04 00       	            nop\.i 0x0;;
+    1150:	01 b0 02 00 00 21 	\[MII\]       mov r86=r0
+    1156:	00 00 00 02 00 00 	            nop\.i 0x0
+    115c:	00 00 04 00       	            nop\.i 0x0;;
+    1160:	01 b8 02 00 00 21 	\[MII\]       mov r87=r0
+    1166:	00 00 00 02 00 00 	            nop\.i 0x0
+    116c:	00 00 04 00       	            nop\.i 0x0;;
+    1170:	01 c0 02 00 00 21 	\[MII\]       mov r88=r0
+    1176:	00 00 00 02 00 00 	            nop\.i 0x0
+    117c:	00 00 04 00       	            nop\.i 0x0;;
+    1180:	01 c8 02 00 00 21 	\[MII\]       mov r89=r0
+    1186:	00 00 00 02 00 00 	            nop\.i 0x0
+    118c:	00 00 04 00       	            nop\.i 0x0;;
+    1190:	01 d0 02 00 00 21 	\[MII\]       mov r90=r0
+    1196:	00 00 00 02 00 00 	            nop\.i 0x0
+    119c:	00 00 04 00       	            nop\.i 0x0;;
+    11a0:	01 d8 02 00 00 21 	\[MII\]       mov r91=r0
+    11a6:	00 00 00 02 00 00 	            nop\.i 0x0
+    11ac:	00 00 04 00       	            nop\.i 0x0;;
+    11b0:	01 e0 02 00 00 21 	\[MII\]       mov r92=r0
+    11b6:	00 00 00 02 00 00 	            nop\.i 0x0
+    11bc:	00 00 04 00       	            nop\.i 0x0;;
+    11c0:	01 e8 02 00 00 21 	\[MII\]       mov r93=r0
+    11c6:	00 00 00 02 00 00 	            nop\.i 0x0
+    11cc:	00 00 04 00       	            nop\.i 0x0;;
+    11d0:	01 f0 02 00 00 21 	\[MII\]       mov r94=r0
+    11d6:	00 00 00 02 00 00 	            nop\.i 0x0
+    11dc:	00 00 04 00       	            nop\.i 0x0;;
+    11e0:	01 f8 02 00 00 21 	\[MII\]       mov r95=r0
+    11e6:	00 00 00 02 00 00 	            nop\.i 0x0
+    11ec:	00 00 04 00       	            nop\.i 0x0;;
+    11f0:	01 00 03 00 00 21 	\[MII\]       mov r96=r0
+    11f6:	00 00 00 02 00 00 	            nop\.i 0x0
+    11fc:	00 00 04 00       	            nop\.i 0x0;;
+    1200:	01 08 03 00 00 21 	\[MII\]       mov r97=r0
+    1206:	00 00 00 02 00 00 	            nop\.i 0x0
+    120c:	00 00 04 00       	            nop\.i 0x0;;
+    1210:	01 10 03 00 00 21 	\[MII\]       mov r98=r0
+    1216:	00 00 00 02 00 00 	            nop\.i 0x0
+    121c:	00 00 04 00       	            nop\.i 0x0;;
+    1220:	01 18 03 00 00 21 	\[MII\]       mov r99=r0
+    1226:	00 00 00 02 00 00 	            nop\.i 0x0
+    122c:	00 00 04 00       	            nop\.i 0x0;;
+    1230:	01 20 03 00 00 21 	\[MII\]       mov r100=r0
+    1236:	00 00 00 02 00 00 	            nop\.i 0x0
+    123c:	00 00 04 00       	            nop\.i 0x0;;
+    1240:	01 28 03 00 00 21 	\[MII\]       mov r101=r0
+    1246:	00 00 00 02 00 00 	            nop\.i 0x0
+    124c:	00 00 04 00       	            nop\.i 0x0;;
+    1250:	01 30 03 00 00 21 	\[MII\]       mov r102=r0
+    1256:	00 00 00 02 00 00 	            nop\.i 0x0
+    125c:	00 00 04 00       	            nop\.i 0x0;;
+    1260:	01 38 03 00 00 21 	\[MII\]       mov r103=r0
+    1266:	00 00 00 02 00 00 	            nop\.i 0x0
+    126c:	00 00 04 00       	            nop\.i 0x0;;
+    1270:	01 40 03 00 00 21 	\[MII\]       mov r104=r0
+    1276:	00 00 00 02 00 00 	            nop\.i 0x0
+    127c:	00 00 04 00       	            nop\.i 0x0;;
+    1280:	01 48 03 00 00 21 	\[MII\]       mov r105=r0
+    1286:	00 00 00 02 00 00 	            nop\.i 0x0
+    128c:	00 00 04 00       	            nop\.i 0x0;;
+    1290:	01 50 03 00 00 21 	\[MII\]       mov r106=r0
+    1296:	00 00 00 02 00 00 	            nop\.i 0x0
+    129c:	00 00 04 00       	            nop\.i 0x0;;
+    12a0:	01 58 03 00 00 21 	\[MII\]       mov r107=r0
+    12a6:	00 00 00 02 00 00 	            nop\.i 0x0
+    12ac:	00 00 04 00       	            nop\.i 0x0;;
+    12b0:	01 60 03 00 00 21 	\[MII\]       mov r108=r0
+    12b6:	00 00 00 02 00 00 	            nop\.i 0x0
+    12bc:	00 00 04 00       	            nop\.i 0x0;;
+    12c0:	01 68 03 00 00 21 	\[MII\]       mov r109=r0
+    12c6:	00 00 00 02 00 00 	            nop\.i 0x0
+    12cc:	00 00 04 00       	            nop\.i 0x0;;
+    12d0:	01 70 03 00 00 21 	\[MII\]       mov r110=r0
+    12d6:	00 00 00 02 00 00 	            nop\.i 0x0
+    12dc:	00 00 04 00       	            nop\.i 0x0;;
+    12e0:	01 78 03 00 00 21 	\[MII\]       mov r111=r0
+    12e6:	00 00 00 02 00 00 	            nop\.i 0x0
+    12ec:	00 00 04 00       	            nop\.i 0x0;;
+    12f0:	01 80 03 00 00 21 	\[MII\]       mov r112=r0
+    12f6:	00 00 00 02 00 00 	            nop\.i 0x0
+    12fc:	00 00 04 00       	            nop\.i 0x0;;
+    1300:	01 88 03 00 00 21 	\[MII\]       mov r113=r0
+    1306:	00 00 00 02 00 00 	            nop\.i 0x0
+    130c:	00 00 04 00       	            nop\.i 0x0;;
+    1310:	01 90 03 00 00 21 	\[MII\]       mov r114=r0
+    1316:	00 00 00 02 00 00 	            nop\.i 0x0
+    131c:	00 00 04 00       	            nop\.i 0x0;;
+    1320:	01 98 03 00 00 21 	\[MII\]       mov r115=r0
+    1326:	00 00 00 02 00 00 	            nop\.i 0x0
+    132c:	00 00 04 00       	            nop\.i 0x0;;
+    1330:	01 a0 03 00 00 21 	\[MII\]       mov r116=r0
+    1336:	00 00 00 02 00 00 	            nop\.i 0x0
+    133c:	00 00 04 00       	            nop\.i 0x0;;
+    1340:	01 a8 03 00 00 21 	\[MII\]       mov r117=r0
+    1346:	00 00 00 02 00 00 	            nop\.i 0x0
+    134c:	00 00 04 00       	            nop\.i 0x0;;
+    1350:	01 b0 03 00 00 21 	\[MII\]       mov r118=r0
+    1356:	00 00 00 02 00 00 	            nop\.i 0x0
+    135c:	00 00 04 00       	            nop\.i 0x0;;
+    1360:	01 b8 03 00 00 21 	\[MII\]       mov r119=r0
+    1366:	00 00 00 02 00 00 	            nop\.i 0x0
+    136c:	00 00 04 00       	            nop\.i 0x0;;
+    1370:	01 c0 03 00 00 21 	\[MII\]       mov r120=r0
+    1376:	00 00 00 02 00 00 	            nop\.i 0x0
+    137c:	00 00 04 00       	            nop\.i 0x0;;
+    1380:	01 c8 03 00 00 21 	\[MII\]       mov r121=r0
+    1386:	00 00 00 02 00 00 	            nop\.i 0x0
+    138c:	00 00 04 00       	            nop\.i 0x0;;
+    1390:	01 d0 03 00 00 21 	\[MII\]       mov r122=r0
+    1396:	00 00 00 02 00 00 	            nop\.i 0x0
+    139c:	00 00 04 00       	            nop\.i 0x0;;
+    13a0:	01 d8 03 00 00 21 	\[MII\]       mov r123=r0
+    13a6:	00 00 00 02 00 00 	            nop\.i 0x0
+    13ac:	00 00 04 00       	            nop\.i 0x0;;
+    13b0:	01 e0 03 00 00 21 	\[MII\]       mov r124=r0
+    13b6:	00 00 00 02 00 00 	            nop\.i 0x0
+    13bc:	00 00 04 00       	            nop\.i 0x0;;
+    13c0:	01 e8 03 00 00 21 	\[MII\]       mov r125=r0
+    13c6:	00 00 00 02 00 00 	            nop\.i 0x0
+    13cc:	00 00 04 00       	            nop\.i 0x0;;
+    13d0:	01 f0 03 00 00 21 	\[MII\]       mov r126=r0
+    13d6:	00 00 00 02 00 00 	            nop\.i 0x0
+    13dc:	00 00 04 00       	            nop\.i 0x0;;
+    13e0:	01 f8 03 00 00 21 	\[MII\]       mov r127=r0
+    13e6:	00 00 00 02 00 00 	            nop\.i 0x0
+    13ec:	00 00 04 00       	            nop\.i 0x0;;
+    13f0:	01 00 01 00 00 21 	\[MII\]       mov r32=r0
+    13f6:	00 00 00 02 00 00 	            nop\.i 0x0
+    13fc:	00 00 04 00       	            nop\.i 0x0;;
+    1400:	01 08 01 00 00 21 	\[MII\]       mov r33=r0
+    1406:	00 00 00 02 00 00 	            nop\.i 0x0
+    140c:	00 00 04 00       	            nop\.i 0x0;;
+    1410:	01 10 01 00 00 21 	\[MII\]       mov r34=r0
+    1416:	00 00 00 02 00 00 	            nop\.i 0x0
+    141c:	00 00 04 00       	            nop\.i 0x0;;
+    1420:	01 18 01 00 00 21 	\[MII\]       mov r35=r0
+    1426:	00 00 00 02 00 00 	            nop\.i 0x0
+    142c:	00 00 04 00       	            nop\.i 0x0;;
+    1430:	01 20 01 00 00 21 	\[MII\]       mov r36=r0
+    1436:	00 00 00 02 00 00 	            nop\.i 0x0
+    143c:	00 00 04 00       	            nop\.i 0x0;;
+    1440:	01 28 01 00 00 21 	\[MII\]       mov r37=r0
+    1446:	00 00 00 02 00 00 	            nop\.i 0x0
+    144c:	00 00 04 00       	            nop\.i 0x0;;
+    1450:	01 30 01 00 00 21 	\[MII\]       mov r38=r0
+    1456:	00 00 00 02 00 00 	            nop\.i 0x0
+    145c:	00 00 04 00       	            nop\.i 0x0;;
+    1460:	01 38 01 00 00 21 	\[MII\]       mov r39=r0
+    1466:	00 00 00 02 00 00 	            nop\.i 0x0
+    146c:	00 00 04 00       	            nop\.i 0x0;;
+    1470:	01 40 01 00 00 21 	\[MII\]       mov r40=r0
+    1476:	00 00 00 02 00 00 	            nop\.i 0x0
+    147c:	00 00 04 00       	            nop\.i 0x0;;
+    1480:	01 48 01 00 00 21 	\[MII\]       mov r41=r0
+    1486:	00 00 00 02 00 00 	            nop\.i 0x0
+    148c:	00 00 04 00       	            nop\.i 0x0;;
+    1490:	01 50 01 00 00 21 	\[MII\]       mov r42=r0
+    1496:	00 00 00 02 00 00 	            nop\.i 0x0
+    149c:	00 00 04 00       	            nop\.i 0x0;;
+    14a0:	01 58 01 00 00 21 	\[MII\]       mov r43=r0
+    14a6:	00 00 00 02 00 00 	            nop\.i 0x0
+    14ac:	00 00 04 00       	            nop\.i 0x0;;
+    14b0:	01 60 01 00 00 21 	\[MII\]       mov r44=r0
+    14b6:	00 00 00 02 00 00 	            nop\.i 0x0
+    14bc:	00 00 04 00       	            nop\.i 0x0;;
+    14c0:	01 68 01 00 00 21 	\[MII\]       mov r45=r0
+    14c6:	00 00 00 02 00 00 	            nop\.i 0x0
+    14cc:	00 00 04 00       	            nop\.i 0x0;;
+    14d0:	01 70 01 00 00 21 	\[MII\]       mov r46=r0
+    14d6:	00 00 00 02 00 00 	            nop\.i 0x0
+    14dc:	00 00 04 00       	            nop\.i 0x0;;
+    14e0:	01 78 01 00 00 21 	\[MII\]       mov r47=r0
+    14e6:	00 00 00 02 00 00 	            nop\.i 0x0
+    14ec:	00 00 04 00       	            nop\.i 0x0;;
+    14f0:	01 80 01 00 00 21 	\[MII\]       mov r48=r0
+    14f6:	00 00 00 02 00 00 	            nop\.i 0x0
+    14fc:	00 00 04 00       	            nop\.i 0x0;;
+    1500:	01 88 01 00 00 21 	\[MII\]       mov r49=r0
+    1506:	00 00 00 02 00 00 	            nop\.i 0x0
+    150c:	00 00 04 00       	            nop\.i 0x0;;
+    1510:	01 90 01 00 00 21 	\[MII\]       mov r50=r0
+    1516:	00 00 00 02 00 00 	            nop\.i 0x0
+    151c:	00 00 04 00       	            nop\.i 0x0;;
+    1520:	01 98 01 00 00 21 	\[MII\]       mov r51=r0
+    1526:	00 00 00 02 00 00 	            nop\.i 0x0
+    152c:	00 00 04 00       	            nop\.i 0x0;;
+    1530:	01 a0 01 00 00 21 	\[MII\]       mov r52=r0
+    1536:	00 00 00 02 00 00 	            nop\.i 0x0
+    153c:	00 00 04 00       	            nop\.i 0x0;;
+    1540:	01 a8 01 00 00 21 	\[MII\]       mov r53=r0
+    1546:	00 00 00 02 00 00 	            nop\.i 0x0
+    154c:	00 00 04 00       	            nop\.i 0x0;;
+    1550:	01 b0 01 00 00 21 	\[MII\]       mov r54=r0
+    1556:	00 00 00 02 00 00 	            nop\.i 0x0
+    155c:	00 00 04 00       	            nop\.i 0x0;;
+    1560:	01 b8 01 00 00 21 	\[MII\]       mov r55=r0
+    1566:	00 00 00 02 00 00 	            nop\.i 0x0
+    156c:	00 00 04 00       	            nop\.i 0x0;;
+    1570:	01 c0 01 00 00 21 	\[MII\]       mov r56=r0
+    1576:	00 00 00 02 00 00 	            nop\.i 0x0
+    157c:	00 00 04 00       	            nop\.i 0x0;;
+    1580:	01 c8 01 00 00 21 	\[MII\]       mov r57=r0
+    1586:	00 00 00 02 00 00 	            nop\.i 0x0
+    158c:	00 00 04 00       	            nop\.i 0x0;;
+    1590:	01 d0 01 00 00 21 	\[MII\]       mov r58=r0
+    1596:	00 00 00 02 00 00 	            nop\.i 0x0
+    159c:	00 00 04 00       	            nop\.i 0x0;;
+    15a0:	01 d8 01 00 00 21 	\[MII\]       mov r59=r0
+    15a6:	00 00 00 02 00 00 	            nop\.i 0x0
+    15ac:	00 00 04 00       	            nop\.i 0x0;;
+    15b0:	01 e0 01 00 00 21 	\[MII\]       mov r60=r0
+    15b6:	00 00 00 02 00 00 	            nop\.i 0x0
+    15bc:	00 00 04 00       	            nop\.i 0x0;;
+    15c0:	01 e8 01 00 00 21 	\[MII\]       mov r61=r0
+    15c6:	00 00 00 02 00 00 	            nop\.i 0x0
+    15cc:	00 00 04 00       	            nop\.i 0x0;;
+    15d0:	01 f0 01 00 00 21 	\[MII\]       mov r62=r0
+    15d6:	00 00 00 02 00 00 	            nop\.i 0x0
+    15dc:	00 00 04 00       	            nop\.i 0x0;;
+    15e0:	01 f8 01 00 00 21 	\[MII\]       mov r63=r0
+    15e6:	00 00 00 02 00 00 	            nop\.i 0x0
+    15ec:	00 00 04 00       	            nop\.i 0x0;;
+    15f0:	01 00 02 00 00 21 	\[MII\]       mov r64=r0
+    15f6:	00 00 00 02 00 00 	            nop\.i 0x0
+    15fc:	00 00 04 00       	            nop\.i 0x0;;
+    1600:	01 08 02 00 00 21 	\[MII\]       mov r65=r0
+    1606:	00 00 00 02 00 00 	            nop\.i 0x0
+    160c:	00 00 04 00       	            nop\.i 0x0;;
+    1610:	01 10 02 00 00 21 	\[MII\]       mov r66=r0
+    1616:	00 00 00 02 00 00 	            nop\.i 0x0
+    161c:	00 00 04 00       	            nop\.i 0x0;;
+    1620:	01 18 02 00 00 21 	\[MII\]       mov r67=r0
+    1626:	00 00 00 02 00 00 	            nop\.i 0x0
+    162c:	00 00 04 00       	            nop\.i 0x0;;
+    1630:	01 20 02 00 00 21 	\[MII\]       mov r68=r0
+    1636:	00 00 00 02 00 00 	            nop\.i 0x0
+    163c:	00 00 04 00       	            nop\.i 0x0;;
+    1640:	01 28 02 00 00 21 	\[MII\]       mov r69=r0
+    1646:	00 00 00 02 00 00 	            nop\.i 0x0
+    164c:	00 00 04 00       	            nop\.i 0x0;;
+    1650:	01 30 02 00 00 21 	\[MII\]       mov r70=r0
+    1656:	00 00 00 02 00 00 	            nop\.i 0x0
+    165c:	00 00 04 00       	            nop\.i 0x0;;
+    1660:	01 38 02 00 00 21 	\[MII\]       mov r71=r0
+    1666:	00 00 00 02 00 00 	            nop\.i 0x0
+    166c:	00 00 04 00       	            nop\.i 0x0;;
+    1670:	01 40 02 00 00 21 	\[MII\]       mov r72=r0
+    1676:	00 00 00 02 00 00 	            nop\.i 0x0
+    167c:	00 00 04 00       	            nop\.i 0x0;;
+    1680:	01 48 02 00 00 21 	\[MII\]       mov r73=r0
+    1686:	00 00 00 02 00 00 	            nop\.i 0x0
+    168c:	00 00 04 00       	            nop\.i 0x0;;
+    1690:	01 50 02 00 00 21 	\[MII\]       mov r74=r0
+    1696:	00 00 00 02 00 00 	            nop\.i 0x0
+    169c:	00 00 04 00       	            nop\.i 0x0;;
+    16a0:	01 58 02 00 00 21 	\[MII\]       mov r75=r0
+    16a6:	00 00 00 02 00 00 	            nop\.i 0x0
+    16ac:	00 00 04 00       	            nop\.i 0x0;;
+    16b0:	01 60 02 00 00 21 	\[MII\]       mov r76=r0
+    16b6:	00 00 00 02 00 00 	            nop\.i 0x0
+    16bc:	00 00 04 00       	            nop\.i 0x0;;
+    16c0:	01 68 02 00 00 21 	\[MII\]       mov r77=r0
+    16c6:	00 00 00 02 00 00 	            nop\.i 0x0
+    16cc:	00 00 04 00       	            nop\.i 0x0;;
+    16d0:	01 70 02 00 00 21 	\[MII\]       mov r78=r0
+    16d6:	00 00 00 02 00 00 	            nop\.i 0x0
+    16dc:	00 00 04 00       	            nop\.i 0x0;;
+    16e0:	01 78 02 00 00 21 	\[MII\]       mov r79=r0
+    16e6:	00 00 00 02 00 00 	            nop\.i 0x0
+    16ec:	00 00 04 00       	            nop\.i 0x0;;
+    16f0:	01 80 02 00 00 21 	\[MII\]       mov r80=r0
+    16f6:	00 00 00 02 00 00 	            nop\.i 0x0
+    16fc:	00 00 04 00       	            nop\.i 0x0;;
+    1700:	01 88 02 00 00 21 	\[MII\]       mov r81=r0
+    1706:	00 00 00 02 00 00 	            nop\.i 0x0
+    170c:	00 00 04 00       	            nop\.i 0x0;;
+    1710:	01 90 02 00 00 21 	\[MII\]       mov r82=r0
+    1716:	00 00 00 02 00 00 	            nop\.i 0x0
+    171c:	00 00 04 00       	            nop\.i 0x0;;
+    1720:	01 98 02 00 00 21 	\[MII\]       mov r83=r0
+    1726:	00 00 00 02 00 00 	            nop\.i 0x0
+    172c:	00 00 04 00       	            nop\.i 0x0;;
+    1730:	01 a0 02 00 00 21 	\[MII\]       mov r84=r0
+    1736:	00 00 00 02 00 00 	            nop\.i 0x0
+    173c:	00 00 04 00       	            nop\.i 0x0;;
+    1740:	01 a8 02 00 00 21 	\[MII\]       mov r85=r0
+    1746:	00 00 00 02 00 00 	            nop\.i 0x0
+    174c:	00 00 04 00       	            nop\.i 0x0;;
+    1750:	01 b0 02 00 00 21 	\[MII\]       mov r86=r0
+    1756:	00 00 00 02 00 00 	            nop\.i 0x0
+    175c:	00 00 04 00       	            nop\.i 0x0;;
+    1760:	01 b8 02 00 00 21 	\[MII\]       mov r87=r0
+    1766:	00 00 00 02 00 00 	            nop\.i 0x0
+    176c:	00 00 04 00       	            nop\.i 0x0;;
+    1770:	01 c0 02 00 00 21 	\[MII\]       mov r88=r0
+    1776:	00 00 00 02 00 00 	            nop\.i 0x0
+    177c:	00 00 04 00       	            nop\.i 0x0;;
+    1780:	01 c8 02 00 00 21 	\[MII\]       mov r89=r0
+    1786:	00 00 00 02 00 00 	            nop\.i 0x0
+    178c:	00 00 04 00       	            nop\.i 0x0;;
+    1790:	01 d0 02 00 00 21 	\[MII\]       mov r90=r0
+    1796:	00 00 00 02 00 00 	            nop\.i 0x0
+    179c:	00 00 04 00       	            nop\.i 0x0;;
+    17a0:	01 d8 02 00 00 21 	\[MII\]       mov r91=r0
+    17a6:	00 00 00 02 00 00 	            nop\.i 0x0
+    17ac:	00 00 04 00       	            nop\.i 0x0;;
+    17b0:	01 e0 02 00 00 21 	\[MII\]       mov r92=r0
+    17b6:	00 00 00 02 00 00 	            nop\.i 0x0
+    17bc:	00 00 04 00       	            nop\.i 0x0;;
+    17c0:	01 e8 02 00 00 21 	\[MII\]       mov r93=r0
+    17c6:	00 00 00 02 00 00 	            nop\.i 0x0
+    17cc:	00 00 04 00       	            nop\.i 0x0;;
+    17d0:	01 f0 02 00 00 21 	\[MII\]       mov r94=r0
+    17d6:	00 00 00 02 00 00 	            nop\.i 0x0
+    17dc:	00 00 04 00       	            nop\.i 0x0;;
+    17e0:	01 f8 02 00 00 21 	\[MII\]       mov r95=r0
+    17e6:	00 00 00 02 00 00 	            nop\.i 0x0
+    17ec:	00 00 04 00       	            nop\.i 0x0;;
+    17f0:	01 00 03 00 00 21 	\[MII\]       mov r96=r0
+    17f6:	00 00 00 02 00 00 	            nop\.i 0x0
+    17fc:	00 00 04 00       	            nop\.i 0x0;;
+    1800:	01 08 03 00 00 21 	\[MII\]       mov r97=r0
+    1806:	00 00 00 02 00 00 	            nop\.i 0x0
+    180c:	00 00 04 00       	            nop\.i 0x0;;
+    1810:	01 10 03 00 00 21 	\[MII\]       mov r98=r0
+    1816:	00 00 00 02 00 00 	            nop\.i 0x0
+    181c:	00 00 04 00       	            nop\.i 0x0;;
+    1820:	01 18 03 00 00 21 	\[MII\]       mov r99=r0
+    1826:	00 00 00 02 00 00 	            nop\.i 0x0
+    182c:	00 00 04 00       	            nop\.i 0x0;;
+    1830:	01 20 03 00 00 21 	\[MII\]       mov r100=r0
+    1836:	00 00 00 02 00 00 	            nop\.i 0x0
+    183c:	00 00 04 00       	            nop\.i 0x0;;
+    1840:	01 28 03 00 00 21 	\[MII\]       mov r101=r0
+    1846:	00 00 00 02 00 00 	            nop\.i 0x0
+    184c:	00 00 04 00       	            nop\.i 0x0;;
+    1850:	01 30 03 00 00 21 	\[MII\]       mov r102=r0
+    1856:	00 00 00 02 00 00 	            nop\.i 0x0
+    185c:	00 00 04 00       	            nop\.i 0x0;;
+    1860:	01 38 03 00 00 21 	\[MII\]       mov r103=r0
+    1866:	00 00 00 02 00 00 	            nop\.i 0x0
+    186c:	00 00 04 00       	            nop\.i 0x0;;
+    1870:	01 40 03 00 00 21 	\[MII\]       mov r104=r0
+    1876:	00 00 00 02 00 00 	            nop\.i 0x0
+    187c:	00 00 04 00       	            nop\.i 0x0;;
+    1880:	01 48 03 00 00 21 	\[MII\]       mov r105=r0
+    1886:	00 00 00 02 00 00 	            nop\.i 0x0
+    188c:	00 00 04 00       	            nop\.i 0x0;;
+    1890:	01 50 03 00 00 21 	\[MII\]       mov r106=r0
+    1896:	00 00 00 02 00 00 	            nop\.i 0x0
+    189c:	00 00 04 00       	            nop\.i 0x0;;
+    18a0:	01 58 03 00 00 21 	\[MII\]       mov r107=r0
+    18a6:	00 00 00 02 00 00 	            nop\.i 0x0
+    18ac:	00 00 04 00       	            nop\.i 0x0;;
+    18b0:	01 60 03 00 00 21 	\[MII\]       mov r108=r0
+    18b6:	00 00 00 02 00 00 	            nop\.i 0x0
+    18bc:	00 00 04 00       	            nop\.i 0x0;;
+    18c0:	01 68 03 00 00 21 	\[MII\]       mov r109=r0
+    18c6:	00 00 00 02 00 00 	            nop\.i 0x0
+    18cc:	00 00 04 00       	            nop\.i 0x0;;
+    18d0:	01 70 03 00 00 21 	\[MII\]       mov r110=r0
+    18d6:	00 00 00 02 00 00 	            nop\.i 0x0
+    18dc:	00 00 04 00       	            nop\.i 0x0;;
+    18e0:	01 78 03 00 00 21 	\[MII\]       mov r111=r0
+    18e6:	00 00 00 02 00 00 	            nop\.i 0x0
+    18ec:	00 00 04 00       	            nop\.i 0x0;;
+    18f0:	01 80 03 00 00 21 	\[MII\]       mov r112=r0
+    18f6:	00 00 00 02 00 00 	            nop\.i 0x0
+    18fc:	00 00 04 00       	            nop\.i 0x0;;
+    1900:	01 88 03 00 00 21 	\[MII\]       mov r113=r0
+    1906:	00 00 00 02 00 00 	            nop\.i 0x0
+    190c:	00 00 04 00       	            nop\.i 0x0;;
+    1910:	01 90 03 00 00 21 	\[MII\]       mov r114=r0
+    1916:	00 00 00 02 00 00 	            nop\.i 0x0
+    191c:	00 00 04 00       	            nop\.i 0x0;;
+    1920:	01 98 03 00 00 21 	\[MII\]       mov r115=r0
+    1926:	00 00 00 02 00 00 	            nop\.i 0x0
+    192c:	00 00 04 00       	            nop\.i 0x0;;
+    1930:	01 a0 03 00 00 21 	\[MII\]       mov r116=r0
+    1936:	00 00 00 02 00 00 	            nop\.i 0x0
+    193c:	00 00 04 00       	            nop\.i 0x0;;
+    1940:	01 a8 03 00 00 21 	\[MII\]       mov r117=r0
+    1946:	00 00 00 02 00 00 	            nop\.i 0x0
+    194c:	00 00 04 00       	            nop\.i 0x0;;
+    1950:	01 b0 03 00 00 21 	\[MII\]       mov r118=r0
+    1956:	00 00 00 02 00 00 	            nop\.i 0x0
+    195c:	00 00 04 00       	            nop\.i 0x0;;
+    1960:	01 b8 03 00 00 21 	\[MII\]       mov r119=r0
+    1966:	00 00 00 02 00 00 	            nop\.i 0x0
+    196c:	00 00 04 00       	            nop\.i 0x0;;
+    1970:	01 c0 03 00 00 21 	\[MII\]       mov r120=r0
+    1976:	00 00 00 02 00 00 	            nop\.i 0x0
+    197c:	00 00 04 00       	            nop\.i 0x0;;
+    1980:	01 c8 03 00 00 21 	\[MII\]       mov r121=r0
+    1986:	00 00 00 02 00 00 	            nop\.i 0x0
+    198c:	00 00 04 00       	            nop\.i 0x0;;
+    1990:	01 d0 03 00 00 21 	\[MII\]       mov r122=r0
+    1996:	00 00 00 02 00 00 	            nop\.i 0x0
+    199c:	00 00 04 00       	            nop\.i 0x0;;
+    19a0:	01 d8 03 00 00 21 	\[MII\]       mov r123=r0
+    19a6:	00 00 00 02 00 00 	            nop\.i 0x0
+    19ac:	00 00 04 00       	            nop\.i 0x0;;
+    19b0:	01 e0 03 00 00 21 	\[MII\]       mov r124=r0
+    19b6:	00 00 00 02 00 00 	            nop\.i 0x0
+    19bc:	00 00 04 00       	            nop\.i 0x0;;
+    19c0:	01 e8 03 00 00 21 	\[MII\]       mov r125=r0
+    19c6:	00 00 00 02 00 00 	            nop\.i 0x0
+    19cc:	00 00 04 00       	            nop\.i 0x0;;
+    19d0:	01 f0 03 00 00 21 	\[MII\]       mov r126=r0
+    19d6:	00 00 00 02 00 00 	            nop\.i 0x0
+    19dc:	00 00 04 00       	            nop\.i 0x0;;
+    19e0:	01 f8 03 00 00 21 	\[MII\]       mov r127=r0
+    19e6:	00 00 00 02 00 00 	            nop\.i 0x0
+    19ec:	00 00 04 00       	            nop\.i 0x0;;
+    19f0:	01 40 00 00 00 21 	\[MII\]       mov r8=r0
+    19f6:	00 00 00 02 00 00 	            nop\.i 0x0
+    19fc:	00 00 04 00       	            nop\.i 0x0;;
+    1a00:	01 48 00 00 00 21 	\[MII\]       mov r9=r0
+    1a06:	00 00 00 02 00 00 	            nop\.i 0x0
+    1a0c:	00 00 04 00       	            nop\.i 0x0;;
+    1a10:	01 50 00 00 00 21 	\[MII\]       mov r10=r0
+    1a16:	00 00 00 02 00 00 	            nop\.i 0x0
+    1a1c:	00 00 04 00       	            nop\.i 0x0;;
+    1a20:	01 58 00 00 00 21 	\[MII\]       mov r11=r0
+    1a26:	00 00 00 02 00 00 	            nop\.i 0x0
+    1a2c:	00 00 04 00       	            nop\.i 0x0;;
+    1a30:	01 08 00 00 00 21 	\[MII\]       mov r1=r0
+    1a36:	c0 00 00 00 42 00 	            mov r12=r0
+    1a3c:	00 00 04 00       	            nop\.i 0x0;;
+    1a40:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1a46:	20 00 00 20 00 00 	            mov f2=f0
+    1a4c:	00 00 04 00       	            nop\.i 0x0;;
+    1a50:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1a56:	30 00 00 20 00 00 	            mov f3=f0
+    1a5c:	00 00 04 00       	            nop\.i 0x0;;
+    1a60:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1a66:	40 00 00 20 00 00 	            mov f4=f0
+    1a6c:	00 00 04 00       	            nop\.i 0x0;;
+    1a70:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1a76:	50 00 00 20 00 00 	            mov f5=f0
+    1a7c:	00 00 04 00       	            nop\.i 0x0;;
+    1a80:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1a86:	60 00 00 20 00 00 	            mov f6=f0
+    1a8c:	00 00 04 00       	            nop\.i 0x0;;
+    1a90:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1a96:	70 00 00 20 00 00 	            mov f7=f0
+    1a9c:	00 00 04 00       	            nop\.i 0x0;;
+    1aa0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1aa6:	80 00 00 20 00 00 	            mov f8=f0
+    1aac:	00 00 04 00       	            nop\.i 0x0;;
+    1ab0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1ab6:	90 00 00 20 00 00 	            mov f9=f0
+    1abc:	00 00 04 00       	            nop\.i 0x0;;
+    1ac0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1ac6:	a0 00 00 20 00 00 	            mov f10=f0
+    1acc:	00 00 04 00       	            nop\.i 0x0;;
+    1ad0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1ad6:	b0 00 00 20 00 00 	            mov f11=f0
+    1adc:	00 00 04 00       	            nop\.i 0x0;;
+    1ae0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1ae6:	c0 00 00 20 00 00 	            mov f12=f0
+    1aec:	00 00 04 00       	            nop\.i 0x0;;
+    1af0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1af6:	d0 00 00 20 00 00 	            mov f13=f0
+    1afc:	00 00 04 00       	            nop\.i 0x0;;
+    1b00:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1b06:	e0 00 00 20 00 00 	            mov f14=f0
+    1b0c:	00 00 04 00       	            nop\.i 0x0;;
+    1b10:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1b16:	f0 00 00 20 00 00 	            mov f15=f0
+    1b1c:	00 00 04 00       	            nop\.i 0x0;;
+    1b20:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1b26:	00 01 00 20 00 00 	            mov f16=f0
+    1b2c:	00 00 04 00       	            nop\.i 0x0;;
+    1b30:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1b36:	10 01 00 20 00 00 	            mov f17=f0
+    1b3c:	00 00 04 00       	            nop\.i 0x0;;
+    1b40:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1b46:	20 01 00 20 00 00 	            mov f18=f0
+    1b4c:	00 00 04 00       	            nop\.i 0x0;;
+    1b50:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1b56:	30 01 00 20 00 00 	            mov f19=f0
+    1b5c:	00 00 04 00       	            nop\.i 0x0;;
+    1b60:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1b66:	40 01 00 20 00 00 	            mov f20=f0
+    1b6c:	00 00 04 00       	            nop\.i 0x0;;
+    1b70:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1b76:	50 01 00 20 00 00 	            mov f21=f0
+    1b7c:	00 00 04 00       	            nop\.i 0x0;;
+    1b80:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1b86:	60 01 00 20 00 00 	            mov f22=f0
+    1b8c:	00 00 04 00       	            nop\.i 0x0;;
+    1b90:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1b96:	70 01 00 20 00 00 	            mov f23=f0
+    1b9c:	00 00 04 00       	            nop\.i 0x0;;
+    1ba0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1ba6:	80 01 00 20 00 00 	            mov f24=f0
+    1bac:	00 00 04 00       	            nop\.i 0x0;;
+    1bb0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1bb6:	90 01 00 20 00 00 	            mov f25=f0
+    1bbc:	00 00 04 00       	            nop\.i 0x0;;
+    1bc0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1bc6:	a0 01 00 20 00 00 	            mov f26=f0
+    1bcc:	00 00 04 00       	            nop\.i 0x0;;
+    1bd0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1bd6:	b0 01 00 20 00 00 	            mov f27=f0
+    1bdc:	00 00 04 00       	            nop\.i 0x0;;
+    1be0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1be6:	c0 01 00 20 00 00 	            mov f28=f0
+    1bec:	00 00 04 00       	            nop\.i 0x0;;
+    1bf0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1bf6:	d0 01 00 20 00 00 	            mov f29=f0
+    1bfc:	00 00 04 00       	            nop\.i 0x0;;
+    1c00:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1c06:	e0 01 00 20 00 00 	            mov f30=f0
+    1c0c:	00 00 04 00       	            nop\.i 0x0;;
+    1c10:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1c16:	f0 01 00 20 00 00 	            mov f31=f0
+    1c1c:	00 00 04 00       	            nop\.i 0x0;;
+    1c20:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1c26:	00 02 00 20 00 00 	            mov f32=f0
+    1c2c:	00 00 04 00       	            nop\.i 0x0;;
+    1c30:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1c36:	10 02 00 20 00 00 	            mov f33=f0
+    1c3c:	00 00 04 00       	            nop\.i 0x0;;
+    1c40:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1c46:	20 02 00 20 00 00 	            mov f34=f0
+    1c4c:	00 00 04 00       	            nop\.i 0x0;;
+    1c50:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1c56:	30 02 00 20 00 00 	            mov f35=f0
+    1c5c:	00 00 04 00       	            nop\.i 0x0;;
+    1c60:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1c66:	40 02 00 20 00 00 	            mov f36=f0
+    1c6c:	00 00 04 00       	            nop\.i 0x0;;
+    1c70:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1c76:	50 02 00 20 00 00 	            mov f37=f0
+    1c7c:	00 00 04 00       	            nop\.i 0x0;;
+    1c80:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1c86:	60 02 00 20 00 00 	            mov f38=f0
+    1c8c:	00 00 04 00       	            nop\.i 0x0;;
+    1c90:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1c96:	70 02 00 20 00 00 	            mov f39=f0
+    1c9c:	00 00 04 00       	            nop\.i 0x0;;
+    1ca0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1ca6:	80 02 00 20 00 00 	            mov f40=f0
+    1cac:	00 00 04 00       	            nop\.i 0x0;;
+    1cb0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1cb6:	90 02 00 20 00 00 	            mov f41=f0
+    1cbc:	00 00 04 00       	            nop\.i 0x0;;
+    1cc0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1cc6:	a0 02 00 20 00 00 	            mov f42=f0
+    1ccc:	00 00 04 00       	            nop\.i 0x0;;
+    1cd0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1cd6:	b0 02 00 20 00 00 	            mov f43=f0
+    1cdc:	00 00 04 00       	            nop\.i 0x0;;
+    1ce0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1ce6:	c0 02 00 20 00 00 	            mov f44=f0
+    1cec:	00 00 04 00       	            nop\.i 0x0;;
+    1cf0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1cf6:	d0 02 00 20 00 00 	            mov f45=f0
+    1cfc:	00 00 04 00       	            nop\.i 0x0;;
+    1d00:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1d06:	e0 02 00 20 00 00 	            mov f46=f0
+    1d0c:	00 00 04 00       	            nop\.i 0x0;;
+    1d10:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1d16:	f0 02 00 20 00 00 	            mov f47=f0
+    1d1c:	00 00 04 00       	            nop\.i 0x0;;
+    1d20:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1d26:	00 03 00 20 00 00 	            mov f48=f0
+    1d2c:	00 00 04 00       	            nop\.i 0x0;;
+    1d30:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1d36:	10 03 00 20 00 00 	            mov f49=f0
+    1d3c:	00 00 04 00       	            nop\.i 0x0;;
+    1d40:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1d46:	20 03 00 20 00 00 	            mov f50=f0
+    1d4c:	00 00 04 00       	            nop\.i 0x0;;
+    1d50:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1d56:	30 03 00 20 00 00 	            mov f51=f0
+    1d5c:	00 00 04 00       	            nop\.i 0x0;;
+    1d60:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1d66:	40 03 00 20 00 00 	            mov f52=f0
+    1d6c:	00 00 04 00       	            nop\.i 0x0;;
+    1d70:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1d76:	50 03 00 20 00 00 	            mov f53=f0
+    1d7c:	00 00 04 00       	            nop\.i 0x0;;
+    1d80:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1d86:	60 03 00 20 00 00 	            mov f54=f0
+    1d8c:	00 00 04 00       	            nop\.i 0x0;;
+    1d90:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1d96:	70 03 00 20 00 00 	            mov f55=f0
+    1d9c:	00 00 04 00       	            nop\.i 0x0;;
+    1da0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1da6:	80 03 00 20 00 00 	            mov f56=f0
+    1dac:	00 00 04 00       	            nop\.i 0x0;;
+    1db0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1db6:	90 03 00 20 00 00 	            mov f57=f0
+    1dbc:	00 00 04 00       	            nop\.i 0x0;;
+    1dc0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1dc6:	a0 03 00 20 00 00 	            mov f58=f0
+    1dcc:	00 00 04 00       	            nop\.i 0x0;;
+    1dd0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1dd6:	b0 03 00 20 00 00 	            mov f59=f0
+    1ddc:	00 00 04 00       	            nop\.i 0x0;;
+    1de0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1de6:	c0 03 00 20 00 00 	            mov f60=f0
+    1dec:	00 00 04 00       	            nop\.i 0x0;;
+    1df0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1df6:	d0 03 00 20 00 00 	            mov f61=f0
+    1dfc:	00 00 04 00       	            nop\.i 0x0;;
+    1e00:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1e06:	e0 03 00 20 00 00 	            mov f62=f0
+    1e0c:	00 00 04 00       	            nop\.i 0x0;;
+    1e10:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1e16:	f0 03 00 20 00 00 	            mov f63=f0
+    1e1c:	00 00 04 00       	            nop\.i 0x0;;
+    1e20:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1e26:	00 04 00 20 00 00 	            mov f64=f0
+    1e2c:	00 00 04 00       	            nop\.i 0x0;;
+    1e30:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1e36:	10 04 00 20 00 00 	            mov f65=f0
+    1e3c:	00 00 04 00       	            nop\.i 0x0;;
+    1e40:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1e46:	20 04 00 20 00 00 	            mov f66=f0
+    1e4c:	00 00 04 00       	            nop\.i 0x0;;
+    1e50:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1e56:	30 04 00 20 00 00 	            mov f67=f0
+    1e5c:	00 00 04 00       	            nop\.i 0x0;;
+    1e60:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1e66:	40 04 00 20 00 00 	            mov f68=f0
+    1e6c:	00 00 04 00       	            nop\.i 0x0;;
+    1e70:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1e76:	50 04 00 20 00 00 	            mov f69=f0
+    1e7c:	00 00 04 00       	            nop\.i 0x0;;
+    1e80:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1e86:	60 04 00 20 00 00 	            mov f70=f0
+    1e8c:	00 00 04 00       	            nop\.i 0x0;;
+    1e90:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1e96:	70 04 00 20 00 00 	            mov f71=f0
+    1e9c:	00 00 04 00       	            nop\.i 0x0;;
+    1ea0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1ea6:	80 04 00 20 00 00 	            mov f72=f0
+    1eac:	00 00 04 00       	            nop\.i 0x0;;
+    1eb0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1eb6:	90 04 00 20 00 00 	            mov f73=f0
+    1ebc:	00 00 04 00       	            nop\.i 0x0;;
+    1ec0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1ec6:	a0 04 00 20 00 00 	            mov f74=f0
+    1ecc:	00 00 04 00       	            nop\.i 0x0;;
+    1ed0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1ed6:	b0 04 00 20 00 00 	            mov f75=f0
+    1edc:	00 00 04 00       	            nop\.i 0x0;;
+    1ee0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1ee6:	c0 04 00 20 00 00 	            mov f76=f0
+    1eec:	00 00 04 00       	            nop\.i 0x0;;
+    1ef0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1ef6:	d0 04 00 20 00 00 	            mov f77=f0
+    1efc:	00 00 04 00       	            nop\.i 0x0;;
+    1f00:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1f06:	e0 04 00 20 00 00 	            mov f78=f0
+    1f0c:	00 00 04 00       	            nop\.i 0x0;;
+    1f10:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1f16:	f0 04 00 20 00 00 	            mov f79=f0
+    1f1c:	00 00 04 00       	            nop\.i 0x0;;
+    1f20:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1f26:	00 05 00 20 00 00 	            mov f80=f0
+    1f2c:	00 00 04 00       	            nop\.i 0x0;;
+    1f30:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1f36:	10 05 00 20 00 00 	            mov f81=f0
+    1f3c:	00 00 04 00       	            nop\.i 0x0;;
+    1f40:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1f46:	20 05 00 20 00 00 	            mov f82=f0
+    1f4c:	00 00 04 00       	            nop\.i 0x0;;
+    1f50:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1f56:	30 05 00 20 00 00 	            mov f83=f0
+    1f5c:	00 00 04 00       	            nop\.i 0x0;;
+    1f60:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1f66:	40 05 00 20 00 00 	            mov f84=f0
+    1f6c:	00 00 04 00       	            nop\.i 0x0;;
+    1f70:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1f76:	50 05 00 20 00 00 	            mov f85=f0
+    1f7c:	00 00 04 00       	            nop\.i 0x0;;
+    1f80:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1f86:	60 05 00 20 00 00 	            mov f86=f0
+    1f8c:	00 00 04 00       	            nop\.i 0x0;;
+    1f90:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1f96:	70 05 00 20 00 00 	            mov f87=f0
+    1f9c:	00 00 04 00       	            nop\.i 0x0;;
+    1fa0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1fa6:	80 05 00 20 00 00 	            mov f88=f0
+    1fac:	00 00 04 00       	            nop\.i 0x0;;
+    1fb0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1fb6:	90 05 00 20 00 00 	            mov f89=f0
+    1fbc:	00 00 04 00       	            nop\.i 0x0;;
+    1fc0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1fc6:	a0 05 00 20 00 00 	            mov f90=f0
+    1fcc:	00 00 04 00       	            nop\.i 0x0;;
+    1fd0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1fd6:	b0 05 00 20 00 00 	            mov f91=f0
+    1fdc:	00 00 04 00       	            nop\.i 0x0;;
+    1fe0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1fe6:	c0 05 00 20 00 00 	            mov f92=f0
+    1fec:	00 00 04 00       	            nop\.i 0x0;;
+    1ff0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    1ff6:	d0 05 00 20 00 00 	            mov f93=f0
+    1ffc:	00 00 04 00       	            nop\.i 0x0;;
+    2000:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2006:	e0 05 00 20 00 00 	            mov f94=f0
+    200c:	00 00 04 00       	            nop\.i 0x0;;
+    2010:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2016:	f0 05 00 20 00 00 	            mov f95=f0
+    201c:	00 00 04 00       	            nop\.i 0x0;;
+    2020:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2026:	00 06 00 20 00 00 	            mov f96=f0
+    202c:	00 00 04 00       	            nop\.i 0x0;;
+    2030:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2036:	10 06 00 20 00 00 	            mov f97=f0
+    203c:	00 00 04 00       	            nop\.i 0x0;;
+    2040:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2046:	20 06 00 20 00 00 	            mov f98=f0
+    204c:	00 00 04 00       	            nop\.i 0x0;;
+    2050:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2056:	30 06 00 20 00 00 	            mov f99=f0
+    205c:	00 00 04 00       	            nop\.i 0x0;;
+    2060:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2066:	40 06 00 20 00 00 	            mov f100=f0
+    206c:	00 00 04 00       	            nop\.i 0x0;;
+    2070:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2076:	50 06 00 20 00 00 	            mov f101=f0
+    207c:	00 00 04 00       	            nop\.i 0x0;;
+    2080:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2086:	60 06 00 20 00 00 	            mov f102=f0
+    208c:	00 00 04 00       	            nop\.i 0x0;;
+    2090:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2096:	70 06 00 20 00 00 	            mov f103=f0
+    209c:	00 00 04 00       	            nop\.i 0x0;;
+    20a0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    20a6:	80 06 00 20 00 00 	            mov f104=f0
+    20ac:	00 00 04 00       	            nop\.i 0x0;;
+    20b0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    20b6:	90 06 00 20 00 00 	            mov f105=f0
+    20bc:	00 00 04 00       	            nop\.i 0x0;;
+    20c0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    20c6:	a0 06 00 20 00 00 	            mov f106=f0
+    20cc:	00 00 04 00       	            nop\.i 0x0;;
+    20d0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    20d6:	b0 06 00 20 00 00 	            mov f107=f0
+    20dc:	00 00 04 00       	            nop\.i 0x0;;
+    20e0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    20e6:	c0 06 00 20 00 00 	            mov f108=f0
+    20ec:	00 00 04 00       	            nop\.i 0x0;;
+    20f0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    20f6:	d0 06 00 20 00 00 	            mov f109=f0
+    20fc:	00 00 04 00       	            nop\.i 0x0;;
+    2100:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2106:	e0 06 00 20 00 00 	            mov f110=f0
+    210c:	00 00 04 00       	            nop\.i 0x0;;
+    2110:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2116:	f0 06 00 20 00 00 	            mov f111=f0
+    211c:	00 00 04 00       	            nop\.i 0x0;;
+    2120:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2126:	00 07 00 20 00 00 	            mov f112=f0
+    212c:	00 00 04 00       	            nop\.i 0x0;;
+    2130:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2136:	10 07 00 20 00 00 	            mov f113=f0
+    213c:	00 00 04 00       	            nop\.i 0x0;;
+    2140:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2146:	20 07 00 20 00 00 	            mov f114=f0
+    214c:	00 00 04 00       	            nop\.i 0x0;;
+    2150:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2156:	30 07 00 20 00 00 	            mov f115=f0
+    215c:	00 00 04 00       	            nop\.i 0x0;;
+    2160:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2166:	40 07 00 20 00 00 	            mov f116=f0
+    216c:	00 00 04 00       	            nop\.i 0x0;;
+    2170:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2176:	50 07 00 20 00 00 	            mov f117=f0
+    217c:	00 00 04 00       	            nop\.i 0x0;;
+    2180:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2186:	60 07 00 20 00 00 	            mov f118=f0
+    218c:	00 00 04 00       	            nop\.i 0x0;;
+    2190:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2196:	70 07 00 20 00 00 	            mov f119=f0
+    219c:	00 00 04 00       	            nop\.i 0x0;;
+    21a0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    21a6:	80 07 00 20 00 00 	            mov f120=f0
+    21ac:	00 00 04 00       	            nop\.i 0x0;;
+    21b0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    21b6:	90 07 00 20 00 00 	            mov f121=f0
+    21bc:	00 00 04 00       	            nop\.i 0x0;;
+    21c0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    21c6:	a0 07 00 20 00 00 	            mov f122=f0
+    21cc:	00 00 04 00       	            nop\.i 0x0;;
+    21d0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    21d6:	b0 07 00 20 00 00 	            mov f123=f0
+    21dc:	00 00 04 00       	            nop\.i 0x0;;
+    21e0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    21e6:	c0 07 00 20 00 00 	            mov f124=f0
+    21ec:	00 00 04 00       	            nop\.i 0x0;;
+    21f0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    21f6:	d0 07 00 20 00 00 	            mov f125=f0
+    21fc:	00 00 04 00       	            nop\.i 0x0;;
+    2200:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2206:	e0 07 00 20 00 00 	            mov f126=f0
+    220c:	00 00 04 00       	            nop\.i 0x0;;
+    2210:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2216:	f0 07 00 20 00 00 	            mov f127=f0
+    221c:	00 00 04 00       	            nop\.i 0x0;;
+    2220:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2226:	80 08 04 20 00 00 	            mov f8=f1
+    222c:	00 00 04 00       	            nop\.i 0x0;;
+    2230:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2236:	90 08 04 20 00 00 	            mov f9=f1
+    223c:	00 00 04 00       	            nop\.i 0x0;;
+    2240:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2246:	a0 08 04 20 00 00 	            mov f10=f1
+    224c:	00 00 04 00       	            nop\.i 0x0;;
+    2250:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2256:	b0 08 04 20 00 00 	            mov f11=f1
+    225c:	00 00 04 00       	            nop\.i 0x0;;
+    2260:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2266:	c0 08 04 20 00 00 	            mov f12=f1
+    226c:	00 00 04 00       	            nop\.i 0x0;;
+    2270:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2276:	d0 08 04 20 00 00 	            mov f13=f1
+    227c:	00 00 04 00       	            nop\.i 0x0;;
+    2280:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2286:	e0 08 04 20 00 00 	            mov f14=f1
+    228c:	00 00 04 00       	            nop\.i 0x0;;
+    2290:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2296:	f0 08 04 20 00 00 	            mov f15=f1
+    229c:	00 00 04 00       	            nop\.i 0x0;;
+    22a0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    22a6:	80 08 04 20 00 00 	            mov f8=f1
+    22ac:	00 00 04 00       	            nop\.i 0x0;;
+    22b0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    22b6:	90 08 04 20 00 00 	            mov f9=f1
+    22bc:	00 00 04 00       	            nop\.i 0x0;;
+    22c0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    22c6:	a0 08 04 20 00 00 	            mov f10=f1
+    22cc:	00 00 04 00       	            nop\.i 0x0;;
+    22d0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    22d6:	b0 08 04 20 00 00 	            mov f11=f1
+    22dc:	00 00 04 00       	            nop\.i 0x0;;
+    22e0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    22e6:	c0 08 04 20 00 00 	            mov f12=f1
+    22ec:	00 00 04 00       	            nop\.i 0x0;;
+    22f0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    22f6:	d0 08 04 20 00 00 	            mov f13=f1
+    22fc:	00 00 04 00       	            nop\.i 0x0;;
+    2300:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2306:	e0 08 04 20 00 00 	            mov f14=f1
+    230c:	00 00 04 00       	            nop\.i 0x0;;
+    2310:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+    2316:	f0 08 04 20 00 00 	            mov f15=f1
+    231c:	00 00 04 00       	            nop\.i 0x0;;
+    2320:	01 08 00 00 00 21 	\[MII\]       mov r1=r0
+    2326:	00 00 00 02 00 00 	            nop\.i 0x0
+    232c:	00 00 04 00       	            nop\.i 0x0;;
+    2330:	21 10 00 00 00 21 	\[MII\] \(p01\) mov r2=r0
+    2336:	00 00 00 02 00 00 	            nop\.i 0x0
+    233c:	00 00 04 00       	            nop\.i 0x0;;
+    2340:	41 18 00 00 00 21 	\[MII\] \(p02\) mov r3=r0
+    2346:	00 00 00 02 00 00 	            nop\.i 0x0
+    234c:	00 00 04 00       	            nop\.i 0x0;;
+    2350:	61 20 00 00 00 21 	\[MII\] \(p03\) mov r4=r0
+    2356:	00 00 00 02 00 00 	            nop\.i 0x0
+    235c:	00 00 04 00       	            nop\.i 0x0;;
+    2360:	81 28 00 00 00 21 	\[MII\] \(p04\) mov r5=r0
+    2366:	00 00 00 02 00 00 	            nop\.i 0x0
+    236c:	00 00 04 00       	            nop\.i 0x0;;
+    2370:	a1 30 00 00 00 21 	\[MII\] \(p05\) mov r6=r0
+    2376:	00 00 00 02 00 00 	            nop\.i 0x0
+    237c:	00 00 04 00       	            nop\.i 0x0;;
+    2380:	c1 38 00 00 00 21 	\[MII\] \(p06\) mov r7=r0
+    2386:	00 00 00 02 00 00 	            nop\.i 0x0
+    238c:	00 00 04 00       	            nop\.i 0x0;;
+    2390:	e1 40 00 00 00 21 	\[MII\] \(p07\) mov r8=r0
+    2396:	00 00 00 02 00 00 	            nop\.i 0x0
+    239c:	00 00 04 00       	            nop\.i 0x0;;
+    23a0:	01 49 00 00 00 21 	\[MII\] \(p08\) mov r9=r0
+    23a6:	00 00 00 02 00 00 	            nop\.i 0x0
+    23ac:	00 00 04 00       	            nop\.i 0x0;;
+    23b0:	21 51 00 00 00 21 	\[MII\] \(p09\) mov r10=r0
+    23b6:	00 00 00 02 00 00 	            nop\.i 0x0
+    23bc:	00 00 04 00       	            nop\.i 0x0;;
+    23c0:	41 59 00 00 00 21 	\[MII\] \(p10\) mov r11=r0
+    23c6:	00 00 00 02 00 00 	            nop\.i 0x0
+    23cc:	00 00 04 00       	            nop\.i 0x0;;
+    23d0:	61 61 00 00 00 21 	\[MII\] \(p11\) mov r12=r0
+    23d6:	00 00 00 02 00 00 	            nop\.i 0x0
+    23dc:	00 00 04 00       	            nop\.i 0x0;;
+    23e0:	81 69 00 00 00 21 	\[MII\] \(p12\) mov r13=r0
+    23e6:	00 00 00 02 00 00 	            nop\.i 0x0
+    23ec:	00 00 04 00       	            nop\.i 0x0;;
+    23f0:	a1 71 00 00 00 21 	\[MII\] \(p13\) mov r14=r0
+    23f6:	00 00 00 02 00 00 	            nop\.i 0x0
+    23fc:	00 00 04 00       	            nop\.i 0x0;;
+    2400:	c1 79 00 00 00 21 	\[MII\] \(p14\) mov r15=r0
+    2406:	00 00 00 02 00 00 	            nop\.i 0x0
+    240c:	00 00 04 00       	            nop\.i 0x0;;
+    2410:	e1 81 00 00 00 21 	\[MII\] \(p15\) mov r16=r0
+    2416:	00 00 00 02 00 00 	            nop\.i 0x0
+    241c:	00 00 04 00       	            nop\.i 0x0;;
+    2420:	01 8a 00 00 00 21 	\[MII\] \(p16\) mov r17=r0
+    2426:	00 00 00 02 00 00 	            nop\.i 0x0
+    242c:	00 00 04 00       	            nop\.i 0x0;;
+    2430:	21 92 00 00 00 21 	\[MII\] \(p17\) mov r18=r0
+    2436:	00 00 00 02 00 00 	            nop\.i 0x0
+    243c:	00 00 04 00       	            nop\.i 0x0;;
+    2440:	41 9a 00 00 00 21 	\[MII\] \(p18\) mov r19=r0
+    2446:	00 00 00 02 00 00 	            nop\.i 0x0
+    244c:	00 00 04 00       	            nop\.i 0x0;;
+    2450:	61 a2 00 00 00 21 	\[MII\] \(p19\) mov r20=r0
+    2456:	00 00 00 02 00 00 	            nop\.i 0x0
+    245c:	00 00 04 00       	            nop\.i 0x0;;
+    2460:	81 aa 00 00 00 21 	\[MII\] \(p20\) mov r21=r0
+    2466:	00 00 00 02 00 00 	            nop\.i 0x0
+    246c:	00 00 04 00       	            nop\.i 0x0;;
+    2470:	a1 b2 00 00 00 21 	\[MII\] \(p21\) mov r22=r0
+    2476:	00 00 00 02 00 00 	            nop\.i 0x0
+    247c:	00 00 04 00       	            nop\.i 0x0;;
+    2480:	c1 ba 00 00 00 21 	\[MII\] \(p22\) mov r23=r0
+    2486:	00 00 00 02 00 00 	            nop\.i 0x0
+    248c:	00 00 04 00       	            nop\.i 0x0;;
+    2490:	e1 c2 00 00 00 21 	\[MII\] \(p23\) mov r24=r0
+    2496:	00 00 00 02 00 00 	            nop\.i 0x0
+    249c:	00 00 04 00       	            nop\.i 0x0;;
+    24a0:	01 cb 00 00 00 21 	\[MII\] \(p24\) mov r25=r0
+    24a6:	00 00 00 02 00 00 	            nop\.i 0x0
+    24ac:	00 00 04 00       	            nop\.i 0x0;;
+    24b0:	21 d3 00 00 00 21 	\[MII\] \(p25\) mov r26=r0
+    24b6:	00 00 00 02 00 00 	            nop\.i 0x0
+    24bc:	00 00 04 00       	            nop\.i 0x0;;
+    24c0:	41 db 00 00 00 21 	\[MII\] \(p26\) mov r27=r0
+    24c6:	00 00 00 02 00 00 	            nop\.i 0x0
+    24cc:	00 00 04 00       	            nop\.i 0x0;;
+    24d0:	61 e3 00 00 00 21 	\[MII\] \(p27\) mov r28=r0
+    24d6:	00 00 00 02 00 00 	            nop\.i 0x0
+    24dc:	00 00 04 00       	            nop\.i 0x0;;
+    24e0:	81 eb 00 00 00 21 	\[MII\] \(p28\) mov r29=r0
+    24e6:	00 00 00 02 00 00 	            nop\.i 0x0
+    24ec:	00 00 04 00       	            nop\.i 0x0;;
+    24f0:	a1 f3 00 00 00 21 	\[MII\] \(p29\) mov r30=r0
+    24f6:	00 00 00 02 00 00 	            nop\.i 0x0
+    24fc:	00 00 04 00       	            nop\.i 0x0;;
+    2500:	c1 fb 00 00 00 21 	\[MII\] \(p30\) mov r31=r0
+    2506:	00 00 00 02 00 00 	            nop\.i 0x0
+    250c:	00 00 04 00       	            nop\.i 0x0;;
+    2510:	e1 03 01 00 00 21 	\[MII\] \(p31\) mov r32=r0
+    2516:	00 00 00 02 00 00 	            nop\.i 0x0
+    251c:	00 00 04 00       	            nop\.i 0x0;;
+    2520:	01 0c 01 00 00 21 	\[MII\] \(p32\) mov r33=r0
+    2526:	00 00 00 02 00 00 	            nop\.i 0x0
+    252c:	00 00 04 00       	            nop\.i 0x0;;
+    2530:	21 14 01 00 00 21 	\[MII\] \(p33\) mov r34=r0
+    2536:	00 00 00 02 00 00 	            nop\.i 0x0
+    253c:	00 00 04 00       	            nop\.i 0x0;;
+    2540:	41 1c 01 00 00 21 	\[MII\] \(p34\) mov r35=r0
+    2546:	00 00 00 02 00 00 	            nop\.i 0x0
+    254c:	00 00 04 00       	            nop\.i 0x0;;
+    2550:	61 24 01 00 00 21 	\[MII\] \(p35\) mov r36=r0
+    2556:	00 00 00 02 00 00 	            nop\.i 0x0
+    255c:	00 00 04 00       	            nop\.i 0x0;;
+    2560:	81 2c 01 00 00 21 	\[MII\] \(p36\) mov r37=r0
+    2566:	00 00 00 02 00 00 	            nop\.i 0x0
+    256c:	00 00 04 00       	            nop\.i 0x0;;
+    2570:	a1 34 01 00 00 21 	\[MII\] \(p37\) mov r38=r0
+    2576:	00 00 00 02 00 00 	            nop\.i 0x0
+    257c:	00 00 04 00       	            nop\.i 0x0;;
+    2580:	c1 3c 01 00 00 21 	\[MII\] \(p38\) mov r39=r0
+    2586:	00 00 00 02 00 00 	            nop\.i 0x0
+    258c:	00 00 04 00       	            nop\.i 0x0;;
+    2590:	e1 44 01 00 00 21 	\[MII\] \(p39\) mov r40=r0
+    2596:	00 00 00 02 00 00 	            nop\.i 0x0
+    259c:	00 00 04 00       	            nop\.i 0x0;;
+    25a0:	01 4d 01 00 00 21 	\[MII\] \(p40\) mov r41=r0
+    25a6:	00 00 00 02 00 00 	            nop\.i 0x0
+    25ac:	00 00 04 00       	            nop\.i 0x0;;
+    25b0:	21 55 01 00 00 21 	\[MII\] \(p41\) mov r42=r0
+    25b6:	00 00 00 02 00 00 	            nop\.i 0x0
+    25bc:	00 00 04 00       	            nop\.i 0x0;;
+    25c0:	41 5d 01 00 00 21 	\[MII\] \(p42\) mov r43=r0
+    25c6:	00 00 00 02 00 00 	            nop\.i 0x0
+    25cc:	00 00 04 00       	            nop\.i 0x0;;
+    25d0:	61 65 01 00 00 21 	\[MII\] \(p43\) mov r44=r0
+    25d6:	00 00 00 02 00 00 	            nop\.i 0x0
+    25dc:	00 00 04 00       	            nop\.i 0x0;;
+    25e0:	81 6d 01 00 00 21 	\[MII\] \(p44\) mov r45=r0
+    25e6:	00 00 00 02 00 00 	            nop\.i 0x0
+    25ec:	00 00 04 00       	            nop\.i 0x0;;
+    25f0:	a1 75 01 00 00 21 	\[MII\] \(p45\) mov r46=r0
+    25f6:	00 00 00 02 00 00 	            nop\.i 0x0
+    25fc:	00 00 04 00       	            nop\.i 0x0;;
+    2600:	c1 7d 01 00 00 21 	\[MII\] \(p46\) mov r47=r0
+    2606:	00 00 00 02 00 00 	            nop\.i 0x0
+    260c:	00 00 04 00       	            nop\.i 0x0;;
+    2610:	e1 85 01 00 00 21 	\[MII\] \(p47\) mov r48=r0
+    2616:	00 00 00 02 00 00 	            nop\.i 0x0
+    261c:	00 00 04 00       	            nop\.i 0x0;;
+    2620:	01 8e 01 00 00 21 	\[MII\] \(p48\) mov r49=r0
+    2626:	00 00 00 02 00 00 	            nop\.i 0x0
+    262c:	00 00 04 00       	            nop\.i 0x0;;
+    2630:	21 96 01 00 00 21 	\[MII\] \(p49\) mov r50=r0
+    2636:	00 00 00 02 00 00 	            nop\.i 0x0
+    263c:	00 00 04 00       	            nop\.i 0x0;;
+    2640:	41 9e 01 00 00 21 	\[MII\] \(p50\) mov r51=r0
+    2646:	00 00 00 02 00 00 	            nop\.i 0x0
+    264c:	00 00 04 00       	            nop\.i 0x0;;
+    2650:	61 a6 01 00 00 21 	\[MII\] \(p51\) mov r52=r0
+    2656:	00 00 00 02 00 00 	            nop\.i 0x0
+    265c:	00 00 04 00       	            nop\.i 0x0;;
+    2660:	81 ae 01 00 00 21 	\[MII\] \(p52\) mov r53=r0
+    2666:	00 00 00 02 00 00 	            nop\.i 0x0
+    266c:	00 00 04 00       	            nop\.i 0x0;;
+    2670:	a1 b6 01 00 00 21 	\[MII\] \(p53\) mov r54=r0
+    2676:	00 00 00 02 00 00 	            nop\.i 0x0
+    267c:	00 00 04 00       	            nop\.i 0x0;;
+    2680:	c1 be 01 00 00 21 	\[MII\] \(p54\) mov r55=r0
+    2686:	00 00 00 02 00 00 	            nop\.i 0x0
+    268c:	00 00 04 00       	            nop\.i 0x0;;
+    2690:	e1 c6 01 00 00 21 	\[MII\] \(p55\) mov r56=r0
+    2696:	00 00 00 02 00 00 	            nop\.i 0x0
+    269c:	00 00 04 00       	            nop\.i 0x0;;
+    26a0:	01 cf 01 00 00 21 	\[MII\] \(p56\) mov r57=r0
+    26a6:	00 00 00 02 00 00 	            nop\.i 0x0
+    26ac:	00 00 04 00       	            nop\.i 0x0;;
+    26b0:	21 d7 01 00 00 21 	\[MII\] \(p57\) mov r58=r0
+    26b6:	00 00 00 02 00 00 	            nop\.i 0x0
+    26bc:	00 00 04 00       	            nop\.i 0x0;;
+    26c0:	41 df 01 00 00 21 	\[MII\] \(p58\) mov r59=r0
+    26c6:	00 00 00 02 00 00 	            nop\.i 0x0
+    26cc:	00 00 04 00       	            nop\.i 0x0;;
+    26d0:	61 e7 01 00 00 21 	\[MII\] \(p59\) mov r60=r0
+    26d6:	00 00 00 02 00 00 	            nop\.i 0x0
+    26dc:	00 00 04 00       	            nop\.i 0x0;;
+    26e0:	81 ef 01 00 00 21 	\[MII\] \(p60\) mov r61=r0
+    26e6:	00 00 00 02 00 00 	            nop\.i 0x0
+    26ec:	00 00 04 00       	            nop\.i 0x0;;
+    26f0:	a1 f7 01 00 00 21 	\[MII\] \(p61\) mov r62=r0
+    26f6:	00 00 00 02 00 00 	            nop\.i 0x0
+    26fc:	00 00 04 00       	            nop\.i 0x0;;
+    2700:	c1 ff 01 00 00 21 	\[MII\] \(p62\) mov r63=r0
+    2706:	00 00 00 02 00 00 	            nop\.i 0x0
+    270c:	00 00 04 00       	            nop\.i 0x0;;
+    2710:	e1 07 02 00 00 21 	\[MII\] \(p63\) mov r64=r0
+    2716:	00 00 00 02 00 00 	            nop\.i 0x0
+    271c:	00 00 04 00       	            nop\.i 0x0;;
+    2720:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2726:	00 00 00 02 00 20 	            nop\.m 0x0
+    272c:	00 00 cc 00       	            mov r1=pr;;
+    2730:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2736:	00 00 00 02 00 00 	            nop\.m 0x0
+    273c:	00 08 00 07       	            mov b0=r0;;
+    2740:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2746:	00 00 00 02 00 20 	            nop\.m 0x0
+    274c:	00 08 00 07       	            mov b1=r0;;
+    2750:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2756:	00 00 00 02 00 40 	            nop\.m 0x0
+    275c:	00 08 00 07       	            mov b2=r0;;
+    2760:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2766:	00 00 00 02 00 60 	            nop\.m 0x0
+    276c:	00 08 00 07       	            mov b3=r0;;
+    2770:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2776:	00 00 00 02 00 80 	            nop\.m 0x0
+    277c:	00 08 00 07       	            mov b4=r0;;
+    2780:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2786:	00 00 00 02 00 a0 	            nop\.m 0x0
+    278c:	00 08 00 07       	            mov b5=r0;;
+    2790:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2796:	00 00 00 02 00 c0 	            nop\.m 0x0
+    279c:	00 08 00 07       	            mov b6=r0;;
+    27a0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    27a6:	00 00 00 02 00 e0 	            nop\.m 0x0
+    27ac:	00 08 00 07       	            mov b7=r0;;
+    27b0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    27b6:	00 00 00 02 00 00 	            nop\.m 0x0
+    27bc:	00 08 00 07       	            mov b0=r0;;
+    27c0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    27c6:	10 00 00 44 08 00 	            mov\.m r1=ar\.k0
+    27cc:	00 00 04 00       	            nop\.i 0x0;;
+    27d0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    27d6:	10 00 04 44 08 00 	            mov\.m r1=ar\.k1
+    27dc:	00 00 04 00       	            nop\.i 0x0;;
+    27e0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    27e6:	10 00 08 44 08 00 	            mov\.m r1=ar\.k2
+    27ec:	00 00 04 00       	            nop\.i 0x0;;
+    27f0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    27f6:	10 00 0c 44 08 00 	            mov\.m r1=ar\.k3
+    27fc:	00 00 04 00       	            nop\.i 0x0;;
+    2800:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2806:	10 00 10 44 08 00 	            mov\.m r1=ar\.k4
+    280c:	00 00 04 00       	            nop\.i 0x0;;
+    2810:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2816:	10 00 14 44 08 00 	            mov\.m r1=ar\.k5
+    281c:	00 00 04 00       	            nop\.i 0x0;;
+    2820:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2826:	10 00 18 44 08 00 	            mov\.m r1=ar\.k6
+    282c:	00 00 04 00       	            nop\.i 0x0;;
+    2830:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2836:	10 00 1c 44 08 00 	            mov\.m r1=ar\.k7
+    283c:	00 00 04 00       	            nop\.i 0x0;;
+    2840:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2846:	10 00 40 44 08 00 	            mov\.m r1=ar\.rsc
+    284c:	00 00 04 00       	            nop\.i 0x0;;
+    2850:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2856:	10 00 44 44 08 00 	            mov\.m r1=ar\.bsp
+    285c:	00 00 04 00       	            nop\.i 0x0;;
+    2860:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2866:	10 00 48 44 08 00 	            mov\.m r1=ar\.bspstore
+    286c:	00 00 04 00       	            nop\.i 0x0;;
+    2870:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2876:	10 00 4c 44 08 00 	            mov\.m r1=ar\.rnat
+    287c:	00 00 04 00       	            nop\.i 0x0;;
+    2880:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2886:	10 00 54 44 08 00 	            mov\.m r1=ar21
+    288c:	00 00 04 00       	            nop\.i 0x0;;
+    2890:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2896:	10 00 60 44 08 00 	            mov\.m r1=ar24
+    289c:	00 00 04 00       	            nop\.i 0x0;;
+    28a0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    28a6:	10 00 64 44 08 00 	            mov\.m r1=ar25
+    28ac:	00 00 04 00       	            nop\.i 0x0;;
+    28b0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    28b6:	10 00 68 44 08 00 	            mov\.m r1=ar26
+    28bc:	00 00 04 00       	            nop\.i 0x0;;
+    28c0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    28c6:	10 00 6c 44 08 00 	            mov\.m r1=ar27
+    28cc:	00 00 04 00       	            nop\.i 0x0;;
+    28d0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    28d6:	10 00 70 44 08 00 	            mov\.m r1=ar28
+    28dc:	00 00 04 00       	            nop\.i 0x0;;
+    28e0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    28e6:	10 00 74 44 08 00 	            mov\.m r1=ar29
+    28ec:	00 00 04 00       	            nop\.i 0x0;;
+    28f0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    28f6:	10 00 78 44 08 00 	            mov\.m r1=ar30
+    28fc:	00 00 04 00       	            nop\.i 0x0;;
+    2900:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2906:	10 00 80 44 08 00 	            mov\.m r1=ar\.ccv
+    290c:	00 00 04 00       	            nop\.i 0x0;;
+    2910:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2916:	10 00 90 44 08 00 	            mov\.m r1=ar\.unat
+    291c:	00 00 04 00       	            nop\.i 0x0;;
+    2920:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2926:	10 00 a0 44 08 00 	            mov\.m r1=ar\.fpsr
+    292c:	00 00 04 00       	            nop\.i 0x0;;
+    2930:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2936:	10 00 c0 44 08 00 	            mov\.m r1=ar48
+    293c:	00 00 04 00       	            nop\.i 0x0;;
+    2940:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2946:	10 00 c4 44 08 00 	            mov\.m r1=ar49
+    294c:	00 00 04 00       	            nop\.i 0x0;;
+    2950:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2956:	10 00 c8 44 08 00 	            mov\.m r1=ar50
+    295c:	00 00 04 00       	            nop\.i 0x0;;
+    2960:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2966:	10 00 cc 44 08 00 	            mov\.m r1=ar51
+    296c:	00 00 04 00       	            nop\.i 0x0;;
+    2970:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2976:	10 00 d0 44 08 00 	            mov\.m r1=ar52
+    297c:	00 00 04 00       	            nop\.i 0x0;;
+    2980:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2986:	10 00 d4 44 08 00 	            mov\.m r1=ar53
+    298c:	00 00 04 00       	            nop\.i 0x0;;
+    2990:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2996:	10 00 d8 44 08 00 	            mov\.m r1=ar54
+    299c:	00 00 04 00       	            nop\.i 0x0;;
+    29a0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    29a6:	10 00 dc 44 08 00 	            mov\.m r1=ar55
+    29ac:	00 00 04 00       	            nop\.i 0x0;;
+    29b0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    29b6:	10 00 e0 44 08 00 	            mov\.m r1=ar56
+    29bc:	00 00 04 00       	            nop\.i 0x0;;
+    29c0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    29c6:	10 00 e4 44 08 00 	            mov\.m r1=ar57
+    29cc:	00 00 04 00       	            nop\.i 0x0;;
+    29d0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    29d6:	10 00 e8 44 08 00 	            mov\.m r1=ar58
+    29dc:	00 00 04 00       	            nop\.i 0x0;;
+    29e0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    29e6:	10 00 ec 44 08 00 	            mov\.m r1=ar59
+    29ec:	00 00 04 00       	            nop\.i 0x0;;
+    29f0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    29f6:	10 00 f0 44 08 00 	            mov\.m r1=ar60
+    29fc:	00 00 04 00       	            nop\.i 0x0;;
+    2a00:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2a06:	10 00 f4 44 08 00 	            mov\.m r1=ar61
+    2a0c:	00 00 04 00       	            nop\.i 0x0;;
+    2a10:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2a16:	10 00 f8 44 08 00 	            mov\.m r1=ar62
+    2a1c:	00 00 04 00       	            nop\.i 0x0;;
+    2a20:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2a26:	10 00 fc 44 08 00 	            mov\.m r1=ar63
+    2a2c:	00 00 04 00       	            nop\.i 0x0;;
+    2a30:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2a36:	00 00 00 02 00 20 	            nop\.m 0x0
+    2a3c:	00 00 ca 00       	            mov\.i r1=ar\.pfs;;
+    2a40:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2a46:	00 00 00 02 00 20 	            nop\.m 0x0
+    2a4c:	00 08 ca 00       	            mov\.i r1=ar\.lc;;
+    2a50:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2a56:	00 00 00 02 00 20 	            nop\.m 0x0
+    2a5c:	00 10 ca 00       	            mov\.i r1=ar\.ec;;
+    2a60:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2a66:	00 00 00 02 00 20 	            nop\.m 0x0
+    2a6c:	00 80 cb 00       	            mov\.i r1=ar112;;
+    2a70:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2a76:	00 00 00 02 00 20 	            nop\.m 0x0
+    2a7c:	00 88 cb 00       	            mov\.i r1=ar113;;
+    2a80:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2a86:	00 00 00 02 00 20 	            nop\.m 0x0
+    2a8c:	00 90 cb 00       	            mov\.i r1=ar114;;
+    2a90:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2a96:	00 00 00 02 00 20 	            nop\.m 0x0
+    2a9c:	00 98 cb 00       	            mov\.i r1=ar115;;
+    2aa0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2aa6:	00 00 00 02 00 20 	            nop\.m 0x0
+    2aac:	00 a0 cb 00       	            mov\.i r1=ar116;;
+    2ab0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2ab6:	00 00 00 02 00 20 	            nop\.m 0x0
+    2abc:	00 a8 cb 00       	            mov\.i r1=ar117;;
+    2ac0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2ac6:	00 00 00 02 00 20 	            nop\.m 0x0
+    2acc:	00 b0 cb 00       	            mov\.i r1=ar118;;
+    2ad0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2ad6:	00 00 00 02 00 20 	            nop\.m 0x0
+    2adc:	00 b8 cb 00       	            mov\.i r1=ar119;;
+    2ae0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2ae6:	00 00 00 02 00 20 	            nop\.m 0x0
+    2aec:	00 c0 cb 00       	            mov\.i r1=ar120;;
+    2af0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2af6:	00 00 00 02 00 20 	            nop\.m 0x0
+    2afc:	00 c8 cb 00       	            mov\.i r1=ar121;;
+    2b00:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2b06:	00 00 00 02 00 20 	            nop\.m 0x0
+    2b0c:	00 d0 cb 00       	            mov\.i r1=ar122;;
+    2b10:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2b16:	00 00 00 02 00 20 	            nop\.m 0x0
+    2b1c:	00 d8 cb 00       	            mov\.i r1=ar123;;
+    2b20:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2b26:	00 00 00 02 00 20 	            nop\.m 0x0
+    2b2c:	00 e0 cb 00       	            mov\.i r1=ar124;;
+    2b30:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2b36:	00 00 00 02 00 20 	            nop\.m 0x0
+    2b3c:	00 e8 cb 00       	            mov\.i r1=ar125;;
+    2b40:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2b46:	00 00 00 02 00 20 	            nop\.m 0x0
+    2b4c:	00 f0 cb 00       	            mov\.i r1=ar126;;
+    2b50:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2b56:	00 00 00 02 00 20 	            nop\.m 0x0
+    2b5c:	00 f8 cb 00       	            mov\.i r1=ar127;;
+    2b60:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2b66:	10 00 00 44 08 00 	            mov\.m r1=ar\.k0
+    2b6c:	00 00 04 00       	            nop\.i 0x0;;
+    2b70:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2b76:	10 00 04 44 08 00 	            mov\.m r1=ar\.k1
+    2b7c:	00 00 04 00       	            nop\.i 0x0;;
+    2b80:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2b86:	10 00 08 44 08 00 	            mov\.m r1=ar\.k2
+    2b8c:	00 00 04 00       	            nop\.i 0x0;;
+    2b90:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2b96:	10 00 0c 44 08 00 	            mov\.m r1=ar\.k3
+    2b9c:	00 00 04 00       	            nop\.i 0x0;;
+    2ba0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2ba6:	10 00 10 44 08 00 	            mov\.m r1=ar\.k4
+    2bac:	00 00 04 00       	            nop\.i 0x0;;
+    2bb0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2bb6:	10 00 14 44 08 00 	            mov\.m r1=ar\.k5
+    2bbc:	00 00 04 00       	            nop\.i 0x0;;
+    2bc0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2bc6:	10 00 18 44 08 00 	            mov\.m r1=ar\.k6
+    2bcc:	00 00 04 00       	            nop\.i 0x0;;
+    2bd0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2bd6:	10 00 1c 44 08 00 	            mov\.m r1=ar\.k7
+    2bdc:	00 00 04 00       	            nop\.i 0x0;;
+    2be0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2be6:	10 00 40 44 08 00 	            mov\.m r1=ar\.rsc
+    2bec:	00 00 04 00       	            nop\.i 0x0;;
+    2bf0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2bf6:	10 00 44 44 08 00 	            mov\.m r1=ar\.bsp
+    2bfc:	00 00 04 00       	            nop\.i 0x0;;
+    2c00:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2c06:	10 00 48 44 08 00 	            mov\.m r1=ar\.bspstore
+    2c0c:	00 00 04 00       	            nop\.i 0x0;;
+    2c10:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2c16:	10 00 4c 44 08 00 	            mov\.m r1=ar\.rnat
+    2c1c:	00 00 04 00       	            nop\.i 0x0;;
+    2c20:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2c26:	10 00 80 44 08 00 	            mov\.m r1=ar\.ccv
+    2c2c:	00 00 04 00       	            nop\.i 0x0;;
+    2c30:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2c36:	10 00 90 44 08 00 	            mov\.m r1=ar\.unat
+    2c3c:	00 00 04 00       	            nop\.i 0x0;;
+    2c40:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2c46:	10 00 a0 44 08 00 	            mov\.m r1=ar\.fpsr
+    2c4c:	00 00 04 00       	            nop\.i 0x0;;
+    2c50:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2c56:	10 00 b0 44 08 00 	            mov\.m r1=ar\.itc
+    2c5c:	00 00 04 00       	            nop\.i 0x0;;
+    2c60:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2c66:	00 00 00 02 00 20 	            nop\.m 0x0
+    2c6c:	00 00 ca 00       	            mov\.i r1=ar\.pfs;;
+    2c70:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2c76:	00 00 00 02 00 20 	            nop\.m 0x0
+    2c7c:	00 08 ca 00       	            mov\.i r1=ar\.lc;;
+    2c80:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2c86:	00 00 00 02 00 20 	            nop\.m 0x0
+    2c8c:	00 10 ca 00       	            mov\.i r1=ar\.ec;;
+    2c90:	1d 08 00 00 24 04 	\[MFB\]       mov r1=cr0
+    2c96:	00 00 00 02 00 00 	            nop\.f 0x0
+    2c9c:	00 00 00 20       	            nop\.b 0x0;;
+    2ca0:	1d 08 00 02 24 04 	\[MFB\]       mov r1=cr1
+    2ca6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2cac:	00 00 00 20       	            nop\.b 0x0;;
+    2cb0:	1d 08 00 04 24 04 	\[MFB\]       mov r1=cr2
+    2cb6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2cbc:	00 00 00 20       	            nop\.b 0x0;;
+    2cc0:	1d 08 00 10 24 04 	\[MFB\]       mov r1=cr8
+    2cc6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2ccc:	00 00 00 20       	            nop\.b 0x0;;
+    2cd0:	1d 08 00 12 24 04 	\[MFB\]       mov r1=cr9
+    2cd6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2cdc:	00 00 00 20       	            nop\.b 0x0;;
+    2ce0:	1d 08 00 20 24 04 	\[MFB\]       mov r1=cr16
+    2ce6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2cec:	00 00 00 20       	            nop\.b 0x0;;
+    2cf0:	1d 08 00 22 24 04 	\[MFB\]       mov r1=cr17
+    2cf6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2cfc:	00 00 00 20       	            nop\.b 0x0;;
+    2d00:	1d 08 00 26 24 04 	\[MFB\]       mov r1=cr19
+    2d06:	00 00 00 02 00 00 	            nop\.f 0x0
+    2d0c:	00 00 00 20       	            nop\.b 0x0;;
+    2d10:	1d 08 00 28 24 04 	\[MFB\]       mov r1=cr20
+    2d16:	00 00 00 02 00 00 	            nop\.f 0x0
+    2d1c:	00 00 00 20       	            nop\.b 0x0;;
+    2d20:	1d 08 00 2a 24 04 	\[MFB\]       mov r1=cr21
+    2d26:	00 00 00 02 00 00 	            nop\.f 0x0
+    2d2c:	00 00 00 20       	            nop\.b 0x0;;
+    2d30:	1d 08 00 2c 24 04 	\[MFB\]       mov r1=cr22
+    2d36:	00 00 00 02 00 00 	            nop\.f 0x0
+    2d3c:	00 00 00 20       	            nop\.b 0x0;;
+    2d40:	1d 08 00 2e 24 04 	\[MFB\]       mov r1=cr23
+    2d46:	00 00 00 02 00 00 	            nop\.f 0x0
+    2d4c:	00 00 00 20       	            nop\.b 0x0;;
+    2d50:	1d 08 00 30 24 04 	\[MFB\]       mov r1=cr24
+    2d56:	00 00 00 02 00 00 	            nop\.f 0x0
+    2d5c:	00 00 00 20       	            nop\.b 0x0;;
+    2d60:	1d 08 00 32 24 04 	\[MFB\]       mov r1=cr25
+    2d66:	00 00 00 02 00 00 	            nop\.f 0x0
+    2d6c:	00 00 00 20       	            nop\.b 0x0;;
+    2d70:	1d 08 00 80 24 04 	\[MFB\]       mov r1=cr64
+    2d76:	00 00 00 02 00 00 	            nop\.f 0x0
+    2d7c:	00 00 00 20       	            nop\.b 0x0;;
+    2d80:	1d 08 00 82 24 04 	\[MFB\]       mov r1=cr65
+    2d86:	00 00 00 02 00 00 	            nop\.f 0x0
+    2d8c:	00 00 00 20       	            nop\.b 0x0;;
+    2d90:	1d 08 00 84 24 04 	\[MFB\]       mov r1=cr66
+    2d96:	00 00 00 02 00 00 	            nop\.f 0x0
+    2d9c:	00 00 00 20       	            nop\.b 0x0;;
+    2da0:	1d 08 00 86 24 04 	\[MFB\]       mov r1=cr67
+    2da6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2dac:	00 00 00 20       	            nop\.b 0x0;;
+    2db0:	1d 08 00 88 24 04 	\[MFB\]       mov r1=cr68
+    2db6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2dbc:	00 00 00 20       	            nop\.b 0x0;;
+    2dc0:	1d 08 00 8a 24 04 	\[MFB\]       mov r1=cr69
+    2dc6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2dcc:	00 00 00 20       	            nop\.b 0x0;;
+    2dd0:	1d 08 00 8c 24 04 	\[MFB\]       mov r1=cr70
+    2dd6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2ddc:	00 00 00 20       	            nop\.b 0x0;;
+    2de0:	1d 08 00 8e 24 04 	\[MFB\]       mov r1=cr71
+    2de6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2dec:	00 00 00 20       	            nop\.b 0x0;;
+    2df0:	1d 08 00 90 24 04 	\[MFB\]       mov r1=cr72
+    2df6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2dfc:	00 00 00 20       	            nop\.b 0x0;;
+    2e00:	1d 08 00 92 24 04 	\[MFB\]       mov r1=cr73
+    2e06:	00 00 00 02 00 00 	            nop\.f 0x0
+    2e0c:	00 00 00 20       	            nop\.b 0x0;;
+    2e10:	1d 08 00 94 24 04 	\[MFB\]       mov r1=cr74
+    2e16:	00 00 00 02 00 00 	            nop\.f 0x0
+    2e1c:	00 00 00 20       	            nop\.b 0x0;;
+    2e20:	1d 08 00 a0 24 04 	\[MFB\]       mov r1=cr80
+    2e26:	00 00 00 02 00 00 	            nop\.f 0x0
+    2e2c:	00 00 00 20       	            nop\.b 0x0;;
+    2e30:	1d 08 00 a2 24 04 	\[MFB\]       mov r1=cr81
+    2e36:	00 00 00 02 00 00 	            nop\.f 0x0
+    2e3c:	00 00 00 20       	            nop\.b 0x0;;
+    2e40:	1d 08 00 00 24 04 	\[MFB\]       mov r1=cr0
+    2e46:	00 00 00 02 00 00 	            nop\.f 0x0
+    2e4c:	00 00 00 20       	            nop\.b 0x0;;
+    2e50:	1d 08 00 02 24 04 	\[MFB\]       mov r1=cr1
+    2e56:	00 00 00 02 00 00 	            nop\.f 0x0
+    2e5c:	00 00 00 20       	            nop\.b 0x0;;
+    2e60:	1d 08 00 04 24 04 	\[MFB\]       mov r1=cr2
+    2e66:	00 00 00 02 00 00 	            nop\.f 0x0
+    2e6c:	00 00 00 20       	            nop\.b 0x0;;
+    2e70:	1d 08 00 10 24 04 	\[MFB\]       mov r1=cr8
+    2e76:	00 00 00 02 00 00 	            nop\.f 0x0
+    2e7c:	00 00 00 20       	            nop\.b 0x0;;
+    2e80:	1d 08 00 20 24 04 	\[MFB\]       mov r1=cr16
+    2e86:	00 00 00 02 00 00 	            nop\.f 0x0
+    2e8c:	00 00 00 20       	            nop\.b 0x0;;
+    2e90:	1d 08 00 22 24 04 	\[MFB\]       mov r1=cr17
+    2e96:	00 00 00 02 00 00 	            nop\.f 0x0
+    2e9c:	00 00 00 20       	            nop\.b 0x0;;
+    2ea0:	1d 08 00 26 24 04 	\[MFB\]       mov r1=cr19
+    2ea6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2eac:	00 00 00 20       	            nop\.b 0x0;;
+    2eb0:	1d 08 00 2c 24 04 	\[MFB\]       mov r1=cr22
+    2eb6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2ebc:	00 00 00 20       	            nop\.b 0x0;;
+    2ec0:	1d 08 00 2e 24 04 	\[MFB\]       mov r1=cr23
+    2ec6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2ecc:	00 00 00 20       	            nop\.b 0x0;;
+    2ed0:	1d 08 00 30 24 04 	\[MFB\]       mov r1=cr24
+    2ed6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2edc:	00 00 00 20       	            nop\.b 0x0;;
+    2ee0:	1d 08 00 32 24 04 	\[MFB\]       mov r1=cr25
+    2ee6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2eec:	00 00 00 20       	            nop\.b 0x0;;
+    2ef0:	1d 08 00 80 24 04 	\[MFB\]       mov r1=cr64
+    2ef6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2efc:	00 00 00 20       	            nop\.b 0x0;;
+    2f00:	1d 08 00 82 24 04 	\[MFB\]       mov r1=cr65
+    2f06:	00 00 00 02 00 00 	            nop\.f 0x0
+    2f0c:	00 00 00 20       	            nop\.b 0x0;;
+    2f10:	1d 08 00 84 24 04 	\[MFB\]       mov r1=cr66
+    2f16:	00 00 00 02 00 00 	            nop\.f 0x0
+    2f1c:	00 00 00 20       	            nop\.b 0x0;;
+    2f20:	1d 08 00 86 24 04 	\[MFB\]       mov r1=cr67
+    2f26:	00 00 00 02 00 00 	            nop\.f 0x0
+    2f2c:	00 00 00 20       	            nop\.b 0x0;;
+    2f30:	1d 08 00 88 24 04 	\[MFB\]       mov r1=cr68
+    2f36:	00 00 00 02 00 00 	            nop\.f 0x0
+    2f3c:	00 00 00 20       	            nop\.b 0x0;;
+    2f40:	1d 08 00 8a 24 04 	\[MFB\]       mov r1=cr69
+    2f46:	00 00 00 02 00 00 	            nop\.f 0x0
+    2f4c:	00 00 00 20       	            nop\.b 0x0;;
+    2f50:	1d 08 00 8c 24 04 	\[MFB\]       mov r1=cr70
+    2f56:	00 00 00 02 00 00 	            nop\.f 0x0
+    2f5c:	00 00 00 20       	            nop\.b 0x0;;
+    2f60:	1d 08 00 8e 24 04 	\[MFB\]       mov r1=cr71
+    2f66:	00 00 00 02 00 00 	            nop\.f 0x0
+    2f6c:	00 00 00 20       	            nop\.b 0x0;;
+    2f70:	1d 08 00 90 24 04 	\[MFB\]       mov r1=cr72
+    2f76:	00 00 00 02 00 00 	            nop\.f 0x0
+    2f7c:	00 00 00 20       	            nop\.b 0x0;;
+    2f80:	1d 08 00 92 24 04 	\[MFB\]       mov r1=cr73
+    2f86:	00 00 00 02 00 00 	            nop\.f 0x0
+    2f8c:	00 00 00 20       	            nop\.b 0x0;;
+    2f90:	1d 08 00 a0 24 04 	\[MFB\]       mov r1=cr80
+    2f96:	00 00 00 02 00 00 	            nop\.f 0x0
+    2f9c:	00 00 00 20       	            nop\.b 0x0;;
+    2fa0:	1d 08 00 a2 24 04 	\[MFB\]       mov r1=cr81
+    2fa6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2fac:	00 00 00 20       	            nop\.b 0x0;;
+    2fb0:	1d 08 00 94 24 04 	\[MFB\]       mov r1=cr74
+    2fb6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2fbc:	00 00 00 20       	            nop\.b 0x0;;
+    2fc0:	1d 08 00 00 25 04 	\[MFB\]       mov r1=psr
+    2fc6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2fcc:	00 00 00 20       	            nop\.b 0x0;;
+    2fd0:	1d 08 00 00 21 04 	\[MFB\]       mov r1=psr\.um
+    2fd6:	00 00 00 02 00 00 	            nop\.f 0x0
+    2fdc:	00 00 00 20       	            nop\.b 0x0;;
+    2fe0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
+    2fe6:	00 00 00 02 00 20 	            nop\.m 0x0
+    2fec:	00 00 c0 00       	            mov r1=ip;;
+    2ff0:	09 08 00 06 14 04 	\[MMI\]       mov r1=pmc\[r3\]
+    2ff6:	20 00 10 28 08 00 	            mov r2=pmc\[r4\]
+    2ffc:	00 00 04 00       	            nop\.i 0x0;;
+    3000:	09 08 00 06 15 04 	\[MMI\]       mov r1=pmd\[r3\]
+    3006:	20 00 10 2a 08 00 	            mov r2=pmd\[r4\]
+    300c:	00 00 04 00       	            nop\.i 0x0;;
+    3010:	09 08 00 06 13 04 	\[MMI\]       mov r1=pkr\[r3\]
+    3016:	20 00 10 26 08 00 	            mov r2=pkr\[r4\]
+    301c:	00 00 04 00       	            nop\.i 0x0;;
+    3020:	09 08 00 06 10 04 	\[MMI\]       mov r1=rr\[r3\]
+    3026:	20 00 10 20 08 00 	            mov r2=rr\[r4\]
+    302c:	00 00 04 00       	            nop\.i 0x0;;
+    3030:	09 08 00 06 12 04 	\[MMI\]       mov r1=ibr\[r3\]
+    3036:	20 00 10 24 08 00 	            mov r2=ibr\[r4\]
+    303c:	00 00 04 00       	            nop\.i 0x0;;
+    3040:	09 08 00 06 11 04 	\[MMI\]       mov r1=dbr\[r3\]
+    3046:	20 00 10 22 08 00 	            mov r2=dbr\[r4\]
+    304c:	00 00 04 00       	            nop\.i 0x0;;
+    3050:	09 08 00 06 17 04 	\[MMI\]       mov r1=cpuid\[r3\]
+    3056:	20 00 10 2e 08 00 	            mov r2=cpuid\[r4\]
+    305c:	00 00 04 00       	            nop\.i 0x0;;
+    3060:	09 08 00 06 17 04 	\[MMI\]       mov r1=cpuid\[r3\]
+    3066:	20 00 10 2e 08 00 	            mov r2=cpuid\[r4\]
+    306c:	00 00 04 00       	            nop\.i 0x0;;
diff --git a/gas/testsuite/gas/ia64/regs.pl b/gas/testsuite/gas/ia64/regs.pl
new file mode 100644
index 0000000..ca51cc0
--- /dev/null
+++ b/gas/testsuite/gas/ia64/regs.pl
@@ -0,0 +1,150 @@
+print ".text\n";
+print "\t.type _start,@","function\n";
+print "_start:\n\n";
+
+print "// Fixed and stacked integer registers.\n";
+for ($i = 1; $i < 128; ++$i) {
+  print "\t{ .mii; mov r$i = r0; nop.i 0; nop.i 0;; }\n";
+}
+print "\n";
+
+print "// Alternate names for input registers\n";
+print "\t.regstk 96, 0, 0, 0\n";
+for ($i = 0; $i < 96; ++$i) {
+  print "\t{ .mii; mov in$i = r0; nop.i 0; nop.i 0;; }\n";
+}
+print "\n";
+
+print "// Alternate names for output registers\n";
+print "\t.regstk 0, 0, 96, 0\n";
+for ($i = 0; $i < 96; ++$i) {
+  print "\t{ .mii; mov out$i = r0; nop.i 0; nop.i 0;; }\n";
+}
+print "\n";
+
+print "// Alternate names for local registers\n";
+print "\t.regstk 0, 96, 0, 0\n";
+for ($i = 0; $i < 96; ++$i) {
+  print "\t{ .mii; mov loc$i = r0; nop.i 0; nop.i 0;; }\n";
+}
+print "\n";
+
+print "// Return value registers\n";
+for ($i = 0; $i < 4; ++$i) {
+  print "\t{ .mii; mov ret$i = r0; nop.i 0; nop.i 0;; }\n";
+}
+print "\n";
+
+print "\t{ .mii;\n";
+print "\tmov gp = r0\n";
+print "\tmov sp = r0\n";
+print "\tnop.i 0;; }\n\n";
+
+print "// Floating point registers\n";
+for ($i = 2; $i < 128; ++$i) {
+  print "\t{ .mfi; mov f$i = f0 ;; }\n";
+}
+print "\n";
+
+print "// Floating point argument registers\n";
+for ($i = 0; $i < 8; ++$i) {
+  print "\t{ .mfi; mov farg$i = f1 ;; }\n";
+}
+print "\n";
+
+print "// Floating point return value registers\n";
+for ($i = 0; $i < 8; ++$i) {
+  print "\t{ .mfi; mov fret$i = f1 ;; }\n";
+}
+print "\n";
+
+print "// Predicate registers\n";
+for ($i = 0; $i < 64; ++$i) {
+  print "\t{ .mii; (p$i)\tmov r", $i+1, " = r0; nop.i 0; nop.i 0;; }\n";
+}
+print "\n";
+
+print "// Predicates as a unit\n";
+print "\t{ .mmi; nop.m 0; mov r1 = pr ;; }\n";
+print "//\tmov r2 = pr.rot\n";
+print "\n";
+
+print "// Branch registers.\n";
+for ($i = 0; $i < 8; ++$i) {
+  print "\t{ .mmi; mov b$i = r0;; }\n";
+}
+print "\n";
+
+print "\t{ .mmi; mov rp = r0;; }\n";
+print "\n";
+
+print "// Application registers\n";
+@reserved = ( 8..15, 20, 22..23, 31, 33..35, 37..39, 41..47, 67..111 );
+%reserved = ();
+foreach $i (@reserved) {
+  $reserved{$i} = 1;
+}
+for ($i = 0; $i < 128; ++$i) {
+  print "//" if $reserved{$i};
+  print "\t{ .mmi; nop.m 0; mov r1 = ar$i ;; }";
+  print "\t\t// reserved" if $reserved{$i};
+  print "\n";
+}
+print "\n";
+
+print "// Application registers by name\n";
+for ($i = 0; $i < 8; ++$i) {
+  print "\t{ .mmi; nop.m 0; mov r1 = ar.k$i ;;}\n";
+}
+
+@regs = ( "rsc", "bsp", "bspstore", "rnat", "ccv", "unat", "fpsr", "itc",
+	  "pfs", "lc", "ec" );
+foreach $i (@regs) {
+  print "\t{ .mmi; nop.m 0; mov r1 = ar.$i ;; }\n";
+}
+print "\n";
+
+print "// Control registers\n";
+@reserved = ( 3..7, 10..15, 18, 26..63, 75..79, 82..127 );
+%reserved = ();
+foreach $i (@reserved) {
+  $reserved{$i} = 1;
+}
+for ($i = 0; $i < 128; ++$i) {
+  print "//" if $reserved{$i};
+  print "\t{ .mfb; mov r1 = cr$i ;; }";
+  print "\t\t// reserved" if $reserved{$i};
+  print "\n";
+}
+print "\n";
+
+print "// Control registers by name\n";
+@regs = ( "dcr", "itm", "iva", "pta", "ipsr", "isr", "iip",
+	  "iipa", "ifs", "iim", "iha", "lid", "ivr",
+	  "tpr", "eoi", "irr0", "irr1", "irr2", "irr3", "itv", "pmv",
+	  "lrr0", "lrr1", "cmcv" );
+# ias doesn't accept these, despite documentation to the contrary.
+# push @regs, "ida", "idtr", "iitr"
+foreach $i (@regs) {
+  print "\t{ .mfb; mov r1 = cr.$i ;; }\n";
+}
+print "\n";
+
+
+print "// Other registers\n";
+print "\t{ .mfb; mov r1 = psr ;; }\n";
+print "//\t{ .mfb; mov r1 = psr.l ;; }\n";
+print "\t{ .mfb; mov r1 = psr.um ;; }\n";
+print "\t{ .mmi; mov r1 = ip ;; }\n";
+print "\n";
+
+print "// Indirect register files\n";
+@regs = ("pmc", "pmd", "pkr", "rr", "ibr", "dbr", "CPUID", "cpuid");
+# ias doesn't accept these, despite documentation to the contrary.
+# push @regs, "itr", "dtr";
+foreach $i (@regs) {
+  print "\t{ .mmi\n";
+  print "\tmov r1 = ${i}[r3]\n";
+  print "\tmov r2 = ${i}[r4]\n";
+  print "\tnop.i 0;; }\n";
+}
diff --git a/gas/testsuite/gas/ia64/regs.s b/gas/testsuite/gas/ia64/regs.s
new file mode 100644
index 0000000..06226a5
--- /dev/null
+++ b/gas/testsuite/gas/ia64/regs.s
@@ -0,0 +1,1017 @@
+.text
+	.type _start,@function
+_start:
+
+// Fixed and stacked integer registers.
+	{ .mii; mov r1 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r2 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r3 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r4 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r5 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r6 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r7 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r8 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r9 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r10 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r11 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r12 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r13 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r14 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r15 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r16 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r17 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r18 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r19 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r20 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r21 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r22 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r23 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r24 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r25 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r26 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r27 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r28 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r29 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r30 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r31 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r32 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r33 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r34 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r35 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r36 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r37 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r38 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r39 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r40 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r41 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r42 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r43 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r44 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r45 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r46 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r47 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r48 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r49 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r50 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r51 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r52 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r53 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r54 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r55 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r56 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r57 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r58 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r59 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r60 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r61 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r62 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r63 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r64 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r65 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r66 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r67 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r68 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r69 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r70 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r71 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r72 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r73 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r74 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r75 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r76 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r77 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r78 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r79 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r80 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r81 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r82 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r83 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r84 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r85 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r86 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r87 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r88 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r89 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r90 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r91 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r92 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r93 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r94 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r95 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r96 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r97 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r98 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r99 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r100 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r101 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r102 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r103 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r104 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r105 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r106 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r107 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r108 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r109 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r110 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r111 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r112 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r113 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r114 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r115 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r116 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r117 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r118 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r119 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r120 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r121 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r122 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r123 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r124 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r125 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r126 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov r127 = r0; nop.i 0; nop.i 0;; }
+
+// Alternate names for input registers
+	.regstk 96, 0, 0, 0
+	{ .mii; mov in0 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in1 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in2 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in3 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in4 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in5 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in6 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in7 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in8 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in9 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in10 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in11 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in12 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in13 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in14 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in15 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in16 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in17 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in18 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in19 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in20 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in21 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in22 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in23 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in24 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in25 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in26 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in27 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in28 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in29 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in30 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in31 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in32 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in33 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in34 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in35 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in36 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in37 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in38 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in39 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in40 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in41 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in42 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in43 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in44 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in45 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in46 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in47 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in48 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in49 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in50 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in51 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in52 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in53 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in54 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in55 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in56 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in57 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in58 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in59 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in60 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in61 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in62 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in63 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in64 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in65 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in66 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in67 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in68 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in69 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in70 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in71 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in72 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in73 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in74 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in75 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in76 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in77 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in78 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in79 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in80 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in81 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in82 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in83 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in84 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in85 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in86 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in87 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in88 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in89 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in90 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in91 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in92 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in93 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in94 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov in95 = r0; nop.i 0; nop.i 0;; }
+
+// Alternate names for output registers
+	.regstk 0, 0, 96, 0
+	{ .mii; mov out0 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out1 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out2 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out3 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out4 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out5 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out6 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out7 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out8 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out9 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out10 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out11 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out12 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out13 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out14 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out15 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out16 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out17 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out18 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out19 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out20 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out21 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out22 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out23 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out24 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out25 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out26 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out27 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out28 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out29 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out30 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out31 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out32 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out33 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out34 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out35 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out36 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out37 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out38 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out39 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out40 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out41 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out42 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out43 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out44 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out45 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out46 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out47 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out48 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out49 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out50 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out51 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out52 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out53 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out54 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out55 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out56 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out57 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out58 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out59 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out60 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out61 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out62 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out63 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out64 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out65 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out66 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out67 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out68 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out69 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out70 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out71 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out72 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out73 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out74 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out75 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out76 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out77 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out78 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out79 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out80 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out81 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out82 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out83 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out84 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out85 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out86 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out87 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out88 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out89 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out90 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out91 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out92 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out93 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out94 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov out95 = r0; nop.i 0; nop.i 0;; }
+
+// Alternate names for local registers
+	.regstk 0, 96, 0, 0
+	{ .mii; mov loc0 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc1 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc2 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc3 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc4 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc5 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc6 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc7 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc8 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc9 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc10 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc11 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc12 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc13 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc14 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc15 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc16 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc17 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc18 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc19 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc20 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc21 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc22 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc23 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc24 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc25 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc26 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc27 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc28 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc29 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc30 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc31 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc32 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc33 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc34 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc35 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc36 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc37 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc38 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc39 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc40 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc41 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc42 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc43 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc44 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc45 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc46 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc47 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc48 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc49 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc50 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc51 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc52 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc53 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc54 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc55 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc56 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc57 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc58 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc59 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc60 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc61 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc62 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc63 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc64 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc65 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc66 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc67 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc68 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc69 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc70 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc71 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc72 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc73 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc74 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc75 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc76 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc77 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc78 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc79 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc80 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc81 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc82 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc83 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc84 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc85 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc86 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc87 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc88 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc89 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc90 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc91 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc92 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc93 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc94 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov loc95 = r0; nop.i 0; nop.i 0;; }
+
+// Return value registers
+	{ .mii; mov ret0 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov ret1 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov ret2 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; mov ret3 = r0; nop.i 0; nop.i 0;; }
+
+	{ .mii;
+	mov gp = r0
+	mov sp = r0
+	nop.i 0;; }
+
+// Floating point registers
+	{ .mfi; mov f2 = f0 ;; }
+	{ .mfi; mov f3 = f0 ;; }
+	{ .mfi; mov f4 = f0 ;; }
+	{ .mfi; mov f5 = f0 ;; }
+	{ .mfi; mov f6 = f0 ;; }
+	{ .mfi; mov f7 = f0 ;; }
+	{ .mfi; mov f8 = f0 ;; }
+	{ .mfi; mov f9 = f0 ;; }
+	{ .mfi; mov f10 = f0 ;; }
+	{ .mfi; mov f11 = f0 ;; }
+	{ .mfi; mov f12 = f0 ;; }
+	{ .mfi; mov f13 = f0 ;; }
+	{ .mfi; mov f14 = f0 ;; }
+	{ .mfi; mov f15 = f0 ;; }
+	{ .mfi; mov f16 = f0 ;; }
+	{ .mfi; mov f17 = f0 ;; }
+	{ .mfi; mov f18 = f0 ;; }
+	{ .mfi; mov f19 = f0 ;; }
+	{ .mfi; mov f20 = f0 ;; }
+	{ .mfi; mov f21 = f0 ;; }
+	{ .mfi; mov f22 = f0 ;; }
+	{ .mfi; mov f23 = f0 ;; }
+	{ .mfi; mov f24 = f0 ;; }
+	{ .mfi; mov f25 = f0 ;; }
+	{ .mfi; mov f26 = f0 ;; }
+	{ .mfi; mov f27 = f0 ;; }
+	{ .mfi; mov f28 = f0 ;; }
+	{ .mfi; mov f29 = f0 ;; }
+	{ .mfi; mov f30 = f0 ;; }
+	{ .mfi; mov f31 = f0 ;; }
+	{ .mfi; mov f32 = f0 ;; }
+	{ .mfi; mov f33 = f0 ;; }
+	{ .mfi; mov f34 = f0 ;; }
+	{ .mfi; mov f35 = f0 ;; }
+	{ .mfi; mov f36 = f0 ;; }
+	{ .mfi; mov f37 = f0 ;; }
+	{ .mfi; mov f38 = f0 ;; }
+	{ .mfi; mov f39 = f0 ;; }
+	{ .mfi; mov f40 = f0 ;; }
+	{ .mfi; mov f41 = f0 ;; }
+	{ .mfi; mov f42 = f0 ;; }
+	{ .mfi; mov f43 = f0 ;; }
+	{ .mfi; mov f44 = f0 ;; }
+	{ .mfi; mov f45 = f0 ;; }
+	{ .mfi; mov f46 = f0 ;; }
+	{ .mfi; mov f47 = f0 ;; }
+	{ .mfi; mov f48 = f0 ;; }
+	{ .mfi; mov f49 = f0 ;; }
+	{ .mfi; mov f50 = f0 ;; }
+	{ .mfi; mov f51 = f0 ;; }
+	{ .mfi; mov f52 = f0 ;; }
+	{ .mfi; mov f53 = f0 ;; }
+	{ .mfi; mov f54 = f0 ;; }
+	{ .mfi; mov f55 = f0 ;; }
+	{ .mfi; mov f56 = f0 ;; }
+	{ .mfi; mov f57 = f0 ;; }
+	{ .mfi; mov f58 = f0 ;; }
+	{ .mfi; mov f59 = f0 ;; }
+	{ .mfi; mov f60 = f0 ;; }
+	{ .mfi; mov f61 = f0 ;; }
+	{ .mfi; mov f62 = f0 ;; }
+	{ .mfi; mov f63 = f0 ;; }
+	{ .mfi; mov f64 = f0 ;; }
+	{ .mfi; mov f65 = f0 ;; }
+	{ .mfi; mov f66 = f0 ;; }
+	{ .mfi; mov f67 = f0 ;; }
+	{ .mfi; mov f68 = f0 ;; }
+	{ .mfi; mov f69 = f0 ;; }
+	{ .mfi; mov f70 = f0 ;; }
+	{ .mfi; mov f71 = f0 ;; }
+	{ .mfi; mov f72 = f0 ;; }
+	{ .mfi; mov f73 = f0 ;; }
+	{ .mfi; mov f74 = f0 ;; }
+	{ .mfi; mov f75 = f0 ;; }
+	{ .mfi; mov f76 = f0 ;; }
+	{ .mfi; mov f77 = f0 ;; }
+	{ .mfi; mov f78 = f0 ;; }
+	{ .mfi; mov f79 = f0 ;; }
+	{ .mfi; mov f80 = f0 ;; }
+	{ .mfi; mov f81 = f0 ;; }
+	{ .mfi; mov f82 = f0 ;; }
+	{ .mfi; mov f83 = f0 ;; }
+	{ .mfi; mov f84 = f0 ;; }
+	{ .mfi; mov f85 = f0 ;; }
+	{ .mfi; mov f86 = f0 ;; }
+	{ .mfi; mov f87 = f0 ;; }
+	{ .mfi; mov f88 = f0 ;; }
+	{ .mfi; mov f89 = f0 ;; }
+	{ .mfi; mov f90 = f0 ;; }
+	{ .mfi; mov f91 = f0 ;; }
+	{ .mfi; mov f92 = f0 ;; }
+	{ .mfi; mov f93 = f0 ;; }
+	{ .mfi; mov f94 = f0 ;; }
+	{ .mfi; mov f95 = f0 ;; }
+	{ .mfi; mov f96 = f0 ;; }
+	{ .mfi; mov f97 = f0 ;; }
+	{ .mfi; mov f98 = f0 ;; }
+	{ .mfi; mov f99 = f0 ;; }
+	{ .mfi; mov f100 = f0 ;; }
+	{ .mfi; mov f101 = f0 ;; }
+	{ .mfi; mov f102 = f0 ;; }
+	{ .mfi; mov f103 = f0 ;; }
+	{ .mfi; mov f104 = f0 ;; }
+	{ .mfi; mov f105 = f0 ;; }
+	{ .mfi; mov f106 = f0 ;; }
+	{ .mfi; mov f107 = f0 ;; }
+	{ .mfi; mov f108 = f0 ;; }
+	{ .mfi; mov f109 = f0 ;; }
+	{ .mfi; mov f110 = f0 ;; }
+	{ .mfi; mov f111 = f0 ;; }
+	{ .mfi; mov f112 = f0 ;; }
+	{ .mfi; mov f113 = f0 ;; }
+	{ .mfi; mov f114 = f0 ;; }
+	{ .mfi; mov f115 = f0 ;; }
+	{ .mfi; mov f116 = f0 ;; }
+	{ .mfi; mov f117 = f0 ;; }
+	{ .mfi; mov f118 = f0 ;; }
+	{ .mfi; mov f119 = f0 ;; }
+	{ .mfi; mov f120 = f0 ;; }
+	{ .mfi; mov f121 = f0 ;; }
+	{ .mfi; mov f122 = f0 ;; }
+	{ .mfi; mov f123 = f0 ;; }
+	{ .mfi; mov f124 = f0 ;; }
+	{ .mfi; mov f125 = f0 ;; }
+	{ .mfi; mov f126 = f0 ;; }
+	{ .mfi; mov f127 = f0 ;; }
+
+// Floating point argument registers
+	{ .mfi; mov farg0 = f1 ;; }
+	{ .mfi; mov farg1 = f1 ;; }
+	{ .mfi; mov farg2 = f1 ;; }
+	{ .mfi; mov farg3 = f1 ;; }
+	{ .mfi; mov farg4 = f1 ;; }
+	{ .mfi; mov farg5 = f1 ;; }
+	{ .mfi; mov farg6 = f1 ;; }
+	{ .mfi; mov farg7 = f1 ;; }
+
+// Floating point return value registers
+	{ .mfi; mov fret0 = f1 ;; }
+	{ .mfi; mov fret1 = f1 ;; }
+	{ .mfi; mov fret2 = f1 ;; }
+	{ .mfi; mov fret3 = f1 ;; }
+	{ .mfi; mov fret4 = f1 ;; }
+	{ .mfi; mov fret5 = f1 ;; }
+	{ .mfi; mov fret6 = f1 ;; }
+	{ .mfi; mov fret7 = f1 ;; }
+
+// Predicate registers
+	{ .mii; (p0)	mov r1 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p1)	mov r2 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p2)	mov r3 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p3)	mov r4 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p4)	mov r5 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p5)	mov r6 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p6)	mov r7 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p7)	mov r8 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p8)	mov r9 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p9)	mov r10 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p10)	mov r11 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p11)	mov r12 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p12)	mov r13 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p13)	mov r14 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p14)	mov r15 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p15)	mov r16 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p16)	mov r17 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p17)	mov r18 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p18)	mov r19 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p19)	mov r20 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p20)	mov r21 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p21)	mov r22 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p22)	mov r23 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p23)	mov r24 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p24)	mov r25 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p25)	mov r26 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p26)	mov r27 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p27)	mov r28 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p28)	mov r29 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p29)	mov r30 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p30)	mov r31 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p31)	mov r32 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p32)	mov r33 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p33)	mov r34 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p34)	mov r35 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p35)	mov r36 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p36)	mov r37 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p37)	mov r38 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p38)	mov r39 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p39)	mov r40 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p40)	mov r41 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p41)	mov r42 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p42)	mov r43 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p43)	mov r44 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p44)	mov r45 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p45)	mov r46 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p46)	mov r47 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p47)	mov r48 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p48)	mov r49 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p49)	mov r50 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p50)	mov r51 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p51)	mov r52 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p52)	mov r53 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p53)	mov r54 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p54)	mov r55 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p55)	mov r56 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p56)	mov r57 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p57)	mov r58 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p58)	mov r59 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p59)	mov r60 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p60)	mov r61 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p61)	mov r62 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p62)	mov r63 = r0; nop.i 0; nop.i 0;; }
+	{ .mii; (p63)	mov r64 = r0; nop.i 0; nop.i 0;; }
+
+// Predicates as a unit
+	{ .mmi; nop.m 0; mov r1 = pr ;; }
+//	mov r2 = pr.rot
+
+// Branch registers.
+	{ .mmi; mov b0 = r0;; }
+	{ .mmi; mov b1 = r0;; }
+	{ .mmi; mov b2 = r0;; }
+	{ .mmi; mov b3 = r0;; }
+	{ .mmi; mov b4 = r0;; }
+	{ .mmi; mov b5 = r0;; }
+	{ .mmi; mov b6 = r0;; }
+	{ .mmi; mov b7 = r0;; }
+
+	{ .mmi; mov rp = r0;; }
+
+// Application registers
+	{ .mmi; nop.m 0; mov r1 = ar0 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar1 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar2 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar3 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar4 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar5 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar6 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar7 ;; }
+//	{ .mmi; nop.m 0; mov r1 = ar8 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar9 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar10 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar11 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar12 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar13 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar14 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar15 ;; }		// reserved
+	{ .mmi; nop.m 0; mov r1 = ar16 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar17 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar18 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar19 ;; }
+//	{ .mmi; nop.m 0; mov r1 = ar20 ;; }		// reserved
+	{ .mmi; nop.m 0; mov r1 = ar21 ;; }
+//	{ .mmi; nop.m 0; mov r1 = ar22 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar23 ;; }		// reserved
+	{ .mmi; nop.m 0; mov r1 = ar24 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar25 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar26 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar27 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar28 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar29 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar30 ;; }
+//	{ .mmi; nop.m 0; mov r1 = ar31 ;; }		// reserved
+	{ .mmi; nop.m 0; mov r1 = ar32 ;; }
+//	{ .mmi; nop.m 0; mov r1 = ar33 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar34 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar35 ;; }		// reserved
+	{ .mmi; nop.m 0; mov r1 = ar36 ;; }
+//	{ .mmi; nop.m 0; mov r1 = ar37 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar38 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar39 ;; }		// reserved
+	{ .mmi; nop.m 0; mov r1 = ar40 ;; }
+//	{ .mmi; nop.m 0; mov r1 = ar41 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar42 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar43 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar44 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar45 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar46 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar47 ;; }		// reserved
+	{ .mmi; nop.m 0; mov r1 = ar48 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar49 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar50 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar51 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar52 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar53 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar54 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar55 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar56 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar57 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar58 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar59 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar60 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar61 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar62 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar63 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar64 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar65 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar66 ;; }
+//	{ .mmi; nop.m 0; mov r1 = ar67 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar68 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar69 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar70 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar71 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar72 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar73 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar74 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar75 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar76 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar77 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar78 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar79 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar80 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar81 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar82 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar83 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar84 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar85 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar86 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar87 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar88 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar89 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar90 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar91 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar92 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar93 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar94 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar95 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar96 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar97 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar98 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar99 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar100 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar101 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar102 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar103 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar104 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar105 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar106 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar107 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar108 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar109 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar110 ;; }		// reserved
+//	{ .mmi; nop.m 0; mov r1 = ar111 ;; }		// reserved
+	{ .mmi; nop.m 0; mov r1 = ar112 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar113 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar114 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar115 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar116 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar117 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar118 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar119 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar120 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar121 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar122 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar123 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar124 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar125 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar126 ;; }
+	{ .mmi; nop.m 0; mov r1 = ar127 ;; }
+
+// Application registers by name
+	{ .mmi; nop.m 0; mov r1 = ar.k0 ;;}
+	{ .mmi; nop.m 0; mov r1 = ar.k1 ;;}
+	{ .mmi; nop.m 0; mov r1 = ar.k2 ;;}
+	{ .mmi; nop.m 0; mov r1 = ar.k3 ;;}
+	{ .mmi; nop.m 0; mov r1 = ar.k4 ;;}
+	{ .mmi; nop.m 0; mov r1 = ar.k5 ;;}
+	{ .mmi; nop.m 0; mov r1 = ar.k6 ;;}
+	{ .mmi; nop.m 0; mov r1 = ar.k7 ;;}
+	{ .mmi; nop.m 0; mov r1 = ar.rsc ;; }
+	{ .mmi; nop.m 0; mov r1 = ar.bsp ;; }
+	{ .mmi; nop.m 0; mov r1 = ar.bspstore ;; }
+	{ .mmi; nop.m 0; mov r1 = ar.rnat ;; }
+	{ .mmi; nop.m 0; mov r1 = ar.ccv ;; }
+	{ .mmi; nop.m 0; mov r1 = ar.unat ;; }
+	{ .mmi; nop.m 0; mov r1 = ar.fpsr ;; }
+	{ .mmi; nop.m 0; mov r1 = ar.itc ;; }
+	{ .mmi; nop.m 0; mov r1 = ar.pfs ;; }
+	{ .mmi; nop.m 0; mov r1 = ar.lc ;; }
+	{ .mmi; nop.m 0; mov r1 = ar.ec ;; }
+
+// Control registers
+	{ .mfb; mov r1 = cr0 ;; }
+	{ .mfb; mov r1 = cr1 ;; }
+	{ .mfb; mov r1 = cr2 ;; }
+//	{ .mfb; mov r1 = cr3 ;; }		// reserved
+//	{ .mfb; mov r1 = cr4 ;; }		// reserved
+//	{ .mfb; mov r1 = cr5 ;; }		// reserved
+//	{ .mfb; mov r1 = cr6 ;; }		// reserved
+//	{ .mfb; mov r1 = cr7 ;; }		// reserved
+	{ .mfb; mov r1 = cr8 ;; }
+	{ .mfb; mov r1 = cr9 ;; }
+//	{ .mfb; mov r1 = cr10 ;; }		// reserved
+//	{ .mfb; mov r1 = cr11 ;; }		// reserved
+//	{ .mfb; mov r1 = cr12 ;; }		// reserved
+//	{ .mfb; mov r1 = cr13 ;; }		// reserved
+//	{ .mfb; mov r1 = cr14 ;; }		// reserved
+//	{ .mfb; mov r1 = cr15 ;; }		// reserved
+	{ .mfb; mov r1 = cr16 ;; }
+	{ .mfb; mov r1 = cr17 ;; }
+//	{ .mfb; mov r1 = cr18 ;; }		// reserved
+	{ .mfb; mov r1 = cr19 ;; }
+	{ .mfb; mov r1 = cr20 ;; }
+	{ .mfb; mov r1 = cr21 ;; }
+	{ .mfb; mov r1 = cr22 ;; }
+	{ .mfb; mov r1 = cr23 ;; }
+	{ .mfb; mov r1 = cr24 ;; }
+	{ .mfb; mov r1 = cr25 ;; }
+//	{ .mfb; mov r1 = cr26 ;; }		// reserved
+//	{ .mfb; mov r1 = cr27 ;; }		// reserved
+//	{ .mfb; mov r1 = cr28 ;; }		// reserved
+//	{ .mfb; mov r1 = cr29 ;; }		// reserved
+//	{ .mfb; mov r1 = cr30 ;; }		// reserved
+//	{ .mfb; mov r1 = cr31 ;; }		// reserved
+//	{ .mfb; mov r1 = cr32 ;; }		// reserved
+//	{ .mfb; mov r1 = cr33 ;; }		// reserved
+//	{ .mfb; mov r1 = cr34 ;; }		// reserved
+//	{ .mfb; mov r1 = cr35 ;; }		// reserved
+//	{ .mfb; mov r1 = cr36 ;; }		// reserved
+//	{ .mfb; mov r1 = cr37 ;; }		// reserved
+//	{ .mfb; mov r1 = cr38 ;; }		// reserved
+//	{ .mfb; mov r1 = cr39 ;; }		// reserved
+//	{ .mfb; mov r1 = cr40 ;; }		// reserved
+//	{ .mfb; mov r1 = cr41 ;; }		// reserved
+//	{ .mfb; mov r1 = cr42 ;; }		// reserved
+//	{ .mfb; mov r1 = cr43 ;; }		// reserved
+//	{ .mfb; mov r1 = cr44 ;; }		// reserved
+//	{ .mfb; mov r1 = cr45 ;; }		// reserved
+//	{ .mfb; mov r1 = cr46 ;; }		// reserved
+//	{ .mfb; mov r1 = cr47 ;; }		// reserved
+//	{ .mfb; mov r1 = cr48 ;; }		// reserved
+//	{ .mfb; mov r1 = cr49 ;; }		// reserved
+//	{ .mfb; mov r1 = cr50 ;; }		// reserved
+//	{ .mfb; mov r1 = cr51 ;; }		// reserved
+//	{ .mfb; mov r1 = cr52 ;; }		// reserved
+//	{ .mfb; mov r1 = cr53 ;; }		// reserved
+//	{ .mfb; mov r1 = cr54 ;; }		// reserved
+//	{ .mfb; mov r1 = cr55 ;; }		// reserved
+//	{ .mfb; mov r1 = cr56 ;; }		// reserved
+//	{ .mfb; mov r1 = cr57 ;; }		// reserved
+//	{ .mfb; mov r1 = cr58 ;; }		// reserved
+//	{ .mfb; mov r1 = cr59 ;; }		// reserved
+//	{ .mfb; mov r1 = cr60 ;; }		// reserved
+//	{ .mfb; mov r1 = cr61 ;; }		// reserved
+//	{ .mfb; mov r1 = cr62 ;; }		// reserved
+//	{ .mfb; mov r1 = cr63 ;; }		// reserved
+	{ .mfb; mov r1 = cr64 ;; }
+	{ .mfb; mov r1 = cr65 ;; }
+	{ .mfb; mov r1 = cr66 ;; }
+	{ .mfb; mov r1 = cr67 ;; }
+	{ .mfb; mov r1 = cr68 ;; }
+	{ .mfb; mov r1 = cr69 ;; }
+	{ .mfb; mov r1 = cr70 ;; }
+	{ .mfb; mov r1 = cr71 ;; }
+	{ .mfb; mov r1 = cr72 ;; }
+	{ .mfb; mov r1 = cr73 ;; }
+	{ .mfb; mov r1 = cr74 ;; }
+//	{ .mfb; mov r1 = cr75 ;; }		// reserved
+//	{ .mfb; mov r1 = cr76 ;; }		// reserved
+//	{ .mfb; mov r1 = cr77 ;; }		// reserved
+//	{ .mfb; mov r1 = cr78 ;; }		// reserved
+//	{ .mfb; mov r1 = cr79 ;; }		// reserved
+	{ .mfb; mov r1 = cr80 ;; }
+	{ .mfb; mov r1 = cr81 ;; }
+//	{ .mfb; mov r1 = cr82 ;; }		// reserved
+//	{ .mfb; mov r1 = cr83 ;; }		// reserved
+//	{ .mfb; mov r1 = cr84 ;; }		// reserved
+//	{ .mfb; mov r1 = cr85 ;; }		// reserved
+//	{ .mfb; mov r1 = cr86 ;; }		// reserved
+//	{ .mfb; mov r1 = cr87 ;; }		// reserved
+//	{ .mfb; mov r1 = cr88 ;; }		// reserved
+//	{ .mfb; mov r1 = cr89 ;; }		// reserved
+//	{ .mfb; mov r1 = cr90 ;; }		// reserved
+//	{ .mfb; mov r1 = cr91 ;; }		// reserved
+//	{ .mfb; mov r1 = cr92 ;; }		// reserved
+//	{ .mfb; mov r1 = cr93 ;; }		// reserved
+//	{ .mfb; mov r1 = cr94 ;; }		// reserved
+//	{ .mfb; mov r1 = cr95 ;; }		// reserved
+//	{ .mfb; mov r1 = cr96 ;; }		// reserved
+//	{ .mfb; mov r1 = cr97 ;; }		// reserved
+//	{ .mfb; mov r1 = cr98 ;; }		// reserved
+//	{ .mfb; mov r1 = cr99 ;; }		// reserved
+//	{ .mfb; mov r1 = cr100 ;; }		// reserved
+//	{ .mfb; mov r1 = cr101 ;; }		// reserved
+//	{ .mfb; mov r1 = cr102 ;; }		// reserved
+//	{ .mfb; mov r1 = cr103 ;; }		// reserved
+//	{ .mfb; mov r1 = cr104 ;; }		// reserved
+//	{ .mfb; mov r1 = cr105 ;; }		// reserved
+//	{ .mfb; mov r1 = cr106 ;; }		// reserved
+//	{ .mfb; mov r1 = cr107 ;; }		// reserved
+//	{ .mfb; mov r1 = cr108 ;; }		// reserved
+//	{ .mfb; mov r1 = cr109 ;; }		// reserved
+//	{ .mfb; mov r1 = cr110 ;; }		// reserved
+//	{ .mfb; mov r1 = cr111 ;; }		// reserved
+//	{ .mfb; mov r1 = cr112 ;; }		// reserved
+//	{ .mfb; mov r1 = cr113 ;; }		// reserved
+//	{ .mfb; mov r1 = cr114 ;; }		// reserved
+//	{ .mfb; mov r1 = cr115 ;; }		// reserved
+//	{ .mfb; mov r1 = cr116 ;; }		// reserved
+//	{ .mfb; mov r1 = cr117 ;; }		// reserved
+//	{ .mfb; mov r1 = cr118 ;; }		// reserved
+//	{ .mfb; mov r1 = cr119 ;; }		// reserved
+//	{ .mfb; mov r1 = cr120 ;; }		// reserved
+//	{ .mfb; mov r1 = cr121 ;; }		// reserved
+//	{ .mfb; mov r1 = cr122 ;; }		// reserved
+//	{ .mfb; mov r1 = cr123 ;; }		// reserved
+//	{ .mfb; mov r1 = cr124 ;; }		// reserved
+//	{ .mfb; mov r1 = cr125 ;; }		// reserved
+//	{ .mfb; mov r1 = cr126 ;; }		// reserved
+//	{ .mfb; mov r1 = cr127 ;; }		// reserved
+
+// Control registers by name
+	{ .mfb; mov r1 = cr.dcr ;; }
+	{ .mfb; mov r1 = cr.itm ;; }
+	{ .mfb; mov r1 = cr.iva ;; }
+	{ .mfb; mov r1 = cr.pta ;; }
+	{ .mfb; mov r1 = cr.ipsr ;; }
+	{ .mfb; mov r1 = cr.isr ;; }
+	{ .mfb; mov r1 = cr.iip ;; }
+	{ .mfb; mov r1 = cr.iipa ;; }
+	{ .mfb; mov r1 = cr.ifs ;; }
+	{ .mfb; mov r1 = cr.iim ;; }
+	{ .mfb; mov r1 = cr.iha ;; }
+	{ .mfb; mov r1 = cr.lid ;; }
+	{ .mfb; mov r1 = cr.ivr ;; }
+	{ .mfb; mov r1 = cr.tpr ;; }
+	{ .mfb; mov r1 = cr.eoi ;; }
+	{ .mfb; mov r1 = cr.irr0 ;; }
+	{ .mfb; mov r1 = cr.irr1 ;; }
+	{ .mfb; mov r1 = cr.irr2 ;; }
+	{ .mfb; mov r1 = cr.irr3 ;; }
+	{ .mfb; mov r1 = cr.itv ;; }
+	{ .mfb; mov r1 = cr.pmv ;; }
+	{ .mfb; mov r1 = cr.lrr0 ;; }
+	{ .mfb; mov r1 = cr.lrr1 ;; }
+	{ .mfb; mov r1 = cr.cmcv ;; }
+
+// Other registers
+	{ .mfb; mov r1 = psr ;; }
+//	{ .mfb; mov r1 = psr.l ;; }
+	{ .mfb; mov r1 = psr.um ;; }
+	{ .mmi; mov r1 = ip ;; }
+
+// Indirect register files
+	{ .mmi
+	mov r1 = pmc[r3]
+	mov r2 = pmc[r4]
+	nop.i 0;; }
+	{ .mmi
+	mov r1 = pmd[r3]
+	mov r2 = pmd[r4]
+	nop.i 0;; }
+	{ .mmi
+	mov r1 = pkr[r3]
+	mov r2 = pkr[r4]
+	nop.i 0;; }
+	{ .mmi
+	mov r1 = rr[r3]
+	mov r2 = rr[r4]
+	nop.i 0;; }
+	{ .mmi
+	mov r1 = ibr[r3]
+	mov r2 = ibr[r4]
+	nop.i 0;; }
+	{ .mmi
+	mov r1 = dbr[r3]
+	mov r2 = dbr[r4]
+	nop.i 0;; }
+	{ .mmi
+	mov r1 = CPUID[r3]
+	mov r2 = CPUID[r4]
+	nop.i 0;; }
+	{ .mmi
+	mov r1 = cpuid[r3]
+	mov r2 = cpuid[r4]
+	nop.i 0;; }
diff --git a/gas/testsuite/gas/vtable/vtable.exp b/gas/testsuite/gas/vtable/vtable.exp
index 0d3e1bc..992f800 100644
--- a/gas/testsuite/gas/vtable/vtable.exp
+++ b/gas/testsuite/gas/vtable/vtable.exp
@@ -20,6 +20,10 @@ if { ([istarget "*-*-elf*"]
      && ![istarget *-*-linux*aout*]
      && ![istarget *-*-linux*oldld*] } then {
 
+    if {[istarget "ia64-*"]} then {
+      return
+    }
+  
     # not supported by D30V
     if {[istarget "d30v-*-*"]} {
       return
diff --git a/include/ChangeLog b/include/ChangeLog
index 0dec2b1..82ad23f 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
+			  David Mosberger  <davidm@hpl.hp.com>
+
+	* dis-asm.h (print_insn_ia64): Declare.
+
 2000-04-05  Richard Henderson  <rth@cygnus.com>
 
 	* splay-tree.h (splay_tree_remove): Declare.
diff --git a/include/dis-asm.h b/include/dis-asm.h
index 6e6c04b..25cd4b5 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -157,6 +157,7 @@ extern int print_insn_big_mips		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_little_mips	PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_i386_att		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_i386_intel	PARAMS ((bfd_vma, disassemble_info*));
+extern int print_insn_ia64		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_i370		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_m68k		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_z8001		PARAMS ((bfd_vma, disassemble_info*));
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 3528516..b08dbdf 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,8 @@
+Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
+			  David Mosberger  <davidm@hpl.hp.com>
+
+	* ia64.h: New file.
+
 2000-04-14  H.J. Lu  <hjl@gnu.org>
 
 	* common.h (ELFOSABI_TRUE64): Renamed to ELFOSABI_TRU64.
diff --git a/include/elf/ia64.h b/include/elf/ia64.h
new file mode 100644
index 0000000..7067b9c
--- /dev/null
+++ b/include/elf/ia64.h
@@ -0,0 +1,167 @@
+/* IA-64 ELF support for BFD.
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+
+#ifndef _ELF_IA64_H
+#define _ELF_IA64_H
+
+/* Bits in the e_flags field of the Elf64_Ehdr:  */
+
+#define EF_IA_64_MASKOS	 0x0000000f	/* os-specific flags */
+#define EF_IA_64_ABI64	 (1 << 4)	/* 64-bit ABI */
+#define EF_IA_64_ARCH	 0xff000000	/* arch. version mask */
+
+/* ??? These four definitions are not part of the SVR4 ABI.
+   They were present in David's initial code drop, so it is probable
+   that they are used by HP/UX.  */
+#define EF_IA_64_TRAPNIL (1 << 0)	/* trap NIL pointer dereferences */
+#define EF_IA_64_EXT	 (1 << 2)	/* program uses arch. extensions */
+#define EF_IA_64_BE	 (1 << 3)	/* PSR BE bit set (big-endian) */
+#define EFA_IA_64_EAS2_3 0x23000000	/* ia64 EAS 2.3 */
+
+#define ELF_STRING_ia64_archext		".IA_64.archext"
+#define ELF_STRING_ia64_pltoff		".IA_64.pltoff"
+#define ELF_STRING_ia64_unwind		".IA_64.unwind"
+#define ELF_STRING_ia64_unwind_info	".IA_64.unwind_info"
+
+/* Bits in the sh_flags field of Elf64_Shdr:  */
+
+#define SHF_IA_64_SHORT		0x10000000	/* section near gp */
+#define SHF_IA_64_NORECOV	0x20000000	/* spec insns w/o recovery */
+
+/* Possible values for sh_type in Elf64_Shdr: */
+
+#define SHT_IA_64_EXT		(SHT_LOPROC + 0)	/* extension bits */
+#define SHT_IA_64_UNWIND	(SHT_LOPROC + 1)	/* unwind bits */
+
+/* Bits in the p_flags field of Elf64_Phdr:  */
+
+#define PF_IA_64_NORECOV	0x80000000
+
+/* Possible values for p_type in Elf64_Phdr:  */
+
+#define PT_IA_64_ARCHEXT	(PT_LOPROC + 0)	/* arch extension bits */
+#define PT_IA_64_UNWIND 	(PT_LOPROC + 1)	/* ia64 unwind bits */
+
+/* Possible values for d_tag in Elf64_Dyn:  */
+
+#define DT_IA_64_PLT_RESERVE	(DT_LOPROC + 0)
+
+/* ia64-specific relocation types: */
+
+/* Relocs apply to specific instructions within a bundle.  The least
+   significant 2 bits of the address indicate which instruction in the
+   bundle the reloc refers to (0=first slot, 1=second slow, 2=third
+   slot, 3=undefined) and the remaining bits give the address of the
+   bundle (16 byte aligned).
+
+   The top 5 bits of the reloc code specifies the expression type, the
+   low 3 bits the format of the data word being relocated.
+
+   ??? Relocations below marked ## are not part of the SVR4 processor
+   suppliment.  They were present in David's initial code drop, so it
+   is possible that they are used by HP/UX.  */
+
+#include "elf/reloc-macros.h"
+
+START_RELOC_NUMBERS (elf_ia64_reloc_type)
+  RELOC_NUMBER (R_IA64_NONE, 0x00)	/* none */
+
+  RELOC_NUMBER (R_IA64_IMM14, 0x21)	/* symbol + addend, add imm14 */
+  RELOC_NUMBER (R_IA64_IMM22, 0x22)	/* symbol + addend, add imm22 */
+  RELOC_NUMBER (R_IA64_IMM64, 0x23)	/* symbol + addend, mov imm64 */
+  RELOC_NUMBER (R_IA64_DIR32MSB, 0x24)	/* symbol + addend, data4 MSB */
+  RELOC_NUMBER (R_IA64_DIR32LSB, 0x25)	/* symbol + addend, data4 LSB */
+  RELOC_NUMBER (R_IA64_DIR64MSB, 0x26)	/* symbol + addend, data8 MSB */
+  RELOC_NUMBER (R_IA64_DIR64LSB, 0x27)	/* symbol + addend, data8 LSB */
+
+  RELOC_NUMBER (R_IA64_GPREL22, 0x2a)	/* @gprel(sym + add), add imm22 */
+  RELOC_NUMBER (R_IA64_GPREL64I, 0x2b)	/* @gprel(sym + add), mov imm64 */
+  RELOC_NUMBER (R_IA64_GPREL32MSB, 0x2c) /* @gprel(sym + add), data4 MSB ## */
+  RELOC_NUMBER (R_IA64_GPREL32LSB, 0x2d) /* @gprel(sym + add), data4 LSB ## */
+  RELOC_NUMBER (R_IA64_GPREL64MSB, 0x2e) /* @gprel(sym + add), data8 MSB */
+  RELOC_NUMBER (R_IA64_GPREL64LSB, 0x2f) /* @gprel(sym + add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_LTOFF22, 0x32)	/* @ltoff(sym + add), add imm22 */
+  RELOC_NUMBER (R_IA64_LTOFF64I, 0x33)	/* @ltoff(sym + add), mov imm64 */
+
+  RELOC_NUMBER (R_IA64_PLTOFF22, 0x3a)	/* @pltoff(sym + add), add imm22 */
+  RELOC_NUMBER (R_IA64_PLTOFF64I, 0x3b)	/* @pltoff(sym + add), mov imm64 */
+  RELOC_NUMBER (R_IA64_PLTOFF64MSB, 0x3e) /* @pltoff(sym + add), data8 MSB */
+  RELOC_NUMBER (R_IA64_PLTOFF64LSB, 0x3f) /* @pltoff(sym + add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_FPTR64I, 0x43)	/* @fptr(sym + add), mov imm64 */
+  RELOC_NUMBER (R_IA64_FPTR32MSB, 0x44)	/* @fptr(sym + add), data4 MSB */
+  RELOC_NUMBER (R_IA64_FPTR32LSB, 0x45)	/* @fptr(sym + add), data4 LSB */
+  RELOC_NUMBER (R_IA64_FPTR64MSB, 0x46)	/* @fptr(sym + add), data8 MSB */
+  RELOC_NUMBER (R_IA64_FPTR64LSB, 0x47)	/* @fptr(sym + add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_PCREL21B, 0x49)	/* @pcrel(sym + add), ptb, call */
+  RELOC_NUMBER (R_IA64_PCREL21M, 0x4a)	/* @pcrel(sym + add), chk.s */
+  RELOC_NUMBER (R_IA64_PCREL21F, 0x4b)	/* @pcrel(sym + add), fchkf */
+  RELOC_NUMBER (R_IA64_PCREL32MSB, 0x4c) /* @pcrel(sym + add), data4 MSB */
+  RELOC_NUMBER (R_IA64_PCREL32LSB, 0x4d) /* @pcrel(sym + add), data4 LSB */
+  RELOC_NUMBER (R_IA64_PCREL64MSB, 0x4e) /* @pcrel(sym + add), data8 MSB */
+  RELOC_NUMBER (R_IA64_PCREL64LSB, 0x4f) /* @pcrel(sym + add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR22, 0x52) /* @ltoff(@fptr(s+a)), imm22 */
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR64I, 0x53) /* @ltoff(@fptr(s+a)), imm64 */
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR64MSB, 0x56) /* @ltoff(@fptr(s+a)), 8 MSB ##*/
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR64LSB, 0x57) /* @ltoff(@fptr(s+a)), 8 LSB ##*/
+
+  RELOC_NUMBER (R_IA64_SEGBASE, 0x58)	/* set segment base for @segrel ## */
+  RELOC_NUMBER (R_IA64_SEGREL32MSB, 0x5c) /* @segrel(sym + add), data4 MSB */
+  RELOC_NUMBER (R_IA64_SEGREL32LSB, 0x5d) /* @segrel(sym + add), data4 LSB */
+  RELOC_NUMBER (R_IA64_SEGREL64MSB, 0x5e) /* @segrel(sym + add), data8 MSB */
+  RELOC_NUMBER (R_IA64_SEGREL64LSB, 0x5f) /* @segrel(sym + add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_SECREL32MSB, 0x64) /* @secrel(sym + add), data4 MSB */
+  RELOC_NUMBER (R_IA64_SECREL32LSB, 0x65) /* @secrel(sym + add), data4 LSB */
+  RELOC_NUMBER (R_IA64_SECREL64MSB, 0x66) /* @secrel(sym + add), data8 MSB */
+  RELOC_NUMBER (R_IA64_SECREL64LSB, 0x67) /* @secrel(sym + add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_REL32MSB, 0x6c)	/* data 4 + REL */
+  RELOC_NUMBER (R_IA64_REL32LSB, 0x6d)	/* data 4 + REL */
+  RELOC_NUMBER (R_IA64_REL64MSB, 0x6e)	/* data 8 + REL */
+  RELOC_NUMBER (R_IA64_REL64LSB, 0x6f)	/* data 8 + REL */
+
+  RELOC_NUMBER (R_IA64_LTV32MSB, 0x70)	/* symbol + addend, data4 MSB */
+  RELOC_NUMBER (R_IA64_LTV32LSB, 0x71)	/* symbol + addend, data4 LSB */
+  RELOC_NUMBER (R_IA64_LTV64MSB, 0x72)	/* symbol + addend, data8 MSB */
+  RELOC_NUMBER (R_IA64_LTV64LSB, 0x73)	/* symbol + addend, data8 LSB */
+
+  RELOC_NUMBER (R_IA64_IPLTMSB, 0x80)	/* dynamic reloc, imported PLT, MSB */
+  RELOC_NUMBER (R_IA64_IPLTLSB, 0x81)	/* dynamic reloc, imported PLT, LSB */
+  RELOC_NUMBER (R_IA64_EPLTMSB, 0x82)	/* dynamic reloc, exported PLT, ## */
+  RELOC_NUMBER (R_IA64_EPLTLSB, 0x83)	/* dynamic reloc, exported PLT, ## */
+  RELOC_NUMBER (R_IA64_COPY, 0x84)	/* dynamic reloc, data copy ## */
+  RELOC_NUMBER (R_IA64_LTOFF22X, 0x86)  /* LTOFF22, relaxable.  */
+  RELOC_NUMBER (R_IA64_LDXMOV, 0x87)	/* Use of LTOFF22X.  */
+
+  RELOC_NUMBER (R_IA64_TPREL22, 0x92)	 /* sym-TP+add, add imm22 ## */
+  RELOC_NUMBER (R_IA64_TPREL64MSB, 0x96) /* sym-TP+add, data8 MSB ## */
+  RELOC_NUMBER (R_IA64_TPREL64LSB, 0x97) /* sym-TP+add, data8 LSB ## */
+
+  RELOC_NUMBER (R_IA64_LTOFF_TP22, 0x9a) /* @ltoff(sym-TP+add), add imm22 ## */
+
+  FAKE_RELOC (R_IA64_MAX_RELOC_CODE, 0x9a)
+END_RELOC_NUMBERS
+
+#endif /* _ELF_IA64_H */
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 7452c2b..cb2d5fe 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,10 @@
+Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
+			  David Mosberger  <davidm@hpl.hp.com>
+			  Timothy Wall <twall@cygnus.com>
+			  Jim Wilson  <wilson@cygnus.com>
+
+	* ia64.h: New file.
+
 2000-03-27  Nick Clifton  <nickc@cygnus.com>
 
 	* d30v.h (SHORT_A1): Fix value.
diff --git a/include/opcode/ia64.h b/include/opcode/ia64.h
new file mode 100644
index 0000000..dd6bccd
--- /dev/null
+++ b/include/opcode/ia64.h
@@ -0,0 +1,388 @@
+/* ia64.h -- Header file for ia64 opcode table
+   Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+
+   See the file HP-COPYRIGHT for additional information.  */
+
+#ifndef opcode_ia64_h
+#define opcode_ia64_h
+
+#include <sys/types.h>
+
+#include <bfd.h>
+
+
+typedef BFD_HOST_U_64_BIT ia64_insn;
+
+enum ia64_insn_type
+  {
+    IA64_TYPE_NIL = 0,	/* illegal type */
+    IA64_TYPE_A,	/* integer alu (I- or M-unit) */
+    IA64_TYPE_I,	/* non-alu integer (I-unit) */
+    IA64_TYPE_M,	/* memory (M-unit) */
+    IA64_TYPE_B,	/* branch (B-unit) */
+    IA64_TYPE_F,	/* floating-point (F-unit) */
+    IA64_TYPE_X,	/* long encoding (X-unit) */
+    IA64_TYPE_DYN,	/* Dynamic opcode */
+    IA64_NUM_TYPES
+  };
+
+enum ia64_unit
+  {
+    IA64_UNIT_NIL = 0,	/* illegal unit */
+    IA64_UNIT_I,	/* integer unit */
+    IA64_UNIT_M,	/* memory unit */
+    IA64_UNIT_B,	/* branching unit */
+    IA64_UNIT_F,	/* floating-point unit */
+    IA64_UNIT_L,	/* long "unit" */
+    IA64_UNIT_X,	/* may be integer or branch unit */
+    IA64_NUM_UNITS
+  };
+
+/* Changes to this enumeration must be propagated to the operand table in
+   bfd/cpu-ia64-opc.c 
+ */ 
+enum ia64_opnd
+  {
+    IA64_OPND_NIL,	/* no operand---MUST BE FIRST!*/
+
+    /* constants */
+    IA64_OPND_AR_CCV,	/* application register ccv (ar.ccv) */
+    IA64_OPND_AR_PFS,	/* application register pfs (ar.pfs) */
+    IA64_OPND_C1,	/* the constant 1 */
+    IA64_OPND_C8,	/* the constant 8 */
+    IA64_OPND_C16,	/* the constant 16 */
+    IA64_OPND_GR0,	/* gr0 */
+    IA64_OPND_IP,	/* instruction pointer (ip) */
+    IA64_OPND_PR,	/* predicate register (pr) */
+    IA64_OPND_PR_ROT,	/* rotating predicate register (pr.rot) */
+    IA64_OPND_PSR,	/* processor status register (psr) */
+    IA64_OPND_PSR_L,	/* processor status register L (psr.l) */
+    IA64_OPND_PSR_UM,	/* processor status register UM (psr.um) */
+
+    /* register operands: */
+    IA64_OPND_AR3,	/* third application register # (bits 20-26) */
+    IA64_OPND_B1,	/* branch register # (bits 6-8) */
+    IA64_OPND_B2,	/* branch register # (bits 13-15) */
+    IA64_OPND_CR3,	/* third control register # (bits 20-26) */
+    IA64_OPND_F1,	/* first floating-point register # */
+    IA64_OPND_F2,	/* second floating-point register # */
+    IA64_OPND_F3,	/* third floating-point register # */
+    IA64_OPND_F4,	/* fourth floating-point register # */
+    IA64_OPND_P1,	/* first predicate # */
+    IA64_OPND_P2,	/* second predicate # */
+    IA64_OPND_R1,	/* first register # */
+    IA64_OPND_R2,	/* second register # */
+    IA64_OPND_R3,	/* third register # */
+    IA64_OPND_R3_2,	/* third register # (limited to gr0-gr3) */
+
+    /* indirect operands: */
+    IA64_OPND_CPUID_R3,	/* cpuid[reg] */
+    IA64_OPND_DBR_R3,	/* dbr[reg] */
+    IA64_OPND_DTR_R3,	/* dtr[reg] */
+    IA64_OPND_ITR_R3,	/* itr[reg] */
+    IA64_OPND_IBR_R3,	/* ibr[reg] */
+    IA64_OPND_MR3,	/* memory at addr of third register # */
+    IA64_OPND_MSR_R3,	/* msr[reg] */
+    IA64_OPND_PKR_R3,	/* pkr[reg] */
+    IA64_OPND_PMC_R3,	/* pmc[reg] */
+    IA64_OPND_PMD_R3,	/* pmd[reg] */
+    IA64_OPND_RR_R3,	/* rr[reg] */
+
+    /* immediate operands: */
+    IA64_OPND_CCNT5,	/* 5-bit count (31 - bits 20-24) */
+    IA64_OPND_CNT2a,	/* 2-bit count (1 + bits 27-28) */
+    IA64_OPND_CNT2b,	/* 2-bit count (bits 27-28): 1, 2, 3 */
+    IA64_OPND_CNT2c,	/* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
+    IA64_OPND_CNT5,	/* 5-bit count (bits 14-18) */
+    IA64_OPND_CNT6,	/* 6-bit count (bits 27-32) */
+    IA64_OPND_CPOS6a,	/* 6-bit count (63 - bits 20-25) */
+    IA64_OPND_CPOS6b,	/* 6-bit count (63 - bits 14-19) */
+    IA64_OPND_CPOS6c,	/* 6-bit count (63 - bits 31-36) */
+    IA64_OPND_IMM1,	/* signed 1-bit immediate (bit 36) */
+    IA64_OPND_IMMU2,	/* unsigned 2-bit immediate (bits 13-14) */
+    IA64_OPND_IMMU7a,	/* unsigned 7-bit immediate (bits 13-19) */
+    IA64_OPND_IMMU7b,	/* unsigned 7-bit immediate (bits 20-26) */
+    IA64_OPND_SOF,	/* 8-bit stack frame size */
+    IA64_OPND_SOL,	/* 8-bit size of locals */
+    IA64_OPND_SOR,	/* 6-bit number of rotating registers (scaled by 8) */
+    IA64_OPND_IMM8,	/* signed 8-bit immediate (bits 13-19 & 36) */
+    IA64_OPND_IMM8U4,	/* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
+    IA64_OPND_IMM8M1,	/* signed 8-bit immediate -1 (bits 13-19 & 36) */
+    IA64_OPND_IMM8M1U4,	/* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
+    IA64_OPND_IMM8M1U8,	/* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
+    IA64_OPND_IMMU9,	/* unsigned 9-bit immediate (bits 33-34, 20-26) */
+    IA64_OPND_IMM9a,	/* signed 9-bit immediate (bits 6-12, 27, 36) */
+    IA64_OPND_IMM9b,	/* signed 9-bit immediate (bits 13-19, 27, 36) */
+    IA64_OPND_IMM14,	/* signed 14-bit immediate (bits 13-19, 27-32, 36) */
+    IA64_OPND_IMM17,	/* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
+    IA64_OPND_IMMU21,	/* unsigned 21-bit immediate (bits 6-25, 36) */
+    IA64_OPND_IMM22,	/* signed 22-bit immediate (bits 13-19, 22-36) */
+    IA64_OPND_IMMU24,	/* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
+    IA64_OPND_IMM44,	/* signed 44-bit immediate (2^16*bits 6-32, 36) */
+    IA64_OPND_IMMU62,	/* unsigned 62-bit immediate */
+    IA64_OPND_IMMU64,	/* unsigned 64-bit immediate (lotsa bits...) */
+    IA64_OPND_INC3,	/* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
+    IA64_OPND_LEN4,	/* 4-bit count (bits 27-30 + 1) */
+    IA64_OPND_LEN6,	/* 6-bit count (bits 27-32 + 1) */
+    IA64_OPND_MBTYPE4,	/* 4-bit mux type (bits 20-23) */
+    IA64_OPND_MHTYPE8,	/* 8-bit mux type (bits 20-27) */
+    IA64_OPND_POS6,	/* 6-bit count (bits 14-19) */
+    IA64_OPND_TAG13,	/* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
+    IA64_OPND_TAG13b,	/* signed 13-bit tag (ip + 16*bits 24-32) */
+    IA64_OPND_TGT25,	/* signed 25-bit (ip + 16*bits 6-25, 36) */
+    IA64_OPND_TGT25b,	/* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
+    IA64_OPND_TGT25c,	/* signed 25-bit (ip + 16*bits 13-32, 36) */
+    IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
+
+    IA64_OPND_COUNT	/* # of operand types (MUST BE LAST!) */
+  };
+
+enum ia64_dependency_mode
+{
+  IA64_DV_RAW,
+  IA64_DV_WAW,
+  IA64_DV_WAR,
+};
+
+enum ia64_dependency_semantics
+{
+  IA64_DVS_NONE,
+  IA64_DVS_IMPLIED,
+  IA64_DVS_IMPLIEDF,
+  IA64_DVS_DATA,
+  IA64_DVS_INSTR,
+  IA64_DVS_SPECIFIC,
+  IA64_DVS_OTHER,
+};
+
+enum ia64_resource_specifier
+{
+  IA64_RS_ANY,
+  IA64_RS_AR_K,
+  IA64_RS_AR_UNAT,
+  IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
+  IA64_RS_ARb, /* 48-63, 112-127 */
+  IA64_RS_BR,
+  IA64_RS_CFM,
+  IA64_RS_CPUID,
+  IA64_RS_CR_IRR,
+  IA64_RS_CR_LRR,
+  IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
+  IA64_RS_DBR,
+  IA64_RS_FR,
+  IA64_RS_FRb,
+  IA64_RS_GR0,
+  IA64_RS_GR,
+  IA64_RS_IBR,
+  IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
+  IA64_RS_MSR,
+  IA64_RS_PKR,
+  IA64_RS_PMC,
+  IA64_RS_PMD,
+  IA64_RS_PR,
+  IA64_RS_PR63,
+  IA64_RS_RR,
+
+  IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
+  IA64_RS_CRX, /* CRs not in RS_CR */
+  IA64_RS_PSR, /* PSR bits */
+  IA64_RS_RSE, /* implementation-specific RSE resources */
+  IA64_RS_AR_FPSR,
+};
+
+enum ia64_rse_resource
+{
+  IA64_RSE_N_STACKED_PHYS,
+  IA64_RSE_BOF,
+  IA64_RSE_STORE_REG,
+  IA64_RSE_LOAD_REG,
+  IA64_RSE_BSPLOAD,
+  IA64_RSE_RNATBITINDEX,
+  IA64_RSE_CFLE,
+  IA64_RSE_NDIRTY,
+};
+
+/* Information about a given resource dependency */
+struct ia64_dependency
+{
+  /* Name of the resource */
+  const char *name;
+  /* Does this dependency need further specification? */
+  enum ia64_resource_specifier specifier;
+  /* Mode of dependency */
+  enum ia64_dependency_mode mode;
+  /* Dependency semantics */
+  enum ia64_dependency_semantics semantics;
+  /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
+#define REG_NONE (-1)
+  int regindex;
+  /* Special info on semantics */
+  const char *info;
+};
+
+/* Two arrays of indexes into the ia64_dependency table.
+   chks are dependencies to check for conflicts when an opcode is
+   encountered; regs are dependencies to register (mark as used) when an
+   opcode is used.  chks correspond to readers (RAW) or writers (WAW or
+   WAR) of a resource, while regs correspond to writers (RAW or WAW) and
+   readers (WAR) of a resource.  */
+struct ia64_opcode_dependency
+{
+  int nchks;
+  const unsigned short *chks;
+  int nregs;
+  const unsigned short *regs;
+};
+
+/* encode/extract the note/index for a dependency */
+#define RDEP(N,X) (((N)<<11)|(X))
+#define NOTE(X) (((X)>>11)&0x1F)
+#define DEP(X) ((X)&0x7FF)
+
+/* A template descriptor describes the execution units that are active
+   for each of the three slots.  It also specifies the location of
+   instruction group boundaries that may be present between two slots.  */
+struct ia64_templ_desc
+  {
+    int group_boundary;	/* 0=no boundary, 1=between slot 0 & 1, etc. */
+    enum ia64_unit exec_unit[3];
+    const char *name;
+  };
+
+/* The opcode table is an array of struct ia64_opcode.  */
+
+struct ia64_opcode
+  {
+    /* The opcode name.  */
+    const char *name;
+
+    /* The type of the instruction: */
+    enum ia64_insn_type type;
+
+    /* Number of output operands: */
+    int num_outputs;
+
+    /* The opcode itself.  Those bits which will be filled in with
+       operands are zeroes.  */
+    ia64_insn opcode;
+
+    /* The opcode mask.  This is used by the disassembler.  This is a
+       mask containing ones indicating those bits which must match the
+       opcode field, and zeroes indicating those bits which need not
+       match (and are presumably filled in by operands).  */
+    ia64_insn mask;
+
+    /* An array of operand codes.  Each code is an index into the
+       operand table.  They appear in the order which the operands must
+       appear in assembly code, and are terminated by a zero.  */
+    enum ia64_opnd operands[5];
+
+    /* One bit flags for the opcode.  These are primarily used to
+       indicate specific processors and environments support the
+       instructions.  The defined values are listed below. */
+    unsigned int flags;
+
+    /* Used by ia64_find_next_opcode (). */
+    short ent_index;
+
+    /* Opcode dependencies. */ 
+    const struct ia64_opcode_dependency *dependencies;
+  };
+
+/* Values defined for the flags field of a struct ia64_opcode.  */
+
+#define IA64_OPCODE_FIRST	(1<<0)	/* must be first in an insn group */
+#define IA64_OPCODE_X_IN_MLX	(1<<1)	/* insn is allowed in X slot of MLX */
+#define IA64_OPCODE_LAST	(1<<2)	/* must be last in an insn group */
+#define IA64_OPCODE_PRIV	(1<<3)	/* privileged instruct */
+#define IA64_OPCODE_SLOT2	(1<<4)	/* insn allowed in slot 2 only */
+#define IA64_OPCODE_NO_PRED	(1<<5)	/* insn cannot be predicated */
+#define IA64_OPCODE_PSEUDO	(1<<6)	/* insn is a pseudo-op */
+#define IA64_OPCODE_F2_EQ_F3	(1<<7)	/* constraint: F2 == F3 */
+#define IA64_OPCODE_LEN_EQ_64MCNT	(1<<8)	/* constraint: LEN == 64-CNT */
+#define IA64_OPCODE_MOD_RRBS    (1<<9) /* modifies all rrbs in CFM */
+
+/* A macro to extract the major opcode from an instruction.  */
+#define IA64_OP(i)	(((i) >> 37) & 0xf)
+
+enum ia64_operand_class
+  {
+    IA64_OPND_CLASS_CST,	/* constant */
+    IA64_OPND_CLASS_REG,	/* register */
+    IA64_OPND_CLASS_IND,	/* indirect register */
+    IA64_OPND_CLASS_ABS,	/* absolute value */
+    IA64_OPND_CLASS_REL,	/* IP-relative value */
+  };
+
+/* The operands table is an array of struct ia64_operand.  */
+
+struct ia64_operand
+{
+  enum ia64_operand_class class;
+
+  /* Set VALUE as the operand bits for the operand of type SELF in the
+     instruction pointed to by CODE.  If an error occurs, *CODE is not
+     modified and the returned string describes the cause of the
+     error.  If no error occurs, NULL is returned.  */
+  const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
+			 ia64_insn *code);
+
+  /* Extract the operand bits for an operand of type SELF from
+     instruction CODE store them in *VALUE.  If an error occurs, the
+     cause of the error is described by the string returned.  If no
+     error occurs, NULL is returned.  */
+  const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
+			  ia64_insn *value);
+
+  /* A string whose meaning depends on the operand class.  */
+
+  const char *str;
+
+  struct bit_field
+    {
+      /* The number of bits in the operand.  */
+      int bits;
+
+      /* How far the operand is left shifted in the instruction.  */
+      int shift;
+    }
+  field[4];		/* no operand has more than this many bit-fields */
+
+  unsigned int flags;
+
+  const char *desc;	/* brief description */
+};
+
+/* Values defined for the flags field of a struct ia64_operand.  */
+
+/* Disassemble as signed decimal (instead of hex): */
+#define IA64_OPND_FLAG_DECIMAL_SIGNED	(1<<0)
+/* Disassemble as unsigned decimal (instead of hex): */
+#define IA64_OPND_FLAG_DECIMAL_UNSIGNED	(1<<1)
+
+extern const struct ia64_templ_desc ia64_templ_desc[16];
+
+/* The tables are sorted by major opcode number and are otherwise in
+   the order in which the disassembler should consider instructions.  */
+extern struct ia64_opcode ia64_opcodes_a[];
+extern struct ia64_opcode ia64_opcodes_i[];
+extern struct ia64_opcode ia64_opcodes_m[];
+extern struct ia64_opcode ia64_opcodes_b[];
+extern struct ia64_opcode ia64_opcodes_f[];
+extern struct ia64_opcode ia64_opcodes_d[];
+
+
+extern struct ia64_opcode *ia64_find_opcode (const char *name);
+extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent);
+
+extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn,
+					    enum ia64_insn_type type);
+
+extern void ia64_free_opcode (struct ia64_opcode *ent);
+extern const struct ia64_dependency *ia64_find_dependency (int index);
+
+/* To avoid circular library dependencies, this array is implemented
+   in bfd/cpu-ia64-opc.c: */
+extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
+
+#endif /* opcode_ia64_h */
diff --git a/ld/ChangeLog b/ld/ChangeLog
index e46704a..45a174e 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,12 @@
+Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
+			  David Mosberger  <davidm@hpl.hp.com>
+
+	* Makefile.am (ALL_64_EMULATIONS): Add eelf64_ia64.o.
+	(eelf64_ia64.c): New rule.
+	* Makefile.in: Rebuild.
+	* configure.tgt (ia64-*-elf*, ia64-*-linux*): New targets.
+	* emulparams/elf64_ia64.sh: New file.
+	
 2000-04-21  Richard Henderson  <rth@cygnus.com>
 
 	* scripttempl/elfd30v.sc: Place .gcc_except_table.
diff --git a/ld/Makefile.am b/ld/Makefile.am
index 45c703a..caa7966 100644
--- a/ld/Makefile.am
+++ b/ld/Makefile.am
@@ -226,6 +226,7 @@ ALL_EMULATIONS = \
 	ez8002.o
 
 ALL_64_EMULATIONS = \
+	eelf64_ia64.o \
 	eelf64_sparc.o \
 	eelf64alpha.o \
 	eelf64bmip.o
@@ -449,6 +450,9 @@ eelf32i370.c: $(srcdir)/emulparams/elf32i370.sh \
 eelf64alpha.c: $(srcdir)/emulparams/elf64alpha.sh \
   $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} elf64alpha "$(tdir_elf64alpha)"
+eelf64_ia64.c: $(srcdir)/emulparams/elf64_ia64.sh \
+  $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} elf64_ia64 "$(tdir_elf64_ia64)"
 eelf64_sparc.c: $(srcdir)/emulparams/elf64_sparc.sh \
   $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} elf64_sparc "$(tdir_elf64_sparc)"
diff --git a/ld/Makefile.in b/ld/Makefile.in
index ab152f0..cd43781 100644
--- a/ld/Makefile.in
+++ b/ld/Makefile.in
@@ -175,7 +175,7 @@ LIBIBERTY = ../libiberty/libiberty.a
 ALL_EMULATIONS =  	ea29k.o 	eaixppc.o 	eaixrs6.o 	ealpha.o 	earcelf.o 	earmelf.o 	earmelf_oabi.o 	earmelf_linux.o 	earmelf_linux26.o 	earmaoutb.o 	earmaoutl.o 	earmcoff.o 	earmnbsd.o 	earmpe.o 	earm_epoc_pe.o 	eavr1200.o 	eavr23xx.o 	eavr44x4.o 	eavr4433.o 	eavr85xx.o 	eavrmega603.o 	eavrmega103.o 	eavrmega161.o 	ecoff_sparc.o 	ed10velf.o 	ed30velf.o 	ed30v_e.o 	ed30v_o.o 	edelta68.o 	eebmon29k.o 	eelf32_sparc.o 	eelf32_i960.o 	eelf32b4300.o 	eelf32bmip.o 	eelf32ebmip.o 	eelf32elmip.o 	eelf32bmipn32.o 	eelf32i370.o 	eelf32l4300.o 	eelf32lmip.o 	eelf32lppc.o 	eelf32lppcsim.o 	eelf32ppc.o 	eelf32ppcsim.o 	eelf32ppclinux.o 	eelf_i386.o 	eelf_i386_be.o 	egld960.o 	egld960coff.o 	eelf32fr30.o 	eelf32mcore.o 	eh8300.o 	eh8300h.o 	eh8300s.o 	eh8500.o 	eh8500b.o 	eh8500c.o 	eh8500m.o 	eh8500s.o 	ehp300bsd.o 	ehp3hpux.o 	ei386aout.o 	ei386beos.o 	ei386bsd.o 	ei386coff.o 	ei386go32.o 	ei386linux.o 	ei386lynx.o 	ei386mach.o 	ei386moss.o 	ei386msdos.o 	ei386nbsd.o 	ei386nw.o 	ei386pe.o 	ei386pe_posix.o 	elnk960.o 	em68k4knbsd.o 	em68kaout.o 	em68kaux.o 	em68kcoff.o 	em68kelf.o 	em68klinux.o 	em68klynx.o 	em68knbsd.o 	em68kpsos.o 	em88kbcs.o 	emcorepe.o 	emipsbig.o 	emipsbsd.o 	emipsidt.o 	emipsidtl.o 	emipslit.o 	emipslnews.o 	emipspe.o 	enews.o 	epjelf.o 	epjlelf.o 	ens32knbsd.o 	epc532macha.o 	eppcmacos.o 	eppcnw.o 	eppcpe.o 	eriscix.o 	esa29200.o 	esh.o 	eshelf.o 	eshlelf.o 	eshl.o 	eshpe.o 	esparcaout.o 	esparclinux.o 	esparclynx.o 	esparcnbsd.o 	est2000.o 	esun3.o 	esun4.o 	etic30aout.o 	etic30coff.o 	etic80coff.o 	evanilla.o 	evax.o 	evsta.o 	ew65.o 	ez8001.o 	ez8002.o
 
 
-ALL_64_EMULATIONS =  	eelf64_sparc.o 	eelf64alpha.o 	eelf64bmip.o
+ALL_64_EMULATIONS =  	eelf64_ia64.o 	eelf64_sparc.o 	eelf64alpha.o 	eelf64bmip.o
 
 
 ALL_EMUL_EXTRA_OFILES =  	pe-dll.o 	deffilep.o
@@ -981,6 +981,9 @@ eelf32i370.c: $(srcdir)/emulparams/elf32i370.sh \
 eelf64alpha.c: $(srcdir)/emulparams/elf64alpha.sh \
   $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} elf64alpha "$(tdir_elf64alpha)"
+eelf64_ia64.c: $(srcdir)/emulparams/elf64_ia64.sh \
+  $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} elf64_ia64 "$(tdir_elf64_ia64)"
 eelf64_sparc.c: $(srcdir)/emulparams/elf64_sparc.sh \
   $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} elf64_sparc "$(tdir_elf64_sparc)"
diff --git a/ld/configure.tgt b/ld/configure.tgt
index 0cf81bd..b267c16 100644
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
@@ -79,6 +79,8 @@ i960-*-coff)		targ_emul=gld960coff ;;
 i960-intel-nindy)	targ_emul=gld960 ;;
 i960-*-rtems*)		targ_emul=gld960coff ;;
 i960-*-elf*)		targ_emul=elf32_i960 ;;
+ia64-*-elf*)		targ_emul=elf64_ia64 ;;
+ia64-*-linux*)		targ_emul=elf64_ia64 ;;
 m32r-*-*)		targ_emul=m32relf ;;
 m68*-sun-sunos[34]*)	targ_emul=sun3 ;;
 m68*-wrs-vxworks*)	targ_emul=sun3 ;;
diff --git a/ld/emulparams/elf64_ia64.sh b/ld/emulparams/elf64_ia64.sh
new file mode 100644
index 0000000..b3d393d
--- /dev/null
+++ b/ld/emulparams/elf64_ia64.sh
@@ -0,0 +1,16 @@
+# See genscripts.sh and ../scripttempl/elf.sc for the meaning of these.
+SCRIPT_NAME=elf
+ELFSIZE=64
+TEMPLATE_NAME=elf32
+OUTPUT_FORMAT="elf64-ia64-little"
+ARCH=ia64
+MACHINE=
+MAXPAGESIZE=0x10000
+TEXT_START_ADDR="0x4000000000000000"
+DATA_ADDR="0x6000000000000000 + (. & (${MAXPAGESIZE} - 1))"
+GENERATE_SHLIB_SCRIPT=yes
+NOP=0x00300000010070000002000001000400  # a bundle full of nops
+OTHER_GOT_SYMBOLS='. = ALIGN (8); PROVIDE (__gp = . + 0x200000);'
+OTHER_GOT_SECTIONS='.IA_64.pltoff : { *(.IA_64.pltoff) }'
+OTHER_PLT_RELOC_SECTIONS='.rela.IA_64.pltoff : { *(.rela.IA_64.pltoff) }'
+OTHER_READONLY_SECTIONS='.opd : { *(.opd) }'
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8c529a8..bb18a8a 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,26 @@
+Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
+			  David Mosberger  <davidm@hpl.hp.com>
+			  Timothy Wall <twall@cygnus.com>
+			  Bob Manson  <manson@charmed.cygnus.com>
+			  Jim Wilson  <wilson@cygnus.com>
+
+	* Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h.
+	(CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c,
+	ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-opc.c, ia64-gen.c,
+	ia64-asmtab.c.
+	(ALL_MACHINES): Add ia64-dis.lo, ia64-opc.lo.
+	(ia64-ic.tbl, ia64-raw.tbl, ia64-waw.tbl, ia64-war.tbl, ia64-gen,
+	ia64-gen.o, ia64-asmtab.c, ia64-dis.lo, ia64-opc.lo): New rules.
+	* Makefile.in: Rebuild.
+	* configure Rebuild.
+	* configure.in (bfd_ia64_arch): New target.
+	* disassemble.c (ARCH_ia64): Define.
+	(disassembler): Support ARCH_ia64.
+	* ia64-asmtab.c, ia64-asmtab.h, ia64-dis.c, ia64-gen.c ia64-ic.tbl,
+	ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c,
+	ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl,
+	ia64-war.tbl, ia64-waw.tbl): New files.
+	
 2000-04-20  Alexandre Oliva  <aoliva@cygnus.com>
 
 	* m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 1f44cdc..3b21289 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -25,6 +25,8 @@ HFILES = \
 	mcore-opc.h \
 	sh-opc.h \
 	sysdep.h \
+	ia64-asmtab.h \
+	ia64-opc.h \
 	w65-opc.h \
 	z8k-opc.h
 
@@ -58,6 +60,16 @@ CFILES = \
 	i370-opc.c \
 	i386-dis.c \
 	i960-dis.c \
+	ia64-dis.c \
+	ia64-opc-a.c \
+	ia64-opc-b.c \
+	ia64-opc-f.c \
+	ia64-opc-i.c \
+	ia64-opc-m.c \
+	ia64-opc-d.c \
+	ia64-opc.c \
+	ia64-gen.c \
+	ia64-asmtab.c \
 	m32r-asm.c \
 	m32r-desc.c \
 	m32r-dis.c \
@@ -120,6 +132,8 @@ ALL_MACHINES = \
 	i370-dis.lo \
 	i370-opc.lo \
 	i960-dis.lo \
+	ia64-dis.lo \
+	ia64-opc.lo \
 	m32r-asm.lo \
 	m32r-desc.lo \
 	m32r-dis.lo \
@@ -202,6 +216,23 @@ CLEANFILES = \
 
 
 
+ia64-ic.tbl: $(srcdir)/ia64-ic.tbl
+	$(LN_S) -f $(srcdir)/ia64-ic.tbl
+ia64-raw.tbl: $(srcdir)/ia64-raw.tbl
+	$(LN_S) -f $(srcdir)/ia64-raw.tbl
+ia64-waw.tbl: $(srcdir)/ia64-waw.tbl
+	$(LN_S) -f $(srcdir)/ia64-waw.tbl
+ia64-war.tbl: $(srcdir)/ia64-war.tbl
+	$(LN_S) -f $(srcdir)/ia64-war.tbl
+
+ia64-gen: ia64-gen.o
+	$(LINK) ia64-gen.o $(LIBIBERTY)
+
+ia64-gen.o: ia64-gen.c ia64-opc.c ia64-opc-a.c ia64-opc-b.c ia64-opc-f.c \
+  ia64-opc-i.c ia64-opc-m.c ia64-opc-d.c ia64-opc.h
+
+ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl
+	./ia64-gen > $(srcdir)/ia64-asmtab.c
 
 # This dependency stuff is copied from BFD.
 
@@ -315,6 +346,9 @@ i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h sysdep.h config.h opintl.h
 i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H)
+ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ia64.h $(BFD_H)
+ia64-opc.lo: $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h sysdep.h ia64-asmtab.h ia64-asmtab.c
 m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
   m32r-opc.h opintl.h
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 7e64477..5d25c9a 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -128,6 +128,8 @@ HFILES = \
 	mcore-opc.h \
 	sh-opc.h \
 	sysdep.h \
+	ia64-asmtab.h \
+	ia64-opc.h \
 	w65-opc.h \
 	z8k-opc.h
 
@@ -162,6 +164,16 @@ CFILES = \
 	i370-opc.c \
 	i386-dis.c \
 	i960-dis.c \
+	ia64-dis.c \
+	ia64-opc-a.c \
+	ia64-opc-b.c \
+	ia64-opc-f.c \
+	ia64-opc-i.c \
+	ia64-opc-m.c \
+	ia64-opc-d.c \
+	ia64-opc.c \
+	ia64-gen.c \
+	ia64-asmtab.c \
 	m32r-asm.c \
 	m32r-desc.c \
 	m32r-dis.c \
@@ -225,6 +237,8 @@ ALL_MACHINES = \
 	i370-dis.lo \
 	i370-opc.lo \
 	i960-dis.lo \
+	ia64-dis.lo \
+	ia64-opc.lo \
 	m32r-asm.lo \
 	m32r-desc.lo \
 	m32r-dis.lo \
@@ -676,6 +690,23 @@ all-redirect all-am all installdirs-am installdirs mostlyclean-generic \
 distclean-generic clean-generic maintainer-clean-generic clean \
 mostlyclean distclean maintainer-clean
 
+ia64-ic.tbl: $(srcdir)/ia64-ic.tbl
+	$(LN_S) -f $(srcdir)/ia64-ic.tbl
+ia64-raw.tbl: $(srcdir)/ia64-raw.tbl
+	$(LN_S) -f $(srcdir)/ia64-raw.tbl
+ia64-waw.tbl: $(srcdir)/ia64-waw.tbl
+	$(LN_S) -f $(srcdir)/ia64-waw.tbl
+ia64-war.tbl: $(srcdir)/ia64-war.tbl
+	$(LN_S) -f $(srcdir)/ia64-war.tbl
+
+ia64-gen: ia64-gen.o
+	$(LINK) ia64-gen.o $(LIBIBERTY)
+
+ia64-gen.o: ia64-gen.c ia64-opc.c ia64-opc-a.c ia64-opc-b.c ia64-opc-f.c \
+  ia64-opc-i.c ia64-opc-m.c ia64-opc-d.c ia64-opc.h
+
+ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl
+	./ia64-gen > $(srcdir)/ia64-asmtab.c
 
 disassemble.lo: disassemble.c $(INCDIR)/dis-asm.h
 	$(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $(srcdir)/disassemble.c
@@ -812,6 +843,9 @@ i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h sysdep.h config.h opintl.h
 i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H)
+ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ia64.h $(BFD_H)
+ia64-opc.lo: $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h sysdep.h ia64-asmtab.h ia64-asmtab.c
 m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
   m32r-opc.h opintl.h
diff --git a/opcodes/configure b/opcodes/configure
index 1b30f7e..99a7d20 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -3955,6 +3955,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_i386_arch)		ta="$ta i386-dis.lo" ;;
 	bfd_i860_arch)		;;
 	bfd_i960_arch)		ta="$ta i960-dis.lo" ;;
+	bfd_ia64_arch)		ta="$ta ia64-dis.lo ia64-opc.lo" ;;
 	bfd_m32r_arch)		ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
 	bfd_m68k_arch)		ta="$ta m68k-dis.lo m68k-opc.lo" ;;
 	bfd_m88k_arch)		ta="$ta m88k-dis.lo" ;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 6895c57..847897b 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -166,6 +166,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_i386_arch)		ta="$ta i386-dis.lo" ;;
 	bfd_i860_arch)		;;
 	bfd_i960_arch)		ta="$ta i960-dis.lo" ;;
+	bfd_ia64_arch)		ta="$ta ia64-dis.lo ia64-opc.lo" ;;
 	bfd_m32r_arch)		ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
 	bfd_m68k_arch)		ta="$ta m68k-dis.lo m68k-opc.lo" ;;
 	bfd_m88k_arch)		ta="$ta m88k-dis.lo" ;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 373b652..479e9e7 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -33,6 +33,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #define ARCH_i370
 #define ARCH_i386
 #define ARCH_i960
+#define ARCH_ia64
 #define ARCH_fr30
 #define ARCH_m32r
 #define ARCH_m68k
@@ -147,6 +148,11 @@ disassembler (abfd)
       disassemble = print_insn_i960;
       break;
 #endif
+#ifdef ARCH_ia64
+    case bfd_arch_ia64:
+      disassemble = print_insn_ia64;
+      break;
+#endif
 #ifdef ARCH_fr30
     case bfd_arch_fr30:
       disassemble = print_insn_fr30;
diff --git a/opcodes/ia64-asmtab.c b/opcodes/ia64-asmtab.c
new file mode 100644
index 0000000..6b30ec6
--- /dev/null
+++ b/opcodes/ia64-asmtab.c
@@ -0,0 +1,5580 @@
+/* This file is automatically generated by ia64-gen.  Do not edit! */
+static const char *ia64_strings[] = {
+  "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and",
+  "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call",
+  "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmpxchg1",
+  "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop", "czx1",
+  "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl", "exit",
+  "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand", "fandcm",
+  "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt", "fetchadd4",
+  "fetchadd8", "few", "fill", "flushrs", "fma", "fmax", "fmerge", "fmin",
+  "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma", "fnmpy", "fnorm", "for",
+  "fpabs", "fpack", "fpamax", "fpamin", "fpcmp", "fpcvt", "fpma", "fpmax",
+  "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg", "fpnegabs", "fpnma",
+  "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta", "fselect", "fsetc",
+  "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu", "g", "ga", "ge",
+  "getf", "geu", "gt", "gtu", "h", "hu", "i", "ia", "imp", "invala", "itc",
+  "itr", "l", "ld1", "ld2", "ld4", "ld8", "ldf", "ldf8", "ldfd", "ldfe",
+  "ldfp8", "ldfpd", "ldfps", "ldfs", "le", "leu", "lfetch", "loadrs",
+  "loop", "lr", "lt", "ltu", "lu", "m", "many", "mf", "mix1", "mix2",
+  "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne", "neq", "nge", "ngt",
+  "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1", "nt2", "nta", "nz",
+  "or", "orcm", "ord", "pack2", "pack4", "padd1", "padd2", "padd4", "pavg1",
+  "pavg2", "pavgsub1", "pavgsub2", "pcmp1", "pcmp2", "pcmp4", "pmax1",
+  "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2", "popcnt", "pr", "probe",
+  "psad1", "pshl2", "pshl4", "pshladd2", "pshr2", "pshr4", "pshradd2",
+  "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz", "rel", "ret", "rfi",
+  "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3", "sa", "se", "setf",
+  "shl", "shladd", "shladdp4", "shr", "shrp", "sig", "spill", "spnt",
+  "sptk", "srlz", "ssm", "sss", "st1", "st2", "st4", "st8", "stf", "stf8",
+  "stfd", "stfe", "stfs", "sub", "sum", "sxt1", "sxt2", "sxt4", "sync",
+  "tak", "tbit", "thash", "tnat", "tpa", "trunc", "ttag", "u", "unc",
+  "unord", "unpack1", "unpack2", "unpack4", "uss", "uus", "uuu", "w",
+  "wexit", "wtop", "x", "xchg1", "xchg2", "xchg4", "xchg8", "xf", "xma",
+  "xmpy", "xor", "xuf", "z", "zxt1", "zxt2", "zxt4",
+};
+
+static const struct ia64_dependency
+dependencies[] = {
+  { "ALAT", 0, 0, 0, -1, },
+  { "AR[BSP]", 25, 0, 2, 17, },
+  { "AR[BSPSTORE]", 25, 0, 2, 18, },
+  { "AR[CCV]", 25, 0, 2, 32, },
+  { "AR[EC]", 25, 0, 2, 66, },
+  { "AR[FPSR].sf0.controls", 29, 0, 2, -1, },
+  { "AR[FPSR].sf1.controls", 29, 0, 2, -1, },
+  { "AR[FPSR].sf2.controls", 29, 0, 2, -1, },
+  { "AR[FPSR].sf3.controls", 29, 0, 2, -1, },
+  { "AR[FPSR].sf0.flags", 29, 0, 2, -1, },
+  { "AR[FPSR].sf1.flags", 29, 0, 2, -1, },
+  { "AR[FPSR].sf2.flags", 29, 0, 2, -1, },
+  { "AR[FPSR].sf3.flags", 29, 0, 2, -1, },
+  { "AR[FPSR].traps", 29, 0, 2, -1, },
+  { "AR[FPSR].rv", 29, 0, 2, -1, },
+  { "AR[ITC]", 25, 0, 2, 44, },
+  { "AR[K%], % in 0 - 7", 1, 0, 2, -1, },
+  { "AR[LC]", 25, 0, 2, 65, },
+  { "AR[PFS]", 25, 0, 2, 64, },
+  { "AR[PFS]", 25, 0, 2, 64, },
+  { "AR[PFS]", 25, 0, 0, 64, },
+  { "AR[RNAT]", 25, 0, 2, 19, },
+  { "AR[RSC]", 25, 0, 2, 16, },
+  { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, },
+  { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, },
+  { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, },
+  { "BR%, % in 0 - 7", 5, 0, 2, -1, },
+  { "BR%, % in 0 - 7", 5, 0, 0, -1, },
+  { "BR%, % in 0 - 7", 5, 0, 2, -1, },
+  { "CFM", 6, 0, 2, -1, },
+  { "CFM", 6, 0, 2, -1, },
+  { "CFM", 6, 0, 2, -1, },
+  { "CFM", 6, 0, 2, -1, },
+  { "CFM", 6, 0, 0, -1, },
+  { "CPUID#", 7, 0, 5, -1, },
+  { "CR[CMCV]", 26, 0, 3, 74, },
+  { "CR[DCR]", 26, 0, 3, 0, },
+  { "CR[EOI]", 26, 0, 6, 67, "SC Section 10.8.3.4", },
+  { "CR[GPTA]", 26, 0, 3, 9, },
+  { "CR[IFA]", 26, 0, 1, 20, },
+  { "CR[IFA]", 26, 0, 3, 20, },
+  { "CR[IFS]", 26, 0, 3, 23, },
+  { "CR[IFS]", 26, 0, 1, 23, },
+  { "CR[IFS]", 26, 0, 1, 23, },
+  { "CR[IHA]", 26, 0, 3, 25, },
+  { "CR[IIM]", 26, 0, 3, 24, },
+  { "CR[IIP]", 26, 0, 3, 19, },
+  { "CR[IIP]", 26, 0, 1, 19, },
+  { "CR[IIPA]", 26, 0, 3, 22, },
+  { "CR[IPSR]", 26, 0, 3, 16, },
+  { "CR[IPSR]", 26, 0, 1, 16, },
+  { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, },
+  { "CR[ISR]", 26, 0, 3, 17, },
+  { "CR[ITIR]", 26, 0, 3, 21, },
+  { "CR[ITIR]", 26, 0, 1, 21, },
+  { "CR[ITM]", 26, 0, 3, 1, },
+  { "CR[ITV]", 26, 0, 3, 72, },
+  { "CR[IVA]", 26, 0, 4, 2, },
+  { "CR[IVR]", 26, 0, 6, 65, "SC Section 10.8.3.2", },
+  { "CR[LID]", 26, 0, 6, 64, "SC Section 10.8.3.1", },
+  { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, },
+  { "CR[PMV]", 26, 0, 3, 73, },
+  { "CR[PTA]", 26, 0, 3, 8, },
+  { "CR[TPR]", 26, 0, 3, 66, },
+  { "CR[TPR]", 26, 0, 6, 66, "SC Section 10.8.3.3", },
+  { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, },
+  { "DBR#", 11, 0, 2, -1, },
+  { "DBR#", 11, 0, 3, -1, },
+  { "DTC", 0, 0, 3, -1, },
+  { "DTC", 0, 0, 2, -1, },
+  { "DTC", 0, 0, 0, -1, },
+  { "DTC", 0, 0, 2, -1, },
+  { "DTC_LIMIT*", 0, 0, 2, -1, },
+  { "DTR", 0, 0, 3, -1, },
+  { "DTR", 0, 0, 2, -1, },
+  { "DTR", 0, 0, 3, -1, },
+  { "DTR", 0, 0, 0, -1, },
+  { "DTR", 0, 0, 2, -1, },
+  { "FR%, % in 0 - 1", 12, 0, 0, -1, },
+  { "FR%, % in 2 - 127", 13, 0, 2, -1, },
+  { "FR%, % in 2 - 127", 13, 0, 0, -1, },
+  { "GR0", 14, 0, 0, -1, },
+  { "GR%, % in 1 - 127", 15, 0, 0, -1, },
+  { "GR%, % in 1 - 127", 15, 0, 2, -1, },
+  { "IBR#", 16, 0, 2, -1, },
+  { "InService*", 17, 0, 3, -1, },
+  { "InService*", 17, 0, 2, -1, },
+  { "InService*", 17, 0, 2, -1, },
+  { "IP", 0, 0, 0, -1, },
+  { "ITC", 0, 0, 4, -1, },
+  { "ITC", 0, 0, 2, -1, },
+  { "ITC", 0, 0, 0, -1, },
+  { "ITC", 0, 0, 4, -1, },
+  { "ITC", 0, 0, 2, -1, },
+  { "ITC_LIMIT*", 0, 0, 2, -1, },
+  { "ITR", 0, 0, 2, -1, },
+  { "ITR", 0, 0, 4, -1, },
+  { "ITR", 0, 0, 2, -1, },
+  { "ITR", 0, 0, 0, -1, },
+  { "ITR", 0, 0, 4, -1, },
+  { "memory", 0, 0, 0, -1, },
+  { "MSR#", 18, 0, 5, -1, },
+  { "PKR#", 19, 0, 3, -1, },
+  { "PKR#", 19, 0, 0, -1, },
+  { "PKR#", 19, 0, 2, -1, },
+  { "PKR#", 19, 0, 2, -1, },
+  { "PMC#", 20, 0, 2, -1, },
+  { "PMC#", 20, 0, 6, -1, "SC+3 Section 12.1.1", },
+  { "PMD#", 21, 0, 2, -1, },
+  { "PR0", 0, 0, 0, -1, },
+  { "PR%, % in 1 - 62", 22, 0, 2, -1, },
+  { "PR%, % in 1 - 62", 22, 0, 2, -1, },
+  { "PR%, % in 1 - 62", 22, 0, 0, -1, },
+  { "PR63", 23, 0, 2, -1, },
+  { "PR63", 23, 0, 2, -1, },
+  { "PR63", 23, 0, 0, -1, },
+  { "PSR.ac", 27, 0, 1, 3, },
+  { "PSR.ac", 27, 0, 3, 3, },
+  { "PSR.ac", 27, 0, 2, 3, },
+  { "PSR.be", 27, 0, 1, 1, },
+  { "PSR.be", 27, 0, 3, 1, },
+  { "PSR.be", 27, 0, 2, 1, },
+  { "PSR.bn", 27, 0, 2, 44, },
+  { "PSR.cpl", 27, 0, 1, 32, },
+  { "PSR.da", 27, 0, 3, 38, },
+  { "PSR.db", 27, 0, 3, 24, },
+  { "PSR.db", 27, 0, 2, 24, },
+  { "PSR.db", 27, 0, 3, 24, },
+  { "PSR.dd", 27, 0, 3, 39, },
+  { "PSR.dfh", 27, 0, 3, 19, },
+  { "PSR.dfh", 27, 0, 2, 19, },
+  { "PSR.dfl", 27, 0, 3, 18, },
+  { "PSR.dfl", 27, 0, 2, 18, },
+  { "PSR.di", 27, 0, 3, 22, },
+  { "PSR.di", 27, 0, 2, 22, },
+  { "PSR.dt", 27, 0, 3, 17, },
+  { "PSR.dt", 27, 0, 2, 17, },
+  { "PSR.ed", 27, 0, 3, 43, },
+  { "PSR.i", 27, 0, 2, 14, },
+  { "PSR.i", 27, 0, 3, 14, },
+  { "PSR.ia", 27, 0, 0, 14, },
+  { "PSR.ic", 27, 0, 2, 13, },
+  { "PSR.ic", 27, 0, 3, 13, },
+  { "PSR.id", 27, 0, 0, 14, },
+  { "PSR.is", 27, 0, 0, 14, },
+  { "PSR.it", 27, 0, 3, 14, },
+  { "PSR.lp", 27, 0, 2, 25, },
+  { "PSR.lp", 27, 0, 3, 25, },
+  { "PSR.lp", 27, 0, 3, 25, },
+  { "PSR.mc", 27, 0, 0, 35, },
+  { "PSR.mfh", 27, 0, 2, 5, },
+  { "PSR.mfl", 27, 0, 2, 4, },
+  { "PSR.pk", 27, 0, 3, 15, },
+  { "PSR.pk", 27, 0, 2, 15, },
+  { "PSR.pp", 27, 0, 2, 21, },
+  { "PSR.ri", 27, 0, 0, 41, },
+  { "PSR.rt", 27, 0, 2, 27, },
+  { "PSR.rt", 27, 0, 3, 27, },
+  { "PSR.rt", 27, 0, 3, 27, },
+  { "PSR.si", 27, 0, 2, 23, },
+  { "PSR.si", 27, 0, 3, 23, },
+  { "PSR.sp", 27, 0, 2, 20, },
+  { "PSR.sp", 27, 0, 3, 20, },
+  { "PSR.ss", 27, 0, 3, 40, },
+  { "PSR.tb", 27, 0, 3, 26, },
+  { "PSR.tb", 27, 0, 2, 26, },
+  { "PSR.up", 27, 0, 2, 2, },
+  { "RR#", 24, 0, 3, -1, },
+  { "RR#", 24, 0, 2, -1, },
+  { "RSE", 28, 0, 2, -1, },
+  { "ALAT", 0, 1, 0, -1, },
+  { "AR[BSP]", 25, 1, 2, 17, },
+  { "AR[BSPSTORE]", 25, 1, 2, 18, },
+  { "AR[CCV]", 25, 1, 2, 32, },
+  { "AR[EC]", 25, 1, 2, 66, },
+  { "AR[FPSR].sf0.controls", 29, 1, 2, -1, },
+  { "AR[FPSR].sf1.controls", 29, 1, 2, -1, },
+  { "AR[FPSR].sf2.controls", 29, 1, 2, -1, },
+  { "AR[FPSR].sf3.controls", 29, 1, 2, -1, },
+  { "AR[FPSR].sf0.flags", 29, 1, 0, -1, },
+  { "AR[FPSR].sf0.flags", 29, 1, 2, -1, },
+  { "AR[FPSR].sf0.flags", 29, 1, 2, -1, },
+  { "AR[FPSR].sf1.flags", 29, 1, 0, -1, },
+  { "AR[FPSR].sf1.flags", 29, 1, 2, -1, },
+  { "AR[FPSR].sf1.flags", 29, 1, 2, -1, },
+  { "AR[FPSR].sf2.flags", 29, 1, 0, -1, },
+  { "AR[FPSR].sf2.flags", 29, 1, 2, -1, },
+  { "AR[FPSR].sf2.flags", 29, 1, 2, -1, },
+  { "AR[FPSR].sf3.flags", 29, 1, 0, -1, },
+  { "AR[FPSR].sf3.flags", 29, 1, 2, -1, },
+  { "AR[FPSR].sf3.flags", 29, 1, 2, -1, },
+  { "AR[FPSR].rv", 29, 1, 2, -1, },
+  { "AR[FPSR].traps", 29, 1, 2, -1, },
+  { "AR[ITC]", 25, 1, 2, 44, },
+  { "AR[K%], % in 0 - 7", 1, 1, 2, -1, },
+  { "AR[LC]", 25, 1, 2, 65, },
+  { "AR[PFS]", 25, 1, 0, 64, },
+  { "AR[PFS]", 25, 1, 2, 64, },
+  { "AR[PFS]", 25, 1, 2, 64, },
+  { "AR[RNAT]", 25, 1, 2, 19, },
+  { "AR[RSC]", 25, 1, 2, 16, },
+  { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, },
+  { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, },
+  { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, },
+  { "BR%, % in 0 - 7", 5, 1, 2, -1, },
+  { "BR%, % in 0 - 7", 5, 1, 2, -1, },
+  { "BR%, % in 0 - 7", 5, 1, 2, -1, },
+  { "BR%, % in 0 - 7", 5, 1, 0, -1, },
+  { "CFM", 6, 1, 2, -1, },
+  { "CPUID#", 7, 1, 0, -1, },
+  { "CR[CMCV]", 26, 1, 2, 74, },
+  { "CR[DCR]", 26, 1, 2, 0, },
+  { "CR[EOI]", 26, 1, 6, 67, "SC Section 10.8.3.4", },
+  { "CR[GPTA]", 26, 1, 2, 9, },
+  { "CR[IFA]", 26, 1, 2, 20, },
+  { "CR[IFS]", 26, 1, 2, 23, },
+  { "CR[IHA]", 26, 1, 2, 25, },
+  { "CR[IIM]", 26, 1, 2, 24, },
+  { "CR[IIP]", 26, 1, 2, 19, },
+  { "CR[IIPA]", 26, 1, 2, 22, },
+  { "CR[IPSR]", 26, 1, 2, 16, },
+  { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, },
+  { "CR[ISR]", 26, 1, 2, 17, },
+  { "CR[ITIR]", 26, 1, 2, 21, },
+  { "CR[ITM]", 26, 1, 2, 1, },
+  { "CR[ITV]", 26, 1, 2, 72, },
+  { "CR[IVA]", 26, 1, 2, 2, },
+  { "CR[IVR]", 26, 1, 6, 65, "SC", },
+  { "CR[LID]", 26, 1, 6, 64, "SC", },
+  { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, },
+  { "CR[PMV]", 26, 1, 2, 73, },
+  { "CR[PTA]", 26, 1, 2, 8, },
+  { "CR[TPR]", 26, 1, 2, 66, },
+  { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, },
+  { "DBR#", 11, 1, 2, -1, },
+  { "DTC", 0, 1, 0, -1, },
+  { "DTC", 0, 1, 2, -1, },
+  { "DTC", 0, 1, 2, -1, },
+  { "DTC_LIMIT*", 0, 1, 2, -1, },
+  { "DTR", 0, 1, 2, -1, },
+  { "DTR", 0, 1, 2, -1, },
+  { "DTR", 0, 1, 2, -1, },
+  { "DTR", 0, 1, 0, -1, },
+  { "FR%, % in 0 - 1", 12, 1, 0, -1, },
+  { "FR%, % in 2 - 127", 13, 1, 2, -1, },
+  { "GR0", 14, 1, 0, -1, },
+  { "GR%, % in 1 - 127", 15, 1, 2, -1, },
+  { "IBR#", 16, 1, 2, -1, },
+  { "InService*", 17, 1, 6, -1, "SC", },
+  { "IP", 0, 1, 0, -1, },
+  { "ITC", 0, 1, 0, -1, },
+  { "ITC", 0, 1, 2, -1, },
+  { "ITC", 0, 1, 2, -1, },
+  { "ITR", 0, 1, 2, -1, },
+  { "ITR", 0, 1, 2, -1, },
+  { "ITR", 0, 1, 0, -1, },
+  { "memory", 0, 1, 0, -1, },
+  { "MSR#", 18, 1, 6, -1, "SC", },
+  { "PKR#", 19, 1, 0, -1, },
+  { "PKR#", 19, 1, 0, -1, },
+  { "PKR#", 19, 1, 2, -1, },
+  { "PMC#", 20, 1, 2, -1, },
+  { "PMD#", 21, 1, 2, -1, },
+  { "PR0", 0, 1, 0, -1, },
+  { "PR%, % in 1 - 62", 22, 1, 0, -1, },
+  { "PR%, % in 1 - 62", 22, 1, 0, -1, },
+  { "PR%, % in 1 - 62", 22, 1, 2, -1, },
+  { "PR%, % in 1 - 62", 22, 1, 2, -1, },
+  { "PR63", 23, 1, 0, -1, },
+  { "PR63", 23, 1, 0, -1, },
+  { "PR63", 23, 1, 2, -1, },
+  { "PR63", 23, 1, 2, -1, },
+  { "PSR.ac", 27, 1, 2, 3, },
+  { "PSR.be", 27, 1, 2, 1, },
+  { "PSR.bn", 27, 1, 2, 44, },
+  { "PSR.cpl", 27, 1, 2, 32, },
+  { "PSR.da", 27, 1, 2, 38, },
+  { "PSR.db", 27, 1, 2, 24, },
+  { "PSR.dd", 27, 1, 2, 39, },
+  { "PSR.dfh", 27, 1, 2, 19, },
+  { "PSR.dfl", 27, 1, 2, 18, },
+  { "PSR.di", 27, 1, 2, 22, },
+  { "PSR.dt", 27, 1, 2, 17, },
+  { "PSR.ed", 27, 1, 2, 43, },
+  { "PSR.i", 27, 1, 2, 14, },
+  { "PSR.ia", 27, 1, 2, 14, },
+  { "PSR.ic", 27, 1, 2, 13, },
+  { "PSR.id", 27, 1, 2, 14, },
+  { "PSR.is", 27, 1, 2, 14, },
+  { "PSR.it", 27, 1, 2, 14, },
+  { "PSR.lp", 27, 1, 2, 25, },
+  { "PSR.mc", 27, 1, 2, 35, },
+  { "PSR.mfh", 27, 1, 0, 5, },
+  { "PSR.mfh", 27, 1, 2, 5, },
+  { "PSR.mfh", 27, 1, 2, 5, },
+  { "PSR.mfl", 27, 1, 0, 4, },
+  { "PSR.mfl", 27, 1, 2, 4, },
+  { "PSR.mfl", 27, 1, 2, 4, },
+  { "PSR.pk", 27, 1, 2, 15, },
+  { "PSR.pp", 27, 1, 2, 21, },
+  { "PSR.ri", 27, 1, 2, 41, },
+  { "PSR.rt", 27, 1, 2, 27, },
+  { "PSR.si", 27, 1, 2, 23, },
+  { "PSR.sp", 27, 1, 2, 20, },
+  { "PSR.ss", 27, 1, 2, 40, },
+  { "PSR.tb", 27, 1, 2, 26, },
+  { "PSR.up", 27, 1, 2, 2, },
+  { "RR#", 24, 1, 2, -1, },
+  { "RSE", 28, 1, 2, -1, },
+  { "PR63", 23, 2, 2, -1, },
+};
+
+static const short dep0[] = {
+  88, 249, 2131, 2294, 
+};
+
+static const short dep1[] = {
+  32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, 20602, 
+  
+};
+
+static const short dep2[] = {
+  2131, 2294, 
+};
+
+static const short dep3[] = {
+  32, 33, 2129, 2130, 2131, 2294, 4127, 20602, 
+};
+
+static const short dep4[] = {
+  32, 33, 81, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, 
+  20602, 
+};
+
+static const short dep5[] = {
+  88, 249, 2157, 2158, 2160, 2161, 2163, 2311, 2314, 2315, 2318, 2319, 
+};
+
+static const short dep6[] = {
+  32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2311, 2314, 2315, 
+  2318, 2319, 4127, 20602, 
+};
+
+static const short dep7[] = {
+  88, 249, 22637, 22638, 22640, 22641, 22643, 22791, 22794, 22795, 22798, 22799, 
+  
+};
+
+static const short dep8[] = {
+  32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, 22791, 
+  22794, 22795, 22798, 22799, 
+};
+
+static const short dep9[] = {
+  88, 249, 2312, 2314, 2316, 2318, 
+};
+
+static const short dep10[] = {
+  32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2312, 2315, 2316, 
+  2319, 4127, 20602, 
+};
+
+static const short dep11[] = {
+  88, 249, 2313, 2315, 2317, 2319, 
+};
+
+static const short dep12[] = {
+  32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2313, 2314, 2317, 
+  2318, 4127, 20602, 
+};
+
+static const short dep13[] = {
+  88, 249, 2312, 2313, 2314, 2315, 2316, 2317, 2318, 2319, 
+};
+
+static const short dep14[] = {
+  32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2312, 2313, 2314, 
+  2315, 2316, 2317, 2318, 2319, 4127, 20602, 
+};
+
+static const short dep15[] = {
+  88, 249, 2357, 
+};
+
+static const short dep16[] = {
+  32, 33, 88, 145, 163, 164, 249, 2074, 2075, 2157, 2159, 2160, 2162, 2163, 
+  4127, 
+};
+
+static const short dep17[] = {
+  88, 144, 249, 288, 2357, 28841, 28980, 
+};
+
+static const short dep18[] = {
+  1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, 
+  23, 24, 25, 32, 33, 88, 133, 145, 163, 164, 249, 288, 2074, 2075, 2157, 2159, 
+  2160, 2162, 2163, 4127, 28841, 28980, 
+};
+
+static const short dep19[] = {
+  1, 4, 32, 88, 123, 171, 174, 208, 249, 275, 2357, 28841, 28980, 
+};
+
+static const short dep20[] = {
+  1, 18, 20, 30, 32, 33, 88, 145, 147, 148, 163, 164, 171, 174, 208, 249, 275, 
+  2074, 2075, 2157, 2159, 2160, 2162, 2163, 4127, 28841, 28980, 
+};
+
+static const short dep21[] = {
+  1, 32, 43, 88, 171, 208, 215, 249, 28841, 28980, 
+};
+
+static const short dep22[] = {
+  1, 30, 32, 33, 88, 142, 163, 171, 208, 215, 249, 4127, 28841, 28980, 
+};
+
+static const short dep23[] = {
+  32, 88, 208, 249, 
+};
+
+static const short dep24[] = {
+  88, 163, 208, 249, 
+};
+
+static const short dep25[] = {
+  1, 32, 88, 117, 118, 120, 121, 122, 123, 124, 127, 128, 129, 130, 131, 132, 
+  133, 134, 135, 136, 137, 139, 140, 141, 142, 143, 144, 145, 148, 149, 150, 
+  151, 152, 153, 154, 155, 158, 159, 160, 161, 162, 163, 164, 165, 166, 171, 
+  208, 249, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 
+  285, 286, 287, 288, 289, 290, 291, 293, 294, 296, 297, 298, 299, 300, 301, 
+  302, 303, 304, 305, 306, 28841, 28980, 
+};
+
+static const short dep26[] = {
+  1, 30, 32, 33, 42, 43, 47, 50, 64, 88, 123, 163, 171, 208, 249, 272, 273, 
+  274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 
+  289, 290, 291, 293, 294, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 
+  306, 4127, 28841, 28980, 
+};
+
+static const short dep27[] = {
+  88, 122, 249, 274, 
+};
+
+static const short dep28[] = {
+  88, 123, 163, 249, 274, 
+};
+
+static const short dep29[] = {
+  88, 123, 249, 275, 
+};
+
+static const short dep30[] = {
+  18, 19, 88, 89, 92, 96, 99, 123, 145, 163, 249, 275, 
+};
+
+static const short dep31[] = {
+  32, 33, 88, 163, 249, 2157, 2159, 2160, 2162, 2163, 4127, 
+};
+
+static const short dep32[] = {
+  1, 18, 32, 88, 171, 196, 197, 208, 249, 2074, 2252, 2255, 2357, 28841, 28980, 
+  
+};
+
+static const short dep33[] = {
+  1, 4, 30, 32, 33, 88, 123, 145, 163, 164, 171, 196, 198, 208, 249, 2074, 2075, 
+  2157, 2159, 2160, 2162, 2163, 2253, 2255, 4127, 28841, 28980, 
+};
+
+static const short dep34[] = {
+  88, 249, 
+};
+
+static const short dep35[] = {
+  88, 163, 249, 2074, 2076, 
+};
+
+static const short dep36[] = {
+  32, 33, 88, 145, 163, 164, 249, 2157, 2159, 2160, 2162, 2163, 4127, 
+};
+
+static const short dep37[] = {
+  4, 29, 30, 31, 88, 113, 114, 174, 208, 249, 270, 271, 2357, 
+};
+
+static const short dep38[] = {
+  4, 29, 32, 33, 88, 145, 163, 164, 174, 208, 249, 270, 271, 309, 2157, 2159, 
+  2160, 2162, 2163, 4127, 
+};
+
+static const short dep39[] = {
+  17, 88, 195, 249, 2357, 
+};
+
+static const short dep40[] = {
+  17, 32, 33, 88, 145, 163, 164, 195, 249, 2157, 2159, 2160, 2162, 2163, 4127, 
+  
+};
+
+static const short dep41[] = {
+  4, 17, 29, 30, 31, 88, 113, 114, 174, 195, 208, 249, 270, 271, 2357, 
+};
+
+static const short dep42[] = {
+  4, 17, 29, 32, 33, 88, 145, 163, 164, 174, 195, 208, 249, 270, 271, 309, 2157, 
+  2159, 2160, 2162, 2163, 4127, 
+};
+
+static const short dep43[] = {
+  1, 4, 30, 32, 33, 88, 123, 145, 163, 164, 171, 196, 198, 208, 249, 2157, 2159, 
+  2160, 2162, 2163, 2253, 2255, 4127, 28841, 28980, 
+};
+
+static const short dep44[] = {
+  88, 163, 249, 
+};
+
+static const short dep45[] = {
+  9, 88, 179, 180, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, 
+  22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799, 
+};
+
+static const short dep46[] = {
+  5, 13, 14, 32, 33, 88, 163, 179, 181, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 22791, 22794, 22795, 
+  22798, 22799, 
+};
+
+static const short dep47[] = {
+  9, 10, 11, 12, 88, 179, 180, 182, 183, 185, 186, 188, 189, 249, 2127, 2292, 
+  18582, 18583, 18724, 18725, 18727, 18728, 22637, 22638, 22639, 22641, 22642, 
+  22791, 22794, 22795, 22798, 22799, 
+};
+
+static const short dep48[] = {
+  5, 6, 7, 8, 13, 14, 32, 33, 88, 163, 179, 181, 182, 184, 185, 187, 188, 190, 
+  249, 2126, 2127, 2128, 2157, 2158, 2161, 2292, 4127, 16513, 16515, 18724, 
+  18726, 18727, 18729, 22791, 22794, 22795, 22798, 22799, 
+};
+
+static const short dep49[] = {
+  10, 88, 182, 183, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, 
+  22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799, 
+};
+
+static const short dep50[] = {
+  6, 13, 14, 32, 33, 88, 163, 182, 184, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 22791, 22794, 22795, 
+  22798, 22799, 
+};
+
+static const short dep51[] = {
+  11, 88, 185, 186, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, 
+  22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799, 
+};
+
+static const short dep52[] = {
+  7, 13, 14, 32, 33, 88, 163, 185, 187, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 22791, 22794, 22795, 
+  22798, 22799, 
+};
+
+static const short dep53[] = {
+  12, 88, 188, 189, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, 
+  22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799, 
+};
+
+static const short dep54[] = {
+  8, 13, 14, 32, 33, 88, 163, 188, 190, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 22791, 22794, 22795, 
+  22798, 22799, 
+};
+
+static const short dep55[] = {
+  9, 88, 179, 180, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, 
+  
+};
+
+static const short dep56[] = {
+  5, 13, 14, 32, 33, 88, 163, 179, 181, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 
+};
+
+static const short dep57[] = {
+  9, 10, 11, 12, 88, 179, 180, 182, 183, 185, 186, 188, 189, 249, 2127, 2292, 
+  18582, 18583, 18724, 18725, 18727, 18728, 
+};
+
+static const short dep58[] = {
+  5, 6, 7, 8, 13, 14, 32, 33, 88, 163, 179, 181, 182, 184, 185, 187, 188, 190, 
+  249, 2126, 2127, 2128, 2157, 2158, 2161, 2292, 4127, 16513, 16515, 18724, 
+  18726, 18727, 18729, 
+};
+
+static const short dep59[] = {
+  10, 88, 182, 183, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, 
+  
+};
+
+static const short dep60[] = {
+  6, 13, 14, 32, 33, 88, 163, 182, 184, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 
+};
+
+static const short dep61[] = {
+  11, 88, 185, 186, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, 
+  
+};
+
+static const short dep62[] = {
+  7, 13, 14, 32, 33, 88, 163, 185, 187, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 
+};
+
+static const short dep63[] = {
+  12, 88, 188, 189, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, 
+  
+};
+
+static const short dep64[] = {
+  8, 13, 14, 32, 33, 88, 163, 188, 190, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 
+};
+
+static const short dep65[] = {
+  88, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, 
+};
+
+static const short dep66[] = {
+  32, 33, 88, 163, 249, 2126, 2127, 2128, 2157, 2158, 2161, 2292, 4127, 16513, 
+  16515, 18724, 18726, 18727, 18729, 
+};
+
+static const short dep67[] = {
+  5, 88, 175, 249, 
+};
+
+static const short dep68[] = {
+  5, 32, 33, 88, 163, 175, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep69[] = {
+  5, 32, 33, 88, 163, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep70[] = {
+  6, 88, 176, 249, 
+};
+
+static const short dep71[] = {
+  5, 32, 33, 88, 163, 176, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep72[] = {
+  7, 88, 177, 249, 
+};
+
+static const short dep73[] = {
+  5, 32, 33, 88, 163, 177, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep74[] = {
+  8, 88, 178, 249, 
+};
+
+static const short dep75[] = {
+  5, 32, 33, 88, 163, 178, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep76[] = {
+  9, 88, 180, 181, 249, 
+};
+
+static const short dep77[] = {
+  32, 33, 88, 163, 180, 181, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep78[] = {
+  32, 33, 88, 163, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep79[] = {
+  10, 88, 183, 184, 249, 
+};
+
+static const short dep80[] = {
+  32, 33, 88, 163, 183, 184, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep81[] = {
+  11, 88, 186, 187, 249, 
+};
+
+static const short dep82[] = {
+  32, 33, 88, 163, 186, 187, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep83[] = {
+  12, 88, 189, 190, 249, 
+};
+
+static const short dep84[] = {
+  32, 33, 88, 163, 189, 190, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep85[] = {
+  9, 13, 14, 32, 33, 88, 145, 163, 164, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep86[] = {
+  9, 10, 13, 14, 32, 33, 88, 145, 163, 164, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep87[] = {
+  9, 11, 13, 14, 32, 33, 88, 145, 163, 164, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep88[] = {
+  9, 12, 13, 14, 32, 33, 88, 145, 163, 164, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep89[] = {
+  9, 88, 179, 180, 249, 
+};
+
+static const short dep90[] = {
+  5, 13, 14, 32, 33, 88, 163, 179, 181, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep91[] = {
+  9, 10, 11, 12, 88, 179, 180, 182, 183, 185, 186, 188, 189, 249, 
+};
+
+static const short dep92[] = {
+  5, 6, 7, 8, 13, 14, 32, 33, 88, 163, 179, 181, 182, 184, 185, 187, 188, 190, 
+  249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep93[] = {
+  10, 88, 182, 183, 249, 
+};
+
+static const short dep94[] = {
+  6, 13, 14, 32, 33, 88, 163, 182, 184, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep95[] = {
+  11, 88, 185, 186, 249, 
+};
+
+static const short dep96[] = {
+  7, 13, 14, 32, 33, 88, 163, 185, 187, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep97[] = {
+  12, 88, 188, 189, 249, 
+};
+
+static const short dep98[] = {
+  8, 13, 14, 32, 33, 88, 163, 188, 190, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep99[] = {
+  9, 88, 179, 180, 249, 2157, 2158, 2159, 2161, 2162, 2311, 2314, 2315, 2318, 
+  2319, 
+};
+
+static const short dep100[] = {
+  5, 13, 14, 32, 33, 88, 163, 179, 181, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  2311, 2314, 2315, 2318, 2319, 4127, 16513, 16515, 
+};
+
+static const short dep101[] = {
+  9, 10, 11, 12, 88, 179, 180, 182, 183, 185, 186, 188, 189, 249, 2157, 2158, 
+  2159, 2161, 2162, 2311, 2314, 2315, 2318, 2319, 
+};
+
+static const short dep102[] = {
+  5, 6, 7, 8, 13, 14, 32, 33, 88, 163, 179, 181, 182, 184, 185, 187, 188, 190, 
+  249, 2126, 2127, 2128, 2157, 2158, 2161, 2311, 2314, 2315, 2318, 2319, 4127, 
+  16513, 16515, 
+};
+
+static const short dep103[] = {
+  10, 88, 182, 183, 249, 2157, 2158, 2159, 2161, 2162, 2311, 2314, 2315, 2318, 
+  2319, 
+};
+
+static const short dep104[] = {
+  6, 13, 14, 32, 33, 88, 163, 182, 184, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  2311, 2314, 2315, 2318, 2319, 4127, 16513, 16515, 
+};
+
+static const short dep105[] = {
+  11, 88, 185, 186, 249, 2157, 2158, 2159, 2161, 2162, 2311, 2314, 2315, 2318, 
+  2319, 
+};
+
+static const short dep106[] = {
+  7, 13, 14, 32, 33, 88, 163, 185, 187, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  2311, 2314, 2315, 2318, 2319, 4127, 16513, 16515, 
+};
+
+static const short dep107[] = {
+  12, 88, 188, 189, 249, 2157, 2158, 2159, 2161, 2162, 2311, 2314, 2315, 2318, 
+  2319, 
+};
+
+static const short dep108[] = {
+  8, 13, 14, 32, 33, 88, 163, 188, 190, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  2311, 2314, 2315, 2318, 2319, 4127, 16513, 16515, 
+};
+
+static const short dep109[] = {
+  9, 88, 179, 180, 249, 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 
+  22798, 22799, 
+};
+
+static const short dep110[] = {
+  5, 13, 14, 32, 33, 88, 163, 179, 181, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  4127, 16513, 16515, 22791, 22794, 22795, 22798, 22799, 
+};
+
+static const short dep111[] = {
+  9, 10, 11, 12, 88, 179, 180, 182, 183, 185, 186, 188, 189, 249, 22637, 22638, 
+  22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799, 
+};
+
+static const short dep112[] = {
+  5, 6, 7, 8, 13, 14, 32, 33, 88, 163, 179, 181, 182, 184, 185, 187, 188, 190, 
+  249, 2126, 2127, 2128, 2157, 2158, 2161, 4127, 16513, 16515, 22791, 22794, 
+  22795, 22798, 22799, 
+};
+
+static const short dep113[] = {
+  10, 88, 182, 183, 249, 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 
+  22798, 22799, 
+};
+
+static const short dep114[] = {
+  6, 13, 14, 32, 33, 88, 163, 182, 184, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  4127, 16513, 16515, 22791, 22794, 22795, 22798, 22799, 
+};
+
+static const short dep115[] = {
+  11, 88, 185, 186, 249, 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 
+  22798, 22799, 
+};
+
+static const short dep116[] = {
+  7, 13, 14, 32, 33, 88, 163, 185, 187, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  4127, 16513, 16515, 22791, 22794, 22795, 22798, 22799, 
+};
+
+static const short dep117[] = {
+  12, 88, 188, 189, 249, 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 
+  22798, 22799, 
+};
+
+static const short dep118[] = {
+  8, 13, 14, 32, 33, 88, 163, 188, 190, 249, 2126, 2127, 2128, 2157, 2158, 2161, 
+  4127, 16513, 16515, 22791, 22794, 22795, 22798, 22799, 
+};
+
+static const short dep119[] = {
+  88, 249, 2157, 2158, 2159, 2161, 2162, 2311, 2314, 2315, 2318, 2319, 
+};
+
+static const short dep120[] = {
+  32, 33, 88, 163, 249, 2126, 2127, 2128, 2157, 2158, 2161, 2311, 2314, 2315, 
+  2318, 2319, 4127, 16513, 16515, 
+};
+
+static const short dep121[] = {
+  88, 249, 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799, 
+  
+};
+
+static const short dep122[] = {
+  32, 33, 88, 163, 249, 2126, 2127, 2128, 2157, 2158, 2161, 4127, 16513, 16515, 
+  22791, 22794, 22795, 22798, 22799, 
+};
+
+static const short dep123[] = {
+  13, 14, 32, 33, 88, 163, 249, 2126, 2127, 2128, 2157, 2158, 2161, 2292, 4127, 
+  16513, 16515, 18724, 18726, 18727, 18729, 
+};
+
+static const short dep124[] = {
+  32, 33, 88, 145, 163, 164, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 
+  20602, 
+};
+
+static const short dep125[] = {
+  88, 249, 2075, 2076, 2253, 2254, 
+};
+
+static const short dep126[] = {
+  32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2252, 2254, 4127, 
+  20602, 
+};
+
+static const short dep127[] = {
+  32, 33, 88, 163, 249, 2074, 2076, 2157, 2158, 2161, 2294, 4127, 20602, 
+};
+
+static const short dep128[] = {
+  88, 249, 14446, 14448, 14449, 14451, 14602, 14603, 14606, 14607, 
+};
+
+static const short dep129[] = {
+  32, 33, 88, 163, 249, 2129, 2130, 2131, 4127, 14602, 14603, 14606, 14607, 
+  20602, 24685, 24686, 24689, 
+};
+
+static const short dep130[] = {
+  88, 110, 112, 113, 115, 249, 14602, 14603, 14606, 14607, 
+};
+
+static const short dep131[] = {
+  32, 33, 88, 163, 249, 4127, 14602, 14603, 14606, 14607, 24685, 24686, 24689, 
+  
+};
+
+static const short dep132[] = {
+  32, 33, 88, 163, 249, 2157, 2158, 2161, 2294, 4127, 20602, 
+};
+
+static const short dep133[] = {
+  32, 33, 88, 110, 113, 163, 249, 2294, 4127, 20602, 24685, 
+};
+
+static const short dep134[] = {
+  4, 17, 19, 20, 88, 174, 195, 198, 249, 2073, 2251, 
+};
+
+static const short dep135[] = {
+  32, 33, 88, 163, 174, 195, 197, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2251, 
+  4127, 20602, 
+};
+
+static const short dep136[] = {
+  4, 17, 18, 19, 32, 33, 88, 163, 249, 2073, 2157, 2158, 2161, 2294, 4127, 20602, 
+  
+};
+
+static const short dep137[] = {
+  0, 32, 33, 88, 145, 163, 164, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep138[] = {
+  0, 88, 170, 249, 
+};
+
+static const short dep139[] = {
+  0, 32, 33, 88, 145, 163, 164, 170, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep140[] = {
+  32, 33, 88, 163, 170, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep141[] = {
+  2, 21, 88, 172, 199, 249, 28841, 28980, 
+};
+
+static const short dep142[] = {
+  1, 2, 21, 22, 88, 157, 158, 163, 172, 199, 249, 28841, 28980, 
+};
+
+static const short dep143[] = {
+  1, 21, 22, 30, 32, 33, 88, 157, 158, 163, 172, 199, 249, 4127, 28841, 28980, 
+  
+};
+
+static const short dep144[] = {
+  0, 32, 33, 88, 163, 170, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep145[] = {
+  1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 21, 22, 23, 88, 171, 172, 
+  173, 175, 176, 177, 178, 180, 181, 183, 184, 186, 187, 189, 190, 191, 192, 
+  193, 199, 200, 201, 249, 2064, 2073, 2242, 2251, 28841, 28980, 
+};
+
+static const short dep146[] = {
+  22, 32, 33, 88, 123, 163, 171, 172, 173, 175, 176, 177, 178, 180, 181, 183, 
+  184, 186, 187, 189, 190, 191, 192, 193, 199, 200, 201, 249, 2129, 2130, 2131, 
+  2157, 2158, 2161, 2242, 2251, 4127, 20602, 28841, 28980, 
+};
+
+static const short dep147[] = {
+  88, 249, 14452, 14454, 14455, 14457, 14486, 14487, 14502, 14608, 14609, 14629, 
+  14630, 14632, 14633, 14642, 
+};
+
+static const short dep148[] = {
+  32, 33, 88, 162, 163, 249, 2157, 2158, 2161, 4127, 14608, 14609, 14629, 14630, 
+  14632, 14633, 14642, 
+};
+
+static const short dep149[] = {
+  14452, 14454, 14455, 14457, 14486, 14487, 14502, 14608, 14609, 14629, 14630, 
+  14632, 14633, 14642, 
+};
+
+static const short dep150[] = {
+  162, 14608, 14609, 14629, 14630, 14632, 14633, 14642, 
+};
+
+static const short dep151[] = {
+  88, 249, 14453, 14454, 14456, 14457, 14465, 14466, 14467, 14468, 14469, 14470, 
+  14471, 14472, 14474, 14477, 14478, 14486, 14487, 14488, 14489, 14490, 14495, 
+  14496, 14497, 14498, 14502, 14608, 14609, 14615, 14616, 14617, 14618, 14620, 
+  14622, 14629, 14630, 14632, 14633, 14634, 14635, 14638, 14639, 14642, 
+};
+
+static const short dep152[] = {
+  32, 33, 64, 88, 123, 163, 249, 2157, 2158, 2161, 4127, 14608, 14609, 14615, 
+  14616, 14617, 14618, 14620, 14622, 14629, 14630, 14632, 14633, 14634, 14635, 
+  14638, 14639, 14642, 
+};
+
+static const short dep153[] = {
+  1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 21, 22, 23, 32, 33, 88, 123, 
+  160, 163, 249, 2064, 2073, 2157, 2158, 2161, 2294, 4127, 20602, 28841, 
+};
+
+static const short dep154[] = {
+  35, 36, 37, 38, 39, 40, 41, 42, 44, 45, 46, 47, 48, 49, 50, 52, 53, 54, 55, 
+  56, 57, 59, 61, 62, 63, 64, 85, 87, 88, 210, 211, 212, 213, 214, 215, 216, 
+  217, 218, 219, 220, 222, 223, 224, 225, 226, 228, 230, 231, 232, 248, 249, 
+  2108, 2277, 
+};
+
+static const short dep155[] = {
+  32, 33, 87, 88, 123, 142, 163, 210, 211, 212, 213, 214, 215, 216, 217, 218, 
+  219, 220, 222, 223, 224, 225, 226, 228, 230, 231, 232, 248, 249, 2129, 2130, 
+  2131, 2157, 2158, 2161, 2277, 4127, 20602, 
+};
+
+static const short dep156[] = {
+  51, 86, 88, 221, 248, 249, 2131, 2294, 
+};
+
+static const short dep157[] = {
+  32, 33, 35, 36, 38, 40, 41, 43, 44, 45, 46, 48, 49, 52, 53, 55, 56, 57, 58, 
+  59, 61, 62, 63, 85, 86, 88, 123, 142, 163, 221, 248, 249, 2099, 2108, 2157, 
+  2158, 2161, 2294, 4127, 20602, 
+};
+
+static const short dep158[] = {
+  2, 21, 33, 88, 172, 199, 208, 249, 2131, 2294, 28841, 28980, 
+};
+
+static const short dep159[] = {
+  2, 18, 19, 21, 22, 30, 32, 33, 88, 157, 158, 163, 172, 199, 208, 249, 2294, 
+  4127, 20602, 28841, 28980, 
+};
+
+static const short dep160[] = {
+  88, 117, 118, 120, 121, 125, 126, 129, 130, 131, 132, 133, 134, 135, 136, 
+  138, 141, 142, 146, 147, 150, 151, 152, 153, 154, 156, 157, 159, 160, 161, 
+  162, 164, 165, 166, 249, 272, 273, 277, 279, 280, 281, 282, 284, 286, 290, 
+  293, 294, 296, 297, 298, 299, 301, 302, 303, 305, 306, 
+};
+
+static const short dep161[] = {
+  32, 33, 64, 88, 123, 163, 249, 272, 273, 277, 279, 280, 281, 282, 284, 286, 
+  290, 293, 294, 296, 297, 298, 299, 301, 302, 303, 305, 306, 2129, 2130, 2131, 
+  2157, 2158, 2161, 4127, 20602, 
+};
+
+static const short dep162[] = {
+  88, 116, 118, 119, 121, 150, 151, 166, 249, 272, 273, 293, 294, 296, 297, 
+  306, 
+};
+
+static const short dep163[] = {
+  32, 33, 88, 162, 163, 249, 272, 273, 293, 294, 296, 297, 306, 2129, 2130, 
+  2131, 2157, 2158, 2161, 4127, 20602, 
+};
+
+static const short dep164[] = {
+  32, 33, 88, 118, 121, 123, 126, 127, 130, 132, 134, 136, 138, 139, 141, 145, 
+  146, 148, 149, 150, 151, 153, 154, 156, 158, 159, 161, 163, 165, 166, 249, 
+  2157, 2158, 2161, 2294, 4127, 20602, 
+};
+
+static const short dep165[] = {
+  32, 33, 88, 118, 121, 150, 151, 163, 166, 249, 2157, 2158, 2161, 2294, 4127, 
+  20602, 
+};
+
+static const short dep166[] = {
+  32, 33, 67, 68, 73, 75, 88, 102, 123, 152, 163, 167, 249, 2129, 2130, 2131, 
+  2157, 2158, 2161, 2294, 4127, 20602, 
+};
+
+static const short dep167[] = {
+  32, 33, 67, 68, 73, 75, 88, 102, 123, 124, 125, 127, 128, 152, 163, 167, 249, 
+  2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, 
+};
+
+static const short dep168[] = {
+  68, 69, 88, 92, 93, 236, 237, 249, 251, 252, 
+};
+
+static const short dep169[] = {
+  32, 33, 39, 54, 69, 71, 77, 88, 90, 93, 123, 142, 163, 167, 236, 237, 249, 
+  251, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, 
+};
+
+static const short dep170[] = {
+  32, 33, 39, 54, 69, 71, 88, 90, 93, 95, 97, 123, 142, 163, 167, 236, 237, 
+  249, 251, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, 
+};
+
+static const short dep171[] = {
+  88, 249, 12455, 12456, 12595, 
+};
+
+static const short dep172[] = {
+  32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 12595, 
+  20602, 
+};
+
+static const short dep173[] = {
+  88, 249, 6210, 6211, 6378, 
+};
+
+static const short dep174[] = {
+  32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 6378, 
+  20602, 
+};
+
+static const short dep175[] = {
+  88, 249, 6228, 6391, 
+};
+
+static const short dep176[] = {
+  32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 6391, 
+  20602, 
+};
+
+static const short dep177[] = {
+  88, 249, 6246, 6247, 6248, 6249, 6402, 6404, 8451, 
+};
+
+static const short dep178[] = {
+  32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 6249, 
+  6403, 6404, 8295, 8450, 20602, 
+};
+
+static const short dep179[] = {
+  88, 249, 6250, 6251, 6405, 
+};
+
+static const short dep180[] = {
+  32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 6405, 
+  20602, 
+};
+
+static const short dep181[] = {
+  88, 249, 6252, 6406, 
+};
+
+static const short dep182[] = {
+  32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 6406, 
+  20602, 
+};
+
+static const short dep183[] = {
+  88, 249, 10341, 10497, 
+};
+
+static const short dep184[] = {
+  32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 10497, 
+  20602, 
+};
+
+static const short dep185[] = {
+  68, 69, 73, 74, 88, 92, 93, 236, 237, 239, 240, 249, 251, 252, 
+};
+
+static const short dep186[] = {
+  32, 33, 39, 69, 71, 74, 77, 88, 90, 93, 123, 142, 163, 167, 236, 237, 239, 
+  241, 249, 251, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, 
+};
+
+static const short dep187[] = {
+  68, 69, 88, 92, 93, 95, 96, 236, 237, 249, 251, 252, 253, 254, 
+};
+
+static const short dep188[] = {
+  32, 33, 39, 54, 69, 71, 88, 90, 93, 95, 97, 123, 142, 163, 167, 236, 237, 
+  249, 251, 252, 253, 254, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, 
+  
+};
+
+static const short dep189[] = {
+  32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, 
+  12456, 20602, 
+};
+
+static const short dep190[] = {
+  32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, 
+  6210, 20602, 
+};
+
+static const short dep191[] = {
+  32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, 
+  6228, 20602, 
+};
+
+static const short dep192[] = {
+  32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, 
+  6248, 8294, 20602, 
+};
+
+static const short dep193[] = {
+  32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, 
+  6250, 20602, 
+};
+
+static const short dep194[] = {
+  32, 33, 88, 123, 162, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 
+  4127, 6251, 6252, 20602, 
+};
+
+static const short dep195[] = {
+  32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, 
+  10341, 20602, 
+};
+
+static const short dep196[] = {
+  32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, 6178, 
+  20602, 
+};
+
+static const short dep197[] = {
+  68, 70, 71, 88, 89, 90, 91, 235, 236, 249, 250, 251, 
+};
+
+static const short dep198[] = {
+  32, 33, 69, 70, 74, 76, 88, 91, 93, 95, 98, 123, 163, 167, 235, 237, 249, 
+  250, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, 
+};
+
+static const short dep199[] = {
+  68, 70, 71, 72, 88, 89, 90, 91, 94, 235, 236, 238, 249, 250, 251, 
+};
+
+static const short dep200[] = {
+  32, 33, 69, 70, 72, 74, 76, 88, 91, 93, 94, 95, 98, 123, 163, 167, 235, 237, 
+  238, 249, 250, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, 
+};
+
+static const short dep201[] = {
+  68, 70, 71, 75, 76, 77, 88, 89, 90, 91, 235, 236, 241, 242, 249, 250, 251, 
+  
+};
+
+static const short dep202[] = {
+  32, 33, 69, 70, 74, 76, 88, 91, 93, 123, 163, 167, 235, 237, 240, 242, 249, 
+  250, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, 
+};
+
+static const short dep203[] = {
+  68, 70, 71, 88, 89, 90, 91, 97, 98, 99, 235, 236, 249, 250, 251, 254, 255, 
+  
+};
+
+static const short dep204[] = {
+  32, 33, 69, 70, 88, 91, 93, 95, 98, 123, 163, 167, 235, 237, 249, 250, 252, 
+  253, 255, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, 
+};
+
+static const short dep205[] = {
+  32, 33, 38, 62, 88, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 
+  4127, 20602, 
+};
+
+static const short dep206[] = {
+  32, 33, 88, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, 
+  20602, 
+};
+
+static const short dep207[] = {
+  32, 33, 68, 73, 75, 88, 123, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 
+  2161, 2294, 4127, 20602, 
+};
+
+static const short dep208[] = {
+  32, 33, 88, 145, 163, 164, 249, 2126, 2127, 2128, 2129, 2130, 2131, 2157, 
+  2158, 2161, 4127, 16513, 16515, 20602, 
+};
+
+static const short dep209[] = {
+  32, 33, 68, 73, 75, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 
+  20602, 
+};
+
+static const short dep210[] = {
+  32, 33, 69, 70, 88, 91, 123, 163, 235, 237, 249, 250, 252, 2129, 2130, 2131, 
+  2157, 2158, 2161, 4127, 20602, 
+};
+
+static const short dep211[] = {
+  32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, 127, 
+  128, 135, 152, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, 
+  20602, 
+};
+
+static const short dep212[] = {
+  32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, 
+  127, 128, 135, 137, 152, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 
+  2294, 4127, 20602, 
+};
+
+static const short dep213[] = {
+  0, 88, 170, 249, 2131, 2294, 
+};
+
+static const short dep214[] = {
+  0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, 
+  127, 128, 135, 152, 163, 167, 170, 249, 2129, 2130, 2131, 2157, 2158, 2161, 
+  2294, 4127, 20602, 
+};
+
+static const short dep215[] = {
+  0, 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 
+  125, 127, 128, 135, 137, 152, 163, 167, 170, 249, 2129, 2130, 2131, 2157, 
+  2158, 2161, 2294, 4127, 20602, 
+};
+
+static const short dep216[] = {
+  23, 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, 
+  127, 128, 135, 152, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 
+  4127, 20602, 
+};
+
+static const short dep217[] = {
+  0, 88, 170, 249, 2294, 26706, 
+};
+
+static const short dep218[] = {
+  0, 88, 100, 170, 249, 256, 
+};
+
+static const short dep219[] = {
+  0, 32, 33, 67, 68, 73, 75, 88, 102, 116, 117, 119, 120, 123, 124, 125, 127, 
+  128, 135, 152, 163, 167, 170, 249, 256, 2129, 2130, 2131, 2157, 2158, 2161, 
+  4127, 20602, 
+};
+
+static const short dep220[] = {
+  0, 23, 88, 100, 170, 201, 249, 256, 
+};
+
+static const short dep221[] = {
+  0, 32, 33, 67, 68, 73, 75, 88, 102, 116, 117, 119, 120, 123, 124, 125, 127, 
+  128, 135, 152, 163, 167, 170, 201, 249, 256, 2129, 2130, 2131, 2157, 2158, 
+  2161, 4127, 20602, 
+};
+
+static const short dep222[] = {
+  0, 88, 100, 170, 249, 256, 2131, 2294, 
+};
+
+static const short dep223[] = {
+  0, 3, 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 
+  125, 127, 128, 135, 152, 163, 167, 170, 249, 256, 2129, 2130, 2131, 2157, 
+  2158, 2161, 2294, 4127, 20602, 
+};
+
+static const short dep224[] = {
+  0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, 
+  127, 128, 135, 152, 163, 167, 170, 249, 256, 2129, 2130, 2131, 2157, 2158, 
+  2161, 2294, 4127, 20602, 
+};
+
+static const short dep225[] = {
+  32, 33, 88, 163, 249, 2126, 2127, 2128, 2157, 2158, 2161, 2294, 4127, 16513, 
+  16515, 20602, 
+};
+
+static const short dep226[] = {
+  32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, 127, 
+  128, 135, 152, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2292, 4127, 
+  16513, 16515, 18724, 18726, 18727, 18729, 20602, 
+};
+
+static const short dep227[] = {
+  32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, 
+  127, 128, 135, 137, 152, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 
+  2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 20602, 
+};
+
+static const short dep228[] = {
+  0, 88, 170, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, 
+};
+
+static const short dep229[] = {
+  0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, 
+  127, 128, 135, 152, 163, 167, 170, 249, 2129, 2130, 2131, 2157, 2158, 2161, 
+  2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 20602, 
+};
+
+static const short dep230[] = {
+  0, 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 
+  125, 127, 128, 135, 137, 152, 163, 167, 170, 249, 2129, 2130, 2131, 2157, 
+  2158, 2161, 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 20602, 
+};
+
+static const short dep231[] = {
+  0, 88, 170, 249, 2128, 2292, 18582, 18583, 18724, 18725, 18727, 18728, 
+};
+
+static const short dep232[] = {
+  32, 33, 67, 88, 123, 137, 163, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep233[] = {
+  32, 33, 67, 88, 123, 124, 128, 137, 163, 249, 2157, 2158, 2161, 4127, 
+};
+
+static const short dep234[] = {
+  32, 33, 67, 88, 123, 137, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 
+  4127, 20602, 
+};
+
+static const short dep235[] = {
+  32, 33, 67, 88, 123, 124, 128, 137, 163, 249, 2129, 2130, 2131, 2157, 2158, 
+  2161, 2294, 4127, 20602, 
+};
+
+static const short dep236[] = {
+  32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, 
+};
+
+static const short dep237[] = {
+  32, 33, 88, 163, 249, 2157, 2158, 2159, 2160, 2161, 2162, 2163, 4127, 
+};
+
+static const short dep238[] = {
+  1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 19, 20, 21, 22, 23, 
+  88, 171, 172, 173, 174, 175, 176, 177, 178, 180, 181, 183, 184, 186, 187, 
+  189, 190, 191, 192, 193, 195, 198, 199, 200, 201, 249, 2064, 2073, 2131, 2242, 
+  2251, 2294, 28841, 28980, 
+};
+
+static const short dep239[] = {
+  1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23, 
+  32, 33, 88, 123, 160, 163, 171, 172, 173, 174, 175, 176, 177, 178, 180, 181, 
+  183, 184, 186, 187, 189, 190, 191, 192, 193, 195, 197, 199, 200, 201, 249, 
+  2064, 2073, 2129, 2130, 2131, 2157, 2158, 2161, 2242, 2251, 2294, 4127, 20602, 
+  28841, 28980, 
+};
+
+#define NELS(X) (sizeof(X)/sizeof(X[0]))
+static const struct ia64_opcode_dependency
+op_dependencies[] = {
+  { NELS(dep1), dep1, NELS(dep0), dep0, },
+  { NELS(dep3), dep3, NELS(dep2), dep2, },
+  { NELS(dep4), dep4, NELS(dep0), dep0, },
+  { NELS(dep6), dep6, NELS(dep5), dep5, },
+  { NELS(dep8), dep8, NELS(dep7), dep7, },
+  { NELS(dep10), dep10, NELS(dep9), dep9, },
+  { NELS(dep12), dep12, NELS(dep11), dep11, },
+  { NELS(dep14), dep14, NELS(dep13), dep13, },
+  { NELS(dep16), dep16, NELS(dep15), dep15, },
+  { NELS(dep18), dep18, NELS(dep17), dep17, },
+  { NELS(dep20), dep20, NELS(dep19), dep19, },
+  { NELS(dep22), dep22, NELS(dep21), dep21, },
+  { NELS(dep24), dep24, NELS(dep23), dep23, },
+  { NELS(dep26), dep26, NELS(dep25), dep25, },
+  { NELS(dep28), dep28, NELS(dep27), dep27, },
+  { NELS(dep30), dep30, NELS(dep29), dep29, },
+  { NELS(dep31), dep31, NELS(dep15), dep15, },
+  { NELS(dep33), dep33, NELS(dep32), dep32, },
+  { NELS(dep35), dep35, NELS(dep34), dep34, },
+  { NELS(dep36), dep36, NELS(dep15), dep15, },
+  { NELS(dep38), dep38, NELS(dep37), dep37, },
+  { NELS(dep40), dep40, NELS(dep39), dep39, },
+  { NELS(dep42), dep42, NELS(dep41), dep41, },
+  { NELS(dep43), dep43, NELS(dep32), dep32, },
+  { NELS(dep44), dep44, NELS(dep34), dep34, },
+  { NELS(dep46), dep46, NELS(dep45), dep45, },
+  { NELS(dep48), dep48, NELS(dep47), dep47, },
+  { NELS(dep50), dep50, NELS(dep49), dep49, },
+  { NELS(dep52), dep52, NELS(dep51), dep51, },
+  { NELS(dep54), dep54, NELS(dep53), dep53, },
+  { NELS(dep56), dep56, NELS(dep55), dep55, },
+  { NELS(dep58), dep58, NELS(dep57), dep57, },
+  { NELS(dep60), dep60, NELS(dep59), dep59, },
+  { NELS(dep62), dep62, NELS(dep61), dep61, },
+  { NELS(dep64), dep64, NELS(dep63), dep63, },
+  { NELS(dep66), dep66, NELS(dep65), dep65, },
+  { NELS(dep68), dep68, NELS(dep67), dep67, },
+  { NELS(dep69), dep69, NELS(dep34), dep34, },
+  { NELS(dep71), dep71, NELS(dep70), dep70, },
+  { NELS(dep73), dep73, NELS(dep72), dep72, },
+  { NELS(dep75), dep75, NELS(dep74), dep74, },
+  { NELS(dep77), dep77, NELS(dep76), dep76, },
+  { NELS(dep78), dep78, NELS(dep34), dep34, },
+  { NELS(dep80), dep80, NELS(dep79), dep79, },
+  { NELS(dep82), dep82, NELS(dep81), dep81, },
+  { NELS(dep84), dep84, NELS(dep83), dep83, },
+  { NELS(dep85), dep85, NELS(dep34), dep34, },
+  { NELS(dep86), dep86, NELS(dep34), dep34, },
+  { NELS(dep87), dep87, NELS(dep34), dep34, },
+  { NELS(dep88), dep88, NELS(dep34), dep34, },
+  { NELS(dep90), dep90, NELS(dep89), dep89, },
+  { NELS(dep92), dep92, NELS(dep91), dep91, },
+  { NELS(dep94), dep94, NELS(dep93), dep93, },
+  { NELS(dep96), dep96, NELS(dep95), dep95, },
+  { NELS(dep98), dep98, NELS(dep97), dep97, },
+  { NELS(dep100), dep100, NELS(dep99), dep99, },
+  { NELS(dep102), dep102, NELS(dep101), dep101, },
+  { NELS(dep104), dep104, NELS(dep103), dep103, },
+  { NELS(dep106), dep106, NELS(dep105), dep105, },
+  { NELS(dep108), dep108, NELS(dep107), dep107, },
+  { NELS(dep110), dep110, NELS(dep109), dep109, },
+  { NELS(dep112), dep112, NELS(dep111), dep111, },
+  { NELS(dep114), dep114, NELS(dep113), dep113, },
+  { NELS(dep116), dep116, NELS(dep115), dep115, },
+  { NELS(dep118), dep118, NELS(dep117), dep117, },
+  { NELS(dep120), dep120, NELS(dep119), dep119, },
+  { NELS(dep122), dep122, NELS(dep121), dep121, },
+  { NELS(dep123), dep123, NELS(dep65), dep65, },
+  { NELS(dep124), dep124, NELS(dep34), dep34, },
+  { NELS(dep126), dep126, NELS(dep125), dep125, },
+  { NELS(dep127), dep127, NELS(dep0), dep0, },
+  { NELS(dep129), dep129, NELS(dep128), dep128, },
+  { NELS(dep131), dep131, NELS(dep130), dep130, },
+  { NELS(dep132), dep132, NELS(dep0), dep0, },
+  { NELS(dep133), dep133, NELS(dep0), dep0, },
+  { NELS(dep135), dep135, NELS(dep134), dep134, },
+  { NELS(dep136), dep136, NELS(dep0), dep0, },
+  { NELS(dep137), dep137, NELS(dep34), dep34, },
+  { NELS(dep139), dep139, NELS(dep138), dep138, },
+  { NELS(dep140), dep140, NELS(dep138), dep138, },
+  { NELS(dep142), dep142, NELS(dep141), dep141, },
+  { NELS(dep143), dep143, NELS(dep141), dep141, },
+  { NELS(dep144), dep144, NELS(dep138), dep138, },
+  { NELS(dep146), dep146, NELS(dep145), dep145, },
+  { NELS(dep148), dep148, NELS(dep147), dep147, },
+  { NELS(dep150), dep150, NELS(dep149), dep149, },
+  { NELS(dep152), dep152, NELS(dep151), dep151, },
+  { NELS(dep153), dep153, NELS(dep0), dep0, },
+  { NELS(dep155), dep155, NELS(dep154), dep154, },
+  { NELS(dep157), dep157, NELS(dep156), dep156, },
+  { NELS(dep159), dep159, NELS(dep158), dep158, },
+  { NELS(dep161), dep161, NELS(dep160), dep160, },
+  { NELS(dep163), dep163, NELS(dep162), dep162, },
+  { NELS(dep164), dep164, NELS(dep0), dep0, },
+  { NELS(dep165), dep165, NELS(dep0), dep0, },
+  { NELS(dep166), dep166, NELS(dep0), dep0, },
+  { NELS(dep167), dep167, NELS(dep34), dep34, },
+  { NELS(dep169), dep169, NELS(dep168), dep168, },
+  { NELS(dep170), dep170, NELS(dep168), dep168, },
+  { NELS(dep172), dep172, NELS(dep171), dep171, },
+  { NELS(dep174), dep174, NELS(dep173), dep173, },
+  { NELS(dep176), dep176, NELS(dep175), dep175, },
+  { NELS(dep178), dep178, NELS(dep177), dep177, },
+  { NELS(dep180), dep180, NELS(dep179), dep179, },
+  { NELS(dep182), dep182, NELS(dep181), dep181, },
+  { NELS(dep184), dep184, NELS(dep183), dep183, },
+  { NELS(dep186), dep186, NELS(dep185), dep185, },
+  { NELS(dep188), dep188, NELS(dep187), dep187, },
+  { NELS(dep189), dep189, NELS(dep0), dep0, },
+  { NELS(dep190), dep190, NELS(dep0), dep0, },
+  { NELS(dep191), dep191, NELS(dep0), dep0, },
+  { NELS(dep192), dep192, NELS(dep0), dep0, },
+  { NELS(dep193), dep193, NELS(dep0), dep0, },
+  { NELS(dep194), dep194, NELS(dep0), dep0, },
+  { NELS(dep195), dep195, NELS(dep0), dep0, },
+  { NELS(dep196), dep196, NELS(dep0), dep0, },
+  { NELS(dep198), dep198, NELS(dep197), dep197, },
+  { NELS(dep200), dep200, NELS(dep199), dep199, },
+  { NELS(dep202), dep202, NELS(dep201), dep201, },
+  { NELS(dep204), dep204, NELS(dep203), dep203, },
+  { NELS(dep205), dep205, NELS(dep0), dep0, },
+  { NELS(dep206), dep206, NELS(dep0), dep0, },
+  { NELS(dep207), dep207, NELS(dep0), dep0, },
+  { NELS(dep208), dep208, NELS(dep34), dep34, },
+  { NELS(dep209), dep209, NELS(dep34), dep34, },
+  { NELS(dep210), dep210, NELS(dep197), dep197, },
+  { NELS(dep211), dep211, NELS(dep0), dep0, },
+  { NELS(dep212), dep212, NELS(dep0), dep0, },
+  { NELS(dep214), dep214, NELS(dep213), dep213, },
+  { NELS(dep215), dep215, NELS(dep213), dep213, },
+  { NELS(dep216), dep216, NELS(dep0), dep0, },
+  { NELS(dep214), dep214, NELS(dep217), dep217, },
+  { NELS(dep219), dep219, NELS(dep218), dep218, },
+  { NELS(dep221), dep221, NELS(dep220), dep220, },
+  { NELS(dep223), dep223, NELS(dep222), dep222, },
+  { NELS(dep224), dep224, NELS(dep222), dep222, },
+  { NELS(dep225), dep225, NELS(dep0), dep0, },
+  { NELS(dep226), dep226, NELS(dep65), dep65, },
+  { NELS(dep227), dep227, NELS(dep65), dep65, },
+  { NELS(dep229), dep229, NELS(dep228), dep228, },
+  { NELS(dep230), dep230, NELS(dep228), dep228, },
+  { NELS(dep229), dep229, NELS(dep231), dep231, },
+  { NELS(dep232), dep232, NELS(dep34), dep34, },
+  { NELS(dep233), dep233, NELS(dep34), dep34, },
+  { NELS(dep234), dep234, NELS(dep0), dep0, },
+  { NELS(dep235), dep235, NELS(dep0), dep0, },
+  { NELS(dep236), dep236, NELS(dep34), dep34, },
+  { NELS(dep237), dep237, NELS(dep15), dep15, },
+  { NELS(dep239), dep239, NELS(dep238), dep238, },
+};
+
+static const struct ia64_completer_table
+completer_table[] = {
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 0 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 1 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 90 },
+  { 0x0, 0x0, 0, 123, -1, 0, 1, 8 },
+  { 0x0, 0x0, 0, 128, -1, 0, 1, 19 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 147 },
+  { 0x0, 0x0, 0, 502, -1, 0, 1, 12 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 11 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 73 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 15 },
+  { 0x1, 0x1, 0, 716, -1, 13, 1, 0 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 35 },
+  { 0x0, 0x0, 0, 142, -1, 0, 1, 31 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 31 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 124 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 46 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 42 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 80 },
+  { 0x0, 0x0, 0, 144, -1, 0, 1, 31 },
+  { 0x0, 0x0, 0, 146, -1, 0, 1, 31 },
+  { 0x0, 0x0, 0, 533, -1, 0, 1, 31 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 26 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 37 },
+  { 0x0, 0x0, 0, 419, -1, 0, 1, 35 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 79 },
+  { 0x0, 0x0, 0, 78, -1, 0, 1, 126 },
+  { 0x0, 0x0, 0, 79, -1, 0, 1, 126 },
+  { 0x0, 0x0, 0, 80, -1, 0, 1, 137 },
+  { 0x0, 0x0, 0, 218, -1, 0, 1, 142 },
+  { 0x0, 0x0, 0, 220, -1, 0, 1, 144 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 81 },
+  { 0x0, 0x0, 0, 81, -1, 0, 1, 42 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 2 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 69 },
+  { 0x1, 0x1, 0, 205, -1, 20, 1, 69 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 70 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 71 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 72 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 74 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 88 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 89 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 91 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 92 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 93 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 94 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 99 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 100 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 101 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 102 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 103 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 104 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 105 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 108 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 109 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 110 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 111 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 112 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 113 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 114 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 115 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 148 },
+  { 0x0, 0x0, 0, 712, -1, 0, 1, 0 },
+  { 0x0, 0x0, 0, 509, -1, 0, 1, 0 },
+  { 0x0, 0x0, 0, 717, -1, 0, 1, 0 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 13 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 86 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 85 },
+  { 0x0, 0x0, 0, 474, -1, 0, 1, 132 },
+  { 0x0, 0x0, 0, 476, -1, 0, 1, 132 },
+  { 0x0, 0x0, 0, 473, -1, 0, 1, 132 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 84 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 122 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 120 },
+  { 0x0, 0x0, 0, -1, -1, 0, 1, 121 },
+  { 0x0, 0x0, 0, 432, -1, 0, 1, 135 },
+  { 0x0, 0x0, 1, 76, -1, 0, 1, 14 },
+  { 0x1, 0x1, 2, -1, -1, 27, 1, 14 },
+  { 0x0, 0x0, 3, -1, 133, 0, 0, -1 },
+  { 0x1, 0x1, 3, 85, 433, 33, 1, 128 },
+  { 0x1, 0x1, 3, 86, 433, 33, 1, 128 },
+  { 0x1, 0x1, 3, 113, 441, 33, 1, 139 },
+  { 0x1, 0x1, 3, -1, -1, 27, 1, 42 },
+  { 0x0, 0x0, 4, 510, 431, 0, 1, 134 },
+  { 0x0, 0x0, 4, 511, 432, 0, 1, 135 },
+  { 0x1, 0x1, 4, 435, 435, 33, 1, 131 },
+  { 0x5, 0x5, 4, 109, 434, 32, 1, 126 },
+  { 0x5, 0x5, 4, 110, 434, 32, 1, 126 },
+  { 0x1, 0x21, 10, 479, -1, 33, 1, 5 },
+  { 0x200001, 0x200001, 10, 480, -1, 12, 1, 5 },
+  { 0x1, 0x1, 10, 481, -1, 33, 1, 5 },
+  { 0x0, 0x0, 10, 482, -1, 0, 1, 5 },
+  { 0x1, 0x1, 10, 483, -1, 12, 1, 5 },
+  { 0x0, 0x0, 10, -1, 490, 0, 0, -1 },
+  { 0x0, 0x0, 10, -1, 491, 0, 0, -1 },
+  { 0x0, 0x0, 10, -1, 492, 0, 0, -1 },
+  { 0x0, 0x0, 10, -1, 493, 0, 0, -1 },
+  { 0x1000001, 0x1000001, 10, 484, -1, 12, 1, 5 },
+  { 0x1, 0x1, 10, 485, -1, 36, 1, 5 },
+  { 0x0, 0x0, 10, 106, 494, 0, 0, -1 },
+  { 0x0, 0x0, 10, 107, 496, 0, 0, -1 },
+  { 0x2, 0x3, 11, -1, -1, 37, 1, 7 },
+  { 0x1, 0x1, 11, 486, -1, 12, 1, 5 },
+  { 0x0, 0x0, 11, 487, -1, 0, 1, 5 },
+  { 0x200001, 0x200001, 11, 488, -1, 12, 1, 5 },
+  { 0x1, 0x1, 11, 489, -1, 33, 1, 5 },
+  { 0x1, 0x1, 11, -1, -1, 36, 1, 7 },
+  { 0x1, 0x1, 11, 495, -1, 36, 1, 5 },
+  { 0x1000001, 0x1000001, 11, 497, -1, 12, 1, 5 },
+  { 0x0, 0x0, 12, -1, -1, 0, 1, 16 },
+  { 0x1, 0x1, 13, 111, 434, 34, 1, 126 },
+  { 0x1, 0x1, 13, 112, 434, 34, 1, 126 },
+  { 0x0, 0x0, 19, 438, 134, 0, 0, -1 },
+  { 0x0, 0x0, 19, 274, 134, 0, 0, -1 },
+  { 0x0, 0x0, 19, 445, 135, 0, 0, -1 },
+  { 0x0, 0x0, 20, -1, 161, 0, 0, -1 },
+  { 0x0, 0x0, 20, -1, 162, 0, 0, -1 },
+  { 0x0, 0x0, 20, -1, 175, 0, 0, -1 },
+  { 0x0, 0x0, 20, -1, 176, 0, 0, -1 },
+  { 0x0, 0x0, 21, 140, 171, 0, 0, -1 },
+  { 0x0, 0x0, 21, 141, 173, 0, 0, -1 },
+  { 0x0, 0x0, 23, -1, 169, 0, 0, -1 },
+  { 0x0, 0x0, 23, -1, 170, 0, 0, -1 },
+  { 0x1, 0x1, 24, -1, -1, 35, 1, 8 },
+  { 0x1, 0x1, 24, 230, -1, 35, 1, 8 },
+  { 0x1, 0x1, 24, -1, -1, 35, 1, 9 },
+  { 0x1, 0x1, 24, -1, -1, 35, 1, 10 },
+  { 0x1, 0x1, 24, -1, -1, 35, 1, 17 },
+  { 0x1, 0x1, 24, -1, -1, 35, 1, 19 },
+  { 0x1, 0x1, 24, 246, -1, 35, 1, 19 },
+  { 0x1, 0x1, 24, -1, -1, 35, 1, 20 },
+  { 0x1, 0x1, 24, -1, -1, 35, 1, 21 },
+  { 0x1, 0x1, 24, -1, -1, 35, 1, 22 },
+  { 0x1, 0x1, 24, -1, -1, 35, 1, 23 },
+  { 0x1, 0x1, 24, 404, -1, 33, 1, 78 },
+  { 0x1, 0x1, 24, 405, 84, 35, 1, 131 },
+  { 0x1, 0x1, 24, 406, 442, 35, 1, 141 },
+  { 0x0, 0x0, 32, 155, 153, 0, 0, -1 },
+  { 0x0, 0x0, 32, 158, 156, 0, 0, -1 },
+  { 0x0, 0x0, 32, 163, 163, 0, 0, -1 },
+  { 0x0, 0x0, 32, 164, 164, 0, 0, -1 },
+  { 0x0, 0x0, 34, -1, 172, 0, 0, -1 },
+  { 0x0, 0x0, 34, -1, 174, 0, 0, -1 },
+  { 0x1, 0x1, 37, 523, 533, 37, 1, 31 },
+  { 0x0, 0x0, 37, 524, 551, 0, 0, -1 },
+  { 0x1, 0x1, 37, 525, -1, 37, 1, 31 },
+  { 0x0, 0x0, 37, 527, 551, 0, 0, -1 },
+  { 0x1, 0x1, 37, 528, -1, 37, 1, 31 },
+  { 0x3, 0x3, 37, 222, -1, 30, 1, 136 },
+  { 0x0, 0x0, 37, 308, -1, 0, 1, 97 },
+  { 0x0, 0x0, 37, -1, -1, 0, 1, 106 },
+  { 0x0, 0x0, 37, 312, -1, 0, 1, 118 },
+  { 0x3, 0x3, 37, 223, -1, 30, 1, 146 },
+  { 0x0, 0x0, 37, 313, -1, 0, 1, 42 },
+  { 0x0, 0x0, 39, 177, 231, 0, 0, -1 },
+  { 0x0, 0x0, 39, 178, 234, 0, 0, -1 },
+  { 0x0, 0x0, 39, 179, 231, 0, 0, -1 },
+  { 0x3, 0x3, 39, 180, 122, 33, 1, 8 },
+  { 0x18000001, 0x18000001, 39, 181, 124, 6, 1, 9 },
+  { 0x3, 0x3, 39, 182, 122, 33, 1, 8 },
+  { 0x0, 0x0, 39, 183, 238, 0, 0, -1 },
+  { 0x3, 0x3, 39, 184, 125, 33, 1, 10 },
+  { 0x0, 0x0, 39, 185, 242, 0, 0, -1 },
+  { 0x3, 0x3, 39, 186, 126, 33, 1, 17 },
+  { 0x0, 0x0, 39, 187, 247, 0, 0, -1 },
+  { 0x3, 0x3, 39, 188, 127, 33, 1, 19 },
+  { 0x0, 0x0, 39, 189, 250, 0, 0, -1 },
+  { 0x0, 0x0, 39, 190, 254, 0, 0, -1 },
+  { 0x3, 0x3, 39, 191, 129, 33, 1, 20 },
+  { 0x18000001, 0x18000001, 39, 192, 129, 6, 1, 20 },
+  { 0x0, 0x0, 39, 193, 258, 0, 0, -1 },
+  { 0x3, 0x3, 39, 194, 130, 33, 1, 21 },
+  { 0x0, 0x0, 39, 195, 262, 0, 0, -1 },
+  { 0x0, 0x0, 39, 196, 266, 0, 0, -1 },
+  { 0x3, 0x3, 39, 197, 131, 33, 1, 22 },
+  { 0x18000001, 0x18000001, 39, 198, 131, 6, 1, 22 },
+  { 0x0, 0x0, 39, 199, 270, 0, 0, -1 },
+  { 0x3, 0x3, 39, 200, 132, 33, 1, 23 },
+  { 0x0, 0x0, 40, 661, 232, 0, 0, -1 },
+  { 0x0, 0x0, 40, 662, 235, 0, 0, -1 },
+  { 0x0, 0x0, 40, 314, 232, 0, 0, -1 },
+  { 0x1, 0x1, 40, 663, 122, 34, 1, 8 },
+  { 0x10000001, 0x10000001, 40, 664, 124, 6, 1, 9 },
+  { 0x1, 0x1, 40, 315, 122, 34, 1, 8 },
+  { 0x0, 0x0, 40, 665, 239, 0, 0, -1 },
+  { 0x1, 0x1, 40, 666, 125, 34, 1, 10 },
+  { 0x0, 0x0, 40, 667, 243, 0, 0, -1 },
+  { 0x1, 0x1, 40, 668, 126, 34, 1, 17 },
+  { 0x0, 0x0, 40, 669, 248, 0, 0, -1 },
+  { 0x1, 0x1, 40, 670, 127, 34, 1, 19 },
+  { 0x0, 0x0, 40, 671, 251, 0, 0, -1 },
+  { 0x0, 0x0, 40, 672, 255, 0, 0, -1 },
+  { 0x1, 0x1, 40, 673, 129, 34, 1, 20 },
+  { 0x10000001, 0x10000001, 40, 674, 129, 6, 1, 20 },
+  { 0x0, 0x0, 40, 675, 259, 0, 0, -1 },
+  { 0x1, 0x1, 40, 676, 130, 34, 1, 21 },
+  { 0x0, 0x0, 40, 677, 263, 0, 0, -1 },
+  { 0x0, 0x0, 40, 678, 267, 0, 0, -1 },
+  { 0x1, 0x1, 40, 679, 131, 34, 1, 22 },
+  { 0x10000001, 0x10000001, 40, 680, 131, 6, 1, 22 },
+  { 0x0, 0x0, 40, 681, 271, 0, 0, -1 },
+  { 0x1, 0x1, 40, 682, 132, 34, 1, 23 },
+  { 0x800001, 0x800001, 40, 705, 316, 4, 1, 18 },
+  { 0x1, 0x1, 40, 516, 316, 4, 1, 18 },
+  { 0x1, 0x1, 40, 221, 317, 4, 1, 24 },
+  { 0x2, 0x3, 40, 319, 318, 20, 1, 69 },
+  { 0x1, 0x1, 40, 320, 318, 21, 1, 69 },
+  { 0x0, 0x0, 41, -1, -1, 0, 1, 82 },
+  { 0x0, 0x0, 41, -1, -1, 0, 1, 125 },
+  { 0x1, 0x1, 43, 342, 87, 38, 1, 3 },
+  { 0x0, 0x0, 43, 409, 101, 0, 0, -1 },
+  { 0x0, 0x0, 43, 410, 92, 0, 0, -1 },
+  { 0x1, 0x1, 43, 346, 87, 38, 1, 3 },
+  { 0x0, 0x0, 43, 334, 538, 0, 0, -1 },
+  { 0x0, 0x0, 43, 335, 724, 0, 1, 56 },
+  { 0x0, 0x0, 43, 336, 554, 0, 0, -1 },
+  { 0x0, 0x0, 43, 337, -1, 0, 1, 51 },
+  { 0x0, 0x0, 43, 298, -1, 0, 1, 0 },
+  { 0x1, 0x1, 44, 447, 447, 30, 1, 143 },
+  { 0x1, 0x1, 44, 225, 446, 30, 1, 142 },
+  { 0x1, 0x1, 44, 449, 449, 30, 1, 145 },
+  { 0x1, 0x1, 44, 226, 448, 30, 1, 144 },
+  { 0x3, 0x3, 45, 340, 317, 3, 1, 24 },
+  { 0x1, 0x1, 46, 529, -1, 30, 1, 136 },
+  { 0x1, 0x1, 46, 532, -1, 30, 1, 146 },
+  { 0x0, 0x0, 48, -1, -1, 0, 1, 42 },
+  { 0x1, 0x1, 55, 446, 217, 31, 1, 143 },
+  { 0x1, 0x1, 55, 448, 219, 31, 1, 145 },
+  { 0x2, 0x3, 55, -1, -1, 27, 1, 96 },
+  { 0x0, 0x0, 55, -1, -1, 0, 1, 96 },
+  { 0x1, 0x1, 55, -1, -1, 28, 1, 96 },
+  { 0x0, 0x0, 64, 360, 122, 0, 1, 8 },
+  { 0x3, 0x3, 64, 361, 122, 33, 1, 8 },
+  { 0x1, 0x1, 64, 362, 122, 34, 1, 8 },
+  { 0x1, 0x1, 64, 363, 122, 33, 1, 8 },
+  { 0x18000001, 0x18000001, 64, 364, 124, 6, 1, 9 },
+  { 0x10000001, 0x10000001, 64, 365, 124, 6, 1, 9 },
+  { 0x8000001, 0x8000001, 64, 366, 124, 6, 1, 9 },
+  { 0x1, 0x1, 64, 367, 124, 6, 1, 9 },
+  { 0x3, 0x3, 64, 368, 125, 33, 1, 10 },
+  { 0x1, 0x1, 64, 369, 125, 34, 1, 10 },
+  { 0x1, 0x1, 64, 370, 125, 33, 1, 10 },
+  { 0x0, 0x0, 64, 371, 125, 0, 1, 10 },
+  { 0x3, 0x3, 64, 372, 126, 33, 1, 17 },
+  { 0x1, 0x1, 64, 373, 126, 34, 1, 17 },
+  { 0x1, 0x1, 64, 374, 126, 33, 1, 17 },
+  { 0x0, 0x0, 64, 375, 126, 0, 1, 17 },
+  { 0x0, 0x0, 64, 376, 127, 0, 1, 19 },
+  { 0x3, 0x3, 64, 377, 127, 33, 1, 19 },
+  { 0x1, 0x1, 64, 378, 127, 34, 1, 19 },
+  { 0x1, 0x1, 64, 379, 127, 33, 1, 19 },
+  { 0x3, 0x3, 64, 380, 129, 33, 1, 20 },
+  { 0x1, 0x1, 64, 381, 129, 34, 1, 20 },
+  { 0x1, 0x1, 64, 382, 129, 33, 1, 20 },
+  { 0x0, 0x0, 64, 383, 129, 0, 1, 20 },
+  { 0x18000001, 0x18000001, 64, 384, 129, 6, 1, 20 },
+  { 0x10000001, 0x10000001, 64, 385, 129, 6, 1, 20 },
+  { 0x8000001, 0x8000001, 64, 386, 129, 6, 1, 20 },
+  { 0x1, 0x1, 64, 387, 129, 6, 1, 20 },
+  { 0x3, 0x3, 64, 388, 130, 33, 1, 21 },
+  { 0x1, 0x1, 64, 389, 130, 34, 1, 21 },
+  { 0x1, 0x1, 64, 390, 130, 33, 1, 21 },
+  { 0x0, 0x0, 64, 391, 130, 0, 1, 21 },
+  { 0x3, 0x3, 64, 392, 131, 33, 1, 22 },
+  { 0x1, 0x1, 64, 393, 131, 34, 1, 22 },
+  { 0x1, 0x1, 64, 394, 131, 33, 1, 22 },
+  { 0x0, 0x0, 64, 395, 131, 0, 1, 22 },
+  { 0x18000001, 0x18000001, 64, 396, 131, 6, 1, 22 },
+  { 0x10000001, 0x10000001, 64, 397, 131, 6, 1, 22 },
+  { 0x8000001, 0x8000001, 64, 398, 131, 6, 1, 22 },
+  { 0x1, 0x1, 64, 399, 131, 6, 1, 22 },
+  { 0x3, 0x3, 64, 400, 132, 33, 1, 23 },
+  { 0x1, 0x1, 64, 401, 132, 34, 1, 23 },
+  { 0x1, 0x1, 64, 402, 132, 33, 1, 23 },
+  { 0x0, 0x0, 64, 403, 132, 0, 1, 23 },
+  { 0x3, 0x3, 65, 438, 439, 33, 1, 130 },
+  { 0x0, 0x0, 65, -1, 440, 0, 1, 137 },
+  { 0x0, 0x0, 106, 278, 548, 0, 0, -1 },
+  { 0x0, 0x0, 106, 279, 715, 0, 1, 31 },
+  { 0x0, 0x0, 108, -1, 550, 0, 0, -1 },
+  { 0x1, 0x1, 108, -1, 715, 27, 1, 31 },
+  { 0x0, 0x0, 109, 281, -1, 0, 1, 117 },
+  { 0x1, 0x1, 110, -1, -1, 27, 1, 117 },
+  { 0x0, 0x0, 111, 289, 718, 0, 1, 3 },
+  { 0x0, 0x0, 111, 292, 89, 0, 0, -1 },
+  { 0x0, 0x0, 111, 293, 103, 0, 0, -1 },
+  { 0x0, 0x0, 111, 295, 94, 0, 0, -1 },
+  { 0x0, 0x0, 111, 408, 718, 0, 1, 3 },
+  { 0x0, 0x0, 111, 296, 546, 0, 0, -1 },
+  { 0x1, 0x9, 111, 297, 724, 33, 1, 56 },
+  { 0x1, 0x1, 113, 408, 718, 37, 1, 3 },
+  { 0x0, 0x0, 113, -1, 718, 0, 1, 3 },
+  { 0x0, 0x0, 114, 299, 718, 0, 1, 3 },
+  { 0x0, 0x0, 114, 330, 90, 0, 0, -1 },
+  { 0x0, 0x0, 114, 331, 101, 0, 0, -1 },
+  { 0x0, 0x0, 114, -1, 718, 0, 1, 3 },
+  { 0x0, 0x0, 114, 333, 92, 0, 0, -1 },
+  { 0x0, 0x0, 114, -1, 538, 0, 0, -1 },
+  { 0x0, 0x0, 114, -1, 724, 0, 1, 56 },
+  { 0x1, 0x1, 114, -1, -1, 27, 1, 0 },
+  { 0x1, 0x1, 115, -1, 718, 37, 1, 3 },
+  { 0x0, 0x0, 115, -1, 718, 0, 1, 3 },
+  { 0x0, 0x0, 116, 326, -1, 0, 1, 0 },
+  { 0x3, 0x3, 116, 304, -1, 34, 1, 35 },
+  { 0x3, 0x3, 116, 305, -1, 34, 1, 42 },
+  { 0x1, 0x1, 117, 327, -1, 35, 1, 35 },
+  { 0x1, 0x1, 117, 328, -1, 35, 1, 42 },
+  { 0x0, 0x0, 118, -1, -1, 0, 1, 42 },
+  { 0x0, 0x0, 118, -1, -1, 0, 1, 68 },
+  { 0x1, 0x1, 118, -1, -1, 27, 1, 98 },
+  { 0x0, 0x0, 118, -1, -1, 0, 1, 107 },
+  { 0x0, 0x0, 118, -1, -1, 0, 1, 75 },
+  { 0x0, 0x0, 118, -1, -1, 0, 1, 76 },
+  { 0x1, 0x1, 118, -1, -1, 27, 1, 119 },
+  { 0x1, 0x1, 118, -1, -1, 27, 1, 42 },
+  { 0x0, 0x0, 119, 661, 154, 0, 0, -1 },
+  { 0x0, 0x0, 119, 663, 157, 0, 0, -1 },
+  { 0x1, 0x1, 120, -1, -1, 35, 1, 18 },
+  { 0x1, 0x1, 120, -1, -1, 35, 1, 24 },
+  { 0x1, 0x1, 120, -1, -1, 23, 1, 69 },
+  { 0x1, 0x1, 120, 708, -1, 23, 1, 69 },
+  { 0x9, 0x9, 120, 517, -1, 20, 1, 69 },
+  { 0x0, 0x0, 124, 503, -1, 0, 1, 0 },
+  { 0x1, 0x1, 124, 341, -1, 28, 1, 35 },
+  { 0x1, 0x1, 124, 505, -1, 27, 1, 35 },
+  { 0x1, 0x1, 124, 506, -1, 29, 1, 0 },
+  { 0x0, 0x0, 124, -1, -1, 0, 1, 116 },
+  { 0x1, 0x1, 124, -1, -1, 29, 1, 0 },
+  { 0x0, 0x0, 124, -1, -1, 0, 1, 35 },
+  { 0x0, 0x0, 124, 354, -1, 0, 1, 42 },
+  { 0x0, 0x0, 137, 338, 718, 0, 1, 3 },
+  { 0x0, 0x0, 137, 343, 91, 0, 0, -1 },
+  { 0x0, 0x0, 137, 344, 102, 0, 0, -1 },
+  { 0x0, 0x0, 137, -1, 718, 0, 1, 3 },
+  { 0x0, 0x0, 137, 345, 93, 0, 0, -1 },
+  { 0x0, 0x0, 137, 347, 540, 0, 0, -1 },
+  { 0x1, 0x1, 137, 348, 724, 33, 1, 56 },
+  { 0x0, 0x0, 137, 349, 555, 0, 0, -1 },
+  { 0x1, 0x1, 137, 350, -1, 28, 1, 51 },
+  { 0x1, 0x1, 138, -1, 718, 37, 1, 3 },
+  { 0x0, 0x0, 138, -1, 718, 0, 1, 3 },
+  { 0x1, 0x1, 141, 707, 317, 3, 1, 24 },
+  { 0x0, 0x0, 142, 504, -1, 0, 1, 35 },
+  { 0x0, 0x0, 143, 351, 718, 0, 1, 3 },
+  { 0x0, 0x0, 143, -1, 88, 0, 0, -1 },
+  { 0x0, 0x0, 143, -1, 104, 0, 0, -1 },
+  { 0x0, 0x0, 143, -1, 95, 0, 0, -1 },
+  { 0x0, 0x0, 143, 407, 718, 0, 1, 3 },
+  { 0x0, 0x0, 143, 727, 542, 0, 0, -1 },
+  { 0x1, 0x1, 143, 728, 724, 36, 1, 56 },
+  { 0x0, 0x0, 143, 413, 556, 0, 0, -1 },
+  { 0x1, 0x1, 143, 414, -1, 27, 1, 51 },
+  { 0x1, 0x1, 144, 407, 718, 37, 1, 3 },
+  { 0x0, 0x0, 144, -1, 718, 0, 1, 3 },
+  { 0x0, 0x0, 145, -1, -1, 0, 1, 35 },
+  { 0x0, 0x0, 145, -1, -1, 0, 1, 42 },
+  { 0x0, 0x0, 146, -1, -1, 0, 1, 42 },
+  { 0x0, 0x0, 146, -1, -1, 0, 1, 68 },
+  { 0x0, 0x0, 146, -1, 719, 0, 1, 65 },
+  { 0x0, 0x0, 146, -1, -1, 0, 1, 83 },
+  { 0x0, 0x0, 146, -1, -1, 0, 1, 87 },
+  { 0x1, 0x1, 147, -1, 122, 12, 1, 8 },
+  { 0x600001, 0x600001, 147, -1, 122, 12, 1, 8 },
+  { 0x400001, 0x400001, 147, -1, 122, 12, 1, 8 },
+  { 0x200001, 0x200001, 147, -1, 122, 12, 1, 8 },
+  { 0x18000041, 0x18000041, 147, -1, 124, 6, 1, 9 },
+  { 0x10000041, 0x10000041, 147, -1, 124, 6, 1, 9 },
+  { 0x8000041, 0x8000041, 147, -1, 124, 6, 1, 9 },
+  { 0x41, 0x41, 147, -1, 124, 6, 1, 9 },
+  { 0x600001, 0x600001, 147, -1, 125, 12, 1, 10 },
+  { 0x400001, 0x400001, 147, -1, 125, 12, 1, 10 },
+  { 0x200001, 0x200001, 147, -1, 125, 12, 1, 10 },
+  { 0x1, 0x1, 147, -1, 125, 12, 1, 10 },
+  { 0x600001, 0x600001, 147, -1, 126, 12, 1, 17 },
+  { 0x400001, 0x400001, 147, -1, 126, 12, 1, 17 },
+  { 0x200001, 0x200001, 147, -1, 126, 12, 1, 17 },
+  { 0x1, 0x1, 147, -1, 126, 12, 1, 17 },
+  { 0x1, 0x1, 147, -1, 127, 12, 1, 19 },
+  { 0x600001, 0x600001, 147, -1, 127, 12, 1, 19 },
+  { 0x400001, 0x400001, 147, -1, 127, 12, 1, 19 },
+  { 0x200001, 0x200001, 147, -1, 127, 12, 1, 19 },
+  { 0x600001, 0x600001, 147, -1, 129, 12, 1, 20 },
+  { 0x400001, 0x400001, 147, -1, 129, 12, 1, 20 },
+  { 0x200001, 0x200001, 147, -1, 129, 12, 1, 20 },
+  { 0x1, 0x1, 147, -1, 129, 12, 1, 20 },
+  { 0x18000041, 0x18000041, 147, -1, 129, 6, 1, 20 },
+  { 0x10000041, 0x10000041, 147, -1, 129, 6, 1, 20 },
+  { 0x8000041, 0x8000041, 147, -1, 129, 6, 1, 20 },
+  { 0x41, 0x41, 147, -1, 129, 6, 1, 20 },
+  { 0x600001, 0x600001, 147, -1, 130, 12, 1, 21 },
+  { 0x400001, 0x400001, 147, -1, 130, 12, 1, 21 },
+  { 0x200001, 0x200001, 147, -1, 130, 12, 1, 21 },
+  { 0x1, 0x1, 147, -1, 130, 12, 1, 21 },
+  { 0x600001, 0x600001, 147, -1, 131, 12, 1, 22 },
+  { 0x400001, 0x400001, 147, -1, 131, 12, 1, 22 },
+  { 0x200001, 0x200001, 147, -1, 131, 12, 1, 22 },
+  { 0x1, 0x1, 147, -1, 131, 12, 1, 22 },
+  { 0x18000041, 0x18000041, 147, -1, 131, 6, 1, 22 },
+  { 0x10000041, 0x10000041, 147, -1, 131, 6, 1, 22 },
+  { 0x8000041, 0x8000041, 147, -1, 131, 6, 1, 22 },
+  { 0x41, 0x41, 147, -1, 131, 6, 1, 22 },
+  { 0x600001, 0x600001, 147, -1, 132, 12, 1, 23 },
+  { 0x400001, 0x400001, 147, -1, 132, 12, 1, 23 },
+  { 0x200001, 0x200001, 147, -1, 132, 12, 1, 23 },
+  { 0x1, 0x1, 147, -1, 132, 12, 1, 23 },
+  { 0x0, 0x0, 156, -1, -1, 0, 1, 77 },
+  { 0x9, 0x9, 156, -1, 435, 32, 1, 131 },
+  { 0x9, 0x9, 156, -1, 442, 32, 1, 141 },
+  { 0x0, 0x0, 157, -1, 88, 0, 0, -1 },
+  { 0x1, 0x1, 157, -1, 718, 38, 1, 3 },
+  { 0x0, 0x0, 157, -1, 102, 0, 0, -1 },
+  { 0x0, 0x0, 157, -1, 93, 0, 0, -1 },
+  { 0x0, 0x0, 158, 420, 538, 0, 0, -1 },
+  { 0x0, 0x0, 158, 421, 724, 0, 1, 56 },
+  { 0x0, 0x0, 158, 422, 557, 0, 0, -1 },
+  { 0x1, 0x1, 158, 423, -1, 29, 1, 51 },
+  { 0x0, 0x0, 159, 417, 546, 0, 0, -1 },
+  { 0x1, 0x9, 159, 418, 724, 33, 1, 56 },
+  { 0x0, 0x0, 160, -1, 538, 0, 0, -1 },
+  { 0x0, 0x0, 160, -1, 724, 0, 1, 56 },
+  { 0x1, 0x1, 161, 429, -1, 27, 1, 35 },
+  { 0x0, 0x0, 162, 424, 540, 0, 0, -1 },
+  { 0x1, 0x1, 162, 425, 724, 33, 1, 56 },
+  { 0x0, 0x0, 162, 426, 558, 0, 0, -1 },
+  { 0x3, 0x3, 162, 427, -1, 28, 1, 51 },
+  { 0x0, 0x0, 163, 498, 542, 0, 0, -1 },
+  { 0x1, 0x1, 163, 499, 724, 36, 1, 56 },
+  { 0x0, 0x0, 163, 500, 559, 0, 0, -1 },
+  { 0x5, 0x5, 163, 501, -1, 27, 1, 51 },
+  { 0x0, 0x0, 164, -1, 719, 0, 1, 65 },
+  { 0x1, 0x1, 166, -1, -1, 28, 1, 35 },
+  { 0x1, 0x1, 167, 526, -1, 27, 1, 35 },
+  { 0x1, 0x1, 168, 454, -1, 28, 1, 134 },
+  { 0x1, 0x1, 168, 455, -1, 28, 1, 135 },
+  { 0x1, 0x1, 168, 456, -1, 28, 1, 128 },
+  { 0x1, 0x1, 168, 457, -1, 28, 1, 126 },
+  { 0x1, 0x1, 168, 458, -1, 28, 1, 131 },
+  { 0x1, 0x1, 168, 459, -1, 28, 1, 127 },
+  { 0x1, 0x1, 168, 460, -1, 28, 1, 129 },
+  { 0x1, 0x1, 168, 461, -1, 28, 1, 126 },
+  { 0x1, 0x1, 168, 462, -1, 28, 1, 130 },
+  { 0x1, 0x1, 168, 463, -1, 28, 1, 137 },
+  { 0x1, 0x1, 168, 464, -1, 28, 1, 139 },
+  { 0x1, 0x1, 168, 465, -1, 28, 1, 141 },
+  { 0x1, 0x1, 168, 466, -1, 28, 1, 138 },
+  { 0x1, 0x1, 168, 467, -1, 28, 1, 140 },
+  { 0x1, 0x1, 168, 468, -1, 28, 1, 137 },
+  { 0x1, 0x1, 168, 450, -1, 28, 1, 142 },
+  { 0x1, 0x1, 168, 451, -1, 28, 1, 143 },
+  { 0x1, 0x1, 168, 452, -1, 28, 1, 144 },
+  { 0x1, 0x1, 168, 453, -1, 28, 1, 145 },
+  { 0x1, 0x1, 169, 469, -1, 29, 1, 142 },
+  { 0x1, 0x1, 169, 470, -1, 29, 1, 143 },
+  { 0x1, 0x1, 169, 471, -1, 29, 1, 144 },
+  { 0x1, 0x1, 169, 472, -1, 29, 1, 145 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 134 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 135 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 128 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 126 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 131 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 127 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 129 },
+  { 0x3, 0x3, 170, 530, -1, 28, 1, 126 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 130 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 137 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 139 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 141 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 138 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 140 },
+  { 0x3, 0x3, 170, 531, -1, 28, 1, 137 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 142 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 143 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 144 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 145 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 132 },
+  { 0x3, 0x3, 170, 512, -1, 28, 1, 132 },
+  { 0x3, 0x3, 170, -1, -1, 28, 1, 133 },
+  { 0x3, 0x3, 170, 513, -1, 28, 1, 132 },
+  { 0x0, 0x0, 171, 744, 96, 0, 0, -1 },
+  { 0x0, 0x0, 171, 745, 98, 0, 1, 3 },
+  { 0x11, 0x31, 172, 718, 100, 33, 1, 6 },
+  { 0x2200001, 0x2200001, 172, -1, 100, 12, 1, 6 },
+  { 0x11, 0x11, 172, -1, 100, 33, 1, 6 },
+  { 0x1, 0x1, 172, -1, 100, 37, 1, 6 },
+  { 0x2000001, 0x2000001, 172, -1, 100, 12, 1, 6 },
+  { 0x200001, 0x200001, 172, -1, 105, 12, 1, 6 },
+  { 0x1, 0x1, 172, 718, 105, 33, 1, 6 },
+  { 0x2000001, 0x2000001, 173, -1, -1, 12, 1, 6 },
+  { 0x1, 0x1, 173, -1, -1, 37, 1, 6 },
+  { 0x2200001, 0x2200001, 173, -1, -1, 12, 1, 6 },
+  { 0x11, 0x11, 173, -1, -1, 33, 1, 6 },
+  { 0x1, 0x1, 173, -1, -1, 12, 1, 7 },
+  { 0x0, 0x0, 173, -1, -1, 0, 1, 7 },
+  { 0x200001, 0x200001, 173, -1, -1, 12, 1, 7 },
+  { 0x1, 0x1, 173, -1, -1, 33, 1, 7 },
+  { 0x9, 0x9, 173, -1, -1, 33, 1, 7 },
+  { 0x1, 0x1, 173, 718, -1, 33, 1, 6 },
+  { 0x1200001, 0x1200001, 173, -1, -1, 12, 1, 7 },
+  { 0x200001, 0x200001, 173, -1, -1, 12, 1, 6 },
+  { 0x0, 0x0, 174, -1, 544, 0, 0, -1 },
+  { 0x9, 0x9, 174, -1, 725, 33, 1, 51 },
+  { 0x0, 0x0, 174, 729, 560, 0, 0, -1 },
+  { 0x7, 0x7, 174, 730, -1, 27, 1, 51 },
+  { 0x1, 0x1, 194, -1, -1, 27, 1, 12 },
+  { 0x1, 0x1, 208, -1, -1, 29, 1, 0 },
+  { 0x2, 0x3, 208, -1, -1, 27, 1, 35 },
+  { 0x0, 0x0, 208, -1, -1, 0, 1, 35 },
+  { 0x0, 0x0, 208, -1, -1, 0, 1, 0 },
+  { 0x0, 0x0, 208, 734, -1, 0, 1, 95 },
+  { 0x0, 0x0, 208, 518, 227, 0, 0, -1 },
+  { 0x1, 0x1, 209, -1, -1, 27, 1, 0 },
+  { 0x1, 0x1, 210, -1, 431, 32, 1, 134 },
+  { 0x1, 0x1, 210, -1, 432, 32, 1, 135 },
+  { 0x1, 0x1, 210, -1, 473, 32, 1, 132 },
+  { 0x1, 0x1, 210, 659, 473, 32, 1, 132 },
+  { 0x0, 0x0, 211, -1, 159, 0, 0, -1 },
+  { 0x0, 0x0, 211, -1, 160, 0, 0, -1 },
+  { 0x0, 0x0, 211, 706, 201, 0, 0, -1 },
+  { 0x5, 0x5, 211, 709, 204, 20, 1, 69 },
+  { 0x0, 0x0, 215, 735, 228, 0, 0, -1 },
+  { 0x0, 0x0, 216, -1, 307, 0, 0, -1 },
+  { 0x0, 0x0, 216, -1, 356, 0, 0, -1 },
+  { 0x0, 0x0, 216, -1, -1, 0, 1, 123 },
+  { 0x0, 0x0, 216, -1, -1, 0, 1, 68 },
+  { 0x1, 0x1, 216, 533, 534, 36, 1, 67 },
+  { 0x1, 0x1, 216, 533, 565, 36, 1, 67 },
+  { 0x0, 0x0, 216, -1, 552, 0, 0, -1 },
+  { 0x0, 0x0, 216, 656, -1, 0, 1, 35 },
+  { 0x0, 0x0, 216, 533, 553, 0, 0, -1 },
+  { 0x1, 0x1, 216, -1, -1, 36, 1, 67 },
+  { 0x1, 0x1, 216, 657, -1, 31, 1, 136 },
+  { 0x1, 0x1, 216, 654, 436, 32, 1, 127 },
+  { 0x1, 0x1, 216, 655, 443, 32, 1, 138 },
+  { 0x1, 0x1, 216, 658, -1, 31, 1, 146 },
+  { 0x0, 0x0, 217, 564, -1, 0, 1, 30 },
+  { 0x0, 0x0, 217, 565, -1, 0, 1, 67 },
+  { 0x0, 0x0, 217, 566, -1, 0, 1, 46 },
+  { 0x0, 0x0, 217, 567, -1, 0, 1, 41 },
+  { 0x1, 0x1, 217, 568, -1, 12, 1, 60 },
+  { 0x0, 0x0, 217, 569, -1, 0, 1, 55 },
+  { 0x200001, 0x200001, 217, 570, -1, 12, 1, 60 },
+  { 0x1, 0x1, 217, 571, -1, 33, 1, 55 },
+  { 0x1000001, 0x1000001, 217, 572, -1, 12, 1, 60 },
+  { 0x1, 0x1, 217, 573, -1, 36, 1, 55 },
+  { 0x1200001, 0x1200001, 217, 574, -1, 12, 1, 50 },
+  { 0x9, 0x9, 217, 575, -1, 33, 1, 50 },
+  { 0x200001, 0x1200001, 217, 576, -1, 12, 1, 60 },
+  { 0x1, 0x9, 217, 577, -1, 33, 1, 55 },
+  { 0x1, 0x1, 217, 578, -1, 28, 1, 30 },
+  { 0x0, 0x0, 217, 579, -1, 0, 1, 30 },
+  { 0x3, 0x3, 217, 580, -1, 27, 1, 30 },
+  { 0x1, 0x1, 217, 581, -1, 27, 1, 30 },
+  { 0x1, 0x1, 217, 582, -1, 37, 1, 30 },
+  { 0x1, 0x1, 217, -1, -1, 36, 1, 67 },
+  { 0x1, 0x1, 217, 583, -1, 36, 1, 67 },
+  { 0x0, 0x0, 217, 584, -1, 0, 1, 50 },
+  { 0x1, 0x1, 217, 585, -1, 28, 1, 50 },
+  { 0x1, 0x1, 217, 586, -1, 27, 1, 50 },
+  { 0x1, 0x1, 217, 587, -1, 29, 1, 50 },
+  { 0x3, 0x3, 217, 588, -1, 28, 1, 50 },
+  { 0x5, 0x5, 217, 589, -1, 27, 1, 50 },
+  { 0x7, 0x7, 217, 590, -1, 27, 1, 50 },
+  { 0x3, 0x3, 217, 591, -1, 27, 1, 50 },
+  { 0x0, 0x0, 217, 592, -1, 0, 1, 25 },
+  { 0x0, 0x0, 217, 593, -1, 0, 1, 36 },
+  { 0x1, 0x1, 218, 594, -1, 34, 1, 32 },
+  { 0x1, 0x1, 218, 595, -1, 34, 1, 67 },
+  { 0x1, 0x1, 218, 596, -1, 34, 1, 47 },
+  { 0x1, 0x1, 218, 597, -1, 34, 1, 43 },
+  { 0x400001, 0x400001, 218, 598, -1, 12, 1, 62 },
+  { 0x1, 0x1, 218, 599, -1, 34, 1, 57 },
+  { 0x600001, 0x600001, 218, 600, -1, 12, 1, 62 },
+  { 0x3, 0x3, 218, 601, -1, 33, 1, 57 },
+  { 0x1400001, 0x1400001, 218, 602, -1, 12, 1, 62 },
+  { 0x5, 0x5, 218, 603, -1, 34, 1, 57 },
+  { 0x1600001, 0x1600001, 218, 604, -1, 12, 1, 52 },
+  { 0xb, 0xb, 218, 605, -1, 33, 1, 52 },
+  { 0x600001, 0x1600001, 218, 606, -1, 12, 1, 62 },
+  { 0x3, 0xb, 218, 607, -1, 33, 1, 57 },
+  { 0x41, 0x41, 218, 608, -1, 28, 1, 32 },
+  { 0x1, 0x1, 218, 609, -1, 34, 1, 32 },
+  { 0x83, 0x83, 218, 610, -1, 27, 1, 32 },
+  { 0x81, 0x81, 218, 611, -1, 27, 1, 32 },
+  { 0x9, 0x9, 218, 612, -1, 34, 1, 32 },
+  { 0x5, 0x5, 218, 613, -1, 34, 1, 67 },
+  { 0x1, 0x1, 218, 614, -1, 34, 1, 52 },
+  { 0x41, 0x41, 218, 615, -1, 28, 1, 52 },
+  { 0x81, 0x81, 218, 616, -1, 27, 1, 52 },
+  { 0x21, 0x21, 218, 617, -1, 29, 1, 52 },
+  { 0x43, 0x43, 218, 618, -1, 28, 1, 52 },
+  { 0x85, 0x85, 218, 619, -1, 27, 1, 52 },
+  { 0x87, 0x87, 218, 620, -1, 27, 1, 52 },
+  { 0x83, 0x83, 218, 621, -1, 27, 1, 52 },
+  { 0x1, 0x1, 218, 622, -1, 34, 1, 27 },
+  { 0x1, 0x1, 218, 623, -1, 34, 1, 38 },
+  { 0x1, 0x1, 219, 624, -1, 35, 1, 33 },
+  { 0x1, 0x1, 219, 625, -1, 35, 1, 67 },
+  { 0x1, 0x1, 219, 626, -1, 35, 1, 48 },
+  { 0x1, 0x1, 219, 627, -1, 35, 1, 44 },
+  { 0x800001, 0x800001, 219, 628, -1, 12, 1, 63 },
+  { 0x1, 0x1, 219, 629, -1, 35, 1, 58 },
+  { 0xa00001, 0xa00001, 219, 630, -1, 12, 1, 63 },
+  { 0x5, 0x5, 219, 631, -1, 33, 1, 58 },
+  { 0x1800001, 0x1800001, 219, 632, -1, 12, 1, 63 },
+  { 0x3, 0x3, 219, 633, -1, 35, 1, 58 },
+  { 0x1a00001, 0x1a00001, 219, 634, -1, 12, 1, 53 },
+  { 0xd, 0xd, 219, 635, -1, 33, 1, 53 },
+  { 0xa00001, 0x1a00001, 219, 636, -1, 12, 1, 63 },
+  { 0x5, 0xd, 219, 637, -1, 33, 1, 58 },
+  { 0x81, 0x81, 219, 638, -1, 28, 1, 33 },
+  { 0x1, 0x1, 219, 639, -1, 35, 1, 33 },
+  { 0x103, 0x103, 219, 640, -1, 27, 1, 33 },
+  { 0x101, 0x101, 219, 641, -1, 27, 1, 33 },
+  { 0x5, 0x5, 219, 642, -1, 35, 1, 33 },
+  { 0x3, 0x3, 219, 643, -1, 35, 1, 67 },
+  { 0x1, 0x1, 219, 644, -1, 35, 1, 53 },
+  { 0x81, 0x81, 219, 645, -1, 28, 1, 53 },
+  { 0x101, 0x101, 219, 646, -1, 27, 1, 53 },
+  { 0x41, 0x41, 219, 647, -1, 29, 1, 53 },
+  { 0x83, 0x83, 219, 648, -1, 28, 1, 53 },
+  { 0x105, 0x105, 219, 649, -1, 27, 1, 53 },
+  { 0x107, 0x107, 219, 650, -1, 27, 1, 53 },
+  { 0x103, 0x103, 219, 651, -1, 27, 1, 53 },
+  { 0x1, 0x1, 219, 652, -1, 35, 1, 28 },
+  { 0x1, 0x1, 219, 653, -1, 35, 1, 39 },
+  { 0x3, 0x3, 220, -1, -1, 34, 1, 34 },
+  { 0x3, 0x3, 220, -1, -1, 34, 1, 67 },
+  { 0x3, 0x3, 220, -1, -1, 34, 1, 49 },
+  { 0x3, 0x3, 220, -1, -1, 34, 1, 45 },
+  { 0xc00001, 0xc00001, 220, -1, -1, 12, 1, 64 },
+  { 0x3, 0x3, 220, 720, -1, 34, 1, 59 },
+  { 0xe00001, 0xe00001, 220, -1, -1, 12, 1, 64 },
+  { 0x7, 0x7, 220, 721, -1, 33, 1, 59 },
+  { 0x1c00001, 0x1c00001, 220, -1, -1, 12, 1, 64 },
+  { 0x7, 0x7, 220, 722, -1, 34, 1, 59 },
+  { 0x1e00001, 0x1e00001, 220, -1, -1, 12, 1, 54 },
+  { 0xf, 0xf, 220, 723, -1, 33, 1, 54 },
+  { 0xe00001, 0x1e00001, 220, -1, -1, 12, 1, 64 },
+  { 0x7, 0xf, 220, 726, -1, 33, 1, 59 },
+  { 0xc1, 0xc1, 220, -1, -1, 28, 1, 34 },
+  { 0x3, 0x3, 220, 713, -1, 34, 1, 34 },
+  { 0x183, 0x183, 220, -1, -1, 27, 1, 34 },
+  { 0x181, 0x181, 220, 714, -1, 27, 1, 34 },
+  { 0xb, 0xb, 220, -1, -1, 34, 1, 34 },
+  { 0x7, 0x7, 220, -1, -1, 34, 1, 67 },
+  { 0x3, 0x3, 220, -1, -1, 34, 1, 54 },
+  { 0xc1, 0xc1, 220, -1, -1, 28, 1, 54 },
+  { 0x181, 0x181, 220, -1, -1, 27, 1, 54 },
+  { 0x61, 0x61, 220, -1, -1, 29, 1, 54 },
+  { 0xc3, 0xc3, 220, -1, -1, 28, 1, 54 },
+  { 0x185, 0x185, 220, -1, -1, 27, 1, 54 },
+  { 0x187, 0x187, 220, -1, -1, 27, 1, 54 },
+  { 0x183, 0x183, 220, -1, -1, 27, 1, 54 },
+  { 0x3, 0x3, 220, -1, -1, 34, 1, 29 },
+  { 0x3, 0x3, 220, -1, -1, 34, 1, 40 },
+  { 0x3, 0x3, 221, -1, 437, 32, 1, 129 },
+  { 0x3, 0x3, 221, -1, 444, 32, 1, 140 },
+  { 0x1, 0x1, 222, -1, -1, 28, 1, 35 },
+  { 0x0, 0x0, 229, -1, -1, 0, 1, 136 },
+  { 0x0, 0x0, 229, -1, -1, 0, 1, 146 },
+  { 0x1, 0x1, 230, -1, 475, 33, 1, 133 },
+  { 0x0, 0x0, 230, -1, 473, 0, 1, 132 },
+  { 0x0, 0x0, 231, 683, 233, 0, 0, -1 },
+  { 0x0, 0x0, 231, 684, 236, 0, 0, -1 },
+  { 0x1, 0x1, 231, 685, 122, 33, 1, 8 },
+  { 0x8000001, 0x8000001, 231, 686, 124, 6, 1, 9 },
+  { 0x0, 0x0, 231, 687, 240, 0, 0, -1 },
+  { 0x1, 0x1, 231, 688, 125, 33, 1, 10 },
+  { 0x0, 0x0, 231, 689, 244, 0, 0, -1 },
+  { 0x1, 0x1, 231, 690, 126, 33, 1, 17 },
+  { 0x0, 0x0, 231, 691, 249, 0, 0, -1 },
+  { 0x1, 0x1, 231, 692, 127, 33, 1, 19 },
+  { 0x0, 0x0, 231, 693, 252, 0, 0, -1 },
+  { 0x0, 0x0, 231, 694, 256, 0, 0, -1 },
+  { 0x1, 0x1, 231, 695, 129, 33, 1, 20 },
+  { 0x8000001, 0x8000001, 231, 696, 129, 6, 1, 20 },
+  { 0x0, 0x0, 231, 697, 260, 0, 0, -1 },
+  { 0x1, 0x1, 231, 698, 130, 33, 1, 21 },
+  { 0x0, 0x0, 231, 699, 264, 0, 0, -1 },
+  { 0x0, 0x0, 231, 700, 268, 0, 0, -1 },
+  { 0x1, 0x1, 231, 701, 131, 33, 1, 22 },
+  { 0x8000001, 0x8000001, 231, 702, 131, 6, 1, 22 },
+  { 0x0, 0x0, 231, 703, 272, 0, 0, -1 },
+  { 0x1, 0x1, 231, 704, 132, 33, 1, 23 },
+  { 0x0, 0x0, 232, -1, 230, 0, 0, -1 },
+  { 0x0, 0x0, 232, -1, 237, 0, 0, -1 },
+  { 0x0, 0x0, 232, -1, 122, 0, 1, 8 },
+  { 0x1, 0x1, 232, -1, 124, 6, 1, 9 },
+  { 0x0, 0x0, 232, -1, 241, 0, 0, -1 },
+  { 0x0, 0x0, 232, -1, 125, 0, 1, 10 },
+  { 0x0, 0x0, 232, -1, 245, 0, 0, -1 },
+  { 0x0, 0x0, 232, -1, 126, 0, 1, 17 },
+  { 0x0, 0x0, 232, -1, 246, 0, 0, -1 },
+  { 0x0, 0x0, 232, -1, 127, 0, 1, 19 },
+  { 0x0, 0x0, 232, -1, 253, 0, 0, -1 },
+  { 0x0, 0x0, 232, -1, 257, 0, 0, -1 },
+  { 0x0, 0x0, 232, -1, 129, 0, 1, 20 },
+  { 0x1, 0x1, 232, -1, 129, 6, 1, 20 },
+  { 0x0, 0x0, 232, -1, 261, 0, 0, -1 },
+  { 0x0, 0x0, 232, -1, 130, 0, 1, 21 },
+  { 0x0, 0x0, 232, -1, 265, 0, 0, -1 },
+  { 0x0, 0x0, 232, -1, 269, 0, 0, -1 },
+  { 0x0, 0x0, 232, -1, 131, 0, 1, 22 },
+  { 0x1, 0x1, 232, -1, 131, 6, 1, 22 },
+  { 0x0, 0x0, 232, -1, 273, 0, 0, -1 },
+  { 0x0, 0x0, 232, -1, 132, 0, 1, 23 },
+  { 0x1, 0x1, 232, -1, 316, 27, 1, 18 },
+  { 0x0, 0x0, 232, -1, 316, 0, 1, 18 },
+  { 0x0, 0x0, 232, -1, 317, 0, 1, 24 },
+  { 0x0, 0x1, 232, -1, 318, 20, 1, 69 },
+  { 0x0, 0x0, 232, -1, 318, 0, 1, 69 },
+  { 0x1, 0x1, 235, 731, -1, 29, 1, 0 },
+  { 0x0, 0x0, 235, -1, -1, 0, 1, 0 },
+  { 0x1, 0x1, 235, 732, -1, 27, 1, 0 },
+  { 0x0, 0x0, 256, -1, 547, 0, 0, -1 },
+  { 0x0, 0x0, 256, -1, 549, 0, 0, -1 },
+  { 0x1, 0x1, 256, -1, -1, 28, 1, 31 },
+  { 0x0, 0x0, 258, -1, -1, 0, 1, 0 },
+  { 0x0, 0x1, 258, -1, -1, 29, 1, 0 },
+  { 0x1, 0x1, 259, -1, -1, 12, 1, 4 },
+  { 0x1, 0x1, 259, -1, -1, 12, 1, 66 },
+  { 0x0, 0x0, 259, -1, 537, 0, 0, -1 },
+  { 0x0, 0x0, 259, -1, 539, 0, 0, -1 },
+  { 0x0, 0x0, 259, -1, 541, 0, 0, -1 },
+  { 0x0, 0x0, 259, -1, 543, 0, 0, -1 },
+  { 0x1, 0x1, 259, -1, -1, 12, 1, 61 },
+  { 0x1, 0x1, 259, -1, -1, 12, 1, 51 },
+  { 0x0, 0x0, 259, -1, 545, 0, 0, -1 },
+  { 0x0, 0x0, 260, -1, 544, 0, 0, -1 },
+  { 0x9, 0x9, 260, -1, 725, 33, 1, 51 },
+  { 0x0, 0x0, 260, -1, 561, 0, 0, -1 },
+  { 0x3, 0x3, 260, -1, -1, 27, 1, 51 },
+  { 0x0, 0x0, 264, -1, -1, 0, 1, 0 },
+  { 0x3, 0x3, 265, 733, -1, 27, 1, 0 },
+  { 0x1, 0x1, 266, -1, -1, 28, 1, 0 },
+  { 0x1, 0x1, 267, -1, -1, 27, 1, 95 },
+  { 0x0, 0x0, 267, -1, 229, 0, 0, -1 },
+  { 0x0, 0x0, 268, 738, 165, 0, 0, -1 },
+  { 0x0, 0x0, 268, 739, 167, 0, 0, -1 },
+  { 0x0, 0x0, 269, -1, 166, 0, 0, -1 },
+  { 0x0, 0x0, 269, -1, 168, 0, 0, -1 },
+  { 0x0, 0x0, 270, -1, -1, 0, 1, 42 },
+  { 0x0, 0x0, 275, -1, -1, 0, 1, 35 },
+  { 0x0, 0x0, 279, -1, 142, 0, 1, 31 },
+  { 0x0, 0x0, 280, -1, -1, 0, 1, 73 },
+  { 0x0, 0x0, 280, -1, 97, 0, 1, 3 },
+  { 0x0, 0x0, 280, -1, 99, 0, 0, -1 },
+};
+
+static const struct ia64_main_table
+main_table[] = {
+  { 5, 1, 1, 0x10000000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 5, 1, 1, 0x10008000000ull, 0x1eff8000000ull, { 23, 24, 25, 3, 0 }, 0x0, 0, },
+  { 5, 7, 1, 0x0ull, 0x0ull, { 23, 65, 25, 0, 0 }, 0x0, 0, },
+  { 6, 1, 1, 0x12000000000ull, 0x1e000000000ull, { 23, 65, 26, 0, 0 }, 0x0, 1, },
+  { 7, 1, 1, 0x10040000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 7, 1, 1, 0x10c00000000ull, 0x1ee00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 0, },
+  { 8, 1, 1, 0x10800000000ull, 0x1ee00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 1, },
+  { 9, 3, 1, 0x2c00000000ull, 0x1ee00000000ull, { 23, 2, 51, 52, 53 }, 0x221, 2, },
+  { 10, 1, 1, 0x10060000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 10, 1, 1, 0x10160000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 0, },
+  { 11, 1, 1, 0x10068000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 11, 1, 1, 0x10168000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 0, },
+  { 14, 4, 0, 0x100000000ull, 0x1eff80011ffull, { 15, 0, 0, 0, 0 }, 0x40, 3, },
+  { 14, 4, 0, 0x100000000ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x0, 136, },
+  { 14, 4, 0, 0x100000000ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x40, 137, },
+  { 14, 4, 0, 0x108000100ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x200, 514, },
+  { 14, 4, 0, 0x108000100ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x240, 515, },
+  { 14, 4, 1, 0x2000000000ull, 0x1ee00001000ull, { 14, 15, 0, 0, 0 }, 0x0, 114, },
+  { 14, 4, 1, 0x2000000000ull, 0x1ee00001000ull, { 14, 15, 0, 0, 0 }, 0x40, 115, },
+  { 14, 4, 0, 0x8000000000ull, 0x1ee000011ffull, { 80, 0, 0, 0, 0 }, 0x40, 4, },
+  { 14, 4, 0, 0x8000000000ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x0, 138, },
+  { 14, 4, 0, 0x8000000000ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x40, 139, },
+  { 14, 4, 0, 0x8000000080ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x210, 736, },
+  { 14, 4, 0, 0x8000000080ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x250, 737, },
+  { 14, 4, 0, 0x8000000140ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x30, 120, },
+  { 14, 4, 0, 0x8000000140ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x70, 121, },
+  { 14, 4, 0, 0x8000000180ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x230, 118, },
+  { 14, 4, 0, 0x8000000180ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x270, 119, },
+  { 14, 4, 1, 0xa000000000ull, 0x1ee00001000ull, { 14, 80, 0, 0, 0 }, 0x0, 116, },
+  { 14, 4, 1, 0xa000000000ull, 0x1ee00001000ull, { 14, 80, 0, 0, 0 }, 0x40, 117, },
+  { 15, 4, 0, 0x0ull, 0x1e1f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 108, },
+  { 15, 5, 0, 0x0ull, 0x1e3f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 224, },
+  { 15, 2, 0, 0x0ull, 0x1eff8000000ull, { 64, 0, 0, 0, 0 }, 0x2, 306, },
+  { 15, 3, 0, 0x0ull, 0x1eff8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 355, },
+  { 15, 6, 0, 0x0ull, 0x1eff8000000ull, { 68, 0, 0, 0, 0 }, 0x0, 740, },
+  { 15, 7, 0, 0x0ull, 0x0ull, { 64, 0, 0, 0, 0 }, 0x0, 5, },
+  { 16, 6, 0, 0x18000000000ull, 0x1ee000011ffull, { 81, 0, 0, 0, 0 }, 0x40, 4, },
+  { 16, 6, 0, 0x18000000000ull, 0x1ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x0, 138, },
+  { 16, 6, 0, 0x18000000000ull, 0x1ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x40, 139, },
+  { 16, 6, 1, 0x1a000000000ull, 0x1ee00001000ull, { 14, 81, 0, 0, 0 }, 0x0, 116, },
+  { 16, 6, 1, 0x1a000000000ull, 0x1ee00001000ull, { 14, 81, 0, 0, 0 }, 0x40, 117, },
+  { 17, 4, 0, 0x4080000000ull, 0x1e9f8000018ull, { 15, 76, 0, 0, 0 }, 0x20, 202, },
+  { 17, 4, 0, 0xe000000000ull, 0x1e800000018ull, { 80, 76, 0, 0, 0 }, 0x20, 203, },
+  { 18, 4, 0, 0x60000000ull, 0x1e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x2c, 75, },
+  { 22, 2, 0, 0x200000000ull, 0x1ee00000000ull, { 24, 79, 0, 0, 0 }, 0x0, 519, },
+  { 22, 3, 0, 0x800000000ull, 0x1ee00000000ull, { 23, 80, 0, 0, 0 }, 0x0, 77, },
+  { 22, 3, 0, 0xc00000000ull, 0x1ee00000000ull, { 17, 80, 0, 0, 0 }, 0x0, 77, },
+  { 22, 3, 0, 0x2200000000ull, 0x1ee00000000ull, { 24, 79, 0, 0, 0 }, 0x0, 520, },
+  { 22, 3, 0, 0x2600000000ull, 0x1ee00000000ull, { 18, 79, 0, 0, 0 }, 0x0, 521, },
+  { 22, 7, 0, 0x0ull, 0x0ull, { 24, 79, 0, 0, 0 }, 0x0, 522, },
+  { 25, 4, 0, 0x20000000ull, 0x1e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x224, 6, },
+  { 26, 1, 2, 0x18000000000ull, 0x1fe00001000ull, { 21, 22, 24, 25, 0 }, 0x0, 208, },
+  { 26, 1, 2, 0x18000000000ull, 0x1fe00001000ull, { 22, 21, 25, 24, 0 }, 0x0, 329, },
+  { 26, 1, 2, 0x18000000000ull, 0x1fe00001000ull, { 21, 22, 25, 24, 0 }, 0x0, 291, },
+  { 26, 1, 2, 0x18000000000ull, 0x1fe00001000ull, { 22, 21, 24, 25, 0 }, 0x0, 282, },
+  { 26, 1, 2, 0x18200000000ull, 0x1fe00001000ull, { 21, 22, 24, 25, 0 }, 0x40, 209, },
+  { 26, 1, 2, 0x19000000000ull, 0x1fe00001000ull, { 21, 22, 6, 25, 0 }, 0x0, 283, },
+  { 26, 1, 2, 0x19000000000ull, 0x1fe00001000ull, { 21, 22, 6, 25, 0 }, 0x40, 284, },
+  { 26, 1, 2, 0x18800000000ull, 0x1ee00001000ull, { 21, 22, 54, 25, 0 }, 0x0, 208, },
+  { 26, 1, 2, 0x18800000000ull, 0x1ee00001000ull, { 21, 22, 56, 25, 0 }, 0x0, 332, },
+  { 26, 1, 2, 0x18800000000ull, 0x1ee00001000ull, { 22, 21, 56, 25, 0 }, 0x0, 294, },
+  { 26, 1, 2, 0x18800000000ull, 0x1ee00001000ull, { 22, 21, 54, 25, 0 }, 0x0, 282, },
+  { 26, 1, 2, 0x18a00000000ull, 0x1ee00001000ull, { 21, 22, 54, 25, 0 }, 0x40, 209, },
+  { 26, 1, 2, 0x1a800000000ull, 0x1ee00001000ull, { 21, 22, 58, 25, 0 }, 0x0, 339, },
+  { 26, 1, 2, 0x1a800000000ull, 0x1ee00001000ull, { 22, 21, 58, 25, 0 }, 0x0, 300, },
+  { 26, 1, 2, 0x1c200000000ull, 0x1fe00001000ull, { 22, 21, 24, 25, 0 }, 0x40, 210, },
+  { 26, 1, 2, 0x1d000000000ull, 0x1fe00001000ull, { 22, 21, 6, 25, 0 }, 0x40, 285, },
+  { 26, 1, 2, 0x1ca00000000ull, 0x1ee00001000ull, { 22, 21, 54, 25, 0 }, 0x40, 210, },
+  { 27, 1, 2, 0x18400000000ull, 0x1fe00001000ull, { 21, 22, 24, 25, 0 }, 0x0, 208, },
+  { 27, 1, 2, 0x18400000000ull, 0x1fe00001000ull, { 22, 21, 25, 24, 0 }, 0x0, 329, },
+  { 27, 1, 2, 0x18400000000ull, 0x1fe00001000ull, { 21, 22, 25, 24, 0 }, 0x0, 291, },
+  { 27, 1, 2, 0x18400000000ull, 0x1fe00001000ull, { 22, 21, 24, 25, 0 }, 0x0, 282, },
+  { 27, 1, 2, 0x18600000000ull, 0x1fe00001000ull, { 21, 22, 24, 25, 0 }, 0x40, 209, },
+  { 27, 1, 2, 0x19400000000ull, 0x1fe00001000ull, { 21, 22, 6, 25, 0 }, 0x0, 283, },
+  { 27, 1, 2, 0x19400000000ull, 0x1fe00001000ull, { 21, 22, 6, 25, 0 }, 0x40, 284, },
+  { 27, 1, 2, 0x18c00000000ull, 0x1ee00001000ull, { 21, 22, 54, 25, 0 }, 0x0, 211, },
+  { 27, 1, 2, 0x18c00000000ull, 0x1ee00001000ull, { 21, 22, 56, 25, 0 }, 0x0, 332, },
+  { 27, 1, 2, 0x18c00000000ull, 0x1ee00001000ull, { 22, 21, 56, 25, 0 }, 0x0, 294, },
+  { 27, 1, 2, 0x18c00000000ull, 0x1ee00001000ull, { 22, 21, 54, 25, 0 }, 0x0, 286, },
+  { 27, 1, 2, 0x18e00000000ull, 0x1ee00001000ull, { 21, 22, 54, 25, 0 }, 0x40, 209, },
+  { 27, 1, 2, 0x1ac00000000ull, 0x1ee00001000ull, { 21, 22, 55, 25, 0 }, 0x0, 352, },
+  { 27, 1, 2, 0x1ac00000000ull, 0x1ee00001000ull, { 21, 22, 57, 25, 0 }, 0x0, 339, },
+  { 27, 1, 2, 0x1ac00000000ull, 0x1ee00001000ull, { 22, 21, 57, 25, 0 }, 0x0, 300, },
+  { 27, 1, 2, 0x1ac00000000ull, 0x1ee00001000ull, { 22, 21, 55, 25, 0 }, 0x0, 290, },
+  { 27, 1, 2, 0x1c600000000ull, 0x1fe00001000ull, { 22, 21, 24, 25, 0 }, 0x40, 210, },
+  { 27, 1, 2, 0x1d400000000ull, 0x1fe00001000ull, { 22, 21, 6, 25, 0 }, 0x40, 285, },
+  { 27, 1, 2, 0x1ce00000000ull, 0x1ee00001000ull, { 22, 21, 54, 25, 0 }, 0x40, 210, },
+  { 28, 3, 1, 0x8008000000ull, 0x1fff8000000ull, { 23, 32, 24, 1, 0 }, 0x0, 82, },
+  { 29, 3, 1, 0x8048000000ull, 0x1fff8000000ull, { 23, 32, 24, 1, 0 }, 0x0, 82, },
+  { 30, 3, 1, 0x8088000000ull, 0x1fff8000000ull, { 23, 32, 24, 1, 0 }, 0x0, 82, },
+  { 31, 3, 1, 0x80c8000000ull, 0x1fff8000000ull, { 23, 32, 24, 1, 0 }, 0x0, 82, },
+  { 33, 4, 0, 0x10000000ull, 0x1e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x224, 7, },
+  { 35, 2, 1, 0xc0000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 321, },
+  { 36, 2, 1, 0xc8000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 321, },
+  { 38, 2, 1, 0x8000000000ull, 0x1e000000000ull, { 23, 24, 25, 46, 71 }, 0x0, 8, },
+  { 38, 2, 1, 0xa600000000ull, 0x1ee04000000ull, { 23, 24, 44, 72, 0 }, 0x0, 743, },
+  { 38, 2, 1, 0xa604000000ull, 0x1ee04000000ull, { 23, 54, 44, 72, 0 }, 0x0, 743, },
+  { 38, 2, 1, 0xae00000000ull, 0x1ee00000000ull, { 23, 47, 25, 45, 72 }, 0x0, 8, },
+  { 42, 4, 0, 0x80000000ull, 0x1e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x20, 9, },
+  { 47, 2, 1, 0xa400000000ull, 0x1ee00002000ull, { 23, 25, 75, 72, 0 }, 0x0, 10, },
+  { 49, 5, 1, 0x80000000ull, 0x1e3f80fe000ull, { 17, 19, 0, 0, 0 }, 0x40, 11, },
+  { 50, 5, 1, 0x10008000000ull, 0x1fff8000000ull, { 17, 19, 18, 0, 0 }, 0x40, 12, },
+  { 51, 5, 1, 0xb8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 533, },
+  { 51, 5, 1, 0xb8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 13, },
+  { 52, 5, 1, 0xb0000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 533, },
+  { 52, 5, 1, 0xb0000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 13, },
+  { 53, 5, 1, 0x160000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 11, },
+  { 54, 5, 1, 0x168000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 11, },
+  { 56, 3, 0, 0x2180000000ull, 0x1eff8000000ull, { 25, 0, 0, 0, 0 }, 0x0, 14, },
+  { 57, 5, 0, 0x40000000ull, 0x1eff8000000ull, { 78, 0, 0, 0, 0 }, 0x0, 535, },
+  { 57, 5, 0, 0x40000000ull, 0x1eff8000000ull, { 78, 0, 0, 0, 0 }, 0x40, 15, },
+  { 58, 5, 2, 0xa000000000ull, 0x1e000001000ull, { 21, 22, 18, 59, 0 }, 0x0, 357, },
+  { 58, 5, 2, 0xa000000000ull, 0x1e000001000ull, { 22, 21, 18, 59, 0 }, 0x40, 428, },
+  { 59, 5, 0, 0x28000000ull, 0x1eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 536, },
+  { 59, 5, 0, 0x28000000ull, 0x1eff8000000ull, { 0, 0, 0, 0, 0 }, 0x40, 16, },
+  { 60, 5, 2, 0x8000000000ull, 0x1fe00001000ull, { 21, 22, 18, 19, 0 }, 0x0, 212, },
+  { 60, 5, 2, 0x8000000000ull, 0x1fe00001000ull, { 21, 22, 18, 19, 0 }, 0x40, 213, },
+  { 60, 5, 2, 0x9000000000ull, 0x1fe00001000ull, { 21, 22, 19, 18, 0 }, 0x0, 287, },
+  { 60, 5, 2, 0x9000000000ull, 0x1fe00001000ull, { 21, 22, 19, 18, 0 }, 0x40, 288, },
+  { 60, 5, 2, 0x8000000000ull, 0x1fe00001000ull, { 22, 21, 18, 19, 0 }, 0x0, 411, },
+  { 60, 5, 2, 0x8000000000ull, 0x1fe00001000ull, { 22, 21, 18, 19, 0 }, 0x40, 412, },
+  { 60, 5, 2, 0x9000000000ull, 0x1fe00001000ull, { 22, 21, 19, 18, 0 }, 0x0, 415, },
+  { 60, 5, 2, 0x9000000000ull, 0x1fe00001000ull, { 22, 21, 19, 18, 0 }, 0x40, 416, },
+  { 61, 5, 1, 0xc0000000ull, 0x1eff8000000ull, { 17, 18, 0, 0, 0 }, 0x0, 276, },
+  { 61, 5, 1, 0xc0000000ull, 0x1eff8000000ull, { 17, 18, 0, 0, 0 }, 0x40, 277, },
+  { 61, 5, 1, 0xe0000000ull, 0x1e3f8000000ull, { 17, 18, 0, 0, 0 }, 0x0, 741, },
+  { 61, 5, 1, 0x10008000000ull, 0x1fff80fe000ull, { 17, 19, 0, 0, 0 }, 0x40, 742, },
+  { 62, 3, 1, 0x8488000000ull, 0x1fff8000000ull, { 23, 32, 70, 0, 0 }, 0x0, 83, },
+  { 63, 3, 1, 0x84c8000000ull, 0x1fff8000000ull, { 23, 32, 70, 0, 0 }, 0x0, 83, },
+  { 66, 3, 0, 0x60000000ull, 0x1eff8000000ull, { 0, 0, 0, 0, 0 }, 0x21, 17, },
+  { 67, 5, 1, 0x10000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 143, },
+  { 67, 5, 1, 0x10000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 18, },
+  { 68, 5, 1, 0xa8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 533, },
+  { 68, 5, 1, 0xa8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 13, },
+  { 69, 5, 1, 0x80000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 430, },
+  { 70, 5, 1, 0xa0000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 533, },
+  { 70, 5, 1, 0xa0000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 13, },
+  { 71, 5, 1, 0x1c8000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 322, },
+  { 72, 5, 1, 0x10000000000ull, 0x1fc000fe000ull, { 17, 19, 20, 0, 0 }, 0x40, 12, },
+  { 73, 5, 1, 0x14000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 145, },
+  { 73, 5, 1, 0x14000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 19, },
+  { 74, 5, 1, 0x88000000ull, 0x1e3f8000000ull, { 17, 19, 0, 0, 0 }, 0xc0, 11, },
+  { 75, 5, 1, 0x88000000ull, 0x1e3f80fe000ull, { 17, 19, 0, 0, 0 }, 0x40, 11, },
+  { 76, 5, 1, 0x18000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 145, },
+  { 76, 5, 1, 0x18000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 19, },
+  { 77, 5, 1, 0x18000000000ull, 0x1fc000fe000ull, { 17, 19, 20, 0, 0 }, 0x40, 12, },
+  { 78, 5, 1, 0x10008000000ull, 0x1fff80fe000ull, { 17, 19, 0, 0, 0 }, 0x40, 12, },
+  { 79, 5, 1, 0x170000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 11, },
+  { 80, 5, 1, 0x2080000000ull, 0x1e3f80fe000ull, { 17, 19, 0, 0, 0 }, 0x40, 11, },
+  { 81, 5, 1, 0x140000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 11, },
+  { 82, 5, 1, 0x20b8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 533, },
+  { 82, 5, 1, 0x20b8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 13, },
+  { 83, 5, 1, 0x20b0000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 533, },
+  { 83, 5, 1, 0x20b0000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 13, },
+  { 84, 5, 1, 0x2180000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 214, },
+  { 84, 5, 1, 0x2180000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 215, },
+  { 85, 5, 1, 0x20c0000000ull, 0x1eff8000000ull, { 17, 18, 0, 0, 0 }, 0x0, 276, },
+  { 85, 5, 1, 0x20c0000000ull, 0x1eff8000000ull, { 17, 18, 0, 0, 0 }, 0x40, 277, },
+  { 86, 5, 1, 0x13000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 533, },
+  { 86, 5, 1, 0x13000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 13, },
+  { 87, 5, 1, 0x20a8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 533, },
+  { 87, 5, 1, 0x20a8000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 13, },
+  { 88, 5, 1, 0x2080000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 430, },
+  { 89, 5, 1, 0x20a0000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 533, },
+  { 89, 5, 1, 0x20a0000000ull, 0x1eff8000000ull, { 17, 18, 19, 0, 0 }, 0x40, 13, },
+  { 90, 5, 1, 0x13000000000ull, 0x1fc000fe000ull, { 17, 19, 20, 0, 0 }, 0x40, 20, },
+  { 91, 5, 1, 0x17000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 533, },
+  { 91, 5, 1, 0x17000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 13, },
+  { 92, 5, 1, 0x2088000000ull, 0x1e3f8000000ull, { 17, 19, 0, 0, 0 }, 0xc0, 11, },
+  { 93, 5, 1, 0x2088000000ull, 0x1e3f80fe000ull, { 17, 19, 0, 0, 0 }, 0x40, 11, },
+  { 94, 5, 1, 0x1b000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 533, },
+  { 94, 5, 1, 0x1b000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 13, },
+  { 95, 5, 1, 0x1b000000000ull, 0x1fc000fe000ull, { 17, 19, 20, 0, 0 }, 0x40, 20, },
+  { 96, 5, 2, 0x2200000000ull, 0x1fe00000000ull, { 17, 22, 18, 19, 0 }, 0x0, 562, },
+  { 96, 5, 2, 0x2200000000ull, 0x1fe00000000ull, { 17, 22, 18, 19, 0 }, 0x40, 21, },
+  { 97, 5, 2, 0x3200000000ull, 0x1fe00000000ull, { 17, 22, 19, 0, 0 }, 0x0, 562, },
+  { 97, 5, 2, 0x3200000000ull, 0x1fe00000000ull, { 17, 22, 19, 0, 0 }, 0x40, 21, },
+  { 98, 5, 2, 0x200000000ull, 0x1fe00000000ull, { 17, 22, 18, 19, 0 }, 0x0, 562, },
+  { 98, 5, 2, 0x200000000ull, 0x1fe00000000ull, { 17, 22, 18, 19, 0 }, 0x40, 21, },
+  { 99, 5, 2, 0x1200000000ull, 0x1fe00000000ull, { 17, 22, 19, 0, 0 }, 0x0, 562, },
+  { 99, 5, 2, 0x1200000000ull, 0x1fe00000000ull, { 17, 22, 19, 0, 0 }, 0x40, 21, },
+  { 100, 5, 1, 0x1c000000000ull, 0x1f000000000ull, { 17, 19, 20, 18, 0 }, 0x0, 11, },
+  { 101, 5, 0, 0x20000000ull, 0x1eff8000000ull, { 49, 50, 0, 0, 0 }, 0x0, 563, },
+  { 101, 5, 0, 0x20000000ull, 0x1eff8000000ull, { 49, 50, 0, 0, 0 }, 0x40, 22, },
+  { 102, 5, 1, 0x14008000000ull, 0x1fff8000000ull, { 17, 19, 18, 0, 0 }, 0x40, 12, },
+  { 103, 5, 1, 0x1a0000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 23, },
+  { 104, 5, 1, 0x1e0000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 323, },
+  { 105, 3, 0, 0x100000000ull, 0x1eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 16, },
+  { 107, 5, 1, 0x178000000ull, 0x1e3f8000000ull, { 17, 18, 19, 0, 0 }, 0x0, 11, },
+  { 112, 3, 1, 0x8708000000ull, 0x1ffc8000000ull, { 23, 18, 0, 0, 0 }, 0x0, 147, },
+  { 121, 3, 0, 0x80000000ull, 0x1eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 24, },
+  { 121, 3, 0, 0x90000000ull, 0x1eff8000000ull, { 23, 0, 0, 0, 0 }, 0x0, 206, },
+  { 121, 3, 0, 0x98000000ull, 0x1eff8000000ull, { 17, 0, 0, 0, 0 }, 0x0, 206, },
+  { 122, 3, 0, 0x2170000000ull, 0x1eff8000000ull, { 24, 0, 0, 0, 0 }, 0xc, 148, },
+  { 123, 3, 1, 0x2070000000ull, 0x1eff8000000ull, { 29, 24, 0, 0, 0 }, 0x8, 149, },
+  { 123, 3, 1, 0x2078000000ull, 0x1eff8000000ull, { 30, 24, 0, 0, 0 }, 0x8, 309, },
+  { 125, 3, 1, 0x8000000000ull, 0x1fff8000000ull, { 23, 32, 0, 0, 0 }, 0x0, 25, },
+  { 125, 3, 1, 0x9000000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 25, },
+  { 125, 3, 1, 0xa000000000ull, 0x1eff0000000ull, { 23, 32, 61, 0, 0 }, 0x0, 25, },
+  { 126, 3, 1, 0x8040000000ull, 0x1fff8000000ull, { 23, 32, 0, 0, 0 }, 0x0, 25, },
+  { 126, 3, 1, 0x9040000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 25, },
+  { 126, 3, 1, 0xa040000000ull, 0x1eff0000000ull, { 23, 32, 61, 0, 0 }, 0x0, 25, },
+  { 127, 3, 1, 0x8080000000ull, 0x1fff8000000ull, { 23, 32, 0, 0, 0 }, 0x0, 25, },
+  { 127, 3, 1, 0x9080000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 25, },
+  { 127, 3, 1, 0xa080000000ull, 0x1eff0000000ull, { 23, 32, 61, 0, 0 }, 0x0, 25, },
+  { 128, 3, 1, 0x80c0000000ull, 0x1fff8000000ull, { 23, 32, 0, 0, 0 }, 0x0, 26, },
+  { 128, 3, 1, 0x90c0000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 26, },
+  { 128, 3, 1, 0xa0c0000000ull, 0x1eff0000000ull, { 23, 32, 61, 0, 0 }, 0x0, 26, },
+  { 129, 3, 1, 0xc6c0000000ull, 0x1fff8000000ull, { 17, 32, 0, 0, 0 }, 0x0, 275, },
+  { 129, 3, 1, 0xd6c0000000ull, 0x1fff8000000ull, { 17, 32, 24, 0, 0 }, 0x0, 275, },
+  { 129, 3, 1, 0xe6c0000000ull, 0x1eff0000000ull, { 17, 32, 61, 0, 0 }, 0x0, 275, },
+  { 130, 3, 1, 0xc040000000ull, 0x1fff8000000ull, { 17, 32, 0, 0, 0 }, 0x0, 27, },
+  { 130, 3, 1, 0xd040000000ull, 0x1fff8000000ull, { 17, 32, 24, 0, 0 }, 0x0, 27, },
+  { 130, 3, 1, 0xe040000000ull, 0x1eff0000000ull, { 17, 32, 61, 0, 0 }, 0x0, 27, },
+  { 131, 3, 1, 0xc0c0000000ull, 0x1fff8000000ull, { 17, 32, 0, 0, 0 }, 0x0, 27, },
+  { 131, 3, 1, 0xd0c0000000ull, 0x1fff8000000ull, { 17, 32, 24, 0, 0 }, 0x0, 27, },
+  { 131, 3, 1, 0xe0c0000000ull, 0x1eff0000000ull, { 17, 32, 61, 0, 0 }, 0x0, 27, },
+  { 132, 3, 1, 0xc000000000ull, 0x1fff8000000ull, { 17, 32, 0, 0, 0 }, 0x0, 27, },
+  { 132, 3, 1, 0xd000000000ull, 0x1fff8000000ull, { 17, 32, 24, 0, 0 }, 0x0, 27, },
+  { 132, 3, 1, 0xe000000000ull, 0x1eff0000000ull, { 17, 32, 61, 0, 0 }, 0x0, 27, },
+  { 133, 3, 2, 0xc048000000ull, 0x1fff8000000ull, { 17, 18, 32, 0, 0 }, 0x0, 27, },
+  { 133, 3, 2, 0xd048000000ull, 0x1fff8000000ull, { 17, 18, 32, 5, 0 }, 0x0, 27, },
+  { 134, 3, 2, 0xc0c8000000ull, 0x1fff8000000ull, { 17, 18, 32, 0, 0 }, 0x0, 27, },
+  { 134, 3, 2, 0xd0c8000000ull, 0x1fff8000000ull, { 17, 18, 32, 5, 0 }, 0x0, 27, },
+  { 135, 3, 2, 0xc088000000ull, 0x1fff8000000ull, { 17, 18, 32, 0, 0 }, 0x0, 27, },
+  { 135, 3, 2, 0xd088000000ull, 0x1fff8000000ull, { 17, 18, 32, 4, 0 }, 0x0, 27, },
+  { 136, 3, 1, 0xc080000000ull, 0x1fff8000000ull, { 17, 32, 0, 0, 0 }, 0x0, 27, },
+  { 136, 3, 1, 0xd080000000ull, 0x1fff8000000ull, { 17, 32, 24, 0, 0 }, 0x0, 27, },
+  { 136, 3, 1, 0xe080000000ull, 0x1eff0000000ull, { 17, 32, 61, 0, 0 }, 0x0, 27, },
+  { 139, 3, 0, 0xcb00000000ull, 0x1fff8000000ull, { 32, 0, 0, 0, 0 }, 0x0, 28, },
+  { 139, 3, 0, 0xdb00000000ull, 0x1fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 29, },
+  { 139, 3, 0, 0xeb00000000ull, 0x1eff0000000ull, { 32, 61, 0, 0, 0 }, 0x0, 29, },
+  { 140, 3, 0, 0x50000000ull, 0x1eff8000000ull, { 0, 0, 0, 0, 0 }, 0x21, 30, },
+  { 148, 3, 0, 0x110000000ull, 0x1eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 31, },
+  { 149, 2, 1, 0xe880000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 324, },
+  { 150, 2, 1, 0xea80000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 324, },
+  { 151, 2, 1, 0xf880000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 324, },
+  { 152, 1, 1, 0x10800000000ull, 0x1fff80fe000ull, { 23, 25, 0, 0, 0 }, 0x0, 1, },
+  { 152, 1, 1, 0x10800000000ull, 0x1ee07f00000ull, { 23, 62, 0, 0, 0 }, 0x40, 1, },
+  { 152, 1, 1, 0x12000000000ull, 0x1e000300000ull, { 23, 65, 0, 0, 0 }, 0x40, 32, },
+  { 152, 5, 1, 0x80000000ull, 0x1e3f8000000ull, { 17, 19, 0, 0, 0 }, 0xc0, 11, },
+  { 152, 2, 1, 0xe00100000ull, 0x1ee00f00000ull, { 14, 24, 0, 0, 0 }, 0x40, 33, },
+  { 152, 2, 1, 0xe00000000ull, 0x1ee00f00000ull, { 14, 24, 77, 0, 0 }, 0x0, 34, },
+  { 152, 2, 1, 0x188000000ull, 0x1eff8000000ull, { 23, 15, 0, 0, 0 }, 0x0, 35, },
+  { 152, 2, 1, 0x600000000ull, 0x1ee00000000ull, { 8, 24, 63, 0, 0 }, 0x0, 36, },
+  { 152, 2, 1, 0x400000000ull, 0x1ee00000000ull, { 9, 67, 0, 0, 0 }, 0x0, 37, },
+  { 152, 2, 1, 0x180000000ull, 0x1eff8000000ull, { 23, 7, 0, 0, 0 }, 0x0, 8, },
+  { 152, 2, 1, 0x198000000ull, 0x1eff8000000ull, { 23, 8, 0, 0, 0 }, 0x0, 38, },
+  { 152, 2, 1, 0x150000000ull, 0x1eff8000000ull, { 13, 24, 0, 0, 0 }, 0x0, 310, },
+  { 152, 2, 1, 0x50000000ull, 0x1eff8000000ull, { 13, 54, 0, 0, 0 }, 0x0, 310, },
+  { 152, 2, 1, 0x190000000ull, 0x1eff8000000ull, { 23, 13, 0, 0, 0 }, 0x0, 311, },
+  { 152, 3, 1, 0x140000000ull, 0x1eff8000000ull, { 13, 54, 0, 0, 0 }, 0x0, 358, },
+  { 152, 3, 1, 0x2150000000ull, 0x1eff8000000ull, { 13, 24, 0, 0, 0 }, 0x0, 358, },
+  { 152, 3, 1, 0x2110000000ull, 0x1eff8000000ull, { 23, 13, 0, 0, 0 }, 0x0, 359, },
+  { 152, 3, 1, 0x2160000000ull, 0x1eff8000000ull, { 16, 24, 0, 0, 0 }, 0x8, 39, },
+  { 152, 3, 1, 0x2120000000ull, 0x1eff8000000ull, { 23, 16, 0, 0, 0 }, 0x8, 40, },
+  { 152, 3, 1, 0x2168000000ull, 0x1eff8000000ull, { 11, 24, 0, 0, 0 }, 0x8, 41, },
+  { 152, 3, 1, 0x2148000000ull, 0x1eff8000000ull, { 12, 24, 0, 0, 0 }, 0x0, 42, },
+  { 152, 3, 1, 0x2128000000ull, 0x1eff8000000ull, { 23, 10, 0, 0, 0 }, 0x8, 43, },
+  { 152, 3, 1, 0x2108000000ull, 0x1eff8000000ull, { 23, 12, 0, 0, 0 }, 0x0, 44, },
+  { 152, 3, 1, 0x2000000000ull, 0x1eff8000000ull, { 37, 24, 0, 0, 0 }, 0x8, 45, },
+  { 152, 3, 1, 0x2008000000ull, 0x1eff8000000ull, { 28, 24, 0, 0, 0 }, 0x8, 46, },
+  { 152, 3, 1, 0x2010000000ull, 0x1eff8000000ull, { 31, 24, 0, 0, 0 }, 0x8, 47, },
+  { 152, 3, 1, 0x2018000000ull, 0x1eff8000000ull, { 34, 24, 0, 0, 0 }, 0x8, 48, },
+  { 152, 3, 1, 0x2020000000ull, 0x1eff8000000ull, { 35, 24, 0, 0, 0 }, 0x8, 49, },
+  { 152, 3, 1, 0x2028000000ull, 0x1eff8000000ull, { 36, 24, 0, 0, 0 }, 0x8, 50, },
+  { 152, 3, 1, 0x2030000000ull, 0x1eff8000000ull, { 33, 24, 0, 0, 0 }, 0x8, 51, },
+  { 152, 3, 1, 0x2080000000ull, 0x1eff8000000ull, { 23, 37, 0, 0, 0 }, 0x8, 52, },
+  { 152, 3, 1, 0x2088000000ull, 0x1eff8000000ull, { 23, 28, 0, 0, 0 }, 0x8, 53, },
+  { 152, 3, 1, 0x2090000000ull, 0x1eff8000000ull, { 23, 31, 0, 0, 0 }, 0x8, 54, },
+  { 152, 3, 1, 0x2098000000ull, 0x1eff8000000ull, { 23, 34, 0, 0, 0 }, 0x8, 55, },
+  { 152, 3, 1, 0x20a0000000ull, 0x1eff8000000ull, { 23, 35, 0, 0, 0 }, 0x8, 56, },
+  { 152, 3, 1, 0x20a8000000ull, 0x1eff8000000ull, { 23, 36, 0, 0, 0 }, 0x0, 57, },
+  { 152, 3, 1, 0x20b0000000ull, 0x1eff8000000ull, { 23, 33, 0, 0, 0 }, 0x8, 58, },
+  { 152, 3, 1, 0x20b8000000ull, 0x1eff8000000ull, { 23, 27, 0, 0, 0 }, 0x0, 59, },
+  { 152, 7, 1, 0x0ull, 0x0ull, { 23, 13, 0, 0, 0 }, 0x0, 60, },
+  { 152, 7, 1, 0x0ull, 0x0ull, { 13, 54, 0, 0, 0 }, 0x0, 60, },
+  { 152, 7, 1, 0x0ull, 0x0ull, { 13, 24, 0, 0, 0 }, 0x0, 60, },
+  { 153, 6, 1, 0xc000000000ull, 0x1e000100000ull, { 23, 69, 0, 0, 0 }, 0x0, 8, },
+  { 154, 2, 1, 0xeca0000000ull, 0x1fff0000000ull, { 23, 24, 73, 0, 0 }, 0x0, 0, },
+  { 155, 2, 1, 0xeea0000000ull, 0x1fff0000000ull, { 23, 24, 74, 0, 0 }, 0x0, 0, },
+  { 165, 4, 0, 0x4000000000ull, 0x1e1f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 108, },
+  { 165, 5, 0, 0x8000000ull, 0x1e3f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 224, },
+  { 165, 2, 0, 0x8000000ull, 0x1eff8000000ull, { 64, 0, 0, 0, 0 }, 0x2, 306, },
+  { 165, 3, 0, 0x8000000ull, 0x1eff8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 355, },
+  { 165, 6, 0, 0x8000000ull, 0x1eff8000000ull, { 68, 0, 0, 0, 0 }, 0x0, 740, },
+  { 165, 7, 0, 0x0ull, 0x0ull, { 64, 0, 0, 0, 0 }, 0x0, 5, },
+  { 172, 1, 1, 0x10070000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 172, 1, 1, 0x10170000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 0, },
+  { 175, 2, 1, 0xea00000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 710, },
+  { 176, 2, 1, 0xf820000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 711, },
+  { 177, 1, 1, 0x10400000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 61, },
+  { 178, 1, 1, 0x10600000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 61, },
+  { 179, 1, 1, 0x11400000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 180, 1, 1, 0x10450000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 62, },
+  { 181, 1, 1, 0x10650000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 62, },
+  { 182, 1, 1, 0x10470000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 183, 1, 1, 0x10670000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 184, 1, 1, 0x10520000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 216, },
+  { 185, 1, 1, 0x10720000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 216, },
+  { 186, 1, 1, 0x11520000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 216, },
+  { 187, 2, 1, 0xe850000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 716, },
+  { 188, 2, 1, 0xea70000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 189, 2, 1, 0xe810000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 716, },
+  { 190, 2, 1, 0xea30000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 191, 2, 1, 0xead0000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 324, },
+  { 192, 2, 1, 0xe230000000ull, 0x1ff30000000ull, { 23, 24, 25, 41, 0 }, 0x0, 63, },
+  { 193, 2, 1, 0xe690000000ull, 0x1fff0000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, },
+  { 195, 3, 1, 0x21c0000000ull, 0x1eff8000000ull, { 23, 25, 24, 0, 0 }, 0x0, 507, },
+  { 195, 3, 1, 0x20c0000000ull, 0x1eff8000000ull, { 23, 25, 48, 0, 0 }, 0x0, 507, },
+  { 195, 3, 0, 0x2188000000ull, 0x1eff8000000ull, { 25, 48, 0, 0, 0 }, 0x0, 508, },
+  { 196, 2, 1, 0xe8b0000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 197, 2, 1, 0xe240000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 197, 2, 1, 0xee50000000ull, 0x1fff0000000ull, { 23, 24, 38, 0, 0 }, 0x0, 0, },
+  { 198, 2, 1, 0xf040000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 198, 2, 1, 0xfc50000000ull, 0x1fff0000000ull, { 23, 24, 38, 0, 0 }, 0x0, 0, },
+  { 199, 1, 1, 0x10680000000ull, 0x1ffe0000000ull, { 23, 24, 40, 25, 0 }, 0x0, 0, },
+  { 200, 2, 1, 0xe220000000ull, 0x1fff0000000ull, { 23, 25, 24, 0, 0 }, 0x0, 63, },
+  { 200, 2, 1, 0xe630000000ull, 0x1fff0000000ull, { 23, 25, 42, 0, 0 }, 0x0, 63, },
+  { 201, 2, 1, 0xf020000000ull, 0x1fff0000000ull, { 23, 25, 24, 0, 0 }, 0x0, 63, },
+  { 201, 2, 1, 0xf430000000ull, 0x1fff0000000ull, { 23, 25, 42, 0, 0 }, 0x0, 63, },
+  { 202, 1, 1, 0x106c0000000ull, 0x1ffe0000000ull, { 23, 24, 40, 25, 0 }, 0x0, 0, },
+  { 203, 1, 1, 0x10420000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 61, },
+  { 204, 1, 1, 0x10620000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 61, },
+  { 205, 1, 1, 0x11420000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 206, 3, 0, 0x2048000000ull, 0x1eff8000000ull, { 25, 24, 0, 0, 0 }, 0x8, 325, },
+  { 206, 3, 0, 0x2050000000ull, 0x1eff8000000ull, { 25, 24, 0, 0, 0 }, 0xc, 280, },
+  { 206, 3, 0, 0x21a0000000ull, 0x1eff8000000ull, { 25, 0, 0, 0, 0 }, 0x8, 207, },
+  { 207, 3, 0, 0x2060000000ull, 0x1eff8000000ull, { 25, 24, 0, 0, 0 }, 0x8, 150, },
+  { 212, 4, 0, 0x40000000ull, 0x1e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x22c, 64, },
+  { 213, 3, 0, 0x38000000ull, 0x1ee78000000ull, { 66, 0, 0, 0, 0 }, 0x8, 65, },
+  { 214, 3, 0, 0x28000000ull, 0x1ee78000000ull, { 66, 0, 0, 0, 0 }, 0x0, 66, },
+  { 223, 3, 1, 0xc708000000ull, 0x1ffc8000000ull, { 17, 24, 0, 0, 0 }, 0x0, 151, },
+  { 224, 2, 1, 0xa600000000ull, 0x1ee04000000ull, { 23, 24, 44, 0, 0 }, 0x140, 0, },
+  { 224, 2, 1, 0xf240000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 225, 1, 1, 0x10080000000ull, 0x1efe0000000ull, { 23, 24, 39, 25, 0 }, 0x0, 0, },
+  { 226, 1, 1, 0x100c0000000ull, 0x1efe0000000ull, { 23, 24, 39, 25, 0 }, 0x0, 0, },
+  { 227, 2, 1, 0xa400000000ull, 0x1ee00002000ull, { 23, 25, 75, 0, 0 }, 0x140, 10, },
+  { 227, 2, 1, 0xf220000000ull, 0x1fff0000000ull, { 23, 25, 24, 0, 0 }, 0x0, 63, },
+  { 228, 2, 1, 0xac00000000ull, 0x1ee00000000ull, { 23, 24, 25, 43, 0 }, 0x0, 0, },
+  { 233, 3, 0, 0x180000000ull, 0x1eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 152, },
+  { 234, 3, 0, 0x30000000ull, 0x1ee78000000ull, { 66, 0, 0, 0, 0 }, 0x8, 65, },
+  { 236, 3, 1, 0x8c00000000ull, 0x1fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 67, },
+  { 236, 3, 1, 0xac00000000ull, 0x1eff0000000ull, { 32, 24, 60, 0, 0 }, 0x0, 67, },
+  { 237, 3, 1, 0x8c40000000ull, 0x1fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 67, },
+  { 237, 3, 1, 0xac40000000ull, 0x1eff0000000ull, { 32, 24, 60, 0, 0 }, 0x0, 67, },
+  { 238, 3, 1, 0x8c80000000ull, 0x1fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 67, },
+  { 238, 3, 1, 0xac80000000ull, 0x1eff0000000ull, { 32, 24, 60, 0, 0 }, 0x0, 67, },
+  { 239, 3, 1, 0x8cc0000000ull, 0x1fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 68, },
+  { 239, 3, 1, 0xacc0000000ull, 0x1eff0000000ull, { 32, 24, 60, 0, 0 }, 0x0, 68, },
+  { 240, 3, 1, 0xcec0000000ull, 0x1fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 660, },
+  { 240, 3, 1, 0xeec0000000ull, 0x1eff0000000ull, { 32, 18, 60, 0, 0 }, 0x0, 660, },
+  { 241, 3, 1, 0xcc40000000ull, 0x1fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 69, },
+  { 241, 3, 1, 0xec40000000ull, 0x1eff0000000ull, { 32, 18, 60, 0, 0 }, 0x0, 69, },
+  { 242, 3, 1, 0xccc0000000ull, 0x1fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 69, },
+  { 242, 3, 1, 0xecc0000000ull, 0x1eff0000000ull, { 32, 18, 60, 0, 0 }, 0x0, 69, },
+  { 243, 3, 1, 0xcc00000000ull, 0x1fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 69, },
+  { 243, 3, 1, 0xec00000000ull, 0x1eff0000000ull, { 32, 18, 60, 0, 0 }, 0x0, 69, },
+  { 244, 3, 1, 0xcc80000000ull, 0x1fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 69, },
+  { 244, 3, 1, 0xec80000000ull, 0x1eff0000000ull, { 32, 18, 60, 0, 0 }, 0x0, 69, },
+  { 245, 1, 1, 0x10028000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 245, 1, 1, 0x10020000000ull, 0x1eff8000000ull, { 23, 24, 25, 3, 0 }, 0x0, 0, },
+  { 245, 1, 1, 0x10128000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 0, },
+  { 246, 3, 0, 0x20000000ull, 0x1ee78000000ull, { 66, 0, 0, 0, 0 }, 0x0, 70, },
+  { 247, 2, 1, 0xa0000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, },
+  { 248, 2, 1, 0xa8000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, },
+  { 249, 2, 1, 0xb0000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, },
+  { 250, 3, 0, 0x198000000ull, 0x1eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 306, },
+  { 251, 3, 1, 0x20f8000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x8, 71, },
+  { 252, 2, 2, 0xa000000000ull, 0x1fe00003000ull, { 21, 22, 25, 75, 0 }, 0x0, 477, },
+  { 252, 2, 2, 0xa000000000ull, 0x1fe00003000ull, { 22, 21, 25, 75, 0 }, 0x40, 478, },
+  { 253, 3, 1, 0x20d0000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 72, },
+  { 254, 2, 2, 0xa000002000ull, 0x1fe00003000ull, { 21, 22, 25, 0, 0 }, 0x0, 477, },
+  { 254, 2, 2, 0xa000002000ull, 0x1fe00003000ull, { 22, 21, 25, 0, 0 }, 0x40, 478, },
+  { 255, 3, 1, 0x20f0000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x8, 71, },
+  { 257, 3, 1, 0x20d8000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 73, },
+  { 261, 2, 1, 0xe840000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 301, },
+  { 262, 2, 1, 0xea40000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 301, },
+  { 263, 2, 1, 0xf840000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 301, },
+  { 271, 3, 1, 0x8208000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 74, },
+  { 272, 3, 1, 0x8248000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 74, },
+  { 273, 3, 1, 0x8288000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 74, },
+  { 274, 3, 1, 0x82c8000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 74, },
+  { 276, 5, 1, 0x1d000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 302, },
+  { 276, 5, 1, 0x1d000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 353, },
+  { 277, 5, 1, 0x1d000000000ull, 0x1fc000fe000ull, { 17, 19, 20, 0, 0 }, 0x40, 303, },
+  { 278, 1, 1, 0x10078000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
+  { 278, 1, 1, 0x10178000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 0, },
+  { 281, 2, 1, 0x80000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, },
+  { 282, 2, 1, 0x88000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, },
+  { 283, 2, 1, 0x90000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, },
+};
+
+static const char dis_table[] = {
+0xa0, 0xc2, 0x60, 0xa0, 0x2c, 0x80, 0xa0, 0x2a, 0x80, 0xa0, 0x1a, 0x70, 
+0x98, 0xb0, 0x01, 0x40, 0x90, 0x50, 0x90, 0x28, 0x24, 0x20, 0x28, 0x24, 
+0x20, 0x20, 0x90, 0x28, 0x24, 0x20, 0x18, 0x24, 0x20, 0x10, 0x90, 0x50, 
+0x90, 0x28, 0x24, 0x20, 0x00, 0x24, 0x1f, 0xf8, 0x90, 0x28, 0x24, 0x1f, 
+0xf0, 0x24, 0x1f, 0xe8, 0xa8, 0x0b, 0x28, 0x15, 0x00, 0x97, 0x00, 0x95, 
+0xa8, 0x9a, 0x98, 0x05, 0x18, 0x90, 0xf8, 0x90, 0x80, 0x90, 0x40, 0x80, 
+0xa4, 0x06, 0x50, 0x37, 0x13, 0x80, 0xa4, 0x2d, 0x18, 0x33, 0xfa, 0x90, 
+0x50, 0x90, 0x28, 0x80, 0x35, 0xac, 0x80, 0x31, 0x08, 0x81, 0x34, 0xec, 
+0x90, 0xe0, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x00, 0x00, 0x33, 0xdb, 0xa4, 
+0x1e, 0xc0, 0x33, 0xd9, 0x90, 0x38, 0xa4, 0x26, 0xd0, 0x34, 0xcf, 0xa4, 
+0x2d, 0xe0, 0x35, 0xb6, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x2e, 0xd0, 0x35, 
+0xde, 0xa4, 0x28, 0xd8, 0x35, 0x23, 0x80, 0xa4, 0x2e, 0xc8, 0x35, 0xdd, 
+0x92, 0x18, 0x91, 0xc0, 0x80, 0x91, 0x80, 0x90, 0xf8, 0xdb, 0x84, 0x60, 
+0xf8, 0x80, 0xc0, 0xc0, 0x80, 0xa4, 0x40, 0x80, 0x8c, 0x41, 0x50, 0x84, 
+0x38, 0x5a, 0xc0, 0xc0, 0x80, 0xa4, 0x40, 0x70, 0x8c, 0x41, 0x30, 0x84, 
+0x38, 0x56, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x37, 0xf8, 0x50, 
+0xc0, 0xc0, 0x81, 0x37, 0xf6, 0xa4, 0x08, 0x30, 0x31, 0x07, 0x80, 0x90, 
+0x28, 0x80, 0x30, 0xe5, 0x80, 0x30, 0xe7, 0x81, 0x90, 0x38, 0xa4, 0x07, 
+0x70, 0x30, 0xea, 0xa4, 0x07, 0x40, 0x30, 0xe6, 0xc0, 0x40, 0x10, 0x10, 
+0x90, 0x38, 0xa4, 0x04, 0x30, 0x30, 0x3f, 0xa4, 0x04, 0x38, 0x30, 0x7b, 
+0x18, 0x24, 0x34, 0xd0, 0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0, 
+0x80, 0xa4, 0x40, 0xb0, 0x38, 0x36, 0xc0, 0xc0, 0x80, 0xa4, 0x40, 0xa0, 
+0x38, 0x32, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x37, 0xfe, 0x50, 
+0xc0, 0xc0, 0x81, 0x37, 0xfc, 0x92, 0xb8, 0x99, 0x84, 0x07, 0x60, 0x90, 
+0x78, 0x90, 0x50, 0x10, 0x10, 0x80, 0xa4, 0x2d, 0x10, 0x33, 0xf9, 0x82, 
+0x35, 0xab, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x26, 0xc8, 0x34, 
+0xce, 0xa4, 0x2d, 0xd8, 0x35, 0xb5, 0x80, 0x90, 0x38, 0xa4, 0x28, 0xf8, 
+0x35, 0x27, 0xa4, 0x28, 0xd0, 0x35, 0x22, 0x83, 0x90, 0xa8, 0xd3, 0x82, 
+0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x40, 0xe0, 0x38, 0x42, 0xc0, 0xc0, 0x80, 
+0xa4, 0x40, 0xd0, 0x38, 0x3e, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 
+0x38, 0x04, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x02, 0x18, 0x24, 0x07, 0x68, 
+0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x41, 0x10, 
+0x38, 0x4e, 0xc0, 0xc0, 0x80, 0xa4, 0x41, 0x00, 0x38, 0x4a, 0xd3, 0x82, 
+0x40, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x0a, 0x50, 0xc0, 0xc0, 0x81, 0x38, 
+0x08, 0x94, 0x50, 0x92, 0xf8, 0x99, 0x84, 0x34, 0xc0, 0x90, 0x78, 0x90, 
+0x50, 0x10, 0x10, 0x80, 0xa4, 0x2d, 0x08, 0x33, 0xf8, 0x82, 0x35, 0xaa, 
+0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x26, 0xc0, 0x34, 0xcd, 0xa4, 
+0x2d, 0xd0, 0x35, 0xb4, 0x80, 0x90, 0x38, 0xa4, 0x28, 0xf0, 0x35, 0x26, 
+0xa4, 0x28, 0xc8, 0x35, 0x21, 0x83, 0x90, 0xe8, 0xd3, 0x83, 0xc0, 0xc0, 
+0xc0, 0x80, 0xa4, 0x40, 0x90, 0x8c, 0x41, 0x70, 0x84, 0x38, 0x58, 0xc0, 
+0xc0, 0x80, 0xa4, 0x40, 0x78, 0x8c, 0x41, 0x40, 0x84, 0x38, 0x57, 0xd3, 
+0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x37, 0xfa, 0x50, 0xc0, 0xc0, 0x81, 
+0x37, 0xf7, 0x18, 0x24, 0x34, 0xc8, 0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 
+0xc0, 0xc0, 0x80, 0xa4, 0x40, 0xc0, 0x38, 0x3a, 0xc0, 0xc0, 0x80, 0xa4, 
+0x40, 0xa8, 0x38, 0x34, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x38, 
+0x00, 0x50, 0xc0, 0xc0, 0x81, 0x37, 0xfd, 0x92, 0xb8, 0x99, 0x84, 0x34, 
+0xb0, 0x90, 0x78, 0x90, 0x50, 0x10, 0x10, 0x80, 0xa4, 0x2d, 0x00, 0x33, 
+0xf7, 0x82, 0x35, 0xa9, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x26, 
+0xb8, 0x34, 0xcc, 0xa4, 0x2d, 0xc8, 0x35, 0xb3, 0x80, 0x90, 0x38, 0xa4, 
+0x28, 0xe8, 0x35, 0x25, 0xa4, 0x28, 0xc0, 0x35, 0x20, 0x83, 0x90, 0xa8, 
+0xd3, 0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x40, 0xf0, 0x38, 0x46, 0xc0, 
+0xc0, 0x80, 0xa4, 0x40, 0xd8, 0x38, 0x40, 0xd3, 0x82, 0x40, 0x50, 0xc0, 
+0xc0, 0x81, 0x38, 0x06, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x03, 0x18, 0x20, 
+0x01, 0x48, 0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4, 
+0x41, 0x20, 0x38, 0x52, 0xc0, 0xc0, 0x80, 0xa4, 0x41, 0x08, 0x38, 0x4c, 
+0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x0c, 0x50, 0xc0, 0xc0, 
+0x81, 0x38, 0x09, 0xda, 0x06, 0xe1, 0xa5, 0xc0, 0x90, 0x60, 0x90, 0x38, 
+0xa4, 0x07, 0xd8, 0x30, 0xf0, 0x80, 0x30, 0xf9, 0x90, 0x38, 0xa4, 0x07, 
+0x90, 0x30, 0xf3, 0x80, 0x30, 0xf6, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x07, 
+0xc0, 0x30, 0xf1, 0x80, 0x30, 0xfa, 0x90, 0x38, 0xa4, 0x07, 0xa8, 0x30, 
+0xf4, 0x80, 0x30, 0xf7, 0xc8, 0x40, 0x18, 0x00, 0x91, 0x38, 0x90, 0x40, 
+0x82, 0xa4, 0x06, 0x68, 0x37, 0x16, 0x90, 0xc0, 0x80, 0x90, 0x90, 0x90, 
+0x48, 0xc9, 0xe1, 0x34, 0xc0, 0x85, 0x35, 0xce, 0xc9, 0xe1, 0x35, 0x40, 
+0x85, 0x34, 0xaa, 0x80, 0x34, 0xd2, 0x10, 0x10, 0x81, 0x35, 0x17, 0x90, 
+0xa8, 0x10, 0x10, 0x90, 0x28, 0x81, 0x34, 0x89, 0x90, 0x38, 0xa4, 0x2d, 
+0x88, 0x35, 0xb2, 0xa4, 0x1f, 0x08, 0x34, 0x8b, 0x90, 0x70, 0x10, 0x10, 
+0x90, 0x38, 0xa4, 0x1f, 0x30, 0x33, 0xe7, 0x80, 0x33, 0xe5, 0x90, 0x60, 
+0x90, 0x28, 0x24, 0x26, 0x50, 0xa4, 0x26, 0x58, 0x34, 0xc9, 0x80, 0xa4, 
+0x1f, 0x20, 0x33, 0xe3, 0x80, 0x90, 0xf8, 0x90, 0x90, 0x90, 0x50, 0x90, 
+0x28, 0x80, 0x37, 0x17, 0x80, 0x35, 0xe1, 0x80, 0xa4, 0x34, 0x90, 0x36, 
+0x93, 0x90, 0x28, 0x81, 0x30, 0x88, 0x80, 0xa4, 0x34, 0xd8, 0x36, 0x9c, 
+0x83, 0x35, 0xd3, 0x98, 0xb0, 0x01, 0x40, 0x90, 0x50, 0x90, 0x28, 0x24, 
+0x20, 0x78, 0x24, 0x20, 0x70, 0x90, 0x28, 0x24, 0x20, 0x68, 0x24, 0x20, 
+0x60, 0x90, 0x50, 0x90, 0x28, 0x24, 0x20, 0x50, 0x24, 0x20, 0x48, 0x90, 
+0x28, 0x24, 0x20, 0x40, 0x24, 0x20, 0x38, 0xa8, 0x08, 0xe0, 0x0d, 0xe0, 
+0x96, 0x38, 0x95, 0xe8, 0x9b, 0x48, 0x05, 0xa8, 0x91, 0xa0, 0x90, 0xd0, 
+0x90, 0x70, 0x90, 0x38, 0xa4, 0x06, 0xd8, 0x30, 0xdc, 0xa4, 0x06, 0xc8, 
+0x30, 0xda, 0x90, 0x38, 0xa4, 0x06, 0xb8, 0x30, 0xd8, 0x80, 0x30, 0xd6, 
+0x90, 0x60, 0x90, 0x28, 0x24, 0x04, 0x68, 0xa4, 0x04, 0x58, 0x30, 0x8c, 
+0x90, 0x38, 0xa4, 0x04, 0x48, 0x30, 0x8a, 0xa4, 0x1e, 0xa0, 0x33, 0xd5, 
+0x90, 0xe0, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x06, 0xa0, 0x30, 0xd5, 0xa4, 
+0x06, 0x90, 0x30, 0xd3, 0x90, 0x38, 0xa4, 0x21, 0x98, 0x34, 0x29, 0xa4, 
+0x24, 0x30, 0x34, 0x80, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x22, 0x20, 0x34, 
+0x50, 0xa4, 0x21, 0xf0, 0x34, 0x4a, 0x10, 0x10, 0xa4, 0x01, 0xf0, 0x30, 
+0x1d, 0x91, 0x50, 0x90, 0x90, 0x90, 0x50, 0x90, 0x28, 0x24, 0x06, 0xe8, 
+0x80, 0x30, 0xe3, 0x80, 0xa4, 0x06, 0xf0, 0x30, 0xe1, 0x90, 0x50, 0x90, 
+0x28, 0x24, 0x06, 0xf8, 0x80, 0x30, 0xe4, 0x90, 0x38, 0xa4, 0x07, 0x00, 
+0x30, 0xe2, 0xa4, 0x1e, 0xb0, 0x33, 0xd7, 0x90, 0xe0, 0x90, 0x70, 0x90, 
+0x38, 0xa4, 0x23, 0x88, 0x35, 0xae, 0xa4, 0x22, 0xb0, 0x34, 0x77, 0x90, 
+0x38, 0xa4, 0x23, 0x08, 0x34, 0x6b, 0xa4, 0x22, 0xe0, 0x34, 0x66, 0x81, 
+0xa4, 0x05, 0x30, 0x30, 0xa7, 0xe4, 0xe1, 0xf7, 0x80, 0x37, 0xe0, 0xed, 
+0x21, 0xf9, 0x21, 0xa5, 0x40, 0x37, 0xe6, 0x92, 0x40, 0x99, 0x18, 0x02, 
+0x00, 0x10, 0x10, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x21, 0x90, 
+0x34, 0x28, 0xa4, 0x24, 0x28, 0x34, 0x7f, 0x80, 0x90, 0x38, 0xa4, 0x22, 
+0x18, 0x34, 0x4f, 0xa4, 0x21, 0xe8, 0x34, 0x49, 0x10, 0x10, 0x80, 0x90, 
+0x70, 0x90, 0x38, 0xa4, 0x23, 0x80, 0x34, 0x7c, 0xa4, 0x22, 0xa8, 0x34, 
+0x76, 0x90, 0x38, 0xa4, 0x23, 0x00, 0x34, 0x6a, 0xa4, 0x22, 0xd8, 0x34, 
+0x65, 0xe4, 0xe1, 0xfa, 0x80, 0x37, 0xec, 0xed, 0x21, 0xfc, 0x21, 0xa5, 
+0x00, 0x37, 0xf2, 0x92, 0x80, 0x92, 0x40, 0x99, 0x18, 0x02, 0x00, 0x10, 
+0x10, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x21, 0x88, 0x34, 0x27, 
+0xa4, 0x24, 0x20, 0x34, 0x7e, 0x80, 0x90, 0x38, 0xa4, 0x22, 0x10, 0x34, 
+0x4e, 0xa4, 0x21, 0xe0, 0x34, 0x48, 0x10, 0x10, 0x80, 0x90, 0x70, 0x90, 
+0x38, 0xa4, 0x23, 0x78, 0x34, 0x7b, 0xa4, 0x22, 0xa0, 0x34, 0x75, 0x90, 
+0x38, 0xa4, 0x22, 0xf8, 0x34, 0x69, 0xa4, 0x22, 0xd0, 0x34, 0x64, 0xe4, 
+0xe1, 0xf7, 0xc0, 0x37, 0xe2, 0xe5, 0x21, 0xf9, 0x40, 0x37, 0xe8, 0x92, 
+0x50, 0x99, 0x18, 0x02, 0x00, 0x10, 0x10, 0x90, 0x80, 0x10, 0x10, 0x90, 
+0x38, 0xa4, 0x21, 0x80, 0x34, 0x26, 0xa4, 0x24, 0x18, 0x34, 0x7d, 0x80, 
+0x90, 0x38, 0xa4, 0x22, 0x08, 0x34, 0x4d, 0xa4, 0x21, 0xd8, 0x34, 0x47, 
+0x10, 0x10, 0x80, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x23, 0x70, 0x34, 0x7a, 
+0xa4, 0x22, 0x98, 0x34, 0x74, 0x90, 0x38, 0xa4, 0x22, 0xf0, 0x34, 0x68, 
+0xa4, 0x22, 0xc8, 0x34, 0x63, 0xec, 0xe1, 0xfa, 0xe2, 0x18, 0x00, 0x37, 
+0xee, 0xe5, 0x21, 0xfc, 0x40, 0x37, 0xf4, 0xc0, 0x40, 0x80, 0x10, 0x10, 
+0x81, 0x90, 0x90, 0x90, 0x48, 0xc9, 0xe1, 0x0b, 0x40, 0x85, 0x34, 0x8a, 
+0xc9, 0xe1, 0x0b, 0x80, 0x85, 0x34, 0x1b, 0x80, 0x34, 0x2c, 0x80, 0xd8, 
+0x47, 0x80, 0x0d, 0xc0, 0xc0, 0x80, 0x10, 0x10, 0x82, 0x90, 0x58, 0xd5, 
+0x81, 0x80, 0x80, 0x36, 0xa5, 0x80, 0x36, 0xab, 0xd5, 0x81, 0x80, 0x80, 
+0x36, 0xa7, 0x80, 0x36, 0xa9, 0xc0, 0x80, 0x10, 0x10, 0x82, 0x90, 0x58, 
+0xd5, 0x81, 0x80, 0x80, 0x36, 0xa6, 0x80, 0x36, 0xac, 0xd5, 0x81, 0x80, 
+0x80, 0x36, 0xa8, 0x80, 0x36, 0xaa, 0xc0, 0x80, 0x84, 0x30, 0xce, 0xa0, 
+0x56, 0x50, 0xa0, 0x40, 0x70, 0xa8, 0x1d, 0x40, 0x33, 0x18, 0xa0, 0x12, 
+0x38, 0xa0, 0x0b, 0x48, 0x96, 0x00, 0x9a, 0xf0, 0x05, 0xc0, 0x91, 0x70, 
+0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x2f, 0xb8, 0x33, 0xd3, 0xa4, 
+0x2f, 0xc8, 0x33, 0xc0, 0x10, 0x10, 0xa4, 0x2f, 0xc0, 0x33, 0xbf, 0x90, 
+0x70, 0x90, 0x38, 0xa4, 0x2f, 0x88, 0x33, 0x82, 0xa4, 0x2f, 0x98, 0x33, 
+0x6f, 0x10, 0x10, 0xa4, 0x2f, 0x90, 0x33, 0x6e, 0x90, 0xb8, 0x90, 0x70, 
+0x90, 0x38, 0xa4, 0x2f, 0x58, 0x33, 0x31, 0xa4, 0x2f, 0x68, 0x33, 0x1e, 
+0x10, 0x10, 0xa4, 0x2f, 0x60, 0x33, 0x1d, 0x90, 0x70, 0x90, 0x38, 0xa4, 
+0x2f, 0x28, 0x32, 0xe0, 0xa4, 0x2f, 0x38, 0x32, 0xca, 0x10, 0x10, 0xa4, 
+0x2f, 0x30, 0x32, 0xc9, 0x91, 0x70, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 
+0xa4, 0x2f, 0xa0, 0x33, 0xbc, 0xa4, 0x2f, 0xb0, 0x33, 0xbe, 0x10, 0x10, 
+0xa4, 0x2f, 0xa8, 0x33, 0xbd, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x2f, 0x70, 
+0x33, 0x6b, 0xa4, 0x2f, 0x80, 0x33, 0x6d, 0x10, 0x10, 0xa4, 0x2f, 0x78, 
+0x33, 0x6c, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x2f, 0x40, 0x33, 
+0x1a, 0xa4, 0x2f, 0x50, 0x33, 0x1c, 0x10, 0x10, 0xa4, 0x2f, 0x48, 0x33, 
+0x1b, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x2f, 0x10, 0x32, 0xc6, 0xa4, 0x2f, 
+0x20, 0x32, 0xc8, 0x10, 0x10, 0xa4, 0x2f, 0x18, 0x32, 0xc7, 0xe4, 0xe1, 
+0x64, 0x80, 0x35, 0x9c, 0x9a, 0xf0, 0x05, 0x00, 0x91, 0x70, 0x90, 0xb8, 
+0x90, 0x70, 0x90, 0x38, 0xa4, 0x00, 0xb0, 0x33, 0xd0, 0xa4, 0x00, 0xa8, 
+0x33, 0xd2, 0x10, 0x10, 0xa4, 0x00, 0xa0, 0x33, 0xd1, 0x90, 0x70, 0x90, 
+0x38, 0xa4, 0x00, 0x98, 0x33, 0x7f, 0xa4, 0x00, 0x90, 0x33, 0x81, 0x10, 
+0x10, 0xa4, 0x00, 0x88, 0x33, 0x80, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 
+0xa4, 0x00, 0x80, 0x33, 0x2e, 0xa4, 0x00, 0x78, 0x33, 0x30, 0x10, 0x10, 
+0xa4, 0x00, 0x70, 0x33, 0x2f, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x00, 0x68, 
+0x32, 0xdd, 0xa4, 0x00, 0x60, 0x32, 0xdf, 0x10, 0x10, 0xa4, 0x00, 0x58, 
+0x32, 0xde, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 
+0xb9, 0x80, 0x33, 0xbb, 0x10, 0x10, 0x80, 0x33, 0xba, 0x90, 0x50, 0x90, 
+0x28, 0x80, 0x33, 0x68, 0x80, 0x33, 0x6a, 0x10, 0x10, 0x80, 0x33, 0x69, 
+0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x17, 0x80, 0x33, 0x19, 
+0x10, 0x10, 0x80, 0x33, 0x18, 0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 0xc3, 
+0x80, 0x32, 0xc5, 0x10, 0x10, 0x80, 0x32, 0xc4, 0xe4, 0xe1, 0x5c, 0x00, 
+0x35, 0x84, 0x95, 0x40, 0x9a, 0x90, 0x05, 0x00, 0x91, 0x10, 0x90, 0x88, 
+0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0xca, 0x80, 0x33, 0xcc, 0x10, 0x10, 
+0x80, 0x33, 0xcb, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x79, 0x80, 0x33, 
+0x7b, 0x10, 0x10, 0x80, 0x33, 0x7a, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 
+0xa4, 0x27, 0xb0, 0x33, 0x28, 0xa4, 0x27, 0xc0, 0x33, 0x2a, 0x10, 0x10, 
+0xa4, 0x27, 0xb8, 0x33, 0x29, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x27, 0x80, 
+0x32, 0xd7, 0xa4, 0x27, 0x90, 0x32, 0xd9, 0x10, 0x10, 0xa4, 0x27, 0x88, 
+0x32, 0xd8, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 
+0xcd, 0x80, 0x33, 0xcf, 0x10, 0x10, 0x80, 0x33, 0xce, 0x90, 0x50, 0x90, 
+0x28, 0x80, 0x33, 0x7c, 0x80, 0x33, 0x7e, 0x10, 0x10, 0x80, 0x33, 0x7d, 
+0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x27, 0x98, 0x33, 0x2b, 0xa4, 
+0x27, 0xa8, 0x33, 0x2d, 0x10, 0x10, 0xa4, 0x27, 0xa0, 0x33, 0x2c, 0x90, 
+0x70, 0x90, 0x38, 0xa4, 0x27, 0x68, 0x32, 0xda, 0xa4, 0x27, 0x78, 0x32, 
+0xdc, 0x10, 0x10, 0xa4, 0x27, 0x70, 0x32, 0xdb, 0xe4, 0xe1, 0x64, 0x00, 
+0x35, 0x9a, 0x98, 0xb8, 0x01, 0x68, 0x10, 0x10, 0x10, 0x10, 0x90, 0x50, 
+0x90, 0x28, 0x80, 0x32, 0xcb, 0x80, 0x32, 0xcd, 0x10, 0x10, 0x80, 0x32, 
+0xcc, 0x90, 0x60, 0x90, 0x30, 0x60, 0xa0, 0xf7, 0x40, 0x60, 0xa0, 0xf7, 
+0xc0, 0x90, 0x30, 0x60, 0xa0, 0xf7, 0x80, 0x60, 0xa0, 0xf8, 0x00, 0xe4, 
+0xe1, 0x5b, 0x00, 0x35, 0x80, 0x96, 0xe8, 0x94, 0x80, 0x9a, 0x30, 0x04, 
+0x40, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0xc4, 
+0x80, 0x33, 0xc6, 0x10, 0x10, 0x80, 0x33, 0xc5, 0x90, 0x50, 0x90, 0x28, 
+0x80, 0x33, 0x73, 0x80, 0x33, 0x75, 0x10, 0x10, 0x80, 0x33, 0x74, 0x90, 
+0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x22, 0x80, 0x33, 0x24, 0x10, 
+0x10, 0x80, 0x33, 0x23, 0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 0xd1, 0x80, 
+0x32, 0xd3, 0x10, 0x10, 0x80, 0x32, 0xd2, 0x91, 0x10, 0x90, 0x88, 0x90, 
+0x50, 0x90, 0x28, 0x80, 0x33, 0xc1, 0x80, 0x33, 0xc3, 0x10, 0x10, 0x80, 
+0x33, 0xc2, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x70, 0x80, 0x33, 0x72, 
+0x10, 0x10, 0x80, 0x33, 0x71, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 
+0x33, 0x1f, 0x80, 0x33, 0x21, 0x10, 0x10, 0x80, 0x33, 0x20, 0x90, 0x50, 
+0x90, 0x28, 0x80, 0x32, 0xce, 0x80, 0x32, 0xd0, 0x10, 0x10, 0x80, 0x32, 
+0xcf, 0xe4, 0xe1, 0x63, 0x80, 0x35, 0x98, 0x88, 0x02, 0x28, 0x91, 0x10, 
+0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0xc7, 0x80, 0x33, 0xc9, 
+0x10, 0x10, 0x80, 0x33, 0xc8, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x76, 
+0x80, 0x33, 0x78, 0x10, 0x10, 0x80, 0x33, 0x77, 0x90, 0x88, 0x90, 0x50, 
+0x90, 0x28, 0x80, 0x33, 0x25, 0x80, 0x33, 0x27, 0x10, 0x10, 0x80, 0x33, 
+0x26, 0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 0xd4, 0x80, 0x32, 0xd6, 0x10, 
+0x10, 0x80, 0x32, 0xd5, 0xe4, 0xe1, 0x5a, 0x00, 0x35, 0x7c, 0x93, 0x40, 
+0x99, 0x90, 0x03, 0x00, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x28, 0x81, 0x30, 
+0x7a, 0x10, 0x10, 0x80, 0x30, 0x79, 0x90, 0x28, 0x81, 0x30, 0x72, 0x10, 
+0x10, 0x80, 0x30, 0x71, 0x90, 0x60, 0x90, 0x28, 0x81, 0x30, 0x6a, 0x10, 
+0x10, 0x80, 0x30, 0x69, 0x90, 0x28, 0x81, 0x30, 0x62, 0x10, 0x10, 0x80, 
+0x30, 0x61, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x28, 0x81, 0x30, 0x77, 0x10, 
+0x10, 0x80, 0x30, 0x78, 0x90, 0x28, 0x81, 0x30, 0x6f, 0x10, 0x10, 0x80, 
+0x30, 0x70, 0x90, 0x60, 0x90, 0x28, 0x81, 0x30, 0x67, 0x10, 0x10, 0x80, 
+0x30, 0x68, 0x90, 0x28, 0x81, 0x30, 0x5f, 0x10, 0x10, 0x80, 0x30, 0x60, 
+0xe4, 0xe1, 0x63, 0x00, 0x35, 0x96, 0x88, 0x00, 0x88, 0x10, 0x10, 0x10, 
+0x10, 0x90, 0x28, 0x81, 0x30, 0x5d, 0x10, 0x10, 0x80, 0x30, 0x5e, 0xe4, 
+0xe1, 0x59, 0x00, 0x35, 0x78, 0xa0, 0x0e, 0x80, 0xa0, 0x09, 0x08, 0x94, 
+0x80, 0x9a, 0x30, 0x04, 0x40, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 
+0x28, 0x80, 0x33, 0xb8, 0x80, 0x33, 0xa5, 0x10, 0x10, 0x80, 0x33, 0xa4, 
+0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x67, 0x80, 0x33, 0x54, 0x10, 0x10, 
+0x80, 0x33, 0x53, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x16, 
+0x80, 0x33, 0x03, 0x10, 0x10, 0x80, 0x33, 0x02, 0x90, 0x50, 0x90, 0x28, 
+0x80, 0x32, 0xc2, 0x80, 0x32, 0xac, 0x10, 0x10, 0x80, 0x32, 0xab, 0x91, 
+0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0xa1, 0x80, 0x33, 
+0xa3, 0x10, 0x10, 0x80, 0x33, 0xa2, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 
+0x50, 0x80, 0x33, 0x52, 0x10, 0x10, 0x80, 0x33, 0x51, 0x90, 0x88, 0x90, 
+0x50, 0x90, 0x28, 0x80, 0x32, 0xff, 0x80, 0x33, 0x01, 0x10, 0x10, 0x80, 
+0x33, 0x00, 0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 0xa8, 0x80, 0x32, 0xaa, 
+0x10, 0x10, 0x80, 0x32, 0xa9, 0xe4, 0xe1, 0x52, 0x00, 0x35, 0x5c, 0x9a, 
+0x30, 0x04, 0x40, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 
+0x33, 0xb5, 0x80, 0x33, 0xb7, 0x10, 0x10, 0x80, 0x33, 0xb6, 0x90, 0x50, 
+0x90, 0x28, 0x80, 0x33, 0x64, 0x80, 0x33, 0x66, 0x10, 0x10, 0x80, 0x33, 
+0x65, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x13, 0x80, 0x33, 
+0x15, 0x10, 0x10, 0x80, 0x33, 0x14, 0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 
+0xbf, 0x80, 0x32, 0xc1, 0x10, 0x10, 0x80, 0x32, 0xc0, 0x91, 0x10, 0x90, 
+0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x9e, 0x80, 0x33, 0xa0, 0x10, 
+0x10, 0x80, 0x33, 0x9f, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x4d, 0x80, 
+0x33, 0x4f, 0x10, 0x10, 0x80, 0x33, 0x4e, 0x90, 0x88, 0x90, 0x50, 0x90, 
+0x28, 0x80, 0x32, 0xfc, 0x80, 0x32, 0xfe, 0x10, 0x10, 0x80, 0x32, 0xfd, 
+0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 0xa5, 0x80, 0x32, 0xa7, 0x10, 0x10, 
+0x80, 0x32, 0xa6, 0xe4, 0xe1, 0x4b, 0x80, 0x35, 0x38, 0x94, 0x80, 0x9a, 
+0x30, 0x04, 0x40, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 
+0x33, 0xaf, 0x80, 0x33, 0xb1, 0x10, 0x10, 0x80, 0x33, 0xb0, 0x90, 0x50, 
+0x90, 0x28, 0x80, 0x33, 0x5e, 0x80, 0x33, 0x60, 0x10, 0x10, 0x80, 0x33, 
+0x5f, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x0d, 0x80, 0x33, 
+0x0f, 0x10, 0x10, 0x80, 0x33, 0x0e, 0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 
+0xb9, 0x80, 0x32, 0xbb, 0x10, 0x10, 0x80, 0x32, 0xba, 0x91, 0x10, 0x90, 
+0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0xb2, 0x80, 0x33, 0xb4, 0x10, 
+0x10, 0x80, 0x33, 0xb3, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x61, 0x80, 
+0x33, 0x63, 0x10, 0x10, 0x80, 0x33, 0x62, 0x90, 0x88, 0x90, 0x50, 0x90, 
+0x28, 0x80, 0x33, 0x10, 0x80, 0x33, 0x12, 0x10, 0x10, 0x80, 0x33, 0x11, 
+0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 0xbc, 0x80, 0x32, 0xbe, 0x10, 0x10, 
+0x80, 0x32, 0xbd, 0xe4, 0xe1, 0x51, 0x00, 0x35, 0x58, 0x88, 0x00, 0xb0, 
+0x10, 0x10, 0x10, 0x10, 0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 0xad, 0x80, 
+0x32, 0xaf, 0x10, 0x10, 0x80, 0x32, 0xae, 0xe4, 0xe1, 0x4b, 0x00, 0x35, 
+0x36, 0x96, 0xe8, 0x94, 0x80, 0x9a, 0x30, 0x04, 0x40, 0x91, 0x10, 0x90, 
+0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0xa9, 0x80, 0x33, 0xab, 0x10, 
+0x10, 0x80, 0x33, 0xaa, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x58, 0x80, 
+0x33, 0x5a, 0x10, 0x10, 0x80, 0x33, 0x59, 0x90, 0x88, 0x90, 0x50, 0x90, 
+0x28, 0x80, 0x33, 0x07, 0x80, 0x33, 0x09, 0x10, 0x10, 0x80, 0x33, 0x08, 
+0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 0xb3, 0x80, 0x32, 0xb5, 0x10, 0x10, 
+0x80, 0x32, 0xb4, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 
+0x33, 0xa6, 0x80, 0x33, 0xa8, 0x10, 0x10, 0x80, 0x33, 0xa7, 0x90, 0x50, 
+0x90, 0x28, 0x80, 0x33, 0x55, 0x80, 0x33, 0x57, 0x10, 0x10, 0x80, 0x33, 
+0x56, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x04, 0x80, 0x33, 
+0x06, 0x10, 0x10, 0x80, 0x33, 0x05, 0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 
+0xb0, 0x80, 0x32, 0xb2, 0x10, 0x10, 0x80, 0x32, 0xb1, 0xe4, 0xe1, 0x50, 
+0x00, 0x35, 0x54, 0x88, 0x02, 0x28, 0x91, 0x10, 0x90, 0x88, 0x90, 0x50, 
+0x90, 0x28, 0x80, 0x33, 0xac, 0x80, 0x33, 0xae, 0x10, 0x10, 0x80, 0x33, 
+0xad, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 0x5b, 0x80, 0x33, 0x5d, 0x10, 
+0x10, 0x80, 0x33, 0x5c, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x33, 
+0x0a, 0x80, 0x33, 0x0c, 0x10, 0x10, 0x80, 0x33, 0x0b, 0x90, 0x50, 0x90, 
+0x28, 0x80, 0x32, 0xb6, 0x80, 0x32, 0xb8, 0x10, 0x10, 0x80, 0x32, 0xb7, 
+0xe4, 0xe1, 0x4a, 0x80, 0x35, 0x34, 0x90, 0x40, 0xe5, 0x21, 0x4f, 0x00, 
+0x35, 0x50, 0xe5, 0x21, 0x4a, 0x00, 0x35, 0x32, 0x9e, 0xb4, 0x2e, 0xc0, 
+0x93, 0x70, 0x91, 0xd8, 0xd5, 0x07, 0x80, 0xd0, 0xc4, 0x40, 0x90, 0x48, 
+0x80, 0x8c, 0x3d, 0x60, 0x84, 0x37, 0xdc, 0xa4, 0x3b, 0xd0, 0x37, 0x92, 
+0x90, 0x28, 0x24, 0x3b, 0x10, 0xa4, 0x39, 0x90, 0x37, 0x4a, 0xd0, 0xc4, 
+0x40, 0x90, 0x48, 0x80, 0x8c, 0x3d, 0x40, 0x84, 0x37, 0xd8, 0xa4, 0x3b, 
+0xc0, 0x37, 0x90, 0x90, 0x28, 0x24, 0x3b, 0x00, 0xa4, 0x39, 0x80, 0x37, 
+0x48, 0xd5, 0x06, 0x80, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x37, 0xb8, 
+0xa4, 0x3c, 0x00, 0x37, 0x98, 0x90, 0x28, 0x24, 0x3b, 0x40, 0xa4, 0x39, 
+0xc0, 0x37, 0x50, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x37, 0xb4, 0xa4, 
+0x3b, 0xf0, 0x37, 0x96, 0x90, 0x28, 0x24, 0x3b, 0x30, 0xa4, 0x39, 0xb0, 
+0x37, 0x4e, 0x91, 0x98, 0xd5, 0x06, 0x80, 0xd0, 0xc3, 0x40, 0x90, 0x28, 
+0x80, 0x37, 0xc4, 0xa4, 0x3c, 0x30, 0x37, 0x9e, 0x90, 0x28, 0x24, 0x3b, 
+0x70, 0xa4, 0x39, 0xf0, 0x37, 0x56, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 
+0x37, 0xc0, 0xa4, 0x3c, 0x20, 0x37, 0x9c, 0x90, 0x28, 0x24, 0x3b, 0x60, 
+0xa4, 0x39, 0xe0, 0x37, 0x54, 0xd5, 0x06, 0x80, 0xd0, 0xc3, 0x40, 0x90, 
+0x28, 0x80, 0x37, 0xd0, 0xa4, 0x3c, 0x60, 0x37, 0xa4, 0x90, 0x28, 0x24, 
+0x3b, 0xa0, 0xa4, 0x3a, 0x20, 0x37, 0x5c, 0xd0, 0xc3, 0x40, 0x90, 0x28, 
+0x80, 0x37, 0xcc, 0xa4, 0x3c, 0x50, 0x37, 0xa2, 0x90, 0x28, 0x24, 0x3b, 
+0x90, 0xa4, 0x3a, 0x10, 0x37, 0x5a, 0x93, 0x70, 0x91, 0xd8, 0xd5, 0x07, 
+0x80, 0xd0, 0xc4, 0x40, 0x90, 0x48, 0x80, 0x8c, 0x3d, 0x80, 0x84, 0x37, 
+0xda, 0xa4, 0x3b, 0xe0, 0x37, 0x94, 0x90, 0x28, 0x24, 0x3b, 0x20, 0xa4, 
+0x39, 0xa0, 0x37, 0x4c, 0xd0, 0xc4, 0x40, 0x90, 0x48, 0x80, 0x8c, 0x3d, 
+0x50, 0x84, 0x37, 0xd9, 0xa4, 0x3b, 0xc8, 0x37, 0x91, 0x90, 0x28, 0x24, 
+0x3b, 0x08, 0xa4, 0x39, 0x88, 0x37, 0x49, 0xd5, 0x06, 0x80, 0xd0, 0xc3, 
+0x40, 0x90, 0x28, 0x80, 0x37, 0xbc, 0xa4, 0x3c, 0x10, 0x37, 0x9a, 0x90, 
+0x28, 0x24, 0x3b, 0x50, 0xa4, 0x39, 0xd0, 0x37, 0x52, 0xd0, 0xc3, 0x40, 
+0x90, 0x28, 0x80, 0x37, 0xb6, 0xa4, 0x3b, 0xf8, 0x37, 0x97, 0x90, 0x28, 
+0x24, 0x3b, 0x38, 0xa4, 0x39, 0xb8, 0x37, 0x4f, 0x91, 0x98, 0xd5, 0x06, 
+0x80, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x37, 0xc8, 0xa4, 0x3c, 0x40, 
+0x37, 0xa0, 0x90, 0x28, 0x24, 0x3b, 0x80, 0xa4, 0x3a, 0x00, 0x37, 0x58, 
+0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x37, 0xc2, 0xa4, 0x3c, 0x28, 0x37, 
+0x9d, 0x90, 0x28, 0x24, 0x3b, 0x68, 0xa4, 0x39, 0xe8, 0x37, 0x55, 0xd5, 
+0x06, 0x80, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x37, 0xd4, 0xa4, 0x3c, 
+0x70, 0x37, 0xa6, 0x90, 0x28, 0x24, 0x3b, 0xb0, 0xa4, 0x3a, 0x30, 0x37, 
+0x5e, 0xd0, 0xc3, 0x40, 0x90, 0x28, 0x80, 0x37, 0xce, 0xa4, 0x3c, 0x58, 
+0x37, 0xa3, 0x90, 0x28, 0x24, 0x3b, 0x98, 0xa4, 0x3a, 0x18, 0x37, 0x5b, 
+0x99, 0x08, 0x01, 0xf0, 0x81, 0x90, 0x78, 0xd4, 0xc2, 0x00, 0xa4, 0x01, 
+0x80, 0x30, 0x2e, 0xa4, 0x01, 0x00, 0x30, 0x1e, 0xd4, 0xc2, 0x00, 0xa4, 
+0x01, 0xc0, 0x30, 0x32, 0xa4, 0x01, 0x40, 0x30, 0x22, 0x81, 0x90, 0x78, 
+0xd4, 0xc2, 0x00, 0xa4, 0x01, 0xe0, 0x30, 0x36, 0xa4, 0x01, 0x60, 0x30, 
+0x26, 0xd4, 0xc2, 0x00, 0xa4, 0x01, 0xd0, 0x30, 0x34, 0xa4, 0x01, 0x50, 
+0x30, 0x24, 0xa8, 0x0b, 0x18, 0x13, 0xa8, 0x96, 0x80, 0x93, 0x40, 0x99, 
+0x90, 0x03, 0x00, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1c, 0x50, 
+0x33, 0x9d, 0x24, 0x1c, 0x48, 0x90, 0x38, 0xa4, 0x19, 0xc8, 0x33, 0x4c, 
+0x24, 0x19, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x17, 0x40, 0x32, 0xfb, 
+0x24, 0x17, 0x38, 0x90, 0x38, 0xa4, 0x14, 0x70, 0x32, 0xa4, 0x24, 0x14, 
+0x68, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1c, 0x40, 0x33, 0x86, 
+0x24, 0x1c, 0x38, 0x90, 0x38, 0xa4, 0x19, 0xb8, 0x33, 0x35, 0x24, 0x19, 
+0xb0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x17, 0x30, 0x32, 0xe4, 0x24, 0x17, 
+0x28, 0x90, 0x38, 0xa4, 0x14, 0x60, 0x32, 0x8a, 0x24, 0x14, 0x58, 0xe4, 
+0xe1, 0xc6, 0x00, 0x37, 0x1a, 0x99, 0x90, 0x03, 0x00, 0x90, 0xc0, 0x90, 
+0x60, 0x90, 0x38, 0xa4, 0x1c, 0xe0, 0x33, 0x9a, 0x24, 0x1c, 0xd8, 0x90, 
+0x38, 0xa4, 0x1a, 0x58, 0x33, 0x49, 0x24, 0x1a, 0x50, 0x90, 0x60, 0x90, 
+0x38, 0xa4, 0x17, 0xd0, 0x32, 0xf8, 0x24, 0x17, 0xc8, 0x90, 0x38, 0xa4, 
+0x15, 0x18, 0x32, 0xa1, 0x24, 0x15, 0x10, 0x90, 0xc0, 0x90, 0x60, 0x90, 
+0x38, 0xa4, 0x1c, 0x28, 0x33, 0x83, 0x24, 0x1c, 0x20, 0x90, 0x38, 0xa4, 
+0x19, 0xa0, 0x33, 0x32, 0x24, 0x19, 0x98, 0x90, 0x60, 0x90, 0x38, 0xa4, 
+0x17, 0x18, 0x32, 0xe1, 0x24, 0x17, 0x10, 0x90, 0x38, 0xa4, 0x14, 0x48, 
+0x32, 0x87, 0x24, 0x14, 0x40, 0xe4, 0xe1, 0xc7, 0x80, 0x37, 0x20, 0x93, 
+0x78, 0x99, 0x90, 0x03, 0x00, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 
+0x1c, 0xb0, 0x33, 0x94, 0x24, 0x1c, 0xa8, 0x90, 0x38, 0xa4, 0x1a, 0x28, 
+0x33, 0x43, 0x24, 0x1a, 0x20, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x17, 0xa0, 
+0x32, 0xf2, 0x24, 0x17, 0x98, 0x90, 0x38, 0xa4, 0x14, 0xe8, 0x32, 0x9b, 
+0x24, 0x14, 0xe0, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1c, 0xc8, 
+0x33, 0x97, 0x24, 0x1c, 0xc0, 0x90, 0x38, 0xa4, 0x1a, 0x40, 0x33, 0x46, 
+0x24, 0x1a, 0x38, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x17, 0xb8, 0x32, 0xf5, 
+0x24, 0x17, 0xb0, 0x90, 0x38, 0xa4, 0x15, 0x00, 0x32, 0x9e, 0x24, 0x14, 
+0xf8, 0xec, 0xa1, 0x74, 0x40, 0x02, 0x00, 0x35, 0xcf, 0xa4, 0x39, 0x20, 
+0x37, 0x26, 0x88, 0x00, 0x88, 0x10, 0x10, 0x10, 0x10, 0x90, 0x38, 0xa4, 
+0x14, 0x88, 0x32, 0x8f, 0x24, 0x14, 0x80, 0xe9, 0x61, 0x75, 0x40, 0x02, 
+0x00, 0x35, 0xd6, 0xe3, 0x61, 0xca, 0x80, 0x37, 0x2c, 0x95, 0x08, 0x93, 
+0x40, 0x99, 0x90, 0x03, 0x00, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 
+0x1c, 0x80, 0x33, 0x8e, 0x24, 0x1c, 0x78, 0x90, 0x38, 0xa4, 0x19, 0xf8, 
+0x33, 0x3d, 0x24, 0x19, 0xf0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x17, 0x70, 
+0x32, 0xec, 0x24, 0x17, 0x68, 0x90, 0x38, 0xa4, 0x14, 0xb8, 0x32, 0x95, 
+0x24, 0x14, 0xb0, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x1c, 0x68, 
+0x33, 0x8b, 0x24, 0x1c, 0x60, 0x90, 0x38, 0xa4, 0x19, 0xe0, 0x33, 0x3a, 
+0x24, 0x19, 0xd8, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x17, 0x58, 0x32, 0xe9, 
+0x24, 0x17, 0x50, 0x90, 0x38, 0xa4, 0x14, 0xa0, 0x32, 0x92, 0x24, 0x14, 
+0x98, 0xe4, 0xe1, 0xc6, 0x40, 0x37, 0x1c, 0x88, 0x01, 0x88, 0x90, 0xc0, 
+0x90, 0x60, 0x90, 0x38, 0xa4, 0x1c, 0x98, 0x33, 0x91, 0x24, 0x1c, 0x90, 
+0x90, 0x38, 0xa4, 0x1a, 0x10, 0x33, 0x40, 0x24, 0x1a, 0x08, 0x90, 0x60, 
+0x90, 0x38, 0xa4, 0x17, 0x88, 0x32, 0xef, 0x24, 0x17, 0x80, 0x90, 0x38, 
+0xa4, 0x14, 0xd0, 0x32, 0x98, 0x24, 0x14, 0xc8, 0xe4, 0xe1, 0xc7, 0xc0, 
+0x37, 0x22, 0x92, 0xd0, 0x99, 0x50, 0x02, 0x80, 0x90, 0xa0, 0x90, 0x50, 
+0x90, 0x28, 0x80, 0x30, 0x76, 0x24, 0x03, 0xa8, 0x90, 0x28, 0x80, 0x30, 
+0x6e, 0x24, 0x03, 0x68, 0x90, 0x50, 0x90, 0x28, 0x80, 0x30, 0x66, 0x24, 
+0x03, 0x28, 0x90, 0x28, 0x80, 0x30, 0x5c, 0x24, 0x02, 0xd8, 0x90, 0xa0, 
+0x90, 0x50, 0x90, 0x28, 0x80, 0x30, 0x73, 0x24, 0x03, 0xa0, 0x90, 0x28, 
+0x80, 0x30, 0x6b, 0x24, 0x03, 0x60, 0x90, 0x50, 0x90, 0x28, 0x80, 0x30, 
+0x63, 0x24, 0x03, 0x20, 0x90, 0x28, 0x80, 0x30, 0x59, 0x24, 0x02, 0xd0, 
+0xec, 0xe1, 0xc9, 0x60, 0x1f, 0x00, 0x37, 0x28, 0x88, 0x00, 0x78, 0x10, 
+0x10, 0x10, 0x10, 0x90, 0x28, 0x80, 0x30, 0x57, 0x24, 0x02, 0xc0, 0xec, 
+0xe1, 0xca, 0xe1, 0x75, 0x00, 0x37, 0x2e, 0xe5, 0xa1, 0x69, 0xc0, 0x35, 
+0xa5, 0xa0, 0x2a, 0x10, 0xa8, 0x16, 0x60, 0x29, 0xd8, 0xa0, 0x0c, 0x48, 
+0xa0, 0x0a, 0xc8, 0x95, 0x60, 0x92, 0xb0, 0x91, 0x40, 0x90, 0x88, 0x90, 
+0x50, 0x90, 0x28, 0x80, 0x32, 0x11, 0x80, 0x32, 0x07, 0x10, 0x10, 0x80, 
+0x32, 0x06, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0e, 0xd8, 0x32, 0x7d, 0xa4, 
+0x0e, 0x88, 0x32, 0x73, 0x10, 0x10, 0xa4, 0x0e, 0x80, 0x32, 0x72, 0x90, 
+0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0c, 0x98, 0x31, 0x6f, 0xa4, 0x0c, 
+0x48, 0x31, 0x65, 0x10, 0x10, 0xa4, 0x0c, 0x40, 0x31, 0x64, 0x90, 0x70, 
+0x90, 0x38, 0xa4, 0x0d, 0xb8, 0x32, 0x47, 0xa4, 0x0d, 0x68, 0x32, 0x3d, 
+0x10, 0x10, 0xa4, 0x0d, 0x60, 0x32, 0x3c, 0x91, 0x40, 0x90, 0x88, 0x90, 
+0x50, 0x90, 0x28, 0x80, 0x32, 0x03, 0x80, 0x32, 0x05, 0x10, 0x10, 0x80, 
+0x32, 0x04, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0e, 0x68, 0x32, 0x6f, 0xa4, 
+0x0e, 0x78, 0x32, 0x71, 0x10, 0x10, 0xa4, 0x0e, 0x70, 0x32, 0x70, 0x90, 
+0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0c, 0x28, 0x31, 0x61, 0xa4, 0x0c, 
+0x38, 0x31, 0x63, 0x10, 0x10, 0xa4, 0x0c, 0x30, 0x31, 0x62, 0x90, 0x70, 
+0x90, 0x38, 0xa4, 0x0d, 0x48, 0x32, 0x39, 0xa4, 0x0d, 0x58, 0x32, 0x3b, 
+0x10, 0x10, 0xa4, 0x0d, 0x50, 0x32, 0x3a, 0x92, 0xb0, 0x91, 0x40, 0x90, 
+0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 0x0e, 0x80, 0x32, 0x10, 0x10, 
+0x10, 0x80, 0x32, 0x0f, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0e, 0xc0, 0x32, 
+0x7a, 0xa4, 0x0e, 0xd0, 0x32, 0x7c, 0x10, 0x10, 0xa4, 0x0e, 0xc8, 0x32, 
+0x7b, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0c, 0x80, 0x31, 0x6c, 
+0xa4, 0x0c, 0x90, 0x31, 0x6e, 0x10, 0x10, 0xa4, 0x0c, 0x88, 0x31, 0x6d, 
+0x90, 0x70, 0x90, 0x38, 0xa4, 0x0d, 0xa0, 0x32, 0x44, 0xa4, 0x0d, 0xb0, 
+0x32, 0x46, 0x10, 0x10, 0xa4, 0x0d, 0xa8, 0x32, 0x45, 0x91, 0x40, 0x90, 
+0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 0x00, 0x80, 0x32, 0x02, 0x10, 
+0x10, 0x80, 0x32, 0x01, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0e, 0x50, 0x32, 
+0x6c, 0xa4, 0x0e, 0x60, 0x32, 0x6e, 0x10, 0x10, 0xa4, 0x0e, 0x58, 0x32, 
+0x6d, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0c, 0x10, 0x31, 0x5e, 
+0xa4, 0x0c, 0x20, 0x31, 0x60, 0x10, 0x10, 0xa4, 0x0c, 0x18, 0x31, 0x5f, 
+0x90, 0x70, 0x90, 0x38, 0xa4, 0x0d, 0x30, 0x32, 0x36, 0xa4, 0x0d, 0x40, 
+0x32, 0x38, 0x10, 0x10, 0xa4, 0x0d, 0x38, 0x32, 0x37, 0x10, 0x10, 0x90, 
+0xa8, 0x10, 0x10, 0x10, 0x10, 0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 0x84, 
+0x80, 0x32, 0x86, 0x10, 0x10, 0x80, 0x32, 0x85, 0x90, 0x60, 0x90, 0x30, 
+0x60, 0xa0, 0x20, 0x80, 0x60, 0xa0, 0x21, 0x00, 0x90, 0x30, 0x60, 0xa0, 
+0x20, 0xc0, 0x60, 0xa0, 0x21, 0x40, 0x97, 0xf0, 0x95, 0x60, 0x92, 0xb0, 
+0x91, 0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 0x0b, 0x80, 
+0x32, 0x0d, 0x10, 0x10, 0x80, 0x32, 0x0c, 0x90, 0x70, 0x90, 0x38, 0xa4, 
+0x0e, 0xa8, 0x32, 0x77, 0xa4, 0x0e, 0xb8, 0x32, 0x79, 0x10, 0x10, 0xa4, 
+0x0e, 0xb0, 0x32, 0x78, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0c, 
+0x68, 0x31, 0x69, 0xa4, 0x0c, 0x78, 0x31, 0x6b, 0x10, 0x10, 0xa4, 0x0c, 
+0x70, 0x31, 0x6a, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0d, 0x88, 0x32, 0x41, 
+0xa4, 0x0d, 0x98, 0x32, 0x43, 0x10, 0x10, 0xa4, 0x0d, 0x90, 0x32, 0x42, 
+0x91, 0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x32, 0x08, 0x80, 
+0x32, 0x0a, 0x10, 0x10, 0x80, 0x32, 0x09, 0x90, 0x70, 0x90, 0x38, 0xa4, 
+0x0e, 0x90, 0x32, 0x74, 0xa4, 0x0e, 0xa0, 0x32, 0x76, 0x10, 0x10, 0xa4, 
+0x0e, 0x98, 0x32, 0x75, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0c, 
+0x50, 0x31, 0x66, 0xa4, 0x0c, 0x60, 0x31, 0x68, 0x10, 0x10, 0xa4, 0x0c, 
+0x58, 0x31, 0x67, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0d, 0x70, 0x32, 0x3e, 
+0xa4, 0x0d, 0x80, 0x32, 0x40, 0x10, 0x10, 0xa4, 0x0d, 0x78, 0x32, 0x3f, 
+0x10, 0x10, 0x91, 0x40, 0x90, 0xa0, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 
+0x39, 0x80, 0x31, 0x2c, 0x90, 0x28, 0x80, 0x31, 0x2b, 0x80, 0x31, 0x2a, 
+0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0x35, 0x80, 0x31, 0x38, 0x90, 0x28, 
+0x80, 0x31, 0x37, 0x80, 0x31, 0x36, 0x90, 0xa0, 0x90, 0x50, 0x90, 0x28, 
+0x80, 0x31, 0x2d, 0x80, 0x31, 0x30, 0x90, 0x28, 0x80, 0x31, 0x2f, 0x80, 
+0x31, 0x2e, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0x31, 0x80, 0x31, 0x34, 
+0x90, 0x28, 0x80, 0x31, 0x33, 0x80, 0x31, 0x32, 0x91, 0x88, 0x80, 0x90, 
+0xc0, 0x90, 0x60, 0x90, 0x28, 0x81, 0x30, 0x4a, 0x10, 0x10, 0x80, 0x30, 
+0x49, 0x90, 0x28, 0x81, 0x30, 0x52, 0x10, 0x10, 0x80, 0x30, 0x51, 0x90, 
+0x60, 0x90, 0x28, 0x81, 0x30, 0x46, 0x10, 0x10, 0x80, 0x30, 0x45, 0x90, 
+0x28, 0x81, 0x30, 0x4e, 0x10, 0x10, 0x80, 0x30, 0x4d, 0x80, 0x10, 0x10, 
+0x10, 0x10, 0x90, 0x28, 0x81, 0x30, 0x55, 0x10, 0x10, 0x80, 0x30, 0x56, 
+0xa0, 0x0b, 0x90, 0xa0, 0x0a, 0xc8, 0x95, 0x60, 0x92, 0xb0, 0x91, 0x40, 
+0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0xff, 0x80, 0x31, 0xf5, 
+0x10, 0x10, 0x80, 0x31, 0xf4, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0e, 0x48, 
+0x32, 0x6b, 0xa4, 0x0d, 0xf8, 0x32, 0x61, 0x10, 0x10, 0xa4, 0x0d, 0xf0, 
+0x32, 0x60, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0c, 0x08, 0x31, 
+0x5d, 0xa4, 0x0b, 0xb8, 0x31, 0x53, 0x10, 0x10, 0xa4, 0x0b, 0xb0, 0x31, 
+0x52, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0d, 0x28, 0x32, 0x35, 0xa4, 0x0c, 
+0xd8, 0x32, 0x2b, 0x10, 0x10, 0xa4, 0x0c, 0xd0, 0x32, 0x2a, 0x91, 0x40, 
+0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0xf1, 0x80, 0x31, 0xf3, 
+0x10, 0x10, 0x80, 0x31, 0xf2, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0d, 0xd8, 
+0x32, 0x5d, 0xa4, 0x0d, 0xe8, 0x32, 0x5f, 0x10, 0x10, 0xa4, 0x0d, 0xe0, 
+0x32, 0x5e, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0b, 0x98, 0x31, 
+0x4f, 0xa4, 0x0b, 0xa8, 0x31, 0x51, 0x10, 0x10, 0xa4, 0x0b, 0xa0, 0x31, 
+0x50, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0c, 0xb8, 0x32, 0x27, 0xa4, 0x0c, 
+0xc8, 0x32, 0x29, 0x10, 0x10, 0xa4, 0x0c, 0xc0, 0x32, 0x28, 0x92, 0xb0, 
+0x91, 0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0xfc, 0x80, 
+0x31, 0xfe, 0x10, 0x10, 0x80, 0x31, 0xfd, 0x90, 0x70, 0x90, 0x38, 0xa4, 
+0x0e, 0x30, 0x32, 0x68, 0xa4, 0x0e, 0x40, 0x32, 0x6a, 0x10, 0x10, 0xa4, 
+0x0e, 0x38, 0x32, 0x69, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0b, 
+0xf0, 0x31, 0x5a, 0xa4, 0x0c, 0x00, 0x31, 0x5c, 0x10, 0x10, 0xa4, 0x0b, 
+0xf8, 0x31, 0x5b, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0d, 0x10, 0x32, 0x32, 
+0xa4, 0x0d, 0x20, 0x32, 0x34, 0x10, 0x10, 0xa4, 0x0d, 0x18, 0x32, 0x33, 
+0x91, 0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0xee, 0x80, 
+0x31, 0xf0, 0x10, 0x10, 0x80, 0x31, 0xef, 0x90, 0x70, 0x90, 0x38, 0xa4, 
+0x0d, 0xc0, 0x32, 0x5a, 0xa4, 0x0d, 0xd0, 0x32, 0x5c, 0x10, 0x10, 0xa4, 
+0x0d, 0xc8, 0x32, 0x5b, 0x90, 0xb8, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0b, 
+0x80, 0x31, 0x4c, 0xa4, 0x0b, 0x90, 0x31, 0x4e, 0x10, 0x10, 0xa4, 0x0b, 
+0x88, 0x31, 0x4d, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0c, 0xa0, 0x32, 0x24, 
+0xa4, 0x0c, 0xb0, 0x32, 0x26, 0x10, 0x10, 0xa4, 0x0c, 0xa8, 0x32, 0x25, 
+0x10, 0x10, 0x80, 0x10, 0x10, 0x10, 0x10, 0x90, 0x50, 0x90, 0x28, 0x80, 
+0x32, 0x81, 0x80, 0x32, 0x83, 0x10, 0x10, 0x80, 0x32, 0x82, 0x80, 0x95, 
+0x60, 0x92, 0xb0, 0x91, 0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 
+0x31, 0xf9, 0x80, 0x31, 0xfb, 0x10, 0x10, 0x80, 0x31, 0xfa, 0x90, 0x70, 
+0x90, 0x38, 0xa4, 0x0e, 0x18, 0x32, 0x65, 0xa4, 0x0e, 0x28, 0x32, 0x67, 
+0x10, 0x10, 0xa4, 0x0e, 0x20, 0x32, 0x66, 0x90, 0xb8, 0x90, 0x70, 0x90, 
+0x38, 0xa4, 0x0b, 0xd8, 0x31, 0x57, 0xa4, 0x0b, 0xe8, 0x31, 0x59, 0x10, 
+0x10, 0xa4, 0x0b, 0xe0, 0x31, 0x58, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0c, 
+0xf8, 0x32, 0x2f, 0xa4, 0x0d, 0x08, 0x32, 0x31, 0x10, 0x10, 0xa4, 0x0d, 
+0x00, 0x32, 0x30, 0x91, 0x40, 0x90, 0x88, 0x90, 0x50, 0x90, 0x28, 0x80, 
+0x31, 0xf6, 0x80, 0x31, 0xf8, 0x10, 0x10, 0x80, 0x31, 0xf7, 0x90, 0x70, 
+0x90, 0x38, 0xa4, 0x0e, 0x00, 0x32, 0x62, 0xa4, 0x0e, 0x10, 0x32, 0x64, 
+0x10, 0x10, 0xa4, 0x0e, 0x08, 0x32, 0x63, 0x90, 0xb8, 0x90, 0x70, 0x90, 
+0x38, 0xa4, 0x0b, 0xc0, 0x31, 0x54, 0xa4, 0x0b, 0xd0, 0x31, 0x56, 0x10, 
+0x10, 0xa4, 0x0b, 0xc8, 0x31, 0x55, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x0c, 
+0xe0, 0x32, 0x2c, 0xa4, 0x0c, 0xf0, 0x32, 0x2e, 0x10, 0x10, 0xa4, 0x0c, 
+0xe8, 0x32, 0x2d, 0x10, 0x10, 0x91, 0x40, 0x90, 0xa0, 0x90, 0x50, 0x90, 
+0x28, 0x80, 0x31, 0x29, 0x80, 0x31, 0x1c, 0x90, 0x28, 0x80, 0x31, 0x1b, 
+0x80, 0x31, 0x1a, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0x25, 0x80, 0x31, 
+0x28, 0x90, 0x28, 0x80, 0x31, 0x27, 0x80, 0x31, 0x26, 0x90, 0xa0, 0x90, 
+0x50, 0x90, 0x28, 0x80, 0x31, 0x1d, 0x80, 0x31, 0x20, 0x90, 0x28, 0x80, 
+0x31, 0x1f, 0x80, 0x31, 0x1e, 0x90, 0x50, 0x90, 0x28, 0x80, 0x31, 0x21, 
+0x80, 0x31, 0x24, 0x90, 0x28, 0x80, 0x31, 0x23, 0x80, 0x31, 0x22, 0xc3, 
+0xc0, 0x30, 0xd1, 0x9c, 0xe8, 0x07, 0x60, 0x91, 0x90, 0x90, 0xf0, 0x10, 
+0x10, 0x80, 0x88, 0x00, 0x80, 0x90, 0x50, 0x90, 0x28, 0x80, 0x30, 0x9e, 
+0x80, 0x30, 0x9f, 0x81, 0x30, 0xa4, 0xd0, 0x41, 0x80, 0x24, 0x05, 0x48, 
+0x24, 0x05, 0x50, 0x10, 0x10, 0x80, 0x90, 0x58, 0x80, 0x90, 0x28, 0x24, 
+0x04, 0xe0, 0x24, 0x04, 0xe8, 0x81, 0x24, 0x05, 0x40, 0x92, 0x68, 0x91, 
+0x00, 0x80, 0x90, 0x90, 0x90, 0x30, 0x80, 0x24, 0x05, 0x70, 0x90, 0x38, 
+0xa4, 0x05, 0x80, 0x30, 0x1c, 0x80, 0x30, 0x1b, 0x80, 0x90, 0x28, 0x80, 
+0x31, 0x04, 0xa4, 0x05, 0x28, 0x31, 0x05, 0x80, 0x90, 0xc0, 0x90, 0x60, 
+0x90, 0x28, 0x80, 0x30, 0xc6, 0xa4, 0x05, 0x68, 0x30, 0xc7, 0x90, 0x28, 
+0x80, 0x30, 0x1a, 0xa4, 0x05, 0x78, 0x30, 0x19, 0x90, 0x50, 0x90, 0x28, 
+0x80, 0x31, 0x02, 0x80, 0x31, 0x03, 0x90, 0x28, 0x24, 0x05, 0x58, 0x24, 
+0x05, 0x60, 0x90, 0x58, 0x80, 0x10, 0x10, 0x80, 0x10, 0x10, 0x80, 0x30, 
+0xd0, 0x80, 0x90, 0x40, 0x10, 0x10, 0x80, 0x24, 0x05, 0x18, 0x80, 0x10, 
+0x10, 0x80, 0x30, 0xcf, 0x91, 0x58, 0x91, 0x00, 0x90, 0x80, 0x81, 0x90, 
+0x50, 0x90, 0x28, 0x80, 0x30, 0x9a, 0x80, 0x30, 0x9b, 0x81, 0x30, 0xa2, 
+0x81, 0x90, 0x50, 0x90, 0x28, 0x80, 0x30, 0x7d, 0x80, 0x30, 0x7e, 0x81, 
+0x30, 0x81, 0x83, 0x90, 0x28, 0x24, 0x04, 0xc0, 0x24, 0x04, 0xc8, 0x90, 
+0xe8, 0x81, 0x90, 0x88, 0x90, 0x38, 0x10, 0x10, 0x80, 0x30, 0xc5, 0x90, 
+0x28, 0x80, 0x30, 0x18, 0x80, 0x30, 0x17, 0x80, 0x90, 0x28, 0x80, 0x31, 
+0x00, 0x80, 0x31, 0x01, 0x82, 0x10, 0x10, 0x80, 0x24, 0x05, 0x08, 0x97, 
+0x10, 0x9e, 0x10, 0x06, 0x98, 0x93, 0x00, 0x91, 0x80, 0x90, 0xc0, 0x90, 
+0x60, 0x90, 0x38, 0xa4, 0x0f, 0x18, 0x31, 0xed, 0x24, 0x0f, 0x10, 0x90, 
+0x38, 0xa4, 0x12, 0x78, 0x32, 0x59, 0x24, 0x12, 0x70, 0x90, 0x60, 0x90, 
+0x38, 0xa4, 0x0a, 0x08, 0x31, 0x4b, 0x24, 0x0a, 0x00, 0x90, 0x38, 0xa4, 
+0x10, 0xc8, 0x32, 0x23, 0x24, 0x10, 0xc0, 0x90, 0xc0, 0x90, 0x60, 0x90, 
+0x38, 0xa4, 0x0f, 0x08, 0x31, 0xdf, 0x24, 0x0f, 0x00, 0x90, 0x38, 0xa4, 
+0x12, 0x68, 0x32, 0x4b, 0x24, 0x12, 0x60, 0x90, 0x60, 0x90, 0x38, 0xa4, 
+0x09, 0xf8, 0x31, 0x3d, 0x24, 0x09, 0xf0, 0x90, 0x38, 0xa4, 0x10, 0xb8, 
+0x32, 0x15, 0x24, 0x10, 0xb0, 0x91, 0x80, 0x90, 0xc0, 0x90, 0x60, 0x90, 
+0x38, 0xa4, 0x0f, 0x60, 0x31, 0xea, 0x24, 0x0f, 0x58, 0x90, 0x38, 0xa4, 
+0x12, 0xc0, 0x32, 0x56, 0x24, 0x12, 0xb8, 0x90, 0x60, 0x90, 0x38, 0xa4, 
+0x0a, 0x50, 0x31, 0x48, 0x24, 0x0a, 0x48, 0x90, 0x38, 0xa4, 0x11, 0x10, 
+0x32, 0x20, 0x24, 0x11, 0x08, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 
+0x0e, 0xf0, 0x31, 0xdc, 0x24, 0x0e, 0xe8, 0x90, 0x38, 0xa4, 0x12, 0x50, 
+0x32, 0x48, 0x24, 0x12, 0x48, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x09, 0xe0, 
+0x31, 0x3a, 0x24, 0x09, 0xd8, 0x90, 0x38, 0xa4, 0x10, 0xa0, 0x32, 0x12, 
+0x24, 0x10, 0x98, 0x10, 0x10, 0x80, 0x10, 0x10, 0x10, 0x10, 0x90, 0x38, 
+0xa4, 0x14, 0x00, 0x32, 0x7e, 0x24, 0x13, 0xf8, 0xd7, 0x42, 0x00, 0xa4, 
+0x34, 0xf8, 0x36, 0x9d, 0xa4, 0x35, 0x08, 0x36, 0xa3, 0x9c, 0xe0, 0x06, 
+0x90, 0x93, 0x00, 0x91, 0x80, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 
+0x0f, 0x48, 0x31, 0xe7, 0x24, 0x0f, 0x40, 0x90, 0x38, 0xa4, 0x12, 0xa8, 
+0x32, 0x53, 0x24, 0x12, 0xa0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x0a, 0x38, 
+0x31, 0x45, 0x24, 0x0a, 0x30, 0x90, 0x38, 0xa4, 0x10, 0xf8, 0x32, 0x1d, 
+0x24, 0x10, 0xf0, 0x90, 0xc0, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x0f, 0x30, 
+0x31, 0xe4, 0x24, 0x0f, 0x28, 0x90, 0x38, 0xa4, 0x12, 0x90, 0x32, 0x50, 
+0x24, 0x12, 0x88, 0x90, 0x60, 0x90, 0x38, 0xa4, 0x0a, 0x20, 0x31, 0x42, 
+0x24, 0x0a, 0x18, 0x90, 0x38, 0xa4, 0x10, 0xe0, 0x32, 0x1a, 0x24, 0x10, 
+0xd8, 0x10, 0x10, 0x90, 0xe0, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x08, 0x60, 
+0x31, 0x19, 0xa4, 0x08, 0x50, 0x31, 0x0b, 0x90, 0x38, 0xa4, 0x08, 0xc0, 
+0x31, 0x15, 0xa4, 0x08, 0xb0, 0x31, 0x17, 0x90, 0x70, 0x90, 0x38, 0xa4, 
+0x08, 0x80, 0x31, 0x0d, 0xa4, 0x08, 0x70, 0x31, 0x0f, 0x90, 0x38, 0xa4, 
+0x08, 0xa0, 0x31, 0x11, 0xa4, 0x08, 0x90, 0x31, 0x13, 0x91, 0x48, 0x80, 
+0x90, 0xa0, 0x90, 0x50, 0x90, 0x28, 0x80, 0x30, 0x48, 0x24, 0x02, 0x38, 
+0x90, 0x28, 0x80, 0x30, 0x50, 0x24, 0x02, 0x78, 0x90, 0x50, 0x90, 0x28, 
+0x80, 0x30, 0x44, 0x24, 0x02, 0x18, 0x90, 0x28, 0x80, 0x30, 0x4c, 0x24, 
+0x02, 0x58, 0x80, 0x10, 0x10, 0x10, 0x10, 0x90, 0x28, 0x80, 0x30, 0x53, 
+0x24, 0x02, 0xa0, 0xd7, 0x42, 0x00, 0xa4, 0x35, 0x00, 0x36, 0x9e, 0xa4, 
+0x35, 0x10, 0x36, 0xa4, 0xa0, 0x14, 0x90, 0xa0, 0x10, 0xb8, 0xa0, 0x0c, 
+0x88, 0x9e, 0x88, 0x09, 0xd0, 0x94, 0xf0, 0x90, 0xb0, 0x88, 0x00, 0x68, 
+0x84, 0x10, 0x10, 0xc9, 0xe1, 0x73, 0x00, 0x85, 0x34, 0xff, 0xcb, 0x61, 
+0x38, 0x00, 0x85, 0x34, 0xc7, 0x9a, 0x00, 0x03, 0xf8, 0x91, 0x98, 0x80, 
+0x91, 0x10, 0x90, 0xa0, 0x90, 0x68, 0x90, 0x20, 0x30, 0xc4, 0xc9, 0xe1, 
+0x70, 0x00, 0x85, 0x34, 0xfd, 0xa4, 0x06, 0x18, 0x30, 0xc2, 0x90, 0x38, 
+0xa4, 0x04, 0xa8, 0x30, 0x96, 0xa4, 0x04, 0xa0, 0x30, 0x93, 0x90, 0x48, 
+0x10, 0x10, 0xa4, 0x05, 0xd8, 0x30, 0xbc, 0x10, 0x10, 0x80, 0x30, 0xb8, 
+0x81, 0x10, 0x10, 0x80, 0xa4, 0x05, 0xa8, 0x30, 0xb6, 0x91, 0xb0, 0x91, 
+0x60, 0x90, 0xe0, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x06, 0x00, 0x30, 0xc1, 
+0xa4, 0x05, 0xf8, 0x30, 0xbe, 0x90, 0x38, 0xa4, 0x04, 0x88, 0x30, 0x92, 
+0xa4, 0x04, 0x80, 0x30, 0x8f, 0x90, 0x48, 0x10, 0x10, 0xa4, 0x05, 0xc8, 
+0x30, 0xba, 0x10, 0x10, 0x80, 0x30, 0xb7, 0x90, 0x28, 0x80, 0x30, 0xa0, 
+0x80, 0x30, 0x97, 0x81, 0x10, 0x10, 0x80, 0xa4, 0x05, 0x98, 0x30, 0xb4, 
+0xcb, 0x61, 0x37, 0xc0, 0x85, 0x34, 0xbc, 0x90, 0xd8, 0x88, 0x00, 0x90, 
+0x84, 0x90, 0x38, 0xc1, 0xc0, 0x85, 0x30, 0xff, 0xc9, 0xe1, 0x6f, 0xc0, 
+0x85, 0x34, 0xfb, 0xcb, 0x61, 0x37, 0x80, 0x85, 0x34, 0xbb, 0x88, 0x00, 
+0x68, 0x84, 0x10, 0x10, 0xc9, 0xe1, 0x6f, 0x80, 0x85, 0x34, 0xf9, 0xcb, 
+0x61, 0x37, 0x40, 0x85, 0x34, 0xba, 0x91, 0xf8, 0x90, 0xb0, 0x88, 0x00, 
+0x68, 0x84, 0x10, 0x10, 0xc9, 0xe1, 0x71, 0x40, 0x85, 0x35, 0x09, 0xcb, 
+0x61, 0x38, 0x80, 0x85, 0x34, 0xc0, 0x88, 0x01, 0x00, 0x90, 0xa0, 0x81, 
+0x90, 0x70, 0x80, 0x90, 0x20, 0x30, 0xbd, 0xc9, 0xe1, 0x71, 0x00, 0x85, 
+0x35, 0x07, 0x81, 0x30, 0x8e, 0x81, 0x10, 0x10, 0x80, 0xa4, 0x05, 0x88, 
+0x30, 0xb2, 0xcb, 0x61, 0x39, 0x80, 0x85, 0x34, 0xbf, 0x90, 0xb0, 0x88, 
+0x00, 0x68, 0x84, 0x10, 0x10, 0xc9, 0xe1, 0x70, 0xc0, 0x85, 0x35, 0x05, 
+0xcb, 0x61, 0x39, 0x40, 0x85, 0x34, 0xbe, 0x88, 0x00, 0x68, 0x84, 0x10, 
+0x10, 0xc9, 0xe1, 0x70, 0x80, 0x85, 0x35, 0x03, 0xcb, 0x61, 0x39, 0x00, 
+0x85, 0x34, 0xbd, 0x92, 0x38, 0x81, 0x91, 0x68, 0x91, 0x18, 0x90, 0x80, 
+0x90, 0x40, 0x80, 0xa4, 0x43, 0x28, 0x38, 0x66, 0x80, 0xa4, 0x02, 0x10, 
+0x30, 0x41, 0x90, 0x28, 0x81, 0x38, 0x63, 0x90, 0x38, 0xa4, 0x42, 0xe8, 
+0x38, 0x5f, 0xa4, 0x00, 0x10, 0x30, 0xc9, 0x90, 0x28, 0x80, 0x30, 0x80, 
+0x80, 0x30, 0x7f, 0x80, 0x90, 0x40, 0x10, 0x10, 0x80, 0x24, 0x02, 0x00, 
+0x10, 0x10, 0x90, 0x38, 0xa4, 0x42, 0xe0, 0x38, 0x5e, 0xa4, 0x00, 0x08, 
+0x30, 0xc8, 0x90, 0x50, 0x80, 0xc9, 0xa2, 0x18, 0x40, 0x85, 0x30, 0xfe, 
+0x80, 0x38, 0x62, 0x9a, 0xd0, 0x03, 0xe0, 0x91, 0x60, 0x90, 0xb0, 0x88, 
+0x00, 0x68, 0x84, 0x10, 0x10, 0xc9, 0xe1, 0x72, 0x80, 0x85, 0x35, 0x13, 
+0xcb, 0x61, 0x3a, 0x80, 0x85, 0x34, 0xc5, 0x88, 0x00, 0x68, 0x84, 0x10, 
+0x10, 0xc9, 0xe1, 0x72, 0x40, 0x85, 0x35, 0x11, 0xcb, 0x61, 0x3a, 0x40, 
+0x85, 0x34, 0xc4, 0x90, 0xb0, 0x88, 0x00, 0x68, 0x84, 0x10, 0x10, 0xc9, 
+0xe1, 0x72, 0x00, 0x85, 0x35, 0x0f, 0xcb, 0x61, 0x3a, 0x00, 0x85, 0x34, 
+0xc3, 0x88, 0x00, 0x68, 0x84, 0x10, 0x10, 0xc9, 0xe1, 0x71, 0xc0, 0x85, 
+0x35, 0x0d, 0xcb, 0x61, 0x39, 0xc0, 0x85, 0x34, 0xc2, 0x90, 0x90, 0x90, 
+0x48, 0xcb, 0xa1, 0x0e, 0x40, 0x85, 0x34, 0x24, 0xcb, 0xa1, 0x0e, 0x00, 
+0x85, 0x34, 0x23, 0x90, 0x48, 0xcb, 0xa1, 0x0d, 0xc0, 0x85, 0x34, 0x22, 
+0xcb, 0xa1, 0x0d, 0x80, 0x85, 0x34, 0x21, 0xcb, 0xa2, 0x19, 0x00, 0x80, 
+0x30, 0xfd, 0x92, 0x40, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x8c, 0x25, 
+0x70, 0x84, 0x24, 0x1f, 0xa8, 0x8c, 0x25, 0x68, 0x84, 0x24, 0x1f, 0x50, 
+0x90, 0x48, 0x8c, 0x25, 0x60, 0x84, 0x24, 0x1f, 0x48, 0x8c, 0x25, 0x58, 
+0x84, 0x24, 0x1f, 0x40, 0x90, 0x90, 0x90, 0x48, 0x8c, 0x25, 0x98, 0x84, 
+0x24, 0x1f, 0x70, 0x8c, 0x25, 0x90, 0x84, 0x24, 0x1f, 0x68, 0x90, 0x48, 
+0x8c, 0x25, 0x88, 0x84, 0x24, 0x1f, 0x60, 0x8c, 0x25, 0x80, 0x84, 0x24, 
+0x1f, 0x58, 0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x8c, 0x25, 0xc0, 0x84, 
+0x24, 0x1f, 0x98, 0x8c, 0x25, 0xb8, 0x84, 0x24, 0x1f, 0x90, 0x90, 0x48, 
+0x8c, 0x25, 0xb0, 0x84, 0x24, 0x1f, 0x88, 0x8c, 0x25, 0xa8, 0x84, 0x24, 
+0x1f, 0x80, 0x90, 0x38, 0xa4, 0x20, 0xf0, 0x34, 0x1f, 0xa4, 0x20, 0xe0, 
+0x34, 0x1d, 0xa0, 0x0f, 0x50, 0xa0, 0x09, 0x08, 0x9a, 0x30, 0x04, 0x40, 
+0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x21, 0xa1, 0x00, 
+0x36, 0x80, 0xe5, 0x21, 0x9d, 0x80, 0x36, 0x90, 0xcb, 0x61, 0x27, 0x80, 
+0x85, 0x34, 0x99, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x21, 0x8e, 0x00, 0x36, 
+0x34, 0xe5, 0x21, 0x8a, 0x80, 0x36, 0x44, 0xcb, 0x61, 0x27, 0x40, 0x85, 
+0x34, 0x8e, 0x90, 0x48, 0xcb, 0xa1, 0x27, 0x00, 0x85, 0x34, 0x8d, 0xcb, 
+0xa1, 0x26, 0xc0, 0x85, 0x34, 0x8c, 0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 
+0x00, 0x80, 0xe5, 0x21, 0x99, 0x00, 0x36, 0x6a, 0xe5, 0x21, 0x97, 0x80, 
+0x36, 0x70, 0xcb, 0x61, 0x28, 0xc0, 0x85, 0x34, 0x92, 0x98, 0x50, 0x00, 
+0x80, 0xe5, 0x21, 0x86, 0x00, 0x36, 0x1e, 0xe5, 0x21, 0x84, 0x80, 0x36, 
+0x24, 0xcb, 0x61, 0x28, 0x80, 0x85, 0x34, 0x91, 0x90, 0x48, 0xcb, 0xa1, 
+0x28, 0x40, 0x85, 0x34, 0x90, 0xcb, 0xa1, 0x28, 0x00, 0x85, 0x34, 0x8f, 
+0x92, 0x20, 0x91, 0x30, 0x90, 0xb8, 0xd5, 0x03, 0x00, 0xc0, 0xc0, 0x81, 
+0x8c, 0x37, 0x08, 0x84, 0x37, 0x11, 0xc0, 0xc0, 0x81, 0x8c, 0x36, 0xe8, 
+0x84, 0x37, 0x0d, 0xd5, 0x02, 0x00, 0xc0, 0xc0, 0x81, 0x36, 0xed, 0xc0, 
+0xc0, 0x81, 0x36, 0xe9, 0x90, 0x78, 0xd5, 0x02, 0x00, 0xc0, 0xc0, 0x81, 
+0x36, 0xf9, 0xc0, 0xc0, 0x81, 0x36, 0xf5, 0xd5, 0x02, 0x00, 0xc0, 0xc0, 
+0x81, 0x37, 0x05, 0xc0, 0xc0, 0x81, 0x37, 0x01, 0x91, 0x70, 0x90, 0xd8, 
+0xd5, 0x03, 0x80, 0xc8, 0xe1, 0x92, 0x80, 0x81, 0x8c, 0x37, 0x28, 0x84, 
+0x37, 0x0f, 0xc8, 0xe1, 0x93, 0x80, 0x81, 0x8c, 0x36, 0xf8, 0x84, 0x37, 
+0x0e, 0xd5, 0x02, 0x80, 0xc8, 0xe1, 0x96, 0x00, 0x81, 0x36, 0xf1, 0xc8, 
+0xe1, 0x92, 0x00, 0x81, 0x36, 0xeb, 0x90, 0x98, 0xd5, 0x02, 0x80, 0xc8, 
+0xe1, 0x7f, 0x80, 0x81, 0x36, 0xfd, 0xc8, 0xe1, 0x80, 0x80, 0x81, 0x36, 
+0xf7, 0xd5, 0x02, 0x80, 0xc8, 0xe1, 0x83, 0x00, 0x81, 0x37, 0x09, 0xc8, 
+0xe1, 0x7f, 0x00, 0x81, 0x37, 0x03, 0x9a, 0x30, 0x04, 0x40, 0x91, 0x90, 
+0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x21, 0x9f, 0x00, 0x36, 0x78, 
+0xe5, 0x21, 0x9c, 0x80, 0x36, 0x8c, 0xcb, 0x61, 0x2a, 0x00, 0x85, 0x34, 
+0x97, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x21, 0x8c, 0x00, 0x36, 0x2c, 0xe5, 
+0x21, 0x89, 0x80, 0x36, 0x40, 0xcb, 0x61, 0x29, 0xc0, 0x85, 0x34, 0x96, 
+0x90, 0x48, 0xcb, 0xa1, 0x29, 0x80, 0x85, 0x34, 0x95, 0xcb, 0xa1, 0x29, 
+0x40, 0x85, 0x34, 0x94, 0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 
+0xe5, 0x21, 0x98, 0x00, 0x36, 0x66, 0xe5, 0x21, 0x96, 0x80, 0x36, 0x6c, 
+0xcb, 0x61, 0x06, 0x40, 0x85, 0x34, 0x14, 0x98, 0x50, 0x00, 0x80, 0xe5, 
+0x21, 0x85, 0x00, 0x36, 0x1a, 0xe5, 0x21, 0x83, 0x80, 0x36, 0x20, 0xcb, 
+0x61, 0x06, 0x00, 0x85, 0x34, 0x13, 0x90, 0x48, 0xcb, 0xa1, 0x05, 0xc0, 
+0x85, 0x34, 0x12, 0xcb, 0xa1, 0x05, 0x80, 0x85, 0x34, 0x11, 0x91, 0x00, 
+0x90, 0x80, 0x90, 0x40, 0xe5, 0x21, 0xab, 0x40, 0x36, 0xb3, 0xe5, 0x21, 
+0xae, 0xc0, 0x36, 0xbf, 0x90, 0x40, 0xe5, 0x21, 0xb1, 0x40, 0x36, 0xcb, 
+0xe5, 0x21, 0xb4, 0xc0, 0x36, 0xd7, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x21, 
+0xab, 0x80, 0x36, 0xb5, 0xe5, 0x21, 0xaf, 0x00, 0x36, 0xc1, 0x90, 0x40, 
+0xe5, 0x21, 0xb1, 0x80, 0x36, 0xcd, 0xe5, 0x21, 0xb5, 0x00, 0x36, 0xd9, 
+0x80, 0x99, 0x28, 0x02, 0xf0, 0x8c, 0x1f, 0xe0, 0x90, 0x80, 0x90, 0x40, 
+0xe5, 0x21, 0xa2, 0x80, 0x36, 0x88, 0xe5, 0x21, 0x9d, 0x00, 0x36, 0x8e, 
+0x90, 0x40, 0xe5, 0x21, 0x8f, 0x80, 0x36, 0x3c, 0xe5, 0x21, 0x8a, 0x00, 
+0x36, 0x42, 0x91, 0x48, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x21, 
+0x98, 0x80, 0x36, 0x68, 0xe5, 0x21, 0x97, 0x00, 0x36, 0x6e, 0xcb, 0x60, 
+0x01, 0xc0, 0x85, 0x30, 0x03, 0x90, 0x40, 0xe5, 0x21, 0x85, 0x80, 0x36, 
+0x1c, 0xe5, 0x21, 0x84, 0x00, 0x36, 0x22, 0x90, 0x48, 0xcb, 0xa0, 0x02, 
+0x40, 0x85, 0x30, 0x05, 0xcb, 0xa0, 0x02, 0x80, 0x85, 0x30, 0x06, 0x10, 
+0x10, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x21, 0x95, 0x00, 0x36, 0x52, 0xe5, 
+0x21, 0x91, 0x80, 0x36, 0x56, 0x90, 0x40, 0xe5, 0x21, 0x82, 0x00, 0x36, 
+0x06, 0xe5, 0x21, 0x7e, 0x80, 0x36, 0x0a, 
+};
+
+static const struct ia64_dis_names ia64_dis_names[] = {
+{ 0x1, 389, 0 },
+{ 0x1, 387, 0 },
+{ 0x1, 386, 0 },
+{ 0x4, 385, 1 },
+{ 0x8, 385, 0 },
+{ 0x2, 385, 0 },
+{ 0x1, 385, 0 },
+{ 0x4, 383, 1 },
+{ 0x1, 384, 0 },
+{ 0x2, 383, 0 },
+{ 0x1, 383, 0 },
+{ 0x4, 382, 0 },
+{ 0x2, 382, 0 },
+{ 0x1, 382, 0 },
+{ 0x4, 381, 0 },
+{ 0x2, 381, 0 },
+{ 0x1, 381, 0 },
+{ 0x4, 380, 0 },
+{ 0x2, 380, 0 },
+{ 0x1, 380, 0 },
+{ 0x4, 379, 0 },
+{ 0x2, 379, 0 },
+{ 0x1, 379, 0 },
+{ 0x2, 378, 0 },
+{ 0x1, 378, 0 },
+{ 0x2, 377, 0 },
+{ 0x1, 377, 0 },
+{ 0x2, 376, 0 },
+{ 0x1, 376, 0 },
+{ 0x1, 374, 0 },
+{ 0x2, 372, 1 },
+{ 0x1, 373, 0 },
+{ 0x12, 372, 1 },
+{ 0x11, 373, 0 },
+{ 0xa, 372, 1 },
+{ 0x9, 373, 0 },
+{ 0x1a, 372, 1 },
+{ 0x7, 373, 0 },
+{ 0x6, 372, 1 },
+{ 0x5, 373, 0 },
+{ 0x5, 372, 1 },
+{ 0x12, 373, 0 },
+{ 0xd, 372, 1 },
+{ 0xe, 373, 0 },
+{ 0x3, 372, 1 },
+{ 0xa, 373, 0 },
+{ 0x2, 369, 1 },
+{ 0x1, 370, 0 },
+{ 0x12, 369, 1 },
+{ 0x11, 370, 0 },
+{ 0xa, 369, 1 },
+{ 0x9, 370, 0 },
+{ 0x1a, 369, 1 },
+{ 0x7, 370, 0 },
+{ 0x6, 369, 1 },
+{ 0x5, 370, 0 },
+{ 0x5, 369, 1 },
+{ 0x12, 370, 0 },
+{ 0xd, 369, 1 },
+{ 0xe, 370, 0 },
+{ 0x3, 369, 1 },
+{ 0xa, 370, 0 },
+{ 0x1, 368, 0 },
+{ 0x1, 363, 0 },
+{ 0x1, 362, 0 },
+{ 0x1, 361, 0 },
+{ 0x1, 360, 0 },
+{ 0x2, 359, 0 },
+{ 0x1, 359, 0 },
+{ 0x2, 358, 0 },
+{ 0x1, 358, 0 },
+{ 0x2, 357, 0 },
+{ 0x1, 357, 0 },
+{ 0x2, 356, 0 },
+{ 0x1, 356, 0 },
+{ 0x2, 355, 0 },
+{ 0x1, 355, 0 },
+{ 0x2, 354, 0 },
+{ 0x1, 354, 0 },
+{ 0x2, 353, 0 },
+{ 0x1, 353, 0 },
+{ 0x2, 352, 0 },
+{ 0x1, 352, 0 },
+{ 0x1, 351, 0 },
+{ 0x3, 351, 0 },
+{ 0x1, 350, 0 },
+{ 0x3, 350, 0 },
+{ 0x8, 349, 0 },
+{ 0x18, 349, 0 },
+{ 0x4, 349, 0 },
+{ 0xc, 349, 0 },
+{ 0x2, 349, 0 },
+{ 0x1, 349, 0 },
+{ 0x8, 348, 0 },
+{ 0x18, 348, 0 },
+{ 0x4, 348, 0 },
+{ 0xc, 348, 0 },
+{ 0x2, 348, 0 },
+{ 0x1, 348, 0 },
+{ 0x4, 347, 0 },
+{ 0xc, 347, 0 },
+{ 0x2, 347, 0 },
+{ 0x1, 347, 0 },
+{ 0x4, 346, 0 },
+{ 0xc, 346, 0 },
+{ 0x2, 346, 0 },
+{ 0x1, 346, 0 },
+{ 0x4, 345, 0 },
+{ 0xc, 345, 0 },
+{ 0x2, 345, 0 },
+{ 0x1, 345, 0 },
+{ 0x4, 344, 0 },
+{ 0xc, 344, 0 },
+{ 0x2, 344, 0 },
+{ 0x1, 344, 0 },
+{ 0x4, 343, 0 },
+{ 0xc, 343, 0 },
+{ 0x2, 343, 0 },
+{ 0x1, 343, 0 },
+{ 0x4, 342, 0 },
+{ 0xc, 342, 0 },
+{ 0x2, 342, 0 },
+{ 0x1, 342, 0 },
+{ 0x1, 341, 0 },
+{ 0x1, 339, 0 },
+{ 0x2, 338, 0 },
+{ 0x1, 338, 0 },
+{ 0x1, 336, 0 },
+{ 0x1, 335, 0 },
+{ 0x1, 334, 0 },
+{ 0x8, 332, 0 },
+{ 0x4, 332, 0 },
+{ 0x2, 332, 0 },
+{ 0x1, 332, 0 },
+{ 0x1, 331, 0 },
+{ 0x1, 330, 0 },
+{ 0x1, 329, 0 },
+{ 0x2, 328, 0 },
+{ 0x1, 328, 0 },
+{ 0x2, 326, 0 },
+{ 0x1, 326, 0 },
+{ 0x1, 325, 0 },
+{ 0x1, 324, 0 },
+{ 0x8, 323, 0 },
+{ 0x4, 323, 0 },
+{ 0x2, 323, 0 },
+{ 0x1, 323, 0 },
+{ 0x8, 322, 0 },
+{ 0x4, 322, 0 },
+{ 0x2, 322, 0 },
+{ 0x1, 322, 0 },
+{ 0x1, 321, 0 },
+{ 0x2, 320, 0 },
+{ 0x1, 320, 0 },
+{ 0x2, 319, 0 },
+{ 0x1, 319, 0 },
+{ 0x2, 318, 0 },
+{ 0x1, 318, 0 },
+{ 0x2, 317, 0 },
+{ 0x1, 317, 0 },
+{ 0x1, 316, 0 },
+{ 0x1, 315, 0 },
+{ 0x1, 314, 0 },
+{ 0x1, 313, 0 },
+{ 0x1, 312, 0 },
+{ 0x1, 311, 0 },
+{ 0x2, 308, 0 },
+{ 0x1, 308, 0 },
+{ 0x1, 307, 0 },
+{ 0x2, 306, 0 },
+{ 0x1, 306, 0 },
+{ 0x2, 305, 0 },
+{ 0x1, 305, 0 },
+{ 0x1, 304, 0 },
+{ 0x1, 303, 0 },
+{ 0x1, 302, 0 },
+{ 0x1, 301, 0 },
+{ 0x2, 300, 0 },
+{ 0x1, 300, 0 },
+{ 0x2, 299, 0 },
+{ 0x1, 299, 0 },
+{ 0x2, 298, 0 },
+{ 0x1, 298, 0 },
+{ 0x1, 297, 0 },
+{ 0x1, 296, 0 },
+{ 0x2, 295, 0 },
+{ 0x1, 295, 0 },
+{ 0x2, 294, 0 },
+{ 0x1, 294, 0 },
+{ 0x1, 293, 0 },
+{ 0x8, 292, 0 },
+{ 0x4, 292, 0 },
+{ 0x2, 292, 0 },
+{ 0x1, 292, 0 },
+{ 0x8, 291, 0 },
+{ 0x4, 291, 0 },
+{ 0x1, 291, 0 },
+{ 0x1, 290, 0 },
+{ 0x2, 289, 0 },
+{ 0x1, 289, 0 },
+{ 0x1, 288, 0 },
+{ 0x1, 287, 0 },
+{ 0x1, 283, 1 },
+{ 0x1, 284, 1 },
+{ 0x1, 285, 0 },
+{ 0x1, 282, 0 },
+{ 0x1, 281, 0 },
+{ 0x1, 280, 0 },
+{ 0x1, 279, 0 },
+{ 0x1, 278, 0 },
+{ 0x1, 270, 0 },
+{ 0x1, 269, 0 },
+{ 0x1, 268, 0 },
+{ 0x1, 267, 0 },
+{ 0x1, 266, 0 },
+{ 0x1, 265, 0 },
+{ 0x1, 264, 0 },
+{ 0x1, 263, 0 },
+{ 0x1, 262, 0 },
+{ 0x1, 261, 0 },
+{ 0x1, 260, 0 },
+{ 0x1, 259, 0 },
+{ 0x1, 258, 0 },
+{ 0x1, 257, 0 },
+{ 0x1, 256, 0 },
+{ 0x1, 255, 0 },
+{ 0x1, 254, 0 },
+{ 0x1, 253, 0 },
+{ 0x1, 252, 0 },
+{ 0x1, 251, 0 },
+{ 0x1, 250, 0 },
+{ 0x1, 248, 0 },
+{ 0x1, 247, 1 },
+{ 0x1, 367, 0 },
+{ 0x1, 246, 1 },
+{ 0x1, 340, 0 },
+{ 0x1, 245, 0 },
+{ 0x1, 244, 0 },
+{ 0x1, 243, 1 },
+{ 0x2, 340, 0 },
+{ 0x10, 242, 0 },
+{ 0x30, 242, 0 },
+{ 0x8, 242, 0 },
+{ 0x48, 242, 0 },
+{ 0xc8, 242, 0 },
+{ 0x28, 242, 0 },
+{ 0x18, 242, 0 },
+{ 0x38, 242, 0 },
+{ 0x4, 242, 0 },
+{ 0x2, 242, 0 },
+{ 0x6, 242, 0 },
+{ 0x1, 241, 1 },
+{ 0x1, 242, 0 },
+{ 0x1, 239, 0 },
+{ 0x1, 238, 0 },
+{ 0x1, 237, 0 },
+{ 0x2, 236, 0 },
+{ 0x1, 236, 0 },
+{ 0x2, 235, 0 },
+{ 0x1, 235, 0 },
+{ 0x2, 234, 0 },
+{ 0x1, 234, 0 },
+{ 0x2, 233, 0 },
+{ 0x1, 233, 0 },
+{ 0x1, 232, 1 },
+{ 0x1, 249, 0 },
+{ 0x20, 231, 0 },
+{ 0x10, 231, 0 },
+{ 0x8, 231, 0 },
+{ 0x4, 231, 0 },
+{ 0x44, 231, 0 },
+{ 0x24, 231, 0 },
+{ 0x14, 231, 0 },
+{ 0xc, 231, 0 },
+{ 0x4c, 231, 0 },
+{ 0x2c, 231, 0 },
+{ 0x1c, 231, 0 },
+{ 0x2, 231, 0 },
+{ 0x12, 231, 0 },
+{ 0xa, 231, 0 },
+{ 0x6, 231, 0 },
+{ 0x1, 231, 0 },
+{ 0x20, 230, 0 },
+{ 0x10, 230, 0 },
+{ 0x8, 230, 0 },
+{ 0x4, 230, 0 },
+{ 0x44, 230, 0 },
+{ 0x24, 230, 0 },
+{ 0x14, 230, 0 },
+{ 0xc, 230, 0 },
+{ 0x4c, 230, 0 },
+{ 0x2c, 230, 0 },
+{ 0x1c, 230, 0 },
+{ 0x2, 230, 0 },
+{ 0x12, 230, 0 },
+{ 0xa, 230, 0 },
+{ 0x6, 230, 0 },
+{ 0x1, 230, 0 },
+{ 0x20, 229, 0 },
+{ 0x10, 229, 0 },
+{ 0x8, 229, 0 },
+{ 0x4, 229, 0 },
+{ 0x44, 229, 0 },
+{ 0x24, 229, 0 },
+{ 0x14, 229, 0 },
+{ 0xc, 229, 0 },
+{ 0x4c, 229, 0 },
+{ 0x2c, 229, 0 },
+{ 0x1c, 229, 0 },
+{ 0x2, 229, 0 },
+{ 0x12, 229, 0 },
+{ 0xa, 229, 0 },
+{ 0x6, 229, 0 },
+{ 0x1, 229, 0 },
+{ 0x40, 228, 0 },
+{ 0x140, 228, 0 },
+{ 0xc0, 228, 0 },
+{ 0x20, 228, 0 },
+{ 0xa0, 228, 0 },
+{ 0x60, 228, 0 },
+{ 0x10, 228, 0 },
+{ 0x8, 228, 0 },
+{ 0x14, 228, 0 },
+{ 0x54, 228, 0 },
+{ 0x34, 228, 0 },
+{ 0xc, 228, 0 },
+{ 0x2c, 228, 0 },
+{ 0x1c, 228, 0 },
+{ 0x2, 228, 0 },
+{ 0xa, 228, 0 },
+{ 0x6, 228, 0 },
+{ 0x1, 228, 0 },
+{ 0x40, 227, 0 },
+{ 0x140, 227, 0 },
+{ 0xc0, 227, 0 },
+{ 0x20, 227, 0 },
+{ 0xa0, 227, 0 },
+{ 0x60, 227, 0 },
+{ 0x10, 227, 0 },
+{ 0x8, 227, 0 },
+{ 0x14, 227, 0 },
+{ 0x54, 227, 0 },
+{ 0x34, 227, 0 },
+{ 0xc, 227, 0 },
+{ 0x2c, 227, 0 },
+{ 0x1c, 227, 0 },
+{ 0x2, 227, 0 },
+{ 0xa, 227, 0 },
+{ 0x6, 227, 0 },
+{ 0x1, 227, 0 },
+{ 0x40, 226, 0 },
+{ 0x140, 226, 0 },
+{ 0xc0, 226, 0 },
+{ 0x20, 226, 0 },
+{ 0xa0, 226, 0 },
+{ 0x60, 226, 0 },
+{ 0x10, 226, 0 },
+{ 0x8, 226, 0 },
+{ 0x14, 226, 0 },
+{ 0x54, 226, 0 },
+{ 0x34, 226, 0 },
+{ 0xc, 226, 0 },
+{ 0x2c, 226, 0 },
+{ 0x1c, 226, 0 },
+{ 0x2, 226, 0 },
+{ 0xa, 226, 0 },
+{ 0x6, 226, 0 },
+{ 0x1, 226, 0 },
+{ 0x40, 225, 0 },
+{ 0x140, 225, 0 },
+{ 0xc0, 225, 0 },
+{ 0x20, 225, 0 },
+{ 0xa0, 225, 0 },
+{ 0x60, 225, 0 },
+{ 0x10, 225, 0 },
+{ 0x8, 225, 0 },
+{ 0x14, 225, 0 },
+{ 0x54, 225, 0 },
+{ 0x34, 225, 0 },
+{ 0xc, 225, 0 },
+{ 0x2c, 225, 0 },
+{ 0x1c, 225, 0 },
+{ 0x2, 225, 0 },
+{ 0xa, 225, 0 },
+{ 0x6, 225, 0 },
+{ 0x1, 225, 0 },
+{ 0x40, 224, 0 },
+{ 0x140, 224, 0 },
+{ 0xc0, 224, 0 },
+{ 0x20, 224, 0 },
+{ 0xa0, 224, 0 },
+{ 0x60, 224, 0 },
+{ 0x10, 224, 0 },
+{ 0x8, 224, 0 },
+{ 0x14, 224, 0 },
+{ 0x54, 224, 0 },
+{ 0x34, 224, 0 },
+{ 0xc, 224, 0 },
+{ 0x2c, 224, 0 },
+{ 0x1c, 224, 0 },
+{ 0x2, 224, 0 },
+{ 0xa, 224, 0 },
+{ 0x6, 224, 0 },
+{ 0x1, 224, 0 },
+{ 0x40, 223, 0 },
+{ 0x140, 223, 0 },
+{ 0xc0, 223, 0 },
+{ 0x20, 223, 0 },
+{ 0xa0, 223, 0 },
+{ 0x60, 223, 0 },
+{ 0x10, 223, 0 },
+{ 0x8, 223, 0 },
+{ 0x14, 223, 0 },
+{ 0x54, 223, 0 },
+{ 0x34, 223, 0 },
+{ 0xc, 223, 0 },
+{ 0x2c, 223, 0 },
+{ 0x1c, 223, 0 },
+{ 0x2, 223, 0 },
+{ 0xa, 223, 0 },
+{ 0x6, 223, 0 },
+{ 0x1, 223, 0 },
+{ 0x40, 222, 0 },
+{ 0x140, 222, 0 },
+{ 0xc0, 222, 0 },
+{ 0x20, 222, 0 },
+{ 0xa0, 222, 0 },
+{ 0x60, 222, 0 },
+{ 0x10, 222, 0 },
+{ 0x8, 222, 0 },
+{ 0x14, 222, 0 },
+{ 0x54, 222, 0 },
+{ 0x34, 222, 0 },
+{ 0xc, 222, 0 },
+{ 0x2c, 222, 0 },
+{ 0x1c, 222, 0 },
+{ 0x2, 222, 0 },
+{ 0xa, 222, 0 },
+{ 0x6, 222, 0 },
+{ 0x1, 222, 0 },
+{ 0x40, 221, 0 },
+{ 0x140, 221, 0 },
+{ 0xc0, 221, 0 },
+{ 0x20, 221, 0 },
+{ 0xa0, 221, 0 },
+{ 0x60, 221, 0 },
+{ 0x10, 221, 0 },
+{ 0x8, 221, 0 },
+{ 0x14, 221, 0 },
+{ 0x54, 221, 0 },
+{ 0x34, 221, 0 },
+{ 0xc, 221, 0 },
+{ 0x2c, 221, 0 },
+{ 0x1c, 221, 0 },
+{ 0x2, 221, 0 },
+{ 0xa, 221, 0 },
+{ 0x6, 221, 0 },
+{ 0x1, 221, 0 },
+{ 0x40, 220, 0 },
+{ 0x140, 220, 0 },
+{ 0xc0, 220, 0 },
+{ 0x20, 220, 0 },
+{ 0xa0, 220, 0 },
+{ 0x60, 220, 0 },
+{ 0x10, 220, 0 },
+{ 0x8, 220, 0 },
+{ 0x14, 220, 0 },
+{ 0x54, 220, 0 },
+{ 0x34, 220, 0 },
+{ 0xc, 220, 0 },
+{ 0x2c, 220, 0 },
+{ 0x1c, 220, 0 },
+{ 0x2, 220, 0 },
+{ 0xa, 220, 0 },
+{ 0x6, 220, 0 },
+{ 0x1, 220, 0 },
+{ 0x40, 219, 0 },
+{ 0x140, 219, 0 },
+{ 0xc0, 219, 0 },
+{ 0x20, 219, 0 },
+{ 0xa0, 219, 0 },
+{ 0x60, 219, 0 },
+{ 0x10, 219, 0 },
+{ 0x8, 219, 0 },
+{ 0x14, 219, 0 },
+{ 0x54, 219, 0 },
+{ 0x34, 219, 0 },
+{ 0xc, 219, 0 },
+{ 0x2c, 219, 0 },
+{ 0x1c, 219, 0 },
+{ 0x2, 219, 0 },
+{ 0xa, 219, 0 },
+{ 0x6, 219, 0 },
+{ 0x1, 219, 0 },
+{ 0x40, 218, 0 },
+{ 0x140, 218, 0 },
+{ 0xc0, 218, 0 },
+{ 0x20, 218, 0 },
+{ 0xa0, 218, 0 },
+{ 0x60, 218, 0 },
+{ 0x10, 218, 0 },
+{ 0x8, 218, 0 },
+{ 0x14, 218, 0 },
+{ 0x54, 218, 0 },
+{ 0x34, 218, 0 },
+{ 0xc, 218, 0 },
+{ 0x2c, 218, 0 },
+{ 0x1c, 218, 0 },
+{ 0x2, 218, 0 },
+{ 0xa, 218, 0 },
+{ 0x6, 218, 0 },
+{ 0x1, 218, 0 },
+{ 0x40, 217, 0 },
+{ 0x140, 217, 0 },
+{ 0xc0, 217, 0 },
+{ 0x20, 217, 0 },
+{ 0xa0, 217, 0 },
+{ 0x60, 217, 0 },
+{ 0x10, 217, 0 },
+{ 0x8, 217, 0 },
+{ 0x14, 217, 0 },
+{ 0x54, 217, 0 },
+{ 0x34, 217, 0 },
+{ 0xc, 217, 0 },
+{ 0x2c, 217, 0 },
+{ 0x1c, 217, 0 },
+{ 0x2, 217, 0 },
+{ 0xa, 217, 0 },
+{ 0x6, 217, 0 },
+{ 0x1, 217, 0 },
+{ 0x40, 216, 0 },
+{ 0x140, 216, 0 },
+{ 0xc0, 216, 0 },
+{ 0x20, 216, 0 },
+{ 0xa0, 216, 0 },
+{ 0x60, 216, 0 },
+{ 0x10, 216, 0 },
+{ 0x8, 216, 0 },
+{ 0x14, 216, 0 },
+{ 0x54, 216, 0 },
+{ 0x34, 216, 0 },
+{ 0xc, 216, 0 },
+{ 0x2c, 216, 0 },
+{ 0x1c, 216, 0 },
+{ 0x2, 216, 0 },
+{ 0xa, 216, 0 },
+{ 0x6, 216, 0 },
+{ 0x1, 216, 0 },
+{ 0x40, 215, 0 },
+{ 0x140, 215, 0 },
+{ 0xc0, 215, 0 },
+{ 0x20, 215, 0 },
+{ 0xa0, 215, 0 },
+{ 0x60, 215, 0 },
+{ 0x10, 215, 0 },
+{ 0x8, 215, 0 },
+{ 0x14, 215, 0 },
+{ 0x54, 215, 0 },
+{ 0x34, 215, 0 },
+{ 0xc, 215, 0 },
+{ 0x2c, 215, 0 },
+{ 0x1c, 215, 0 },
+{ 0x2, 215, 0 },
+{ 0xa, 215, 0 },
+{ 0x6, 215, 0 },
+{ 0x1, 215, 0 },
+{ 0x40, 214, 0 },
+{ 0x140, 214, 0 },
+{ 0xc0, 214, 0 },
+{ 0x20, 214, 0 },
+{ 0xa0, 214, 0 },
+{ 0x60, 214, 0 },
+{ 0x10, 214, 0 },
+{ 0x8, 214, 0 },
+{ 0x14, 214, 0 },
+{ 0x54, 214, 0 },
+{ 0x34, 214, 0 },
+{ 0xc, 214, 0 },
+{ 0x2c, 214, 0 },
+{ 0x1c, 214, 0 },
+{ 0x2, 214, 0 },
+{ 0xa, 214, 0 },
+{ 0x6, 214, 0 },
+{ 0x1, 214, 0 },
+{ 0x40, 213, 0 },
+{ 0x140, 213, 0 },
+{ 0xc0, 213, 0 },
+{ 0x20, 213, 0 },
+{ 0xa0, 213, 0 },
+{ 0x60, 213, 0 },
+{ 0x10, 213, 0 },
+{ 0x8, 213, 0 },
+{ 0x14, 213, 0 },
+{ 0x54, 213, 0 },
+{ 0x34, 213, 0 },
+{ 0xc, 213, 0 },
+{ 0x2c, 213, 0 },
+{ 0x1c, 213, 0 },
+{ 0x2, 213, 0 },
+{ 0xa, 213, 0 },
+{ 0x6, 213, 0 },
+{ 0x1, 213, 0 },
+{ 0x40, 212, 0 },
+{ 0x140, 212, 0 },
+{ 0xc0, 212, 0 },
+{ 0x20, 212, 0 },
+{ 0xa0, 212, 0 },
+{ 0x60, 212, 0 },
+{ 0x10, 212, 0 },
+{ 0x8, 212, 0 },
+{ 0x14, 212, 0 },
+{ 0x54, 212, 0 },
+{ 0x34, 212, 0 },
+{ 0xc, 212, 0 },
+{ 0x2c, 212, 0 },
+{ 0x1c, 212, 0 },
+{ 0x2, 212, 0 },
+{ 0xa, 212, 0 },
+{ 0x6, 212, 0 },
+{ 0x1, 212, 0 },
+{ 0x40, 211, 0 },
+{ 0x140, 211, 0 },
+{ 0xc0, 211, 0 },
+{ 0x20, 211, 0 },
+{ 0xa0, 211, 0 },
+{ 0x60, 211, 0 },
+{ 0x10, 211, 0 },
+{ 0x8, 211, 0 },
+{ 0x14, 211, 0 },
+{ 0x54, 211, 0 },
+{ 0x34, 211, 0 },
+{ 0xc, 211, 0 },
+{ 0x2c, 211, 0 },
+{ 0x1c, 211, 0 },
+{ 0x2, 211, 0 },
+{ 0xa, 211, 0 },
+{ 0x6, 211, 0 },
+{ 0x1, 211, 0 },
+{ 0x1, 210, 0 },
+{ 0x5, 210, 0 },
+{ 0x3, 210, 0 },
+{ 0x1, 209, 0 },
+{ 0x5, 209, 0 },
+{ 0x3, 209, 0 },
+{ 0x1, 208, 0 },
+{ 0x5, 208, 0 },
+{ 0x3, 208, 0 },
+{ 0x200, 207, 0 },
+{ 0xa00, 207, 0 },
+{ 0x600, 207, 0 },
+{ 0x100, 207, 0 },
+{ 0x500, 207, 0 },
+{ 0x300, 207, 0 },
+{ 0x80, 207, 0 },
+{ 0x40, 207, 0 },
+{ 0x20, 207, 0 },
+{ 0xa0, 207, 0 },
+{ 0x60, 207, 0 },
+{ 0x50, 207, 0 },
+{ 0x150, 207, 0 },
+{ 0xd0, 207, 0 },
+{ 0x30, 207, 0 },
+{ 0x130, 207, 0 },
+{ 0xb0, 207, 0 },
+{ 0x70, 207, 0 },
+{ 0x170, 207, 0 },
+{ 0xf0, 207, 0 },
+{ 0x8, 207, 0 },
+{ 0x28, 207, 0 },
+{ 0x18, 207, 0 },
+{ 0x4, 207, 0 },
+{ 0x14, 207, 0 },
+{ 0xc, 207, 0 },
+{ 0x2, 207, 0 },
+{ 0xa, 207, 0 },
+{ 0x6, 207, 0 },
+{ 0x1, 207, 0 },
+{ 0x200, 206, 0 },
+{ 0xa00, 206, 0 },
+{ 0x600, 206, 0 },
+{ 0x100, 206, 0 },
+{ 0x500, 206, 0 },
+{ 0x300, 206, 0 },
+{ 0x80, 206, 0 },
+{ 0x40, 206, 0 },
+{ 0x20, 206, 0 },
+{ 0xa0, 206, 0 },
+{ 0x60, 206, 0 },
+{ 0x50, 206, 0 },
+{ 0x150, 206, 0 },
+{ 0xd0, 206, 0 },
+{ 0x30, 206, 0 },
+{ 0x130, 206, 0 },
+{ 0xb0, 206, 0 },
+{ 0x70, 206, 0 },
+{ 0x170, 206, 0 },
+{ 0xf0, 206, 0 },
+{ 0x8, 206, 0 },
+{ 0x28, 206, 0 },
+{ 0x18, 206, 0 },
+{ 0x4, 206, 0 },
+{ 0x14, 206, 0 },
+{ 0xc, 206, 0 },
+{ 0x2, 206, 0 },
+{ 0xa, 206, 0 },
+{ 0x6, 206, 0 },
+{ 0x1, 206, 0 },
+{ 0x200, 205, 0 },
+{ 0xa00, 205, 0 },
+{ 0x600, 205, 0 },
+{ 0x100, 205, 0 },
+{ 0x500, 205, 0 },
+{ 0x300, 205, 0 },
+{ 0x80, 205, 0 },
+{ 0x40, 205, 0 },
+{ 0x20, 205, 0 },
+{ 0xa0, 205, 0 },
+{ 0x60, 205, 0 },
+{ 0x50, 205, 0 },
+{ 0x150, 205, 0 },
+{ 0xd0, 205, 0 },
+{ 0x30, 205, 0 },
+{ 0x130, 205, 0 },
+{ 0xb0, 205, 0 },
+{ 0x70, 205, 0 },
+{ 0x170, 205, 0 },
+{ 0xf0, 205, 0 },
+{ 0x8, 205, 0 },
+{ 0x28, 205, 0 },
+{ 0x18, 205, 0 },
+{ 0x4, 205, 0 },
+{ 0x14, 205, 0 },
+{ 0xc, 205, 0 },
+{ 0x2, 205, 0 },
+{ 0xa, 205, 0 },
+{ 0x6, 205, 0 },
+{ 0x1, 205, 0 },
+{ 0x100, 204, 0 },
+{ 0x500, 204, 0 },
+{ 0x300, 204, 0 },
+{ 0x80, 204, 0 },
+{ 0x280, 204, 0 },
+{ 0x180, 204, 0 },
+{ 0x40, 204, 0 },
+{ 0x20, 204, 0 },
+{ 0x50, 204, 0 },
+{ 0x150, 204, 0 },
+{ 0xd0, 204, 0 },
+{ 0x30, 204, 0 },
+{ 0x130, 204, 0 },
+{ 0xb0, 204, 0 },
+{ 0x70, 204, 0 },
+{ 0x170, 204, 0 },
+{ 0xf0, 204, 0 },
+{ 0x8, 204, 0 },
+{ 0x28, 204, 0 },
+{ 0x18, 204, 0 },
+{ 0x4, 204, 0 },
+{ 0x14, 204, 0 },
+{ 0xc, 204, 0 },
+{ 0x2, 204, 0 },
+{ 0xa, 204, 0 },
+{ 0x6, 204, 0 },
+{ 0x1, 204, 0 },
+{ 0x100, 203, 0 },
+{ 0x500, 203, 0 },
+{ 0x300, 203, 0 },
+{ 0x80, 203, 0 },
+{ 0x280, 203, 0 },
+{ 0x180, 203, 0 },
+{ 0x40, 203, 0 },
+{ 0x20, 203, 0 },
+{ 0x50, 203, 0 },
+{ 0x150, 203, 0 },
+{ 0xd0, 203, 0 },
+{ 0x30, 203, 0 },
+{ 0x130, 203, 0 },
+{ 0xb0, 203, 0 },
+{ 0x70, 203, 0 },
+{ 0x170, 203, 0 },
+{ 0xf0, 203, 0 },
+{ 0x8, 203, 0 },
+{ 0x28, 203, 0 },
+{ 0x18, 203, 0 },
+{ 0x4, 203, 0 },
+{ 0x14, 203, 0 },
+{ 0xc, 203, 0 },
+{ 0x2, 203, 0 },
+{ 0xa, 203, 0 },
+{ 0x6, 203, 0 },
+{ 0x1, 203, 0 },
+{ 0x100, 202, 0 },
+{ 0x500, 202, 0 },
+{ 0x300, 202, 0 },
+{ 0x80, 202, 0 },
+{ 0x280, 202, 0 },
+{ 0x180, 202, 0 },
+{ 0x40, 202, 0 },
+{ 0x20, 202, 0 },
+{ 0x50, 202, 0 },
+{ 0x150, 202, 0 },
+{ 0xd0, 202, 0 },
+{ 0x30, 202, 0 },
+{ 0x130, 202, 0 },
+{ 0xb0, 202, 0 },
+{ 0x70, 202, 0 },
+{ 0x170, 202, 0 },
+{ 0xf0, 202, 0 },
+{ 0x8, 202, 0 },
+{ 0x28, 202, 0 },
+{ 0x18, 202, 0 },
+{ 0x4, 202, 0 },
+{ 0x14, 202, 0 },
+{ 0xc, 202, 0 },
+{ 0x2, 202, 0 },
+{ 0xa, 202, 0 },
+{ 0x6, 202, 0 },
+{ 0x1, 202, 0 },
+{ 0x100, 201, 0 },
+{ 0x500, 201, 0 },
+{ 0x300, 201, 0 },
+{ 0x80, 201, 0 },
+{ 0x280, 201, 0 },
+{ 0x180, 201, 0 },
+{ 0x40, 201, 0 },
+{ 0x20, 201, 0 },
+{ 0x50, 201, 0 },
+{ 0x150, 201, 0 },
+{ 0xd0, 201, 0 },
+{ 0x30, 201, 0 },
+{ 0x130, 201, 0 },
+{ 0xb0, 201, 0 },
+{ 0x70, 201, 0 },
+{ 0x170, 201, 0 },
+{ 0xf0, 201, 0 },
+{ 0x8, 201, 0 },
+{ 0x28, 201, 0 },
+{ 0x18, 201, 0 },
+{ 0x4, 201, 0 },
+{ 0x14, 201, 0 },
+{ 0xc, 201, 0 },
+{ 0x2, 201, 0 },
+{ 0xa, 201, 0 },
+{ 0x6, 201, 0 },
+{ 0x1, 201, 0 },
+{ 0x100, 200, 0 },
+{ 0x500, 200, 0 },
+{ 0x300, 200, 0 },
+{ 0x80, 200, 0 },
+{ 0x280, 200, 0 },
+{ 0x180, 200, 0 },
+{ 0x40, 200, 0 },
+{ 0x20, 200, 0 },
+{ 0x50, 200, 0 },
+{ 0x150, 200, 0 },
+{ 0xd0, 200, 0 },
+{ 0x30, 200, 0 },
+{ 0x130, 200, 0 },
+{ 0xb0, 200, 0 },
+{ 0x70, 200, 0 },
+{ 0x170, 200, 0 },
+{ 0xf0, 200, 0 },
+{ 0x8, 200, 0 },
+{ 0x28, 200, 0 },
+{ 0x18, 200, 0 },
+{ 0x4, 200, 0 },
+{ 0x14, 200, 0 },
+{ 0xc, 200, 0 },
+{ 0x2, 200, 0 },
+{ 0xa, 200, 0 },
+{ 0x6, 200, 0 },
+{ 0x1, 200, 0 },
+{ 0x100, 199, 0 },
+{ 0x500, 199, 0 },
+{ 0x300, 199, 0 },
+{ 0x80, 199, 0 },
+{ 0x280, 199, 0 },
+{ 0x180, 199, 0 },
+{ 0x40, 199, 0 },
+{ 0x20, 199, 0 },
+{ 0x50, 199, 0 },
+{ 0x150, 199, 0 },
+{ 0xd0, 199, 0 },
+{ 0x30, 199, 0 },
+{ 0x130, 199, 0 },
+{ 0xb0, 199, 0 },
+{ 0x70, 199, 0 },
+{ 0x170, 199, 0 },
+{ 0xf0, 199, 0 },
+{ 0x8, 199, 0 },
+{ 0x28, 199, 0 },
+{ 0x18, 199, 0 },
+{ 0x4, 199, 0 },
+{ 0x14, 199, 0 },
+{ 0xc, 199, 0 },
+{ 0x2, 199, 0 },
+{ 0xa, 199, 0 },
+{ 0x6, 199, 0 },
+{ 0x1, 199, 0 },
+{ 0x100, 198, 0 },
+{ 0x500, 198, 0 },
+{ 0x300, 198, 0 },
+{ 0x80, 198, 0 },
+{ 0x280, 198, 0 },
+{ 0x180, 198, 0 },
+{ 0x40, 198, 0 },
+{ 0x20, 198, 0 },
+{ 0x50, 198, 0 },
+{ 0x150, 198, 0 },
+{ 0xd0, 198, 0 },
+{ 0x30, 198, 0 },
+{ 0x130, 198, 0 },
+{ 0xb0, 198, 0 },
+{ 0x70, 198, 0 },
+{ 0x170, 198, 0 },
+{ 0xf0, 198, 0 },
+{ 0x8, 198, 0 },
+{ 0x28, 198, 0 },
+{ 0x18, 198, 0 },
+{ 0x4, 198, 0 },
+{ 0x14, 198, 0 },
+{ 0xc, 198, 0 },
+{ 0x2, 198, 0 },
+{ 0xa, 198, 0 },
+{ 0x6, 198, 0 },
+{ 0x1, 198, 0 },
+{ 0x100, 197, 0 },
+{ 0x500, 197, 0 },
+{ 0x300, 197, 0 },
+{ 0x80, 197, 0 },
+{ 0x280, 197, 0 },
+{ 0x180, 197, 0 },
+{ 0x40, 197, 0 },
+{ 0x20, 197, 0 },
+{ 0x50, 197, 0 },
+{ 0x150, 197, 0 },
+{ 0xd0, 197, 0 },
+{ 0x30, 197, 0 },
+{ 0x130, 197, 0 },
+{ 0xb0, 197, 0 },
+{ 0x70, 197, 0 },
+{ 0x170, 197, 0 },
+{ 0xf0, 197, 0 },
+{ 0x8, 197, 0 },
+{ 0x28, 197, 0 },
+{ 0x18, 197, 0 },
+{ 0x4, 197, 0 },
+{ 0x14, 197, 0 },
+{ 0xc, 197, 0 },
+{ 0x2, 197, 0 },
+{ 0xa, 197, 0 },
+{ 0x6, 197, 0 },
+{ 0x1, 197, 0 },
+{ 0x100, 196, 0 },
+{ 0x500, 196, 0 },
+{ 0x300, 196, 0 },
+{ 0x80, 196, 0 },
+{ 0x280, 196, 0 },
+{ 0x180, 196, 0 },
+{ 0x40, 196, 0 },
+{ 0x20, 196, 0 },
+{ 0x50, 196, 0 },
+{ 0x150, 196, 0 },
+{ 0xd0, 196, 0 },
+{ 0x30, 196, 0 },
+{ 0x130, 196, 0 },
+{ 0xb0, 196, 0 },
+{ 0x70, 196, 0 },
+{ 0x170, 196, 0 },
+{ 0xf0, 196, 0 },
+{ 0x8, 196, 0 },
+{ 0x28, 196, 0 },
+{ 0x18, 196, 0 },
+{ 0x4, 196, 0 },
+{ 0x14, 196, 0 },
+{ 0xc, 196, 0 },
+{ 0x2, 196, 0 },
+{ 0xa, 196, 0 },
+{ 0x6, 196, 0 },
+{ 0x1, 196, 0 },
+{ 0x1, 195, 0 },
+{ 0x1, 194, 0 },
+{ 0x2, 193, 0 },
+{ 0x1, 193, 0 },
+{ 0x1, 192, 0 },
+{ 0x1, 191, 1 },
+{ 0x1, 390, 0 },
+{ 0x1, 190, 1 },
+{ 0x1, 388, 0 },
+{ 0x8, 189, 0 },
+{ 0x4, 189, 0 },
+{ 0x2, 189, 0 },
+{ 0x1, 189, 0 },
+{ 0x1, 188, 0 },
+{ 0x1, 187, 0 },
+{ 0x2, 186, 0 },
+{ 0x1, 186, 0 },
+{ 0x4, 185, 0 },
+{ 0x2, 185, 0 },
+{ 0x1, 185, 0 },
+{ 0x40, 184, 0 },
+{ 0x20, 184, 0 },
+{ 0x10, 184, 0 },
+{ 0x44, 184, 0 },
+{ 0x24, 184, 0 },
+{ 0x14, 184, 0 },
+{ 0xc, 184, 1 },
+{ 0x4, 184, 0 },
+{ 0x22, 184, 0 },
+{ 0x12, 184, 0 },
+{ 0xa, 184, 0 },
+{ 0x6, 184, 1 },
+{ 0x2, 184, 0 },
+{ 0x1, 184, 1 },
+{ 0x8, 184, 0 },
+{ 0x8, 182, 0 },
+{ 0x4, 182, 0 },
+{ 0x2, 182, 0 },
+{ 0x1, 182, 1 },
+{ 0x1, 183, 0 },
+{ 0x1, 181, 0 },
+{ 0x8, 179, 0 },
+{ 0x4, 179, 0 },
+{ 0x2, 179, 0 },
+{ 0x1, 179, 1 },
+{ 0x1, 180, 0 },
+{ 0x8, 177, 0 },
+{ 0x4, 177, 0 },
+{ 0x2, 177, 0 },
+{ 0x1, 177, 1 },
+{ 0x1, 178, 0 },
+{ 0x8, 175, 0 },
+{ 0x4, 175, 0 },
+{ 0x2, 175, 0 },
+{ 0x1, 175, 1 },
+{ 0x1, 176, 0 },
+{ 0x8, 173, 0 },
+{ 0x4, 173, 0 },
+{ 0x2, 173, 0 },
+{ 0x1, 173, 1 },
+{ 0x1, 174, 0 },
+{ 0x10, 172, 0 },
+{ 0x8, 172, 0 },
+{ 0x4, 172, 0 },
+{ 0x1, 172, 1 },
+{ 0x2, 172, 0 },
+{ 0x8, 170, 0 },
+{ 0x4, 170, 0 },
+{ 0x2, 170, 0 },
+{ 0x1, 170, 1 },
+{ 0x1, 171, 0 },
+{ 0x1, 169, 0 },
+{ 0x8, 166, 0 },
+{ 0x4, 166, 0 },
+{ 0x2, 166, 0 },
+{ 0x1, 166, 1 },
+{ 0x1, 167, 0 },
+{ 0x10, 165, 0 },
+{ 0x8, 165, 0 },
+{ 0x4, 165, 0 },
+{ 0x1, 165, 1 },
+{ 0x2, 165, 0 },
+{ 0x8, 163, 0 },
+{ 0x4, 163, 0 },
+{ 0x2, 163, 0 },
+{ 0x1, 163, 1 },
+{ 0x1, 164, 1 },
+{ 0x1, 271, 0 },
+{ 0x4, 162, 0 },
+{ 0x2, 162, 0 },
+{ 0x1, 162, 1 },
+{ 0x1, 168, 0 },
+{ 0x8, 160, 0 },
+{ 0x4, 160, 0 },
+{ 0x2, 160, 0 },
+{ 0x1, 160, 1 },
+{ 0x1, 161, 1 },
+{ 0x1, 272, 0 },
+{ 0x8, 158, 0 },
+{ 0x4, 158, 0 },
+{ 0x2, 158, 0 },
+{ 0x1, 158, 1 },
+{ 0x1, 159, 0 },
+{ 0x442, 156, 0 },
+{ 0x242, 156, 0 },
+{ 0x142, 156, 0 },
+{ 0xc2, 156, 1 },
+{ 0x6, 157, 1 },
+{ 0x1, 375, 0 },
+{ 0x22, 156, 0 },
+{ 0x12, 156, 0 },
+{ 0xa, 156, 0 },
+{ 0x6, 156, 1 },
+{ 0x2, 157, 1 },
+{ 0x2, 309, 0 },
+{ 0x221, 156, 0 },
+{ 0x121, 156, 0 },
+{ 0xa1, 156, 0 },
+{ 0x61, 156, 1 },
+{ 0x3, 157, 1 },
+{ 0x1, 371, 0 },
+{ 0x11, 156, 0 },
+{ 0x9, 156, 0 },
+{ 0x5, 156, 0 },
+{ 0x3, 156, 1 },
+{ 0x1, 157, 1 },
+{ 0x1, 309, 0 },
+{ 0x880, 154, 0 },
+{ 0x480, 154, 0 },
+{ 0x280, 154, 0 },
+{ 0x180, 154, 1 },
+{ 0x80, 155, 1 },
+{ 0xc, 310, 0 },
+{ 0x440, 154, 0 },
+{ 0x240, 154, 0 },
+{ 0x140, 154, 0 },
+{ 0xc0, 154, 1 },
+{ 0x40, 155, 0 },
+{ 0x220, 154, 0 },
+{ 0x120, 154, 0 },
+{ 0xa0, 154, 0 },
+{ 0x60, 154, 1 },
+{ 0x20, 155, 0 },
+{ 0x110, 154, 0 },
+{ 0x90, 154, 0 },
+{ 0x50, 154, 0 },
+{ 0x30, 154, 1 },
+{ 0x10, 155, 0 },
+{ 0x88, 154, 0 },
+{ 0x48, 154, 0 },
+{ 0x28, 154, 0 },
+{ 0x18, 154, 1 },
+{ 0x8, 155, 1 },
+{ 0x1, 327, 0 },
+{ 0x44, 154, 0 },
+{ 0x24, 154, 0 },
+{ 0x14, 154, 0 },
+{ 0xc, 154, 1 },
+{ 0x4, 155, 1 },
+{ 0x6, 310, 0 },
+{ 0x22, 154, 0 },
+{ 0x12, 154, 0 },
+{ 0xa, 154, 0 },
+{ 0x6, 154, 1 },
+{ 0x2, 155, 1 },
+{ 0x3, 310, 0 },
+{ 0x11, 154, 0 },
+{ 0x9, 154, 0 },
+{ 0x5, 154, 0 },
+{ 0x8, 152, 0 },
+{ 0x4, 152, 0 },
+{ 0x2, 152, 0 },
+{ 0x1, 152, 1 },
+{ 0x1, 153, 1 },
+{ 0x1, 273, 0 },
+{ 0x8, 150, 0 },
+{ 0x4, 150, 0 },
+{ 0x2, 150, 0 },
+{ 0x1, 150, 1 },
+{ 0x1, 151, 1 },
+{ 0x1, 274, 0 },
+{ 0x1, 149, 0 },
+{ 0x1, 148, 0 },
+{ 0x1, 147, 0 },
+{ 0x40, 145, 0 },
+{ 0x20, 145, 0 },
+{ 0x10, 145, 0 },
+{ 0x44, 145, 0 },
+{ 0x24, 145, 0 },
+{ 0x14, 145, 0 },
+{ 0xc, 145, 1 },
+{ 0x4, 145, 0 },
+{ 0x22, 145, 0 },
+{ 0x12, 145, 0 },
+{ 0xa, 145, 0 },
+{ 0x6, 145, 1 },
+{ 0x2, 145, 0 },
+{ 0x1, 145, 1 },
+{ 0x8, 145, 0 },
+{ 0x20, 143, 0 },
+{ 0x10, 143, 0 },
+{ 0x8, 143, 0 },
+{ 0x4, 143, 1 },
+{ 0x1, 144, 0 },
+{ 0x22, 143, 0 },
+{ 0x12, 143, 0 },
+{ 0xa, 143, 0 },
+{ 0x6, 143, 1 },
+{ 0x4, 144, 0 },
+{ 0x11, 143, 0 },
+{ 0x9, 143, 0 },
+{ 0x5, 143, 0 },
+{ 0x3, 143, 1 },
+{ 0x2, 144, 0 },
+{ 0x1, 142, 0 },
+{ 0x20, 139, 0 },
+{ 0x10, 139, 0 },
+{ 0x8, 139, 0 },
+{ 0x4, 139, 1 },
+{ 0x1, 140, 0 },
+{ 0x22, 139, 0 },
+{ 0x12, 139, 0 },
+{ 0xa, 139, 0 },
+{ 0x6, 139, 1 },
+{ 0x4, 140, 0 },
+{ 0x11, 139, 0 },
+{ 0x9, 139, 0 },
+{ 0x5, 139, 0 },
+{ 0x3, 139, 1 },
+{ 0x2, 140, 0 },
+{ 0x40, 138, 0 },
+{ 0x20, 138, 0 },
+{ 0x10, 138, 0 },
+{ 0x44, 138, 0 },
+{ 0x24, 138, 0 },
+{ 0x14, 138, 0 },
+{ 0xc, 138, 1 },
+{ 0x4, 138, 0 },
+{ 0x22, 138, 0 },
+{ 0x12, 138, 0 },
+{ 0xa, 138, 0 },
+{ 0x6, 138, 1 },
+{ 0x2, 138, 0 },
+{ 0x1, 138, 1 },
+{ 0x8, 138, 0 },
+{ 0x4, 137, 0 },
+{ 0x2, 137, 0 },
+{ 0x1, 137, 0 },
+{ 0x8, 135, 0 },
+{ 0x4, 135, 0 },
+{ 0x2, 135, 0 },
+{ 0x1, 135, 1 },
+{ 0x1, 136, 1 },
+{ 0x1, 364, 0 },
+{ 0x4, 134, 0 },
+{ 0x2, 134, 1 },
+{ 0x1, 240, 0 },
+{ 0x1, 134, 1 },
+{ 0x1, 141, 0 },
+{ 0x8, 132, 0 },
+{ 0x4, 132, 0 },
+{ 0x2, 132, 0 },
+{ 0x1, 132, 1 },
+{ 0x1, 133, 1 },
+{ 0x1, 365, 0 },
+{ 0x20, 130, 0 },
+{ 0x10, 130, 0 },
+{ 0x8, 130, 0 },
+{ 0x4, 130, 1 },
+{ 0x1, 131, 0 },
+{ 0x2, 130, 1 },
+{ 0xc, 131, 0 },
+{ 0x12, 130, 0 },
+{ 0xa, 130, 0 },
+{ 0x6, 130, 0 },
+{ 0x11, 130, 0 },
+{ 0x9, 130, 0 },
+{ 0x5, 130, 0 },
+{ 0x3, 130, 1 },
+{ 0x2, 131, 0 },
+{ 0x1, 129, 0 },
+{ 0x2, 128, 0 },
+{ 0xa, 128, 0 },
+{ 0x6, 128, 0 },
+{ 0x1, 128, 0 },
+{ 0x5, 128, 0 },
+{ 0x3, 128, 0 },
+{ 0x2, 127, 0 },
+{ 0xa, 127, 0 },
+{ 0x6, 127, 0 },
+{ 0x1, 127, 0 },
+{ 0x5, 127, 0 },
+{ 0x3, 127, 0 },
+{ 0x41, 126, 1 },
+{ 0x40, 146, 0 },
+{ 0x21, 126, 1 },
+{ 0x20, 146, 0 },
+{ 0x11, 126, 1 },
+{ 0x10, 146, 0 },
+{ 0x9, 126, 1 },
+{ 0x1, 126, 1 },
+{ 0x1, 146, 1 },
+{ 0x8, 146, 0 },
+{ 0x45, 126, 1 },
+{ 0x44, 146, 0 },
+{ 0x25, 126, 1 },
+{ 0x24, 146, 0 },
+{ 0x15, 126, 1 },
+{ 0x14, 146, 0 },
+{ 0xd, 126, 1 },
+{ 0x5, 126, 1 },
+{ 0xc, 146, 1 },
+{ 0x4, 146, 0 },
+{ 0x23, 126, 1 },
+{ 0x22, 146, 0 },
+{ 0x13, 126, 1 },
+{ 0x12, 146, 0 },
+{ 0xb, 126, 1 },
+{ 0xa, 146, 0 },
+{ 0x7, 126, 1 },
+{ 0x3, 126, 1 },
+{ 0x6, 146, 1 },
+{ 0x2, 146, 0 },
+{ 0x1, 125, 0 },
+{ 0x442, 123, 0 },
+{ 0x242, 123, 0 },
+{ 0x142, 123, 0 },
+{ 0xc2, 123, 1 },
+{ 0x6, 124, 0 },
+{ 0x22, 123, 0 },
+{ 0x12, 123, 0 },
+{ 0xa, 123, 0 },
+{ 0x221, 123, 0 },
+{ 0x121, 123, 0 },
+{ 0xa1, 123, 0 },
+{ 0x61, 123, 1 },
+{ 0x3, 124, 0 },
+{ 0x11, 123, 0 },
+{ 0x9, 123, 0 },
+{ 0x5, 123, 0 },
+{ 0x1108, 115, 1 },
+{ 0x1108, 119, 0 },
+{ 0x908, 115, 1 },
+{ 0x908, 119, 0 },
+{ 0x508, 115, 1 },
+{ 0x508, 119, 0 },
+{ 0x308, 115, 1 },
+{ 0x18, 116, 1 },
+{ 0x308, 119, 1 },
+{ 0x18, 120, 0 },
+{ 0x88, 115, 1 },
+{ 0x88, 119, 0 },
+{ 0x48, 115, 1 },
+{ 0x48, 119, 0 },
+{ 0x28, 115, 1 },
+{ 0x28, 119, 0 },
+{ 0x18, 115, 1 },
+{ 0x8, 116, 1 },
+{ 0x18, 119, 1 },
+{ 0x8, 120, 0 },
+{ 0x884, 115, 1 },
+{ 0x442, 117, 1 },
+{ 0x884, 119, 1 },
+{ 0x442, 121, 0 },
+{ 0x484, 115, 1 },
+{ 0x242, 117, 1 },
+{ 0x484, 119, 1 },
+{ 0x242, 121, 0 },
+{ 0x284, 115, 1 },
+{ 0x142, 117, 1 },
+{ 0x284, 119, 1 },
+{ 0x142, 121, 0 },
+{ 0x184, 115, 1 },
+{ 0xc, 116, 1 },
+{ 0xc2, 117, 1 },
+{ 0x6, 118, 1 },
+{ 0x184, 119, 1 },
+{ 0xc, 120, 1 },
+{ 0xc2, 121, 1 },
+{ 0x6, 122, 0 },
+{ 0x44, 115, 1 },
+{ 0x22, 117, 1 },
+{ 0x44, 119, 1 },
+{ 0x22, 121, 0 },
+{ 0x24, 115, 1 },
+{ 0x12, 117, 1 },
+{ 0x24, 119, 1 },
+{ 0x12, 121, 0 },
+{ 0x14, 115, 1 },
+{ 0xa, 117, 1 },
+{ 0x14, 119, 1 },
+{ 0xa, 121, 0 },
+{ 0xc, 115, 1 },
+{ 0x4, 116, 1 },
+{ 0x6, 117, 1 },
+{ 0x2, 118, 1 },
+{ 0xc, 119, 1 },
+{ 0x4, 120, 1 },
+{ 0x6, 121, 1 },
+{ 0x2, 122, 0 },
+{ 0x442, 115, 1 },
+{ 0x221, 117, 1 },
+{ 0x442, 119, 1 },
+{ 0x221, 121, 0 },
+{ 0x242, 115, 1 },
+{ 0x121, 117, 1 },
+{ 0x242, 119, 1 },
+{ 0x121, 121, 0 },
+{ 0x142, 115, 1 },
+{ 0xa1, 117, 1 },
+{ 0x142, 119, 1 },
+{ 0xa1, 121, 0 },
+{ 0xc2, 115, 1 },
+{ 0x6, 116, 1 },
+{ 0x61, 117, 1 },
+{ 0x3, 118, 1 },
+{ 0xc2, 119, 1 },
+{ 0x6, 120, 1 },
+{ 0x61, 121, 1 },
+{ 0x3, 122, 0 },
+{ 0x22, 115, 1 },
+{ 0x11, 117, 1 },
+{ 0x22, 119, 1 },
+{ 0x11, 121, 0 },
+{ 0x12, 115, 1 },
+{ 0x9, 117, 1 },
+{ 0x12, 119, 1 },
+{ 0x9, 121, 0 },
+{ 0xa, 115, 1 },
+{ 0x5, 117, 1 },
+{ 0xa, 119, 1 },
+{ 0x5, 121, 0 },
+{ 0x6, 115, 1 },
+{ 0x2, 116, 1 },
+{ 0x3, 117, 1 },
+{ 0x1, 118, 1 },
+{ 0x6, 119, 1 },
+{ 0x2, 120, 1 },
+{ 0x3, 121, 1 },
+{ 0x1, 122, 0 },
+{ 0x221, 115, 1 },
+{ 0x221, 119, 0 },
+{ 0x121, 115, 1 },
+{ 0x121, 119, 0 },
+{ 0xa1, 115, 1 },
+{ 0xa1, 119, 0 },
+{ 0x61, 115, 1 },
+{ 0x3, 116, 1 },
+{ 0x61, 119, 1 },
+{ 0x3, 120, 0 },
+{ 0x11, 115, 1 },
+{ 0x11, 119, 0 },
+{ 0x9, 115, 1 },
+{ 0x9, 119, 0 },
+{ 0x5, 115, 1 },
+{ 0x5, 119, 0 },
+{ 0x3, 115, 1 },
+{ 0x1, 116, 1 },
+{ 0x3, 119, 1 },
+{ 0x1, 120, 0 },
+{ 0x8, 113, 0 },
+{ 0x4, 113, 0 },
+{ 0x2, 113, 0 },
+{ 0x1, 113, 1 },
+{ 0x1, 114, 0 },
+{ 0x1, 111, 1 },
+{ 0x1, 112, 0 },
+{ 0x3, 111, 1 },
+{ 0x3, 112, 0 },
+{ 0x8, 109, 0 },
+{ 0x4, 109, 0 },
+{ 0x2, 109, 0 },
+{ 0x1, 109, 1 },
+{ 0x1, 110, 0 },
+{ 0x1, 108, 1 },
+{ 0x3, 154, 1 },
+{ 0x1, 155, 0 },
+{ 0x1, 107, 0 },
+{ 0x1, 106, 0 },
+{ 0x8, 104, 0 },
+{ 0x4, 104, 0 },
+{ 0x2, 104, 0 },
+{ 0x1, 104, 1 },
+{ 0x1, 105, 1 },
+{ 0x1, 366, 0 },
+{ 0x8, 102, 0 },
+{ 0x4, 102, 0 },
+{ 0x2, 102, 0 },
+{ 0x1, 102, 1 },
+{ 0x1, 103, 0 },
+{ 0x40, 101, 0 },
+{ 0x20, 101, 0 },
+{ 0x10, 101, 1 },
+{ 0x2, 291, 0 },
+{ 0x44, 101, 0 },
+{ 0x24, 101, 0 },
+{ 0x14, 101, 0 },
+{ 0xc, 101, 1 },
+{ 0x4, 101, 0 },
+{ 0x22, 101, 0 },
+{ 0x12, 101, 0 },
+{ 0xa, 101, 0 },
+{ 0x6, 101, 1 },
+{ 0x2, 101, 0 },
+{ 0x1, 101, 1 },
+{ 0x8, 101, 0 },
+{ 0x1, 100, 0 },
+{ 0x2, 99, 1 },
+{ 0x2, 337, 0 },
+{ 0x1, 99, 1 },
+{ 0x1, 337, 0 },
+{ 0x1, 98, 0 },
+{ 0x1, 97, 0 },
+{ 0x1, 96, 0 },
+{ 0x1, 95, 1 },
+{ 0x1, 333, 0 },
+{ 0x1, 94, 0 },
+{ 0x2, 93, 0 },
+{ 0x1, 93, 1 },
+{ 0x6, 123, 1 },
+{ 0x2, 124, 0 },
+{ 0x2, 92, 0 },
+{ 0x1, 92, 1 },
+{ 0x3, 123, 1 },
+{ 0x1, 124, 0 },
+{ 0x1, 91, 0 },
+{ 0x2, 90, 0 },
+{ 0xa, 90, 0 },
+{ 0x6, 90, 0 },
+{ 0x1, 90, 0 },
+{ 0x5, 90, 0 },
+{ 0x3, 90, 0 },
+{ 0x2, 89, 0 },
+{ 0xa, 89, 0 },
+{ 0x6, 89, 0 },
+{ 0x1, 89, 0 },
+{ 0x5, 89, 0 },
+{ 0x3, 89, 0 },
+{ 0x2, 88, 0 },
+{ 0xa, 88, 0 },
+{ 0x6, 88, 0 },
+{ 0x1, 88, 0 },
+{ 0x5, 88, 0 },
+{ 0x3, 88, 0 },
+{ 0x2, 87, 0 },
+{ 0xa, 87, 0 },
+{ 0x6, 87, 0 },
+{ 0x1, 87, 0 },
+{ 0x5, 87, 0 },
+{ 0x3, 87, 0 },
+{ 0x34, 75, 1 },
+{ 0x7, 86, 0 },
+{ 0xc, 75, 1 },
+{ 0x3, 79, 0 },
+{ 0x2, 75, 1 },
+{ 0x1, 76, 1 },
+{ 0x1, 77, 1 },
+{ 0x1, 78, 0 },
+{ 0x6, 75, 1 },
+{ 0x3, 76, 1 },
+{ 0x3, 77, 1 },
+{ 0x3, 78, 0 },
+{ 0x1, 75, 1 },
+{ 0x2, 78, 0 },
+{ 0x9, 75, 1 },
+{ 0x6, 78, 0 },
+{ 0xd, 75, 1 },
+{ 0xe, 86, 0 },
+{ 0x3, 75, 1 },
+{ 0x6, 79, 0 },
+{ 0x28, 73, 1 },
+{ 0x5, 74, 0 },
+{ 0x68, 73, 1 },
+{ 0x7, 85, 0 },
+{ 0x18, 73, 1 },
+{ 0x3, 74, 0 },
+{ 0x14, 73, 1 },
+{ 0xa, 74, 0 },
+{ 0x34, 73, 1 },
+{ 0xe, 85, 0 },
+{ 0xc, 73, 1 },
+{ 0x6, 74, 0 },
+{ 0xa, 73, 1 },
+{ 0x14, 74, 0 },
+{ 0x1a, 73, 1 },
+{ 0x1c, 85, 0 },
+{ 0x6, 73, 1 },
+{ 0xc, 74, 0 },
+{ 0x5, 73, 1 },
+{ 0x28, 74, 0 },
+{ 0xd, 73, 1 },
+{ 0x38, 85, 0 },
+{ 0x3, 73, 1 },
+{ 0x18, 74, 0 },
+{ 0x28, 68, 1 },
+{ 0x5, 72, 0 },
+{ 0x68, 68, 1 },
+{ 0x7, 84, 0 },
+{ 0x18, 68, 1 },
+{ 0x3, 72, 0 },
+{ 0x4, 68, 1 },
+{ 0x2, 69, 1 },
+{ 0x2, 70, 1 },
+{ 0x2, 71, 0 },
+{ 0xc, 68, 1 },
+{ 0x6, 69, 1 },
+{ 0x6, 70, 1 },
+{ 0x6, 71, 0 },
+{ 0x2, 68, 1 },
+{ 0x1, 69, 1 },
+{ 0x1, 70, 1 },
+{ 0x1, 71, 0 },
+{ 0x6, 68, 1 },
+{ 0x3, 69, 1 },
+{ 0x3, 70, 1 },
+{ 0x3, 71, 0 },
+{ 0x1, 68, 1 },
+{ 0x4, 71, 0 },
+{ 0x9, 68, 1 },
+{ 0xc, 71, 0 },
+{ 0x5, 68, 1 },
+{ 0xa, 72, 0 },
+{ 0xd, 68, 1 },
+{ 0xe, 84, 0 },
+{ 0x3, 68, 1 },
+{ 0x6, 72, 0 },
+{ 0x68, 58, 1 },
+{ 0x7, 67, 0 },
+{ 0x18, 58, 1 },
+{ 0x3, 62, 0 },
+{ 0x2, 58, 1 },
+{ 0x1, 59, 1 },
+{ 0x1, 60, 1 },
+{ 0x1, 61, 0 },
+{ 0x6, 58, 1 },
+{ 0x3, 59, 1 },
+{ 0x3, 60, 1 },
+{ 0x3, 61, 0 },
+{ 0x1, 58, 1 },
+{ 0x4, 61, 0 },
+{ 0x9, 58, 1 },
+{ 0xc, 61, 0 },
+{ 0xd, 58, 1 },
+{ 0xe, 67, 0 },
+{ 0x3, 58, 1 },
+{ 0x6, 62, 0 },
+{ 0x28, 56, 1 },
+{ 0x5, 57, 0 },
+{ 0x68, 56, 1 },
+{ 0x7, 66, 0 },
+{ 0x18, 56, 1 },
+{ 0x3, 57, 0 },
+{ 0x14, 56, 1 },
+{ 0xa, 57, 0 },
+{ 0x34, 56, 1 },
+{ 0xe, 66, 0 },
+{ 0xc, 56, 1 },
+{ 0x6, 57, 0 },
+{ 0xa, 56, 1 },
+{ 0x14, 57, 0 },
+{ 0x1a, 56, 1 },
+{ 0x1c, 66, 0 },
+{ 0x6, 56, 1 },
+{ 0xc, 57, 0 },
+{ 0x5, 56, 1 },
+{ 0x28, 57, 0 },
+{ 0xd, 56, 1 },
+{ 0x38, 66, 0 },
+{ 0x3, 56, 1 },
+{ 0x18, 57, 0 },
+{ 0x28, 51, 1 },
+{ 0x5, 55, 0 },
+{ 0x68, 51, 1 },
+{ 0x7, 65, 0 },
+{ 0x18, 51, 1 },
+{ 0x3, 55, 0 },
+{ 0x4, 51, 1 },
+{ 0x2, 52, 1 },
+{ 0x2, 53, 1 },
+{ 0x2, 54, 0 },
+{ 0xc, 51, 1 },
+{ 0x6, 52, 1 },
+{ 0x6, 53, 1 },
+{ 0x6, 54, 0 },
+{ 0x2, 51, 1 },
+{ 0x1, 52, 1 },
+{ 0x1, 53, 1 },
+{ 0x1, 54, 0 },
+{ 0x6, 51, 1 },
+{ 0x3, 52, 1 },
+{ 0x3, 53, 1 },
+{ 0x3, 54, 0 },
+{ 0x1, 51, 1 },
+{ 0x4, 54, 0 },
+{ 0x9, 51, 1 },
+{ 0xc, 54, 0 },
+{ 0x5, 51, 1 },
+{ 0xa, 55, 0 },
+{ 0xd, 51, 1 },
+{ 0xe, 65, 0 },
+{ 0x3, 51, 1 },
+{ 0x6, 55, 0 },
+{ 0x2, 50, 0 },
+{ 0x1, 50, 0 },
+{ 0x1, 48, 0 },
+{ 0x3, 47, 0 },
+{ 0x5, 46, 0 },
+{ 0x3, 46, 0 },
+{ 0x5, 45, 0 },
+{ 0x3, 45, 0 },
+{ 0x3, 44, 0 },
+{ 0x2, 43, 0 },
+{ 0x1, 43, 0 },
+{ 0x8, 42, 0 },
+{ 0x18, 42, 0 },
+{ 0x4, 42, 0 },
+{ 0xc, 42, 0 },
+{ 0x2, 42, 0 },
+{ 0x6, 42, 0 },
+{ 0x1, 42, 0 },
+{ 0x3, 42, 0 },
+{ 0x4, 41, 0 },
+{ 0xc, 41, 0 },
+{ 0xa, 41, 0 },
+{ 0x1a, 41, 0 },
+{ 0x6, 41, 0 },
+{ 0xe, 41, 0 },
+{ 0x1, 41, 0 },
+{ 0x3, 41, 0 },
+{ 0x51, 39, 0 },
+{ 0xd1, 39, 1 },
+{ 0xc, 58, 1 },
+{ 0x6, 61, 1 },
+{ 0x3, 63, 1 },
+{ 0x3, 64, 0 },
+{ 0x31, 39, 1 },
+{ 0x11, 40, 0 },
+{ 0x71, 39, 1 },
+{ 0x31, 40, 1 },
+{ 0x4, 58, 1 },
+{ 0x2, 61, 1 },
+{ 0x1, 63, 1 },
+{ 0x1, 64, 0 },
+{ 0x29, 39, 0 },
+{ 0x69, 39, 1 },
+{ 0x28, 58, 1 },
+{ 0x5, 62, 0 },
+{ 0x19, 39, 1 },
+{ 0x9, 40, 0 },
+{ 0x39, 39, 1 },
+{ 0x19, 40, 1 },
+{ 0x5, 58, 1 },
+{ 0xa, 62, 0 },
+{ 0x15, 39, 0 },
+{ 0x35, 39, 1 },
+{ 0x3, 80, 1 },
+{ 0x3, 81, 1 },
+{ 0x3, 82, 1 },
+{ 0x3, 83, 0 },
+{ 0xd, 39, 1 },
+{ 0x5, 40, 0 },
+{ 0x1d, 39, 1 },
+{ 0xd, 40, 1 },
+{ 0x1, 80, 1 },
+{ 0x1, 81, 1 },
+{ 0x1, 82, 1 },
+{ 0x1, 83, 0 },
+{ 0xb, 39, 0 },
+{ 0x1b, 39, 1 },
+{ 0x14, 75, 1 },
+{ 0x5, 79, 0 },
+{ 0x7, 39, 1 },
+{ 0x3, 40, 0 },
+{ 0xf, 39, 1 },
+{ 0x7, 40, 1 },
+{ 0x5, 75, 1 },
+{ 0xa, 79, 0 },
+{ 0x51, 37, 1 },
+{ 0x50, 37, 0 },
+{ 0xd1, 37, 1 },
+{ 0xd0, 37, 0 },
+{ 0x31, 37, 1 },
+{ 0x30, 37, 1 },
+{ 0x11, 38, 1 },
+{ 0x10, 38, 0 },
+{ 0x71, 37, 1 },
+{ 0x70, 37, 1 },
+{ 0x31, 38, 1 },
+{ 0x30, 38, 0 },
+{ 0x29, 37, 1 },
+{ 0x28, 37, 0 },
+{ 0x69, 37, 1 },
+{ 0x68, 37, 0 },
+{ 0x19, 37, 1 },
+{ 0x18, 37, 1 },
+{ 0x9, 38, 1 },
+{ 0x8, 38, 0 },
+{ 0x39, 37, 1 },
+{ 0x38, 37, 1 },
+{ 0x19, 38, 1 },
+{ 0x18, 38, 0 },
+{ 0x15, 37, 1 },
+{ 0x14, 37, 0 },
+{ 0x35, 37, 1 },
+{ 0x34, 37, 0 },
+{ 0xd, 37, 1 },
+{ 0xc, 37, 1 },
+{ 0x5, 38, 1 },
+{ 0x4, 38, 0 },
+{ 0x1d, 37, 1 },
+{ 0x1c, 37, 1 },
+{ 0xd, 38, 1 },
+{ 0xc, 38, 0 },
+{ 0xb, 37, 1 },
+{ 0xa, 37, 0 },
+{ 0x1b, 37, 1 },
+{ 0x1a, 37, 0 },
+{ 0x7, 37, 1 },
+{ 0x6, 37, 1 },
+{ 0x3, 38, 1 },
+{ 0x2, 38, 0 },
+{ 0xf, 37, 1 },
+{ 0xe, 37, 1 },
+{ 0x7, 38, 1 },
+{ 0x6, 38, 0 },
+{ 0x8, 36, 0 },
+{ 0x18, 36, 0 },
+{ 0x2, 36, 1 },
+{ 0xc, 36, 0 },
+{ 0x1, 36, 1 },
+{ 0x4, 36, 0 },
+{ 0x1, 32, 1 },
+{ 0x1, 33, 1 },
+{ 0x1, 34, 0 },
+{ 0x1, 31, 0 },
+{ 0x1, 30, 0 },
+{ 0x51, 28, 0 },
+{ 0xd1, 28, 0 },
+{ 0x31, 28, 1 },
+{ 0x11, 29, 0 },
+{ 0x71, 28, 1 },
+{ 0x31, 29, 0 },
+{ 0x29, 28, 0 },
+{ 0x69, 28, 0 },
+{ 0x19, 28, 1 },
+{ 0x9, 29, 0 },
+{ 0x39, 28, 1 },
+{ 0x19, 29, 0 },
+{ 0x15, 28, 0 },
+{ 0x35, 28, 0 },
+{ 0xd, 28, 1 },
+{ 0x5, 29, 0 },
+{ 0x1d, 28, 1 },
+{ 0xd, 29, 0 },
+{ 0xb, 28, 0 },
+{ 0x1b, 28, 0 },
+{ 0x7, 28, 1 },
+{ 0x3, 29, 0 },
+{ 0xf, 28, 1 },
+{ 0x7, 29, 0 },
+{ 0xa2, 26, 0 },
+{ 0x1a2, 26, 0 },
+{ 0x62, 26, 1 },
+{ 0x22, 27, 0 },
+{ 0xe2, 26, 1 },
+{ 0x62, 27, 0 },
+{ 0x52, 26, 0 },
+{ 0xd2, 26, 0 },
+{ 0x32, 26, 1 },
+{ 0x12, 27, 0 },
+{ 0x72, 26, 1 },
+{ 0x32, 27, 0 },
+{ 0x2a, 26, 0 },
+{ 0x6a, 26, 0 },
+{ 0x1a, 26, 1 },
+{ 0xa, 27, 0 },
+{ 0x3a, 26, 1 },
+{ 0x1a, 27, 0 },
+{ 0x16, 26, 0 },
+{ 0x36, 26, 0 },
+{ 0xe, 26, 1 },
+{ 0x6, 27, 0 },
+{ 0x1e, 26, 1 },
+{ 0xe, 27, 0 },
+{ 0x51, 26, 0 },
+{ 0xd1, 26, 0 },
+{ 0x31, 26, 1 },
+{ 0x11, 27, 0 },
+{ 0x71, 26, 1 },
+{ 0x31, 27, 0 },
+{ 0x29, 26, 0 },
+{ 0x69, 26, 0 },
+{ 0x19, 26, 1 },
+{ 0x9, 27, 0 },
+{ 0x39, 26, 1 },
+{ 0x19, 27, 0 },
+{ 0x15, 26, 0 },
+{ 0x35, 26, 0 },
+{ 0xd, 26, 1 },
+{ 0x5, 27, 0 },
+{ 0x1d, 26, 1 },
+{ 0xd, 27, 0 },
+{ 0xb, 26, 0 },
+{ 0x1b, 26, 0 },
+{ 0x7, 26, 1 },
+{ 0x3, 27, 0 },
+{ 0xf, 26, 1 },
+{ 0x7, 27, 0 },
+{ 0x51, 24, 0 },
+{ 0xd1, 24, 0 },
+{ 0x31, 24, 1 },
+{ 0x11, 25, 0 },
+{ 0x71, 24, 1 },
+{ 0x31, 25, 0 },
+{ 0x29, 24, 0 },
+{ 0x69, 24, 0 },
+{ 0x19, 24, 1 },
+{ 0x9, 25, 0 },
+{ 0x39, 24, 1 },
+{ 0x19, 25, 0 },
+{ 0x15, 24, 0 },
+{ 0x35, 24, 0 },
+{ 0xd, 24, 1 },
+{ 0x5, 25, 0 },
+{ 0x1d, 24, 1 },
+{ 0xd, 25, 0 },
+{ 0xb, 24, 0 },
+{ 0x1b, 24, 0 },
+{ 0x7, 24, 1 },
+{ 0x3, 25, 0 },
+{ 0xf, 24, 1 },
+{ 0x7, 25, 0 },
+{ 0xa2, 22, 0 },
+{ 0x1a2, 22, 0 },
+{ 0x62, 22, 1 },
+{ 0x22, 23, 0 },
+{ 0xe2, 22, 1 },
+{ 0x62, 23, 0 },
+{ 0x52, 22, 0 },
+{ 0xd2, 22, 0 },
+{ 0x32, 22, 1 },
+{ 0x12, 23, 0 },
+{ 0x72, 22, 1 },
+{ 0x32, 23, 0 },
+{ 0x2a, 22, 0 },
+{ 0x6a, 22, 0 },
+{ 0x1a, 22, 1 },
+{ 0xa, 23, 0 },
+{ 0x3a, 22, 1 },
+{ 0x1a, 23, 0 },
+{ 0x16, 22, 0 },
+{ 0x36, 22, 0 },
+{ 0xe, 22, 1 },
+{ 0x6, 23, 0 },
+{ 0x1e, 22, 1 },
+{ 0xe, 23, 0 },
+{ 0x51, 22, 0 },
+{ 0xd1, 22, 0 },
+{ 0x31, 22, 1 },
+{ 0x11, 23, 0 },
+{ 0x71, 22, 1 },
+{ 0x31, 23, 0 },
+{ 0x29, 22, 0 },
+{ 0x69, 22, 0 },
+{ 0x19, 22, 1 },
+{ 0x9, 23, 0 },
+{ 0x39, 22, 1 },
+{ 0x19, 23, 0 },
+{ 0x15, 22, 0 },
+{ 0x35, 22, 0 },
+{ 0xd, 22, 1 },
+{ 0x5, 23, 0 },
+{ 0x1d, 22, 1 },
+{ 0xd, 23, 0 },
+{ 0xb, 22, 0 },
+{ 0x1b, 22, 0 },
+{ 0x7, 22, 1 },
+{ 0x3, 23, 0 },
+{ 0xf, 22, 1 },
+{ 0x7, 23, 0 },
+{ 0x51, 20, 1 },
+{ 0x50, 20, 0 },
+{ 0xd1, 20, 1 },
+{ 0xd0, 20, 0 },
+{ 0x31, 20, 1 },
+{ 0x30, 20, 1 },
+{ 0x11, 21, 1 },
+{ 0x10, 21, 0 },
+{ 0x71, 20, 1 },
+{ 0x70, 20, 1 },
+{ 0x31, 21, 1 },
+{ 0x30, 21, 0 },
+{ 0x29, 20, 1 },
+{ 0x28, 20, 0 },
+{ 0x69, 20, 1 },
+{ 0x68, 20, 0 },
+{ 0x19, 20, 1 },
+{ 0x18, 20, 1 },
+{ 0x9, 21, 1 },
+{ 0x8, 21, 0 },
+{ 0x39, 20, 1 },
+{ 0x38, 20, 1 },
+{ 0x19, 21, 1 },
+{ 0x18, 21, 0 },
+{ 0x15, 20, 1 },
+{ 0x14, 20, 0 },
+{ 0x35, 20, 1 },
+{ 0x34, 20, 0 },
+{ 0xd, 20, 1 },
+{ 0xc, 20, 1 },
+{ 0x5, 21, 1 },
+{ 0x4, 21, 0 },
+{ 0x1d, 20, 1 },
+{ 0x1c, 20, 1 },
+{ 0xd, 21, 1 },
+{ 0xc, 21, 0 },
+{ 0xb, 20, 1 },
+{ 0xa, 20, 0 },
+{ 0x1b, 20, 1 },
+{ 0x1a, 20, 0 },
+{ 0x7, 20, 1 },
+{ 0x6, 20, 1 },
+{ 0x3, 21, 1 },
+{ 0x2, 21, 0 },
+{ 0xf, 20, 1 },
+{ 0xe, 20, 1 },
+{ 0x7, 21, 1 },
+{ 0x6, 21, 0 },
+{ 0x8, 19, 0 },
+{ 0x18, 19, 0 },
+{ 0x2, 19, 1 },
+{ 0xc, 19, 0 },
+{ 0x1, 19, 1 },
+{ 0x4, 19, 0 },
+{ 0x51, 17, 0 },
+{ 0xd1, 17, 0 },
+{ 0x31, 17, 1 },
+{ 0x11, 18, 0 },
+{ 0x71, 17, 1 },
+{ 0x31, 18, 0 },
+{ 0x29, 17, 0 },
+{ 0x69, 17, 0 },
+{ 0x19, 17, 1 },
+{ 0x9, 18, 0 },
+{ 0x39, 17, 1 },
+{ 0x19, 18, 0 },
+{ 0x15, 17, 0 },
+{ 0x35, 17, 0 },
+{ 0xd, 17, 1 },
+{ 0x5, 18, 0 },
+{ 0x1d, 17, 1 },
+{ 0xd, 18, 0 },
+{ 0xb, 17, 0 },
+{ 0x1b, 17, 0 },
+{ 0x7, 17, 1 },
+{ 0x3, 18, 0 },
+{ 0xf, 17, 1 },
+{ 0x7, 18, 0 },
+{ 0x51, 15, 0 },
+{ 0xd1, 15, 0 },
+{ 0x31, 15, 1 },
+{ 0x11, 16, 0 },
+{ 0x71, 15, 1 },
+{ 0x31, 16, 0 },
+{ 0x29, 15, 0 },
+{ 0x69, 15, 0 },
+{ 0x19, 15, 1 },
+{ 0x9, 16, 0 },
+{ 0x39, 15, 1 },
+{ 0x19, 16, 0 },
+{ 0x15, 15, 0 },
+{ 0x35, 15, 0 },
+{ 0xd, 15, 1 },
+{ 0x5, 16, 0 },
+{ 0x1d, 15, 1 },
+{ 0xd, 16, 0 },
+{ 0xb, 15, 0 },
+{ 0x1b, 15, 0 },
+{ 0x7, 15, 1 },
+{ 0x3, 16, 0 },
+{ 0xf, 15, 1 },
+{ 0x7, 16, 0 },
+{ 0x288, 13, 0 },
+{ 0x688, 13, 0 },
+{ 0x188, 13, 1 },
+{ 0x88, 14, 0 },
+{ 0x388, 13, 1 },
+{ 0x188, 14, 0 },
+{ 0x148, 13, 0 },
+{ 0x348, 13, 0 },
+{ 0xc8, 13, 1 },
+{ 0x48, 14, 0 },
+{ 0x1c8, 13, 1 },
+{ 0xc8, 14, 0 },
+{ 0xa8, 13, 0 },
+{ 0x1a8, 13, 0 },
+{ 0x68, 13, 1 },
+{ 0x28, 14, 0 },
+{ 0xe8, 13, 1 },
+{ 0x68, 14, 0 },
+{ 0x58, 13, 0 },
+{ 0xd8, 13, 0 },
+{ 0x38, 13, 1 },
+{ 0x18, 14, 0 },
+{ 0x78, 13, 1 },
+{ 0x38, 14, 0 },
+{ 0x51, 13, 1 },
+{ 0xa0, 13, 0 },
+{ 0xd1, 13, 1 },
+{ 0x1a0, 13, 0 },
+{ 0x31, 13, 1 },
+{ 0x60, 13, 1 },
+{ 0x11, 14, 1 },
+{ 0x20, 14, 0 },
+{ 0x71, 13, 1 },
+{ 0xe0, 13, 1 },
+{ 0x31, 14, 1 },
+{ 0x60, 14, 0 },
+{ 0x29, 13, 1 },
+{ 0x50, 13, 0 },
+{ 0x69, 13, 1 },
+{ 0xd0, 13, 0 },
+{ 0x19, 13, 1 },
+{ 0x30, 13, 1 },
+{ 0x9, 14, 1 },
+{ 0x10, 14, 0 },
+{ 0x39, 13, 1 },
+{ 0x70, 13, 1 },
+{ 0x19, 14, 1 },
+{ 0x30, 14, 0 },
+{ 0x15, 13, 1 },
+{ 0x14, 13, 0 },
+{ 0x35, 13, 1 },
+{ 0x34, 13, 0 },
+{ 0xd, 13, 1 },
+{ 0xc, 13, 1 },
+{ 0x5, 14, 1 },
+{ 0x4, 14, 0 },
+{ 0x1d, 13, 1 },
+{ 0x1c, 13, 1 },
+{ 0xd, 14, 1 },
+{ 0xc, 14, 0 },
+{ 0xb, 13, 1 },
+{ 0xa, 13, 0 },
+{ 0x1b, 13, 1 },
+{ 0x1a, 13, 0 },
+{ 0x7, 13, 1 },
+{ 0x6, 13, 1 },
+{ 0x3, 14, 1 },
+{ 0x2, 14, 0 },
+{ 0xf, 13, 1 },
+{ 0xe, 13, 1 },
+{ 0x7, 14, 1 },
+{ 0x6, 14, 0 },
+{ 0x8, 12, 0 },
+{ 0x18, 12, 0 },
+{ 0x2, 12, 1 },
+{ 0xc, 12, 0 },
+{ 0x1, 12, 1 },
+{ 0x4, 12, 0 },
+{ 0x1, 11, 0 },
+{ 0x1, 10, 0 },
+{ 0x1, 9, 0 },
+{ 0x1, 8, 0 },
+{ 0x1, 7, 0 },
+{ 0x1, 6, 0 },
+{ 0x1, 5, 0 },
+{ 0x1, 4, 0 },
+{ 0x1, 3, 0 },
+{ 0x1, 1, 0 },
+{ 0x1, 0, 0 },
+};
+
diff --git a/opcodes/ia64-asmtab.h b/opcodes/ia64-asmtab.h
new file mode 100644
index 0000000..2bbdee3
--- /dev/null
+++ b/opcodes/ia64-asmtab.h
@@ -0,0 +1,145 @@
+/* ia64-asmtab.h -- Header for compacted IA-64 opcode tables.
+   Copyright (C) 1999 Free Software Foundation, Inc.
+   Contributed by Bob Manson of Cygnus Support <manson@cygnus.com>
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the
+   Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
+
+#ifndef IA64_ASMTAB_H
+#define IA64_ASMTAB_H
+
+#include "opcode/ia64.h"
+
+/* The primary opcode table is made up of the following: */
+struct ia64_main_table
+{
+  /* The entry in the string table that corresponds to the name of this
+     opcode. */
+  unsigned short name_index;
+
+  /* The type of opcode; corresponds to the TYPE field in 
+     struct ia64_opcode. */
+  unsigned char opcode_type;
+
+  /* The number of outputs for this opcode. */
+  unsigned char num_outputs;
+
+  /* The base insn value for this opcode.  It may be modified by completers. */
+  ia64_insn opcode;
+
+  /* The mask of valid bits in OPCODE. Zeros indicate operand fields. */
+  ia64_insn mask;
+
+  /* The operands of this instruction.  Corresponds to the OPERANDS field
+     in struct ia64_opcode. */
+  unsigned char operands[5];
+
+  /* The flags for this instruction.  Corresponds to the FLAGS field in
+     struct ia64_opcode. */
+  short flags;
+
+  /* The tree of completers for this instruction; this is an offset into
+     completer_table. */
+  short completers;
+};
+
+/* Each instruction has a set of possible "completers", or additional
+   suffixes that can alter the instruction's behavior, and which has
+   potentially different dependencies.
+
+   The completer entries modify certain bits in the instruction opcode.
+   Which bits are to be modified are marked by the BITS, MASK and
+   OFFSET fields.  The completer entry may also note dependencies for the
+   opcode. 
+
+   These completers are arranged in a DAG; the pointers are indexes
+   into the completer_table array.  The completer DAG is searched by
+   find_completer () and ia64_find_matching_opcode ().
+
+   Note that each completer needs to be applied in turn, so that if we
+   have the instruction
+   	cmp.lt.unc
+   the completer entries for both "lt" and "unc" would need to be applied
+   to the opcode's value.
+
+   Some instructions do not require any completers; these contain an
+   empty completer entry.  Instructions that require a completer do
+   not contain an empty entry.
+
+   Terminal completers (those completers that validly complete an
+   instruction) are marked by having the TERMINAL_COMPLETER flag set. 
+
+   Only dependencies listed in the terminal completer for an opcode are
+   considered to apply to that opcode instance. */
+
+struct ia64_completer_table
+{
+  /* The bit value that this completer sets. */
+  unsigned int bits;
+
+  /* And its mask. 1s are bits that are to be modified in the 
+     instruction. */
+  unsigned int mask;
+
+  /* The entry in the string table that corresponds to the name of this
+     completer. */
+  unsigned short name_index;
+
+  /* An alternative completer, or -1 if this is the end of the chain. */
+  short alternative;
+
+  /* A pointer to the DAG of completers that can potentially follow
+     this one, or -1. */
+  short subentries;
+
+  /* The bit offset in the instruction where BITS and MASK should be
+     applied. */
+  unsigned char offset : 7;
+
+  unsigned char terminal_completer : 1;
+
+  /* Index into the dependency list table */
+  short dependencies;
+};
+
+/* This contains sufficient information for the disassembler to resolve
+   the complete name of the original instruction.  */
+struct ia64_dis_names 
+{
+  /* COMPLETER_INDEX represents the tree of completers that make up
+     the instruction.  The LSB represents the top of the tree for the
+     specified instruction. 
+
+     A 0 bit indicates to go to the next alternate completer via the
+     alternative field; a 1 bit indicates that the current completer
+     is part of the instruction, and to go down the subentries index.
+     We know we've reached the final completer when we run out of 1
+     bits.
+
+     There is always at least one 1 bit. */
+  unsigned int completer_index : 20;
+
+  /* The index in the main_table[] array for the instruction. */
+  unsigned short insn_index : 11;
+
+  /* If set, the next entry in this table is an alternate possibility
+     for this instruction encoding.  Which one to use is determined by
+     the instruction type and other factors (see opcode_verify ()).  */
+  unsigned int next_flag : 1;
+};
+
+#endif
diff --git a/opcodes/ia64-dis.c b/opcodes/ia64-dis.c
new file mode 100644
index 0000000..7a68597
--- /dev/null
+++ b/opcodes/ia64-dis.c
@@ -0,0 +1,264 @@
+/* ia64-dis.c -- Disassemble ia64 instructions
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the
+   Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
+
+#include <assert.h>
+#include <string.h>
+
+#include "dis-asm.h"
+#include "opcode/ia64.h"
+
+#define NELEMS(a)	((int) (sizeof (a) / sizeof (a[0])))
+
+/* Disassemble ia64 instruction.  */
+
+/* Return the instruction type for OPCODE found in unit UNIT. */
+
+static enum ia64_insn_type
+unit_to_type (ia64_insn opcode, enum ia64_unit unit)
+{
+  enum ia64_insn_type type;
+  int op;
+
+  op = IA64_OP (opcode);
+
+  if (op >= 8 && (unit == IA64_UNIT_I || unit == IA64_UNIT_M))
+    {
+      type = IA64_TYPE_A;
+    }
+  else
+    {
+      switch (unit)
+	{
+	case IA64_UNIT_I:
+	  type = IA64_TYPE_I; break;
+	case IA64_UNIT_M:
+	  type = IA64_TYPE_M; break;
+	case IA64_UNIT_B:
+	  type = IA64_TYPE_B; break;
+	case IA64_UNIT_F:
+	  type = IA64_TYPE_F; break;
+        case IA64_UNIT_L:
+	case IA64_UNIT_X:
+	  type = IA64_TYPE_X; break;
+	default:
+	  type = -1;
+	}
+    }
+  return type;
+}
+
+int
+print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
+{
+  ia64_insn t0, t1, slot[3], template, s_bit, insn;
+  int slotnum, j, status, need_comma, retval, slot_multiplier;
+  const struct ia64_operand *odesc;
+  const struct ia64_opcode *idesc;
+  const char *err, *str, *tname;
+  BFD_HOST_U_64_BIT value;
+  bfd_byte bundle[16];
+  enum ia64_unit unit;
+  char regname[16];
+
+  if (info->bytes_per_line == 0)
+    info->bytes_per_line = 6;
+  info->display_endian = info->endian;
+
+  slot_multiplier = info->bytes_per_line;
+  retval = slot_multiplier;
+
+  slotnum = (((long) memaddr) & 0xf) / slot_multiplier;
+  if (slotnum > 2)
+    return -1;
+
+  memaddr -= (memaddr & 0xf);
+  status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info);
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, memaddr, info);
+      return -1;
+    }
+  /* bundles are always in little-endian byte order */
+  t0 = bfd_getl64 (bundle);
+  t1 = bfd_getl64 (bundle + 8);
+  s_bit = t0 & 1;
+  template = (t0 >> 1) & 0xf;
+  slot[0] = (t0 >>  5) & 0x1ffffffffffLL;
+  slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
+  slot[2] = (t1 >> 23) & 0x1ffffffffffLL;
+
+  tname = ia64_templ_desc[template].name;
+  if (slotnum == 0)
+    (*info->fprintf_func) (info->stream, "[%s] ", tname);
+  else
+    (*info->fprintf_func) (info->stream, "      ", tname);
+
+  unit = ia64_templ_desc[template].exec_unit[slotnum];
+
+  if (template == 2 && slotnum == 1)
+    {
+      /* skip L slot in MLI template: */
+      slotnum = 2;
+      retval += slot_multiplier;
+    }
+
+  insn = slot[slotnum];
+
+  if (unit == IA64_UNIT_NIL)
+    goto decoding_failed;
+
+  idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit));
+  if (idesc == NULL)
+    goto decoding_failed;
+
+  /* print predicate, if any: */
+
+  if ((idesc->flags & IA64_OPCODE_NO_PRED)
+      || (insn & 0x3f) == 0)
+    (*info->fprintf_func) (info->stream, "      ");
+  else
+    (*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f));
+
+  /* now the actual instruction: */
+
+  (*info->fprintf_func) (info->stream, "%s", idesc->name);
+  if (idesc->operands[0])
+    (*info->fprintf_func) (info->stream, " ");
+
+  need_comma = 0;
+  for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j)
+    {
+      odesc = elf64_ia64_operands + idesc->operands[j];
+
+      if (need_comma)
+	(*info->fprintf_func) (info->stream, ",");
+
+      if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
+	{
+	  /* special case of 64 bit immediate load: */
+	  value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7)
+	    | (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21)
+	    | (slot[1] << 22) | (((insn >> 36) & 0x1) << 63);
+	}
+      else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
+        {
+          /* 62-bit immediate for nop.x/break.x */
+          value = ((slot[1] & 0x1ffffffffffLL) << 21)
+            | (((insn >> 36) & 0x1) << 20)
+            | ((insn >> 6) & 0xfffff);
+        }
+      else
+	{
+	  err = (*odesc->extract) (odesc, insn, &value);
+	  if (err)
+	    {
+	      (*info->fprintf_func) (info->stream, "%s", err);
+	      goto done;
+	    }
+	}
+
+	switch (odesc->class)
+	  {
+	  case IA64_OPND_CLASS_CST:
+	    (*info->fprintf_func) (info->stream, "%s", odesc->str);
+	    break;
+
+	  case IA64_OPND_CLASS_REG:
+	    if (odesc->str[0] == 'a' && odesc->str[1] == 'r')
+	      {
+		switch (value)
+		  {
+		  case 0: case 1: case 2: case 3:
+		  case 4: case 5: case 6: case 7:
+		    sprintf (regname, "ar.k%u", (unsigned int) value);
+		    break;
+		  case 16:	strcpy (regname, "ar.rsc"); break;
+		  case 17:	strcpy (regname, "ar.bsp"); break;
+		  case 18:	strcpy (regname, "ar.bspstore"); break;
+		  case 19:	strcpy (regname, "ar.rnat"); break;
+		  case 32:	strcpy (regname, "ar.ccv"); break;
+		  case 36:	strcpy (regname, "ar.unat"); break;
+		  case 40:	strcpy (regname, "ar.fpsr"); break;
+		  case 44:	strcpy (regname, "ar.itc"); break;
+		  case 64:	strcpy (regname, "ar.pfs"); break;
+		  case 65:	strcpy (regname, "ar.lc"); break;
+		  case 66:	strcpy (regname, "ar.ec"); break;
+		  default:
+		    sprintf (regname, "ar%u", (unsigned int) value);
+		    break;
+		  }
+		(*info->fprintf_func) (info->stream, "%s", regname);
+	      }
+	    else
+	      (*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value);
+	    break;
+
+	  case IA64_OPND_CLASS_IND:
+	    (*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value);
+	    break;
+
+	  case IA64_OPND_CLASS_ABS:
+	    str = 0;
+	    if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4)
+	      switch (value)
+		{
+		case 0x0: str = "@brcst"; break;
+		case 0x8: str = "@mix"; break;
+		case 0x9: str = "@shuf"; break;
+		case 0xa: str = "@alt"; break;
+		case 0xb: str = "@rev"; break;
+		}
+
+	    if (str)
+	      (*info->fprintf_func) (info->stream, "%s", str);
+	    else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED)
+	      (*info->fprintf_func) (info->stream, "%lld", value);
+	    else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED)
+	      (*info->fprintf_func) (info->stream, "%llu", value);
+	    else
+	      (*info->fprintf_func) (info->stream, "0x%llx", value);
+	    break;
+
+	  case IA64_OPND_CLASS_REL:
+	    (*info->print_address_func) (memaddr + value, info);
+	    break;
+	  }
+
+      need_comma = 1;
+      if (j + 1 == idesc->num_outputs)
+	{
+	  (*info->fprintf_func) (info->stream, "=");
+	  need_comma = 0;
+	}
+    }
+  if (slotnum + 1 == ia64_templ_desc[template].group_boundary 
+      || ((slotnum == 2) && s_bit))
+    (*info->fprintf_func) (info->stream, ";;");
+
+ done:
+  if (slotnum == 2)
+    retval += 16 - 3*slot_multiplier;
+  return retval;
+
+ decoding_failed:
+  (*info->fprintf_func) (info->stream, "      data8 %#011llx", insn);
+  goto done;
+}
diff --git a/opcodes/ia64-gen.c b/opcodes/ia64-gen.c
new file mode 100644
index 0000000..093d686
--- /dev/null
+++ b/opcodes/ia64-gen.c
@@ -0,0 +1,2723 @@
+/* ia64-gen.c -- Generate a shrunk set of opcode tables
+   Copyright (c) 1999 Free Software Foundation, Inc.
+   Written by Bob Manson, Cygnus Solutions, <manson@cygnus.com>
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the
+   Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
+
+/* While the ia64-opc-* set of opcode tables are easy to maintain,
+   they waste a tremendous amount of space.  ia64-gen rearranges the
+   instructions into a directed acyclic graph (DAG) of instruction opcodes and 
+   their possible completers, as well as compacting the set of strings used.  
+
+   The disassembler table consists of a state machine that does
+   branching based on the bits of the opcode being disassembled.  The
+   state encodings have been chosen to minimize the amount of space
+   required.  
+
+   The resource table is constructed based on some text dependency tables, 
+   which are also easier to maintain than the final representation.
+
+*/
+
+#include <stdio.h>
+#include <ctype.h>
+
+#include "ansidecl.h"
+#include "libiberty.h"
+#include "sysdep.h"
+#include "ia64-opc.h"
+#include "ia64-opc-a.c"
+#include "ia64-opc-i.c"
+#include "ia64-opc-m.c"
+#include "ia64-opc-b.c"
+#include "ia64-opc-f.c"
+#include "ia64-opc-x.c"
+#include "ia64-opc-d.c"
+
+int debug = 0;
+
+#define tmalloc(X) (X *) xmalloc (sizeof (X))
+
+/* The main opcode table entry.  Each entry is a unique combination of
+   name and flags (no two entries in the table compare as being equal
+   via opcodes_eq). */
+struct main_entry
+{
+  /* The base name of this opcode.  The names of its completers are
+     appended to it to generate the full instruction name. */
+  struct string_entry *name;
+  /* The base opcode entry.  Which one to use is a fairly arbitrary choice;
+     it uses the first one passed to add_opcode_entry. */
+  struct ia64_opcode *opcode;
+  /* The list of completers that can be applied to this opcode. */
+  struct completer_entry *completers;
+  /* Next entry in the chain. */
+  struct main_entry *next;
+} *maintable;
+
+/* The set of possible completers for an opcode. */
+struct completer_entry
+{
+  /* This entry's index in the ia64_completer_table[] array. */
+  int num;
+
+  /* The name of the completer. */
+  struct string_entry *name;
+
+  /* This entry's parent. */
+  struct completer_entry *parent;
+
+  /* Set if this is a terminal completer (occurs at the end of an
+     opcode). */
+  int is_terminal;
+
+  /* An alternative completer. */
+  struct completer_entry *alternative;
+
+  /* Additional completers that can be appended to this one.  */
+  struct completer_entry *addl_entries;
+
+  /* Before compute_completer_bits () is invoked, this contains the actual
+     instruction opcode for this combination of opcode and completers.
+     Afterwards, it contains those bits that are different from its
+     parent opcode. */
+  ia64_insn bits;
+
+  /* Bits set to 1 correspond to those bits in this completer's opcode
+     that are different from its parent completer's opcode (or from
+     the base opcode if the entry is the root of the opcode's completer
+     list).  This field is filled in by compute_completer_bits (). */
+  ia64_insn mask;
+
+  /* Index into the opcode dependency list, or -1 if none */
+  int dependencies;
+};
+
+/* One entry in the disassembler name table. */
+struct disent
+{
+  /* The index into the ia64_name_dis array for this entry. */
+  int ournum;
+
+  /* The index into the main_table[] array. */
+  int insn;
+
+  /* The completer_index value for this entry. */
+  int completer_index;
+
+  /* How many other entries share this decode. */
+  int nextcnt;
+
+  /* The next entry sharing the same decode. */
+  struct disent *nexte;
+
+  /* The next entry in the name list. */
+  struct disent *next_ent;
+} *disinsntable = NULL;
+
+/* A state machine that will eventually be used to generate the
+   disassembler table. */
+struct bittree
+{
+  struct disent *disent;
+  struct bittree *bits[3];
+  int bits_to_skip;
+  int skip_flag;
+} *bittree;
+
+/* The string table contains all opcodes and completers sorted in
+   alphabetical order.  */
+
+/* One entry in the string table. */
+struct string_entry 
+{
+  /* The index in the ia64_strings[] array for this entry. */
+  int num;
+  /* And the string. */
+  char *s;
+} **string_table = NULL;
+int strtablen = 0;
+int strtabtotlen = 0;
+
+
+/* resource dependency entries */
+struct rdep
+{
+  char *name;                       /* resource name */
+  unsigned 
+    mode:2,                         /* RAW, WAW, or WAR */
+    semantics:3;                    /* dependency semantics */
+  char *extra;                      /* additional semantics info */
+  int nchks;                   
+  int total_chks;                   /* total #of terminal insns */
+  int *chks;                        /* insn classes which read (RAW), write
+                                       (WAW), or write (WAR) this rsrc */ // 
+  int *chknotes;                    /* dependency notes for each class */
+  int nregs;
+  int total_regs;                   /* total #of terminal insns */
+  int *regs;                        /* insn class which write (RAW), write2
+                                       (WAW), or read (WAR) this rsrc */
+  int *regnotes;                    /* dependency notes for each class */
+
+  int waw_special;                  /* special WAW dependency note */
+} **rdeps = NULL;
+
+static int rdepslen = 0;
+static int rdepstotlen = 0;
+
+/* array of all instruction classes */
+struct iclass
+{ 
+  char *name;                       /* instruction class name */
+  int is_class;                     /* is a class, not a terminal */
+  int nsubs;                        
+  int *subs;                        /* other classes within this class */
+  int nxsubs;                       
+  int xsubs[4];                     /* exclusions */
+  char *comment;                    /* optional comment */
+  int note;                         /* optional note */
+  int terminal_resolved;            /* did we match this with anything? */
+  int orphan;                       /* detect class orphans */
+} **ics = NULL;
+
+static int iclen = 0;
+static int ictotlen = 0;
+
+/* an opcode dependency (chk/reg pair of dependency lists) */
+struct opdep
+{
+  int chk;                          /* index into dlists */
+  int reg;                          /* index into dlists */
+} **opdeps;
+
+static int opdeplen = 0;
+static int opdeptotlen = 0;
+
+/* a generic list of dependencies w/notes encoded.  these may be shared. */
+struct deplist
+{
+  int len;
+  unsigned short *deps;
+} **dlists;
+
+static int dlistlen = 0;
+static int dlisttotlen = 0;
+
+/* add NAME to the resource table, where TYPE is RAW or WAW */
+static struct rdep *
+insert_resource (const char *name, enum ia64_dependency_mode type)
+{
+  if (rdepslen == rdepstotlen)
+    {
+      rdepstotlen += 20;
+      rdeps = (struct rdep **)
+        xrealloc (rdeps, sizeof(struct rdep **) * rdepstotlen);
+    }
+  rdeps[rdepslen] = tmalloc(struct rdep);
+  memset((void *)rdeps[rdepslen], 0, sizeof(struct rdep));
+  rdeps[rdepslen]->name = xstrdup (name);
+  rdeps[rdepslen]->mode = type;
+  rdeps[rdepslen]->waw_special = 0;
+  
+  return rdeps[rdepslen++];
+}
+
+/* are the lists of dependency indexes equivalent? */
+static int
+deplist_equals (struct deplist *d1, struct deplist *d2)
+{
+  int i;
+
+  if (d1->len != d2->len)
+    return 0;
+
+  for (i=0;i < d1->len;i++)
+    {
+      if (d1->deps[i] != d2->deps[i])
+        return 0;
+    }
+
+  return 1;
+}
+
+/* add the list of dependencies to the list of dependency lists */
+static short
+insert_deplist(int count, unsigned short *deps)
+{
+  /* sort the list, then see if an equivalent list exists already.
+     this results in a much smaller set of dependency lists
+   */
+  struct deplist *list;
+  char set[0x10000];
+  int i;
+
+  memset ((void *)set, 0, sizeof(set));
+  for (i=0;i < count;i++)
+    set[deps[i]] = 1;
+  count = 0;
+  for (i=0;i < sizeof(set);i++)
+    if (set[i])
+      ++count;
+
+  list = tmalloc(struct deplist);
+  list->len = count;
+  list->deps = (unsigned short *)malloc (sizeof(unsigned short) * count);
+  for (i=0, count=0;i < sizeof(set);i++)
+    {
+      if (set[i])
+        {
+          list->deps[count++] = i;
+        }
+    }
+
+  /* does this list exist already? */
+  for (i=0;i < dlistlen;i++)
+    {
+      if (deplist_equals (list, dlists[i]))
+        {
+          free (list->deps);
+          free (list);
+          return i;
+        }
+    }
+
+  if (dlistlen == dlisttotlen)
+    {
+      dlisttotlen += 20;
+      dlists = (struct deplist **)
+        xrealloc (dlists, sizeof(struct deplist **) * dlisttotlen);
+    }
+  dlists[dlistlen] = list;
+
+  return dlistlen++;
+}
+
+/* add the given pair of dependency lists to the opcode dependency list */
+static short
+insert_dependencies (int nchks, unsigned short *chks, 
+                     int nregs, unsigned short *regs)
+{
+  struct opdep *pair;
+  int i;
+  int regind = -1;
+  int chkind = -1;
+
+  if (nregs > 0)
+    regind = insert_deplist (nregs, regs);
+  if (nchks > 0)
+    chkind = insert_deplist (nchks, chks);
+
+  for (i=0;i < opdeplen;i++)
+    {
+      if (opdeps[i]->chk == chkind 
+          && opdeps[i]->reg == regind)
+        return i;
+    }
+  pair = tmalloc(struct opdep);
+  pair->chk = chkind;
+  pair->reg = regind;
+  
+  if (opdeplen == opdeptotlen)
+    {
+      opdeptotlen += 20;
+      opdeps = (struct opdep **)
+        xrealloc (opdeps, sizeof(struct opdep **) * opdeptotlen);
+    }
+  opdeps[opdeplen] = pair;
+
+  return opdeplen++;
+}
+
+static void 
+mark_used (struct iclass *ic, int clear_terminals)
+{
+  int i;
+
+  ic->orphan = 0;
+  if (clear_terminals)
+    ic->terminal_resolved = 1;
+
+  for (i=0;i < ic->nsubs;i++)
+    {
+      mark_used (ics[ic->subs[i]], clear_terminals);
+    }
+  for (i=0;i < ic->nxsubs;i++)
+    {
+      mark_used (ics[ic->xsubs[i]], clear_terminals);
+    }
+}
+
+/* look up an instruction class; if CREATE make a new one if none found;
+   returns the index into the insn class array */
+static int
+fetch_insn_class(const char *full_name, int create)
+{
+  char *name;
+  char *notestr;
+  char *xsect;
+  char *comment;
+  int i, note = 0;
+  int ind;
+  int is_class = 0;
+
+  if (strncmp (full_name, "IC:", 3) == 0)
+    {
+      name = xstrdup (full_name + 3);
+      is_class = 1;
+    }
+  else
+    name = xstrdup (full_name);
+
+  if ((xsect = strchr(name, '\\')) != NULL)
+    is_class = 1;
+  if ((comment = strchr(name, '[')) != NULL)
+    is_class = 1;
+  if ((notestr = strchr(name, '+')) != NULL)
+    {
+      char *nextnotestr;
+      is_class = 1;
+      note = atoi (notestr + 1);
+      if ((nextnotestr = strchr (notestr + 1, '+')) != NULL)
+        {
+          if (strcmp (notestr, "+1+13") == 0)
+            note = 13;
+          else if (!xsect || nextnotestr < xsect)
+            fprintf (stderr, "Warning: multiple note %s not handled\n",
+                     notestr);
+        }
+    }
+
+  /* if it's a composite class, leave the notes and comments in place so that
+     we have a unique name for the composite class */
+  if (!xsect)
+    {
+      if (notestr)
+        *notestr = 0;
+      if (comment)
+        *comment = 0;
+    }
+
+  for (i=0;i < iclen;i++)
+    if (strcmp(name, ics[i]->name) == 0
+        && ((comment == NULL && ics[i]->comment == NULL)
+            || (comment != NULL && ics[i]->comment != NULL
+                && strncmp (ics[i]->comment, comment, 
+                            strlen (ics[i]->comment)) == 0))
+        && note == ics[i]->note)
+      return i;
+
+  if (!create)
+    return -1;
+
+  /* doesn't exist, so make a new one */
+  if (iclen == ictotlen)
+    {
+      ictotlen += 20;
+      ics = (struct iclass **)
+        xrealloc(ics, (ictotlen)*sizeof(struct iclass *));
+    }
+  ind = iclen++;
+  ics[ind] = tmalloc(struct iclass);
+  memset((void *)ics[ind], 0, sizeof(struct iclass));
+  ics[ind]->name = xstrdup(name);
+  ics[ind]->is_class = is_class;
+  ics[ind]->orphan = 1;
+
+  if (comment)
+    {
+      ics[ind]->comment = xstrdup (comment + 1);
+      ics[ind]->comment[strlen(ics[ind]->comment)-1] = 0;
+    }
+  if (notestr)
+    ics[ind]->note = note;
+
+  /* if it's a composite class, there's a comment or note, look for an
+     existing class or terminal with the same name. */ 
+  if ((xsect || comment || notestr) && is_class)
+    {
+      // first, populate with the class we're based on
+      char *subname = name;
+      if (xsect)
+        *xsect = 0;
+      else if (comment)
+        *comment = 0;
+      else if (notestr)
+        *notestr = 0;
+      ics[ind]->nsubs = 1;
+      ics[ind]->subs = tmalloc(int);
+      ics[ind]->subs[0] = fetch_insn_class (subname, 1);;
+    }
+
+  while (xsect)
+    {
+      char *subname = xsect + 1;
+      xsect = strchr (subname, '\\');
+      if (xsect)
+        *xsect = 0;
+      ics[ind]->xsubs[ics[ind]->nxsubs] = fetch_insn_class (subname,1);
+      ics[ind]->nxsubs++;
+    }
+  free (name);
+
+  return ind;
+}
+
+/* for sorting a class's sub-class list only; make sure classes appear before
+   terminals  */
+static int
+sub_compare (const void *e1, const void *e2)
+{
+  struct iclass *ic1 = ics[*(int *)e1];
+  struct iclass *ic2 = ics[*(int *)e2];
+
+  if (ic1->is_class)
+    {
+      if (!ic2->is_class)
+        return -1;
+    }
+  else if (ic2->is_class)
+    return 1;
+
+  return strcmp (ic1->name, ic2->name);
+}
+
+static void
+load_insn_classes()
+{
+  FILE *fp = fopen("ia64-ic.tbl", "r");
+  char buf[2048];
+
+  /* discard first line */
+  fgets (buf, sizeof(buf), fp);
+
+  while (!feof(fp))
+    {
+      int iclass;
+      char *name;
+      char *tmp;
+      
+      if (fgets (buf, sizeof(buf), fp) == NULL)
+        break;
+      
+      while (isspace(buf[strlen(buf)-1]))
+        buf[strlen(buf)-1] = '\0';
+
+      name = tmp = buf;
+      while (*tmp != ';')
+        {
+          ++tmp;
+          if (tmp == buf + sizeof(buf))
+            abort ();
+        }
+      *tmp++ = '\0';
+
+      iclass = fetch_insn_class(name, 1);
+      ics[iclass]->is_class = 1;
+
+      if (strcmp (name, "none") == 0)
+        {
+          ics[iclass]->is_class = 0;
+          ics[iclass]->terminal_resolved = 1;
+          continue;
+        }
+
+      /* for this class, record all sub-classes */
+      while (*tmp)
+        {
+          char *subname;
+          int sub;
+
+          while (*tmp && isspace(*tmp))
+            {
+              ++tmp;
+              if (tmp == buf + sizeof(buf))
+                abort();
+            }
+          subname = tmp;
+          while (*tmp && *tmp != ',')
+            {
+              ++tmp;
+              if (tmp == buf + sizeof(buf))
+                abort();
+            }
+          if (*tmp == ',')
+            *tmp++ = '\0';
+          
+          ics[iclass]->subs = (int *)
+            xrealloc((void *)ics[iclass]->subs, 
+                     (ics[iclass]->nsubs+1)*sizeof(int));
+
+          sub = fetch_insn_class(subname, 1);
+          ics[iclass]->subs = (int *)
+            xrealloc(ics[iclass]->subs, (ics[iclass]->nsubs+1)*sizeof(int));
+          ics[iclass]->subs[ics[iclass]->nsubs++] = sub;
+        }
+      /* make sure classes come before terminals */
+      qsort ((void *)ics[iclass]->subs, 
+             ics[iclass]->nsubs, sizeof(int), sub_compare);
+    }
+  fclose(fp);
+
+  if (debug)
+    {
+      printf ("%d classes\n", iclen);
+    }
+}
+
+/* extract the insn classes from the given line */
+static void
+parse_resource_users(ref, usersp, nusersp, notesp)
+  char *ref;
+  int **usersp;
+  int *nusersp;
+  int **notesp;
+{
+  int c;
+  char *line = xstrdup (ref);
+  char *tmp = line;
+  int *users = *usersp;
+  int count = *nusersp;
+  int *notes = *notesp;
+
+  c = *tmp;
+  while (c != 0)
+    {
+      char *notestr;
+      int note;
+      char *xsect;
+      int iclass;
+      int create = 0;
+      char *name;
+      
+      while (isspace(*tmp))
+        ++tmp;
+      name = tmp;
+      while (*tmp && *tmp != ',')
+        ++tmp;
+      c = *tmp;
+      *tmp++ = '\0';
+      
+      xsect = strchr(name, '\\');
+      if ((notestr = strstr(name, "+")) != NULL)
+        {
+          char *nextnotestr;
+          note = atoi (notestr + 1);
+          if ((nextnotestr = strchr (notestr + 1, '+')) != NULL)
+            {
+              /* note 13 always implies note 1 */
+              if (strcmp (notestr, "+1+13") == 0)
+                note = 13;
+              else if (!xsect || nextnotestr < xsect)
+                fprintf (stderr, "Warning: multiple note %s not handled\n",
+                         notestr);
+            }
+          if (!xsect)
+            *notestr = '\0';
+        }
+      else 
+        note = 0;
+      
+      /* All classes are created when the insn class table is parsed;
+         Individual instructions might not appear until the dependency tables
+         are read.  Only create new classes if it's *not* an insn class,
+         or if it's a composite class (which wouldn't necessarily be in the IC
+         table).
+      */
+      if (strncmp(name, "IC:", 3) != 0 || xsect != NULL)
+        create = 1;
+      
+      iclass = fetch_insn_class(name, create);
+      if (iclass != -1)
+        {
+          users = (int *)
+            xrealloc ((void *)users,(count+1)*sizeof(int));
+          notes = (int *)
+            xrealloc ((void *)notes,(count+1)*sizeof(int));
+          notes[count] = note;
+          users[count++] = iclass;
+          mark_used (ics[iclass], 0);
+        }
+      else
+        {
+          if (debug)
+            printf("Class %s not found\n", name);
+        }
+    }
+  /* update the return values */
+  *usersp = users;
+  *nusersp = count;
+  *notesp = notes;
+
+  free (line);
+}
+
+static int
+parse_semantics (char *sem)
+{
+  if (strcmp (sem, "none") == 0)
+    return IA64_DVS_NONE;
+  else if (strcmp (sem, "implied") == 0)
+    return IA64_DVS_IMPLIED;
+  else if (strcmp (sem, "impliedF") == 0)
+    return IA64_DVS_IMPLIEDF;
+  else if (strcmp (sem, "data") == 0)
+    return IA64_DVS_DATA;
+  else if (strcmp (sem, "instr") == 0)
+    return IA64_DVS_INSTR;
+  else if (strcmp (sem, "specific") == 0)
+    return IA64_DVS_SPECIFIC;
+  else 
+    return IA64_DVS_OTHER;
+}
+
+static void
+add_dep (const char *name, const char *chk, const char *reg,
+         int semantics, int mode, char *extra, int flag)
+{
+  struct rdep *rs;
+
+  rs = insert_resource (name, mode);
+  parse_resource_users (chk, &rs->chks, &rs->nchks,
+                        &rs->chknotes);
+  parse_resource_users (reg, &rs->regs, &rs->nregs,
+                        &rs->regnotes);
+  rs->semantics = semantics;
+  rs->extra = extra;
+  rs->waw_special = flag;
+}
+
+static void
+load_depfile (const char *filename, enum ia64_dependency_mode mode)
+{
+  FILE *fp = fopen(filename, "r");
+  char buf[1024];
+
+  fgets(buf, sizeof(buf), fp);
+  while (!feof(fp))
+    {
+      char *name, *tmp;
+      int semantics;
+      char *extra;
+      char *regp, *chkp;
+
+      if (fgets (buf, sizeof(buf), fp) == NULL)
+        break;
+
+      while (isspace(buf[strlen(buf)-1]))
+        buf[strlen(buf)-1] = '\0';
+
+      name = tmp = buf;
+      while (*tmp != ';')
+        ++tmp;
+      *tmp++ = '\0';
+      
+      while (isspace (*tmp))
+        ++tmp;
+      regp = tmp;
+      tmp = strchr (tmp, ';');
+      if (!tmp)
+        abort ();
+      *tmp++ = 0;
+      while (isspace (*tmp))
+        ++tmp;
+      chkp = tmp;
+      tmp = strchr (tmp, ';');
+      if (!tmp)
+        abort ();
+      *tmp++ = 0;
+      while (isspace (*tmp))
+        ++tmp;
+      semantics = parse_semantics (tmp);
+      extra = semantics == IA64_DVS_OTHER ? xstrdup (tmp) : NULL;
+
+      /* For WAW entries, if the chks and regs differ, we need to enter the
+         entries in both positions so that the tables will be parsed properly,
+         without a lot of extra work */
+      if (mode == IA64_DV_WAW && strcmp (regp, chkp) != 0)
+        {
+          add_dep (name, chkp, regp, semantics, mode, extra, 0);
+          add_dep (name, regp, chkp, semantics, mode, extra, 1);
+        }
+      else
+        {
+          add_dep (name, chkp, regp, semantics, mode, extra, 0);
+        }
+    }
+  fclose(fp);
+}
+
+static void
+load_dependencies()
+{
+  load_depfile ("ia64-raw.tbl", IA64_DV_RAW);
+  load_depfile ("ia64-waw.tbl", IA64_DV_WAW);
+  load_depfile ("ia64-war.tbl", IA64_DV_WAR);
+
+  if (debug)
+      printf ("%d RAW/WAW/WAR dependencies\n", rdepslen);
+}
+
+/* is the given operand an indirect register file operand? */
+static int 
+irf_operand (int op, const char *field)
+{
+  if (!field)
+    {
+      return op == IA64_OPND_RR_R3 || op == IA64_OPND_DBR_R3
+        || op == IA64_OPND_IBR_R3 || op == IA64_OPND_PKR_R3
+        || op == IA64_OPND_PMC_R3 || op == IA64_OPND_PMD_R3
+	|| op == IA64_OPND_MSR_R3 || op == IA64_OPND_CPUID_R3;
+    }
+  else
+    {
+      return ((op == IA64_OPND_RR_R3 && strstr (field, "rr"))
+              || (op == IA64_OPND_DBR_R3 && strstr (field, "dbr"))
+              || (op == IA64_OPND_IBR_R3 && strstr (field, "ibr"))
+              || (op == IA64_OPND_PKR_R3 && strstr (field, "pkr"))
+              || (op == IA64_OPND_PMC_R3 && strstr (field, "pmc"))
+              || (op == IA64_OPND_PMD_R3 && strstr (field, "pmd"))
+              || (op == IA64_OPND_MSR_R3 && strstr (field, "msr"))
+              || (op == IA64_OPND_CPUID_R3 && strstr (field, "cpuid")));
+    }
+}
+
+/* handle mov_ar, mov_br, mov_cr, mov_indirect, mov_ip, mov_pr, mov_psr, and
+   mov_um insn classes */
+static int
+in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic, 
+                 const char *format, const char *field)
+{
+  int plain_mov = strcmp (idesc->name, "mov") == 0;
+
+  if (!format)
+    return 0;
+
+  switch (ic->name[4])
+    {
+    default:
+      abort ();
+    case 'a':
+      {
+        int i = strcmp (idesc->name, "mov.i") == 0;
+        int m = strcmp (idesc->name, "mov.m") == 0;
+        int i2627 = i && idesc->operands[0] == IA64_OPND_AR3;
+        int i28 = i && idesc->operands[1] == IA64_OPND_AR3;
+        int m2930 = m && idesc->operands[0] == IA64_OPND_AR3;
+        int m31 = m && idesc->operands[1] == IA64_OPND_AR3;
+        int pseudo0 = plain_mov && idesc->operands[1] == IA64_OPND_AR3;
+        int pseudo1 = plain_mov && idesc->operands[0] == IA64_OPND_AR3;
+
+        /* IC:mov ar */
+        if (i2627)
+          return strstr (format, "I26") || strstr (format, "I27");
+        if (i28)
+          return strstr (format, "I28") != NULL;
+        if (m2930)
+          return strstr (format, "M29") || strstr (format, "M30");
+        if (m31)
+          return strstr (format, "M31") != NULL;
+        if (pseudo0 || pseudo1)
+          return 1;
+      }
+      break;
+    case 'b':
+      {
+        int i21 = idesc->operands[0] == IA64_OPND_B1;
+        int i22 = plain_mov && idesc->operands[1] == IA64_OPND_B2;
+        if (i22)
+          return strstr (format, "I22") != NULL;
+        if (i21)
+          return strstr (format, "I21") != NULL;
+      }
+      break;
+    case 'c':
+      {
+        int m32 = plain_mov && idesc->operands[0] == IA64_OPND_CR3;
+        int m33 = plain_mov && idesc->operands[1] == IA64_OPND_CR3;
+        if (m32)
+          return strstr (format, "M32") != NULL;
+        if (m33)
+          return strstr (format, "M33") != NULL;
+      }
+      break;
+    case 'i':
+      if (ic->name[5] == 'n')
+        {
+          int m42 = plain_mov && irf_operand (idesc->operands[0], field);
+          int m43 = plain_mov && irf_operand (idesc->operands[1], field);
+          if (m42)
+            return strstr (format, "M42") != NULL;
+          if (m43)
+            return strstr (format, "M43") != NULL;
+        }
+      else if (ic->name[5] == 'p')
+        {
+          return idesc->operands[1] == IA64_OPND_IP;
+        }
+      else
+        abort ();
+      break;
+    case 'p':
+      if (ic->name[5] == 'r')
+        {
+          int i25 = plain_mov && idesc->operands[1] == IA64_OPND_PR;
+          int i23 = plain_mov && idesc->operands[0] == IA64_OPND_PR;
+          int i24 = plain_mov && idesc->operands[0] == IA64_OPND_PR_ROT;
+          if (i23)
+            return strstr (format, "I23") != NULL;
+          if (i24)
+            return strstr (format, "I24") != NULL;
+          if (i25)
+            return strstr (format, "I25") != NULL;
+        }
+      else if (ic->name[5] == 's')
+        {
+          int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_L;
+          int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR;
+          if (m35)
+            return strstr (format, "M35") != NULL;
+          if (m36)
+            return strstr (format, "M36") != NULL;
+        }
+      else
+        abort ();
+      break;
+    case 'u':
+      {
+        int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_UM;
+        int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR_UM;
+        if (m35)
+          return strstr (format, "M35") != NULL;
+        if (m36)
+          return strstr (format, "M36") != NULL;
+      }
+      break;
+    }
+  return 0;
+}
+
+
+/* is the given opcode in the given insn class? */
+static int
+in_iclass(struct ia64_opcode *idesc, struct iclass *ic, 
+          const char *format, const char *field, int *notep)
+{
+  int i;
+  int resolved = 0;
+
+  if (ic->comment)
+    {
+      if (!strncmp (ic->comment, "Format", 6))
+        {
+          /* assume that the first format seen is the most restrictive, and
+             only keep a later one if it looks like it's more restrictive. */
+          if (format)
+            {
+              if (strlen (ic->comment) < strlen (format))
+                {
+                  fprintf (stderr, "Warning: most recent format '%s'\n"
+                           "appears more restrictive than '%s'\n",
+                           ic->comment, format);
+                  format = ic->comment; 
+                }
+            }
+          else
+            format = ic->comment;
+        }
+      else if (!strncmp (ic->comment, "Field", 5))
+        {
+          if (field)
+            fprintf (stderr, "Overlapping field %s->%s\n",
+                     ic->comment, field);
+          field = ic->comment;
+        }
+    }
+
+  /* an insn class matches anything that is the same followed by completers,
+     except when the absence and presence of completers constitutes different
+     instructions */
+  if (ic->nsubs == 0 && ic->nxsubs == 0)
+    {
+      int is_mov = strncmp (idesc->name, "mov", 3) == 0;
+      int plain_mov = strcmp (idesc->name, "mov") == 0;
+      int len = strlen(ic->name);
+
+      resolved = ((strncmp (ic->name, idesc->name, len) == 0)
+                  && (idesc->name[len] == '\0' 
+                      || idesc->name[len] == '.'));
+
+      /* all break and nop variations must match exactly */
+      if (resolved &&
+          (strcmp (ic->name, "break") == 0
+           || strcmp (ic->name, "nop") == 0))
+        resolved = strcmp (ic->name, idesc->name) == 0;
+
+      /* assume restrictions in the FORMAT/FIELD negate resolution,
+         unless specifically allowed by clauses in this block */
+      if (resolved && field)
+        {
+          /* check Field(sf)==sN against opcode sN */
+          if (strstr(field, "(sf)==") != NULL)
+            {
+              char *sf;
+              if ((sf = strstr (idesc->name, ".s")) != 0)
+                {
+                  resolved = strcmp (sf + 1, strstr (field, "==") + 2) == 0;
+                }
+            }
+          /* check Field(lftype)==XXX */
+          else if (strstr (field, "(lftype)") != NULL)
+            {
+              if (strstr (idesc->name, "fault") != NULL)
+                resolved = strstr (field, "fault") != NULL;
+              else
+                resolved = strstr (field, "fault") == NULL;
+            }
+          /* handle Field(ctype)==XXX */
+          else if (strstr (field, "(ctype)") != NULL)
+            {
+              if (strstr (idesc->name, "or.andcm"))
+                resolved = strstr (field, "or.andcm") != NULL;
+              else if (strstr (idesc->name, "and.orcm"))
+                resolved = strstr (field, "and.orcm") != NULL;
+              else if (strstr (idesc->name, "orcm"))
+                resolved = strstr (field, "or orcm") != NULL;
+              else if (strstr (idesc->name, "or"))
+                resolved = strstr (field, "or orcm") != NULL;
+              else if (strstr (idesc->name, "andcm"))
+                resolved = strstr (field, "and andcm") != NULL;
+              else if (strstr (idesc->name, "and"))
+                resolved = strstr (field, "and andcm") != NULL;
+              else if (strstr (idesc->name, "unc"))
+                resolved = strstr (field, "unc") != NULL;
+              else
+                resolved = strcmp (field, "Field(ctype)==") == 0;
+            }
+        }
+      if (resolved && format)
+        {
+          if (strncmp (idesc->name, "dep", 3) == 0
+                   && strstr (format, "I13") != NULL)
+            resolved = idesc->operands[1] == IA64_OPND_IMM8;
+          else if (strncmp (idesc->name, "chk", 3) == 0
+                   && strstr (format, "M21") != NULL)
+            resolved = idesc->operands[0] == IA64_OPND_F2;
+          else if (strncmp (idesc->name, "lfetch", 6) == 0)
+            resolved = (strstr (format, "M14 M15") != NULL
+                        && (idesc->operands[1] == IA64_OPND_R2
+                            || idesc->operands[1] == IA64_OPND_IMM9b));
+          else if (strncmp (idesc->name, "br.call", 7) == 0
+                   && strstr (format, "B5") != NULL)
+            resolved = idesc->operands[1] == IA64_OPND_B2;
+          else if (strncmp (idesc->name, "br.call", 7) == 0
+                   && strstr (format, "B3") != NULL)
+            resolved = idesc->operands[1] == IA64_OPND_TGT25c;
+          else if (strncmp (idesc->name, "brp", 3) == 0
+                   && strstr (format, "B7") != NULL)
+            resolved = idesc->operands[0] == IA64_OPND_B2;
+          else if (strcmp (ic->name, "invala") == 0)
+            resolved = strcmp (idesc->name, ic->name) == 0;
+          else
+            resolved = 0;
+        }
+
+      /* misc brl variations ('.cond' is optional); 
+         plain brl matches brl.cond */
+      if (!resolved
+          && (strcmp (idesc->name, "brl") == 0
+              || strncmp (idesc->name, "brl.", 4) == 0)
+          && strcmp (ic->name, "brl.cond") == 0)
+        {
+          resolved = 1;
+        }
+
+      /* misc br variations ('.cond' is optional) */
+      if (!resolved 
+          && (strcmp (idesc->name, "br") == 0
+              || strncmp (idesc->name, "br.", 3) == 0)
+          && strcmp (ic->name, "br.cond") == 0)
+        {
+          if (format)
+            resolved = (strstr (format, "B4") != NULL
+                        && idesc->operands[0] == IA64_OPND_B2)
+              || (strstr (format, "B1") != NULL
+                  && idesc->operands[0] == IA64_OPND_TGT25c);
+          else
+            resolved = 1;
+        }
+
+      /* probe variations */
+      if (!resolved && strncmp (idesc->name, "probe", 5) == 0)
+        {
+          resolved = strcmp (ic->name, "probe") == 0 
+            && !((strstr (idesc->name, "fault") != NULL) 
+                 ^ (format && strstr (format, "M40") != NULL));
+        }
+      /* mov variations */
+      if (!resolved && is_mov)
+        {
+          if (plain_mov)
+            {
+              /* mov alias for fmerge */
+              if (strcmp (ic->name, "fmerge") == 0)
+                {
+                  resolved = idesc->operands[0] == IA64_OPND_F1
+                    && idesc->operands[1] == IA64_OPND_F3;
+                }
+              /* mov alias for adds (r3 or imm14) */
+              else if (strcmp (ic->name, "adds") == 0)
+                {
+                  resolved = (idesc->operands[0] == IA64_OPND_R1
+                              && (idesc->operands[1] == IA64_OPND_R3
+                                  || (idesc->operands[1] == IA64_OPND_IMM14)));
+                }
+              /* mov alias for addl */
+              else if (strcmp (ic->name, "addl") == 0)
+                {
+                  resolved = idesc->operands[0] == IA64_OPND_R1
+                    && idesc->operands[1] == IA64_OPND_IMM22;
+                }
+            }
+          /* some variants of mov and mov.[im] */
+          if (!resolved && strncmp (ic->name, "mov_", 4) == 0)
+            {
+              resolved = in_iclass_mov_x (idesc, ic, format, field);
+            }
+        }
+
+      /* keep track of this so we can flag any insn classes which aren't 
+         mapped onto at least one real insn */
+      if (resolved)
+        {
+          ic->terminal_resolved = 1;
+        }
+    }
+  else for (i=0;i < ic->nsubs;i++)
+    {
+      if (in_iclass(idesc, ics[ic->subs[i]], format, field, notep))
+        {
+          int j;
+          for (j=0;j < ic->nxsubs;j++)
+            {
+              if (in_iclass(idesc, ics[ic->xsubs[j]], NULL, NULL, NULL))
+                return 0;
+            }
+          if (debug > 1)
+            printf ("%s is in IC %s\n",
+                    idesc->name, ic->name);
+          resolved = 1;
+          break;
+        }
+    }
+  
+  /* If it's in this IC, add the IC note (if any) to the insn */
+  if (resolved)
+    {
+      if (ic->note && notep)
+        {
+          if (*notep && *notep != ic->note)
+            {
+              fprintf (stderr, "Warning: overwriting note %d with note %d"
+                       "(IC:%s)\n",
+                       *notep, ic->note, ic->name);
+            }
+          *notep = ic->note;
+        }
+    }
+
+  return resolved;
+}
+
+
+static int
+lookup_regindex (const char *name, int specifier)
+{
+  switch (specifier)
+    {
+    case IA64_RS_ARX:
+      if (strstr (name, "[RSC]"))
+        return 16;
+      if (strstr (name, "[BSP]"))
+        return 17;
+      else if (strstr (name, "[BSPSTORE]"))
+        return 18;
+      else if (strstr (name, "[RNAT]"))
+        return 19;
+      else if (strstr (name, "[CCV]"))
+        return 32;
+      else if (strstr (name, "[ITC]"))
+        return 44;
+      else if (strstr (name, "[PFS]"))
+        return 64;
+      else if (strstr (name, "[LC]"))
+        return 65;
+      else if (strstr (name, "[EC]"))
+        return 66;
+      abort ();
+    case IA64_RS_CRX:
+      if (strstr (name, "[DCR]"))
+        return 0;
+      else if (strstr (name, "[ITM]"))
+        return 1;
+      else if (strstr (name, "[IVA]"))
+        return 2;
+      else if (strstr (name, "[PTA]"))
+        return 8;
+      else if (strstr (name, "[GPTA]"))
+        return 9;
+      else if (strstr (name, "[IPSR]"))
+        return 16;
+      else if (strstr (name, "[ISR]"))
+        return 17;
+      else if (strstr (name, "[IIP]"))
+        return 19;
+      else if (strstr (name, "[IFA]"))
+        return 20;
+      else if (strstr (name, "[ITIR]"))
+        return 21;
+      else if (strstr (name, "[IIPA]"))
+        return 22;
+      else if (strstr (name, "[IFS]"))
+        return 23;
+      else if (strstr (name, "[IIM]"))
+        return 24;
+      else if (strstr (name, "[IHA]"))
+        return 25;
+      else if (strstr (name, "[LID]"))
+        return 64;
+      else if (strstr (name, "[IVR]"))
+        return 65;
+      else if (strstr (name, "[TPR]"))
+        return 66;
+      else if (strstr (name, "[EOI]"))
+        return 67;
+      else if (strstr (name, "[ITV]"))
+        return 72;
+      else if (strstr (name, "[PMV]"))
+        return 73;
+      else if (strstr (name, "[CMCV]"))
+        return 74;
+      abort ();
+    case IA64_RS_PSR:
+      if (strstr (name, ".be"))
+        return 1;
+      else if (strstr (name, ".up"))
+        return 2;
+      else if (strstr (name, ".ac"))
+        return 3;
+      else if (strstr (name, ".mfl"))
+        return 4;
+      else if (strstr (name, ".mfh"))
+        return 5;
+      else if (strstr (name, ".ic"))
+        return 13;
+      else if (strstr (name, ".i"))
+        return 14;
+      else if (strstr (name, ".pk"))
+        return 15;
+      else if (strstr (name, ".dt"))
+        return 17;
+      else if (strstr (name, ".dfl"))
+        return 18;
+      else if (strstr (name, ".dfh"))
+        return 19;
+      else if (strstr (name, ".sp"))
+        return 20;
+      else if (strstr (name, ".pp"))
+        return 21;
+      else if (strstr (name, ".di"))
+        return 22;
+      else if (strstr (name, ".si"))
+        return 23;
+      else if (strstr (name, ".db"))
+        return 24;
+      else if (strstr (name, ".lp"))
+        return 25;
+      else if (strstr (name, ".tb"))
+        return 26;
+      else if (strstr (name, ".rt"))
+        return 27;
+      else if (strstr (name, ".cpl"))
+        return 32;
+      else if (strstr (name, ".rs"))
+        return 34;
+      else if (strstr (name, ".mc"))
+        return 35;
+      else if (strstr (name, ".it"))
+        return 36;
+      else if (strstr (name, ".id"))
+        return 37;
+      else if (strstr (name, ".da"))
+        return 38;
+      else if (strstr (name, ".dd"))
+        return 39;
+      else if (strstr (name, ".ss"))
+        return 40;
+      else if (strstr (name, ".ri"))
+        return 41;
+      else if (strstr (name, ".ed"))
+        return 43;
+      else if (strstr (name, ".bn"))
+        return 44;
+      else if (strstr (name, ".ia"))
+        return 45;
+      else
+        abort ();
+    default:
+      break;
+    }
+  return REG_NONE;
+}
+
+static int
+lookup_specifier (const char *name)
+{
+  if (strchr (name, '%'))
+    {
+      if (strstr (name, "AR[K%]") != NULL)
+        return IA64_RS_AR_K;
+      if (strstr (name, "AR[UNAT]") != NULL)
+        return IA64_RS_AR_UNAT;
+      if (strstr (name, "AR%, % in 8") != NULL)
+        return IA64_RS_AR;
+      if (strstr (name, "AR%, % in 48") != NULL)
+        return IA64_RS_ARb;
+      if (strstr (name, "BR%") != NULL)
+        return IA64_RS_BR;
+      if (strstr (name, "CR[IRR%]") != NULL)
+        return IA64_RS_CR_IRR;
+      if (strstr (name, "CR[LRR%]") != NULL)
+        return IA64_RS_CR_LRR;
+      if (strstr (name, "CR%") != NULL)
+        return IA64_RS_CR;
+      if (strstr (name, "FR%, % in 0") != NULL)
+        return IA64_RS_FR;
+      if (strstr (name, "FR%, % in 2") != NULL)
+        return IA64_RS_FRb;
+      if (strstr (name, "GR%") != NULL)
+        return IA64_RS_GR;
+      if (strstr (name, "PR%") != NULL)
+        return IA64_RS_PR;
+
+      fprintf (stderr, "Warning! Don't know how to specify %% dependency %s\n",
+               name);
+    }
+  else if (strchr (name, '#'))
+    {
+      if (strstr (name, "CPUID#") != NULL)
+        return IA64_RS_CPUID;
+      if (strstr (name, "DBR#") != NULL)
+        return IA64_RS_DBR;
+      if (strstr (name, "IBR#") != NULL)
+        return IA64_RS_IBR;
+      if (strstr (name, "MSR#") != NULL)
+	return IA64_RS_MSR;
+      if (strstr (name, "PKR#") != NULL)
+        return IA64_RS_PKR;
+      if (strstr (name, "PMC#") != NULL)
+        return IA64_RS_PMC;
+      if (strstr (name, "PMD#") != NULL)
+        return IA64_RS_PMD;
+      if (strstr (name, "RR#") != NULL)
+        return IA64_RS_RR;
+      
+      fprintf (stderr, "Warning! Don't know how to specify # dependency %s\n",
+               name);
+    }
+  else if (strncmp (name, "AR[FPSR]", 8) == 0)
+    return IA64_RS_AR_FPSR;
+  else if (strncmp (name, "AR[", 3) == 0)
+    return IA64_RS_ARX;
+  else if (strncmp (name, "CR[", 3) == 0)
+    return IA64_RS_CRX;
+  else if (strncmp (name, "PSR.", 4) == 0)
+    return IA64_RS_PSR;
+  else if (strcmp (name, "InService*") == 0)
+    return IA64_RS_INSERVICE;
+  else if (strcmp (name, "GR0") == 0)
+    return IA64_RS_GR0;
+  else if (strcmp (name, "CFM") == 0)
+    return IA64_RS_CFM;
+  else if (strcmp (name, "PR63") == 0)
+    return IA64_RS_PR63;
+  else if (strcmp (name, "RSE") == 0)
+    return IA64_RS_RSE;
+
+  return IA64_RS_ANY;
+}
+
+void
+print_dependency_table ()
+{
+  int i, j;
+
+  if (debug) 
+    {
+      for (i=0;i < iclen;i++)
+        {
+          if (ics[i]->is_class)
+            {
+              if (!ics[i]->nsubs)
+                {
+                  fprintf (stderr, "Warning: IC:%s", ics[i]->name);
+                  if (ics[i]->comment)
+                    fprintf (stderr, "[%s]", ics[i]->comment);
+                  fprintf (stderr, " has no terminals or sub-classes\n");
+                }
+            }
+          else 
+            {
+              if (!ics[i]->terminal_resolved && !ics[i]->orphan)
+                {
+                  fprintf(stderr, "Warning: no insns mapped directly to "
+                          "terminal IC %s", ics[i]->name);
+                  if (ics[i]->comment)
+                    fprintf(stderr, "[%s] ", ics[i]->comment);
+                  fprintf(stderr, "\n");
+                }
+            }
+        }
+
+      for (i=0;i < iclen;i++)
+        {
+          if (ics[i]->orphan)
+            {
+              mark_used (ics[i], 1);
+              fprintf (stderr, "Warning: class %s is defined but not used\n", 
+                       ics[i]->name);
+            }
+        }
+
+      if (debug > 1) for (i=0;i < rdepslen;i++)
+        {  
+          static const char *mode_str[] = { "RAW", "WAW", "WAR" };
+          if (rdeps[i]->total_chks == 0)
+            {
+              fprintf (stderr, "Warning: rsrc %s (%s) has no chks%s\n", 
+                       rdeps[i]->name, mode_str[rdeps[i]->mode],
+                       rdeps[i]->total_regs ? "" : " or regs");
+            }
+          else if (rdeps[i]->total_regs == 0)
+            {
+              fprintf (stderr, "Warning: rsrc %s (%s) has no regs\n", 
+                       rdeps[i]->name, mode_str[rdeps[i]->mode]);
+            }
+        }
+    }
+
+  /* the dependencies themselves */
+  printf ("static const struct ia64_dependency\ndependencies[] = {\n");
+  for (i=0;i < rdepslen;i++)
+    {
+      /* '%', '#', AR[], CR[], or PSR. indicates we need to specify the actual
+         resource used */ 
+      int specifier = lookup_specifier (rdeps[i]->name);
+      int regindex = lookup_regindex (rdeps[i]->name, specifier);
+
+      printf ("  { \"%s\", %d, %d, %d, %d, ",
+              rdeps[i]->name, specifier,
+              (int)rdeps[i]->mode, (int)rdeps[i]->semantics, regindex);
+      if (rdeps[i]->semantics == IA64_DVS_OTHER)
+        printf ("\"%s\", ", rdeps[i]->extra);
+      printf("},\n");
+    }
+  printf ("};\n\n");
+
+  /* and dependency lists */
+  for (i=0;i < dlistlen;i++)
+    {
+      int len = 2;
+      printf ("static const short dep%d[] = {\n  ", i);
+      for (j=0;j < dlists[i]->len; j++)
+        {
+          len += printf ("%d, ", dlists[i]->deps[j]);
+          if (len > 75)
+            {
+              printf("\n  ");
+              len = 2;
+            }
+        }
+      printf ("\n};\n\n");
+    }
+
+  /* and opcode dependency list */
+  printf ("#define NELS(X) (sizeof(X)/sizeof(X[0]))\n");
+  printf ("static const struct ia64_opcode_dependency\n");
+  printf ("op_dependencies[] = {\n");
+  for (i=0;i < opdeplen;i++)
+    {
+      printf ("  { ");
+      if (opdeps[i]->chk == -1)
+        printf ("0, NULL, ");
+      else 
+        printf ("NELS(dep%d), dep%d, ", opdeps[i]->chk, opdeps[i]->chk);
+      if (opdeps[i]->reg == -1)
+        printf ("0, NULL, ");
+      else 
+        printf ("NELS(dep%d), dep%d, ", opdeps[i]->reg, opdeps[i]->reg);
+      printf ("},\n");
+    }
+  printf ("};\n\n");
+}
+
+
+/* Add STR to the string table. */
+
+static struct string_entry *
+insert_string (str)
+     char *str;
+{
+  int start = 0, end = strtablen;
+  int i, x;
+
+  if (strtablen == strtabtotlen)
+    {
+      strtabtotlen += 20;
+      string_table = (struct string_entry **)
+	xrealloc (string_table, 
+		  sizeof (struct string_entry **) * strtabtotlen);
+    }
+
+  if (strtablen == 0)
+    {
+      strtablen = 1;
+      string_table[0] = tmalloc (struct string_entry);
+      string_table[0]->s = xstrdup (str);
+      string_table[0]->num = 0;
+      return string_table[0];
+    }
+
+  if (strcmp (str, string_table[strtablen - 1]->s) > 0)
+    {
+      i = end;
+    }
+  else if (strcmp (str, string_table[0]->s) < 0)
+    {
+      i = 0;
+    }
+  else
+    {
+      while (1)
+	{
+	  int c;
+
+	  i = (start + end) / 2;
+	  c = strcmp (str, string_table[i]->s);
+	  if (c < 0)
+	    {
+	      end = i - 1;
+	    }
+	  else if (c == 0)
+	    {
+	      return string_table[i];
+	    }
+	  else
+	    {
+	      start = i + 1;
+	    }
+	  if (start > end)
+	    {
+	      break;
+	    }
+	}
+    }
+  for (; i > 0 && i < strtablen; i--)
+    {
+      if (strcmp (str, string_table[i - 1]->s) > 0)
+	{
+	  break;
+	}
+    }
+  for (; i < strtablen; i++)
+    {
+      if (strcmp (str, string_table[i]->s) < 0)
+	{
+	  break;
+	}
+    }
+  for (x = strtablen - 1; x >= i; x--)
+    {
+      string_table[x + 1] = string_table[x];
+      string_table[x + 1]->num = x + 1;
+    }
+  string_table[i] = tmalloc (struct string_entry);
+  string_table[i]->s = xstrdup (str);
+  string_table[i]->num = i;
+  strtablen++;
+  return string_table[i];
+}
+
+struct bittree *
+make_bittree_entry ()
+{
+  struct bittree *res = tmalloc (struct bittree);
+
+  res->disent = NULL;
+  res->bits[0] = NULL;
+  res->bits[1] = NULL;
+  res->bits[2] = NULL;
+  res->skip_flag = 0;
+  res->bits_to_skip = 0;
+  return res;
+}
+
+struct disent *
+add_dis_table_ent (which, insn, completer_index)
+     struct disent *which;
+     int insn;
+     int completer_index;
+{
+  int ci = 0;
+  struct disent *ent;
+
+  if (which != NULL)
+    {
+      ent = which;
+
+      ent->nextcnt++;
+      while (ent->nexte != NULL)
+	{
+	  ent = ent->nexte;
+	}
+      ent = (ent->nexte = tmalloc (struct disent));
+    }
+  else
+    {
+      ent = tmalloc (struct disent);
+      ent->next_ent = disinsntable;
+      disinsntable = ent;
+      which = ent;
+    }
+  ent->nextcnt = 0;
+  ent->nexte = NULL;
+  ent->insn = insn;
+  while (completer_index != 1)
+    {
+      ci = (ci << 1) | (completer_index & 1);
+      completer_index >>= 1;
+    }
+  ent->completer_index = ci;
+  return which;
+}
+
+void
+finish_distable ()
+{
+  struct disent *ent = disinsntable;
+  struct disent *prev = ent;
+
+  ent->ournum = 32768;
+  while ((ent = ent->next_ent) != NULL)
+    {
+      ent->ournum = prev->ournum + prev->nextcnt + 1;
+      prev = ent;
+    }
+}
+
+void
+insert_bit_table_ent (curr_ent, bit, opcode, mask, opcodenum, completer_index)
+     struct bittree *curr_ent;
+     int bit;
+     ia64_insn opcode; 
+     ia64_insn mask;
+     int opcodenum;
+     int completer_index;
+{
+  ia64_insn m;
+  int b;
+  struct bittree *next;
+
+  if (bit == -1)
+    {
+      struct disent *nent = add_dis_table_ent (curr_ent->disent, opcodenum,
+					       completer_index);
+      curr_ent->disent = nent;
+      return;
+    }
+
+  m = ((ia64_insn) 1) << bit;
+
+  if (mask & m)
+    {
+      b = (opcode & m) ? 1 : 0;
+    }
+  else
+    {
+      b = 2;
+    }
+  next = curr_ent->bits[b];
+  if (next == NULL)
+    {
+      next = make_bittree_entry ();
+      curr_ent->bits[b] = next;
+    }
+  insert_bit_table_ent (next, bit - 1, opcode, mask, opcodenum,
+			completer_index);
+}
+
+void
+add_dis_entry (first, opcode, mask, opcodenum, ent, completer_index)
+     int first;
+     ia64_insn opcode;
+     ia64_insn mask;
+     int opcodenum;
+     struct completer_entry *ent;
+     int completer_index;
+{
+  if (completer_index & (1 << 20))
+    {
+      abort ();
+    }
+  while (ent != NULL)
+    {
+      ia64_insn newopcode = (opcode & (~ ent->mask)) | ent->bits;
+      add_dis_entry (first, newopcode, mask, opcodenum, ent->addl_entries,
+		     (completer_index << 1) | 1);
+      if (ent->is_terminal)
+	{
+	  insert_bit_table_ent (bittree, 40, newopcode, mask, opcodenum, 
+				(completer_index << 1) | 1);
+	}
+      completer_index <<= 1;
+      ent = ent->alternative;
+    }
+}
+
+/* This optimization pass combines multiple "don't care" nodes. */
+void
+compact_distree (ent)
+     struct bittree *ent;
+{
+#define IS_SKIP(ent) \
+    ((ent->bits[2] !=NULL) \
+     && (ent->bits[0] == NULL && ent->bits[1] == NULL && ent->skip_flag == 0))
+
+  int bitcnt = 0;
+  struct bittree *nent = ent;
+  int x;
+
+  while (IS_SKIP (nent))
+    {
+      bitcnt++;
+      nent = nent->bits[2];
+    }
+
+  if (bitcnt)
+    {
+      struct bittree *next = ent->bits[2];
+
+      ent->bits[0] = nent->bits[0];
+      ent->bits[1] = nent->bits[1];
+      ent->bits[2] = nent->bits[2];
+      ent->disent = nent->disent;
+      ent->skip_flag = 1;
+      ent->bits_to_skip = bitcnt;
+      while (next != nent)
+	{
+	  struct bittree *b = next;
+	  next = next->bits[2];
+	  free (b);
+	}
+      free (nent);
+    }
+
+  for (x = 0; x < 3; x++)
+    {
+      struct bittree *i = ent->bits[x];
+      if (i != NULL)
+	{
+	  compact_distree (i);
+	}
+    }
+}
+
+static unsigned char *insn_list;
+static int insn_list_len = 0;
+static int tot_insn_list_len = 0;
+
+/* Generate the disassembler state machine corresponding to the tree
+   in ENT.  */
+void
+gen_dis_table (ent)
+     struct bittree *ent;
+{
+  int x;
+  int our_offset = insn_list_len;
+  int bitsused = 5;
+  int totbits = bitsused;
+  int needed_bytes;
+  int zero_count = 0;
+  int zero_dest = 0;	/* initialize this with 0 to keep gcc quiet... */
+
+  /* If this is a terminal entry, there's no point in skipping any
+     bits. */
+  if (ent->skip_flag && ent->bits[0] == NULL && ent->bits[1] == NULL &&
+      ent->bits[2] == NULL)
+    {
+      if (ent->disent == NULL)
+	{
+	  abort ();
+	}
+      else
+	{
+	  ent->skip_flag = 0;
+	}
+    }
+
+  /* Calculate the amount of space needed for this entry, or at least
+     a conservatively large approximation. */
+  if (ent->skip_flag)
+    {
+      totbits += 5;
+    }
+  for (x = 1; x < 3; x++)
+    {
+      if (ent->bits[x] != NULL)
+	{
+	  totbits += 16;
+	}
+    }
+
+  if (ent->disent != NULL)
+    {
+      if (ent->bits[2] != NULL)
+	{
+	  abort ();
+	}
+      totbits += 16;
+    }
+
+  /* Now allocate the space. */
+  needed_bytes = (totbits + 7) / 8;
+  if ((needed_bytes + insn_list_len) > tot_insn_list_len)
+    {
+      tot_insn_list_len += 256;
+      insn_list = (char *) xrealloc (insn_list, tot_insn_list_len);
+    }
+  our_offset = insn_list_len;
+  insn_list_len += needed_bytes;
+  memset (insn_list + our_offset, 0, needed_bytes);
+
+  /* Encode the skip entry by setting bit 6 set in the state op field,
+     and store the # of bits to skip immediately after. */
+  if (ent->skip_flag)
+    {
+      bitsused += 5;
+      insn_list[our_offset + 0] |= 0x40 | ((ent->bits_to_skip >> 2) & 0xf);
+      insn_list[our_offset + 1] |= ((ent->bits_to_skip & 3) << 6);
+    }
+
+#define IS_ONLY_IFZERO(ENT) \
+  ((ENT)->bits[0] != NULL && (ENT)->bits[1] == NULL && (ENT)->bits[2] == NULL \
+   && (ENT)->disent == NULL && (ENT)->skip_flag == 0)
+
+  /* Store an "if (bit is zero)" instruction by setting bit 7 in the
+     state op field. */
+
+  if (ent->bits[0] != NULL)
+    {
+      struct bittree *nent = ent->bits[0];
+      zero_count = 0;
+
+      insn_list[our_offset] |= 0x80;
+
+      /* We can encode sequences of multiple "if (bit is zero)" tests
+	 by storing the # of zero bits to check in the lower 3 bits of
+	 the instruction.  However, this only applies if the state
+	 solely tests for a zero bit.  */
+
+      if (IS_ONLY_IFZERO (ent))
+	{
+	  while (IS_ONLY_IFZERO (nent) && zero_count < 7)
+	    {
+	      nent = nent->bits[0];
+	      zero_count++;
+	    }
+
+	  insn_list[our_offset + 0] |= zero_count;
+	}
+      zero_dest = insn_list_len;
+      gen_dis_table (nent);
+    }
+
+  /* Now store the remaining tests.  We also handle a sole "termination
+     entry" by storing it as an "any bit" test.  */
+
+  for (x = 1; x < 3; x++)
+    {
+      if (ent->bits[x] != NULL || (x == 2 && ent->disent != NULL))
+	{
+	  struct bittree *i = ent->bits[x];
+	  int idest;
+	  int currbits = 15;
+
+	  if (i != NULL)
+	    {
+	      /* If the instruction being branched to only consists of
+		 a termination entry, use the termination entry as the
+		 place to branch to instead.  */
+	      if (i->bits[0] == NULL && i->bits[1] == NULL
+		  && i->bits[2] == NULL && i->disent != NULL)
+		{
+		  idest = i->disent->ournum;
+		  i = NULL;
+		}
+	      else
+		{
+		  idest = insn_list_len - our_offset;
+		}
+	    }
+	  else
+	    {
+	      idest = ent->disent->ournum;
+	    }
+
+	  /* If the destination offset for the if (bit is 1) test is less 
+	     than 256 bytes away, we can store it as 8-bits instead of 16;
+	     the instruction has bit 5 set for the 16-bit address, and bit
+	     4 for the 8-bit address.  Since we've already allocated 16
+	     bits for the address we need to deallocate the space.
+
+	     Note that branchings within the table are relative, and
+	     there are no branches that branch past our instruction yet
+	     so we do not need to adjust any other offsets. */
+
+	  if (x == 1)
+	    {
+	      if (idest <= 256)
+		{
+		  int start = our_offset + bitsused / 8 + 1;
+
+		  memmove (insn_list + start,
+			   insn_list + start + 1,
+			   insn_list_len - (start + 1));
+		  currbits = 7;
+		  totbits -= 8;
+		  needed_bytes--;
+		  insn_list_len--;
+		  insn_list[our_offset] |= 0x10;
+		  idest--;
+		}
+	      else
+		{
+		  insn_list[our_offset] |= 0x20;
+		}
+	    }
+	  else
+	    {
+	      /* An instruction which solely consists of a termination
+		 marker and whose disassembly name index is < 4096
+		 can be stored in 16 bits.  The encoding is slightly
+		 odd; the upper 4 bits of the instruction are 0x3, and
+		 bit 3 loses its normal meaning.  */
+
+	      if (ent->bits[0] == NULL && ent->bits[1] == NULL
+		  && ent->bits[2] == NULL && ent->skip_flag == 0
+		  && ent->disent != NULL
+		  && ent->disent->ournum < (32768 + 4096))
+		{
+		  int start = our_offset + bitsused / 8 + 1;
+
+		  memmove (insn_list + start,
+			   insn_list + start + 1,
+			   insn_list_len - (start + 1));
+		  currbits = 11;
+		  totbits -= 5;
+		  bitsused--;
+		  needed_bytes--;
+		  insn_list_len--;
+		  insn_list[our_offset] |= 0x30;
+		  idest &= ~32768;
+		}
+	      else
+		{
+		  insn_list[our_offset] |= 0x08;
+		}
+	    }
+	  if (debug)
+	    {
+	      int id = idest;
+
+	      if (i == NULL)
+		{
+		  id |= 32768;
+		}
+	      else if (! (id & 32768))
+		{
+		  id += our_offset;
+		}
+	      if (x == 1)
+		{
+		  printf ("%d: if (1) goto %d\n", our_offset, id);
+		}
+	      else
+		{
+		  printf ("%d: try %d\n", our_offset, id);
+		}
+	    }
+
+	  /* Store the address of the entry being branched to. */
+	  while (currbits >= 0)
+	    {
+	      char *byte = insn_list + our_offset + bitsused / 8;
+
+	      if (idest & (1 << currbits))
+		{
+		  *byte |= (1 << (7 - (bitsused % 8)));
+		}
+	      bitsused++;
+	      currbits--;
+	    }
+
+	  /* Now generate the states for the entry being branched to. */
+	  if (i != NULL)
+	    {
+	      gen_dis_table (i);
+	    }
+
+	}
+    }
+  if (debug)
+    {
+      if (ent->skip_flag)
+	{
+	  printf ("%d: skipping %d\n", our_offset, ent->bits_to_skip);
+	}
+  
+      if (ent->bits[0] != NULL)
+	{
+	  printf ("%d: if (0:%d) goto %d\n", our_offset, zero_count + 1,
+		  zero_dest);
+	}
+    }
+  if (bitsused != totbits)
+    {
+      abort ();
+    }
+}
+
+void
+print_dis_table ()
+{
+  int x;
+  struct disent *cent = disinsntable;
+
+  printf ("static const char dis_table[] = {\n");
+  for (x = 0; x < insn_list_len; x++)
+    {
+      if ((x > 0) && ((x % 12) == 0))
+	{
+	  printf ("\n");
+	}
+      printf ("0x%02x, ", insn_list[x]);
+    }
+  printf ("\n};\n\n");
+
+  printf ("static const struct ia64_dis_names ia64_dis_names[] = {\n");
+  while (cent != NULL)
+    {
+      struct disent *ent = cent;
+
+      while (ent != NULL)
+	{
+	  printf ("{ 0x%x, %d, %d },\n", ent->completer_index,
+		  ent->insn,
+		  (ent->nexte != NULL ? 1 : 0));
+	  ent = ent->nexte;
+	}
+      cent = cent->next_ent;
+    }
+  printf ("};\n\n");
+}
+
+void
+generate_disassembler ()
+{
+  int mainnum = 0;
+  struct main_entry *ptr = maintable;
+
+  bittree = make_bittree_entry ();
+
+  while (ptr != NULL)
+    {
+      if (ptr->opcode->type != IA64_TYPE_DYN)
+	{
+	  add_dis_entry (bittree,
+			 ptr->opcode->opcode, ptr->opcode->mask, mainnum,
+			 ptr->completers, 1);
+	}
+      mainnum++;
+      ptr = ptr->next;
+    }
+
+  compact_distree (bittree);
+  finish_distable ();
+  gen_dis_table (bittree);
+
+  print_dis_table ();
+}
+
+void
+print_string_table ()
+{
+  int x;
+  char lbuf[80], buf[80];
+  int blen = 0;
+
+  printf ("static const char *ia64_strings[] = {\n");
+  lbuf[0] = '\0';
+  for (x = 0; x < strtablen; x++)
+    {
+      int len;
+      
+      if (strlen (string_table[x]->s) > 75)
+	{
+	  abort ();
+	}
+      sprintf (buf, " \"%s\",", string_table[x]->s);
+      len = strlen (buf);
+      if ((blen + len) > 75)
+	{
+	  printf (" %s\n", lbuf);
+	  lbuf[0] = '\0';
+	  blen = 0;
+	}
+      strcat (lbuf, buf);
+      blen += len;
+    }
+  if (blen > 0)
+    {
+      printf (" %s\n", lbuf);
+    }
+  printf ("};\n\n");
+}
+
+static struct completer_entry **glist;
+static int glistlen = 0;
+static int glisttotlen = 0;
+
+/* If the completer trees ENT1 and ENT2 are equal, return 1. */
+
+int
+completer_entries_eq (ent1, ent2)
+     struct completer_entry *ent1, *ent2;
+{
+  while (ent1 != NULL && ent2 != NULL)
+    {
+      if (ent1->name->num != ent2->name->num
+	  || ent1->bits != ent2->bits
+	  || ent1->mask != ent2->mask
+	  || ent1->is_terminal != ent2->is_terminal
+          || ent1->dependencies != ent2->dependencies)
+	{
+	  return 0;
+	}
+      if (! completer_entries_eq (ent1->addl_entries, ent2->addl_entries))
+	{
+	  return 0;
+	}
+      ent1 = ent1->alternative;
+      ent2 = ent2->alternative;
+    }
+  return ent1 == ent2;
+}
+
+/* Insert ENT into the global list of completers and return it.  If an
+   equivalent entry (according to completer_entries_eq) already exists,
+   it is returned instead. */
+struct completer_entry *
+insert_gclist (ent)
+     struct completer_entry *ent;
+{
+  if (ent != NULL)
+    {
+      int i;
+      int x;
+      int start = 0, end;
+
+      ent->addl_entries = insert_gclist (ent->addl_entries);
+      ent->alternative = insert_gclist (ent->alternative);
+
+      i = glistlen / 2;
+      end = glistlen;
+
+      if (glisttotlen == glistlen)
+	{
+	  glisttotlen += 20;
+	  glist = (struct completer_entry **)
+	    xrealloc (glist, sizeof (struct completer_entry *) * glisttotlen);
+	}
+
+      if (glistlen == 0)
+	{
+	  glist[0] = ent;
+	  glistlen = 1;
+	  return ent;
+	}
+
+      if (ent->name->num < glist[0]->name->num)
+	{
+	  i = 0;
+	}
+      else if (ent->name->num > glist[end - 1]->name->num)
+	{
+	  i = end;
+	}
+      else
+	{
+	  int c;
+
+	  while (1)
+	    {
+	      i = (start + end) / 2;
+	      c = ent->name->num - glist[i]->name->num;
+	      if (c < 0)
+		{
+		  end = i - 1;
+		}
+	      else if (c == 0)
+		{
+		  while (i > 0 
+			 && ent->name->num == glist[i - 1]->name->num)
+		    {
+		      i--;
+		    }
+		  break;
+		}
+	      else
+		{
+		  start = i + 1;
+		}
+	      if (start > end)
+		{
+		  break;
+		}
+	    }
+	  if (c == 0)
+	    {
+	      while (i < glistlen)
+		{
+		  if (ent->name->num != glist[i]->name->num)
+		    {
+		      break;
+		    }
+		  if (completer_entries_eq (ent, glist[i]))
+		    {
+		      return glist[i];
+		    }
+		  i++;
+		}
+	    }
+	}
+      for (; i > 0 && i < glistlen; i--)
+	{
+	  if (ent->name->num >= glist[i - 1]->name->num)
+	    {
+	      break;
+	    }
+	}
+      for (; i < glistlen; i++)
+	{
+	  if (ent->name->num < glist[i]->name->num)
+	    {
+	      break;
+	    }
+	}
+      for (x = glistlen - 1; x >= i; x--)
+	{
+	  glist[x + 1] = glist[x];
+	}
+      glist[i] = ent;
+      glistlen++;
+    }
+  return ent;
+}
+
+static int
+get_prefix_len (name)
+     const char *name;
+{
+  char *c;
+
+  if (name[0] == '\0')
+    {
+      return 0;
+    }
+
+  c = strchr (name, '.');
+  if (c != NULL)
+    {
+      return c - name;
+    }
+  else
+    {
+      return strlen (name);
+    }
+}
+
+static void
+compute_completer_bits (ment, ent)
+     struct main_entry *ment;
+     struct completer_entry *ent;
+{
+  while (ent != NULL)
+    {
+      compute_completer_bits (ment, ent->addl_entries);
+
+      if (ent->is_terminal)
+	{
+	  ia64_insn mask = 0;
+	  ia64_insn our_bits = ent->bits;
+	  struct completer_entry *p = ent->parent;
+	  ia64_insn p_bits;
+	  int x;
+
+	  while (p != NULL && ! p->is_terminal)
+	    {
+	      p = p->parent;
+	    }
+      
+	  if (p != NULL)
+	    {
+	      p_bits = p->bits;
+	    }
+	  else
+	    {
+	      p_bits = ment->opcode->opcode;
+	    }
+
+	  for (x = 0; x < 64; x++)
+	    {
+	      ia64_insn m = ((ia64_insn) 1) << x;
+	      if ((p_bits & m) != (our_bits & m))
+		{
+		  mask |= m;
+		}
+	      else
+		{
+		  our_bits &= ~m;
+		}
+	    }
+	  ent->bits = our_bits;
+	  ent->mask = mask;
+	}
+      else
+	{
+	  ent->bits = 0;
+	  ent->mask = 0;
+	}
+
+      ent = ent->alternative;
+    }
+}
+
+/* Find identical completer trees that are used in different
+   instructions and collapse their entries. */
+void
+collapse_redundant_completers ()
+{
+  struct main_entry *ptr;
+  int x;
+
+  for (ptr = maintable; ptr != NULL; ptr = ptr->next)
+    {
+      if (ptr->completers == NULL)
+	{
+	  abort ();
+	}
+      compute_completer_bits (ptr, ptr->completers);
+      ptr->completers = insert_gclist (ptr->completers);
+    }
+
+  /* The table has been finalized, now number the indexes.  */
+  for (x = 0; x < glistlen; x++)
+    {
+      glist[x]->num = x;
+    }
+}
+
+
+/* attach two lists of dependencies to each opcode.
+   1) all resources which, when already marked in use, conflict with this
+   opcode (chks) 
+   2) all resources which must be marked in use when this opcode is used
+   (regs) 
+*/
+int
+insert_opcode_dependencies (opc, cmp)
+     struct ia64_opcode *opc;
+     struct completer_entry *cmp;
+{
+  /* note all resources which point to this opcode.  rfi has the most chks
+     (79) and cmpxchng has the most regs (54) so 100 here should be enough */
+  int i;
+  int nregs = 0;
+  unsigned short regs[256];                  
+  int nchks = 0;
+  unsigned short chks[256];
+  /* flag insns for which no class matched; there should be none */
+  int no_class_found = 1;
+
+  for (i=0;i < rdepslen;i++)
+    {
+      struct rdep *rs = rdeps[i];
+      int j;
+
+      if (strcmp (opc->name, "cmp.eq.and") == 0
+          && strncmp (rs->name, "PR%", 3) == 0
+          && rs->mode == 1)
+        no_class_found = 99;
+
+      for (j=0; j < rs->nregs;j++)
+        {
+          int ic_note = 0;
+
+          if (in_iclass (opc, ics[rs->regs[j]], NULL, NULL, &ic_note))
+            {
+              /* We can ignore ic_note 11 for non PR resources */
+              if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0)
+                ic_note = 0;
+
+              if (ic_note != 0 && rs->regnotes[j] != 0
+                  && ic_note != rs->regnotes[j]
+                  && !(ic_note == 11 && rs->regnotes[j] == 1))
+                fprintf (stderr, "Warning: IC note %d in opcode %s (IC:%s)"
+                         " conflicts with resource %s note %d\n", 
+                         ic_note, opc->name, ics[rs->regs[j]]->name,
+                         rs->name, rs->regnotes[j]);
+              /* Instruction class notes override resource notes.
+                 So far, only note 11 applies to an IC instead of a resource,
+                 and note 11 implies note 1.
+               */
+              if (ic_note)
+                regs[nregs++] = RDEP(ic_note, i);
+              else
+                regs[nregs++] = RDEP(rs->regnotes[j], i);
+              no_class_found = 0;
+              ++rs->total_regs;
+            }
+        }
+      for (j=0;j < rs->nchks;j++)
+        {
+          int ic_note = 0;
+
+          if (in_iclass (opc, ics[rs->chks[j]], NULL, NULL, &ic_note))
+            {
+              /* We can ignore ic_note 11 for non PR resources */
+              if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0)
+                ic_note = 0;
+
+              if (ic_note != 0 && rs->chknotes[j] != 0
+                  && ic_note != rs->chknotes[j]
+                  && !(ic_note == 11 && rs->chknotes[j] == 1))
+                fprintf (stderr, "Warning: IC note %d for opcode %s (IC:%s)"
+                         " conflicts with resource %s note %d\n", 
+                         ic_note, opc->name, ics[rs->chks[j]]->name,
+                         rs->name, rs->chknotes[j]);
+              if (ic_note)
+                chks[nchks++] = RDEP(ic_note, i);
+              else
+                chks[nchks++] = RDEP(rs->chknotes[j], i);
+              no_class_found = 0;
+              ++rs->total_chks;
+            }
+        }
+    }
+
+  if (no_class_found)
+    fprintf (stderr, "Warning: opcode %s has no class (ops %d %d %d)\n", 
+             opc->name, 
+             opc->operands[0], opc->operands[1], opc->operands[2]);
+
+  return insert_dependencies (nchks, chks, nregs, regs);
+}
+
+void
+insert_completer_entry (opc, tabent)
+     struct ia64_opcode *opc;
+     struct main_entry *tabent;
+{
+  struct completer_entry **ptr = &tabent->completers;
+  struct completer_entry *parent = NULL;
+  char pcopy[129], *prefix;
+  int at_end = 0;
+
+  if (strlen (opc->name) > 128)
+    {
+      abort ();
+    }
+  strcpy (pcopy, opc->name);
+  prefix = pcopy + get_prefix_len (pcopy);
+  if (prefix[0] != '\0')
+    {
+      prefix++;
+    }
+
+  while (! at_end)
+    {
+      int need_new_ent = 1;
+      int plen = get_prefix_len (prefix);
+      struct string_entry *sent;
+
+      at_end = (prefix[plen] == '\0');
+      prefix[plen] = '\0';
+      sent = insert_string (prefix);
+
+      while (*ptr != NULL)
+	{
+	  int cmpres = sent->num - (*ptr)->name->num;
+
+	  if (cmpres == 0)
+	    {
+	      need_new_ent = 0;
+	      break;
+	    }
+	  else if (cmpres < 0)
+	    {
+	      break;
+	    }
+	  else
+	    {
+	      ptr = &((*ptr)->alternative);
+	    }
+	}
+      if (need_new_ent)
+	{
+	  struct completer_entry *nent = tmalloc (struct completer_entry);
+	  nent->name = sent;
+	  nent->parent = parent;
+	  nent->addl_entries = NULL;
+	  nent->alternative = *ptr;
+	  *ptr = nent;
+	  nent->is_terminal = 0;
+          nent->dependencies = -1;
+	}
+
+      if (! at_end)
+	{
+	  parent = *ptr;
+	  ptr = &((*ptr)->addl_entries);
+	  prefix += plen + 1;
+	}
+    }
+
+  if ((*ptr)->is_terminal)
+    {
+      abort ();
+    }
+
+  (*ptr)->is_terminal = 1;
+  (*ptr)->mask = (ia64_insn)-1;
+  (*ptr)->bits = opc->opcode;
+
+  (*ptr)->dependencies = insert_opcode_dependencies (opc, *ptr);
+}
+
+void
+print_completer_entry (ent)
+     struct completer_entry *ent;
+{
+  int moffset = 0;
+  ia64_insn mask = ent->mask, bits = ent->bits;
+
+  if (mask != 0)
+    {
+      while (! (mask & 1))
+	{
+	  moffset++;
+	  mask = mask >> 1;
+	  bits = bits >> 1;
+	}
+      if (bits & 0xffffffff00000000LL)
+	{
+	  abort ();
+	}
+    }
+  
+  printf ("  { 0x%x, 0x%x, %d, %d, %d, %d, %d, %d },\n",
+	  (int)bits,
+	  (int)mask,
+	  ent->name->num,
+	  ent->alternative != NULL ? ent->alternative->num : -1,
+	  ent->addl_entries != NULL ? ent->addl_entries->num : -1,
+	  moffset,
+	  ent->is_terminal ? 1 : 0,
+          ent->dependencies);
+}
+
+void
+print_completer_table ()
+{
+  int x;
+
+  printf ("static const struct ia64_completer_table\ncompleter_table[] = {\n");
+  for (x = 0; x < glistlen; x++)
+    {
+      print_completer_entry (glist[x]);
+    }
+  printf ("};\n\n");
+}
+
+int
+opcodes_eq (opc1, opc2)
+     struct ia64_opcode *opc1;
+     struct ia64_opcode *opc2;
+{
+  int x;
+  int plen1, plen2;
+
+  if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type) 
+      || (opc1->num_outputs != opc2->num_outputs)
+      || (opc1->flags != opc2->flags))
+    {
+      return 0;
+    }
+  for (x = 0; x < 5; x++)
+    {
+      if (opc1->operands[x] != opc2->operands[x])
+	{
+	  return 0;
+	}
+    }
+  plen1 = get_prefix_len (opc1->name);
+  plen2 = get_prefix_len (opc2->name);
+  if (plen1 == plen2 && (memcmp (opc1->name, opc2->name, plen1) == 0))
+    {
+      return 1;
+    }
+  return 0;
+}
+
+void
+add_opcode_entry (opc)
+     struct ia64_opcode *opc;
+{
+  struct main_entry **place;
+  struct string_entry *name;
+  char prefix[129];
+  int found_it = 0;
+
+  if (strlen (opc->name) > 128)
+    {
+      abort ();
+    }
+  place = &maintable;
+  strcpy (prefix, opc->name);
+  prefix[get_prefix_len (prefix)] = '\0';
+  name = insert_string (prefix);
+
+  /* Walk the list of opcode table entries.  If it's a new
+     instruction, allocate and fill in a new entry.  */
+
+  while (*place != NULL)
+    {
+      if ((*place)->name->num == name->num
+	  && opcodes_eq ((*place)->opcode, opc))
+	{
+	  found_it = 1;
+	  break;
+	}
+      if ((*place)->name->num > name->num)
+	{
+	  break;
+	}
+      place = &((*place)->next);
+    }
+  if (! found_it)
+    {
+      struct main_entry *nent = tmalloc (struct main_entry);
+
+      nent->name = name;
+      nent->opcode = opc;
+      nent->next = *place;
+      nent->completers = 0;
+      *place = nent;
+    }
+  insert_completer_entry (opc, *place);
+}
+
+void
+print_main_table ()
+{
+  struct main_entry *ptr = maintable;
+
+  printf ("static const struct ia64_main_table\nmain_table[] = {\n");
+  while (ptr != NULL)
+    {
+      printf ("  { %d, %d, %d, 0x%llxull, 0x%llxull, { %d, %d, %d, %d, %d }, 0x%x, %d, },\n",
+	      ptr->name->num,
+	      ptr->opcode->type,
+	      ptr->opcode->num_outputs,
+	      ptr->opcode->opcode,
+	      ptr->opcode->mask,
+	      ptr->opcode->operands[0],
+	      ptr->opcode->operands[1],
+	      ptr->opcode->operands[2],
+	      ptr->opcode->operands[3],
+	      ptr->opcode->operands[4],
+	      ptr->opcode->flags,
+	      ptr->completers->num);
+
+      ptr = ptr->next;
+    }
+  printf ("};\n\n");
+}
+
+void
+shrink (table)
+     struct ia64_opcode *table;
+{
+  int curr_opcode;
+
+  for (curr_opcode = 0; table[curr_opcode].name != NULL; curr_opcode++)
+    {
+      add_opcode_entry (table + curr_opcode);
+    }
+}
+
+int
+main (int argc, char **argv)
+{
+  if (argc > 1)
+    {
+      debug = 1;
+    }
+
+  load_insn_classes();
+  load_dependencies();
+
+  shrink (ia64_opcodes_a);
+  shrink (ia64_opcodes_b);
+  shrink (ia64_opcodes_f);
+  shrink (ia64_opcodes_i);
+  shrink (ia64_opcodes_m);
+  shrink (ia64_opcodes_x);
+  shrink (ia64_opcodes_d);
+
+  collapse_redundant_completers ();
+
+  printf ("/* This file is automatically generated by ia64-gen.  Do not edit! */\n");
+  print_string_table ();
+  print_dependency_table ();
+  print_completer_table ();
+  print_main_table ();
+
+  generate_disassembler ();
+
+  exit (0);
+}
diff --git a/opcodes/ia64-ic.tbl b/opcodes/ia64-ic.tbl
new file mode 100644
index 0000000..021194a
--- /dev/null
+++ b/opcodes/ia64-ic.tbl
@@ -0,0 +1,205 @@
+Class;	Events/Instructions
+all;	IC:predicatable-instructions, IC:unpredicatable-instructions
+branches;	IC:indirect-brs, IC:ip-rel-brs
+cfm-readers;	IC:fr-readers, IC:fr-writers, IC:gr-readers, IC:gr-writers, IC:mod-sched-brs, IC:predicatable-instructions, IC:pr-writers, alloc, br.call, brl.call, br.ret, cover, loadrs, rfi, IC:chk-a, invala.e
+chk-a;	chk.a.clr, chk.a.nc
+cmpxchg;	cmpxchg1, cmpxchg2, cmpxchg4, cmpxchg8
+czx;	czx1, czx2
+fcmp-s0;	fcmp[Field(sf)==s0]
+fcmp-s1;	fcmp[Field(sf)==s1]
+fcmp-s2;	fcmp[Field(sf)==s2]
+fcmp-s3;	fcmp[Field(sf)==s3]
+fetchadd;	fetchadd4, fetchadd8
+fp-arith;	fadd, famax, famin, fcvt.fx, fcvt.fxu, fcvt.xuf, fma, fmax, fmin, fmpy, fms, fnma, fnmpy, fnorm, fpamax, fpamin, fpcvt.fx, fpcvt.fxu, fpma, fpmax, fpmin, fpmpy, fpms, fpnma, fpnmpy, fprcpa, fprsqrta, frcpa, frsqrta, fsub
+fp-arith-s0;	IC:fp-arith[Field(sf)==s0]
+fp-arith-s1;	IC:fp-arith[Field(sf)==s1]
+fp-arith-s2;	IC:fp-arith[Field(sf)==s2]
+fp-arith-s3;	IC:fp-arith[Field(sf)==s3]
+fp-non-arith;	fabs, fand, fandcm, fclass, fcvt.xf, fmerge, fmix, fneg, fnegabs, for, fpabs, fpmerge, fpack, fpneg, fpnegabs, fselect, fswap, fsxt, fxor, xma
+fpcmp-s0;	fpcmp[Field(sf)==s0]
+fpcmp-s1;	fpcmp[Field(sf)==s1]
+fpcmp-s2;	fpcmp[Field(sf)==s2]
+fpcmp-s3;	fpcmp[Field(sf)==s3]
+fr-readers;	IC:fp-arith, IC:fp-non-arith, IC:pr-writers-fp, chk.s[Format in {M21}], getf
+fr-writers;	IC:fp-arith, IC:fp-non-arith\fclass, IC:mem-readers-fp
+gr-readers;	IC:gr-readers-writers, IC:mem-readers, IC:mem-writers, chk.s, cmp, cmp4, fc, itc.i, itc.d, itr.i, itr.d, IC:mov-to-AR-gr, IC:mov-to-BR, IC:mov-to-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-to-PR-allreg, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:probe-all, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, setf, tbit, tnat
+gr-readers-writers;	IC:mov-from-IND, add, addl, addp4, adds, and, andcm, IC:czx, dep\dep[Format in {I13}], extr, IC:mem-readers-int, IC:ld-all-postinc, IC:lfetch-postinc, IC:mix, IC:mux, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-nofault, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, shl, shladd, shladdp4, shr, shrp, IC:st-postinc, sub, IC:sxt, tak, thash, tpa, ttag, IC:unpack, xor, IC:zxt
+gr-writers;	alloc, dep, getf, IC:gr-readers-writers, IC:mem-readers-int, IC:mov-from-AR, IC:mov-from-BR, IC:mov-from-CR, IC:mov-from-PR, IC:mov-immediate, IC:mov-from-PSR, IC:mov-from-PSR-um, IC:mov-ip, movl
+indirect-brp;	brp[Format in {B7}]
+indirect-brs;	br.call[Format in {B5}], br.cond[Format in {B4}], br.ia, br.ret
+invala-all;	invala[Format in {M24}], invala.e
+ip-rel-brs;	IC:mod-sched-brs, br.call[Format in {B3}], brl.call, brl.cond, br.cond[Format in {B1}], br.cloop
+ld;	ld1, ld2, ld4, ld8, ld8.fill
+ld-a;	ld1.a, ld2.a, ld4.a, ld8.a
+ld-all-postinc;	IC:ld[Format in {M2 M3}], IC:ldfp[Format in {M12}], IC:ldf[Format in {M7 M8}]
+ld-c;	IC:ld-c-nc, IC:ld-c-clr
+ld-c-clr;	ld1.c.clr, ld2.c.clr, ld4.c.clr, ld8.c.clr, IC:ld-c-clr-acq
+ld-c-clr-acq;	ld1.c.clr.acq, ld2.c.clr.acq, ld4.c.clr.acq, ld8.c.clr.acq
+ld-c-nc;	ld1.c.nc, ld2.c.nc, ld4.c.nc, ld8.c.nc
+ld-s;	ld1.s, ld2.s, ld4.s, ld8.s
+ld-sa;	ld1.sa, ld2.sa, ld4.sa, ld8.sa
+ldf;	ldfs, ldfd, ldfe, ldf8, ldf.fill
+ldf-a;	ldfs.a, ldfd.a, ldfe.a, ldf8.a
+ldf-c;	IC:ldf-c-nc, IC:ldf-c-clr
+ldf-c-clr;	ldfs.c.clr, ldfd.c.clr, ldfe.c.clr, ldf8.c.clr
+ldf-c-nc;	ldfs.c.nc, ldfd.c.nc, ldfe.c.nc, ldf8.c.nc
+ldf-s;	ldfs.s, ldfd.s, ldfe.s, ldf8.s
+ldf-sa;	ldfs.sa, ldfd.sa, ldfe.sa, ldf8.sa
+ldfp;	ldfps, ldfpd, ldfp8
+ldfp-a;	ldfps.a, ldfpd.a, ldfp8.a
+ldfp-c;	IC:ldfp-c-nc, IC:ldfp-c-clr
+ldfp-c-clr;	ldfps.c.clr, ldfpd.c.clr, ldfp8.c.clr
+ldfp-c-nc;	ldfps.c.nc, ldfpd.c.nc, ldfp8.c.nc
+ldfp-s;	ldfps.s, ldfpd.s, ldfp8.s
+ldfp-sa;	ldfps.sa, ldfpd.sa, ldfp8.sa
+lfetch-all;	lfetch
+lfetch-fault;	lfetch[Field(lftype)==fault]
+lfetch-nofault;	lfetch[Field(lftype)==]
+lfetch-postinc;	lfetch[Format in {M14 M15}]
+mem-readers;	IC:mem-readers-fp, IC:mem-readers-int
+mem-readers-alat;	IC:ld-a, IC:ldf-a, IC:ldfp-a, IC:ld-sa, IC:ldf-sa, IC:ldfp-sa, IC:ld-c, IC:ldf-c, IC:ldfp-c
+mem-readers-fp;	IC:ldf, IC:ldfp
+mem-readers-int;	IC:cmpxchg, IC:fetchadd, IC:xchg, IC:ld
+mem-readers-spec;	IC:ld-s, IC:ld-sa, IC:ldf-s, IC:ldf-sa, IC:ldfp-s, IC:ldfp-sa
+mem-writers;	IC:mem-writers-fp, IC:mem-writers-int
+mem-writers-fp;	IC:stf
+mem-writers-int;	IC:cmpxchg, IC:fetchadd, IC:xchg, IC:st
+mix;	mix1, mix2, mix4
+mod-sched-brs;	br.cexit, br.ctop, br.wexit, br.wtop
+mod-sched-brs-counted;	br.cexit, br.cloop, br.ctop
+mov-from-AR;	IC:mov-from-AR-M, IC:mov-from-AR-I, IC:mov-from-AR-IM
+mov-from-AR-BSP;	IC:mov-from-AR-M[Field(ar3) == BSP]
+mov-from-AR-BSPSTORE;	IC:mov-from-AR-M[Field(ar3) == BSPSTORE]
+mov-from-AR-CCV;	IC:mov-from-AR-M[Field(ar3) == CCV]
+mov-from-AR-EC;	IC:mov-from-AR-I[Field(ar3) == EC]
+mov-from-AR-FPSR;	IC:mov-from-AR-M[Field(ar3) == FPSR]
+mov-from-AR-I;	mov_ar[Format in {I28}]
+mov-from-AR-ig;	IC:mov-from-AR-IM[Field(ar3) in {48-63 112-127}]
+mov-from-AR-IM;	mov_ar[Format in {I28 M31}]
+mov-from-AR-ITC;	IC:mov-from-AR-M[Field(ar3) == ITC]
+mov-from-AR-K;	IC:mov-from-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}]
+mov-from-AR-LC;	IC:mov-from-AR-I[Field(ar3) == LC]
+mov-from-AR-M;	mov_ar[Format in {M31}]
+mov-from-AR-PFS;	IC:mov-from-AR-I[Field(ar3) == PFS]
+mov-from-AR-RNAT;	IC:mov-from-AR-M[Field(ar3) == RNAT]
+mov-from-AR-RSC;	IC:mov-from-AR-M[Field(ar3) == RSC]
+mov-from-AR-rv;	IC:none
+mov-from-AR-UNAT;	IC:mov-from-AR-M[Field(ar3) == UNAT]
+mov-from-BR;	mov_br[Format in {I22}]
+mov-from-CR;	mov_cr[Format in {M33}]
+mov-from-CR-CMCV;	IC:mov-from-CR[Field(cr3) == CMCV]
+mov-from-CR-DCR;	IC:mov-from-CR[Field(cr3) == DCR]
+mov-from-CR-EOI;	IC:mov-from-CR[Field(cr3) == EOI]
+mov-from-CR-GPTA;	IC:mov-from-CR[Field(cr3) == GPTA]
+mov-from-CR-IFA;	IC:mov-from-CR[Field(cr3) == IFA]
+mov-from-CR-IFS;	IC:mov-from-CR[Field(cr3) == IFS]
+mov-from-CR-IHA;	IC:mov-from-CR[Field(cr3) == IHA]
+mov-from-CR-IIM;	IC:mov-from-CR[Field(cr3) == IIM]
+mov-from-CR-IIP;	IC:mov-from-CR[Field(cr3) == IIP]
+mov-from-CR-IIPA;	IC:mov-from-CR[Field(cr3) == IIPA]
+mov-from-CR-IPSR;	IC:mov-from-CR[Field(cr3) == IPSR]
+mov-from-CR-IRR;	IC:mov-from-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}]
+mov-from-CR-ISR;	IC:mov-from-CR[Field(cr3) == ISR]
+mov-from-CR-ITIR;	IC:mov-from-CR[Field(cr3) == ITIR]
+mov-from-CR-ITM;	IC:mov-from-CR[Field(cr3) == ITM]
+mov-from-CR-ITV;	IC:mov-from-CR[Field(cr3) == ITV]
+mov-from-CR-IVA;	IC:mov-from-CR[Field(cr3) == IVA]
+mov-from-CR-IVR;	IC:mov-from-CR[Field(cr3) == IVR]
+mov-from-CR-LID;	IC:mov-from-CR[Field(cr3) == LID]
+mov-from-CR-LRR;	IC:mov-from-CR[Field(cr3) in {LRR0 LRR1}]
+mov-from-CR-PMV;	IC:mov-from-CR[Field(cr3) == PMV]
+mov-from-CR-PTA;	IC:mov-from-CR[Field(cr3) == PTA]
+mov-from-CR-rv;	IC:none
+mov-from-CR-TPR;	IC:mov-from-CR[Field(cr3) == TPR]
+mov-from-IND;	mov_indirect[Format in {M43}]
+mov-from-IND-CPUID;	IC:mov-from-IND[Field(ireg) == cpuid]
+mov-from-IND-DBR;	IC:mov-from-IND[Field(ireg) == dbr]
+mov-from-IND-IBR;	IC:mov-from-IND[Field(ireg) == ibr]
+mov-from-IND-MSR;	IC:mov-from-IND[Field(ireg) == msr]
+mov-from-IND-PKR;	IC:mov-from-IND[Field(ireg) == pkr]
+mov-from-IND-PMC;	IC:mov-from-IND[Field(ireg) == pmc]
+mov-from-IND-PMD;	IC:mov-from-IND[Field(ireg) == pmd]
+mov-from-IND-priv;	IC:mov-from-IND[Field(ireg) in {dbr ibr msr pkr pmc rr}]
+mov-from-IND-RR;	IC:mov-from-IND[Field(ireg) == rr]
+mov-from-PR;	mov_pr[Format in {I25}]
+mov-from-PSR;	mov_psr[Format in {M36}]
+mov-from-PSR-um;	mov_um[Format in {M36}]
+mov-immediate;	addl[Format in {A5}]
+mov-ip;	mov_ip[Format in {I25}]
+mov-to-AR;	IC:mov-to-AR-M, IC:mov-to-AR-I
+mov-to-AR-BSP;	IC:mov-to-AR-M[Field(ar3) == BSP]
+mov-to-AR-BSPSTORE;	IC:mov-to-AR-M[Field(ar3) == BSPSTORE]
+mov-to-AR-CCV;	IC:mov-to-AR-M[Field(ar3) == CCV]
+mov-to-AR-EC;	IC:mov-to-AR-I[Field(ar3) == EC]
+mov-to-AR-FPSR;	IC:mov-to-AR-M[Field(ar3) == FPSR]
+mov-to-AR-gr;	IC:mov-to-AR-M[Format in {M29}], IC:mov-to-AR-I[Format in {I26}]
+mov-to-AR-I;	mov_ar[Format in {I26 I27}]
+mov-to-AR-ig;	IC:mov-to-AR-IM[Field(ar3) in {48-63 112-127}]
+mov-to-AR-IM;	mov_ar[Format in {I26 I27 M29 M30}]
+mov-to-AR-ITC;	IC:mov-to-AR-M[Field(ar3) == ITC]
+mov-to-AR-K;	IC:mov-to-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}]
+mov-to-AR-LC;	IC:mov-to-AR-I[Field(ar3) == LC]
+mov-to-AR-M;	mov_ar[Format in {M29 M30}]
+mov-to-AR-PFS;	IC:mov-to-AR-I[Field(ar3) == PFS]
+mov-to-AR-RNAT;	IC:mov-to-AR-M[Field(ar3) == RNAT]
+mov-to-AR-RSC;	IC:mov-to-AR-M[Field(ar3) == RSC]
+mov-to-AR-UNAT;	IC:mov-to-AR-M[Field(ar3) == UNAT]
+mov-to-BR;	mov_br[Format in {I21}]
+mov-to-CR;	mov_cr[Format in {M32}]
+mov-to-CR-CMCV;	IC:mov-to-CR[Field(cr3) == CMCV]
+mov-to-CR-DCR;	IC:mov-to-CR[Field(cr3) == DCR]
+mov-to-CR-EOI;	IC:mov-to-CR[Field(cr3) == EOI]
+mov-to-CR-GPTA;	IC:mov-to-CR[Field(cr3) == GPTA]
+mov-to-CR-IFA;	IC:mov-to-CR[Field(cr3) == IFA]
+mov-to-CR-IFS;	IC:mov-to-CR[Field(cr3) == IFS]
+mov-to-CR-IHA;	IC:mov-to-CR[Field(cr3) == IHA]
+mov-to-CR-IIM;	IC:mov-to-CR[Field(cr3) == IIM]
+mov-to-CR-IIP;	IC:mov-to-CR[Field(cr3) == IIP]
+mov-to-CR-IIPA;	IC:mov-to-CR[Field(cr3) == IIPA]
+mov-to-CR-IPSR;	IC:mov-to-CR[Field(cr3) == IPSR]
+mov-to-CR-IRR;	IC:mov-to-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}]
+mov-to-CR-ISR;	IC:mov-to-CR[Field(cr3) == ISR]
+mov-to-CR-ITIR;	IC:mov-to-CR[Field(cr3) == ITIR]
+mov-to-CR-ITM;	IC:mov-to-CR[Field(cr3) == ITM]
+mov-to-CR-ITV;	IC:mov-to-CR[Field(cr3) == ITV]
+mov-to-CR-IVA;	IC:mov-to-CR[Field(cr3) == IVA]
+mov-to-CR-IVR;	IC:mov-to-CR[Field(cr3) == IVR]
+mov-to-CR-LID;	IC:mov-to-CR[Field(cr3) == LID]
+mov-to-CR-LRR;	IC:mov-to-CR[Field(cr3) in {LRR0 LRR1}]
+mov-to-CR-PMV;	IC:mov-to-CR[Field(cr3) == PMV]
+mov-to-CR-PTA;	IC:mov-to-CR[Field(cr3) == PTA]
+mov-to-CR-TPR;	IC:mov-to-CR[Field(cr3) == TPR]
+mov-to-IND;	mov_indirect[Format in {M42}]
+mov-to-IND-CPUID;	IC:mov-to-IND[Field(ireg) == cpuid]
+mov-to-IND-DBR;	IC:mov-to-IND[Field(ireg) == dbr]
+mov-to-IND-IBR;	IC:mov-to-IND[Field(ireg) == ibr]
+mov-to-IND-MSR;	IC:mov-to-IND[Field(ireg) == msr]
+mov-to-IND-PKR;	IC:mov-to-IND[Field(ireg) == pkr]
+mov-to-IND-PMC;	IC:mov-to-IND[Field(ireg) == pmc]
+mov-to-IND-PMD;	IC:mov-to-IND[Field(ireg) == pmd]
+mov-to-IND-priv;	IC:mov-to-IND
+mov-to-IND-RR;	IC:mov-to-IND[Field(ireg) == rr]
+mov-to-PR;	IC:mov-to-PR-allreg, IC:mov-to-PR-rotreg
+mov-to-PR-allreg;	mov_pr[Format in {I23}]
+mov-to-PR-rotreg;	mov_pr[Format in {I24}]
+mov-to-PSR-l;	mov_psr[Format in {M35}]
+mov-to-PSR-um;	mov_um[Format in {M35}]
+mux;	mux1, mux2
+none;	-
+pack;	pack2, pack4
+padd;	padd1, padd2, padd4
+pavg;	pavg1, pavg2
+pavgsub;	pavgsub1, pavgsub2
+pcmp;	pcmp1, pcmp2, pcmp4
+pmax;	pmax1, pmax2
+pmin;	pmin1, pmin2
+pmpy;	pmpy2
+pmpyshr;	pmpyshr2
+pr-and-writers;	IC:pr-gen-writers-int[Field(ctype) in {and andcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}]
+pr-gen-writers-fp;	fclass, fcmp
+pr-gen-writers-int;	cmp, cmp4, tbit, tnat
+pr-norm-writers-fp;	IC:pr-gen-writers-fp[Field(ctype)==]
+pr-norm-writers-int;	IC:pr-gen-writers-int[Field(ctype)==]
+pr-or-writers;	IC:pr-gen-writers-int[Field(ctype) in {or orcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}]
+pr-readers-br;	br.call, br.cond, brl.call, brl.cond, br.ret, br.wexit, br.wtop, break.b, break, nop.b, nop, IC:ReservedBQP
+pr-readers-nobr-nomovpr;	add, addp4, and, andcm, break.f, break.i, break.m, break.x, break, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, IC:invala-all, itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M, IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-immediate, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, nop.f, nop.i, nop.m, nop.x, nop, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak,
\ No newline at end of file
diff --git a/opcodes/ia64-opc-a.c b/opcodes/ia64-opc-a.c
new file mode 100644
index 0000000..8df8029
--- /dev/null
+++ b/opcodes/ia64-opc-a.c
@@ -0,0 +1,364 @@
+/* ia64-opc-a.c -- IA-64 `A' opcode table.
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the
+   Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
+
+#include "ia64-opc.h"
+
+#define A	IA64_TYPE_A, 1
+#define A2	IA64_TYPE_A, 2
+
+/* instruction bit fields: */
+#define bC(x)		(((ia64_insn) ((x) & 0x1)) << 12)
+#define bImm14(x)	((((ia64_insn) (((x) >>  0) & 0x7f)) << 13) | \
+			 (((ia64_insn) (((x) >>  7) & 0x3f)) << 27) | \
+			 (((ia64_insn) (((x) >> 13) & 0x01)) << 36))
+#define bR3a(x)		(((ia64_insn) ((x) & 0x7f)) << 20)
+#define bR3b(x)		(((ia64_insn) ((x) & 0x3)) << 20)
+#define bTa(x)		(((ia64_insn) ((x) & 0x1)) << 33)
+#define bTb(x)		(((ia64_insn) ((x) & 0x1)) << 36)
+#define bVe(x)		(((ia64_insn) ((x) & 0x1)) << 33)
+#define bX(x)		(((ia64_insn) ((x) & 0x1)) << 33)
+#define bX2(x)		(((ia64_insn) ((x) & 0x3)) << 34)
+#define bX2a(x)		(((ia64_insn) ((x) & 0x3)) << 34)
+#define bX2b(x)		(((ia64_insn) ((x) & 0x3)) << 27)
+#define bX4(x)		(((ia64_insn) ((x) & 0xf)) << 29)
+#define bZa(x)		(((ia64_insn) ((x) & 0x1)) << 36)
+#define bZb(x)		(((ia64_insn) ((x) & 0x1)) << 33)
+
+/* instruction bit masks: */
+#define mC	bC (-1)
+#define mImm14	bImm14 (-1)
+#define mR3a	bR3a (-1)
+#define mR3b	bR3b (-1)
+#define mTa	bTa (-1)
+#define mTb	bTb (-1)
+#define mVe	bVe (-1)
+#define mX	bX (-1)
+#define mX2	bX2 (-1)
+#define mX2a	bX2a (-1)
+#define mX2b	bX2b (-1)
+#define mX4	bX4 (-1)
+#define mZa	bZa (-1)
+#define mZb	bZb (-1)
+
+#define OpR3b(a,b)		(bOp (a) | bR3b (b)), (mOp | mR3b)
+#define OpX2aVe(a,b,c)		(bOp (a) | bX2a (b) | bVe (c)), \
+				(mOp | mX2a | mVe)
+#define OpX2aVeR3a(a,b,c,d)	(bOp (a) | bX2a (b) | bVe (c) | bR3a (d)), \
+				(mOp | mX2a | mVe | mR3a)
+#define OpX2aVeImm14(a,b,c,d)	(bOp (a) | bX2a (b) | bVe (c) | bImm14 (d)), \
+				(mOp | mX2a | mVe | mImm14)
+#define OpX2aVeX4(a,b,c,d)	(bOp (a) | bX2a (b) | bVe (c) | bX4 (d)), \
+				(mOp | mX2a | mVe | mX4)
+#define OpX2aVeX4X2b(a,b,c,d,e)	\
+	(bOp (a) | bX2a (b) | bVe (c) | bX4 (d) | bX2b (e)), \
+	(mOp | mX2a | mVe | mX4 | mX2b)
+#define OpX2TbTaC(a,b,c,d,e) \
+	(bOp (a) | bX2 (b) | bTb (c) | bTa (d) | bC (e)), \
+	(mOp | mX2 | mTb | mTa | mC)
+#define OpX2TaC(a,b,c,d)	(bOp (a) | bX2 (b) | bTa (c) | bC (d)), \
+				(mOp | mX2 | mTa | mC)
+#define OpX2aZaZbX4(a,b,c,d,e) \
+	(bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e)), \
+	(mOp | mX2a | mZa | mZb | mX4)
+#define OpX2aZaZbX4X2b(a,b,c,d,e,f) \
+	(bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e) | bX2b (f)), \
+	(mOp | mX2a | mZa | mZb | mX4 | mX2b)
+
+struct ia64_opcode ia64_opcodes_a[] =
+  {
+    /* A-type instruction encodings (sorted according to major opcode) */
+
+    {"add",	 A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}},
+    {"add",	 A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}},
+    {"sub",	 A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}},
+    {"sub",	 A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}},
+    {"addp4",	 A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}},
+    {"and",	 A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}},
+    {"andcm",	 A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}},
+    {"or",	 A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}},
+    {"xor",	 A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}},
+    {"shladd",	 A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}},
+    {"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}},
+    {"sub",	 A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}},
+    {"and",	 A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}},
+    {"andcm",	 A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}},
+    {"or",	 A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}},
+    {"xor",	 A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}},
+    {"mov",	 A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}},
+    {"mov",	 A, OpX2aVeR3a (8, 2, 0, 0), {R1, IMM14}, PSEUDO},
+    {"adds",	 A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}},
+    {"addp4",	 A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}},
+    {"padd1",		 A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}},
+    {"padd2",		 A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}},
+    {"padd4",		 A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}},
+    {"padd1.sss",	 A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}},
+    {"padd2.sss",	 A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}},
+    {"padd1.uuu",	 A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}},
+    {"padd2.uuu",	 A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}},
+    {"padd1.uus",	 A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}},
+    {"padd2.uus",	 A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}},
+    {"psub1",		 A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}},
+    {"psub2",		 A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}},
+    {"psub4",		 A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}},
+    {"psub1.sss",	 A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}},
+    {"psub2.sss",	 A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}},
+    {"psub1.uuu",	 A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}},
+    {"psub2.uuu",	 A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}},
+    {"psub1.uus",	 A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}},
+    {"psub2.uus",	 A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}},
+    {"pavg1",		 A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}},
+    {"pavg2",		 A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}},
+    {"pavg1.raz",	 A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}},
+    {"pavg2.raz",	 A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}},
+    {"pavgsub1",	 A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}},
+    {"pavgsub2",	 A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}},
+    {"pcmp1.eq",	 A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}},
+    {"pcmp2.eq",	 A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}},
+    {"pcmp4.eq",	 A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}},
+    {"pcmp1.gt",	 A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}},
+    {"pcmp2.gt",	 A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}},
+    {"pcmp4.gt",	 A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}},
+    {"pshladd2",	 A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}},
+    {"pshradd2",	 A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}},
+
+    {"mov",		 A, OpR3b (9, 0), {R1, IMM22}, PSEUDO},
+    {"addl",		 A, Op    (9),	  {R1, IMM22, R3_2}},
+
+    {"cmp.lt",		 A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}},
+    {"cmp.le",		 A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}},
+    {"cmp.gt",		 A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}},
+    {"cmp.ge",		 A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}},
+    {"cmp.lt.unc",	 A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}},
+    {"cmp.le.unc",	 A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}},
+    {"cmp.gt.unc",	 A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}},
+    {"cmp.ge.unc",	 A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}},
+    {"cmp.eq.and",	 A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}},
+    {"cmp.ne.andcm",	 A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
+    {"cmp.ne.and",	 A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}},
+    {"cmp.eq.andcm",	 A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
+    {"cmp4.lt",		 A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}},
+    {"cmp4.le",		 A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}},
+    {"cmp4.gt",		 A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}},
+    {"cmp4.ge",		 A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}},
+    {"cmp4.lt.unc",	 A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}},
+    {"cmp4.le.unc",	 A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}},
+    {"cmp4.gt.unc",	 A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}},
+    {"cmp4.ge.unc",	 A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}},
+    {"cmp4.eq.and",	 A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}},
+    {"cmp4.ne.andcm",	 A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
+    {"cmp4.ne.and",	 A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}},
+    {"cmp4.eq.andcm",	 A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
+    {"cmp.gt.and",	 A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}},
+    {"cmp.le.andcm",	 A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp.le.and",	 A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}},
+    {"cmp.gt.andcm",	 A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp.ge.and",	 A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}},
+    {"cmp.lt.andcm",	 A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp.lt.and",	 A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}},
+    {"cmp.ge.andcm",	 A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp4.gt.and",	 A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}},
+    {"cmp4.le.andcm",	 A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp4.le.and",	 A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}},
+    {"cmp4.gt.andcm",	 A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp4.ge.and",	 A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}},
+    {"cmp4.lt.andcm",	 A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp4.lt.and",	 A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}},
+    {"cmp4.ge.andcm",	 A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp.lt",		 A2, OpX2TaC   (0xc, 2, 0, 0), {P1, P2, IMM8, R3}},
+    {"cmp.le",		 A2, OpX2TaC   (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}},
+    {"cmp.gt",		 A2, OpX2TaC   (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}},
+    {"cmp.ge",		 A2, OpX2TaC   (0xc, 2, 0, 0), {P2, P1, IMM8, R3}},
+    {"cmp.lt.unc",	 A2, OpX2TaC   (0xc, 2, 0, 1), {P1, P2, IMM8, R3}},
+    {"cmp.le.unc",	 A2, OpX2TaC   (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}},
+    {"cmp.gt.unc",	 A2, OpX2TaC   (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}},
+    {"cmp.ge.unc",	 A2, OpX2TaC   (0xc, 2, 0, 1), {P2, P1, IMM8, R3}},
+    {"cmp.eq.and",	 A2, OpX2TaC   (0xc, 2, 1, 0), {P1, P2, IMM8, R3}},
+    {"cmp.ne.andcm",	 A2, OpX2TaC   (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
+    {"cmp.ne.and",	 A2, OpX2TaC   (0xc, 2, 1, 1), {P1, P2, IMM8, R3}},
+    {"cmp.eq.andcm",	 A2, OpX2TaC   (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
+    {"cmp4.lt",		 A2, OpX2TaC   (0xc, 3, 0, 0), {P1, P2, IMM8, R3}},
+    {"cmp4.le",		 A2, OpX2TaC   (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}},
+    {"cmp4.gt",		 A2, OpX2TaC   (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}},
+    {"cmp4.ge",		 A2, OpX2TaC   (0xc, 3, 0, 0), {P2, P1, IMM8, R3}},
+    {"cmp4.lt.unc",	 A2, OpX2TaC   (0xc, 3, 0, 1), {P1, P2, IMM8, R3}},
+    {"cmp4.le.unc",	 A2, OpX2TaC   (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}},
+    {"cmp4.gt.unc",	 A2, OpX2TaC   (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}},
+    {"cmp4.ge.unc",	 A2, OpX2TaC   (0xc, 3, 0, 1), {P2, P1, IMM8, R3}},
+    {"cmp4.eq.and",	 A2, OpX2TaC   (0xc, 3, 1, 0), {P1, P2, IMM8, R3}},
+    {"cmp4.ne.andcm",	 A2, OpX2TaC   (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
+    {"cmp4.ne.and",	 A2, OpX2TaC   (0xc, 3, 1, 1), {P1, P2, IMM8, R3}},
+    {"cmp4.eq.andcm",	 A2, OpX2TaC   (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
+    {"cmp.ltu",		 A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}},
+    {"cmp.leu",		 A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}},
+    {"cmp.gtu",		 A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}},
+    {"cmp.geu",		 A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}},
+    {"cmp.ltu.unc",	 A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}},
+    {"cmp.leu.unc",	 A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}},
+    {"cmp.gtu.unc",	 A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}},
+    {"cmp.geu.unc",	 A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}},
+    {"cmp.eq.or",	 A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}},
+    {"cmp.ne.orcm",	 A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
+    {"cmp.ne.or",	 A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}},
+    {"cmp.eq.orcm",	 A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
+    {"cmp4.ltu",	 A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}},
+    {"cmp4.leu",	 A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}},
+    {"cmp4.gtu",	 A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}},
+    {"cmp4.geu",	 A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}},
+    {"cmp4.ltu.unc",	 A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}},
+    {"cmp4.leu.unc",	 A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}},
+    {"cmp4.gtu.unc",	 A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}},
+    {"cmp4.geu.unc",	 A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}},
+    {"cmp4.eq.or",	 A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}},
+    {"cmp4.ne.orcm",	 A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
+    {"cmp4.ne.or",	 A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}},
+    {"cmp4.eq.orcm",	 A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
+    {"cmp.gt.or",	 A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}},
+    {"cmp.le.orcm",	 A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp.le.or",	 A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}},
+    {"cmp.gt.orcm",	 A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp.ge.or",	 A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}},
+    {"cmp.lt.orcm",	 A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp.lt.or",	 A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}},
+    {"cmp.ge.orcm",	 A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp4.gt.or",	 A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}},
+    {"cmp4.le.orcm",	 A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp4.le.or",	 A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}},
+    {"cmp4.gt.orcm",	 A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp4.ge.or",	 A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}},
+    {"cmp4.lt.orcm",	 A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp4.lt.or",	 A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}},
+    {"cmp4.ge.orcm",	 A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
+    {"cmp.ltu",		 A2, OpX2TaC   (0xd, 2, 0, 0), {P1, P2, IMM8, R3}},
+    {"cmp.leu",		 A2, OpX2TaC   (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}},
+    {"cmp.gtu",		 A2, OpX2TaC   (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}},
+    {"cmp.geu",		 A2, OpX2TaC   (0xd, 2, 0, 0), {P2, P1, IMM8, R3}},
+    {"cmp.ltu.unc",	 A2, OpX2TaC   (0xd, 2, 0, 1), {P1, P2, IMM8, R3}},
+    {"cmp.leu.unc",	 A2, OpX2TaC   (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3}},
+    {"cmp.gtu.unc",	 A2, OpX2TaC   (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3}},
+    {"cmp.geu.unc",	 A2, OpX2TaC   (0xd, 2, 0, 1), {P2, P1, IMM8, R3}},
+    {"cmp.eq.or",	 A2, OpX2TaC   (0xd, 2, 1, 0), {P1, P2, IMM8, R3}},
+    {"cmp.ne.orcm",	 A2, OpX2TaC   (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
+    {"cmp.ne.or",	 A2, OpX2TaC   (0xd, 2, 1, 1), {P1, P2, IMM8, R3}},
+    {"cmp.eq.orcm",	 A2, OpX2TaC   (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
+    {"cmp4.ltu",	 A2, OpX2TaC   (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}},
+    {"cmp4.leu",	 A2, OpX2TaC   (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}},
+    {"cmp4.gtu",	 A2, OpX2TaC   (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}},
+    {"cmp4.geu",	 A2, OpX2TaC   (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}},
+    {"cmp4.ltu.unc",	 A2, OpX2TaC   (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}},
+    {"cmp4.leu.unc",	 A2, OpX2TaC   (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}},
+    {"cmp4.gtu.unc",	 A2, OpX2TaC   (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}},
+    {"cmp4.geu.unc",	 A2, OpX2TaC   (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}},
+    {"cmp4.eq.or",	 A2, OpX2TaC   (0xd, 3, 1, 0), {P1, P2, IMM8, R3}},
+    {"cmp4.ne.orcm",	 A2, OpX2TaC   (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
+    {"cmp4.ne.or",	 A2, OpX2TaC   (0xd, 3, 1, 1), {P1, P2, IMM8, R3}},
+    {"cmp4.eq.orcm",	 A2, OpX2TaC   (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
+    {"cmp.eq",		 A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}},
+    {"cmp.ne",		 A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}},
+    {"cmp.eq.unc",	 A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}},
+    {"cmp.ne.unc",	 A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}},
+    {"cmp.eq.or.andcm",	 A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}},
+    {"cmp.ne.and.orcm",	 A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO},
+    {"cmp.ne.or.andcm",	 A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}},
+    {"cmp.eq.and.orcm",	 A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO},
+    {"cmp4.eq",		 A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}},
+    {"cmp4.ne",		 A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}},
+    {"cmp4.eq.unc",	 A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}},
+    {"cmp4.ne.unc",	 A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}},
+    {"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}},
+    {"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO},
+    {"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}},
+    {"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO},
+    {"cmp.gt.or.andcm",	 A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3}},
+    {"cmp.le.and.orcm",	 A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO},
+    {"cmp.le.or.andcm",	 A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3}},
+    {"cmp.gt.and.orcm",	 A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO},
+    {"cmp.ge.or.andcm",	 A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3}},
+    {"cmp.lt.and.orcm",	 A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO},
+    {"cmp.lt.or.andcm",	 A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3}},
+    {"cmp.ge.and.orcm",	 A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO},
+    {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3}},
+    {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO},
+    {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3}},
+    {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO},
+    {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3}},
+    {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO},
+    {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3}},
+    {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO},
+    {"cmp.eq",		 A2, OpX2TaC   (0xe, 2, 0, 0), {P1, P2, IMM8, R3}},
+    {"cmp.ne",		 A2, OpX2TaC   (0xe, 2, 0, 0), {P2, P1, IMM8, R3}},
+    {"cmp.eq.unc",	 A2, OpX2TaC   (0xe, 2, 0, 1), {P1, P2, IMM8, R3}},
+    {"cmp.ne.unc",	 A2, OpX2TaC   (0xe, 2, 0, 1), {P2, P1, IMM8, R3}},
+    {"cmp.eq.or.andcm",	 A2, OpX2TaC   (0xe, 2, 1, 0), {P1, P2, IMM8, R3}},
+    {"cmp.ne.and.orcm",	 A2, OpX2TaC   (0xe, 2, 1, 0), {P2, P1, IMM8, R3}, PSEUDO},
+    {"cmp.ne.or.andcm",	 A2, OpX2TaC   (0xe, 2, 1, 1), {P1, P2, IMM8, R3}},
+    {"cmp.eq.and.orcm",	 A2, OpX2TaC   (0xe, 2, 1, 1), {P2, P1, IMM8, R3}, PSEUDO},
+    {"cmp4.eq",		 A2, OpX2TaC   (0xe, 3, 0, 0), {P1, P2, IMM8, R3}},
+    {"cmp4.ne",		 A2, OpX2TaC   (0xe, 3, 0, 0), {P2, P1, IMM8, R3}},
+    {"cmp4.eq.unc",	 A2, OpX2TaC   (0xe, 3, 0, 1), {P1, P2, IMM8, R3}},
+    {"cmp4.ne.unc",	 A2, OpX2TaC   (0xe, 3, 0, 1), {P2, P1, IMM8, R3}},
+    {"cmp4.eq.or.andcm", A2, OpX2TaC   (0xe, 3, 1, 0), {P1, P2, IMM8, R3}},
+    {"cmp4.ne.and.orcm", A2, OpX2TaC   (0xe, 3, 1, 0), {P2, P1, IMM8, R3}, PSEUDO},
+    {"cmp4.ne.or.andcm", A2, OpX2TaC   (0xe, 3, 1, 1), {P1, P2, IMM8, R3}},
+    {"cmp4.eq.and.orcm", A2, OpX2TaC   (0xe, 3, 1, 1), {P2, P1, IMM8, R3}, PSEUDO},
+
+    {0}
+  };
+
+#undef A
+#undef A2
+#undef bC
+#undef bImm14
+#undef bR3a
+#undef bR3b
+#undef bTa
+#undef bTb
+#undef bVe
+#undef bX
+#undef bX2
+#undef bX2a
+#undef bX2b
+#undef bX4
+#undef bZa
+#undef bZb
+#undef mC
+#undef mImm14
+#undef mR3a
+#undef mR3b
+#undef mTa
+#undef mTb
+#undef mVe
+#undef mX
+#undef mX2
+#undef mX2a
+#undef mX2b
+#undef mX4
+#undef mZa
+#undef mZb
+#undef OpR3a
+#undef OpR3b
+#undef OpX2aVe
+#undef OpX2aVeImm14
+#undef OpX2aVeX4
+#undef OpX2aVeX4X2b
+#undef OpX2TbTaC
+#undef OpX2TaC
+#undef OpX2aZaZbX4
+#undef OpX2aZaZbX4X2b
diff --git a/opcodes/ia64-opc-b.c b/opcodes/ia64-opc-b.c
new file mode 100644
index 0000000..5277663
--- /dev/null
+++ b/opcodes/ia64-opc-b.c
@@ -0,0 +1,486 @@
+/* ia64-opc-b.c -- IA-64 `B' opcode table.
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the
+   Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
+
+#include "ia64-opc.h"
+
+#define B0	IA64_TYPE_B, 0
+#define B	IA64_TYPE_B, 1
+
+/* instruction bit fields: */
+#define bBtype(x)	(((ia64_insn) ((x) & 0x7)) << 6)
+#define bD(x)		(((ia64_insn) ((x) & 0x1)) << 35)
+#define bIh(x)		(((ia64_insn) ((x) & 0x1)) << 35)
+#define bPa(x)		(((ia64_insn) ((x) & 0x1)) << 12)
+#define bPr(x)		(((ia64_insn) ((x) & 0x3f)) << 0)
+#define bWha(x)		(((ia64_insn) ((x) & 0x3)) << 33)
+#define bWhb(x)		(((ia64_insn) ((x) & 0x3)) << 3)
+#define bX6(x)		(((ia64_insn) ((x) & 0x3f)) << 27)
+
+#define mBtype		bBtype (-1)
+#define mD		bD (-1)
+#define mIh		bIh (-1)
+#define mPa		bPa (-1)
+#define mPr		bPr (-1)
+#define mWha		bWha (-1)
+#define mWhb		bWhb (-1)
+#define mX6		bX6 (-1)
+
+#define OpX6(a,b) 	(bOp (a) | bX6 (b)), (mOp | mX6)
+#define OpPaWhaD(a,b,c,d) \
+	(bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD)
+#define OpBtypePaWhaD(a,b,c,d,e) \
+	(bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \
+	(mOp | mBtype | mPa | mWha | mD)
+#define OpBtypePaWhaDPr(a,b,c,d,e,f) \
+	(bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \
+	(mOp | mBtype | mPa | mWha | mD | mPr)
+#define OpX6BtypePaWhaD(a,b,c,d,e,f) \
+	(bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f)), \
+	(mOp | mX6 | mBtype | mPa | mWha | mD)
+#define OpX6BtypePaWhaDPr(a,b,c,d,e,f,g) \
+   (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f) | bPr (g)), \
+	(mOp | mX6 | mBtype | mPa | mWha | mD | mPr)
+#define OpIhWhb(a,b,c) \
+	(bOp (a) | bIh (b) | bWhb (c)), \
+	(mOp | mIh | mWhb)
+#define OpX6IhWhb(a,b,c,d) \
+	(bOp (a) | bX6 (b) | bIh (c) | bWhb (d)), \
+	(mOp | mX6 | mIh | mWhb)
+
+struct ia64_opcode ia64_opcodes_b[] =
+  {
+    /* B-type instruction encodings (sorted according to major opcode) */
+
+#define BR(a,b) \
+      B0, OpX6BtypePaWhaDPr (0, 0x20, 0, a, 0, b, 0), {B2}, PSEUDO
+    {"br.few",		BR (0, 0)},
+    {"br",		BR (0, 0)},
+    {"br.few.clr",	BR (0, 1)},
+    {"br.clr",		BR (0, 1)},
+    {"br.many",		BR (1, 0)},
+    {"br.many.clr",	BR (1, 1)},
+#undef BR
+
+#define BR(a,b,c,d,e)	B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}
+    {"br.cond.sptk.few",	BR (0x20, 0, 0, 0, 0)},
+    {"br.cond.sptk",		BR (0x20, 0, 0, 0, 0), PSEUDO},
+    {"br.cond.sptk.few.clr",	BR (0x20, 0, 0, 0, 1)},
+    {"br.cond.sptk.clr",	BR (0x20, 0, 0, 0, 1), PSEUDO},
+    {"br.cond.spnt.few",	BR (0x20, 0, 0, 1, 0)},
+    {"br.cond.spnt",		BR (0x20, 0, 0, 1, 0), PSEUDO},
+    {"br.cond.spnt.few.clr",	BR (0x20, 0, 0, 1, 1)},
+    {"br.cond.spnt.clr",	BR (0x20, 0, 0, 1, 1), PSEUDO},
+    {"br.cond.dptk.few",	BR (0x20, 0, 0, 2, 0)},
+    {"br.cond.dptk",		BR (0x20, 0, 0, 2, 0), PSEUDO},
+    {"br.cond.dptk.few.clr",	BR (0x20, 0, 0, 2, 1)},
+    {"br.cond.dptk.clr",	BR (0x20, 0, 0, 2, 1), PSEUDO},
+    {"br.cond.dpnt.few",	BR (0x20, 0, 0, 3, 0)},
+    {"br.cond.dpnt",		BR (0x20, 0, 0, 3, 0), PSEUDO},
+    {"br.cond.dpnt.few.clr",	BR (0x20, 0, 0, 3, 1)},
+    {"br.cond.dpnt.clr",	BR (0x20, 0, 0, 3, 1), PSEUDO},
+    {"br.cond.sptk.many",	BR (0x20, 0, 1, 0, 0)},
+    {"br.cond.sptk.many.clr",	BR (0x20, 0, 1, 0, 1)},
+    {"br.cond.spnt.many",	BR (0x20, 0, 1, 1, 0)},
+    {"br.cond.spnt.many.clr",	BR (0x20, 0, 1, 1, 1)},
+    {"br.cond.dptk.many",	BR (0x20, 0, 1, 2, 0)},
+    {"br.cond.dptk.many.clr",	BR (0x20, 0, 1, 2, 1)},
+    {"br.cond.dpnt.many",	BR (0x20, 0, 1, 3, 0)},
+    {"br.cond.dpnt.many.clr",	BR (0x20, 0, 1, 3, 1)},
+    {"br.sptk.few",		BR (0x20, 0, 0, 0, 0)},
+    {"br.sptk",			BR (0x20, 0, 0, 0, 0), PSEUDO},
+    {"br.sptk.few.clr",		BR (0x20, 0, 0, 0, 1)},
+    {"br.sptk.clr",		BR (0x20, 0, 0, 0, 1), PSEUDO},
+    {"br.spnt.few",		BR (0x20, 0, 0, 1, 0)},
+    {"br.spnt",			BR (0x20, 0, 0, 1, 0), PSEUDO},
+    {"br.spnt.few.clr",		BR (0x20, 0, 0, 1, 1)},
+    {"br.spnt.clr",		BR (0x20, 0, 0, 1, 1), PSEUDO},
+    {"br.dptk.few",		BR (0x20, 0, 0, 2, 0)},
+    {"br.dptk",			BR (0x20, 0, 0, 2, 0), PSEUDO},
+    {"br.dptk.few.clr",		BR (0x20, 0, 0, 2, 1)},
+    {"br.dptk.clr",		BR (0x20, 0, 0, 2, 1), PSEUDO},
+    {"br.dpnt.few",		BR (0x20, 0, 0, 3, 0)},
+    {"br.dpnt",			BR (0x20, 0, 0, 3, 0), PSEUDO},
+    {"br.dpnt.few.clr",		BR (0x20, 0, 0, 3, 1)},
+    {"br.dpnt.clr",		BR (0x20, 0, 0, 3, 1), PSEUDO},
+    {"br.sptk.many",		BR (0x20, 0, 1, 0, 0)},
+    {"br.sptk.many.clr",	BR (0x20, 0, 1, 0, 1)},
+    {"br.spnt.many",		BR (0x20, 0, 1, 1, 0)},
+    {"br.spnt.many.clr",	BR (0x20, 0, 1, 1, 1)},
+    {"br.dptk.many",		BR (0x20, 0, 1, 2, 0)},
+    {"br.dptk.many.clr",	BR (0x20, 0, 1, 2, 1)},
+    {"br.dpnt.many",		BR (0x20, 0, 1, 3, 0)},
+    {"br.dpnt.many.clr",	BR (0x20, 0, 1, 3, 1)},
+    {"br.ia.sptk.few",		BR (0x20, 1, 0, 0, 0)},
+    {"br.ia.sptk",		BR (0x20, 1, 0, 0, 0), PSEUDO},
+    {"br.ia.sptk.few.clr",	BR (0x20, 1, 0, 0, 1)},
+    {"br.ia.sptk.clr",		BR (0x20, 1, 0, 0, 1), PSEUDO},
+    {"br.ia.spnt.few",		BR (0x20, 1, 0, 1, 0)},
+    {"br.ia.spnt",		BR (0x20, 1, 0, 1, 0), PSEUDO},
+    {"br.ia.spnt.few.clr",	BR (0x20, 1, 0, 1, 1)},
+    {"br.ia.spnt.clr",		BR (0x20, 1, 0, 1, 1), PSEUDO},
+    {"br.ia.dptk.few",		BR (0x20, 1, 0, 2, 0)},
+    {"br.ia.dptk",		BR (0x20, 1, 0, 2, 0), PSEUDO},
+    {"br.ia.dptk.few.clr",	BR (0x20, 1, 0, 2, 1)},
+    {"br.ia.dptk.clr",		BR (0x20, 1, 0, 2, 1), PSEUDO},
+    {"br.ia.dpnt.few",		BR (0x20, 1, 0, 3, 0)},
+    {"br.ia.dpnt",		BR (0x20, 1, 0, 3, 0), PSEUDO},
+    {"br.ia.dpnt.few.clr",	BR (0x20, 1, 0, 3, 1)},
+    {"br.ia.dpnt.clr",		BR (0x20, 1, 0, 3, 1), PSEUDO},
+    {"br.ia.sptk.many",		BR (0x20, 1, 1, 0, 0)},
+    {"br.ia.sptk.many.clr",	BR (0x20, 1, 1, 0, 1)},
+    {"br.ia.spnt.many",		BR (0x20, 1, 1, 1, 0)},
+    {"br.ia.spnt.many.clr",	BR (0x20, 1, 1, 1, 1)},
+    {"br.ia.dptk.many",		BR (0x20, 1, 1, 2, 0)},
+    {"br.ia.dptk.many.clr",	BR (0x20, 1, 1, 2, 1)},
+    {"br.ia.dpnt.many",		BR (0x20, 1, 1, 3, 0)},
+    {"br.ia.dpnt.many.clr",	BR (0x20, 1, 1, 3, 1)},
+    {"br.ret.sptk.few",		BR (0x21, 4, 0, 0, 0), MOD_RRBS},
+    {"br.ret.sptk",		BR (0x21, 4, 0, 0, 0), PSEUDO | MOD_RRBS},
+    {"br.ret.sptk.few.clr",	BR (0x21, 4, 0, 0, 1), MOD_RRBS},
+    {"br.ret.sptk.clr",		BR (0x21, 4, 0, 0, 1), PSEUDO | MOD_RRBS},
+    {"br.ret.spnt.few",		BR (0x21, 4, 0, 1, 0), MOD_RRBS},
+    {"br.ret.spnt",		BR (0x21, 4, 0, 1, 0), PSEUDO | MOD_RRBS},
+    {"br.ret.spnt.few.clr",	BR (0x21, 4, 0, 1, 1), MOD_RRBS},
+    {"br.ret.spnt.clr",		BR (0x21, 4, 0, 1, 1), PSEUDO | MOD_RRBS},
+    {"br.ret.dptk.few",		BR (0x21, 4, 0, 2, 0), MOD_RRBS},
+    {"br.ret.dptk",		BR (0x21, 4, 0, 2, 0), PSEUDO | MOD_RRBS},
+    {"br.ret.dptk.few.clr",	BR (0x21, 4, 0, 2, 1), MOD_RRBS},
+    {"br.ret.dptk.clr",		BR (0x21, 4, 0, 2, 1), PSEUDO | MOD_RRBS},
+    {"br.ret.dpnt.few",		BR (0x21, 4, 0, 3, 0), MOD_RRBS},
+    {"br.ret.dpnt",		BR (0x21, 4, 0, 3, 0), PSEUDO | MOD_RRBS},
+    {"br.ret.dpnt.few.clr",	BR (0x21, 4, 0, 3, 1), MOD_RRBS},
+    {"br.ret.dpnt.clr",		BR (0x21, 4, 0, 3, 1), PSEUDO | MOD_RRBS},
+    {"br.ret.sptk.many",	BR (0x21, 4, 1, 0, 0), MOD_RRBS},
+    {"br.ret.sptk.many.clr",	BR (0x21, 4, 1, 0, 1), MOD_RRBS},
+    {"br.ret.spnt.many",	BR (0x21, 4, 1, 1, 0), MOD_RRBS},
+    {"br.ret.spnt.many.clr",	BR (0x21, 4, 1, 1, 1), MOD_RRBS},
+    {"br.ret.dptk.many",	BR (0x21, 4, 1, 2, 0), MOD_RRBS},
+    {"br.ret.dptk.many.clr",	BR (0x21, 4, 1, 2, 1), MOD_RRBS},
+    {"br.ret.dpnt.many",	BR (0x21, 4, 1, 3, 0), MOD_RRBS},
+    {"br.ret.dpnt.many.clr",	BR (0x21, 4, 1, 3, 1), MOD_RRBS},
+#undef BR
+
+    {"cover",		B0, OpX6 (0, 0x02), {0, }, NO_PRED | LAST | MOD_RRBS},
+    {"clrrrb",		B0, OpX6 (0, 0x04), {0, }, NO_PRED | LAST | MOD_RRBS},
+    {"clrrrb.pr",	B0, OpX6 (0, 0x05), {0, }, NO_PRED | LAST | MOD_RRBS},
+    {"rfi",		B0, OpX6 (0, 0x08), {0, }, NO_PRED | LAST | PRIV | MOD_RRBS},
+    {"bsw.0",		B0, OpX6 (0, 0x0c), {0, }, NO_PRED | LAST | PRIV},
+    {"bsw.1",		B0, OpX6 (0, 0x0d), {0, }, NO_PRED | LAST | PRIV},
+    {"epc",		B0, OpX6 (0, 0x10), {0, }, NO_PRED},
+
+    {"break.b",		B0, OpX6 (0, 0x00), {IMMU21}},
+
+    {"br.call.sptk.few",	B, OpPaWhaD (1, 0, 0, 0), {B1, B2}},
+    {"br.call.sptk",		B, OpPaWhaD (1, 0, 0, 0), {B1, B2}, PSEUDO},
+    {"br.call.sptk.few.clr",	B, OpPaWhaD (1, 0, 0, 1), {B1, B2}},
+    {"br.call.sptk.clr",	B, OpPaWhaD (1, 0, 0, 1), {B1, B2}, PSEUDO},
+    {"br.call.spnt.few",	B, OpPaWhaD (1, 0, 1, 0), {B1, B2}},
+    {"br.call.spnt",		B, OpPaWhaD (1, 0, 1, 0), {B1, B2}, PSEUDO},
+    {"br.call.spnt.few.clr",	B, OpPaWhaD (1, 0, 1, 1), {B1, B2}},
+    {"br.call.spnt.clr",	B, OpPaWhaD (1, 0, 1, 1), {B1, B2}, PSEUDO},
+    {"br.call.dptk.few",	B, OpPaWhaD (1, 0, 2, 0), {B1, B2}},
+    {"br.call.dptk",		B, OpPaWhaD (1, 0, 2, 0), {B1, B2}, PSEUDO},
+    {"br.call.dptk.few.clr",	B, OpPaWhaD (1, 0, 2, 1), {B1, B2}},
+    {"br.call.dptk.clr",	B, OpPaWhaD (1, 0, 2, 1), {B1, B2}, PSEUDO},
+    {"br.call.dpnt.few",	B, OpPaWhaD (1, 0, 3, 0), {B1, B2}},
+    {"br.call.dpnt",		B, OpPaWhaD (1, 0, 3, 0), {B1, B2}, PSEUDO},
+    {"br.call.dpnt.few.clr",	B, OpPaWhaD (1, 0, 3, 1), {B1, B2}},
+    {"br.call.dpnt.clr",	B, OpPaWhaD (1, 0, 3, 1), {B1, B2}, PSEUDO},
+    {"br.call.sptk.many",	B, OpPaWhaD (1, 1, 0, 0), {B1, B2}},
+    {"br.call.sptk.many.clr",	B, OpPaWhaD (1, 1, 0, 1), {B1, B2}},
+    {"br.call.spnt.many",	B, OpPaWhaD (1, 1, 1, 0), {B1, B2}},
+    {"br.call.spnt.many.clr",	B, OpPaWhaD (1, 1, 1, 1), {B1, B2}},
+    {"br.call.dptk.many",	B, OpPaWhaD (1, 1, 2, 0), {B1, B2}},
+    {"br.call.dptk.many.clr",	B, OpPaWhaD (1, 1, 2, 1), {B1, B2}},
+    {"br.call.dpnt.many",	B, OpPaWhaD (1, 1, 3, 0), {B1, B2}},
+    {"br.call.dpnt.many.clr",	B, OpPaWhaD (1, 1, 3, 1), {B1, B2}},
+
+#define BRP(a,b,c) \
+      B0, OpX6IhWhb (2, a, b, c), {B2, TAG13}, NO_PRED
+    {"brp.sptk",		BRP (0x10, 0, 0)},
+    {"brp.dptk",		BRP (0x10, 0, 2)},
+    {"brp.sptk.imp",		BRP (0x10, 1, 0)},
+    {"brp.dptk.imp",		BRP (0x10, 1, 2)},
+    {"brp.ret.sptk",		BRP (0x11, 0, 0)},
+    {"brp.ret.dptk",		BRP (0x11, 0, 2)},
+    {"brp.ret.sptk.imp",	BRP (0x11, 1, 0)},
+    {"brp.ret.dptk.imp",	BRP (0x11, 1, 2)},
+#undef BRP
+
+    {"nop.b",		B0, OpX6 (2, 0x00), {IMMU21}},
+
+#define BR(a,b) \
+      B0, OpBtypePaWhaDPr (4, 0, a, 0, b, 0), {TGT25c}, PSEUDO
+    {"br.few",		BR (0, 0)},
+    {"br",		BR (0, 0)},
+    {"br.few.clr",	BR (0, 1)},
+    {"br.clr",		BR (0, 1)},
+    {"br.many",		BR (1, 0)},
+    {"br.many.clr",	BR (1, 1)},
+#undef BR
+
+    {"br.cond.sptk.few",	B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}},
+    {"br.cond.sptk",		B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}, PSEUDO},
+    {"br.cond.sptk.few.clr",	B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}},
+    {"br.cond.sptk.clr",	B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}, PSEUDO},
+    {"br.cond.spnt.few",	B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}},
+    {"br.cond.spnt",		B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}, PSEUDO},
+    {"br.cond.spnt.few.clr",	B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}},
+    {"br.cond.spnt.clr",	B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}, PSEUDO},
+    {"br.cond.dptk.few",	B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}},
+    {"br.cond.dptk",		B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}, PSEUDO},
+    {"br.cond.dptk.few.clr",	B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}},
+    {"br.cond.dptk.clr",	B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}, PSEUDO},
+    {"br.cond.dpnt.few",	B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}},
+    {"br.cond.dpnt",		B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}, PSEUDO},
+    {"br.cond.dpnt.few.clr",	B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}},
+    {"br.cond.dpnt.clr",	B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}, PSEUDO},
+    {"br.cond.sptk.many",	B0, OpBtypePaWhaD (4, 0, 1, 0, 0), {TGT25c}},
+    {"br.cond.sptk.many.clr",	B0, OpBtypePaWhaD (4, 0, 1, 0, 1), {TGT25c}},
+    {"br.cond.spnt.many",	B0, OpBtypePaWhaD (4, 0, 1, 1, 0), {TGT25c}},
+    {"br.cond.spnt.many.clr",	B0, OpBtypePaWhaD (4, 0, 1, 1, 1), {TGT25c}},
+    {"br.cond.dptk.many",	B0, OpBtypePaWhaD (4, 0, 1, 2, 0), {TGT25c}},
+    {"br.cond.dptk.many.clr",	B0, OpBtypePaWhaD (4, 0, 1, 2, 1), {TGT25c}},
+    {"br.cond.dpnt.many",	B0, OpBtypePaWhaD (4, 0, 1, 3, 0), {TGT25c}},
+    {"br.cond.dpnt.many.clr",	B0, OpBtypePaWhaD (4, 0, 1, 3, 1), {TGT25c}},
+    {"br.sptk.few",		B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}},
+    {"br.sptk",			B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}, PSEUDO},
+    {"br.sptk.few.clr",		B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}},
+    {"br.sptk.clr",		B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}, PSEUDO},
+    {"br.spnt.few",		B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}},
+    {"br.spnt",			B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}, PSEUDO},
+    {"br.spnt.few.clr",		B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}},
+    {"br.spnt.clr",		B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}, PSEUDO},
+    {"br.dptk.few",		B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}},
+    {"br.dptk",			B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}, PSEUDO},
+    {"br.dptk.few.clr",		B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}},
+    {"br.dptk.clr",		B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}, PSEUDO},
+    {"br.dpnt.few",		B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}},
+    {"br.dpnt",			B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}, PSEUDO},
+    {"br.dpnt.few.clr",		B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}},
+    {"br.dpnt.clr",		B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}, PSEUDO},
+    {"br.sptk.many",		B0, OpBtypePaWhaD (4, 0, 1, 0, 0), {TGT25c}},
+    {"br.sptk.many.clr",	B0, OpBtypePaWhaD (4, 0, 1, 0, 1), {TGT25c}},
+    {"br.spnt.many",		B0, OpBtypePaWhaD (4, 0, 1, 1, 0), {TGT25c}},
+    {"br.spnt.many.clr",	B0, OpBtypePaWhaD (4, 0, 1, 1, 1), {TGT25c}},
+    {"br.dptk.many",		B0, OpBtypePaWhaD (4, 0, 1, 2, 0), {TGT25c}},
+    {"br.dptk.many.clr",	B0, OpBtypePaWhaD (4, 0, 1, 2, 1), {TGT25c}},
+    {"br.dpnt.many",		B0, OpBtypePaWhaD (4, 0, 1, 3, 0), {TGT25c}},
+    {"br.dpnt.many.clr",	B0, OpBtypePaWhaD (4, 0, 1, 3, 1), {TGT25c}},
+
+#define BR(a,b,c,d) \
+	B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2
+    {"br.wexit.sptk.few",	BR (2, 0, 0, 0) | MOD_RRBS},
+    {"br.wexit.sptk",		BR (2, 0, 0, 0) | PSEUDO | MOD_RRBS},
+    {"br.wexit.sptk.few.clr",	BR (2, 0, 0, 1) | MOD_RRBS},
+    {"br.wexit.sptk.clr",	BR (2, 0, 0, 1) | PSEUDO | MOD_RRBS},
+    {"br.wexit.spnt.few",	BR (2, 0, 1, 0) | MOD_RRBS},
+    {"br.wexit.spnt",		BR (2, 0, 1, 0) | PSEUDO | MOD_RRBS},
+    {"br.wexit.spnt.few.clr",	BR (2, 0, 1, 1) | MOD_RRBS},
+    {"br.wexit.spnt.clr",	BR (2, 0, 1, 1) | PSEUDO | MOD_RRBS},
+    {"br.wexit.dptk.few",	BR (2, 0, 2, 0) | MOD_RRBS},
+    {"br.wexit.dptk",		BR (2, 0, 2, 0) | PSEUDO | MOD_RRBS},
+    {"br.wexit.dptk.few.clr",	BR (2, 0, 2, 1) | MOD_RRBS},
+    {"br.wexit.dptk.clr",	BR (2, 0, 2, 1) | PSEUDO | MOD_RRBS},
+    {"br.wexit.dpnt.few",	BR (2, 0, 3, 0) | MOD_RRBS},
+    {"br.wexit.dpnt",		BR (2, 0, 3, 0) | PSEUDO | MOD_RRBS},
+    {"br.wexit.dpnt.few.clr",	BR (2, 0, 3, 1) | MOD_RRBS},
+    {"br.wexit.dpnt.clr",	BR (2, 0, 3, 1) | PSEUDO | MOD_RRBS},
+    {"br.wexit.sptk.many",	BR (2, 1, 0, 0) | MOD_RRBS},
+    {"br.wexit.sptk.many.clr",	BR (2, 1, 0, 1) | MOD_RRBS},
+    {"br.wexit.spnt.many",	BR (2, 1, 1, 0) | MOD_RRBS},
+    {"br.wexit.spnt.many.clr",	BR (2, 1, 1, 1) | MOD_RRBS},
+    {"br.wexit.dptk.many",	BR (2, 1, 2, 0) | MOD_RRBS},
+    {"br.wexit.dptk.many.clr",	BR (2, 1, 2, 1) | MOD_RRBS},
+    {"br.wexit.dpnt.many",	BR (2, 1, 3, 0) | MOD_RRBS},
+    {"br.wexit.dpnt.many.clr",	BR (2, 1, 3, 1) | MOD_RRBS},
+    {"br.wtop.sptk.few",	BR (3, 0, 0, 0) | MOD_RRBS},
+    {"br.wtop.sptk",		BR (3, 0, 0, 0) | PSEUDO | MOD_RRBS},
+    {"br.wtop.sptk.few.clr",	BR (3, 0, 0, 1) | MOD_RRBS},
+    {"br.wtop.sptk.clr",	BR (3, 0, 0, 1) | PSEUDO | MOD_RRBS},
+    {"br.wtop.spnt.few",	BR (3, 0, 1, 0) | MOD_RRBS},
+    {"br.wtop.spnt",		BR (3, 0, 1, 0) | PSEUDO | MOD_RRBS},
+    {"br.wtop.spnt.few.clr",	BR (3, 0, 1, 1) | MOD_RRBS},
+    {"br.wtop.spnt.clr",	BR (3, 0, 1, 1) | PSEUDO | MOD_RRBS},
+    {"br.wtop.dptk.few",	BR (3, 0, 2, 0) | MOD_RRBS},
+    {"br.wtop.dptk",		BR (3, 0, 2, 0) | PSEUDO | MOD_RRBS},
+    {"br.wtop.dptk.few.clr",	BR (3, 0, 2, 1) | MOD_RRBS},
+    {"br.wtop.dptk.clr",	BR (3, 0, 2, 1) | PSEUDO | MOD_RRBS},
+    {"br.wtop.dpnt.few",	BR (3, 0, 3, 0) | MOD_RRBS},
+    {"br.wtop.dpnt",		BR (3, 0, 3, 0) | PSEUDO | MOD_RRBS},
+    {"br.wtop.dpnt.few.clr",	BR (3, 0, 3, 1) | MOD_RRBS},
+    {"br.wtop.dpnt.clr",	BR (3, 0, 3, 1) | PSEUDO | MOD_RRBS},
+    {"br.wtop.sptk.many",	BR (3, 1, 0, 0) | MOD_RRBS},
+    {"br.wtop.sptk.many.clr",	BR (3, 1, 0, 1) | MOD_RRBS},
+    {"br.wtop.spnt.many",	BR (3, 1, 1, 0) | MOD_RRBS},
+    {"br.wtop.spnt.many.clr",	BR (3, 1, 1, 1) | MOD_RRBS},
+    {"br.wtop.dptk.many",	BR (3, 1, 2, 0) | MOD_RRBS},
+    {"br.wtop.dptk.many.clr",	BR (3, 1, 2, 1) | MOD_RRBS},
+    {"br.wtop.dpnt.many",	BR (3, 1, 3, 0) | MOD_RRBS},
+    {"br.wtop.dpnt.many.clr",	BR (3, 1, 3, 1) | MOD_RRBS},
+
+#undef BR
+#define BR(a,b,c,d) \
+	B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED
+    {"br.cloop.sptk.few",	BR (5, 0, 0, 0)},
+    {"br.cloop.sptk",		BR (5, 0, 0, 0) | PSEUDO},
+    {"br.cloop.sptk.few.clr",	BR (5, 0, 0, 1)},
+    {"br.cloop.sptk.clr",	BR (5, 0, 0, 1) | PSEUDO},
+    {"br.cloop.spnt.few",	BR (5, 0, 1, 0)},
+    {"br.cloop.spnt",		BR (5, 0, 1, 0) | PSEUDO},
+    {"br.cloop.spnt.few.clr",	BR (5, 0, 1, 1)},
+    {"br.cloop.spnt.clr",	BR (5, 0, 1, 1) | PSEUDO},
+    {"br.cloop.dptk.few",	BR (5, 0, 2, 0)},
+    {"br.cloop.dptk",		BR (5, 0, 2, 0) | PSEUDO},
+    {"br.cloop.dptk.few.clr",	BR (5, 0, 2, 1)},
+    {"br.cloop.dptk.clr",	BR (5, 0, 2, 1) | PSEUDO},
+    {"br.cloop.dpnt.few",	BR (5, 0, 3, 0)},
+    {"br.cloop.dpnt",		BR (5, 0, 3, 0) | PSEUDO},
+    {"br.cloop.dpnt.few.clr",	BR (5, 0, 3, 1)},
+    {"br.cloop.dpnt.clr",	BR (5, 0, 3, 1) | PSEUDO},
+    {"br.cloop.sptk.many",	BR (5, 1, 0, 0)},
+    {"br.cloop.sptk.many.clr",	BR (5, 1, 0, 1)},
+    {"br.cloop.spnt.many",	BR (5, 1, 1, 0)},
+    {"br.cloop.spnt.many.clr",	BR (5, 1, 1, 1)},
+    {"br.cloop.dptk.many",	BR (5, 1, 2, 0)},
+    {"br.cloop.dptk.many.clr",	BR (5, 1, 2, 1)},
+    {"br.cloop.dpnt.many",	BR (5, 1, 3, 0)},
+    {"br.cloop.dpnt.many.clr",	BR (5, 1, 3, 1)},
+    {"br.cexit.sptk.few",	BR (6, 0, 0, 0) | MOD_RRBS},
+    {"br.cexit.sptk",		BR (6, 0, 0, 0) | PSEUDO | MOD_RRBS},
+    {"br.cexit.sptk.few.clr",	BR (6, 0, 0, 1) | MOD_RRBS},
+    {"br.cexit.sptk.clr",	BR (6, 0, 0, 1) | PSEUDO | MOD_RRBS},
+    {"br.cexit.spnt.few",	BR (6, 0, 1, 0) | MOD_RRBS},
+    {"br.cexit.spnt",		BR (6, 0, 1, 0) | PSEUDO | MOD_RRBS},
+    {"br.cexit.spnt.few.clr",	BR (6, 0, 1, 1) | MOD_RRBS},
+    {"br.cexit.spnt.clr",	BR (6, 0, 1, 1) | PSEUDO | MOD_RRBS},
+    {"br.cexit.dptk.few",	BR (6, 0, 2, 0) | MOD_RRBS},
+    {"br.cexit.dptk",		BR (6, 0, 2, 0) | PSEUDO | MOD_RRBS},
+    {"br.cexit.dptk.few.clr",	BR (6, 0, 2, 1) | MOD_RRBS},
+    {"br.cexit.dptk.clr",	BR (6, 0, 2, 1) | PSEUDO | MOD_RRBS},
+    {"br.cexit.dpnt.few",	BR (6, 0, 3, 0) | MOD_RRBS},
+    {"br.cexit.dpnt",		BR (6, 0, 3, 0) | PSEUDO | MOD_RRBS},
+    {"br.cexit.dpnt.few.clr",	BR (6, 0, 3, 1) | MOD_RRBS},
+    {"br.cexit.dpnt.clr",	BR (6, 0, 3, 1) | PSEUDO | MOD_RRBS},
+    {"br.cexit.sptk.many",	BR (6, 1, 0, 0) | MOD_RRBS},
+    {"br.cexit.sptk.many.clr",	BR (6, 1, 0, 1) | MOD_RRBS},
+    {"br.cexit.spnt.many",	BR (6, 1, 1, 0) | MOD_RRBS},
+    {"br.cexit.spnt.many.clr",	BR (6, 1, 1, 1) | MOD_RRBS},
+    {"br.cexit.dptk.many",	BR (6, 1, 2, 0) | MOD_RRBS},
+    {"br.cexit.dptk.many.clr",	BR (6, 1, 2, 1) | MOD_RRBS},
+    {"br.cexit.dpnt.many",	BR (6, 1, 3, 0) | MOD_RRBS},
+    {"br.cexit.dpnt.many.clr",	BR (6, 1, 3, 1) | MOD_RRBS},
+    {"br.ctop.sptk.few",	BR (7, 0, 0, 0) | MOD_RRBS},
+    {"br.ctop.sptk",		BR (7, 0, 0, 0) | PSEUDO | MOD_RRBS},
+    {"br.ctop.sptk.few.clr",	BR (7, 0, 0, 1) | MOD_RRBS},
+    {"br.ctop.sptk.clr",	BR (7, 0, 0, 1) | PSEUDO | MOD_RRBS},
+    {"br.ctop.spnt.few",	BR (7, 0, 1, 0) | MOD_RRBS},
+    {"br.ctop.spnt",		BR (7, 0, 1, 0) | PSEUDO | MOD_RRBS},
+    {"br.ctop.spnt.few.clr",	BR (7, 0, 1, 1) | MOD_RRBS},
+    {"br.ctop.spnt.clr",	BR (7, 0, 1, 1) | PSEUDO | MOD_RRBS},
+    {"br.ctop.dptk.few",	BR (7, 0, 2, 0) | MOD_RRBS},
+    {"br.ctop.dptk",		BR (7, 0, 2, 0) | PSEUDO | MOD_RRBS},
+    {"br.ctop.dptk.few.clr",	BR (7, 0, 2, 1) | MOD_RRBS},
+    {"br.ctop.dptk.clr",	BR (7, 0, 2, 1) | PSEUDO | MOD_RRBS},
+    {"br.ctop.dpnt.few",	BR (7, 0, 3, 0) | MOD_RRBS},
+    {"br.ctop.dpnt",		BR (7, 0, 3, 0) | PSEUDO | MOD_RRBS},
+    {"br.ctop.dpnt.few.clr",	BR (7, 0, 3, 1) | MOD_RRBS},
+    {"br.ctop.dpnt.clr",	BR (7, 0, 3, 1) | PSEUDO | MOD_RRBS},
+    {"br.ctop.sptk.many",	BR (7, 1, 0, 0) | MOD_RRBS},
+    {"br.ctop.sptk.many.clr",	BR (7, 1, 0, 1) | MOD_RRBS},
+    {"br.ctop.spnt.many",	BR (7, 1, 1, 0) | MOD_RRBS},
+    {"br.ctop.spnt.many.clr",	BR (7, 1, 1, 1) | MOD_RRBS},
+    {"br.ctop.dptk.many",	BR (7, 1, 2, 0) | MOD_RRBS},
+    {"br.ctop.dptk.many.clr",	BR (7, 1, 2, 1) | MOD_RRBS},
+    {"br.ctop.dpnt.many",	BR (7, 1, 3, 0) | MOD_RRBS},
+    {"br.ctop.dpnt.many.clr",	BR (7, 1, 3, 1) | MOD_RRBS},
+
+#undef BR
+#define BR(a,b,c,d) \
+	B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2
+    {"br.call.sptk.few",	B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}},
+    {"br.call.sptk",		B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, PSEUDO},
+    {"br.call.sptk.few.clr",	B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}},
+    {"br.call.sptk.clr",	B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, PSEUDO},
+    {"br.call.spnt.few",	B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}},
+    {"br.call.spnt",		B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, PSEUDO},
+    {"br.call.spnt.few.clr",	B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}},
+    {"br.call.spnt.clr",	B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, PSEUDO},
+    {"br.call.dptk.few",	B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}},
+    {"br.call.dptk",		B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, PSEUDO},
+    {"br.call.dptk.few.clr",	B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}},
+    {"br.call.dptk.clr",	B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, PSEUDO},
+    {"br.call.dpnt.few",	B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}},
+    {"br.call.dpnt",		B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, PSEUDO},
+    {"br.call.dpnt.few.clr",	B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}},
+    {"br.call.dpnt.clr",	B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, PSEUDO},
+    {"br.call.sptk.many",	B, OpPaWhaD (5, 1, 0, 0), {B1, TGT25c}},
+    {"br.call.sptk.many.clr",	B, OpPaWhaD (5, 1, 0, 1), {B1, TGT25c}},
+    {"br.call.spnt.many",	B, OpPaWhaD (5, 1, 1, 0), {B1, TGT25c}},
+    {"br.call.spnt.many.clr",	B, OpPaWhaD (5, 1, 1, 1), {B1, TGT25c}},
+    {"br.call.dptk.many",	B, OpPaWhaD (5, 1, 2, 0), {B1, TGT25c}},
+    {"br.call.dptk.many.clr",	B, OpPaWhaD (5, 1, 2, 1), {B1, TGT25c}},
+    {"br.call.dpnt.many",	B, OpPaWhaD (5, 1, 3, 0), {B1, TGT25c}},
+    {"br.call.dpnt.many.clr",	B, OpPaWhaD (5, 1, 3, 1), {B1, TGT25c}},
+#undef BR
+
+    /* branch predict */
+#define BRP(a,b) \
+      B0, OpIhWhb (7, a, b), {TGT25c, TAG13}, NO_PRED
+    {"brp.sptk",		BRP (0, 0)},
+    {"brp.loop",		BRP (0, 1)},
+    {"brp.dptk",		BRP (0, 2)},
+    {"brp.exit",		BRP (0, 3)},
+    {"brp.sptk.imp",		BRP (1, 0)},
+    {"brp.loop.imp",		BRP (1, 1)},
+    {"brp.dptk.imp",		BRP (1, 2)},
+    {"brp.exit.imp",		BRP (1, 3)},
+#undef BRP
+
+    {0}
+  };
+
+#undef B0
+#undef B
+#undef bBtype
+#undef bD
+#undef bIh
+#undef bPa
+#undef bPr
+#undef bWha
+#undef bWhb
+#undef bX6
+#undef mBtype
+#undef mD
+#undef mIh
+#undef mPa
+#undef mPr
+#undef mWha
+#undef mWhb
+#undef mX6
+#undef OpX6
+#undef OpPaWhaD
+#undef OpBtypePaWhaD
+#undef OpBtypePaWhaDPr
+#undef OpX6BtypePaWhaD
+#undef OpX6BtypePaWhaDPr
+#undef OpIhWhb
+#undef OpX6IhWhb
diff --git a/opcodes/ia64-opc-d.c b/opcodes/ia64-opc-d.c
new file mode 100644
index 0000000..6021d3b
--- /dev/null
+++ b/opcodes/ia64-opc-d.c
@@ -0,0 +1,12 @@
+struct ia64_opcode ia64_opcodes_d[] =
+  {
+    {"add",   IA64_TYPE_DYN, 1, 0, 0,
+     {IA64_OPND_R1, IA64_OPND_IMM22, IA64_OPND_R3}},
+    {"break", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}},
+    {"chk.s", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_R2, IA64_OPND_TGT25b}},
+    {"mov",   IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1,  IA64_OPND_AR3}},
+    {"mov",   IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_IMM8}},
+    {"mov",   IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_R2}},
+    {"nop",   IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}},
+    {0}
+  };
diff --git a/opcodes/ia64-opc-f.c b/opcodes/ia64-opc-f.c
new file mode 100644
index 0000000..5b9af51
--- /dev/null
+++ b/opcodes/ia64-opc-f.c
@@ -0,0 +1,625 @@
+/* ia64-opc-f.c -- IA-64 `F' opcode table.
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the
+   Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
+
+#include "ia64-opc.h"
+
+#define f0	IA64_TYPE_F, 0
+#define f	IA64_TYPE_F, 1
+#define f2	IA64_TYPE_F, 2
+
+#define bF2(x)	(((ia64_insn) ((x) & 0x7f)) << 13)
+#define bF4(x)	(((ia64_insn) ((x) & 0x7f)) << 27)
+#define bQ(x)	(((ia64_insn) ((x) & 0x1)) << 36)
+#define bRa(x)	(((ia64_insn) ((x) & 0x1)) << 33)
+#define bRb(x)	(((ia64_insn) ((x) & 0x1)) << 36)
+#define bSf(x)	(((ia64_insn) ((x) & 0x3)) << 34)
+#define bTa(x)	(((ia64_insn) ((x) & 0x1)) << 12)
+#define bXa(x)	(((ia64_insn) ((x) & 0x1)) << 36)
+#define bXb(x)	(((ia64_insn) ((x) & 0x1)) << 33)
+#define bX2(x)	(((ia64_insn) ((x) & 0x3)) << 34)
+#define bX6(x)	(((ia64_insn) ((x) & 0x3f)) << 27)
+
+#define mF2	bF2 (-1)
+#define mF4	bF4 (-1)
+#define mQ	bQ (-1)
+#define mRa	bRa (-1)
+#define mRb	bRb (-1)
+#define mSf	bSf (-1)
+#define mTa	bTa (-1)
+#define mXa	bXa (-1)
+#define mXb	bXb (-1)
+#define mX2	bX2 (-1)
+#define mX6	bX6 (-1)
+
+#define OpXa(a,b)	(bOp (a) | bXa (b)), (mOp | mXa)
+#define OpXaSf(a,b,c)	(bOp (a) | bXa (b) | bSf (c)), (mOp | mXa | mSf)
+#define OpXaSfF2(a,b,c,d) \
+	(bOp (a) | bXa (b) | bSf (c) | bF2 (d)), (mOp | mXa | mSf | mF2)
+#define OpXaSfF4(a,b,c,d) \
+	(bOp (a) | bXa (b) | bSf (c) | bF4 (d)), (mOp | mXa | mSf | mF4)
+#define OpXaSfF2F4(a,b,c,d,e) \
+	(bOp (a) | bXa (b) | bSf (c) | bF2 (d) | bF4 (e)), \
+	(mOp | mXa | mSf | mF2 | mF4)
+#define OpXaX2(a,b,c)	(bOp (a) | bXa (b) | bX2 (c)), (mOp | mXa | mX2)
+#define OpXaX2F2(a,b,c,d) \
+	(bOp (a) | bXa (b) | bX2 (c) | bF2 (d)), (mOp | mXa | mX2 | mF2)
+#define OpRaRbTaSf(a,b,c,d,e) \
+	(bOp (a) | bRa (b) | bRb (c) | bTa (d) | bSf (e)), \
+	(mOp | mRa | mRb | mTa | mSf)
+#define OpTa(a,b)	(bOp (a) | bTa (b)), (mOp | mTa)
+#define OpXbQSf(a,b,c,d) \
+	(bOp (a) | bXb (b) | bQ (c) | bSf (d)), (mOp | mXb | mQ | mSf)
+#define OpXbX6(a,b,c) \
+	(bOp (a) | bXb (b) | bX6 (c)), (mOp | mXb | mX6)
+#define OpXbX6F2(a,b,c,d) \
+	(bOp (a) | bXb (b) | bX6 (c) | bF2 (d)), (mOp | mXb | mX6 | mF2)
+#define OpXbX6Sf(a,b,c,d) \
+	(bOp (a) | bXb (b) | bX6 (c) | bSf (d)), (mOp | mXb | mX6 | mSf)
+
+struct ia64_opcode ia64_opcodes_f[] =
+  {
+    /* F-type instruction encodings (sorted according to major opcode) */
+
+    {"frcpa.s0",	f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}},
+    {"frcpa",		f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO},
+    {"frcpa.s1",	f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}},
+    {"frcpa.s2",	f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}},
+    {"frcpa.s3",	f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}},
+
+    {"frsqrta.s0",	f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}},
+    {"frsqrta",		f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO},
+    {"frsqrta.s1",	f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}},
+    {"frsqrta.s2",	f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}},
+    {"frsqrta.s3",	f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F3}},
+
+    {"fmin.s0",		f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}},
+    {"fmin",		f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, PSEUDO},
+    {"fmin.s1",		f, OpXbX6Sf (0, 0, 0x14, 1), {F1, F2, F3}},
+    {"fmin.s2",		f, OpXbX6Sf (0, 0, 0x14, 2), {F1, F2, F3}},
+    {"fmin.s3",		f, OpXbX6Sf (0, 0, 0x14, 3), {F1, F2, F3}},
+    {"fmax.s0",		f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}},
+    {"fmax",		f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, PSEUDO},
+    {"fmax.s1",		f, OpXbX6Sf (0, 0, 0x15, 1), {F1, F2, F3}},
+    {"fmax.s2",		f, OpXbX6Sf (0, 0, 0x15, 2), {F1, F2, F3}},
+    {"fmax.s3",		f, OpXbX6Sf (0, 0, 0x15, 3), {F1, F2, F3}},
+    {"famin.s0",	f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}},
+    {"famin",		f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, PSEUDO},
+    {"famin.s1",	f, OpXbX6Sf (0, 0, 0x16, 1), {F1, F2, F3}},
+    {"famin.s2",	f, OpXbX6Sf (0, 0, 0x16, 2), {F1, F2, F3}},
+    {"famin.s3",	f, OpXbX6Sf (0, 0, 0x16, 3), {F1, F2, F3}},
+    {"famax.s0",	f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}},
+    {"famax",		f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, PSEUDO},
+    {"famax.s1",	f, OpXbX6Sf (0, 0, 0x17, 1), {F1, F2, F3}},
+    {"famax.s2",	f, OpXbX6Sf (0, 0, 0x17, 2), {F1, F2, F3}},
+    {"famax.s3",	f, OpXbX6Sf (0, 0, 0x17, 3), {F1, F2, F3}},
+
+    {"mov",		f, OpXbX6 (0, 0, 0x10), {F1, F3}, PSEUDO | F2_EQ_F3},
+    {"fabs",		f, OpXbX6F2 (0, 0, 0x10, 0), {F1, F3}, PSEUDO},
+    {"fmerge.s",	f, OpXbX6   (0, 0, 0x10), {F1, F2, F3}},
+    {"fneg",		f, OpXbX6   (0, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3},
+    {"fnegabs",		f, OpXbX6F2 (0, 0, 0x11, 0), {F1, F3}, PSEUDO},
+    {"fmerge.ns",	f, OpXbX6   (0, 0, 0x11), {F1, F2, F3}},
+
+    {"fmerge.se",	f, OpXbX6 (0, 0, 0x12), {F1, F2, F3}},
+    {"fmix.lr",		f, OpXbX6 (0, 0, 0x39), {F1, F2, F3}},
+    {"fmix.r",		f, OpXbX6 (0, 0, 0x3a), {F1, F2, F3}},
+    {"fmix.l",		f, OpXbX6 (0, 0, 0x3b), {F1, F2, F3}},
+    {"fsxt.r",		f, OpXbX6 (0, 0, 0x3c), {F1, F2, F3}},
+    {"fsxt.l",		f, OpXbX6 (0, 0, 0x3d), {F1, F2, F3}},
+    {"fpack",		f, OpXbX6 (0, 0, 0x28), {F1, F2, F3}},
+    {"fswap",		f, OpXbX6 (0, 0, 0x34), {F1, F2, F3}},
+    {"fswap.nl",	f, OpXbX6 (0, 0, 0x35), {F1, F2, F3}},
+    {"fswap.nr",	f, OpXbX6 (0, 0, 0x36), {F1, F2, F3}},
+    {"fand",		f, OpXbX6 (0, 0, 0x2c), {F1, F2, F3}},
+    {"fandcm",		f, OpXbX6 (0, 0, 0x2d), {F1, F2, F3}},
+    {"for",		f, OpXbX6 (0, 0, 0x2e), {F1, F2, F3}},
+    {"fxor",		f, OpXbX6 (0, 0, 0x2f), {F1, F2, F3}},
+
+    {"fcvt.fx.s0",		f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}},
+    {"fcvt.fx",			f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, PSEUDO},
+    {"fcvt.fx.s1",		f, OpXbX6Sf (0, 0, 0x18, 1), {F1, F2}},
+    {"fcvt.fx.s2",		f, OpXbX6Sf (0, 0, 0x18, 2), {F1, F2}},
+    {"fcvt.fx.s3",		f, OpXbX6Sf (0, 0, 0x18, 3), {F1, F2}},
+    {"fcvt.fxu.s0",		f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}},
+    {"fcvt.fxu",		f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, PSEUDO},
+    {"fcvt.fxu.s1",		f, OpXbX6Sf (0, 0, 0x19, 1), {F1, F2}},
+    {"fcvt.fxu.s2",		f, OpXbX6Sf (0, 0, 0x19, 2), {F1, F2}},
+    {"fcvt.fxu.s3",		f, OpXbX6Sf (0, 0, 0x19, 3), {F1, F2}},
+    {"fcvt.fx.trunc.s0",	f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}},
+    {"fcvt.fx.trunc",		f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, PSEUDO},
+    {"fcvt.fx.trunc.s1",	f, OpXbX6Sf (0, 0, 0x1a, 1), {F1, F2}},
+    {"fcvt.fx.trunc.s2",	f, OpXbX6Sf (0, 0, 0x1a, 2), {F1, F2}},
+    {"fcvt.fx.trunc.s3",	f, OpXbX6Sf (0, 0, 0x1a, 3), {F1, F2}},
+    {"fcvt.fxu.trunc.s0",	f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}},
+    {"fcvt.fxu.trunc",		f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, PSEUDO},
+    {"fcvt.fxu.trunc.s1",	f, OpXbX6Sf (0, 0, 0x1b, 1), {F1, F2}},
+    {"fcvt.fxu.trunc.s2",	f, OpXbX6Sf (0, 0, 0x1b, 2), {F1, F2}},
+    {"fcvt.fxu.trunc.s3",	f, OpXbX6Sf (0, 0, 0x1b, 3), {F1, F2}},
+
+    {"fcvt.xf",		f, OpXbX6 (0, 0, 0x1c), {F1, F2}},
+
+    {"fsetc.s0",	f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}},
+    {"fsetc",		f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, PSEUDO},
+    {"fsetc.s1",	f0, OpXbX6Sf (0, 0, 0x04, 1), {IMMU7a, IMMU7b}},
+    {"fsetc.s2",	f0, OpXbX6Sf (0, 0, 0x04, 2), {IMMU7a, IMMU7b}},
+    {"fsetc.s3",	f0, OpXbX6Sf (0, 0, 0x04, 3), {IMMU7a, IMMU7b}},
+    {"fclrf.s0",	f0, OpXbX6Sf (0, 0, 0x05, 0)},
+    {"fclrf",		f0, OpXbX6Sf (0, 0, 0x05, 0), {0}, PSEUDO},
+    {"fclrf.s1",	f0, OpXbX6Sf (0, 0, 0x05, 1)},
+    {"fclrf.s2",	f0, OpXbX6Sf (0, 0, 0x05, 2)},
+    {"fclrf.s3",	f0, OpXbX6Sf (0, 0, 0x05, 3)},
+    {"fchkf.s0",	f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}},
+    {"fchkf",		f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, PSEUDO},
+    {"fchkf.s1",	f0, OpXbX6Sf (0, 0, 0x08, 1), {TGT25}},
+    {"fchkf.s2",	f0, OpXbX6Sf (0, 0, 0x08, 2), {TGT25}},
+    {"fchkf.s3",	f0, OpXbX6Sf (0, 0, 0x08, 3), {TGT25}},
+
+    {"break.f",		f0, OpXbX6 (0, 0, 0x00), {IMMU21}},
+    {"nop.f",		f0, OpXbX6 (0, 0, 0x01), {IMMU21}},
+
+    {"fprcpa.s0",	f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}},
+    {"fprcpa",		f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO},
+    {"fprcpa.s1",	f2, OpXbQSf (1, 1, 0, 1), {F1, P2, F2, F3}},
+    {"fprcpa.s2",	f2, OpXbQSf (1, 1, 0, 2), {F1, P2, F2, F3}},
+    {"fprcpa.s3",	f2, OpXbQSf (1, 1, 0, 3), {F1, P2, F2, F3}},
+
+    {"fprsqrta.s0",	f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}},
+    {"fprsqrta",	f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, PSEUDO},
+    {"fprsqrta.s1",	f2, OpXbQSf (1, 1, 1, 1), {F1, P2, F3}},
+    {"fprsqrta.s2",	f2, OpXbQSf (1, 1, 1, 2), {F1, P2, F3}},
+    {"fprsqrta.s3",	f2, OpXbQSf (1, 1, 1, 3), {F1, P2, F3}},
+
+    {"fpmin.s0",	f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}},
+    {"fpmin",		f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, PSEUDO},
+    {"fpmin.s1",	f, OpXbX6Sf (1, 0, 0x14, 1), {F1, F2, F3}},
+    {"fpmin.s2",	f, OpXbX6Sf (1, 0, 0x14, 2), {F1, F2, F3}},
+    {"fpmin.s3",	f, OpXbX6Sf (1, 0, 0x14, 3), {F1, F2, F3}},
+    {"fpmax.s0",	f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}},
+    {"fpmax",		f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, PSEUDO},
+    {"fpmax.s1",	f, OpXbX6Sf (1, 0, 0x15, 1), {F1, F2, F3}},
+    {"fpmax.s2",	f, OpXbX6Sf (1, 0, 0x15, 2), {F1, F2, F3}},
+    {"fpmax.s3",	f, OpXbX6Sf (1, 0, 0x15, 3), {F1, F2, F3}},
+    {"fpamin.s0",	f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}},
+    {"fpamin",		f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, PSEUDO},
+    {"fpamin.s1",	f, OpXbX6Sf (1, 0, 0x16, 1), {F1, F2, F3}},
+    {"fpamin.s2",	f, OpXbX6Sf (1, 0, 0x16, 2), {F1, F2, F3}},
+    {"fpamin.s3",	f, OpXbX6Sf (1, 0, 0x16, 3), {F1, F2, F3}},
+    {"fpamax.s0",	f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}},
+    {"fpamax",		f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, PSEUDO},
+    {"fpamax.s1",	f, OpXbX6Sf (1, 0, 0x17, 1), {F1, F2, F3}},
+    {"fpamax.s2",	f, OpXbX6Sf (1, 0, 0x17, 2), {F1, F2, F3}},
+    {"fpamax.s3",	f, OpXbX6Sf (1, 0, 0x17, 3), {F1, F2, F3}},
+    {"fpcmp.eq.s0",	f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}},
+    {"fpcmp.eq",	f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, PSEUDO},
+    {"fpcmp.eq.s1",	f, OpXbX6Sf (1, 0, 0x30, 1), {F1, F2, F3}},
+    {"fpcmp.eq.s2",	f, OpXbX6Sf (1, 0, 0x30, 2), {F1, F2, F3}},
+    {"fpcmp.eq.s3",	f, OpXbX6Sf (1, 0, 0x30, 3), {F1, F2, F3}},
+    {"fpcmp.lt.s0",	f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}},
+    {"fpcmp.lt",	f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, PSEUDO},
+    {"fpcmp.lt.s1",	f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F2, F3}},
+    {"fpcmp.lt.s2",	f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F2, F3}},
+    {"fpcmp.lt.s3",	f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F2, F3}},
+    {"fpcmp.le.s0",	f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}},
+    {"fpcmp.le",	f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, PSEUDO},
+    {"fpcmp.le.s1",	f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F2, F3}},
+    {"fpcmp.le.s2",	f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F2, F3}},
+    {"fpcmp.le.s3",	f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F2, F3}},
+    {"fpcmp.unord.s0",	f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}},
+    {"fpcmp.unord",	f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, PSEUDO},
+    {"fpcmp.unord.s1",	f, OpXbX6Sf (1, 0, 0x33, 1), {F1, F2, F3}},
+    {"fpcmp.unord.s2",	f, OpXbX6Sf (1, 0, 0x33, 2), {F1, F2, F3}},
+    {"fpcmp.unord.s3",	f, OpXbX6Sf (1, 0, 0x33, 3), {F1, F2, F3}},
+    {"fpcmp.neq.s0",	f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}},
+    {"fpcmp.neq",	f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, PSEUDO},
+    {"fpcmp.neq.s1",	f, OpXbX6Sf (1, 0, 0x34, 1), {F1, F2, F3}},
+    {"fpcmp.neq.s2",	f, OpXbX6Sf (1, 0, 0x34, 2), {F1, F2, F3}},
+    {"fpcmp.neq.s3",	f, OpXbX6Sf (1, 0, 0x34, 3), {F1, F2, F3}},
+    {"fpcmp.nlt.s0",	f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}},
+    {"fpcmp.nlt",	f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, PSEUDO},
+    {"fpcmp.nlt.s1",	f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F2, F3}},
+    {"fpcmp.nlt.s2",	f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F2, F3}},
+    {"fpcmp.nlt.s3",	f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F2, F3}},
+    {"fpcmp.nle.s0",	f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}},
+    {"fpcmp.nle",	f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, PSEUDO},
+    {"fpcmp.nle.s1",	f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F2, F3}},
+    {"fpcmp.nle.s2",	f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F2, F3}},
+    {"fpcmp.nle.s3",	f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F2, F3}},
+    {"fpcmp.ord.s0",	f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}},
+    {"fpcmp.ord",	f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, PSEUDO},
+    {"fpcmp.ord.s1",	f, OpXbX6Sf (1, 0, 0x37, 1), {F1, F2, F3}},
+    {"fpcmp.ord.s2",	f, OpXbX6Sf (1, 0, 0x37, 2), {F1, F2, F3}},
+    {"fpcmp.ord.s3",	f, OpXbX6Sf (1, 0, 0x37, 3), {F1, F2, F3}},
+
+    {"fpabs",		f, OpXbX6F2 (1, 0, 0x10, 0), {F1, F3}, PSEUDO},
+    {"fpmerge.s",	f, OpXbX6   (1, 0, 0x10), {F1, F2, F3}},
+    {"fpneg",		f, OpXbX6   (1, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3},
+    {"fpnegabs",	f, OpXbX6F2 (1, 0, 0x11, 0), {F1, F3}, PSEUDO},
+    {"fpmerge.ns",	f, OpXbX6   (1, 0, 0x11), {F1, F2, F3}},
+    {"fpmerge.se",	f, OpXbX6 (1, 0, 0x12), {F1, F2, F3}},
+
+    {"fpcvt.fx.s0",		f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}},
+    {"fpcvt.fx",		f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, PSEUDO},
+    {"fpcvt.fx.s1",		f, OpXbX6Sf (1, 0, 0x18, 1), {F1, F2}},
+    {"fpcvt.fx.s2",		f, OpXbX6Sf (1, 0, 0x18, 2), {F1, F2}},
+    {"fpcvt.fx.s3",		f, OpXbX6Sf (1, 0, 0x18, 3), {F1, F2}},
+    {"fpcvt.fxu.s0",		f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}},
+    {"fpcvt.fxu",		f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, PSEUDO},
+    {"fpcvt.fxu.s1",		f, OpXbX6Sf (1, 0, 0x19, 1), {F1, F2}},
+    {"fpcvt.fxu.s2",		f, OpXbX6Sf (1, 0, 0x19, 2), {F1, F2}},
+    {"fpcvt.fxu.s3",		f, OpXbX6Sf (1, 0, 0x19, 3), {F1, F2}},
+    {"fpcvt.fx.trunc.s0",	f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}},
+    {"fpcvt.fx.trunc",		f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, PSEUDO},
+    {"fpcvt.fx.trunc.s1",	f, OpXbX6Sf (1, 0, 0x1a, 1), {F1, F2}},
+    {"fpcvt.fx.trunc.s2",	f, OpXbX6Sf (1, 0, 0x1a, 2), {F1, F2}},
+    {"fpcvt.fx.trunc.s3",	f, OpXbX6Sf (1, 0, 0x1a, 3), {F1, F2}},
+    {"fpcvt.fxu.trunc.s0",	f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}},
+    {"fpcvt.fxu.trunc",		f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, PSEUDO},
+    {"fpcvt.fxu.trunc.s1",	f, OpXbX6Sf (1, 0, 0x1b, 1), {F1, F2}},
+    {"fpcvt.fxu.trunc.s2",	f, OpXbX6Sf (1, 0, 0x1b, 2), {F1, F2}},
+    {"fpcvt.fxu.trunc.s3",	f, OpXbX6Sf (1, 0, 0x1b, 3), {F1, F2}},
+
+    {"fcmp.eq.s0",	  f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}},
+    {"fcmp.eq",		  f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO},
+    {"fcmp.eq.s1",	  f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P1, P2, F2, F3}},
+    {"fcmp.eq.s2",	  f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P1, P2, F2, F3}},
+    {"fcmp.eq.s3",	  f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P1, P2, F2, F3}},
+    {"fcmp.lt.s0",	  f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}},
+    {"fcmp.lt",		  f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO},
+    {"fcmp.lt.s1",	  f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F2, F3}},
+    {"fcmp.lt.s2",	  f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F2, F3}},
+    {"fcmp.lt.s3",	  f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F2, F3}},
+    {"fcmp.le.s0",	  f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}},
+    {"fcmp.le",		  f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO},
+    {"fcmp.le.s1",	  f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F2, F3}},
+    {"fcmp.le.s2",	  f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F2, F3}},
+    {"fcmp.le.s3",	  f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F2, F3}},
+    {"fcmp.unord.s0",	  f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}},
+    {"fcmp.unord",	  f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO},
+    {"fcmp.unord.s1",	  f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P1, P2, F2, F3}},
+    {"fcmp.unord.s2",	  f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P1, P2, F2, F3}},
+    {"fcmp.unord.s3",	  f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P1, P2, F2, F3}},
+    {"fcmp.eq.unc.s0",	  f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}},
+    {"fcmp.eq.unc",	  f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO},
+    {"fcmp.eq.unc.s1",	  f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P1, P2, F2, F3}},
+    {"fcmp.eq.unc.s2",	  f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P1, P2, F2, F3}},
+    {"fcmp.eq.unc.s3",	  f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P1, P2, F2, F3}},
+    {"fcmp.lt.unc.s0",	  f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}},
+    {"fcmp.lt.unc",	  f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO},
+    {"fcmp.lt.unc.s1",	  f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F2, F3}},
+    {"fcmp.lt.unc.s2",	  f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F2, F3}},
+    {"fcmp.lt.unc.s3",	  f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F2, F3}},
+    {"fcmp.le.unc.s0",	  f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}},
+    {"fcmp.le.unc",	  f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO},
+    {"fcmp.le.unc.s1",	  f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F2, F3}},
+    {"fcmp.le.unc.s2",	  f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F2, F3}},
+    {"fcmp.le.unc.s3",	  f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F2, F3}},
+    {"fcmp.unord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}},
+    {"fcmp.unord.unc",    f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO},
+    {"fcmp.unord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P1, P2, F2, F3}},
+    {"fcmp.unord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P1, P2, F2, F3}},
+    {"fcmp.unord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P1, P2, F2, F3}},
+
+    /* pseudo-ops of the above */
+    {"fcmp.gt.s0",	  f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}},
+    {"fcmp.gt",		  f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, PSEUDO},
+    {"fcmp.gt.s1",	  f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F3, F2}},
+    {"fcmp.gt.s2",	  f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F3, F2}},
+    {"fcmp.gt.s3",	  f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F3, F2}},
+    {"fcmp.ge.s0",	  f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}},
+    {"fcmp.ge",		  f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, PSEUDO},
+    {"fcmp.ge.s1",	  f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F3, F2}},
+    {"fcmp.ge.s2",	  f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F3, F2}},
+    {"fcmp.ge.s3",	  f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F3, F2}},
+    {"fcmp.neq.s0",	  f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}},
+    {"fcmp.neq",	  f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO},
+    {"fcmp.neq.s1",	  f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P2, P1, F2, F3}},
+    {"fcmp.neq.s2",	  f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P2, P1, F2, F3}},
+    {"fcmp.neq.s3",	  f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P2, P1, F2, F3}},
+    {"fcmp.nlt.s0",	  f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}},
+    {"fcmp.nlt",	  f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO},
+    {"fcmp.nlt.s1",	  f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F2, F3}},
+    {"fcmp.nlt.s2",	  f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F2, F3}},
+    {"fcmp.nlt.s3",	  f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F2, F3}},
+    {"fcmp.nle.s0",	  f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}},
+    {"fcmp.nle",	  f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO},
+    {"fcmp.nle.s1",	  f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F2, F3}},
+    {"fcmp.nle.s2",	  f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F2, F3}},
+    {"fcmp.nle.s3",	  f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F2, F3}},
+    {"fcmp.ngt.s0",	  f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}},
+    {"fcmp.ngt",	  f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, PSEUDO},
+    {"fcmp.ngt.s1",	  f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F3, F2}},
+    {"fcmp.ngt.s2",	  f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F3, F2}},
+    {"fcmp.ngt.s3",	  f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F3, F2}},
+    {"fcmp.nge.s0",	  f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}},
+    {"fcmp.nge",	  f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, PSEUDO},
+    {"fcmp.nge.s1",	  f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F3, F2}},
+    {"fcmp.nge.s2",	  f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F3, F2}},
+    {"fcmp.nge.s3",	  f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F3, F2}},
+    {"fcmp.ord.s0",	  f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}},
+    {"fcmp.ord",	  f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO},
+    {"fcmp.ord.s1",	  f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P2, P1, F2, F3}},
+    {"fcmp.ord.s2",	  f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P2, P1, F2, F3}},
+    {"fcmp.ord.s3",	  f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P2, P1, F2, F3}},
+    {"fcmp.gt.unc.s0",	  f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}},
+    {"fcmp.gt.unc",	  f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, PSEUDO},
+    {"fcmp.gt.unc.s1",	  f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F3, F2}},
+    {"fcmp.gt.unc.s2",	  f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F3, F2}},
+    {"fcmp.gt.unc.s3",	  f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F3, F2}},
+    {"fcmp.ge.unc.s0",	  f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}},
+    {"fcmp.ge.unc",	  f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, PSEUDO},
+    {"fcmp.ge.unc.s1",	  f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F3, F2}},
+    {"fcmp.ge.unc.s2",	  f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F3, F2}},
+    {"fcmp.ge.unc.s3",	  f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F3, F2}},
+    {"fcmp.neq.unc.s0",	  f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}},
+    {"fcmp.neq.unc",	  f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO},
+    {"fcmp.neq.unc.s1",	  f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P2, P1, F2, F3}},
+    {"fcmp.neq.unc.s2",	  f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P2, P1, F2, F3}},
+    {"fcmp.neq.unc.s3",	  f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P2, P1, F2, F3}},
+    {"fcmp.nlt.unc.s0",	  f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}},
+    {"fcmp.nlt.unc",	  f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO},
+    {"fcmp.nlt.unc.s1",	  f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F2, F3}},
+    {"fcmp.nlt.unc.s2",	  f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F2, F3}},
+    {"fcmp.nlt.unc.s3",	  f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F2, F3}},
+    {"fcmp.nle.unc.s0",	  f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}},
+    {"fcmp.nle.unc",	  f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO},
+    {"fcmp.nle.unc.s1",	  f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F2, F3}},
+    {"fcmp.nle.unc.s2",	  f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F2, F3}},
+    {"fcmp.nle.unc.s3",	  f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F2, F3}},
+    {"fcmp.ngt.unc.s0",	  f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}},
+    {"fcmp.ngt.unc",	  f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, PSEUDO},
+    {"fcmp.ngt.unc.s1",	  f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F3, F2}},
+    {"fcmp.ngt.unc.s2",	  f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F3, F2}},
+    {"fcmp.ngt.unc.s3",	  f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F3, F2}},
+    {"fcmp.nge.unc.s0",	  f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}},
+    {"fcmp.nge.unc",	  f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, PSEUDO},
+    {"fcmp.nge.unc.s1",	  f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F3, F2}},
+    {"fcmp.nge.unc.s2",	  f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F3, F2}},
+    {"fcmp.nge.unc.s3",	  f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F3, F2}},
+    {"fcmp.ord.unc.s0",	  f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}},
+    {"fcmp.ord.unc",	  f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO},
+    {"fcmp.ord.unc.s1",   f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P2, P1, F2, F3}},
+    {"fcmp.ord.unc.s2",   f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P2, P1, F2, F3}},
+    {"fcmp.ord.unc.s3",   f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P2, P1, F2, F3}},
+
+    {"fclass.m",	f2, OpTa (5, 0), {P1, P2, F2, IMMU9}},
+    {"fclass.nm",	f2, OpTa (5, 0), {P2, P1, F2, IMMU9}, PSEUDO},
+    {"fclass.m.unc",	f2, OpTa (5, 1), {P1, P2, F2, IMMU9}},
+    {"fclass.nm.unc",	f2, OpTa (5, 1), {P2, P1, F2, IMMU9}, PSEUDO},
+
+    /* note: fnorm and fcvt.xuf have identical encodings! */
+    {"fnorm.s0",	f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+    {"fnorm",		f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+    {"fnorm.s1",	f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO},
+    {"fnorm.s2",	f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO},
+    {"fnorm.s3",	f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO},
+    {"fnorm.s.s0",	f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO},
+    {"fnorm.s",		f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO},
+    {"fnorm.s.s1",	f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO},
+    {"fnorm.s.s2",	f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO},
+    {"fnorm.s.s3",	f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO},
+    {"fcvt.xuf.s0",	f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+    {"fcvt.xuf",	f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+    {"fcvt.xuf.s1",	f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO},
+    {"fcvt.xuf.s2",	f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO},
+    {"fcvt.xuf.s3",	f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO},
+    {"fcvt.xuf.s.s0",	f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO},
+    {"fcvt.xuf.s",	f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO},
+    {"fcvt.xuf.s.s1",	f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO},
+    {"fcvt.xuf.s.s2",	f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO},
+    {"fcvt.xuf.s.s3",	f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO},
+    {"fadd.s0",		f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+    {"fadd",		f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+    {"fadd.s1",		f, OpXaSfF4 (0x8, 0, 1, 1), {F1, F3, F2}, PSEUDO},
+    {"fadd.s2",		f, OpXaSfF4 (0x8, 0, 2, 1), {F1, F3, F2}, PSEUDO},
+    {"fadd.s3",		f, OpXaSfF4 (0x8, 0, 3, 1), {F1, F3, F2}, PSEUDO},
+    {"fadd.s.s0",	f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO},
+    {"fadd.s",		f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO},
+    {"fadd.s.s1",	f, OpXaSfF4 (0x8, 1, 1, 1), {F1, F3, F2}, PSEUDO},
+    {"fadd.s.s2",	f, OpXaSfF4 (0x8, 1, 2, 1), {F1, F3, F2}, PSEUDO},
+    {"fadd.s.s3",	f, OpXaSfF4 (0x8, 1, 3, 1), {F1, F3, F2}, PSEUDO},
+    {"fmpy.s0",		f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fmpy",		f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fmpy.s1",		f, OpXaSfF2 (0x8, 0, 1, 0), {F1, F3, F4}, PSEUDO},
+    {"fmpy.s2",		f, OpXaSfF2 (0x8, 0, 2, 0), {F1, F3, F4}, PSEUDO},
+    {"fmpy.s3",		f, OpXaSfF2 (0x8, 0, 3, 0), {F1, F3, F4}, PSEUDO},
+    {"fmpy.s.s0",	f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fmpy.s",		f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fmpy.s.s1",	f, OpXaSfF2 (0x8, 1, 1, 0), {F1, F3, F4}, PSEUDO},
+    {"fmpy.s.s2",	f, OpXaSfF2 (0x8, 1, 2, 0), {F1, F3, F4}, PSEUDO},
+    {"fmpy.s.s3",	f, OpXaSfF2 (0x8, 1, 3, 0), {F1, F3, F4}, PSEUDO},
+    {"fma.s0",		f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}},
+    {"fma",		f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, PSEUDO},
+    {"fma.s1",		f, OpXaSf (0x8, 0, 1), {F1, F3, F4, F2}},
+    {"fma.s2",		f, OpXaSf (0x8, 0, 2), {F1, F3, F4, F2}},
+    {"fma.s3",		f, OpXaSf (0x8, 0, 3), {F1, F3, F4, F2}},
+    {"fma.s.s0",	f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, PSEUDO},
+    {"fma.s",		f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}},
+    {"fma.s.s1",	f, OpXaSf (0x8, 1, 1), {F1, F3, F4, F2}},
+    {"fma.s.s2",	f, OpXaSf (0x8, 1, 2), {F1, F3, F4, F2}},
+    {"fma.s.s3",	f, OpXaSf (0x8, 1, 3), {F1, F3, F4, F2}},
+
+    {"fnorm.d.s0",	f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+    {"fnorm.d",		f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+    {"fnorm.d.s1",	f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO},
+    {"fnorm.d.s2",	f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO},
+    {"fnorm.d.s3",	f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO},
+    {"fcvt.xuf.d.s0",	f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+    {"fcvt.xuf.d",	f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO},
+    {"fcvt.xuf.d.s1",	f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO},
+    {"fcvt.xuf.d.s2",	f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO},
+    {"fcvt.xuf.d.s3",	f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO},
+    {"fadd.d.s0",	f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+    {"fadd.d",		f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+    {"fadd.d.s1",	f, OpXaSfF4 (0x9, 0, 1, 1), {F1, F3, F2}, PSEUDO},
+    {"fadd.d.s2",	f, OpXaSfF4 (0x9, 0, 2, 1), {F1, F3, F2}, PSEUDO},
+    {"fadd.d.s3",	f, OpXaSfF4 (0x9, 0, 3, 1), {F1, F3, F2}, PSEUDO},
+    {"fmpy.d.s0",	f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fmpy.d",		f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fmpy.d.s1",	f, OpXaSfF2 (0x9, 0, 1, 0), {F1, F3, F4}, PSEUDO},
+    {"fmpy.d.s2",	f, OpXaSfF2 (0x9, 0, 2, 0), {F1, F3, F4}, PSEUDO},
+    {"fmpy.d.s3",	f, OpXaSfF2 (0x9, 0, 3, 0), {F1, F3, F4}, PSEUDO},
+    {"fma.d.s0",	f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}},
+    {"fma.d",		f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, PSEUDO},
+    {"fma.d.s1",	f, OpXaSf (0x9, 0, 1), {F1, F3, F4, F2}},
+    {"fma.d.s2",	f, OpXaSf (0x9, 0, 2), {F1, F3, F4, F2}},
+    {"fma.d.s3",	f, OpXaSf (0x9, 0, 3), {F1, F3, F4, F2}},
+
+    {"fpmpy.s0",	f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fpmpy",		f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fpmpy.s1",	f, OpXaSfF2 (0x9, 1, 1, 0), {F1, F3, F4}, PSEUDO},
+    {"fpmpy.s2",	f, OpXaSfF2 (0x9, 1, 2, 0), {F1, F3, F4}, PSEUDO},
+    {"fpmpy.s3",	f, OpXaSfF2 (0x9, 1, 3, 0), {F1, F3, F4}, PSEUDO},
+    {"fpma.s0",		f, OpXaSf   (0x9, 1, 0), {F1, F3, F4, F2}},
+    {"fpma",		f, OpXaSf   (0x9, 1, 0), {F1, F3, F4, F2}, PSEUDO},
+    {"fpma.s1",		f, OpXaSf   (0x9, 1, 1), {F1, F3, F4, F2}},
+    {"fpma.s2",		f, OpXaSf   (0x9, 1, 2), {F1, F3, F4, F2}},
+    {"fpma.s3",		f, OpXaSf   (0x9, 1, 3), {F1, F3, F4, F2}},
+
+    {"fsub.s0",		f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+    {"fsub",		f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+    {"fsub.s1",		f, OpXaSfF4 (0xa, 0, 1, 1), {F1, F3, F2}, PSEUDO},
+    {"fsub.s2",		f, OpXaSfF4 (0xa, 0, 2, 1), {F1, F3, F2}, PSEUDO},
+    {"fsub.s3",		f, OpXaSfF4 (0xa, 0, 3, 1), {F1, F3, F2}, PSEUDO},
+    {"fsub.s.s0",	f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO},
+    {"fsub.s",		f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO},
+    {"fsub.s.s1",	f, OpXaSfF4 (0xa, 1, 1, 1), {F1, F3, F2}, PSEUDO},
+    {"fsub.s.s2",	f, OpXaSfF4 (0xa, 1, 2, 1), {F1, F3, F2}, PSEUDO},
+    {"fsub.s.s3",	f, OpXaSfF4 (0xa, 1, 3, 1), {F1, F3, F2}, PSEUDO},
+    {"fms.s0",		f, OpXaSf   (0xa, 0, 0), {F1, F3, F4, F2}},
+    {"fms",		f, OpXaSf   (0xa, 0, 0), {F1, F3, F4, F2}, PSEUDO},
+    {"fms.s1",		f, OpXaSf   (0xa, 0, 1), {F1, F3, F4, F2}},
+    {"fms.s2",		f, OpXaSf   (0xa, 0, 2), {F1, F3, F4, F2}},
+    {"fms.s3",		f, OpXaSf   (0xa, 0, 3), {F1, F3, F4, F2}},
+    {"fms.s.s0",	f, OpXaSf   (0xa, 1, 0), {F1, F3, F4, F2}},
+    {"fms.s",		f, OpXaSf   (0xa, 1, 0), {F1, F3, F4, F2}, PSEUDO},
+    {"fms.s.s1",	f, OpXaSf   (0xa, 1, 1), {F1, F3, F4, F2}},
+    {"fms.s.s2",	f, OpXaSf   (0xa, 1, 2), {F1, F3, F4, F2}},
+    {"fms.s.s3",	f, OpXaSf   (0xa, 1, 3), {F1, F3, F4, F2}},
+    {"fsub.d.s0",	f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+    {"fsub.d",		f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO},
+    {"fsub.d.s1",	f, OpXaSfF4 (0xb, 0, 1, 1), {F1, F3, F2}, PSEUDO},
+    {"fsub.d.s2",	f, OpXaSfF4 (0xb, 0, 2, 1), {F1, F3, F2}, PSEUDO},
+    {"fsub.d.s3",	f, OpXaSfF4 (0xb, 0, 3, 1), {F1, F3, F2}, PSEUDO},
+    {"fms.d.s0",	f, OpXaSf   (0xb, 0, 0), {F1, F3, F4, F2}},
+    {"fms.d",		f, OpXaSf   (0xb, 0, 0), {F1, F3, F4, F2}, PSEUDO},
+    {"fms.d.s1",	f, OpXaSf   (0xb, 0, 1), {F1, F3, F4, F2}},
+    {"fms.d.s2",	f, OpXaSf   (0xb, 0, 2), {F1, F3, F4, F2}},
+    {"fms.d.s3",	f, OpXaSf   (0xb, 0, 3), {F1, F3, F4, F2}},
+
+    {"fpms.s0",		f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}},
+    {"fpms",		f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, PSEUDO},
+    {"fpms.s1",		f, OpXaSf (0xb, 1, 1), {F1, F3, F4, F2}},
+    {"fpms.s2",		f, OpXaSf (0xb, 1, 2), {F1, F3, F4, F2}},
+    {"fpms.s3",		f, OpXaSf (0xb, 1, 3), {F1, F3, F4, F2}},
+
+    {"fnmpy.s0",	f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fnmpy",		f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fnmpy.s1",	f, OpXaSfF2 (0xc, 0, 1, 0), {F1, F3, F4}, PSEUDO},
+    {"fnmpy.s2",	f, OpXaSfF2 (0xc, 0, 2, 0), {F1, F3, F4}, PSEUDO},
+    {"fnmpy.s3",	f, OpXaSfF2 (0xc, 0, 3, 0), {F1, F3, F4}, PSEUDO},
+    {"fnmpy.s.s0",	f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fnmpy.s",		f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fnmpy.s.s1",	f, OpXaSfF2 (0xc, 1, 1, 0), {F1, F3, F4}, PSEUDO},
+    {"fnmpy.s.s2",	f, OpXaSfF2 (0xc, 1, 2, 0), {F1, F3, F4}, PSEUDO},
+    {"fnmpy.s.s3",	f, OpXaSfF2 (0xc, 1, 3, 0), {F1, F3, F4}, PSEUDO},
+    {"fnma.s0",		f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}},
+    {"fnma",		f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, PSEUDO},
+    {"fnma.s1",		f, OpXaSf (0xc, 0, 1), {F1, F3, F4, F2}},
+    {"fnma.s2",		f, OpXaSf (0xc, 0, 2), {F1, F3, F4, F2}},
+    {"fnma.s3",		f, OpXaSf (0xc, 0, 3), {F1, F3, F4, F2}},
+    {"fnma.s.s0",	f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}},
+    {"fnma.s",		f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, PSEUDO},
+    {"fnma.s.s1",	f, OpXaSf (0xc, 1, 1), {F1, F3, F4, F2}},
+    {"fnma.s.s2",	f, OpXaSf (0xc, 1, 2), {F1, F3, F4, F2}},
+    {"fnma.s.s3",	f, OpXaSf (0xc, 1, 3), {F1, F3, F4, F2}},
+    {"fnmpy.d.s0",	f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fnmpy.d",		f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fnmpy.d.s1",	f, OpXaSfF2 (0xd, 0, 1, 0), {F1, F3, F4}, PSEUDO},
+    {"fnmpy.d.s2",	f, OpXaSfF2 (0xd, 0, 2, 0), {F1, F3, F4}, PSEUDO},
+    {"fnmpy.d.s3",	f, OpXaSfF2 (0xd, 0, 3, 0), {F1, F3, F4}, PSEUDO},
+    {"fnma.d.s0",	f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}},
+    {"fnma.d",		f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, PSEUDO},
+    {"fnma.d.s1",	f, OpXaSf (0xd, 0, 1), {F1, F3, F4, F2}},
+    {"fnma.d.s2",	f, OpXaSf (0xd, 0, 2), {F1, F3, F4, F2}},
+    {"fnma.d.s3",	f, OpXaSf (0xd, 0, 3), {F1, F3, F4, F2}},
+
+    {"fpnmpy.s0",	f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fpnmpy",		f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"fpnmpy.s1",	f, OpXaSfF2 (0xd, 1, 1, 0), {F1, F3, F4}, PSEUDO},
+    {"fpnmpy.s2",	f, OpXaSfF2 (0xd, 1, 2, 0), {F1, F3, F4}, PSEUDO},
+    {"fpnmpy.s3",	f, OpXaSfF2 (0xd, 1, 3, 0), {F1, F3, F4}, PSEUDO},
+    {"fpnma.s0",	f, OpXaSf   (0xd, 1, 0), {F1, F3, F4, F2}},
+    {"fpnma",		f, OpXaSf   (0xd, 1, 0), {F1, F3, F4, F2}, PSEUDO},
+    {"fpnma.s1",	f, OpXaSf   (0xd, 1, 1), {F1, F3, F4, F2}},
+    {"fpnma.s2",	f, OpXaSf   (0xd, 1, 2), {F1, F3, F4, F2}},
+    {"fpnma.s3",	f, OpXaSf   (0xd, 1, 3), {F1, F3, F4, F2}},
+
+    {"xmpy.l",		f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"xmpy.lu",		f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO},
+    {"xmpy.h",		f, OpXaX2F2 (0xe, 1, 3, 0), {F1, F3, F4}, PSEUDO},
+    {"xmpy.hu",		f, OpXaX2F2 (0xe, 1, 2, 0), {F1, F3, F4}, PSEUDO},
+    {"xma.l",		f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}},
+    {"xma.lu",		f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, PSEUDO},
+    {"xma.h",		f, OpXaX2 (0xe, 1, 3), {F1, F3, F4, F2}},
+    {"xma.hu",		f, OpXaX2 (0xe, 1, 2), {F1, F3, F4, F2}},
+
+    {"fselect",		f, OpXa (0xe, 0), {F1, F3, F4, F2}},
+
+    {0}
+  };
+
+#undef f0
+#undef f
+#undef f2
+#undef bF2
+#undef bF4
+#undef bQ
+#undef bRa
+#undef bRb
+#undef bSf
+#undef bTa
+#undef bXa
+#undef bXb
+#undef bX2
+#undef bX6
+#undef mF2
+#undef mF4
+#undef mQ
+#undef mRa
+#undef mRb
+#undef mSf
+#undef mTa
+#undef mXa
+#undef mXb
+#undef mX2
+#undef mX6
+#undef OpXa
+#undef OpXaSf
+#undef OpXaSfF2
+#undef OpXaSfF4
+#undef OpXaSfF2F4
+#undef OpXaX2
+#undef OpRaRbTaSf
+#undef OpTa
+#undef OpXbQSf
+#undef OpXbX6
+#undef OpXbX6F2
+#undef OpXbX6Sf
diff --git a/opcodes/ia64-opc-i.c b/opcodes/ia64-opc-i.c
new file mode 100644
index 0000000..2871920
--- /dev/null
+++ b/opcodes/ia64-opc-i.c
@@ -0,0 +1,296 @@
+/* ia64-opc-i.c -- IA-64 `I' opcode table.
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the
+   Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
+
+#include "ia64-opc.h"
+
+#define I0	IA64_TYPE_I, 0
+#define I	IA64_TYPE_I, 1
+#define I2	IA64_TYPE_I, 2
+
+/* instruction bit fields: */
+#define bC(x)		(((ia64_insn) ((x) & 0x1)) << 12)
+#define bIh(x)		(((ia64_insn) ((x) & 0x1)) << 23)
+#define bTa(x)		(((ia64_insn) ((x) & 0x1)) << 33)
+#define bTag13(x)	(((ia64_insn) ((x) & 0x1)) << 33)
+#define bTb(x)		(((ia64_insn) ((x) & 0x1)) << 36)
+#define bVc(x)		(((ia64_insn) ((x) & 0x1)) << 20)
+#define bVe(x)		(((ia64_insn) ((x) & 0x1)) << 32)
+#define bWh(x)		(((ia64_insn) ((x) & 0x3)) << 20)
+#define bX(x)		(((ia64_insn) ((x) & 0x1)) << 33)
+#define bXb(x)		(((ia64_insn) ((x) & 0x1)) << 22)
+#define bX2(x)		(((ia64_insn) ((x) & 0x3)) << 34)
+#define bX2a(x)		(((ia64_insn) ((x) & 0x3)) << 34)
+#define bX2b(x)		(((ia64_insn) ((x) & 0x3)) << 28)
+#define bX2c(x)		(((ia64_insn) ((x) & 0x3)) << 30)
+#define bX3(x)		(((ia64_insn) ((x) & 0x7)) << 33)
+#define bX6(x)		(((ia64_insn) ((x) & 0x3f)) << 27)
+#define bYa(x)		(((ia64_insn) ((x) & 0x1)) << 13)
+#define bYb(x)		(((ia64_insn) ((x) & 0x1)) << 26)
+#define bZa(x)		(((ia64_insn) ((x) & 0x1)) << 36)
+#define bZb(x)		(((ia64_insn) ((x) & 0x1)) << 33)
+
+/* instruction bit masks: */
+#define mC	bC (-1)
+#define mIh	bIh (-1)
+#define mTa	bTa (-1)
+#define mTag13	bTag13 (-1)
+#define mTb	bTb (-1)
+#define mVc	bVc (-1)
+#define mVe	bVe (-1)
+#define mWh	bWh (-1)
+#define mX	bX (-1)
+#define mXb	bXb (-1)
+#define mX2	bX2 (-1)
+#define mX2a	bX2a (-1)
+#define mX2b	bX2b (-1)
+#define mX2c	bX2c (-1)
+#define mX3	bX3 (-1)
+#define mX6	bX6 (-1)
+#define mYa	bYa (-1)
+#define mYb	bYb (-1)
+#define mZa	bZa (-1)
+#define mZb	bZb (-1)
+
+#define OpZaZbVeX2aX2b(a,b,c,d,e,f) \
+	(bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \
+	(mOp | mZa | mZb | mVe | mX2a | mX2b)
+#define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \
+  (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \
+	(mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c)
+#define OpX2X(a,b,c)		(bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX)
+#define OpX2XYa(a,b,c,d)	(bOp (a) | bX2 (b) | bX (c) | bYa (d)), \
+				(mOp | mX2 | mX | mYa)
+#define OpX2XYb(a,b,c,d)	(bOp (a) | bX2 (b) | bX (c) | bYb (d)), \
+				(mOp | mX2 | mX | mYb)
+#define OpX2TaTbYaC(a,b,c,d,e,f) \
+	(bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \
+	(mOp | mX2 | mTa | mTb | mYa | mC)
+#define OpX3(a,b)		(bOp (a) | bX3 (b)), (mOp | mX3)
+#define OpX3X6(a,b,c)		(bOp (a) | bX3 (b) | bX6(c)), \
+				(mOp | mX3 | mX6)
+#define OpX3XbIhWh(a,b,c,d,e) \
+  (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \
+  (mOp | mX3 | mXb | mIh | mWh)
+#define OpX3XbIhWhTag13(a,b,c,d,e,f) \
+     (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \
+     (mOp | mX3 | mXb | mIh | mWh | mTag13)
+
+struct ia64_opcode ia64_opcodes_i[] =
+  {
+    /* I-type instruction encodings (sorted according to major opcode) */
+
+    {"break.i",	I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX},
+    {"nop.i",	I0, OpX3X6 (0, 0, 0x01), {IMMU21}, X_IN_MLX},
+    {"chk.s.i",	I0, OpX3 (0, 1), {R2, TGT25b}},
+
+    {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO},
+#define MOV(a,b,c,d) \
+    I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}
+    {"mov.sptk",		MOV (7, 0, 0, 0)},
+    {"mov.sptk.imp",		MOV (7, 0, 1, 0)},
+    {"mov",			MOV (7, 0, 0, 1)},
+    {"mov.imp",			MOV (7, 0, 1, 1)},
+    {"mov.dptk",		MOV (7, 0, 0, 2)},
+    {"mov.dptk.imp",		MOV (7, 0, 1, 2)},
+    {"mov.ret.sptk",		MOV (7, 1, 0, 0)},
+    {"mov.ret.sptk.imp",	MOV (7, 1, 1, 0)},
+    {"mov.ret",			MOV (7, 1, 0, 1)},
+    {"mov.ret.imp",		MOV (7, 1, 1, 1)},
+    {"mov.ret.dptk",		MOV (7, 1, 0, 2)},
+    {"mov.ret.dptk.imp",	MOV (7, 1, 1, 2)},
+#undef MOV
+    {"mov",	I, OpX3X6 (0, 0, 0x31), {R1, B2}},
+    {"mov",	I, OpX3 (0, 3), {PR, R2, IMM17}},
+    {"mov",	I, OpX3 (0, 2), {PR_ROT, IMM44}},
+    {"mov",	I, OpX3X6 (0, 0, 0x30), {R1, IP}},
+    {"mov",	I, OpX3X6 (0, 0, 0x33), {R1, PR}},
+    {"mov.i",	I, OpX3X6 (0, 0, 0x2a), {AR3, R2}},
+    {"mov.i",	I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}},
+    {"mov.i",	I, OpX3X6 (0, 0, 0x32), {R1, AR3}},
+    {"zxt1",	I, OpX3X6 (0, 0, 0x10), {R1, R3}},
+    {"zxt2",	I, OpX3X6 (0, 0, 0x11), {R1, R3}},
+    {"zxt4",	I, OpX3X6 (0, 0, 0x12), {R1, R3}},
+    {"sxt1",	I, OpX3X6 (0, 0, 0x14), {R1, R3}},
+    {"sxt2",	I, OpX3X6 (0, 0, 0x15), {R1, R3}},
+    {"sxt4",	I, OpX3X6 (0, 0, 0x16), {R1, R3}},
+    {"czx1.l",	I, OpX3X6 (0, 0, 0x18), {R1, R3}},
+    {"czx2.l",	I, OpX3X6 (0, 0, 0x19), {R1, R3}},
+    {"czx1.r",	I, OpX3X6 (0, 0, 0x1c), {R1, R3}},
+    {"czx2.r",	I, OpX3X6 (0, 0, 0x1d), {R1, R3}},
+
+    {"dep",	I, Op (4), {R1, R2, R3, CPOS6c, LEN4}},
+
+    {"shrp",	I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}},
+
+    {"shr.u",	I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6},
+     PSEUDO | LEN_EQ_64MCNT},
+    {"extr.u",	I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}},
+
+    {"shr",	I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6},
+     PSEUDO | LEN_EQ_64MCNT},
+    {"extr",	I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}},
+
+    {"shl",	I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a},
+     PSEUDO | LEN_EQ_64MCNT},
+    {"dep.z",	I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}},
+    {"dep.z",	I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}},
+    {"dep",	I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}},
+#define TBIT(a,b,c,d) \
+        I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}
+#define TBITCM(a,b,c,d)	\
+        I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO
+    {"tbit.z",		 TBIT   (0, 0, 0, 0)},
+    {"tbit.nz",		 TBITCM (0, 0, 0, 0)},
+    {"tbit.z.unc",	 TBIT   (0, 0, 0, 1)},
+    {"tbit.nz.unc",	 TBITCM (0, 0, 0, 1)},
+    {"tbit.z.and",	 TBIT   (0, 1, 0, 0)},
+    {"tbit.nz.andcm",	 TBITCM (0, 1, 0, 0)},
+    {"tbit.nz.and",	 TBIT   (0, 1, 0, 1)},
+    {"tbit.z.andcm",	 TBITCM (0, 1, 0, 1)},
+    {"tbit.z.or",	 TBIT   (1, 0, 0, 0)},
+    {"tbit.nz.orcm",	 TBITCM (1, 0, 0, 0)},
+    {"tbit.nz.or",	 TBIT   (1, 0, 0, 1)},
+    {"tbit.z.orcm",	 TBITCM (1, 0, 0, 1)},
+    {"tbit.z.or.andcm",	 TBIT   (1, 1, 0, 0)},
+    {"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)},
+    {"tbit.nz.or.andcm", TBIT   (1, 1, 0, 1)},
+    {"tbit.z.and.orcm",  TBITCM (1, 1, 0, 1)},
+#undef TBIT
+#define TNAT(a,b,c,d) \
+	I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}
+#define TNATCM(a,b,c,d) \
+	I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO
+    {"tnat.z",		 TNAT   (0, 0, 1, 0)},
+    {"tnat.nz",		 TNATCM (0, 0, 1, 0)},
+    {"tnat.z.unc",	 TNAT   (0, 0, 1, 1)},
+    {"tnat.nz.unc",	 TNATCM (0, 0, 1, 1)},
+    {"tnat.z.and",	 TNAT   (0, 1, 1, 0)},
+    {"tnat.nz.andcm",	 TNATCM (0, 1, 1, 0)},
+    {"tnat.nz.and",	 TNAT   (0, 1, 1, 1)},
+    {"tnat.z.andcm",	 TNATCM (0, 1, 1, 1)},
+    {"tnat.z.or",	 TNAT   (1, 0, 1, 0)},
+    {"tnat.nz.orcm",	 TNATCM (1, 0, 1, 0)},
+    {"tnat.nz.or",	 TNAT   (1, 0, 1, 1)},
+    {"tnat.z.orcm",	 TNATCM (1, 0, 1, 1)},
+    {"tnat.z.or.andcm",	 TNAT   (1, 1, 1, 0)},
+    {"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)},
+    {"tnat.nz.or.andcm", TNAT   (1, 1, 1, 1)},
+    {"tnat.z.and.orcm",  TNATCM (1, 1, 1, 1)},
+#undef TNAT
+
+    {"pmpyshr2",   I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}},
+    {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}},
+    {"pmpy2.r",	   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}},
+    {"pmpy2.l",	   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}},
+    {"mix1.r",	   I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}},
+    {"mix2.r",	   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}},
+    {"mix4.r",	   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}},
+    {"mix1.l",	   I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}},
+    {"mix2.l",	   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}},
+    {"mix4.l",	   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}},
+    {"pack2.uss",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}},
+    {"pack2.sss",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}},
+    {"pack4.sss",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}},
+    {"unpack1.h",  I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}},
+    {"unpack2.h",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}},
+    {"unpack4.h",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}},
+    {"unpack1.l",  I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}},
+    {"unpack2.l",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}},
+    {"unpack4.l",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}},
+    {"pmin1.u",	   I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}},
+    {"pmax1.u",	   I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}},
+    {"pmin2",	   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}},
+    {"pmax2",	   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}},
+    {"psad1",	   I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}},
+    {"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}},
+    {"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}},
+    {"pshr2",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}},
+    {"pshr4",	I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}},
+    {"shr",	I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}},
+    {"pshr2.u",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}},
+    {"pshr4.u",	I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}},
+    {"shr.u",	I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}},
+    {"pshr2",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}},
+    {"pshr4",	I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}},
+    {"pshr2.u",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}},
+    {"pshr4.u",	I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}},
+    {"pshl2",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}},
+    {"pshl4",	I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}},
+    {"shl",	I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}},
+    {"pshl2",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}},
+    {"pshl4",	I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}},
+    {"popcnt",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}},
+
+    {0}
+  };
+
+#undef I0
+#undef I
+#undef I2
+#undef L
+#undef bC
+#undef bIh
+#undef bTa
+#undef bTag13
+#undef bTb
+#undef bVc
+#undef bVe
+#undef bWh
+#undef bX
+#undef bXb
+#undef bX2
+#undef bX2a
+#undef bX2b
+#undef bX2c
+#undef bX3
+#undef bX6
+#undef bY
+#undef bZa
+#undef bZb
+#undef mC
+#undef mIh
+#undef mTa
+#undef mTag13
+#undef mTb
+#undef mVc
+#undef mVe
+#undef mWh
+#undef mX
+#undef mXb
+#undef mX2
+#undef mX2a
+#undef mX2b
+#undef mX2c
+#undef mX3
+#undef mX6
+#undef mY
+#undef mZa
+#undef mZb
+#undef OpZaZbVeX2aX2b
+#undef OpZaZbVeX2aX2bX2c
+#undef OpX2X
+#undef OpX2XYa
+#undef OpX2XYb
+#undef OpX2TaTbYaC
+#undef OpX3
+#undef OpX3X6
+#undef OpX3XbIhWh
+#undef OpX3XbIhWhTag13
diff --git a/opcodes/ia64-opc-m.c b/opcodes/ia64-opc-m.c
new file mode 100644
index 0000000..13a971e
--- /dev/null
+++ b/opcodes/ia64-opc-m.c
@@ -0,0 +1,1042 @@
+/* ia64-opc-m.c -- IA-64 `M' opcode table.
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the
+   Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
+
+#include "ia64-opc.h"
+
+#define M0	IA64_TYPE_M, 0
+#define M	IA64_TYPE_M, 1
+#define M2	IA64_TYPE_M, 2
+
+/* instruction bit fields: */
+#define bM(x)		(((ia64_insn) ((x) & 0x1)) << 36)
+#define bX(x)		(((ia64_insn) ((x) & 0x1)) << 27)
+#define bX2(x)		(((ia64_insn) ((x) & 0x3)) << 31)
+#define bX3(x)		(((ia64_insn) ((x) & 0x7)) << 33)
+#define bX4(x)		(((ia64_insn) ((x) & 0xf)) << 27)
+#define bX6a(x)		(((ia64_insn) ((x) & 0x3f)) << 30)
+#define bX6b(x)		(((ia64_insn) ((x) & 0x3f)) << 27)
+#define bHint(x)	(((ia64_insn) ((x) & 0x3)) << 28)
+
+#define mM	bM (-1)
+#define mX	bX (-1)
+#define mX2	bX2 (-1)
+#define mX3	bX3 (-1)
+#define mX4	bX4 (-1)
+#define mX6a	bX6a (-1)
+#define mX6b	bX6b (-1)
+#define mHint	bHint (-1)
+
+#define OpX3(a,b) 		(bOp (a) | bX3 (b)), (mOp | mX3)
+#define OpX3X6b(a,b,c) 		(bOp (a) | bX3 (b) | bX6b (c)), \
+				(mOp | mX3 | mX6b)
+#define OpX3X4(a,b,c)	 	(bOp (a) | bX3 (b) | bX4 (c)), \
+				(mOp | mX3 | mX4)
+#define OpX3X4X2(a,b,c,d) 	(bOp (a) | bX3 (b) | bX4 (c) | bX2 (d)), \
+				(mOp | mX3 | mX4 | mX2)
+#define OpX6aHint(a,b,c) 	(bOp (a) | bX6a (b) | bHint (c)), \
+				(mOp | mX6a | mHint)
+#define OpXX6aHint(a,b,c,d) 	(bOp (a) | bX (b) | bX6a (c) | bHint (d)), \
+				(mOp | mX | mX6a | mHint)
+#define OpMXX6a(a,b,c,d) \
+	(bOp (a) | bM (b) | bX (c) | bX6a (d)), (mOp | mM | mX | mX6a)
+#define OpMXX6aHint(a,b,c,d,e) \
+	(bOp (a) | bM (b) | bX (c) | bX6a (d) | bHint (e)), \
+	(mOp | mM | mX | mX6a | mHint)
+
+struct ia64_opcode ia64_opcodes_m[] =
+  {
+    /* M-type instruction encodings (sorted according to major opcode) */
+
+    {"chk.a.nc",	M0, OpX3 (0, 4), {R1, TGT25c}},
+    {"chk.a.clr",	M0, OpX3 (0, 5), {R1, TGT25c}},
+    {"chk.a.nc",	M0, OpX3 (0, 6), {F1, TGT25c}},
+    {"chk.a.clr",	M0, OpX3 (0, 7), {F1, TGT25c}},
+
+    {"invala",		M0, OpX3X4X2 (0, 0, 0, 1)},
+    {"fwb",		M0, OpX3X4X2 (0, 0, 0, 2)},
+    {"mf",		M0, OpX3X4X2 (0, 0, 2, 2)},
+    {"mf.a",		M0, OpX3X4X2 (0, 0, 3, 2)},
+    {"srlz.d",		M0, OpX3X4X2 (0, 0, 0, 3)},
+    {"srlz.i",		M0, OpX3X4X2 (0, 0, 1, 3)},
+    {"sync.i",		M0, OpX3X4X2 (0, 0, 3, 3)},
+    {"flushrs",		M0, OpX3X4X2 (0, 0, 0xc, 0), {0, }, FIRST | NO_PRED},
+    {"loadrs",		M0, OpX3X4X2 (0, 0, 0xa, 0), {0, }, FIRST | NO_PRED},
+    {"invala.e",	M0, OpX3X4X2 (0, 0, 2, 1), {R1}},
+    {"invala.e",	M0, OpX3X4X2 (0, 0, 3, 1), {F1}},
+    {"mov.m",		M, OpX3X4X2 (0, 0, 8, 2), {AR3, IMM8}},
+
+    {"break.m",		M0, OpX3X4X2 (0, 0, 0, 0), {IMMU21}},
+    {"nop.m",		M0, OpX3X4X2 (0, 0, 1, 0), {IMMU21}},
+
+    {"sum",		M0, OpX3X4 (0, 0, 4), {IMMU24}},
+    {"rum",		M0, OpX3X4 (0, 0, 5), {IMMU24}},
+    {"ssm",		M0, OpX3X4 (0, 0, 6), {IMMU24}, PRIV},
+    {"rsm",		M0, OpX3X4 (0, 0, 7), {IMMU24}, PRIV},
+
+    {"mov.m",	M, OpX3X6b (1, 0, 0x2a), {AR3, R2}},
+    {"mov.m",	M, OpX3X6b (1, 0, 0x22), {R1, AR3}},
+    {"mov",	M, OpX3X6b (1, 0, 0x2c), {CR3, R2}, PRIV},
+    {"mov",	M, OpX3X6b (1, 0, 0x24), {R1, CR3}, PRIV},
+
+    {"alloc",	M, OpX3 (1, 6), {R1, AR_PFS, SOF, SOL, SOR}, FIRST|NO_PRED|MOD_RRBS},
+
+    {"mov",	M, OpX3X6b (1, 0, 0x2d), {PSR_L, R2}, PRIV},
+    {"mov",	M, OpX3X6b (1, 0, 0x29), {PSR_UM, R2}},
+    {"mov",	M, OpX3X6b (1, 0, 0x25), {R1, PSR}, PRIV},
+    {"mov",	M, OpX3X6b (1, 0, 0x21), {R1, PSR_UM}},
+    {"probe.r",	M, OpX3X6b (1, 0, 0x38), {R1, R3, R2}},
+    {"probe.w",	M, OpX3X6b (1, 0, 0x39), {R1, R3, R2}},
+    {"probe.r", M, OpX3X6b (1, 0, 0x18), {R1, R3, IMMU2}},
+    {"probe.w", M, OpX3X6b (1, 0, 0x19), {R1, R3, IMMU2}},
+    {"probe.rw.fault", M0, OpX3X6b (1, 0, 0x31), {R3, IMMU2}},
+    {"probe.r.fault",  M0, OpX3X6b (1, 0, 0x32), {R3, IMMU2}},
+    {"probe.w.fault",  M0, OpX3X6b (1, 0, 0x33), {R3, IMMU2}},
+    {"itc.d",	M0, OpX3X6b (1, 0, 0x2e), {R2}, LAST | PRIV},
+    {"itc.i",	M0, OpX3X6b (1, 0, 0x2f), {R2}, LAST | PRIV},
+
+    {"mov",	M, OpX3X6b (1, 0, 0x00), {RR_R3, R2}, PRIV},
+    {"mov",	M, OpX3X6b (1, 0, 0x01), {DBR_R3, R2}, PRIV},
+    {"mov",	M, OpX3X6b (1, 0, 0x02), {IBR_R3, R2}, PRIV},
+    {"mov",	M, OpX3X6b (1, 0, 0x03), {PKR_R3, R2}, PRIV},
+    {"mov",	M, OpX3X6b (1, 0, 0x04), {PMC_R3, R2}, PRIV},
+    {"mov",	M, OpX3X6b (1, 0, 0x05), {PMD_R3, R2}, PRIV},
+    {"mov",	M, OpX3X6b (1, 0, 0x06), {MSR_R3, R2}, PRIV},
+    {"itr.d",	M, OpX3X6b (1, 0, 0x0e), {DTR_R3, R2}, PRIV},
+    {"itr.i",	M, OpX3X6b (1, 0, 0x0f), {ITR_R3, R2}, PRIV},
+
+    {"mov",	M, OpX3X6b (1, 0, 0x10), {R1, RR_R3}, PRIV},
+    {"mov",	M, OpX3X6b (1, 0, 0x11), {R1, DBR_R3}, PRIV},
+    {"mov",	M, OpX3X6b (1, 0, 0x12), {R1, IBR_R3}, PRIV},
+    {"mov",	M, OpX3X6b (1, 0, 0x13), {R1, PKR_R3}, PRIV},
+    {"mov",	M, OpX3X6b (1, 0, 0x14), {R1, PMC_R3}, PRIV},
+    {"mov",	M, OpX3X6b (1, 0, 0x15), {R1, PMD_R3}},
+    {"mov",	M, OpX3X6b (1, 0, 0x16), {R1, MSR_R3}, PRIV},
+    {"mov",	M, OpX3X6b (1, 0, 0x17), {R1, CPUID_R3}},
+
+    {"ptc.l",	M0, OpX3X6b (1, 0, 0x09), {R3, R2}, PRIV},
+    {"ptc.g",	M0, OpX3X6b (1, 0, 0x0a), {R3, R2}, LAST | PRIV},
+    {"ptc.ga",	M0, OpX3X6b (1, 0, 0x0b), {R3, R2}, LAST | PRIV},
+    {"ptr.d",	M0, OpX3X6b (1, 0, 0x0c), {R3, R2}, PRIV},
+    {"ptr.i",	M0, OpX3X6b (1, 0, 0x0d), {R3, R2}, PRIV},
+
+    {"thash",	M, OpX3X6b (1, 0, 0x1a), {R1, R3}},
+    {"ttag",	M, OpX3X6b (1, 0, 0x1b), {R1, R3}},
+    {"tpa",	M, OpX3X6b (1, 0, 0x1e), {R1, R3}, PRIV},
+    {"tak",	M, OpX3X6b (1, 0, 0x1f), {R1, R3}, PRIV},
+
+    {"chk.s.m",	M0, OpX3 (1, 1), {R2, TGT25b}},
+    {"chk.s",	M0, OpX3 (1, 3), {F2, TGT25b}},
+
+    {"fc",	M0, OpX3X6b (1, 0, 0x30), {R3}},
+    {"ptc.e",	M0, OpX3X6b (1, 0, 0x34), {R3}, PRIV},
+
+    /* integer load */
+    {"ld1",		M, OpMXX6aHint (4, 0, 0, 0x00, 0), {R1, MR3}},
+    {"ld1.nt1",		M, OpMXX6aHint (4, 0, 0, 0x00, 1), {R1, MR3}},
+    {"ld1.nta",		M, OpMXX6aHint (4, 0, 0, 0x00, 3), {R1, MR3}},
+    {"ld2",		M, OpMXX6aHint (4, 0, 0, 0x01, 0), {R1, MR3}},
+    {"ld2.nt1",		M, OpMXX6aHint (4, 0, 0, 0x01, 1), {R1, MR3}},
+    {"ld2.nta",		M, OpMXX6aHint (4, 0, 0, 0x01, 3), {R1, MR3}},
+    {"ld4",		M, OpMXX6aHint (4, 0, 0, 0x02, 0), {R1, MR3}},
+    {"ld4.nt1",		M, OpMXX6aHint (4, 0, 0, 0x02, 1), {R1, MR3}},
+    {"ld4.nta",		M, OpMXX6aHint (4, 0, 0, 0x02, 3), {R1, MR3}},
+    {"ld8",		M, OpMXX6aHint (4, 0, 0, 0x03, 0), {R1, MR3}},
+    {"ld8.nt1",		M, OpMXX6aHint (4, 0, 0, 0x03, 1), {R1, MR3}},
+    {"ld8.nta",		M, OpMXX6aHint (4, 0, 0, 0x03, 3), {R1, MR3}},
+    {"ld1.s",		M, OpMXX6aHint (4, 0, 0, 0x04, 0), {R1, MR3}},
+    {"ld1.s.nt1",	M, OpMXX6aHint (4, 0, 0, 0x04, 1), {R1, MR3}},
+    {"ld1.s.nta",	M, OpMXX6aHint (4, 0, 0, 0x04, 3), {R1, MR3}},
+    {"ld2.s",		M, OpMXX6aHint (4, 0, 0, 0x05, 0), {R1, MR3}},
+    {"ld2.s.nt1",	M, OpMXX6aHint (4, 0, 0, 0x05, 1), {R1, MR3}},
+    {"ld2.s.nta",	M, OpMXX6aHint (4, 0, 0, 0x05, 3), {R1, MR3}},
+    {"ld4.s",		M, OpMXX6aHint (4, 0, 0, 0x06, 0), {R1, MR3}},
+    {"ld4.s.nt1",	M, OpMXX6aHint (4, 0, 0, 0x06, 1), {R1, MR3}},
+    {"ld4.s.nta",	M, OpMXX6aHint (4, 0, 0, 0x06, 3), {R1, MR3}},
+    {"ld8.s",		M, OpMXX6aHint (4, 0, 0, 0x07, 0), {R1, MR3}},
+    {"ld8.s.nt1",	M, OpMXX6aHint (4, 0, 0, 0x07, 1), {R1, MR3}},
+    {"ld8.s.nta",	M, OpMXX6aHint (4, 0, 0, 0x07, 3), {R1, MR3}},
+    {"ld1.a",		M, OpMXX6aHint (4, 0, 0, 0x08, 0), {R1, MR3}},
+    {"ld1.a.nt1",	M, OpMXX6aHint (4, 0, 0, 0x08, 1), {R1, MR3}},
+    {"ld1.a.nta",	M, OpMXX6aHint (4, 0, 0, 0x08, 3), {R1, MR3}},
+    {"ld2.a",		M, OpMXX6aHint (4, 0, 0, 0x09, 0), {R1, MR3}},
+    {"ld2.a.nt1",	M, OpMXX6aHint (4, 0, 0, 0x09, 1), {R1, MR3}},
+    {"ld2.a.nta",	M, OpMXX6aHint (4, 0, 0, 0x09, 3), {R1, MR3}},
+    {"ld4.a",		M, OpMXX6aHint (4, 0, 0, 0x0a, 0), {R1, MR3}},
+    {"ld4.a.nt1",	M, OpMXX6aHint (4, 0, 0, 0x0a, 1), {R1, MR3}},
+    {"ld4.a.nta",	M, OpMXX6aHint (4, 0, 0, 0x0a, 3), {R1, MR3}},
+    {"ld8.a",		M, OpMXX6aHint (4, 0, 0, 0x0b, 0), {R1, MR3}},
+    {"ld8.a.nt1",	M, OpMXX6aHint (4, 0, 0, 0x0b, 1), {R1, MR3}},
+    {"ld8.a.nta",	M, OpMXX6aHint (4, 0, 0, 0x0b, 3), {R1, MR3}},
+    {"ld1.sa",		M, OpMXX6aHint (4, 0, 0, 0x0c, 0), {R1, MR3}},
+    {"ld1.sa.nt1",	M, OpMXX6aHint (4, 0, 0, 0x0c, 1), {R1, MR3}},
+    {"ld1.sa.nta",	M, OpMXX6aHint (4, 0, 0, 0x0c, 3), {R1, MR3}},
+    {"ld2.sa",		M, OpMXX6aHint (4, 0, 0, 0x0d, 0), {R1, MR3}},
+    {"ld2.sa.nt1",	M, OpMXX6aHint (4, 0, 0, 0x0d, 1), {R1, MR3}},
+    {"ld2.sa.nta",	M, OpMXX6aHint (4, 0, 0, 0x0d, 3), {R1, MR3}},
+    {"ld4.sa",		M, OpMXX6aHint (4, 0, 0, 0x0e, 0), {R1, MR3}},
+    {"ld4.sa.nt1",	M, OpMXX6aHint (4, 0, 0, 0x0e, 1), {R1, MR3}},
+    {"ld4.sa.nta",	M, OpMXX6aHint (4, 0, 0, 0x0e, 3), {R1, MR3}},
+    {"ld8.sa",		M, OpMXX6aHint (4, 0, 0, 0x0f, 0), {R1, MR3}},
+    {"ld8.sa.nt1",	M, OpMXX6aHint (4, 0, 0, 0x0f, 1), {R1, MR3}},
+    {"ld8.sa.nta",	M, OpMXX6aHint (4, 0, 0, 0x0f, 3), {R1, MR3}},
+    {"ld1.bias",	M, OpMXX6aHint (4, 0, 0, 0x10, 0), {R1, MR3}},
+    {"ld1.bias.nt1",	M, OpMXX6aHint (4, 0, 0, 0x10, 1), {R1, MR3}},
+    {"ld1.bias.nta",	M, OpMXX6aHint (4, 0, 0, 0x10, 3), {R1, MR3}},
+    {"ld2.bias",	M, OpMXX6aHint (4, 0, 0, 0x11, 0), {R1, MR3}},
+    {"ld2.bias.nt1",	M, OpMXX6aHint (4, 0, 0, 0x11, 1), {R1, MR3}},
+    {"ld2.bias.nta",	M, OpMXX6aHint (4, 0, 0, 0x11, 3), {R1, MR3}},
+    {"ld4.bias",	M, OpMXX6aHint (4, 0, 0, 0x12, 0), {R1, MR3}},
+    {"ld4.bias.nt1",	M, OpMXX6aHint (4, 0, 0, 0x12, 1), {R1, MR3}},
+    {"ld4.bias.nta",	M, OpMXX6aHint (4, 0, 0, 0x12, 3), {R1, MR3}},
+    {"ld8.bias",	M, OpMXX6aHint (4, 0, 0, 0x13, 0), {R1, MR3}},
+    {"ld8.bias.nt1",	M, OpMXX6aHint (4, 0, 0, 0x13, 1), {R1, MR3}},
+    {"ld8.bias.nta",	M, OpMXX6aHint (4, 0, 0, 0x13, 3), {R1, MR3}},
+    {"ld1.acq",		M, OpMXX6aHint (4, 0, 0, 0x14, 0), {R1, MR3}},
+    {"ld1.acq.nt1",	M, OpMXX6aHint (4, 0, 0, 0x14, 1), {R1, MR3}},
+    {"ld1.acq.nta",	M, OpMXX6aHint (4, 0, 0, 0x14, 3), {R1, MR3}},
+    {"ld2.acq",		M, OpMXX6aHint (4, 0, 0, 0x15, 0), {R1, MR3}},
+    {"ld2.acq.nt1",	M, OpMXX6aHint (4, 0, 0, 0x15, 1), {R1, MR3}},
+    {"ld2.acq.nta",	M, OpMXX6aHint (4, 0, 0, 0x15, 3), {R1, MR3}},
+    {"ld4.acq",		M, OpMXX6aHint (4, 0, 0, 0x16, 0), {R1, MR3}},
+    {"ld4.acq.nt1",	M, OpMXX6aHint (4, 0, 0, 0x16, 1), {R1, MR3}},
+    {"ld4.acq.nta",	M, OpMXX6aHint (4, 0, 0, 0x16, 3), {R1, MR3}},
+    {"ld8.acq",		M, OpMXX6aHint (4, 0, 0, 0x17, 0), {R1, MR3}},
+    {"ld8.acq.nt1",	M, OpMXX6aHint (4, 0, 0, 0x17, 1), {R1, MR3}},
+    {"ld8.acq.nta",	M, OpMXX6aHint (4, 0, 0, 0x17, 3), {R1, MR3}},
+    {"ld8.fill",	M, OpMXX6aHint (4, 0, 0, 0x1b, 0), {R1, MR3}},
+    {"ld8.fill.nt1",	M, OpMXX6aHint (4, 0, 0, 0x1b, 1), {R1, MR3}},
+    {"ld8.fill.nta",	M, OpMXX6aHint (4, 0, 0, 0x1b, 3), {R1, MR3}},
+    {"ld1.c.clr",	M, OpMXX6aHint (4, 0, 0, 0x20, 0), {R1, MR3}},
+    {"ld1.c.clr.nt1",	M, OpMXX6aHint (4, 0, 0, 0x20, 1), {R1, MR3}},
+    {"ld1.c.clr.nta",	M, OpMXX6aHint (4, 0, 0, 0x20, 3), {R1, MR3}},
+    {"ld2.c.clr",	M, OpMXX6aHint (4, 0, 0, 0x21, 0), {R1, MR3}},
+    {"ld2.c.clr.nt1",	M, OpMXX6aHint (4, 0, 0, 0x21, 1), {R1, MR3}},
+    {"ld2.c.clr.nta",	M, OpMXX6aHint (4, 0, 0, 0x21, 3), {R1, MR3}},
+    {"ld4.c.clr",	M, OpMXX6aHint (4, 0, 0, 0x22, 0), {R1, MR3}},
+    {"ld4.c.clr.nt1",	M, OpMXX6aHint (4, 0, 0, 0x22, 1), {R1, MR3}},
+    {"ld4.c.clr.nta",	M, OpMXX6aHint (4, 0, 0, 0x22, 3), {R1, MR3}},
+    {"ld8.c.clr",	M, OpMXX6aHint (4, 0, 0, 0x23, 0), {R1, MR3}},
+    {"ld8.c.clr.nt1",	M, OpMXX6aHint (4, 0, 0, 0x23, 1), {R1, MR3}},
+    {"ld8.c.clr.nta",	M, OpMXX6aHint (4, 0, 0, 0x23, 3), {R1, MR3}},
+    {"ld1.c.nc",	M, OpMXX6aHint (4, 0, 0, 0x24, 0), {R1, MR3}},
+    {"ld1.c.nc.nt1",	M, OpMXX6aHint (4, 0, 0, 0x24, 1), {R1, MR3}},
+    {"ld1.c.nc.nta",	M, OpMXX6aHint (4, 0, 0, 0x24, 3), {R1, MR3}},
+    {"ld2.c.nc",	M, OpMXX6aHint (4, 0, 0, 0x25, 0), {R1, MR3}},
+    {"ld2.c.nc.nt1",	M, OpMXX6aHint (4, 0, 0, 0x25, 1), {R1, MR3}},
+    {"ld2.c.nc.nta",	M, OpMXX6aHint (4, 0, 0, 0x25, 3), {R1, MR3}},
+    {"ld4.c.nc",	M, OpMXX6aHint (4, 0, 0, 0x26, 0), {R1, MR3}},
+    {"ld4.c.nc.nt1",	M, OpMXX6aHint (4, 0, 0, 0x26, 1), {R1, MR3}},
+    {"ld4.c.nc.nta",	M, OpMXX6aHint (4, 0, 0, 0x26, 3), {R1, MR3}},
+    {"ld8.c.nc",	M, OpMXX6aHint (4, 0, 0, 0x27, 0), {R1, MR3}},
+    {"ld8.c.nc.nt1",	M, OpMXX6aHint (4, 0, 0, 0x27, 1), {R1, MR3}},
+    {"ld8.c.nc.nta",	M, OpMXX6aHint (4, 0, 0, 0x27, 3), {R1, MR3}},
+    {"ld1.c.clr.acq",	  M, OpMXX6aHint (4, 0, 0, 0x28, 0), {R1, MR3}},
+    {"ld1.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x28, 1), {R1, MR3}},
+    {"ld1.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x28, 3), {R1, MR3}},
+    {"ld2.c.clr.acq",	  M, OpMXX6aHint (4, 0, 0, 0x29, 0), {R1, MR3}},
+    {"ld2.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x29, 1), {R1, MR3}},
+    {"ld2.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x29, 3), {R1, MR3}},
+    {"ld4.c.clr.acq",	  M, OpMXX6aHint (4, 0, 0, 0x2a, 0), {R1, MR3}},
+    {"ld4.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2a, 1), {R1, MR3}},
+    {"ld4.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2a, 3), {R1, MR3}},
+    {"ld8.c.clr.acq",	  M, OpMXX6aHint (4, 0, 0, 0x2b, 0), {R1, MR3}},
+    {"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2b, 1), {R1, MR3}},
+    {"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2b, 3), {R1, MR3}},
+
+    /* integer load w/increment by register */
+    {"ld1",		M, OpMXX6aHint (4, 1, 0, 0x00, 0), {R1, MR3, R2}},
+    {"ld1.nt1",		M, OpMXX6aHint (4, 1, 0, 0x00, 1), {R1, MR3, R2}},
+    {"ld1.nta",		M, OpMXX6aHint (4, 1, 0, 0x00, 3), {R1, MR3, R2}},
+    {"ld2",		M, OpMXX6aHint (4, 1, 0, 0x01, 0), {R1, MR3, R2}},
+    {"ld2.nt1",		M, OpMXX6aHint (4, 1, 0, 0x01, 1), {R1, MR3, R2}},
+    {"ld2.nta",		M, OpMXX6aHint (4, 1, 0, 0x01, 3), {R1, MR3, R2}},
+    {"ld4",		M, OpMXX6aHint (4, 1, 0, 0x02, 0), {R1, MR3, R2}},
+    {"ld4.nt1",		M, OpMXX6aHint (4, 1, 0, 0x02, 1), {R1, MR3, R2}},
+    {"ld4.nta",		M, OpMXX6aHint (4, 1, 0, 0x02, 3), {R1, MR3, R2}},
+    {"ld8",		M, OpMXX6aHint (4, 1, 0, 0x03, 0), {R1, MR3, R2}},
+    {"ld8.nt1",		M, OpMXX6aHint (4, 1, 0, 0x03, 1), {R1, MR3, R2}},
+    {"ld8.nta",		M, OpMXX6aHint (4, 1, 0, 0x03, 3), {R1, MR3, R2}},
+    {"ld1.s",		M, OpMXX6aHint (4, 1, 0, 0x04, 0), {R1, MR3, R2}},
+    {"ld1.s.nt1",	M, OpMXX6aHint (4, 1, 0, 0x04, 1), {R1, MR3, R2}},
+    {"ld1.s.nta",	M, OpMXX6aHint (4, 1, 0, 0x04, 3), {R1, MR3, R2}},
+    {"ld2.s",		M, OpMXX6aHint (4, 1, 0, 0x05, 0), {R1, MR3, R2}},
+    {"ld2.s.nt1",	M, OpMXX6aHint (4, 1, 0, 0x05, 1), {R1, MR3, R2}},
+    {"ld2.s.nta",	M, OpMXX6aHint (4, 1, 0, 0x05, 3), {R1, MR3, R2}},
+    {"ld4.s",		M, OpMXX6aHint (4, 1, 0, 0x06, 0), {R1, MR3, R2}},
+    {"ld4.s.nt1",	M, OpMXX6aHint (4, 1, 0, 0x06, 1), {R1, MR3, R2}},
+    {"ld4.s.nta",	M, OpMXX6aHint (4, 1, 0, 0x06, 3), {R1, MR3, R2}},
+    {"ld8.s",		M, OpMXX6aHint (4, 1, 0, 0x07, 0), {R1, MR3, R2}},
+    {"ld8.s.nt1",	M, OpMXX6aHint (4, 1, 0, 0x07, 1), {R1, MR3, R2}},
+    {"ld8.s.nta",	M, OpMXX6aHint (4, 1, 0, 0x07, 3), {R1, MR3, R2}},
+    {"ld1.a",		M, OpMXX6aHint (4, 1, 0, 0x08, 0), {R1, MR3, R2}},
+    {"ld1.a.nt1",	M, OpMXX6aHint (4, 1, 0, 0x08, 1), {R1, MR3, R2}},
+    {"ld1.a.nta",	M, OpMXX6aHint (4, 1, 0, 0x08, 3), {R1, MR3, R2}},
+    {"ld2.a",		M, OpMXX6aHint (4, 1, 0, 0x09, 0), {R1, MR3, R2}},
+    {"ld2.a.nt1",	M, OpMXX6aHint (4, 1, 0, 0x09, 1), {R1, MR3, R2}},
+    {"ld2.a.nta",	M, OpMXX6aHint (4, 1, 0, 0x09, 3), {R1, MR3, R2}},
+    {"ld4.a",		M, OpMXX6aHint (4, 1, 0, 0x0a, 0), {R1, MR3, R2}},
+    {"ld4.a.nt1",	M, OpMXX6aHint (4, 1, 0, 0x0a, 1), {R1, MR3, R2}},
+    {"ld4.a.nta",	M, OpMXX6aHint (4, 1, 0, 0x0a, 3), {R1, MR3, R2}},
+    {"ld8.a",		M, OpMXX6aHint (4, 1, 0, 0x0b, 0), {R1, MR3, R2}},
+    {"ld8.a.nt1",	M, OpMXX6aHint (4, 1, 0, 0x0b, 1), {R1, MR3, R2}},
+    {"ld8.a.nta",	M, OpMXX6aHint (4, 1, 0, 0x0b, 3), {R1, MR3, R2}},
+    {"ld1.sa",		M, OpMXX6aHint (4, 1, 0, 0x0c, 0), {R1, MR3, R2}},
+    {"ld1.sa.nt1",	M, OpMXX6aHint (4, 1, 0, 0x0c, 1), {R1, MR3, R2}},
+    {"ld1.sa.nta",	M, OpMXX6aHint (4, 1, 0, 0x0c, 3), {R1, MR3, R2}},
+    {"ld2.sa",		M, OpMXX6aHint (4, 1, 0, 0x0d, 0), {R1, MR3, R2}},
+    {"ld2.sa.nt1",	M, OpMXX6aHint (4, 1, 0, 0x0d, 1), {R1, MR3, R2}},
+    {"ld2.sa.nta",	M, OpMXX6aHint (4, 1, 0, 0x0d, 3), {R1, MR3, R2}},
+    {"ld4.sa",		M, OpMXX6aHint (4, 1, 0, 0x0e, 0), {R1, MR3, R2}},
+    {"ld4.sa.nt1",	M, OpMXX6aHint (4, 1, 0, 0x0e, 1), {R1, MR3, R2}},
+    {"ld4.sa.nta",	M, OpMXX6aHint (4, 1, 0, 0x0e, 3), {R1, MR3, R2}},
+    {"ld8.sa",		M, OpMXX6aHint (4, 1, 0, 0x0f, 0), {R1, MR3, R2}},
+    {"ld8.sa.nt1",	M, OpMXX6aHint (4, 1, 0, 0x0f, 1), {R1, MR3, R2}},
+    {"ld8.sa.nta",	M, OpMXX6aHint (4, 1, 0, 0x0f, 3), {R1, MR3, R2}},
+    {"ld1.bias",	M, OpMXX6aHint (4, 1, 0, 0x10, 0), {R1, MR3, R2}},
+    {"ld1.bias.nt1",	M, OpMXX6aHint (4, 1, 0, 0x10, 1), {R1, MR3, R2}},
+    {"ld1.bias.nta",	M, OpMXX6aHint (4, 1, 0, 0x10, 3), {R1, MR3, R2}},
+    {"ld2.bias",	M, OpMXX6aHint (4, 1, 0, 0x11, 0), {R1, MR3, R2}},
+    {"ld2.bias.nt1",	M, OpMXX6aHint (4, 1, 0, 0x11, 1), {R1, MR3, R2}},
+    {"ld2.bias.nta",	M, OpMXX6aHint (4, 1, 0, 0x11, 3), {R1, MR3, R2}},
+    {"ld4.bias",	M, OpMXX6aHint (4, 1, 0, 0x12, 0), {R1, MR3, R2}},
+    {"ld4.bias.nt1",	M, OpMXX6aHint (4, 1, 0, 0x12, 1), {R1, MR3, R2}},
+    {"ld4.bias.nta",	M, OpMXX6aHint (4, 1, 0, 0x12, 3), {R1, MR3, R2}},
+    {"ld8.bias",	M, OpMXX6aHint (4, 1, 0, 0x13, 0), {R1, MR3, R2}},
+    {"ld8.bias.nt1",	M, OpMXX6aHint (4, 1, 0, 0x13, 1), {R1, MR3, R2}},
+    {"ld8.bias.nta",	M, OpMXX6aHint (4, 1, 0, 0x13, 3), {R1, MR3, R2}},
+    {"ld1.acq",		M, OpMXX6aHint (4, 1, 0, 0x14, 0), {R1, MR3, R2}},
+    {"ld1.acq.nt1",	M, OpMXX6aHint (4, 1, 0, 0x14, 1), {R1, MR3, R2}},
+    {"ld1.acq.nta",	M, OpMXX6aHint (4, 1, 0, 0x14, 3), {R1, MR3, R2}},
+    {"ld2.acq",		M, OpMXX6aHint (4, 1, 0, 0x15, 0), {R1, MR3, R2}},
+    {"ld2.acq.nt1",	M, OpMXX6aHint (4, 1, 0, 0x15, 1), {R1, MR3, R2}},
+    {"ld2.acq.nta",	M, OpMXX6aHint (4, 1, 0, 0x15, 3), {R1, MR3, R2}},
+    {"ld4.acq",		M, OpMXX6aHint (4, 1, 0, 0x16, 0), {R1, MR3, R2}},
+    {"ld4.acq.nt1",	M, OpMXX6aHint (4, 1, 0, 0x16, 1), {R1, MR3, R2}},
+    {"ld4.acq.nta",	M, OpMXX6aHint (4, 1, 0, 0x16, 3), {R1, MR3, R2}},
+    {"ld8.acq",		M, OpMXX6aHint (4, 1, 0, 0x17, 0), {R1, MR3, R2}},
+    {"ld8.acq.nt1",	M, OpMXX6aHint (4, 1, 0, 0x17, 1), {R1, MR3, R2}},
+    {"ld8.acq.nta",	M, OpMXX6aHint (4, 1, 0, 0x17, 3), {R1, MR3, R2}},
+    {"ld8.fill",	M, OpMXX6aHint (4, 1, 0, 0x1b, 0), {R1, MR3, R2}},
+    {"ld8.fill.nt1",	M, OpMXX6aHint (4, 1, 0, 0x1b, 1), {R1, MR3, R2}},
+    {"ld8.fill.nta",	M, OpMXX6aHint (4, 1, 0, 0x1b, 3), {R1, MR3, R2}},
+    {"ld1.c.clr",	M, OpMXX6aHint (4, 1, 0, 0x20, 0), {R1, MR3, R2}},
+    {"ld1.c.clr.nt1",	M, OpMXX6aHint (4, 1, 0, 0x20, 1), {R1, MR3, R2}},
+    {"ld1.c.clr.nta",	M, OpMXX6aHint (4, 1, 0, 0x20, 3), {R1, MR3, R2}},
+    {"ld2.c.clr",	M, OpMXX6aHint (4, 1, 0, 0x21, 0), {R1, MR3, R2}},
+    {"ld2.c.clr.nt1",	M, OpMXX6aHint (4, 1, 0, 0x21, 1), {R1, MR3, R2}},
+    {"ld2.c.clr.nta",	M, OpMXX6aHint (4, 1, 0, 0x21, 3), {R1, MR3, R2}},
+    {"ld4.c.clr",	M, OpMXX6aHint (4, 1, 0, 0x22, 0), {R1, MR3, R2}},
+    {"ld4.c.clr.nt1",	M, OpMXX6aHint (4, 1, 0, 0x22, 1), {R1, MR3, R2}},
+    {"ld4.c.clr.nta",	M, OpMXX6aHint (4, 1, 0, 0x22, 3), {R1, MR3, R2}},
+    {"ld8.c.clr",	M, OpMXX6aHint (4, 1, 0, 0x23, 0), {R1, MR3, R2}},
+    {"ld8.c.clr.nt1",	M, OpMXX6aHint (4, 1, 0, 0x23, 1), {R1, MR3, R2}},
+    {"ld8.c.clr.nta",	M, OpMXX6aHint (4, 1, 0, 0x23, 3), {R1, MR3, R2}},
+    {"ld1.c.nc",	M, OpMXX6aHint (4, 1, 0, 0x24, 0), {R1, MR3, R2}},
+    {"ld1.c.nc.nt1",	M, OpMXX6aHint (4, 1, 0, 0x24, 1), {R1, MR3, R2}},
+    {"ld1.c.nc.nta",	M, OpMXX6aHint (4, 1, 0, 0x24, 3), {R1, MR3, R2}},
+    {"ld2.c.nc",	M, OpMXX6aHint (4, 1, 0, 0x25, 0), {R1, MR3, R2}},
+    {"ld2.c.nc.nt1",	M, OpMXX6aHint (4, 1, 0, 0x25, 1), {R1, MR3, R2}},
+    {"ld2.c.nc.nta",	M, OpMXX6aHint (4, 1, 0, 0x25, 3), {R1, MR3, R2}},
+    {"ld4.c.nc",	M, OpMXX6aHint (4, 1, 0, 0x26, 0), {R1, MR3, R2}},
+    {"ld4.c.nc.nt1",	M, OpMXX6aHint (4, 1, 0, 0x26, 1), {R1, MR3, R2}},
+    {"ld4.c.nc.nta",	M, OpMXX6aHint (4, 1, 0, 0x26, 3), {R1, MR3, R2}},
+    {"ld8.c.nc",	M, OpMXX6aHint (4, 1, 0, 0x27, 0), {R1, MR3, R2}},
+    {"ld8.c.nc.nt1",	M, OpMXX6aHint (4, 1, 0, 0x27, 1), {R1, MR3, R2}},
+    {"ld8.c.nc.nta",	M, OpMXX6aHint (4, 1, 0, 0x27, 3), {R1, MR3, R2}},
+    {"ld1.c.clr.acq",	  M, OpMXX6aHint (4, 1, 0, 0x28, 0), {R1, MR3, R2}},
+    {"ld1.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x28, 1), {R1, MR3, R2}},
+    {"ld1.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x28, 3), {R1, MR3, R2}},
+    {"ld2.c.clr.acq",	  M, OpMXX6aHint (4, 1, 0, 0x29, 0), {R1, MR3, R2}},
+    {"ld2.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x29, 1), {R1, MR3, R2}},
+    {"ld2.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x29, 3), {R1, MR3, R2}},
+    {"ld4.c.clr.acq",	  M, OpMXX6aHint (4, 1, 0, 0x2a, 0), {R1, MR3, R2}},
+    {"ld4.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x2a, 1), {R1, MR3, R2}},
+    {"ld4.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x2a, 3), {R1, MR3, R2}},
+    {"ld8.c.clr.acq",	  M, OpMXX6aHint (4, 1, 0, 0x2b, 0), {R1, MR3, R2}},
+    {"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x2b, 1), {R1, MR3, R2}},
+    {"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x2b, 3), {R1, MR3, R2}},
+
+    {"st1",		M, OpMXX6aHint (4, 0, 0, 0x30, 0), {MR3, R2}},
+    {"st1.nta",		M, OpMXX6aHint (4, 0, 0, 0x30, 3), {MR3, R2}},
+    {"st2",		M, OpMXX6aHint (4, 0, 0, 0x31, 0), {MR3, R2}},
+    {"st2.nta",		M, OpMXX6aHint (4, 0, 0, 0x31, 3), {MR3, R2}},
+    {"st4",		M, OpMXX6aHint (4, 0, 0, 0x32, 0), {MR3, R2}},
+    {"st4.nta",		M, OpMXX6aHint (4, 0, 0, 0x32, 3), {MR3, R2}},
+    {"st8",		M, OpMXX6aHint (4, 0, 0, 0x33, 0), {MR3, R2}},
+    {"st8.nta",		M, OpMXX6aHint (4, 0, 0, 0x33, 3), {MR3, R2}},
+    {"st1.rel",		M, OpMXX6aHint (4, 0, 0, 0x34, 0), {MR3, R2}},
+    {"st1.rel.nta",	M, OpMXX6aHint (4, 0, 0, 0x34, 3), {MR3, R2}},
+    {"st2.rel",		M, OpMXX6aHint (4, 0, 0, 0x35, 0), {MR3, R2}},
+    {"st2.rel.nta",	M, OpMXX6aHint (4, 0, 0, 0x35, 3), {MR3, R2}},
+    {"st4.rel",		M, OpMXX6aHint (4, 0, 0, 0x36, 0), {MR3, R2}},
+    {"st4.rel.nta",	M, OpMXX6aHint (4, 0, 0, 0x36, 3), {MR3, R2}},
+    {"st8.rel",		M, OpMXX6aHint (4, 0, 0, 0x37, 0), {MR3, R2}},
+    {"st8.rel.nta",	M, OpMXX6aHint (4, 0, 0, 0x37, 3), {MR3, R2}},
+    {"st8.spill",	M, OpMXX6aHint (4, 0, 0, 0x3b, 0), {MR3, R2}},
+    {"st8.spill.nta",	M, OpMXX6aHint (4, 0, 0, 0x3b, 3), {MR3, R2}},
+
+#define CMPXCHG(c,h)	M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CCV}
+    {"cmpxchg1.acq",		CMPXCHG (0x00, 0)},
+    {"cmpxchg1.acq.nt1",	CMPXCHG (0x00, 1)},
+    {"cmpxchg1.acq.nta",	CMPXCHG (0x00, 3)},
+    {"cmpxchg2.acq",		CMPXCHG (0x01, 0)},
+    {"cmpxchg2.acq.nt1",	CMPXCHG (0x01, 1)},
+    {"cmpxchg2.acq.nta",	CMPXCHG (0x01, 3)},
+    {"cmpxchg4.acq",		CMPXCHG (0x02, 0)},
+    {"cmpxchg4.acq.nt1",	CMPXCHG (0x02, 1)},
+    {"cmpxchg4.acq.nta",	CMPXCHG (0x02, 3)},
+    {"cmpxchg8.acq",		CMPXCHG (0x03, 0)},
+    {"cmpxchg8.acq.nt1",	CMPXCHG (0x03, 1)},
+    {"cmpxchg8.acq.nta",	CMPXCHG (0x03, 3)},
+    {"cmpxchg1.rel",		CMPXCHG (0x04, 0)},
+    {"cmpxchg1.rel.nt1",	CMPXCHG (0x04, 1)},
+    {"cmpxchg1.rel.nta",	CMPXCHG (0x04, 3)},
+    {"cmpxchg2.rel",		CMPXCHG (0x05, 0)},
+    {"cmpxchg2.rel.nt1",	CMPXCHG (0x05, 1)},
+    {"cmpxchg2.rel.nta",	CMPXCHG (0x05, 3)},
+    {"cmpxchg4.rel",		CMPXCHG (0x06, 0)},
+    {"cmpxchg4.rel.nt1",	CMPXCHG (0x06, 1)},
+    {"cmpxchg4.rel.nta",	CMPXCHG (0x06, 3)},
+    {"cmpxchg8.rel",		CMPXCHG (0x07, 0)},
+    {"cmpxchg8.rel.nt1",	CMPXCHG (0x07, 1)},
+    {"cmpxchg8.rel.nta",	CMPXCHG (0x07, 3)},
+#undef CMPXCHG
+    {"xchg1",		  M, OpMXX6aHint (4, 0, 1, 0x08, 0), {R1, MR3, R2}},
+    {"xchg1.nt1",	  M, OpMXX6aHint (4, 0, 1, 0x08, 1), {R1, MR3, R2}},
+    {"xchg1.nta",	  M, OpMXX6aHint (4, 0, 1, 0x08, 3), {R1, MR3, R2}},
+    {"xchg2",		  M, OpMXX6aHint (4, 0, 1, 0x09, 0), {R1, MR3, R2}},
+    {"xchg2.nt1",	  M, OpMXX6aHint (4, 0, 1, 0x09, 1), {R1, MR3, R2}},
+    {"xchg2.nta",	  M, OpMXX6aHint (4, 0, 1, 0x09, 3), {R1, MR3, R2}},
+    {"xchg4",		  M, OpMXX6aHint (4, 0, 1, 0x0a, 0), {R1, MR3, R2}},
+    {"xchg4.nt1",	  M, OpMXX6aHint (4, 0, 1, 0x0a, 1), {R1, MR3, R2}},
+    {"xchg4.nta",	  M, OpMXX6aHint (4, 0, 1, 0x0a, 3), {R1, MR3, R2}},
+    {"xchg8",		  M, OpMXX6aHint (4, 0, 1, 0x0b, 0), {R1, MR3, R2}},
+    {"xchg8.nt1",	  M, OpMXX6aHint (4, 0, 1, 0x0b, 1), {R1, MR3, R2}},
+    {"xchg8.nta",	  M, OpMXX6aHint (4, 0, 1, 0x0b, 3), {R1, MR3, R2}},
+
+    {"fetchadd4.acq",	  M, OpMXX6aHint (4, 0, 1, 0x12, 0), {R1, MR3, INC3}},
+    {"fetchadd4.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x12, 1), {R1, MR3, INC3}},
+    {"fetchadd4.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x12, 3), {R1, MR3, INC3}},
+    {"fetchadd8.acq",	  M, OpMXX6aHint (4, 0, 1, 0x13, 0), {R1, MR3, INC3}},
+    {"fetchadd8.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x13, 1), {R1, MR3, INC3}},
+    {"fetchadd8.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x13, 3), {R1, MR3, INC3}},
+    {"fetchadd4.rel",	  M, OpMXX6aHint (4, 0, 1, 0x16, 0), {R1, MR3, INC3}},
+    {"fetchadd4.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x16, 1), {R1, MR3, INC3}},
+    {"fetchadd4.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x16, 3), {R1, MR3, INC3}},
+    {"fetchadd8.rel",	  M, OpMXX6aHint (4, 0, 1, 0x17, 0), {R1, MR3, INC3}},
+    {"fetchadd8.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x17, 1), {R1, MR3, INC3}},
+    {"fetchadd8.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x17, 3), {R1, MR3, INC3}},
+
+    {"getf.sig",	  M, OpMXX6a (4, 0, 1, 0x1c), {R1, F2}},
+    {"getf.exp",	  M, OpMXX6a (4, 0, 1, 0x1d), {R1, F2}},
+    {"getf.s",		  M, OpMXX6a (4, 0, 1, 0x1e), {R1, F2}},
+    {"getf.d",		  M, OpMXX6a (4, 0, 1, 0x1f), {R1, F2}},
+
+    /* integer load w/increment by immediate */
+    {"ld1",		M, OpX6aHint (5, 0x00, 0), {R1, MR3, IMM9b}},
+    {"ld1.nt1",		M, OpX6aHint (5, 0x00, 1), {R1, MR3, IMM9b}},
+    {"ld1.nta",		M, OpX6aHint (5, 0x00, 3), {R1, MR3, IMM9b}},
+    {"ld2",		M, OpX6aHint (5, 0x01, 0), {R1, MR3, IMM9b}},
+    {"ld2.nt1",		M, OpX6aHint (5, 0x01, 1), {R1, MR3, IMM9b}},
+    {"ld2.nta",		M, OpX6aHint (5, 0x01, 3), {R1, MR3, IMM9b}},
+    {"ld4",		M, OpX6aHint (5, 0x02, 0), {R1, MR3, IMM9b}},
+    {"ld4.nt1",		M, OpX6aHint (5, 0x02, 1), {R1, MR3, IMM9b}},
+    {"ld4.nta",		M, OpX6aHint (5, 0x02, 3), {R1, MR3, IMM9b}},
+    {"ld8",		M, OpX6aHint (5, 0x03, 0), {R1, MR3, IMM9b}},
+    {"ld8.nt1",		M, OpX6aHint (5, 0x03, 1), {R1, MR3, IMM9b}},
+    {"ld8.nta",		M, OpX6aHint (5, 0x03, 3), {R1, MR3, IMM9b}},
+    {"ld1.s",		M, OpX6aHint (5, 0x04, 0), {R1, MR3, IMM9b}},
+    {"ld1.s.nt1",	M, OpX6aHint (5, 0x04, 1), {R1, MR3, IMM9b}},
+    {"ld1.s.nta",	M, OpX6aHint (5, 0x04, 3), {R1, MR3, IMM9b}},
+    {"ld2.s",		M, OpX6aHint (5, 0x05, 0), {R1, MR3, IMM9b}},
+    {"ld2.s.nt1",	M, OpX6aHint (5, 0x05, 1), {R1, MR3, IMM9b}},
+    {"ld2.s.nta",	M, OpX6aHint (5, 0x05, 3), {R1, MR3, IMM9b}},
+    {"ld4.s",		M, OpX6aHint (5, 0x06, 0), {R1, MR3, IMM9b}},
+    {"ld4.s.nt1",	M, OpX6aHint (5, 0x06, 1), {R1, MR3, IMM9b}},
+    {"ld4.s.nta",	M, OpX6aHint (5, 0x06, 3), {R1, MR3, IMM9b}},
+    {"ld8.s",		M, OpX6aHint (5, 0x07, 0), {R1, MR3, IMM9b}},
+    {"ld8.s.nt1",	M, OpX6aHint (5, 0x07, 1), {R1, MR3, IMM9b}},
+    {"ld8.s.nta",	M, OpX6aHint (5, 0x07, 3), {R1, MR3, IMM9b}},
+    {"ld1.a",		M, OpX6aHint (5, 0x08, 0), {R1, MR3, IMM9b}},
+    {"ld1.a.nt1",	M, OpX6aHint (5, 0x08, 1), {R1, MR3, IMM9b}},
+    {"ld1.a.nta",	M, OpX6aHint (5, 0x08, 3), {R1, MR3, IMM9b}},
+    {"ld2.a",		M, OpX6aHint (5, 0x09, 0), {R1, MR3, IMM9b}},
+    {"ld2.a.nt1",	M, OpX6aHint (5, 0x09, 1), {R1, MR3, IMM9b}},
+    {"ld2.a.nta",	M, OpX6aHint (5, 0x09, 3), {R1, MR3, IMM9b}},
+    {"ld4.a",		M, OpX6aHint (5, 0x0a, 0), {R1, MR3, IMM9b}},
+    {"ld4.a.nt1",	M, OpX6aHint (5, 0x0a, 1), {R1, MR3, IMM9b}},
+    {"ld4.a.nta",	M, OpX6aHint (5, 0x0a, 3), {R1, MR3, IMM9b}},
+    {"ld8.a",		M, OpX6aHint (5, 0x0b, 0), {R1, MR3, IMM9b}},
+    {"ld8.a.nt1",	M, OpX6aHint (5, 0x0b, 1), {R1, MR3, IMM9b}},
+    {"ld8.a.nta",	M, OpX6aHint (5, 0x0b, 3), {R1, MR3, IMM9b}},
+    {"ld1.sa",		M, OpX6aHint (5, 0x0c, 0), {R1, MR3, IMM9b}},
+    {"ld1.sa.nt1",	M, OpX6aHint (5, 0x0c, 1), {R1, MR3, IMM9b}},
+    {"ld1.sa.nta",	M, OpX6aHint (5, 0x0c, 3), {R1, MR3, IMM9b}},
+    {"ld2.sa",		M, OpX6aHint (5, 0x0d, 0), {R1, MR3, IMM9b}},
+    {"ld2.sa.nt1",	M, OpX6aHint (5, 0x0d, 1), {R1, MR3, IMM9b}},
+    {"ld2.sa.nta",	M, OpX6aHint (5, 0x0d, 3), {R1, MR3, IMM9b}},
+    {"ld4.sa",		M, OpX6aHint (5, 0x0e, 0), {R1, MR3, IMM9b}},
+    {"ld4.sa.nt1",	M, OpX6aHint (5, 0x0e, 1), {R1, MR3, IMM9b}},
+    {"ld4.sa.nta",	M, OpX6aHint (5, 0x0e, 3), {R1, MR3, IMM9b}},
+    {"ld8.sa",		M, OpX6aHint (5, 0x0f, 0), {R1, MR3, IMM9b}},
+    {"ld8.sa.nt1",	M, OpX6aHint (5, 0x0f, 1), {R1, MR3, IMM9b}},
+    {"ld8.sa.nta",	M, OpX6aHint (5, 0x0f, 3), {R1, MR3, IMM9b}},
+    {"ld1.bias",	M, OpX6aHint (5, 0x10, 0), {R1, MR3, IMM9b}},
+    {"ld1.bias.nt1",	M, OpX6aHint (5, 0x10, 1), {R1, MR3, IMM9b}},
+    {"ld1.bias.nta",	M, OpX6aHint (5, 0x10, 3), {R1, MR3, IMM9b}},
+    {"ld2.bias",	M, OpX6aHint (5, 0x11, 0), {R1, MR3, IMM9b}},
+    {"ld2.bias.nt1",	M, OpX6aHint (5, 0x11, 1), {R1, MR3, IMM9b}},
+    {"ld2.bias.nta",	M, OpX6aHint (5, 0x11, 3), {R1, MR3, IMM9b}},
+    {"ld4.bias",	M, OpX6aHint (5, 0x12, 0), {R1, MR3, IMM9b}},
+    {"ld4.bias.nt1",	M, OpX6aHint (5, 0x12, 1), {R1, MR3, IMM9b}},
+    {"ld4.bias.nta",	M, OpX6aHint (5, 0x12, 3), {R1, MR3, IMM9b}},
+    {"ld8.bias",	M, OpX6aHint (5, 0x13, 0), {R1, MR3, IMM9b}},
+    {"ld8.bias.nt1",	M, OpX6aHint (5, 0x13, 1), {R1, MR3, IMM9b}},
+    {"ld8.bias.nta",	M, OpX6aHint (5, 0x13, 3), {R1, MR3, IMM9b}},
+    {"ld1.acq",		M, OpX6aHint (5, 0x14, 0), {R1, MR3, IMM9b}},
+    {"ld1.acq.nt1",	M, OpX6aHint (5, 0x14, 1), {R1, MR3, IMM9b}},
+    {"ld1.acq.nta",	M, OpX6aHint (5, 0x14, 3), {R1, MR3, IMM9b}},
+    {"ld2.acq",		M, OpX6aHint (5, 0x15, 0), {R1, MR3, IMM9b}},
+    {"ld2.acq.nt1",	M, OpX6aHint (5, 0x15, 1), {R1, MR3, IMM9b}},
+    {"ld2.acq.nta",	M, OpX6aHint (5, 0x15, 3), {R1, MR3, IMM9b}},
+    {"ld4.acq",		M, OpX6aHint (5, 0x16, 0), {R1, MR3, IMM9b}},
+    {"ld4.acq.nt1",	M, OpX6aHint (5, 0x16, 1), {R1, MR3, IMM9b}},
+    {"ld4.acq.nta",	M, OpX6aHint (5, 0x16, 3), {R1, MR3, IMM9b}},
+    {"ld8.acq",		M, OpX6aHint (5, 0x17, 0), {R1, MR3, IMM9b}},
+    {"ld8.acq.nt1",	M, OpX6aHint (5, 0x17, 1), {R1, MR3, IMM9b}},
+    {"ld8.acq.nta",	M, OpX6aHint (5, 0x17, 3), {R1, MR3, IMM9b}},
+    {"ld8.fill",	M, OpX6aHint (5, 0x1b, 0), {R1, MR3, IMM9b}},
+    {"ld8.fill.nt1",	M, OpX6aHint (5, 0x1b, 1), {R1, MR3, IMM9b}},
+    {"ld8.fill.nta",	M, OpX6aHint (5, 0x1b, 3), {R1, MR3, IMM9b}},
+    {"ld1.c.clr",	M, OpX6aHint (5, 0x20, 0), {R1, MR3, IMM9b}},
+    {"ld1.c.clr.nt1",	M, OpX6aHint (5, 0x20, 1), {R1, MR3, IMM9b}},
+    {"ld1.c.clr.nta",	M, OpX6aHint (5, 0x20, 3), {R1, MR3, IMM9b}},
+    {"ld2.c.clr",	M, OpX6aHint (5, 0x21, 0), {R1, MR3, IMM9b}},
+    {"ld2.c.clr.nt1",	M, OpX6aHint (5, 0x21, 1), {R1, MR3, IMM9b}},
+    {"ld2.c.clr.nta",	M, OpX6aHint (5, 0x21, 3), {R1, MR3, IMM9b}},
+    {"ld4.c.clr",	M, OpX6aHint (5, 0x22, 0), {R1, MR3, IMM9b}},
+    {"ld4.c.clr.nt1",	M, OpX6aHint (5, 0x22, 1), {R1, MR3, IMM9b}},
+    {"ld4.c.clr.nta",	M, OpX6aHint (5, 0x22, 3), {R1, MR3, IMM9b}},
+    {"ld8.c.clr",	M, OpX6aHint (5, 0x23, 0), {R1, MR3, IMM9b}},
+    {"ld8.c.clr.nt1",	M, OpX6aHint (5, 0x23, 1), {R1, MR3, IMM9b}},
+    {"ld8.c.clr.nta",	M, OpX6aHint (5, 0x23, 3), {R1, MR3, IMM9b}},
+    {"ld1.c.nc",	M, OpX6aHint (5, 0x24, 0), {R1, MR3, IMM9b}},
+    {"ld1.c.nc.nt1",	M, OpX6aHint (5, 0x24, 1), {R1, MR3, IMM9b}},
+    {"ld1.c.nc.nta",	M, OpX6aHint (5, 0x24, 3), {R1, MR3, IMM9b}},
+    {"ld2.c.nc",	M, OpX6aHint (5, 0x25, 0), {R1, MR3, IMM9b}},
+    {"ld2.c.nc.nt1",	M, OpX6aHint (5, 0x25, 1), {R1, MR3, IMM9b}},
+    {"ld2.c.nc.nta",	M, OpX6aHint (5, 0x25, 3), {R1, MR3, IMM9b}},
+    {"ld4.c.nc",	M, OpX6aHint (5, 0x26, 0), {R1, MR3, IMM9b}},
+    {"ld4.c.nc.nt1",	M, OpX6aHint (5, 0x26, 1), {R1, MR3, IMM9b}},
+    {"ld4.c.nc.nta",	M, OpX6aHint (5, 0x26, 3), {R1, MR3, IMM9b}},
+    {"ld8.c.nc",	M, OpX6aHint (5, 0x27, 0), {R1, MR3, IMM9b}},
+    {"ld8.c.nc.nt1",	M, OpX6aHint (5, 0x27, 1), {R1, MR3, IMM9b}},
+    {"ld8.c.nc.nta",	M, OpX6aHint (5, 0x27, 3), {R1, MR3, IMM9b}},
+    {"ld1.c.clr.acq",	  M, OpX6aHint (5, 0x28, 0), {R1, MR3, IMM9b}},
+    {"ld1.c.clr.acq.nt1", M, OpX6aHint (5, 0x28, 1), {R1, MR3, IMM9b}},
+    {"ld1.c.clr.acq.nta", M, OpX6aHint (5, 0x28, 3), {R1, MR3, IMM9b}},
+    {"ld2.c.clr.acq",	  M, OpX6aHint (5, 0x29, 0), {R1, MR3, IMM9b}},
+    {"ld2.c.clr.acq.nt1", M, OpX6aHint (5, 0x29, 1), {R1, MR3, IMM9b}},
+    {"ld2.c.clr.acq.nta", M, OpX6aHint (5, 0x29, 3), {R1, MR3, IMM9b}},
+    {"ld4.c.clr.acq",	  M, OpX6aHint (5, 0x2a, 0), {R1, MR3, IMM9b}},
+    {"ld4.c.clr.acq.nt1", M, OpX6aHint (5, 0x2a, 1), {R1, MR3, IMM9b}},
+    {"ld4.c.clr.acq.nta", M, OpX6aHint (5, 0x2a, 3), {R1, MR3, IMM9b}},
+    {"ld8.c.clr.acq",	  M, OpX6aHint (5, 0x2b, 0), {R1, MR3, IMM9b}},
+    {"ld8.c.clr.acq.nt1", M, OpX6aHint (5, 0x2b, 1), {R1, MR3, IMM9b}},
+    {"ld8.c.clr.acq.nta", M, OpX6aHint (5, 0x2b, 3), {R1, MR3, IMM9b}},
+
+    /* store w/increment by immediate */
+    {"st1",		M, OpX6aHint (5, 0x30, 0), {MR3, R2, IMM9a}},
+    {"st1.nta",		M, OpX6aHint (5, 0x30, 3), {MR3, R2, IMM9a}},
+    {"st2",		M, OpX6aHint (5, 0x31, 0), {MR3, R2, IMM9a}},
+    {"st2.nta",		M, OpX6aHint (5, 0x31, 3), {MR3, R2, IMM9a}},
+    {"st4",		M, OpX6aHint (5, 0x32, 0), {MR3, R2, IMM9a}},
+    {"st4.nta",		M, OpX6aHint (5, 0x32, 3), {MR3, R2, IMM9a}},
+    {"st8",		M, OpX6aHint (5, 0x33, 0), {MR3, R2, IMM9a}},
+    {"st8.nta",		M, OpX6aHint (5, 0x33, 3), {MR3, R2, IMM9a}},
+    {"st1.rel",		M, OpX6aHint (5, 0x34, 0), {MR3, R2, IMM9a}},
+    {"st1.rel.nta",	M, OpX6aHint (5, 0x34, 3), {MR3, R2, IMM9a}},
+    {"st2.rel",		M, OpX6aHint (5, 0x35, 0), {MR3, R2, IMM9a}},
+    {"st2.rel.nta",	M, OpX6aHint (5, 0x35, 3), {MR3, R2, IMM9a}},
+    {"st4.rel",		M, OpX6aHint (5, 0x36, 0), {MR3, R2, IMM9a}},
+    {"st4.rel.nta",	M, OpX6aHint (5, 0x36, 3), {MR3, R2, IMM9a}},
+    {"st8.rel",		M, OpX6aHint (5, 0x37, 0), {MR3, R2, IMM9a}},
+    {"st8.rel.nta",	M, OpX6aHint (5, 0x37, 3), {MR3, R2, IMM9a}},
+    {"st8.spill",	M, OpX6aHint (5, 0x3b, 0), {MR3, R2, IMM9a}},
+    {"st8.spill.nta",	M, OpX6aHint (5, 0x3b, 3), {MR3, R2, IMM9a}},
+
+    /* floating-point load */
+    {"ldfs",		M, OpMXX6aHint (6, 0, 0, 0x02, 0), {F1, MR3}},
+    {"ldfs.nt1",	M, OpMXX6aHint (6, 0, 0, 0x02, 1), {F1, MR3}},
+    {"ldfs.nta",	M, OpMXX6aHint (6, 0, 0, 0x02, 3), {F1, MR3}},
+    {"ldfd",		M, OpMXX6aHint (6, 0, 0, 0x03, 0), {F1, MR3}},
+    {"ldfd.nt1",	M, OpMXX6aHint (6, 0, 0, 0x03, 1), {F1, MR3}},
+    {"ldfd.nta",	M, OpMXX6aHint (6, 0, 0, 0x03, 3), {F1, MR3}},
+    {"ldf8",		M, OpMXX6aHint (6, 0, 0, 0x01, 0), {F1, MR3}},
+    {"ldf8.nt1",	M, OpMXX6aHint (6, 0, 0, 0x01, 1), {F1, MR3}},
+    {"ldf8.nta",	M, OpMXX6aHint (6, 0, 0, 0x01, 3), {F1, MR3}},
+    {"ldfe",		M, OpMXX6aHint (6, 0, 0, 0x00, 0), {F1, MR3}},
+    {"ldfe.nt1",	M, OpMXX6aHint (6, 0, 0, 0x00, 1), {F1, MR3}},
+    {"ldfe.nta",	M, OpMXX6aHint (6, 0, 0, 0x00, 3), {F1, MR3}},
+    {"ldfs.s",		M, OpMXX6aHint (6, 0, 0, 0x06, 0), {F1, MR3}},
+    {"ldfs.s.nt1",	M, OpMXX6aHint (6, 0, 0, 0x06, 1), {F1, MR3}},
+    {"ldfs.s.nta",	M, OpMXX6aHint (6, 0, 0, 0x06, 3), {F1, MR3}},
+    {"ldfd.s",		M, OpMXX6aHint (6, 0, 0, 0x07, 0), {F1, MR3}},
+    {"ldfd.s.nt1",	M, OpMXX6aHint (6, 0, 0, 0x07, 1), {F1, MR3}},
+    {"ldfd.s.nta",	M, OpMXX6aHint (6, 0, 0, 0x07, 3), {F1, MR3}},
+    {"ldf8.s",		M, OpMXX6aHint (6, 0, 0, 0x05, 0), {F1, MR3}},
+    {"ldf8.s.nt1",	M, OpMXX6aHint (6, 0, 0, 0x05, 1), {F1, MR3}},
+    {"ldf8.s.nta",	M, OpMXX6aHint (6, 0, 0, 0x05, 3), {F1, MR3}},
+    {"ldfe.s",		M, OpMXX6aHint (6, 0, 0, 0x04, 0), {F1, MR3}},
+    {"ldfe.s.nt1",	M, OpMXX6aHint (6, 0, 0, 0x04, 1), {F1, MR3}},
+    {"ldfe.s.nta",	M, OpMXX6aHint (6, 0, 0, 0x04, 3), {F1, MR3}},
+    {"ldfs.a",		M, OpMXX6aHint (6, 0, 0, 0x0a, 0), {F1, MR3}},
+    {"ldfs.a.nt1",	M, OpMXX6aHint (6, 0, 0, 0x0a, 1), {F1, MR3}},
+    {"ldfs.a.nta",	M, OpMXX6aHint (6, 0, 0, 0x0a, 3), {F1, MR3}},
+    {"ldfd.a",		M, OpMXX6aHint (6, 0, 0, 0x0b, 0), {F1, MR3}},
+    {"ldfd.a.nt1",	M, OpMXX6aHint (6, 0, 0, 0x0b, 1), {F1, MR3}},
+    {"ldfd.a.nta",	M, OpMXX6aHint (6, 0, 0, 0x0b, 3), {F1, MR3}},
+    {"ldf8.a",		M, OpMXX6aHint (6, 0, 0, 0x09, 0), {F1, MR3}},
+    {"ldf8.a.nt1",	M, OpMXX6aHint (6, 0, 0, 0x09, 1), {F1, MR3}},
+    {"ldf8.a.nta",	M, OpMXX6aHint (6, 0, 0, 0x09, 3), {F1, MR3}},
+    {"ldfe.a",		M, OpMXX6aHint (6, 0, 0, 0x08, 0), {F1, MR3}},
+    {"ldfe.a.nt1",	M, OpMXX6aHint (6, 0, 0, 0x08, 1), {F1, MR3}},
+    {"ldfe.a.nta",	M, OpMXX6aHint (6, 0, 0, 0x08, 3), {F1, MR3}},
+    {"ldfs.sa",		M, OpMXX6aHint (6, 0, 0, 0x0e, 0), {F1, MR3}},
+    {"ldfs.sa.nt1",	M, OpMXX6aHint (6, 0, 0, 0x0e, 1), {F1, MR3}},
+    {"ldfs.sa.nta",	M, OpMXX6aHint (6, 0, 0, 0x0e, 3), {F1, MR3}},
+    {"ldfd.sa",		M, OpMXX6aHint (6, 0, 0, 0x0f, 0), {F1, MR3}},
+    {"ldfd.sa.nt1",	M, OpMXX6aHint (6, 0, 0, 0x0f, 1), {F1, MR3}},
+    {"ldfd.sa.nta",	M, OpMXX6aHint (6, 0, 0, 0x0f, 3), {F1, MR3}},
+    {"ldf8.sa",		M, OpMXX6aHint (6, 0, 0, 0x0d, 0), {F1, MR3}},
+    {"ldf8.sa.nt1",	M, OpMXX6aHint (6, 0, 0, 0x0d, 1), {F1, MR3}},
+    {"ldf8.sa.nta",	M, OpMXX6aHint (6, 0, 0, 0x0d, 3), {F1, MR3}},
+    {"ldfe.sa",		M, OpMXX6aHint (6, 0, 0, 0x0c, 0), {F1, MR3}},
+    {"ldfe.sa.nt1",	M, OpMXX6aHint (6, 0, 0, 0x0c, 1), {F1, MR3}},
+    {"ldfe.sa.nta",	M, OpMXX6aHint (6, 0, 0, 0x0c, 3), {F1, MR3}},
+    {"ldf.fill",	M, OpMXX6aHint (6, 0, 0, 0x1b, 0), {F1, MR3}},
+    {"ldf.fill.nt1",	M, OpMXX6aHint (6, 0, 0, 0x1b, 1), {F1, MR3}},
+    {"ldf.fill.nta",	M, OpMXX6aHint (6, 0, 0, 0x1b, 3), {F1, MR3}},
+    {"ldfs.c.clr",	M, OpMXX6aHint (6, 0, 0, 0x22, 0), {F1, MR3}},
+    {"ldfs.c.clr.nt1",	M, OpMXX6aHint (6, 0, 0, 0x22, 1), {F1, MR3}},
+    {"ldfs.c.clr.nta",	M, OpMXX6aHint (6, 0, 0, 0x22, 3), {F1, MR3}},
+    {"ldfd.c.clr",	M, OpMXX6aHint (6, 0, 0, 0x23, 0), {F1, MR3}},
+    {"ldfd.c.clr.nt1",	M, OpMXX6aHint (6, 0, 0, 0x23, 1), {F1, MR3}},
+    {"ldfd.c.clr.nta",	M, OpMXX6aHint (6, 0, 0, 0x23, 3), {F1, MR3}},
+    {"ldf8.c.clr",	M, OpMXX6aHint (6, 0, 0, 0x21, 0), {F1, MR3}},
+    {"ldf8.c.clr.nt1",	M, OpMXX6aHint (6, 0, 0, 0x21, 1), {F1, MR3}},
+    {"ldf8.c.clr.nta",	M, OpMXX6aHint (6, 0, 0, 0x21, 3), {F1, MR3}},
+    {"ldfe.c.clr",	M, OpMXX6aHint (6, 0, 0, 0x20, 0), {F1, MR3}},
+    {"ldfe.c.clr.nt1",	M, OpMXX6aHint (6, 0, 0, 0x20, 1), {F1, MR3}},
+    {"ldfe.c.clr.nta",	M, OpMXX6aHint (6, 0, 0, 0x20, 3), {F1, MR3}},
+    {"ldfs.c.nc",	M, OpMXX6aHint (6, 0, 0, 0x26, 0), {F1, MR3}},
+    {"ldfs.c.nc.nt1",	M, OpMXX6aHint (6, 0, 0, 0x26, 1), {F1, MR3}},
+    {"ldfs.c.nc.nta",	M, OpMXX6aHint (6, 0, 0, 0x26, 3), {F1, MR3}},
+    {"ldfd.c.nc",	M, OpMXX6aHint (6, 0, 0, 0x27, 0), {F1, MR3}},
+    {"ldfd.c.nc.nt1",	M, OpMXX6aHint (6, 0, 0, 0x27, 1), {F1, MR3}},
+    {"ldfd.c.nc.nta",	M, OpMXX6aHint (6, 0, 0, 0x27, 3), {F1, MR3}},
+    {"ldf8.c.nc",	M, OpMXX6aHint (6, 0, 0, 0x25, 0), {F1, MR3}},
+    {"ldf8.c.nc.nt1",	M, OpMXX6aHint (6, 0, 0, 0x25, 1), {F1, MR3}},
+    {"ldf8.c.nc.nta",	M, OpMXX6aHint (6, 0, 0, 0x25, 3), {F1, MR3}},
+    {"ldfe.c.nc",	M, OpMXX6aHint (6, 0, 0, 0x24, 0), {F1, MR3}},
+    {"ldfe.c.nc.nt1",	M, OpMXX6aHint (6, 0, 0, 0x24, 1), {F1, MR3}},
+    {"ldfe.c.nc.nta",	M, OpMXX6aHint (6, 0, 0, 0x24, 3), {F1, MR3}},
+
+    {"ldfs",		M, OpMXX6aHint (6, 1, 0, 0x02, 0), {F1, MR3, R2}},
+    {"ldfs.nt1",	M, OpMXX6aHint (6, 1, 0, 0x02, 1), {F1, MR3, R2}},
+    {"ldfs.nta",	M, OpMXX6aHint (6, 1, 0, 0x02, 3), {F1, MR3, R2}},
+    {"ldfd",		M, OpMXX6aHint (6, 1, 0, 0x03, 0), {F1, MR3, R2}},
+    {"ldfd.nt1",	M, OpMXX6aHint (6, 1, 0, 0x03, 1), {F1, MR3, R2}},
+    {"ldfd.nta",	M, OpMXX6aHint (6, 1, 0, 0x03, 3), {F1, MR3, R2}},
+    {"ldf8",		M, OpMXX6aHint (6, 1, 0, 0x01, 0), {F1, MR3, R2}},
+    {"ldf8.nt1",	M, OpMXX6aHint (6, 1, 0, 0x01, 1), {F1, MR3, R2}},
+    {"ldf8.nta",	M, OpMXX6aHint (6, 1, 0, 0x01, 3), {F1, MR3, R2}},
+    {"ldfe",		M, OpMXX6aHint (6, 1, 0, 0x00, 0), {F1, MR3, R2}},
+    {"ldfe.nt1",	M, OpMXX6aHint (6, 1, 0, 0x00, 1), {F1, MR3, R2}},
+    {"ldfe.nta",	M, OpMXX6aHint (6, 1, 0, 0x00, 3), {F1, MR3, R2}},
+    {"ldfs.s",		M, OpMXX6aHint (6, 1, 0, 0x06, 0), {F1, MR3, R2}},
+    {"ldfs.s.nt1",	M, OpMXX6aHint (6, 1, 0, 0x06, 1), {F1, MR3, R2}},
+    {"ldfs.s.nta",	M, OpMXX6aHint (6, 1, 0, 0x06, 3), {F1, MR3, R2}},
+    {"ldfd.s",		M, OpMXX6aHint (6, 1, 0, 0x07, 0), {F1, MR3, R2}},
+    {"ldfd.s.nt1",	M, OpMXX6aHint (6, 1, 0, 0x07, 1), {F1, MR3, R2}},
+    {"ldfd.s.nta",	M, OpMXX6aHint (6, 1, 0, 0x07, 3), {F1, MR3, R2}},
+    {"ldf8.s",		M, OpMXX6aHint (6, 1, 0, 0x05, 0), {F1, MR3, R2}},
+    {"ldf8.s.nt1",	M, OpMXX6aHint (6, 1, 0, 0x05, 1), {F1, MR3, R2}},
+    {"ldf8.s.nta",	M, OpMXX6aHint (6, 1, 0, 0x05, 3), {F1, MR3, R2}},
+    {"ldfe.s",		M, OpMXX6aHint (6, 1, 0, 0x04, 0), {F1, MR3, R2}},
+    {"ldfe.s.nt1",	M, OpMXX6aHint (6, 1, 0, 0x04, 1), {F1, MR3, R2}},
+    {"ldfe.s.nta",	M, OpMXX6aHint (6, 1, 0, 0x04, 3), {F1, MR3, R2}},
+    {"ldfs.a",		M, OpMXX6aHint (6, 1, 0, 0x0a, 0), {F1, MR3, R2}},
+    {"ldfs.a.nt1",	M, OpMXX6aHint (6, 1, 0, 0x0a, 1), {F1, MR3, R2}},
+    {"ldfs.a.nta",	M, OpMXX6aHint (6, 1, 0, 0x0a, 3), {F1, MR3, R2}},
+    {"ldfd.a",		M, OpMXX6aHint (6, 1, 0, 0x0b, 0), {F1, MR3, R2}},
+    {"ldfd.a.nt1",	M, OpMXX6aHint (6, 1, 0, 0x0b, 1), {F1, MR3, R2}},
+    {"ldfd.a.nta",	M, OpMXX6aHint (6, 1, 0, 0x0b, 3), {F1, MR3, R2}},
+    {"ldf8.a",		M, OpMXX6aHint (6, 1, 0, 0x09, 0), {F1, MR3, R2}},
+    {"ldf8.a.nt1",	M, OpMXX6aHint (6, 1, 0, 0x09, 1), {F1, MR3, R2}},
+    {"ldf8.a.nta",	M, OpMXX6aHint (6, 1, 0, 0x09, 3), {F1, MR3, R2}},
+    {"ldfe.a",		M, OpMXX6aHint (6, 1, 0, 0x08, 0), {F1, MR3, R2}},
+    {"ldfe.a.nt1",	M, OpMXX6aHint (6, 1, 0, 0x08, 1), {F1, MR3, R2}},
+    {"ldfe.a.nta",	M, OpMXX6aHint (6, 1, 0, 0x08, 3), {F1, MR3, R2}},
+    {"ldfs.sa",		M, OpMXX6aHint (6, 1, 0, 0x0e, 0), {F1, MR3, R2}},
+    {"ldfs.sa.nt1",	M, OpMXX6aHint (6, 1, 0, 0x0e, 1), {F1, MR3, R2}},
+    {"ldfs.sa.nta",	M, OpMXX6aHint (6, 1, 0, 0x0e, 3), {F1, MR3, R2}},
+    {"ldfd.sa",		M, OpMXX6aHint (6, 1, 0, 0x0f, 0), {F1, MR3, R2}},
+    {"ldfd.sa.nt1",	M, OpMXX6aHint (6, 1, 0, 0x0f, 1), {F1, MR3, R2}},
+    {"ldfd.sa.nta",	M, OpMXX6aHint (6, 1, 0, 0x0f, 3), {F1, MR3, R2}},
+    {"ldf8.sa",		M, OpMXX6aHint (6, 1, 0, 0x0d, 0), {F1, MR3, R2}},
+    {"ldf8.sa.nt1",	M, OpMXX6aHint (6, 1, 0, 0x0d, 1), {F1, MR3, R2}},
+    {"ldf8.sa.nta",	M, OpMXX6aHint (6, 1, 0, 0x0d, 3), {F1, MR3, R2}},
+    {"ldfe.sa",		M, OpMXX6aHint (6, 1, 0, 0x0c, 0), {F1, MR3, R2}},
+    {"ldfe.sa.nt1",	M, OpMXX6aHint (6, 1, 0, 0x0c, 1), {F1, MR3, R2}},
+    {"ldfe.sa.nta",	M, OpMXX6aHint (6, 1, 0, 0x0c, 3), {F1, MR3, R2}},
+    {"ldf.fill",	M, OpMXX6aHint (6, 1, 0, 0x1b, 0), {F1, MR3, R2}},
+    {"ldf.fill.nt1",	M, OpMXX6aHint (6, 1, 0, 0x1b, 1), {F1, MR3, R2}},
+    {"ldf.fill.nta",	M, OpMXX6aHint (6, 1, 0, 0x1b, 3), {F1, MR3, R2}},
+    {"ldfs.c.clr",	M, OpMXX6aHint (6, 1, 0, 0x22, 0), {F1, MR3, R2}},
+    {"ldfs.c.clr.nt1",	M, OpMXX6aHint (6, 1, 0, 0x22, 1), {F1, MR3, R2}},
+    {"ldfs.c.clr.nta",	M, OpMXX6aHint (6, 1, 0, 0x22, 3), {F1, MR3, R2}},
+    {"ldfd.c.clr",	M, OpMXX6aHint (6, 1, 0, 0x23, 0), {F1, MR3, R2}},
+    {"ldfd.c.clr.nt1",	M, OpMXX6aHint (6, 1, 0, 0x23, 1), {F1, MR3, R2}},
+    {"ldfd.c.clr.nta",	M, OpMXX6aHint (6, 1, 0, 0x23, 3), {F1, MR3, R2}},
+    {"ldf8.c.clr",	M, OpMXX6aHint (6, 1, 0, 0x21, 0), {F1, MR3, R2}},
+    {"ldf8.c.clr.nt1",	M, OpMXX6aHint (6, 1, 0, 0x21, 1), {F1, MR3, R2}},
+    {"ldf8.c.clr.nta",	M, OpMXX6aHint (6, 1, 0, 0x21, 3), {F1, MR3, R2}},
+    {"ldfe.c.clr",	M, OpMXX6aHint (6, 1, 0, 0x20, 0), {F1, MR3, R2}},
+    {"ldfe.c.clr.nt1",	M, OpMXX6aHint (6, 1, 0, 0x20, 1), {F1, MR3, R2}},
+    {"ldfe.c.clr.nta",	M, OpMXX6aHint (6, 1, 0, 0x20, 3), {F1, MR3, R2}},
+    {"ldfs.c.nc",	M, OpMXX6aHint (6, 1, 0, 0x26, 0), {F1, MR3, R2}},
+    {"ldfs.c.nc.nt1",	M, OpMXX6aHint (6, 1, 0, 0x26, 1), {F1, MR3, R2}},
+    {"ldfs.c.nc.nta",	M, OpMXX6aHint (6, 1, 0, 0x26, 3), {F1, MR3, R2}},
+    {"ldfd.c.nc",	M, OpMXX6aHint (6, 1, 0, 0x27, 0), {F1, MR3, R2}},
+    {"ldfd.c.nc.nt1",	M, OpMXX6aHint (6, 1, 0, 0x27, 1), {F1, MR3, R2}},
+    {"ldfd.c.nc.nta",	M, OpMXX6aHint (6, 1, 0, 0x27, 3), {F1, MR3, R2}},
+    {"ldf8.c.nc",	M, OpMXX6aHint (6, 1, 0, 0x25, 0), {F1, MR3, R2}},
+    {"ldf8.c.nc.nt1",	M, OpMXX6aHint (6, 1, 0, 0x25, 1), {F1, MR3, R2}},
+    {"ldf8.c.nc.nta",	M, OpMXX6aHint (6, 1, 0, 0x25, 3), {F1, MR3, R2}},
+    {"ldfe.c.nc",	M, OpMXX6aHint (6, 1, 0, 0x24, 0), {F1, MR3, R2}},
+    {"ldfe.c.nc.nt1",	M, OpMXX6aHint (6, 1, 0, 0x24, 1), {F1, MR3, R2}},
+    {"ldfe.c.nc.nta",	M, OpMXX6aHint (6, 1, 0, 0x24, 3), {F1, MR3, R2}},
+
+    /* floating-point store */
+    {"stfs",		M, OpMXX6aHint (6, 0, 0, 0x32, 0), {MR3, F2}},
+    {"stfs.nta",	M, OpMXX6aHint (6, 0, 0, 0x32, 3), {MR3, F2}},
+    {"stfd",		M, OpMXX6aHint (6, 0, 0, 0x33, 0), {MR3, F2}},
+    {"stfd.nta",	M, OpMXX6aHint (6, 0, 0, 0x33, 3), {MR3, F2}},
+    {"stf8",		M, OpMXX6aHint (6, 0, 0, 0x31, 0), {MR3, F2}},
+    {"stf8.nta",	M, OpMXX6aHint (6, 0, 0, 0x31, 3), {MR3, F2}},
+    {"stfe",		M, OpMXX6aHint (6, 0, 0, 0x30, 0), {MR3, F2}},
+    {"stfe.nta",	M, OpMXX6aHint (6, 0, 0, 0x30, 3), {MR3, F2}},
+    {"stf.spill",	M, OpMXX6aHint (6, 0, 0, 0x3b, 0), {MR3, F2}},
+    {"stf.spill.nta",	M, OpMXX6aHint (6, 0, 0, 0x3b, 3), {MR3, F2}},
+
+    /* floating-point load pair */
+    {"ldfps",		M2, OpMXX6aHint (6, 0, 1, 0x02, 0), {F1, F2, MR3}},
+    {"ldfps.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x02, 1), {F1, F2, MR3}},
+    {"ldfps.nta",	M2, OpMXX6aHint (6, 0, 1, 0x02, 3), {F1, F2, MR3}},
+    {"ldfpd",		M2, OpMXX6aHint (6, 0, 1, 0x03, 0), {F1, F2, MR3}},
+    {"ldfpd.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x03, 1), {F1, F2, MR3}},
+    {"ldfpd.nta",	M2, OpMXX6aHint (6, 0, 1, 0x03, 3), {F1, F2, MR3}},
+    {"ldfp8",		M2, OpMXX6aHint (6, 0, 1, 0x01, 0), {F1, F2, MR3}},
+    {"ldfp8.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x01, 1), {F1, F2, MR3}},
+    {"ldfp8.nta",	M2, OpMXX6aHint (6, 0, 1, 0x01, 3), {F1, F2, MR3}},
+    {"ldfps.s",		M2, OpMXX6aHint (6, 0, 1, 0x06, 0), {F1, F2, MR3}},
+    {"ldfps.s.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x06, 1), {F1, F2, MR3}},
+    {"ldfps.s.nta",	M2, OpMXX6aHint (6, 0, 1, 0x06, 3), {F1, F2, MR3}},
+    {"ldfpd.s",		M2, OpMXX6aHint (6, 0, 1, 0x07, 0), {F1, F2, MR3}},
+    {"ldfpd.s.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x07, 1), {F1, F2, MR3}},
+    {"ldfpd.s.nta",	M2, OpMXX6aHint (6, 0, 1, 0x07, 3), {F1, F2, MR3}},
+    {"ldfp8.s",		M2, OpMXX6aHint (6, 0, 1, 0x05, 0), {F1, F2, MR3}},
+    {"ldfp8.s.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x05, 1), {F1, F2, MR3}},
+    {"ldfp8.s.nta",	M2, OpMXX6aHint (6, 0, 1, 0x05, 3), {F1, F2, MR3}},
+    {"ldfps.a",		M2, OpMXX6aHint (6, 0, 1, 0x0a, 0), {F1, F2, MR3}},
+    {"ldfps.a.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x0a, 1), {F1, F2, MR3}},
+    {"ldfps.a.nta",	M2, OpMXX6aHint (6, 0, 1, 0x0a, 3), {F1, F2, MR3}},
+    {"ldfpd.a",		M2, OpMXX6aHint (6, 0, 1, 0x0b, 0), {F1, F2, MR3}},
+    {"ldfpd.a.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x0b, 1), {F1, F2, MR3}},
+    {"ldfpd.a.nta",	M2, OpMXX6aHint (6, 0, 1, 0x0b, 3), {F1, F2, MR3}},
+    {"ldfp8.a",		M2, OpMXX6aHint (6, 0, 1, 0x09, 0), {F1, F2, MR3}},
+    {"ldfp8.a.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x09, 1), {F1, F2, MR3}},
+    {"ldfp8.a.nta",	M2, OpMXX6aHint (6, 0, 1, 0x09, 3), {F1, F2, MR3}},
+    {"ldfps.sa",	M2, OpMXX6aHint (6, 0, 1, 0x0e, 0), {F1, F2, MR3}},
+    {"ldfps.sa.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x0e, 1), {F1, F2, MR3}},
+    {"ldfps.sa.nta",	M2, OpMXX6aHint (6, 0, 1, 0x0e, 3), {F1, F2, MR3}},
+    {"ldfpd.sa",	M2, OpMXX6aHint (6, 0, 1, 0x0f, 0), {F1, F2, MR3}},
+    {"ldfpd.sa.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x0f, 1), {F1, F2, MR3}},
+    {"ldfpd.sa.nta",	M2, OpMXX6aHint (6, 0, 1, 0x0f, 3), {F1, F2, MR3}},
+    {"ldfp8.sa",	M2, OpMXX6aHint (6, 0, 1, 0x0d, 0), {F1, F2, MR3}},
+    {"ldfp8.sa.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x0d, 1), {F1, F2, MR3}},
+    {"ldfp8.sa.nta",	M2, OpMXX6aHint (6, 0, 1, 0x0d, 3), {F1, F2, MR3}},
+    {"ldfps.c.clr",	M2, OpMXX6aHint (6, 0, 1, 0x22, 0), {F1, F2, MR3}},
+    {"ldfps.c.clr.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x22, 1), {F1, F2, MR3}},
+    {"ldfps.c.clr.nta",	M2, OpMXX6aHint (6, 0, 1, 0x22, 3), {F1, F2, MR3}},
+    {"ldfpd.c.clr",	M2, OpMXX6aHint (6, 0, 1, 0x23, 0), {F1, F2, MR3}},
+    {"ldfpd.c.clr.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x23, 1), {F1, F2, MR3}},
+    {"ldfpd.c.clr.nta",	M2, OpMXX6aHint (6, 0, 1, 0x23, 3), {F1, F2, MR3}},
+    {"ldfp8.c.clr",	M2, OpMXX6aHint (6, 0, 1, 0x21, 0), {F1, F2, MR3}},
+    {"ldfp8.c.clr.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x21, 1), {F1, F2, MR3}},
+    {"ldfp8.c.clr.nta",	M2, OpMXX6aHint (6, 0, 1, 0x21, 3), {F1, F2, MR3}},
+    {"ldfps.c.nc",	M2, OpMXX6aHint (6, 0, 1, 0x26, 0), {F1, F2, MR3}},
+    {"ldfps.c.nc.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x26, 1), {F1, F2, MR3}},
+    {"ldfps.c.nc.nta",	M2, OpMXX6aHint (6, 0, 1, 0x26, 3), {F1, F2, MR3}},
+    {"ldfpd.c.nc",	M2, OpMXX6aHint (6, 0, 1, 0x27, 0), {F1, F2, MR3}},
+    {"ldfpd.c.nc.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x27, 1), {F1, F2, MR3}},
+    {"ldfpd.c.nc.nta",	M2, OpMXX6aHint (6, 0, 1, 0x27, 3), {F1, F2, MR3}},
+    {"ldfp8.c.nc",	M2, OpMXX6aHint (6, 0, 1, 0x25, 0), {F1, F2, MR3}},
+    {"ldfp8.c.nc.nt1",	M2, OpMXX6aHint (6, 0, 1, 0x25, 1), {F1, F2, MR3}},
+    {"ldfp8.c.nc.nta",	M2, OpMXX6aHint (6, 0, 1, 0x25, 3), {F1, F2, MR3}},
+
+    /* floating-point load pair w/increment by immediate */
+#define LD(a,b,c)	M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c}
+    {"ldfps",		LD (0x02, 0, C8)},
+    {"ldfps.nt1",	LD (0x02, 1, C8)},
+    {"ldfps.nta",	LD (0x02, 3, C8)},
+    {"ldfpd",		LD (0x03, 0, C16)},
+    {"ldfpd.nt1",	LD (0x03, 1, C16)},
+    {"ldfpd.nta",	LD (0x03, 3, C16)},
+    {"ldfp8",		LD (0x01, 0, C16)},
+    {"ldfp8.nt1",	LD (0x01, 1, C16)},
+    {"ldfp8.nta",	LD (0x01, 3, C16)},
+    {"ldfps.s",		LD (0x06, 0, C8)},
+    {"ldfps.s.nt1",	LD (0x06, 1, C8)},
+    {"ldfps.s.nta",	LD (0x06, 3, C8)},
+    {"ldfpd.s",		LD (0x07, 0, C16)},
+    {"ldfpd.s.nt1",	LD (0x07, 1, C16)},
+    {"ldfpd.s.nta",	LD (0x07, 3, C16)},
+    {"ldfp8.s",		LD (0x05, 0, C16)},
+    {"ldfp8.s.nt1",	LD (0x05, 1, C16)},
+    {"ldfp8.s.nta",	LD (0x05, 3, C16)},
+    {"ldfps.a",		LD (0x0a, 0, C8)},
+    {"ldfps.a.nt1",	LD (0x0a, 1, C8)},
+    {"ldfps.a.nta",	LD (0x0a, 3, C8)},
+    {"ldfpd.a",		LD (0x0b, 0, C16)},
+    {"ldfpd.a.nt1",	LD (0x0b, 1, C16)},
+    {"ldfpd.a.nta",	LD (0x0b, 3, C16)},
+    {"ldfp8.a",		LD (0x09, 0, C16)},
+    {"ldfp8.a.nt1",	LD (0x09, 1, C16)},
+    {"ldfp8.a.nta",	LD (0x09, 3, C16)},
+    {"ldfps.sa",	LD (0x0e, 0, C8)},
+    {"ldfps.sa.nt1",	LD (0x0e, 1, C8)},
+    {"ldfps.sa.nta",	LD (0x0e, 3, C8)},
+    {"ldfpd.sa",	LD (0x0f, 0, C16)},
+    {"ldfpd.sa.nt1",	LD (0x0f, 1, C16)},
+    {"ldfpd.sa.nta",	LD (0x0f, 3, C16)},
+    {"ldfp8.sa",	LD (0x0d, 0, C16)},
+    {"ldfp8.sa.nt1",	LD (0x0d, 1, C16)},
+    {"ldfp8.sa.nta",	LD (0x0d, 3, C16)},
+    {"ldfps.c.clr",	LD (0x22, 0, C8)},
+    {"ldfps.c.clr.nt1",	LD (0x22, 1, C8)},
+    {"ldfps.c.clr.nta",	LD (0x22, 3, C8)},
+    {"ldfpd.c.clr",	LD (0x23, 0, C16)},
+    {"ldfpd.c.clr.nt1",	LD (0x23, 1, C16)},
+    {"ldfpd.c.clr.nta",	LD (0x23, 3, C16)},
+    {"ldfp8.c.clr",	LD (0x21, 0, C16)},
+    {"ldfp8.c.clr.nt1",	LD (0x21, 1, C16)},
+    {"ldfp8.c.clr.nta",	LD (0x21, 3, C16)},
+    {"ldfps.c.nc",	LD (0x26, 0, C8)},
+    {"ldfps.c.nc.nt1",	LD (0x26, 1, C8)},
+    {"ldfps.c.nc.nta",	LD (0x26, 3, C8)},
+    {"ldfpd.c.nc",	LD (0x27, 0, C16)},
+    {"ldfpd.c.nc.nt1",	LD (0x27, 1, C16)},
+    {"ldfpd.c.nc.nta",	LD (0x27, 3, C16)},
+    {"ldfp8.c.nc",	LD (0x25, 0, C16)},
+    {"ldfp8.c.nc.nt1",	LD (0x25, 1, C16)},
+    {"ldfp8.c.nc.nta",	LD (0x25, 3, C16)},
+#undef LD
+
+    /* line prefetch */
+    {"lfetch",			M0, OpMXX6aHint (6, 0, 0, 0x2c, 0), {MR3}},
+    {"lfetch.nt1",		M0, OpMXX6aHint (6, 0, 0, 0x2c, 1), {MR3}},
+    {"lfetch.nt2",		M0, OpMXX6aHint (6, 0, 0, 0x2c, 2), {MR3}},
+    {"lfetch.nta",		M0, OpMXX6aHint (6, 0, 0, 0x2c, 3), {MR3}},
+    {"lfetch.excl",		M0, OpMXX6aHint (6, 0, 0, 0x2d, 0), {MR3}},
+    {"lfetch.excl.nt1",		M0, OpMXX6aHint (6, 0, 0, 0x2d, 1), {MR3}},
+    {"lfetch.excl.nt2",		M0, OpMXX6aHint (6, 0, 0, 0x2d, 2), {MR3}},
+    {"lfetch.excl.nta",		M0, OpMXX6aHint (6, 0, 0, 0x2d, 3), {MR3}},
+    {"lfetch.fault",		M0, OpMXX6aHint (6, 0, 0, 0x2e, 0), {MR3}},
+    {"lfetch.fault.nt1",	M0, OpMXX6aHint (6, 0, 0, 0x2e, 1), {MR3}},
+    {"lfetch.fault.nt2",	M0, OpMXX6aHint (6, 0, 0, 0x2e, 2), {MR3}},
+    {"lfetch.fault.nta",	M0, OpMXX6aHint (6, 0, 0, 0x2e, 3), {MR3}},
+    {"lfetch.fault.excl",	M0, OpMXX6aHint (6, 0, 0, 0x2f, 0), {MR3}},
+    {"lfetch.fault.excl.nt1",	M0, OpMXX6aHint (6, 0, 0, 0x2f, 1), {MR3}},
+    {"lfetch.fault.excl.nt2",	M0, OpMXX6aHint (6, 0, 0, 0x2f, 2), {MR3}},
+    {"lfetch.fault.excl.nta",	M0, OpMXX6aHint (6, 0, 0, 0x2f, 3), {MR3}},
+
+    /* line prefetch w/increment by register */
+    {"lfetch",			M0, OpMXX6aHint (6, 1, 0, 0x2c, 0), {MR3, R2}},
+    {"lfetch.nt1",		M0, OpMXX6aHint (6, 1, 0, 0x2c, 1), {MR3, R2}},
+    {"lfetch.nt2",		M0, OpMXX6aHint (6, 1, 0, 0x2c, 2), {MR3, R2}},
+    {"lfetch.nta",		M0, OpMXX6aHint (6, 1, 0, 0x2c, 3), {MR3, R2}},
+    {"lfetch.excl",		M0, OpMXX6aHint (6, 1, 0, 0x2d, 0), {MR3, R2}},
+    {"lfetch.excl.nt1",		M0, OpMXX6aHint (6, 1, 0, 0x2d, 1), {MR3, R2}},
+    {"lfetch.excl.nt2",		M0, OpMXX6aHint (6, 1, 0, 0x2d, 2), {MR3, R2}},
+    {"lfetch.excl.nta",		M0, OpMXX6aHint (6, 1, 0, 0x2d, 3), {MR3, R2}},
+    {"lfetch.fault",		M0, OpMXX6aHint (6, 1, 0, 0x2e, 0), {MR3, R2}},
+    {"lfetch.fault.nt1",	M0, OpMXX6aHint (6, 1, 0, 0x2e, 1), {MR3, R2}},
+    {"lfetch.fault.nt2",	M0, OpMXX6aHint (6, 1, 0, 0x2e, 2), {MR3, R2}},
+    {"lfetch.fault.nta",	M0, OpMXX6aHint (6, 1, 0, 0x2e, 3), {MR3, R2}},
+    {"lfetch.fault.excl",	M0, OpMXX6aHint (6, 1, 0, 0x2f, 0), {MR3, R2}},
+    {"lfetch.fault.excl.nt1",	M0, OpMXX6aHint (6, 1, 0, 0x2f, 1), {MR3, R2}},
+    {"lfetch.fault.excl.nt2",	M0, OpMXX6aHint (6, 1, 0, 0x2f, 2), {MR3, R2}},
+    {"lfetch.fault.excl.nta",	M0, OpMXX6aHint (6, 1, 0, 0x2f, 3), {MR3, R2}},
+
+    /* semaphore operations */
+    {"setf.sig",	M, OpMXX6a (6, 0, 1, 0x1c), {F1, R2}},
+    {"setf.exp",	M, OpMXX6a (6, 0, 1, 0x1d), {F1, R2}},
+    {"setf.s",		M, OpMXX6a (6, 0, 1, 0x1e), {F1, R2}},
+    {"setf.d",		M, OpMXX6a (6, 0, 1, 0x1f), {F1, R2}},
+
+    {"ldfs",		M, OpX6aHint (7, 0x02, 0), {F1, MR3, IMM9b}},
+    {"ldfs.nt1",	M, OpX6aHint (7, 0x02, 1), {F1, MR3, IMM9b}},
+    {"ldfs.nta",	M, OpX6aHint (7, 0x02, 3), {F1, MR3, IMM9b}},
+    {"ldfd",		M, OpX6aHint (7, 0x03, 0), {F1, MR3, IMM9b}},
+    {"ldfd.nt1",	M, OpX6aHint (7, 0x03, 1), {F1, MR3, IMM9b}},
+    {"ldfd.nta",	M, OpX6aHint (7, 0x03, 3), {F1, MR3, IMM9b}},
+    {"ldf8",		M, OpX6aHint (7, 0x01, 0), {F1, MR3, IMM9b}},
+    {"ldf8.nt1",	M, OpX6aHint (7, 0x01, 1), {F1, MR3, IMM9b}},
+    {"ldf8.nta",	M, OpX6aHint (7, 0x01, 3), {F1, MR3, IMM9b}},
+    {"ldfe",		M, OpX6aHint (7, 0x00, 0), {F1, MR3, IMM9b}},
+    {"ldfe.nt1",	M, OpX6aHint (7, 0x00, 1), {F1, MR3, IMM9b}},
+    {"ldfe.nta",	M, OpX6aHint (7, 0x00, 3), {F1, MR3, IMM9b}},
+    {"ldfs.s",		M, OpX6aHint (7, 0x06, 0), {F1, MR3, IMM9b}},
+    {"ldfs.s.nt1",	M, OpX6aHint (7, 0x06, 1), {F1, MR3, IMM9b}},
+    {"ldfs.s.nta",	M, OpX6aHint (7, 0x06, 3), {F1, MR3, IMM9b}},
+    {"ldfd.s",		M, OpX6aHint (7, 0x07, 0), {F1, MR3, IMM9b}},
+    {"ldfd.s.nt1",	M, OpX6aHint (7, 0x07, 1), {F1, MR3, IMM9b}},
+    {"ldfd.s.nta",	M, OpX6aHint (7, 0x07, 3), {F1, MR3, IMM9b}},
+    {"ldf8.s",		M, OpX6aHint (7, 0x05, 0), {F1, MR3, IMM9b}},
+    {"ldf8.s.nt1",	M, OpX6aHint (7, 0x05, 1), {F1, MR3, IMM9b}},
+    {"ldf8.s.nta",	M, OpX6aHint (7, 0x05, 3), {F1, MR3, IMM9b}},
+    {"ldfe.s",		M, OpX6aHint (7, 0x04, 0), {F1, MR3, IMM9b}},
+    {"ldfe.s.nt1",	M, OpX6aHint (7, 0x04, 1), {F1, MR3, IMM9b}},
+    {"ldfe.s.nta",	M, OpX6aHint (7, 0x04, 3), {F1, MR3, IMM9b}},
+    {"ldfs.a",		M, OpX6aHint (7, 0x0a, 0), {F1, MR3, IMM9b}},
+    {"ldfs.a.nt1",	M, OpX6aHint (7, 0x0a, 1), {F1, MR3, IMM9b}},
+    {"ldfs.a.nta",	M, OpX6aHint (7, 0x0a, 3), {F1, MR3, IMM9b}},
+    {"ldfd.a",		M, OpX6aHint (7, 0x0b, 0), {F1, MR3, IMM9b}},
+    {"ldfd.a.nt1",	M, OpX6aHint (7, 0x0b, 1), {F1, MR3, IMM9b}},
+    {"ldfd.a.nta",	M, OpX6aHint (7, 0x0b, 3), {F1, MR3, IMM9b}},
+    {"ldf8.a",		M, OpX6aHint (7, 0x09, 0), {F1, MR3, IMM9b}},
+    {"ldf8.a.nt1",	M, OpX6aHint (7, 0x09, 1), {F1, MR3, IMM9b}},
+    {"ldf8.a.nta",	M, OpX6aHint (7, 0x09, 3), {F1, MR3, IMM9b}},
+    {"ldfe.a",		M, OpX6aHint (7, 0x08, 0), {F1, MR3, IMM9b}},
+    {"ldfe.a.nt1",	M, OpX6aHint (7, 0x08, 1), {F1, MR3, IMM9b}},
+    {"ldfe.a.nta",	M, OpX6aHint (7, 0x08, 3), {F1, MR3, IMM9b}},
+    {"ldfs.sa",		M, OpX6aHint (7, 0x0e, 0), {F1, MR3, IMM9b}},
+    {"ldfs.sa.nt1",	M, OpX6aHint (7, 0x0e, 1), {F1, MR3, IMM9b}},
+    {"ldfs.sa.nta",	M, OpX6aHint (7, 0x0e, 3), {F1, MR3, IMM9b}},
+    {"ldfd.sa",		M, OpX6aHint (7, 0x0f, 0), {F1, MR3, IMM9b}},
+    {"ldfd.sa.nt1",	M, OpX6aHint (7, 0x0f, 1), {F1, MR3, IMM9b}},
+    {"ldfd.sa.nta",	M, OpX6aHint (7, 0x0f, 3), {F1, MR3, IMM9b}},
+    {"ldf8.sa",		M, OpX6aHint (7, 0x0d, 0), {F1, MR3, IMM9b}},
+    {"ldf8.sa.nt1",	M, OpX6aHint (7, 0x0d, 1), {F1, MR3, IMM9b}},
+    {"ldf8.sa.nta",	M, OpX6aHint (7, 0x0d, 3), {F1, MR3, IMM9b}},
+    {"ldfe.sa",		M, OpX6aHint (7, 0x0c, 0), {F1, MR3, IMM9b}},
+    {"ldfe.sa.nt1",	M, OpX6aHint (7, 0x0c, 1), {F1, MR3, IMM9b}},
+    {"ldfe.sa.nta",	M, OpX6aHint (7, 0x0c, 3), {F1, MR3, IMM9b}},
+    {"ldf.fill",	M, OpX6aHint (7, 0x1b, 0), {F1, MR3, IMM9b}},
+    {"ldf.fill.nt1",	M, OpX6aHint (7, 0x1b, 1), {F1, MR3, IMM9b}},
+    {"ldf.fill.nta",	M, OpX6aHint (7, 0x1b, 3), {F1, MR3, IMM9b}},
+    {"ldfs.c.clr",	M, OpX6aHint (7, 0x22, 0), {F1, MR3, IMM9b}},
+    {"ldfs.c.clr.nt1",	M, OpX6aHint (7, 0x22, 1), {F1, MR3, IMM9b}},
+    {"ldfs.c.clr.nta",	M, OpX6aHint (7, 0x22, 3), {F1, MR3, IMM9b}},
+    {"ldfd.c.clr",	M, OpX6aHint (7, 0x23, 0), {F1, MR3, IMM9b}},
+    {"ldfd.c.clr.nt1",	M, OpX6aHint (7, 0x23, 1), {F1, MR3, IMM9b}},
+    {"ldfd.c.clr.nta",	M, OpX6aHint (7, 0x23, 3), {F1, MR3, IMM9b}},
+    {"ldf8.c.clr",	M, OpX6aHint (7, 0x21, 0), {F1, MR3, IMM9b}},
+    {"ldf8.c.clr.nt1",	M, OpX6aHint (7, 0x21, 1), {F1, MR3, IMM9b}},
+    {"ldf8.c.clr.nta",	M, OpX6aHint (7, 0x21, 3), {F1, MR3, IMM9b}},
+    {"ldfe.c.clr",	M, OpX6aHint (7, 0x20, 0), {F1, MR3, IMM9b}},
+    {"ldfe.c.clr.nt1",	M, OpX6aHint (7, 0x20, 1), {F1, MR3, IMM9b}},
+    {"ldfe.c.clr.nta",	M, OpX6aHint (7, 0x20, 3), {F1, MR3, IMM9b}},
+    {"ldfs.c.nc",	M, OpX6aHint (7, 0x26, 0), {F1, MR3, IMM9b}},
+    {"ldfs.c.nc.nt1",	M, OpX6aHint (7, 0x26, 1), {F1, MR3, IMM9b}},
+    {"ldfs.c.nc.nta",	M, OpX6aHint (7, 0x26, 3), {F1, MR3, IMM9b}},
+    {"ldfd.c.nc",	M, OpX6aHint (7, 0x27, 0), {F1, MR3, IMM9b}},
+    {"ldfd.c.nc.nt1",	M, OpX6aHint (7, 0x27, 1), {F1, MR3, IMM9b}},
+    {"ldfd.c.nc.nta",	M, OpX6aHint (7, 0x27, 3), {F1, MR3, IMM9b}},
+    {"ldf8.c.nc",	M, OpX6aHint (7, 0x25, 0), {F1, MR3, IMM9b}},
+    {"ldf8.c.nc.nt1",	M, OpX6aHint (7, 0x25, 1), {F1, MR3, IMM9b}},
+    {"ldf8.c.nc.nta",	M, OpX6aHint (7, 0x25, 3), {F1, MR3, IMM9b}},
+    {"ldfe.c.nc",	M, OpX6aHint (7, 0x24, 0), {F1, MR3, IMM9b}},
+    {"ldfe.c.nc.nt1",	M, OpX6aHint (7, 0x24, 1), {F1, MR3, IMM9b}},
+    {"ldfe.c.nc.nta",	M, OpX6aHint (7, 0x24, 3), {F1, MR3, IMM9b}},
+
+    /* floating-point store w/increment by immediate */
+    {"stfs",		M, OpX6aHint (7, 0x32, 0), {MR3, F2, IMM9a}},
+    {"stfs.nta",	M, OpX6aHint (7, 0x32, 3), {MR3, F2, IMM9a}},
+    {"stfd",		M, OpX6aHint (7, 0x33, 0), {MR3, F2, IMM9a}},
+    {"stfd.nta",	M, OpX6aHint (7, 0x33, 3), {MR3, F2, IMM9a}},
+    {"stf8",		M, OpX6aHint (7, 0x31, 0), {MR3, F2, IMM9a}},
+    {"stf8.nta",	M, OpX6aHint (7, 0x31, 3), {MR3, F2, IMM9a}},
+    {"stfe",		M, OpX6aHint (7, 0x30, 0), {MR3, F2, IMM9a}},
+    {"stfe.nta",	M, OpX6aHint (7, 0x30, 3), {MR3, F2, IMM9a}},
+    {"stf.spill",	M, OpX6aHint (7, 0x3b, 0), {MR3, F2, IMM9a}},
+    {"stf.spill.nta",	M, OpX6aHint (7, 0x3b, 3), {MR3, F2, IMM9a}},
+
+    /* line prefetch w/increment by immediate */
+    {"lfetch",			M0, OpX6aHint (7, 0x2c, 0), {MR3, IMM9b}},
+    {"lfetch.nt1",		M0, OpX6aHint (7, 0x2c, 1), {MR3, IMM9b}},
+    {"lfetch.nt2",		M0, OpX6aHint (7, 0x2c, 2), {MR3, IMM9b}},
+    {"lfetch.nta",		M0, OpX6aHint (7, 0x2c, 3), {MR3, IMM9b}},
+    {"lfetch.excl",		M0, OpX6aHint (7, 0x2d, 0), {MR3, IMM9b}},
+    {"lfetch.excl.nt1",		M0, OpX6aHint (7, 0x2d, 1), {MR3, IMM9b}},
+    {"lfetch.excl.nt2",		M0, OpX6aHint (7, 0x2d, 2), {MR3, IMM9b}},
+    {"lfetch.excl.nta",		M0, OpX6aHint (7, 0x2d, 3), {MR3, IMM9b}},
+    {"lfetch.fault",		M0, OpX6aHint (7, 0x2e, 0), {MR3, IMM9b}},
+    {"lfetch.fault.nt1",	M0, OpX6aHint (7, 0x2e, 1), {MR3, IMM9b}},
+    {"lfetch.fault.nt2",	M0, OpX6aHint (7, 0x2e, 2), {MR3, IMM9b}},
+    {"lfetch.fault.nta",	M0, OpX6aHint (7, 0x2e, 3), {MR3, IMM9b}},
+    {"lfetch.fault.excl",	M0, OpX6aHint (7, 0x2f, 0), {MR3, IMM9b}},
+    {"lfetch.fault.excl.nt1",	M0, OpX6aHint (7, 0x2f, 1), {MR3, IMM9b}},
+    {"lfetch.fault.excl.nt2",	M0, OpX6aHint (7, 0x2f, 2), {MR3, IMM9b}},
+    {"lfetch.fault.excl.nta",	M0, OpX6aHint (7, 0x2f, 3), {MR3, IMM9b}},
+
+    {0}
+  };
+
+#undef M0
+#undef M
+#undef M2
+#undef bM
+#undef bX
+#undef bX2
+#undef bX3
+#undef bX4
+#undef bX6a
+#undef bX6b
+#undef bHint
+#undef mM
+#undef mX
+#undef mX2
+#undef mX3
+#undef mX4
+#undef mX6a
+#undef mX6b
+#undef mHint
+#undef OpX3
+#undef OpX3X6b
+#undef OpX3X4
+#undef OpX3X4X2
+#undef OpX6aHint
+#undef OpXX6aHint
+#undef OpMXX6a
+#undef OpMXX6aHint
diff --git a/opcodes/ia64-opc-x.c b/opcodes/ia64-opc-x.c
new file mode 100644
index 0000000..8432d68
--- /dev/null
+++ b/opcodes/ia64-opc-x.c
@@ -0,0 +1,178 @@
+/* ia64-opc-x.c -- IA-64 `X' opcode table.
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Timothy Wall <twall@cygnus.com>
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the
+   Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
+
+#include "ia64-opc.h"
+
+/* identify the specific X-unit type */
+#define X0      IA64_TYPE_X, 0
+#define X	IA64_TYPE_X, 1
+
+/* instruction bit fields: */
+#define bBtype(x)	(((ia64_insn) ((x) & 0x7)) << 6)
+#define bD(x)		(((ia64_insn) ((x) & 0x1)) << 35)
+#define bPa(x)		(((ia64_insn) ((x) & 0x1)) << 12)
+#define bPr(x)		(((ia64_insn) ((x) & 0x3f)) << 0)
+#define bVc(x)		(((ia64_insn) ((x) & 0x1)) << 20)
+#define bWha(x)		(((ia64_insn) ((x) & 0x3)) << 33)
+#define bX3(x)		(((ia64_insn) ((x) & 0x7)) << 33)
+#define bX6(x)		(((ia64_insn) ((x) & 0x3f)) << 27)
+
+#define mBtype		bBtype (-1)
+#define mD		bD (-1)
+#define mPa		bPa (-1)
+#define mPr		bPr (-1)
+#define mVc             bVc (-1)
+#define mWha		bWha (-1)
+#define mX3             bX3 (-1)
+#define mX6		bX6 (-1)
+
+#define OpX3X6(a,b,c)		(bOp (a) | bX3 (b) | bX6(c)), \
+				(mOp | mX3 | mX6)
+#define OpVc(a,b)		(bOp (a) | bVc (b)), (mOp | mVc)
+#define OpPaWhaD(a,b,c,d) \
+	(bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD)
+#define OpBtypePaWhaD(a,b,c,d,e) \
+	(bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \
+	(mOp | mBtype | mPa | mWha | mD)
+#define OpBtypePaWhaDPr(a,b,c,d,e,f) \
+	(bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \
+	(mOp | mBtype | mPa | mWha | mD | mPr)
+
+struct ia64_opcode ia64_opcodes_x[] =
+  {
+    {"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}},
+    {"nop.x",   X0, OpX3X6 (0, 0, 0x01), {IMMU62}},
+    {"movl",	X,  OpVc (6, 0), {R1, IMMU64}},
+#define BRL(a,b) \
+      X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, 0
+    {"brl.few",         BRL (0, 0) | PSEUDO},
+    {"brl",             BRL (0, 0) | PSEUDO},
+    {"brl.few.clr",	BRL (0, 1) | PSEUDO},
+    {"brl.clr",		BRL (0, 1) | PSEUDO},
+    {"brl.many",	BRL (1, 0) | PSEUDO},
+    {"brl.many.clr",	BRL (1, 1) | PSEUDO},
+#undef BRL
+#define BRL(a,b,c) \
+      X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, 0
+    {"brl.cond.sptk.few",	BRL (0, 0, 0)},
+    {"brl.cond.sptk",		BRL (0, 0, 0) | PSEUDO},
+    {"brl.cond.sptk.few.clr",	BRL (0, 0, 1)},
+    {"brl.cond.sptk.clr",	BRL (0, 0, 1) | PSEUDO},
+    {"brl.cond.spnt.few",	BRL (0, 1, 0)},
+    {"brl.cond.spnt",		BRL (0, 1, 0) | PSEUDO},
+    {"brl.cond.spnt.few.clr",	BRL (0, 1, 1)},
+    {"brl.cond.spnt.clr",	BRL (0, 1, 1) | PSEUDO},
+    {"brl.cond.dptk.few",	BRL (0, 2, 0)},
+    {"brl.cond.dptk",		BRL (0, 2, 0) | PSEUDO},
+    {"brl.cond.dptk.few.clr",	BRL (0, 2, 1)},
+    {"brl.cond.dptk.clr",	BRL (0, 2, 1) | PSEUDO},
+    {"brl.cond.dpnt.few",	BRL (0, 3, 0)},
+    {"brl.cond.dpnt",		BRL (0, 3, 0) | PSEUDO},
+    {"brl.cond.dpnt.few.clr",	BRL (0, 3, 1)},
+    {"brl.cond.dpnt.clr",	BRL (0, 3, 1) | PSEUDO},
+    {"brl.cond.sptk.many",	BRL (1, 0, 0)},
+    {"brl.cond.sptk.many.clr",	BRL (1, 0, 1)},
+    {"brl.cond.spnt.many",	BRL (1, 1, 0)},
+    {"brl.cond.spnt.many.clr",	BRL (1, 1, 1)},
+    {"brl.cond.dptk.many",	BRL (1, 2, 0)},
+    {"brl.cond.dptk.many.clr",	BRL (1, 2, 1)},
+    {"brl.cond.dpnt.many",	BRL (1, 3, 0)},
+    {"brl.cond.dpnt.many.clr",	BRL (1, 3, 1)},
+    {"brl.sptk.few",		BRL (0, 0, 0)},
+    {"brl.sptk",		BRL (0, 0, 0) | PSEUDO},
+    {"brl.sptk.few.clr",	BRL (0, 0, 1)},
+    {"brl.sptk.clr",		BRL (0, 0, 1) | PSEUDO},
+    {"brl.spnt.few",		BRL (0, 1, 0)},
+    {"brl.spnt",		BRL (0, 1, 0) | PSEUDO},
+    {"brl.spnt.few.clr",	BRL (0, 1, 1)},
+    {"brl.spnt.clr",		BRL (0, 1, 1) | PSEUDO},
+    {"brl.dptk.few",		BRL (0, 2, 0)},
+    {"brl.dptk",		BRL (0, 2, 0) | PSEUDO},
+    {"brl.dptk.few.clr",	BRL (0, 2, 1)},
+    {"brl.dptk.clr",		BRL (0, 2, 1) | PSEUDO},
+    {"brl.dpnt.few",		BRL (0, 3, 0)},
+    {"brl.dpnt",		BRL (0, 3, 0) | PSEUDO},
+    {"brl.dpnt.few.clr",	BRL (0, 3, 1)},
+    {"brl.dpnt.clr",		BRL (0, 3, 1) | PSEUDO},
+    {"brl.sptk.many",		BRL (1, 0, 0)},
+    {"brl.sptk.many.clr",	BRL (1, 0, 1)},
+    {"brl.spnt.many",		BRL (1, 1, 0)},
+    {"brl.spnt.many.clr",	BRL (1, 1, 1)},
+    {"brl.dptk.many",		BRL (1, 2, 0)},
+    {"brl.dptk.many.clr",	BRL (1, 2, 1)},
+    {"brl.dpnt.many",		BRL (1, 3, 0)},
+    {"brl.dpnt.many.clr",	BRL (1, 3, 1)},
+#undef BRL
+#define BRL(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, 0
+    {"brl.call.sptk.few",	BRL (0, 0, 0)},
+    {"brl.call.sptk",		BRL (0, 0, 0) | PSEUDO},
+    {"brl.call.sptk.few.clr",	BRL (0, 0, 1)},
+    {"brl.call.sptk.clr",	BRL (0, 0, 1) | PSEUDO},
+    {"brl.call.spnt.few",	BRL (0, 1, 0)},
+    {"brl.call.spnt",		BRL (0, 1, 0) | PSEUDO},
+    {"brl.call.spnt.few.clr",	BRL (0, 1, 1)},
+    {"brl.call.spnt.clr",	BRL (0, 1, 1) | PSEUDO},
+    {"brl.call.dptk.few",	BRL (0, 2, 0)},
+    {"brl.call.dptk",		BRL (0, 2, 0) | PSEUDO},
+    {"brl.call.dptk.few.clr",	BRL (0, 2, 1)},
+    {"brl.call.dptk.clr",	BRL (0, 2, 1) | PSEUDO},
+    {"brl.call.dpnt.few",	BRL (0, 3, 0)},
+    {"brl.call.dpnt",		BRL (0, 3, 0) | PSEUDO},
+    {"brl.call.dpnt.few.clr",	BRL (0, 3, 1)},
+    {"brl.call.dpnt.clr",	BRL (0, 3, 1) | PSEUDO},
+    {"brl.call.sptk.many",	BRL (1, 0, 0)},
+    {"brl.call.sptk.many.clr",	BRL (1, 0, 1)},
+    {"brl.call.spnt.many",	BRL (1, 1, 0)},
+    {"brl.call.spnt.many.clr",	BRL (1, 1, 1)},
+    {"brl.call.dptk.many",	BRL (1, 2, 0)},
+    {"brl.call.dptk.many.clr",	BRL (1, 2, 1)},
+    {"brl.call.dpnt.many",	BRL (1, 3, 0)},
+    {"brl.call.dpnt.many.clr",	BRL (1, 3, 1)},
+#undef BRL
+    {0}
+  };
+
+#undef X0
+#undef X
+
+#undef bBtype
+#undef bD
+#undef bPa
+#undef bPr
+#undef bVc
+#undef bWha
+#undef bX3
+#undef bX6
+
+#undef mBtype
+#undef mD
+#undef mPa
+#undef mPr
+#undef mVc
+#undef mWha
+#undef mX3
+#undef mX6
+
+#undef OpX3X6
+#undef OpVc
+#undef OpPaWhaD
+#undef OpBtypePaWhaD
+#undef OpBtypePaWhaDPr
diff --git a/opcodes/ia64-opc.c b/opcodes/ia64-opc.c
new file mode 100644
index 0000000..a25dd66
--- /dev/null
+++ b/opcodes/ia64-opc.c
@@ -0,0 +1,741 @@
+/* ia64-opc.c -- Functions to access the compacted opcode table
+   Copyright (C) 1999 Free Software Foundation, Inc.
+   Written by Bob Manson of Cygnus Solutions, <manson@cygnus.com>
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the
+   Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
+
+#include "ansidecl.h"
+#include "libiberty.h"
+#include "sysdep.h"
+#include "ia64-asmtab.h"
+#include "ia64-asmtab.c"
+
+const struct ia64_templ_desc ia64_templ_desc[16] =
+  {
+    { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" },	/* 0 */
+    { 2, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" },
+    { 0, { IA64_UNIT_M, IA64_UNIT_L, IA64_UNIT_X }, "MLX" },
+    { 0, { 0, },				    "-3-" },
+    { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" },	/* 4 */
+    { 1, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" },
+    { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_I }, "MFI" },
+    { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_F }, "MMF" },
+    { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_B }, "MIB" },	/* 8 */
+    { 0, { IA64_UNIT_M, IA64_UNIT_B, IA64_UNIT_B }, "MBB" },
+    { 0, { 0, },				    "-a-" },
+    { 0, { IA64_UNIT_B, IA64_UNIT_B, IA64_UNIT_B }, "BBB" },
+    { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_B }, "MMB" },	/* c */
+    { 0, { 0, },				    "-d-" },
+    { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_B }, "MFB" },
+    { 0, { 0, },				    "-f-" },
+  };
+
+
+/* Copy the prefix contained in *PTR (up to a '.' or a NUL) to DEST.
+   PTR will be adjusted to point to the start of the next portion
+   of the opcode, or at the NUL character. */
+
+static void
+get_opc_prefix (ptr, dest)
+     const char **ptr;
+     char *dest;
+{
+  char *c = strchr (*ptr, '.');
+  if (c != NULL)
+    {
+      memcpy (dest, *ptr, c - *ptr);
+      dest[c - *ptr] = '\0';
+      *ptr = c + 1;
+    }
+  else
+    {
+      int l = strlen (*ptr);
+      memcpy (dest, *ptr, l);
+      dest[l] = '\0';
+      *ptr += l;
+    }
+}
+
+/* Find the index of the entry in the string table corresponding to
+   STR; return -1 if one does not exist. */
+
+static short
+find_string_ent (str)
+     const char *str;
+{
+  short start = 0;
+  short end = sizeof (ia64_strings) / sizeof (const char *);
+  short i = (start + end) / 2;
+
+  if (strcmp (str, ia64_strings[end - 1]) > 0)
+    {
+      return -1;
+    }
+  while (start <= end)
+    {
+      int c = strcmp (str, ia64_strings[i]);
+      if (c < 0)
+	{
+	  end = i - 1;
+	}
+      else if (c == 0)
+	{
+	  return i;
+	}
+      else
+	{
+	  start = i + 1;
+	}
+      i = (start + end) / 2;
+    }
+  return -1;
+}
+
+/* Find the opcode in the main opcode table whose name is STRINGINDEX, or
+   return -1 if one does not exist. */
+
+static short
+find_main_ent (nameindex)
+     short nameindex;
+{
+  short start = 0;
+  short end = sizeof (main_table) / sizeof (struct ia64_main_table);
+  short i = (start + end) / 2;
+
+  if (nameindex < main_table[0].name_index
+      || nameindex > main_table[end - 1].name_index)
+    {
+      return -1;
+    }
+  while (start <= end)
+    {
+      if (nameindex < main_table[i].name_index)
+	{
+	  end = i - 1;
+	}
+      else if (nameindex == main_table[i].name_index)
+	{
+	  while (i > 0 && main_table[i - 1].name_index == nameindex)
+	    {
+	      i--;
+	    }
+	  return i;
+	}
+      else
+	{
+	  start = i + 1;
+	}
+      i = (start + end) / 2;
+    }
+  return -1;
+}
+
+/* Find the index of the entry in the completer table that is part of
+   MAIN_ENT (starting from PREV_COMPLETER) that matches NAME, or
+   return -1 if one does not exist. */
+
+static short 
+find_completer (main_ent, prev_completer, name)
+     short main_ent;
+     short prev_completer;
+     const char *name;
+{
+  short name_index = find_string_ent (name);
+
+  if (name_index < 0)
+    {
+      return -1;
+    }
+
+  if (prev_completer == -1)
+    {
+      prev_completer = main_table[main_ent].completers;
+    }
+  else
+    {
+      prev_completer = completer_table[prev_completer].subentries;
+    }
+
+  while (prev_completer != -1)
+    {
+      if (completer_table[prev_completer].name_index == name_index)
+	{
+	  return prev_completer;
+	}
+      prev_completer = completer_table[prev_completer].alternative;
+    }
+  return -1;
+}
+
+/* Apply the completer referred to by COMPLETER_INDEX to OPCODE, and
+   return the result. */
+
+static ia64_insn
+apply_completer (opcode, completer_index)
+     ia64_insn opcode;
+     int completer_index;
+{
+  ia64_insn mask = completer_table[completer_index].mask;
+  ia64_insn bits = completer_table[completer_index].bits;
+  int shiftamt = (completer_table[completer_index].offset & 63);
+
+  mask = mask << shiftamt;
+  bits = bits << shiftamt;
+  opcode = (opcode & ~mask) | bits;
+  return opcode;
+}
+
+/* Extract BITS number of bits starting from OP_POINTER + BITOFFSET in
+   the dis_table array, and return its value.  (BITOFFSET is numbered
+   starting from MSB to LSB, so a BITOFFSET of 0 indicates the MSB of the
+   first byte in OP_POINTER.) */
+
+static int
+extract_op_bits (op_pointer, bitoffset, bits)
+     int op_pointer;
+     int bitoffset;
+     int bits;
+{
+  int res = 0;
+
+  op_pointer += (bitoffset / 8);
+
+  if (bitoffset % 8)
+    {
+      unsigned int op = dis_table[op_pointer++];
+      int numb = 8 - (bitoffset % 8);
+      int mask = (1 << numb) - 1;
+      int bata = (bits < numb) ? bits : numb;
+      int delta = numb - bata;
+
+      res = (res << bata) | ((op & mask) >> delta);
+      bitoffset += bata;
+      bits -= bata;
+    }
+  while (bits >= 8)
+    {
+      res = (res << 8) | (dis_table[op_pointer++] & 255);
+      bits -= 8;
+    }
+  if (bits > 0)
+    {
+      unsigned int op = (dis_table[op_pointer++] & 255);
+      res = (res << bits) | (op >> (8 - bits));
+    }
+  return res;
+}
+
+/* Examine the state machine entry at OP_POINTER in the dis_table
+   array, and extract its values into OPVAL and OP.  The length of the
+   state entry in bits is returned. */
+
+static int
+extract_op (op_pointer, opval, op)
+     int op_pointer;
+     int *opval;
+     unsigned int *op;
+{
+  int oplen = 5;
+
+  *op = dis_table[op_pointer];
+
+  if ((*op) & 0x40)
+    {
+      opval[0] = extract_op_bits (op_pointer, oplen, 5);
+      oplen += 5;
+    }
+  switch ((*op) & 0x30)
+    {
+    case 0x10:
+      {
+	opval[1] = extract_op_bits (op_pointer, oplen, 8);
+	oplen += 8;
+	opval[1] += op_pointer;
+	break;
+      }
+    case 0x20:
+      {
+	opval[1] = extract_op_bits (op_pointer, oplen, 16);
+	if (! (opval[1] & 32768))
+	  {
+	    opval[1] += op_pointer;
+	  }
+	oplen += 16;
+	break;
+      }
+    case 0x30:
+      {
+	oplen--;
+	opval[2] = extract_op_bits (op_pointer, oplen, 12);
+	oplen += 12;
+	opval[2] |= 32768;
+	break;
+      }
+    }
+  if (((*op) & 0x08) && (((*op) & 0x30) != 0x30))
+    {
+      opval[2] = extract_op_bits (op_pointer, oplen, 16);
+      oplen += 16;
+      if (! (opval[2] & 32768))
+	{
+	  opval[2] += op_pointer;
+	}
+    }
+  return oplen;
+}
+
+/* Returns a non-zero value if the opcode in the main_table list at
+   PLACE matches OPCODE and is of type TYPE. */
+
+static int
+opcode_verify (opcode, place, type)
+     ia64_insn opcode;
+     int place;
+     enum ia64_insn_type type;
+{
+  if (main_table[place].opcode_type != type)
+    {
+      return 0;
+    }
+  if (main_table[place].flags 
+      & (IA64_OPCODE_F2_EQ_F3 | IA64_OPCODE_LEN_EQ_64MCNT))
+    {
+      const struct ia64_operand *o1, *o2;
+      ia64_insn f2, f3;
+
+      if (main_table[place].flags & IA64_OPCODE_F2_EQ_F3)
+	{
+	  o1 = elf64_ia64_operands + IA64_OPND_F2;
+	  o2 = elf64_ia64_operands + IA64_OPND_F3;
+	  (*o1->extract) (o1, opcode, &f2);
+	  (*o2->extract) (o2, opcode, &f3);
+	  if (f2 != f3)
+	    return 0;
+	}
+      else
+	{
+	  ia64_insn len, count;
+
+	  /* length must equal 64-count: */
+	  o1 = elf64_ia64_operands + IA64_OPND_LEN6;
+	  o2 = elf64_ia64_operands + main_table[place].operands[2];
+	  (*o1->extract) (o1, opcode, &len);
+	  (*o2->extract) (o2, opcode, &count);
+	  if (len != 64 - count)
+	    return 0;
+	}
+    }
+  return 1;
+}
+
+/* Find an instruction entry in the ia64_dis_names array that matches
+   opcode OPCODE and is of type TYPE.  Returns either a positive index
+   into the array, or a negative value if an entry for OPCODE could
+   not be found.  */
+
+static int
+locate_opcode_ent (opcode, type)
+     ia64_insn opcode;
+     enum ia64_insn_type type;
+{
+  int currtest[41];
+  int bitpos[41];
+  int op_ptr[41];
+  int currstatenum = 0;
+
+  currtest[currstatenum] = 0;
+  op_ptr[currstatenum] = 0;
+  bitpos[currstatenum] = 40;
+
+  while (1)
+    {
+      int op_pointer = op_ptr[currstatenum];
+      unsigned int op;
+      int currbitnum = bitpos[currstatenum];
+      int oplen;
+      int opval[3];
+      int next_op;
+      int currbit;
+
+      oplen = extract_op (op_pointer, opval, &op);
+
+      bitpos[currstatenum] = currbitnum;
+
+      /* Skip opval[0] bits in the instruction. */
+      if (op & 0x40)
+	{
+	  currbitnum -= opval[0];
+	}
+
+      /* The value of the current bit being tested. */
+      currbit = opcode & (((ia64_insn) 1) << currbitnum) ? 1 : 0;
+      next_op = -1;
+
+      /* We always perform the tests specified in the current state in
+	 a particular order, falling through to the next test if the
+	 previous one failed. */
+      switch (currtest[currstatenum])
+	{
+	case 0:
+	  currtest[currstatenum]++;
+	  if (currbit == 0 && (op & 0x80))
+	    {
+	      /* Check for a zero bit.  If this test solely checks for
+		 a zero bit, we can check for up to 8 consecutive zero
+		 bits (the number to check is specified by the lower 3
+		 bits in the state code.)
+
+		 If the state instruction matches, we go to the very
+		 next state instruction; otherwise, try the next test. */
+
+	      if ((op & 0xf8) == 0x80)
+		{
+		  int count = op & 0x7;
+		  int x;
+
+		  for (x = 0; x <= count; x++)
+		    {
+		      int i =
+			opcode & (((ia64_insn) 1) << (currbitnum - x)) ? 1 : 0;
+		      if (i)
+			{
+			  break;
+			}
+		    }
+		  if (x > count)
+		    {
+		      next_op = op_pointer + ((oplen + 7) / 8);
+		      currbitnum -= count;
+		      break;
+		    }
+		}
+	      else if (! currbit)
+		{
+		  next_op = op_pointer + ((oplen + 7) / 8);
+		  break;
+		}
+	    }
+	  /* FALLTHROUGH */
+	case 1:
+	  /* If the bit in the instruction is one, go to the state
+	     instruction specified by opval[1]. */
+	  currtest[currstatenum]++;
+	  if (currbit && (op & 0x30) != 0 && ((op & 0x30) != 0x30))
+	    {
+	      next_op = opval[1];
+	      break;
+	    }
+	  /* FALLTHROUGH */
+	case 2:
+	  /* Don't care.  Skip the current bit and go to the state
+	     instruction specified by opval[2].
+
+	     An encoding of 0x30 is special; this means that a 12-bit
+	     offset into the ia64_dis_names[] array is specified.  */
+	  currtest[currstatenum]++;
+	  if ((op & 0x08) || ((op & 0x30) == 0x30))
+	    {
+	      next_op = opval[2];
+	      break;
+	    }
+	}
+
+      /* If bit 15 is set in the address of the next state, an offset
+	 in the ia64_dis_names array was specified instead.  We then
+	 check to see if an entry in the list of opcodes matches the
+	 opcode we were given; if so, we have succeeded.  */
+
+      if ((next_op >= 0) && (next_op & 32768))
+	{
+	  short disent = next_op & 32767;
+
+	  if (next_op > 65535)
+	    {
+	      abort ();
+	    }
+
+	  /* Run through the list of opcodes to check, trying to find
+	     one that matches.  */
+	  while (disent >= 0)
+	    {
+	      int place = ia64_dis_names[disent].insn_index;
+
+	      if (opcode_verify (opcode, place, type))
+		{
+		  break;
+		}
+	      if (ia64_dis_names[disent].next_flag)
+		{
+		  disent++;
+		}
+	      else
+		{
+		  disent = -1;
+		}
+	    }
+
+	  if (disent >= 0)
+	    {
+	      return disent;
+	    }
+	  else
+	    {
+	      /* Failed to match; try the next test in this state. */
+	      next_op = -2;
+	    }
+	}
+
+      /* next_op == -1 is "back up to the previous state".
+	 next_op == -2 is "stay in this state and try the next test".
+	 Otherwise, transition to the state indicated by next_op. */
+
+      if (next_op == -1)
+	{
+	  currstatenum--;
+	  if (currstatenum < 0)
+	    {
+	      return -1;
+	    }
+	}
+      else if (next_op >= 0)
+	{
+	  currstatenum++;
+	  bitpos[currstatenum] = currbitnum - 1;
+	  op_ptr[currstatenum] = next_op;
+	  currtest[currstatenum] = 0;
+	}
+    }
+}
+
+/* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */
+
+static struct ia64_opcode *
+make_ia64_opcode (opcode, name, place, depind)
+     ia64_insn opcode;
+     const char *name;
+     int place;
+     int depind;
+{
+  struct ia64_opcode *res =
+    (struct ia64_opcode *) xmalloc (sizeof (struct ia64_opcode));
+  res->name = xstrdup (name);
+  res->type = main_table[place].opcode_type;
+  res->num_outputs = main_table[place].num_outputs;
+  res->opcode = opcode;
+  res->mask = main_table[place].mask;
+  res->operands[0] = main_table[place].operands[0];
+  res->operands[1] = main_table[place].operands[1];
+  res->operands[2] = main_table[place].operands[2];
+  res->operands[3] = main_table[place].operands[3];
+  res->operands[4] = main_table[place].operands[4];
+  res->flags = main_table[place].flags;
+  res->ent_index = place;
+  res->dependencies = &op_dependencies[depind];
+  return res;
+}
+
+/* Determine the ia64_opcode entry for the opcode specified by INSN
+   and TYPE.  If a valid entry is not found, return NULL. */
+struct ia64_opcode *
+ia64_dis_opcode (insn, type)
+     ia64_insn insn;
+     enum ia64_insn_type type;
+{
+  int disent = locate_opcode_ent (insn, type);
+
+  if (disent < 0)
+    {
+      return NULL;
+    }
+  else
+    {
+      unsigned int cb = ia64_dis_names[disent].completer_index;
+      static char name[128];
+      int place = ia64_dis_names[disent].insn_index;
+      int ci = main_table[place].completers;
+      ia64_insn tinsn = main_table[place].opcode;
+
+      strcpy (name, ia64_strings [main_table[place].name_index]);
+
+      while (cb)
+	{
+	  if (cb & 1)
+	    {
+	      int cname = completer_table[ci].name_index;
+
+	      tinsn = apply_completer (tinsn, ci);
+
+	      if (ia64_strings[cname][0] != '\0')
+		{
+		  strcat (name, ".");
+		  strcat (name, ia64_strings[cname]);
+		}
+	      if (cb != 1)
+		{
+		  ci = completer_table[ci].subentries;
+		}
+	    }
+	  else
+	    {
+	      ci = completer_table[ci].alternative;
+	    }
+	  if (ci < 0)
+	    {
+	      abort ();
+	    }
+	  cb = cb >> 1;
+	}
+      if (tinsn != (insn & main_table[place].mask))
+	{
+	  abort ();
+	}
+      return make_ia64_opcode (insn, name, place, 
+                               completer_table[ci].dependencies);
+    }
+}
+
+/* Search the main_opcode table starting from PLACE for an opcode that
+   matches NAME.  Return NULL if one is not found. */
+
+static struct ia64_opcode *
+ia64_find_matching_opcode (name, place)
+     const char *name;
+     short place;
+{
+  char op[129];
+  const char *suffix;
+  short name_index;
+
+  if (strlen (name) > 128)
+    {
+      return NULL;
+    }
+  suffix = name;
+  get_opc_prefix (&suffix, op);
+  name_index = find_string_ent (op);
+  if (name_index < 0)
+    {
+      return NULL;
+    }
+
+  while (main_table[place].name_index == name_index)
+    {
+      const char *curr_suffix = suffix;
+      ia64_insn curr_insn = main_table[place].opcode;
+      short completer = -1;
+
+      do {
+      	if (suffix[0] == '\0')
+	  {
+	    completer = find_completer (place, completer, suffix);
+	  }
+	else
+	  {
+	    get_opc_prefix (&curr_suffix, op);
+	    completer = find_completer (place, completer, op);
+	  }
+	if (completer != -1)
+	  {
+	    curr_insn = apply_completer (curr_insn, completer);
+	  }
+      } while (completer != -1 && curr_suffix[0] != '\0');
+
+      if (completer != -1 && curr_suffix[0] == '\0'
+	  && completer_table[completer].terminal_completer)
+	{
+          int depind = completer_table[completer].dependencies;
+	  return make_ia64_opcode (curr_insn, name, place, depind);
+	}
+      else
+	{
+	  place++;
+	}
+    }
+  return NULL;
+}
+
+/* Find the next opcode after PREV_ENT that matches PREV_ENT, or return NULL
+   if one does not exist.
+
+   It is the caller's responsibility to invoke ia64_free_opcode () to
+   release any resources used by the returned entry. */
+
+struct ia64_opcode *
+ia64_find_next_opcode (prev_ent)
+     struct ia64_opcode *prev_ent;
+{
+  return ia64_find_matching_opcode (prev_ent->name,
+				    prev_ent->ent_index + 1);
+}
+
+/* Find the first opcode that matches NAME, or return NULL if it does
+   not exist.
+
+   It is the caller's responsibility to invoke ia64_free_opcode () to
+   release any resources used by the returned entry. */
+
+struct ia64_opcode *
+ia64_find_opcode (name)
+     const char *name;
+{
+  char op[129];
+  const char *suffix;
+  short place;
+  short name_index;
+
+  if (strlen (name) > 128)
+    {
+      return NULL;
+    }
+  suffix = name;
+  get_opc_prefix (&suffix, op);
+  name_index = find_string_ent (op);
+  if (name_index < 0)
+    {
+      return NULL;
+    }
+
+  place = find_main_ent (name_index);
+
+  if (place < 0)
+    {
+      return NULL;
+    }
+  return ia64_find_matching_opcode (name, place);
+}
+
+/* Free any resources used by ENT. */
+void
+ia64_free_opcode (ent)
+     struct ia64_opcode *ent;
+{
+  free ((void *)ent->name);
+  free (ent);
+}
+
+const struct ia64_dependency *
+ia64_find_dependency (index)
+  int index;
+{
+  index = DEP(index);
+
+  if (index < 0 || index >= sizeof(dependencies) / sizeof(dependencies[0]))
+    return NULL;
+
+  return &dependencies[index];
+}
diff --git a/opcodes/ia64-opc.h b/opcodes/ia64-opc.h
new file mode 100644
index 0000000..8a208fd
--- /dev/null
+++ b/opcodes/ia64-opc.h
@@ -0,0 +1,129 @@
+/* ia64-opc.h -- IA-64 opcode table.
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the
+   Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
+
+#ifndef IA64_OPC_H
+#define IA64_OPC_H
+
+#include "opcode/ia64.h"
+
+/* define a couple of abbreviations: */
+
+#define bOp(x)	(((ia64_insn) ((x) & 0xf)) << 37)
+#define mOp	bOp (-1)
+#define Op(x)	bOp (x), mOp
+
+#define FIRST		IA64_OPCODE_FIRST
+#define X_IN_MLX	IA64_OPCODE_X_IN_MLX
+#define LAST		IA64_OPCODE_LAST
+#define PRIV		IA64_OPCODE_PRIV
+#define NO_PRED		IA64_OPCODE_NO_PRED
+#define SLOT2		IA64_OPCODE_SLOT2
+#define PSEUDO		IA64_OPCODE_PSEUDO
+#define F2_EQ_F3	IA64_OPCODE_F2_EQ_F3
+#define LEN_EQ_64MCNT	IA64_OPCODE_LEN_EQ_64MCNT
+#define MOD_RRBS        IA64_OPCODE_MOD_RRBS
+
+#define AR_CCV	IA64_OPND_AR_CCV
+#define AR_PFS	IA64_OPND_AR_PFS
+#define C1	IA64_OPND_C1
+#define C8	IA64_OPND_C8
+#define C16	IA64_OPND_C16
+#define GR0	IA64_OPND_GR0
+#define IP	IA64_OPND_IP
+#define PR	IA64_OPND_PR
+#define PR_ROT	IA64_OPND_PR_ROT
+#define PSR	IA64_OPND_PSR
+#define PSR_L	IA64_OPND_PSR_L
+#define PSR_UM	IA64_OPND_PSR_UM
+
+#define AR3	IA64_OPND_AR3
+#define B1	IA64_OPND_B1
+#define B2	IA64_OPND_B2
+#define CR3	IA64_OPND_CR3
+#define F1	IA64_OPND_F1
+#define F2	IA64_OPND_F2
+#define F3	IA64_OPND_F3
+#define F4	IA64_OPND_F4
+#define P1	IA64_OPND_P1
+#define P2	IA64_OPND_P2
+#define R1	IA64_OPND_R1
+#define R2	IA64_OPND_R2
+#define R3	IA64_OPND_R3
+#define R3_2	IA64_OPND_R3_2
+
+#define CPUID_R3 IA64_OPND_CPUID_R3
+#define DBR_R3	IA64_OPND_DBR_R3
+#define DTR_R3	IA64_OPND_DTR_R3
+#define ITR_R3	IA64_OPND_ITR_R3
+#define IBR_R3	IA64_OPND_IBR_R3
+#define MR3	IA64_OPND_MR3
+#define MSR_R3	IA64_OPND_MSR_R3
+#define PKR_R3	IA64_OPND_PKR_R3
+#define PMC_R3	IA64_OPND_PMC_R3
+#define PMD_R3	IA64_OPND_PMD_R3
+#define RR_R3	IA64_OPND_RR_R3
+
+#define CCNT5	IA64_OPND_CCNT5
+#define CNT2a	IA64_OPND_CNT2a
+#define CNT2b	IA64_OPND_CNT2b
+#define CNT2c	IA64_OPND_CNT2c
+#define CNT5	IA64_OPND_CNT5
+#define CNT6	IA64_OPND_CNT6
+#define CPOS6a	IA64_OPND_CPOS6a
+#define CPOS6b	IA64_OPND_CPOS6b
+#define CPOS6c	IA64_OPND_CPOS6c
+#define IMM1	IA64_OPND_IMM1
+#define IMM14	IA64_OPND_IMM14
+#define IMM17	IA64_OPND_IMM17
+#define IMM22	IA64_OPND_IMM22
+#define IMM44	IA64_OPND_IMM44
+#define SOF	IA64_OPND_SOF
+#define SOL	IA64_OPND_SOL
+#define SOR	IA64_OPND_SOR
+#define IMM8	IA64_OPND_IMM8
+#define IMM8U4	IA64_OPND_IMM8U4
+#define IMM8M1	IA64_OPND_IMM8M1
+#define IMM8M1U4 IA64_OPND_IMM8M1U4
+#define IMM8M1U8 IA64_OPND_IMM8M1U8
+#define IMM9a	IA64_OPND_IMM9a
+#define IMM9b	IA64_OPND_IMM9b
+#define IMMU2	IA64_OPND_IMMU2
+#define IMMU21	IA64_OPND_IMMU21
+#define IMMU24	IA64_OPND_IMMU24
+#define IMMU62	IA64_OPND_IMMU62
+#define IMMU64	IA64_OPND_IMMU64
+#define IMMU7a	IA64_OPND_IMMU7a
+#define IMMU7b	IA64_OPND_IMMU7b
+#define IMMU9	IA64_OPND_IMMU9
+#define INC3	IA64_OPND_INC3
+#define LEN4	IA64_OPND_LEN4
+#define LEN6	IA64_OPND_LEN6
+#define MBTYPE4	IA64_OPND_MBTYPE4
+#define MHTYPE8	IA64_OPND_MHTYPE8
+#define POS6	IA64_OPND_POS6
+#define TAG13	IA64_OPND_TAG13
+#define TAG13b	IA64_OPND_TAG13b
+#define TGT25	IA64_OPND_TGT25
+#define TGT25b	IA64_OPND_TGT25b
+#define TGT25c	IA64_OPND_TGT25c
+#define TGT64   IA64_OPND_TGT64
+
+#endif
diff --git a/opcodes/ia64-raw.tbl b/opcodes/ia64-raw.tbl
new file mode 100644
index 0000000..3b39e73
--- /dev/null
+++ b/opcodes/ia64-raw.tbl
@@ -0,0 +1,171 @@
+Resource Name;	Writers;	Readers;	Semantics of Dependency
+ALAT;	chk.a.clr, IC:mem-readers-alat, IC:mem-writers, IC:invala-all;	IC:mem-readers-alat, IC:mem-writers, IC:chk-a, invala.e;	none
+AR[BSP];	br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi;	br.call, brl.call, br.ia, br.ret, cover, flushrs, loadrs, IC:mov-from-AR-BSP, rfi;	impliedF
+AR[BSPSTORE];	alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE;	alloc, br.ia, flushrs, IC:mov-from-AR-BSPSTORE;	impliedF
+AR[CCV];	IC:mov-to-AR-CCV;	br.ia, IC:cmpxchg, IC:mov-from-AR-CCV;	impliedF
+AR[EC];	IC:mod-sched-brs, br.ret, IC:mov-to-AR-EC;	br.call, brl.call, br.ia, IC:mod-sched-brs, IC:mov-from-AR-EC;	impliedF
+AR[FPSR].sf0.controls;	IC:mov-to-AR-FPSR, fsetc.s0;	br.ia, IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0, fsetc, IC:mov-from-AR-FPSR;	impliedF
+AR[FPSR].sf1.controls;	IC:mov-to-AR-FPSR, fsetc.s1;	br.ia, IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-from-AR-FPSR;	impliedF
+AR[FPSR].sf2.controls;	IC:mov-to-AR-FPSR, fsetc.s2;	br.ia, IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-from-AR-FPSR;	impliedF
+AR[FPSR].sf3.controls;	IC:mov-to-AR-FPSR, fsetc.s3;	br.ia, IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-from-AR-FPSR;	impliedF
+AR[FPSR].sf0.flags;	IC:fp-arith-s0, fclrf.s0, IC:fcmp-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR;	br.ia, fchkf, IC:mov-from-AR-FPSR;	impliedF
+AR[FPSR].sf1.flags;	IC:fp-arith-s1, fclrf.s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR;	br.ia, fchkf.s1, IC:mov-from-AR-FPSR;	impliedF
+AR[FPSR].sf2.flags;	IC:fp-arith-s2, fclrf.s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR;	br.ia, fchkf.s2, IC:mov-from-AR-FPSR;	impliedF
+AR[FPSR].sf3.flags;	IC:fp-arith-s3, fclrf.s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR;	br.ia, fchkf.s3, IC:mov-from-AR-FPSR;	impliedF
+AR[FPSR].traps;	IC:mov-to-AR-FPSR;	br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR;	impliedF
+AR[FPSR].rv;	IC:mov-to-AR-FPSR;	br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR;	impliedF
+AR[ITC];	IC:mov-to-AR-ITC;	br.ia, IC:mov-from-AR-ITC;	impliedF
+AR[K%], % in 0 - 7;	IC:mov-to-AR-K+1;	br.ia, IC:mov-from-AR-K+1;	impliedF
+AR[LC];	IC:mod-sched-brs-counted, IC:mov-to-AR-LC;	br.ia, IC:mod-sched-brs-counted, IC:mov-from-AR-LC;	impliedF
+AR[PFS];	br.call, brl.call;	alloc, br.ia, br.ret, epc, IC:mov-from-AR-PFS;	impliedF
+AR[PFS];	IC:mov-to-AR-PFS;	alloc, br.ia, epc, IC:mov-from-AR-PFS;	impliedF
+AR[PFS];	IC:mov-to-AR-PFS;	br.ret;	none
+AR[RNAT];	alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE;	alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RNAT;	impliedF
+AR[RSC];	IC:mov-to-AR-RSC;	alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RSC, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-RNAT, IC:mov-from-AR-RNAT, IC:mov-to-AR-BSPSTORE;	impliedF
+AR[UNAT]{%}, % in 0 - 63;	IC:mov-to-AR-UNAT, st8.spill;	br.ia, ld8.fill, IC:mov-from-AR-UNAT;	impliedF
+AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111;	IC:none;	br.ia, IC:mov-from-AR-rv+1;	none
+AR%, % in 48-63, 112-127;	IC:mov-to-AR-ig+1;	br.ia, IC:mov-from-AR-ig+1;	impliedF
+BR%, % in 0 - 7;	br.call+1, brl.call+1;	IC:indirect-brs+1, IC:indirect-brp+1, IC:mov-from-BR+1;	impliedF
+BR%, % in 0 - 7;	IC:mov-to-BR+1;	IC:indirect-brs+1;	none
+BR%, % in 0 - 7;	IC:mov-to-BR+1;	IC:indirect-brp+1, IC:mov-from-BR+1;	impliedF
+CFM;	IC:mod-sched-brs;	IC:mod-sched-brs;	impliedF
+CFM;	IC:mod-sched-brs;	cover, alloc, rfi, loadrs, br.ret, br.call, brl.call;	impliedF
+CFM;	IC:mod-sched-brs;	IC:cfm-readers+2;	impliedF
+CFM;	br.call, brl.call, br.ret, clrrrb, cover, rfi;	IC:cfm-readers;	impliedF
+CFM;	alloc;	IC:cfm-readers;	none
+CPUID#;	IC:none;	IC:mov-from-IND-CPUID+3;	specific
+CR[CMCV];	IC:mov-to-CR-CMCV;	IC:mov-from-CR-CMCV;	data
+CR[DCR];	IC:mov-to-CR-DCR;	IC:mov-from-CR-DCR, IC:mem-readers-spec;	data
+CR[EOI];	IC:mov-to-CR-EOI;	IC:none;	SC Section 10.8.3.4
+CR[GPTA];	IC:mov-to-CR-GPTA;	IC:mov-from-CR-GPTA, thash;	data
+CR[IFA];	IC:mov-to-CR-IFA;	itc.i, itc.d, itr.i, itr.d;	implied
+CR[IFA];	IC:mov-to-CR-IFA;	IC:mov-from-CR-IFA;	data
+CR[IFS];	IC:mov-to-CR-IFS;	IC:mov-from-CR-IFS;	data
+CR[IFS];	IC:mov-to-CR-IFS;	rfi;	implied
+CR[IFS];	cover;	rfi, IC:mov-from-CR-IFS;	implied
+CR[IHA];	IC:mov-to-CR-IHA;	IC:mov-from-CR-IHA;	data
+CR[IIM];	IC:mov-to-CR-IIM;	IC:mov-from-CR-IIM;	data
+CR[IIP];	IC:mov-to-CR-IIP;	IC:mov-from-CR-IIP;	data
+CR[IIP];	IC:mov-to-CR-IIP;	rfi;	implied
+CR[IIPA];	IC:mov-to-CR-IIPA;	IC:mov-from-CR-IIPA;	data
+CR[IPSR];	IC:mov-to-CR-IPSR;	IC:mov-from-CR-IPSR;	data
+CR[IPSR];	IC:mov-to-CR-IPSR;	rfi;	implied
+CR[IRR%], % in 0 - 3;	IC:mov-from-CR-IVR;	IC:mov-from-CR-IRR+1;	data
+CR[ISR];	IC:mov-to-CR-ISR;	IC:mov-from-CR-ISR;	data
+CR[ITIR];	IC:mov-to-CR-ITIR;	IC:mov-from-CR-ITIR;	data
+CR[ITIR];	IC:mov-to-CR-ITIR;	itc.i, itc.d, itr.i, itc.d;	implied
+CR[ITM];	IC:mov-to-CR-ITM;	IC:mov-from-CR-ITM;	data
+CR[ITV];	IC:mov-to-CR-ITV;	IC:mov-from-CR-ITV;	data
+CR[IVA];	IC:mov-to-CR-IVA;	IC:mov-from-CR-IVA;	instr
+CR[IVR];	IC:none;	IC:mov-from-CR-IVR;	SC Section 10.8.3.2
+CR[LID];	IC:mov-to-CR-LID;	IC:mov-from-CR-LID;	SC Section 10.8.3.1
+CR[LRR%], % in 0 - 1;	IC:mov-to-CR-LRR+1;	IC:mov-from-CR-LRR+1;	data
+CR[PMV];	IC:mov-to-CR-PMV;	IC:mov-from-CR-PMV;	data
+CR[PTA];	IC:mov-to-CR-PTA;	IC:mov-from-CR-PTA, thash;	data
+CR[TPR];	IC:mov-to-CR-TPR;	IC:mov-from-CR-TPR, IC:mov-from-CR-IVR;	data
+CR[TPR];	IC:mov-to-CR-TPR;	IC:mov-to-PSR-l, rfi, rsm, ssm;	SC Section 10.8.3.3
+CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127;	IC:none;	IC:mov-from-CR-rv+1;	none
+DBR#;	IC:mov-to-IND-DBR+3;	IC:mov-from-IND-DBR+3;	impliedF
+DBR#;	IC:mov-to-IND-DBR+3;	IC:probe-all, IC:lfetch-all, IC:mem-readers, IC:mem-writers;	data
+DTC;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d;	IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa;	data
+DTC;	itc.i, itc.d, itr.i, itr.d;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d;	impliedF
+DTC;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d;	none
+DTC;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d;	itc.i, itc.d, itr.i, itr.d;	impliedF
+DTC_LIMIT*;	ptc.g, ptc.ga;	ptc.g, ptc.ga;	impliedF
+DTR;	itr.d;	IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa;	data
+DTR;	itr.d;	ptc.g, ptc.ga, ptc.l, ptr.d, itr.d;	impliedF
+DTR;	ptr.d;	IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa;	data
+DTR;	ptr.d;	ptc.g, ptc.ga, ptc.l, ptr.d;	none
+DTR;	ptr.d;	itr.d, itc.d;	impliedF
+FR%, % in 0 - 1;	IC:none;	IC:fr-readers+1;	none
+FR%, % in 2 - 127;	IC:fr-writers+1\IC:ldf-c+1\IC:ldfp-c+1;	IC:fr-readers+1;	impliedF
+FR%, % in 2 - 127;	IC:ldf-c+1, IC:ldfp-c+1;	IC:fr-readers+1;	none
+GR0;	IC:none;	IC:gr-readers+1, IC:mov-immediate;	none
+GR%, % in 1 - 127;	IC:ld-c+1+13;	IC:gr-readers+1;	none
+GR%, % in 1 - 127;	IC:gr-writers+1\IC:ld-c+1+13;	IC:gr-readers+1;	impliedF
+IBR#;	IC:mov-to-IND-IBR+3;	IC:mov-from-IND-IBR+3;	impliedF
+InService*;	IC:mov-to-CR-EOI;	IC:mov-from-CR-IVR;	data
+InService*;	IC:mov-from-CR-IVR;	IC:mov-from-CR-IVR;	impliedF
+InService*;	IC:mov-to-CR-EOI;	IC:mov-to-CR-EOI;	impliedF
+IP;	IC:all;	IC:all;	none
+ITC;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d;	epc;	instr
+ITC;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d;	itc.i, itc.d, itr.i, itr.d;	impliedF
+ITC;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d;	ptr.i, ptr.d, ptc.e, ptc.g, ptc.ga, ptc.l;	none
+ITC;	itc.i, itc.d, itr.i, itr.d;	epc;	instr
+ITC;	itc.i, itc.d, itr.i, itr.d;	itc.d, itc.i, itr.d, itr.i, ptr.d, ptr.i, ptc.g, ptc.ga, ptc.l;	impliedF
+ITC_LIMIT*;	ptc.g, ptc.ga;	ptc.g, ptc.ga;	impliedF
+ITR;	itr.i;	itr.i, itc.i, ptc.g, ptc.ga, ptc.l, ptr.i;	impliedF
+ITR;	itr.i;	epc;	instr
+ITR;	ptr.i;	itc.i, itr.i;	impliedF
+ITR;	ptr.i;	ptc.g, ptc.ga, ptc.l, ptr.i;	none
+ITR;	ptr.i;	epc;	instr
+memory;	IC:mem-writers;	IC:mem-readers;	none
+MSR#;	IC:mov-to-IND-MSR+5;	IC:mov-from-IND-MSR+5;	specific
+PKR#;	IC:mov-to-IND-PKR+3;	IC:mem-readers, IC:mem-writers, IC:mov-from-IND-PKR+4, IC:probe-all;	data
+PKR#;	IC:mov-to-IND-PKR+3;	IC:mov-to-IND-PKR+4;	none
+PKR#;	IC:mov-to-IND-PKR+3;	IC:mov-from-IND-PKR+3;	impliedF
+PKR#;	IC:mov-to-IND-PKR+3;	IC:mov-to-IND-PKR+3;	impliedF
+PMC#;	IC:mov-to-IND-PMC+3;	IC:mov-from-IND-PMC+3;	impliedF
+PMC#;	IC:mov-to-IND-PMC+3;	IC:mov-from-IND-PMD+3;	SC+3 Section 12.1.1
+PMD#;	IC:mov-to-IND-PMD+3;	IC:mov-from-IND-PMD+3;	impliedF
+PR0;	IC:pr-writers+1;	IC:pr-readers-br+1, IC:pr-readers-nobr-nomovpr+1 , IC:mov-from-PR+12, IC:mov-to-PR+12;	none
+PR%, % in 1 - 62;	IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg;	IC:pr-readers-nobr-nomovpr+1 , IC:mov-from-PR, IC:mov-to-PR+12;	impliedF
+PR%, % in 1 - 62;	IC:pr-writers-fp+1;	IC:pr-readers-br+1;	impliedF
+PR%, % in 1 - 62;	IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg;	IC:pr-readers-br+1;	none
+PR63;	IC:mod-sched-brs, IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg;	IC:pr-readers-nobr-nomovpr+1 , IC:mov-from-PR, IC:mov-to-PR+12;	impliedF
+PR63;	IC:pr-writers-fp+1, IC:mod-sched-brs;	IC:pr-readers-br+1;	impliedF
+PR63;	IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg;	IC:pr-readers-br+1;	none
+PSR.ac;	IC:user-mask-writers-partial+7, IC:mov-to-PSR-um;	IC:mem-readers, IC:mem-writers;	implied
+PSR.ac;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mem-readers, IC:mem-writers;	data
+PSR.ac;	IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-PSR, IC:mov-from-PSR-um;	impliedF
+PSR.be;	IC:user-mask-writers-partial+7, IC:mov-to-PSR-um;	IC:mem-readers, IC:mem-writers;	implied
+PSR.be;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mem-readers, IC:mem-writers;	data
+PSR.be;	IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-PSR, IC:mov-from-PSR-um;	impliedF
+PSR.bn;	bsw, rfi;	IC:gr-readers+10, IC:gr-writers+10;	impliedF
+PSR.cpl;	epc, br.ret, rfi;	IC:priv-ops, br.call, brl.call, epc, IC:mov-from-AR-ITC, IC:mov-to-AR-ITC, IC:mov-to-AR-RSC, IC:mov-to-AR-K, IC:mov-from-IND-PMD, IC:probe-all, IC:mem-readers, IC:mem-writers, IC:lfetch-all;	implied
+PSR.da;	rfi;	IC:mem-readers, IC:lfetch-fault, IC:mem-writers, IC:probe-fault;	data
+PSR.db;	IC:mov-to-PSR-l;	IC:mem-readers, IC:mem-writers, IC:probe-fault;	data
+PSR.db;	IC:mov-to-PSR-l;	IC:mov-from-PSR;	impliedF
+PSR.db;	rfi;	IC:mem-readers, IC:mem-writers, IC:mov-from-PSR, IC:probe-fault;	data
+PSR.dd;	rfi;	IC:mem-readers, IC:probe-fault, IC:mem-writers, IC:lfetch-fault;	data
+PSR.dfh;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:fr-readers+8, IC:fr-writers+8;	data
+PSR.dfh;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-PSR;	impliedF
+PSR.dfl;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:fr-writers+8, IC:fr-readers+8;	data
+PSR.dfl;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-PSR;	impliedF
+PSR.di;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	br.ia;	data
+PSR.di;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-PSR;	impliedF
+PSR.dt;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mem-readers, IC:mem-writers;	data
+PSR.dt;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-PSR;	impliedF
+PSR.ed;	rfi;	IC:lfetch-all, IC:mem-readers-spec;	data
+PSR.i;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l;	IC:mov-from-PSR;	impliedF
+PSR.i;	rfi;	IC:mov-from-PSR;	data
+PSR.ia;	rfi;	IC:none;	none
+PSR.ic;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-PSR;	impliedF
+PSR.ic;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	cover, itc.i, itc.d, itr.i, itr.d, IC:mov-from-CR-ITIR, IC:mov-from-CR-IFS, IC:mov-from-CR-IIM, IC:mov-from-CR-IIP, IC:mov-from-CR-IPSR, IC:mov-from-CR-ISR, IC:mov-from-CR-IFA, IC:mov-from-CR-IHA, IC:mov-from-CR-IIPA, IC:mov-to-CR-ITIR, IC:mov-to-CR-IFS, IC:mov-to-CR-IIM, IC:mov-to-CR-IIP, IC:mov-to-CR-IPSR, IC:mov-to-CR-ISR, IC:mov-to-CR-IFA, IC:mov-to-CR-IHA, IC:mov-to-CR-IIPA;	data
+PSR.id;	rfi;	IC:none;	none
+PSR.is;	br.ia, rfi;	IC:none;	none
+PSR.it;	rfi;	IC:branches, IC:mov-from-PSR, chk, epc, fchkf;	data
+PSR.lp;	IC:mov-to-PSR-l;	IC:mov-from-PSR;	impliedF
+PSR.lp;	IC:mov-to-PSR-l;	br.ret;	data
+PSR.lp;	rfi;	IC:mov-from-PSR, br.ret;	data
+PSR.mc;	rfi;	IC:mov-from-PSR;	none
+PSR.mfh;	IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-PSR-um, IC:mov-from-PSR;	impliedF
+PSR.mfl;	IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-PSR-um, IC:mov-from-PSR;	impliedF
+PSR.pk;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mem-readers, IC:mem-writers, IC:probe-all;	data
+PSR.pk;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-PSR;	impliedF
+PSR.pp;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-PSR;	impliedF
+PSR.ri;	rfi;	IC:none;	none
+PSR.rt;	IC:mov-to-PSR-l;	IC:mov-from-PSR;	impliedF
+PSR.rt;	IC:mov-to-PSR-l;	alloc, flushrs, loadrs;	data
+PSR.rt;	rfi;	IC:mov-from-PSR, alloc, flushrs, loadrs;	data
+PSR.si;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-PSR;	impliedF
+PSR.si;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-AR-ITC;	data
+PSR.sp;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-PSR;	impliedF
+PSR.sp;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-IND-PMD, IC:mov-to-PSR-um, rum, sum;	data
+PSR.ss;	rfi;	IC:all;	data
+PSR.tb;	IC:mov-to-PSR-l, rfi;	IC:branches, chk, fchkf;	data
+PSR.tb;	IC:mov-to-PSR-l, rfi;	IC:mov-from-PSR;	impliedF
+PSR.up;	IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:mov-from-PSR-um, IC:mov-from-PSR;	impliedF
+RR#;	IC:mov-to-IND-RR+6;	IC:mem-readers, IC:mem-writers, itc.i, itc.d, itr.i, itr.d, IC:probe-all, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, tak, thash, tpa, ttag;	data
+RR#;	IC:mov-to-IND-RR+6;	IC:mov-from-IND-RR+6;	impliedF
+RSE;	IC:rse-writers+14;	IC:rse-readers+14;	impliedF
diff --git a/opcodes/ia64-war.tbl b/opcodes/ia64-war.tbl
new file mode 100644
index 0000000..aa49e08
--- /dev/null
+++ b/opcodes/ia64-war.tbl
@@ -0,0 +1,2 @@
+Resource Name;	Readers;	Writers;	Results of Dependency
+PR63;	IC:pr-readers-br+1;	IC:mod-sched-brs;	impliedF
diff --git a/opcodes/ia64-waw.tbl b/opcodes/ia64-waw.tbl
new file mode 100644
index 0000000..0fa743e
--- /dev/null
+++ b/opcodes/ia64-waw.tbl
@@ -0,0 +1,125 @@
+Resource Name;	Writers;	Writers;	Semantics of Dependency
+ALAT;	IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all;	IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all;	none
+AR[BSP];	br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi;	br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi;	impliedF
+AR[BSPSTORE];	alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE;	alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE;	impliedF
+AR[CCV];	IC:mov-to-AR-CCV;	IC:mov-to-AR-CCV;	impliedF
+AR[EC];	br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC;	br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC;	impliedF
+AR[FPSR].sf0.controls;	IC:mov-to-AR-FPSR, fsetc.s0;	IC:mov-to-AR-FPSR, fsetc.s0;	impliedF
+AR[FPSR].sf1.controls;	IC:mov-to-AR-FPSR, fsetc.s1;	IC:mov-to-AR-FPSR, fsetc.s1;	impliedF
+AR[FPSR].sf2.controls;	IC:mov-to-AR-FPSR, fsetc.s2;	IC:mov-to-AR-FPSR, fsetc.s2;	impliedF
+AR[FPSR].sf3.controls;	IC:mov-to-AR-FPSR, fsetc.s3;	IC:mov-to-AR-FPSR, fsetc.s3;	impliedF
+AR[FPSR].sf0.flags;	IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0;	IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0;	none
+AR[FPSR].sf0.flags;	fclrf.s0, IC:fcmp-s0, IC:fp-arith-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR;	fclrf.s0, IC:mov-to-AR-FPSR;	impliedF
+AR[FPSR].sf1.flags;	IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1;	IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1;	none
+AR[FPSR].sf1.flags;	fclrf.s1, IC:fcmp-s1, IC:fp-arith-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR;	fclrf.s1, IC:mov-to-AR-FPSR;	impliedF
+AR[FPSR].sf2.flags;	IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2;	IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2;	none
+AR[FPSR].sf2.flags;	fclrf.s2, IC:fcmp-s2, IC:fp-arith-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR;	fclrf.s2, IC:mov-to-AR-FPSR;	impliedF
+AR[FPSR].sf3.flags;	IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3;	IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3;	none
+AR[FPSR].sf3.flags;	fclrf.s3, IC:fcmp-s3, IC:fp-arith-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR;	fclrf.s3, IC:mov-to-AR-FPSR;	impliedF
+AR[FPSR].rv;	IC:mov-to-AR-FPSR;	IC:mov-to-AR-FPSR;	impliedF
+AR[FPSR].traps;	IC:mov-to-AR-FPSR;	IC:mov-to-AR-FPSR;	impliedF
+AR[ITC];	IC:mov-to-AR-ITC;	IC:mov-to-AR-ITC;	impliedF
+AR[K%], % in 0 - 7;	IC:mov-to-AR-K+1;	IC:mov-to-AR-K+1;	impliedF
+AR[LC];	IC:mod-sched-brs-counted, IC:mov-to-AR-LC;	IC:mod-sched-brs-counted, IC:mov-to-AR-LC;	impliedF
+AR[PFS];	br.call, brl.call;	br.call, brl.call;	none
+AR[PFS];	br.call, brl.call;	IC:mov-to-AR-PFS;	impliedF
+AR[RNAT];	alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE;	alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE;	impliedF
+AR[RSC];	IC:mov-to-AR-RSC;	IC:mov-to-AR-RSC;	impliedF
+AR[UNAT]{%}, % in 0 - 63;	IC:mov-to-AR-UNAT, st8.spill;	IC:mov-to-AR-UNAT, st8.spill;	impliedF
+AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111;	IC:none;	IC:none;	none
+AR%, % in 48 - 63, 112-127;	IC:mov-to-AR-ig+1;	IC:mov-to-AR-ig+1;	impliedF
+BR%, % in 0 - 7;	br.call+1, brl.call+1;	IC:mov-to-BR+1;	impliedF
+BR%, % in 0 - 7;	IC:mov-to-BR+1;	IC:mov-to-BR+1;	impliedF
+BR%, % in 0 - 7;	br.call+1, brl.call+1;	br.call+1, brl.call+1;	none
+CFM;	IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi;	IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi;	impliedF
+CPUID#;	IC:none;	IC:none;	none
+CR[CMCV];	IC:mov-to-CR-CMCV;	IC:mov-to-CR-CMCV;	impliedF
+CR[DCR];	IC:mov-to-CR-DCR;	IC:mov-to-CR-DCR;	impliedF
+CR[EOI];	IC:mov-to-CR-EOI;	IC:mov-to-CR-EOI;	SC Section 10.8.3.4
+CR[GPTA];	IC:mov-to-CR-GPTA;	IC:mov-to-CR-GPTA;	impliedF
+CR[IFA];	IC:mov-to-CR-IFA;	IC:mov-to-CR-IFA;	impliedF
+CR[IFS];	IC:mov-to-CR-IFS, cover;	IC:mov-to-CR-IFS, cover;	impliedF
+CR[IHA];	IC:mov-to-CR-IHA;	IC:mov-to-CR-IHA;	impliedF
+CR[IIM];	IC:mov-to-CR-IIM;	IC:mov-to-CR-IIM;	impliedF
+CR[IIP];	IC:mov-to-CR-IIP;	IC:mov-to-CR-IIP;	impliedF
+CR[IIPA];	IC:mov-to-CR-IIPA;	IC:mov-to-CR-IIPA;	impliedF
+CR[IPSR];	IC:mov-to-CR-IPSR;	IC:mov-to-CR-IPSR;	impliedF
+CR[IRR%], % in 0 - 3;	IC:mov-from-CR-IVR;	IC:mov-from-CR-IVR;	impliedF
+CR[ISR];	IC:mov-to-CR-ISR;	IC:mov-to-CR-ISR;	impliedF
+CR[ITIR];	IC:mov-to-CR-ITIR;	IC:mov-to-CR-ITIR;	impliedF
+CR[ITM];	IC:mov-to-CR-ITM;	IC:mov-to-CR-ITM;	impliedF
+CR[ITV];	IC:mov-to-CR-ITV;	IC:mov-to-CR-ITV;	impliedF
+CR[IVA];	IC:mov-to-CR-IVA;	IC:mov-to-CR-IVA;	impliedF
+CR[IVR];	IC:none;	IC:none;	SC
+CR[LID];	IC:mov-to-CR-LID;	IC:mov-to-CR-LID;	SC
+CR[LRR%], % in 0 - 1;	IC:mov-to-CR-LRR+1;	IC:mov-to-CR-LRR+1;	impliedF
+CR[PMV];	IC:mov-to-CR-PMV;	IC:mov-to-CR-PMV;	impliedF
+CR[PTA];	IC:mov-to-CR-PTA;	IC:mov-to-CR-PTA;	impliedF
+CR[TPR];	IC:mov-to-CR-TPR;	IC:mov-to-CR-TPR;	impliedF
+CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127;	IC:none;	IC:none;	none
+DBR#;	IC:mov-to-IND-DBR+3;	IC:mov-to-IND-DBR+3;	impliedF
+DTC;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d;	none
+DTC;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d;	itc.i, itc.d, itr.i, itr.d;	impliedF
+DTC_LIMIT*;	ptc.g, ptc.ga;	ptc.g, ptc.ga;	impliedF
+DTR;	itr.d;	itr.d;	impliedF
+DTR;	itr.d;	ptr.d;	impliedF
+DTR;	ptr.d;	ptr.d;	none
+FR%, % in 0 - 1;	IC:none;	IC:none;	none
+FR%, % in 2 - 127;	IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1;	IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1;	impliedF
+GR0;	IC:none;	IC:none;	none
+GR%, % in 1 - 127;	IC:ld-c+1, IC:gr-writers+1;	IC:ld-c+1, IC:gr-writers+1;	impliedF
+IBR#;	IC:mov-to-IND-IBR+3;	IC:mov-to-IND-IBR+3;	impliedF
+InService*;	IC:mov-to-CR-EOI, IC:mov-from-CR-IVR;	IC:mov-to-CR-EOI, IC:mov-from-CR-IVR;	SC
+IP;	IC:all;	IC:all;	none
+ITC;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d;	none
+ITC;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d;	itc.i, itc.d, itr.i, itr.d;	impliedF
+ITR;	itr.i;	itr.i, ptr.i;	impliedF
+ITR;	ptr.i;	ptr.i;	none
+memory;	IC:mem-writers;	IC:mem-writers;	none
+MSR#;	IC:mov-to-IND-MSR+5;	IC:mov-to-IND-MSR+5;	SC
+PKR#;	IC:mov-to-IND-PKR+3;	IC:mov-to-IND-PKR+4;	none
+PKR#;	IC:mov-to-IND-PKR+3;	IC:mov-to-IND-PKR+3;	impliedF
+PMC#;	IC:mov-to-IND-PMC+3;	IC:mov-to-IND-PMC+3;	impliedF
+PMD#;	IC:mov-to-IND-PMD+3;	IC:mov-to-IND-PMD+3;	impliedF
+PR0;	IC:pr-writers+1;	IC:pr-writers+1;	none
+PR%, % in 1 - 62;	IC:pr-and-writers+1;	IC:pr-and-writers+1;	none
+PR%, % in 1 - 62;	IC:pr-or-writers+1;	IC:pr-or-writers+1;	none
+PR%, % in 1 - 62;	IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR+7;	IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR+7;	impliedF
+PR63;	IC:pr-and-writers+1;	IC:pr-and-writers+1;	none
+PR63;	IC:pr-or-writers+1;	IC:pr-or-writers+1;	none
+PR63;	IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR+7;	IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR+7;	impliedF
+PSR.ac;	IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	impliedF
+PSR.be;	IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	impliedF
+PSR.bn;	bsw, rfi;	bsw, rfi;	impliedF
+PSR.cpl;	epc, br.ret, rfi;	epc, br.ret, rfi;	impliedF
+PSR.da;	rfi;	rfi;	impliedF
+PSR.db;	IC:mov-to-PSR-l, rfi;	IC:mov-to-PSR-l, rfi;	impliedF
+PSR.dd;	rfi;	rfi;	impliedF
+PSR.dfh;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	impliedF
+PSR.dfl;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	impliedF
+PSR.di;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	impliedF
+PSR.dt;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	impliedF
+PSR.ed;	rfi;	rfi;	impliedF
+PSR.i;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	impliedF
+PSR.ia;	rfi;	rfi;	impliedF
+PSR.ic;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	impliedF
+PSR.id;	rfi;	rfi;	impliedF
+PSR.is;	br.ia, rfi;	br.ia, rfi;	impliedF
+PSR.it;	rfi;	rfi;	impliedF
+PSR.lp;	IC:mov-to-PSR-l, rfi;	IC:mov-to-PSR-l, rfi;	impliedF
+PSR.mc;	rfi;	rfi;	impliedF
+PSR.mfh;	IC:fr-writers+9;	IC:fr-writers+9;	none
+PSR.mfh;	IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	impliedF
+PSR.mfl;	IC:fr-writers+9;	IC:fr-writers+9;	none
+PSR.mfl;	IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	impliedF
+PSR.pk;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	impliedF
+PSR.pp;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	impliedF
+PSR.ri;	rfi;	rfi;	impliedF
+PSR.rt;	IC:mov-to-PSR-l, rfi;	IC:mov-to-PSR-l, rfi;	impliedF
+PSR.si;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	impliedF
+PSR.sp;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	impliedF
+PSR.ss;	rfi;	rfi;	impliedF
+PSR.tb;	IC:mov-to-PSR-l, rfi;	IC:mov-to-PSR-l, rfi;	impliedF
+PSR.up;	IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi;	impliedF
+RR#;	IC:mov-to-IND-RR+6;	IC:mov-to-IND-RR+6;	impliedF
+RSE;	IC:rse-writers+14;	IC:rse-writers+14;	impliedF