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| author | Doug Evans <dje@google.com> | 1998-06-10 17:56:18 +0000 |
|---|---|---|
| committer | Doug Evans <dje@google.com> | 1998-06-10 17:56:18 +0000 |
| commit | f3c7eb69df3f19a581d88b7141aace41c6475f77 (patch) | |
| tree | a598fa1d5045fdb50563128f661a38553b3d2f34 | |
| parent | c488e9b543af8f2b4076d4ddee1d3a14e1b5fbd3 (diff) | |
| download | gdb-f3c7eb69df3f19a581d88b7141aace41c6475f77.zip gdb-f3c7eb69df3f19a581d88b7141aace41c6475f77.tar.gz gdb-f3c7eb69df3f19a581d88b7141aace41c6475f77.tar.bz2 | |
* sim/m32r/addx.cgs: Add another test.
* sim/m32r/jmp.cgs: Add another test.
* sim/m32r/bra8-2.cgs: New testcase.
* sim/m32r/hello.ms: Run on m32rx too.
| -rw-r--r-- | sim/testsuite/ChangeLog | 9 | ||||
| -rw-r--r-- | sim/testsuite/sim/m32r/.Sanitize | 1 | ||||
| -rw-r--r-- | sim/testsuite/sim/m32r/addx.cgs | 39 |
3 files changed, 49 insertions, 0 deletions
diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog index 5d3118a..ff462bf 100644 --- a/sim/testsuite/ChangeLog +++ b/sim/testsuite/ChangeLog @@ -1,3 +1,12 @@ +Wed Jun 10 10:53:20 1998 Doug Evans <devans@seba.cygnus.com> + + * sim/m32r/addx.cgs: Add another test. + * sim/m32r/jmp.cgs: Add another test. +start-sanitize-m32rx + * sim/m32r/bra8-2.cgs: New testcase. + * sim/m32r/hello.ms: Run on m32rx too. +end-sanitize-m32rx + start-sanitize-sky Tue Jun 9 08:55:05 1998 Doug Evans <devans@canuck.cygnus.com> diff --git a/sim/testsuite/sim/m32r/.Sanitize b/sim/testsuite/sim/m32r/.Sanitize index e313082..53a2266 100644 --- a/sim/testsuite/sim/m32r/.Sanitize +++ b/sim/testsuite/sim/m32r/.Sanitize @@ -20,6 +20,7 @@ bcl24.cgs bcl8.cgs bncl24.cgs bncl8.cgs +bra8-2.cgs cmpeq.cgs cmpz.cgs divh.cgs diff --git a/sim/testsuite/sim/m32r/addx.cgs b/sim/testsuite/sim/m32r/addx.cgs new file mode 100644 index 0000000..c8eb14d --- /dev/null +++ b/sim/testsuite/sim/m32r/addx.cgs @@ -0,0 +1,39 @@ +# m32r testcase for addx $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addx +addx: + mvi_h_condbit 1 + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + addx r4, r5 + bc not_ok + test_h_gr r4, 4 + + mvi_h_gr r4, 0xfffffffe + addx r4, r5 + bnc not_ok + test_h_gr r4, 0 + + mvi_h_gr r4, -1 + mvi_h_gr r5, -1 + mvi_h_condbit 1 + addx r4,r5 + bnc not_ok + test_h_gr r4, -1 + + mvi_h_gr r4,-1 + mvi_h_gr r5,0x7fffffff + mvi_h_condbit 1 + addx r5,r4 + bnc not_ok + test_h_gr r5,0x7fffffff + + pass + +not_ok: + fail |