diff options
| author | Andrew Cagney <cagney@redhat.com> | 1998-03-03 05:39:49 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1998-03-03 05:39:49 +0000 |
| commit | ca6f76d13558a4ae3935f309db6d4540114b6a14 (patch) | |
| tree | ee1d95cf7cebcc52a8b7bd8d0f011c6420725d50 | |
| parent | 3cdda79a7cf4730828844e8523e42373214423a4 (diff) | |
| download | gdb-ca6f76d13558a4ae3935f309db6d4540114b6a14.zip gdb-ca6f76d13558a4ae3935f309db6d4540114b6a14.tar.gz gdb-ca6f76d13558a4ae3935f309db6d4540114b6a14.tar.bz2 | |
Fix DIV, DIV1 (wrong check for overflow) and DIVU1 (shouldn't check
for overflow).
Pacify GCC.
| -rw-r--r-- | sim/mips/ChangeLog | 20 | ||||
| -rw-r--r-- | sim/mips/mips.igen | 7 | ||||
| -rw-r--r-- | sim/mips/sim-main.h | 2 |
3 files changed, 26 insertions, 3 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 9b2a8e5..2044b41 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,23 @@ +Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-main.h (GETFCC): Return an unsigned value. + +start-sanitize-r5900 + * r5900.igen: Use an unsigned array index variable `i'. + (QFSRV): Ditto for variable bytes. + +end-sanitize-r5900 +Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * mips.igen (DIV): Fix check for -1 / MIN_INT. + (DADD): Result destination is RD not RT. + +start-sanitize-r5900 + * r5900.igen (DIV1): Fix check for -1 / MIN_INT. + (DIVU1): Don't check for MIN_INT / -1 as performing unsigned + divide. + +end-sanitize-r5900 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com> * sim-main.h (HIACCESS, LOACCESS): Always define. diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 839ae7a..64a7c73 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -1,3 +1,5 @@ +// -*- C -*- +// // <insn> ::= // <insn-word> { "+" <insn-word> } // ":" <format-name> @@ -624,9 +626,10 @@ *tx19: // end-sanitize-tx19 { + /* this check's for overflow */ ALU64_BEGIN (GPR[RS]); ALU64_ADD (GPR[RT]); - ALU64_END (GPR[RT]); + ALU64_END (GPR[RD]); } @@ -787,7 +790,7 @@ LO = EXTEND32 (0x80000000); HI = EXTEND32 (0); } - else if (d == -1 && d == 0x80000000) + else if (n == SIGNED32 (0x80000000) && d == -1) { LO = EXTEND32 (0x80000000); HI = EXTEND32 (0); diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index f9a9278..697d145 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -126,7 +126,7 @@ convert (SD, CPU, cia, rm, op, from, to) int bit = ((cc == 0) ? 23 : (24 + (cc)));\ FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\ } -#define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0) +#define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0) /* This should be the COC1 value at the start of the preceding instruction: */ |