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| author | Jeff Law <law@redhat.com> | 1997-05-06 19:42:17 +0000 |
|---|---|---|
| committer | Jeff Law <law@redhat.com> | 1997-05-06 19:42:17 +0000 |
| commit | 8def9220345a634cea86a9cd6599b3f9e6aca5cf (patch) | |
| tree | 05d56bc20c3d19c06c6d651f547005f6a1938364 | |
| parent | 1ec53ef5977df594329dccfa4336847782905248 (diff) | |
| download | gdb-8def9220345a634cea86a9cd6599b3f9e6aca5cf.zip gdb-8def9220345a634cea86a9cd6599b3f9e6aca5cf.tar.gz gdb-8def9220345a634cea86a9cd6599b3f9e6aca5cf.tar.bz2 | |
* mn10300_sim.h: Fix ordering of bits in the PSW.
| -rw-r--r-- | sim/mn10300/ChangeLog | 2 | ||||
| -rw-r--r-- | sim/mn10300/mn10300_sim.h | 8 |
2 files changed, 6 insertions, 4 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog index f3280cc..51efa7b 100644 --- a/sim/mn10300/ChangeLog +++ b/sim/mn10300/ChangeLog @@ -1,5 +1,7 @@ Tue May 6 13:24:36 1997 Jeffrey A Law (law@cygnus.com) + * mn10300_sim.h: Fix ordering of bits in the PSW. + * interp.c: Improve hashing routine to avoid long list traversals for common instructions. Add HASH_STAT support. Rewrite opcode dispatch code using a big switch instead of diff --git a/sim/mn10300/mn10300_sim.h b/sim/mn10300/mn10300_sim.h index 2fcb85a..40cef23 100644 --- a/sim/mn10300/mn10300_sim.h +++ b/sim/mn10300/mn10300_sim.h @@ -72,10 +72,10 @@ extern struct simops Simops[]; #define PC (State.regs[9]) #define PSW (State.regs[11]) -#define PSW_V 0x1 -#define PSW_C 0x2 -#define PSW_N 0x4 -#define PSW_Z 0x8 +#define PSW_Z 0x1 +#define PSW_N 0x2 +#define PSW_C 0x4 +#define PSW_V 0x8 #define REG_D0 0 #define REG_A0 4 |