This commit was manufactured by cvs2svn to create branch

'carlton_dictionary-branch'.

Cherrypick from master 2003-12-13 20:12:31 UTC Jim Blandy <jimb@codesourcery.com> '* gdb.base/freebpcmd.exp, gdb.base/freebpcmd.c: New test.':
    bfd/po/ro.po
    gdb/config/arm/tm-nbsd.h
    gdb/libunwind-frame.c
    gdb/libunwind-frame.h
    gdb/testsuite/gdb.arch/i386-unwind.c
    gdb/testsuite/gdb.arch/i386-unwind.exp
    gdb/testsuite/gdb.asm/empty.inc
    gdb/testsuite/gdb.asm/frv.inc
    gdb/testsuite/gdb.asm/netbsd.inc
    gdb/testsuite/gdb.base/break1.c
    gdb/testsuite/gdb.base/freebpcmd.c
    gdb/testsuite/gdb.base/freebpcmd.exp
    gdb/testsuite/gdb.cp/class2.cc
    gdb/testsuite/gdb.cp/class2.exp
    sim/m32r/cpu2.c
    sim/m32r/cpu2.h
    sim/m32r/decode2.c
    sim/m32r/decode2.h
    sim/m32r/m32r2.c
    sim/m32r/mloop2.in
    sim/m32r/model2.c
    sim/m32r/sem2-switch.c

22 files changed, 18913 insertions, 0 deletions

diff --git a/bfd/po/ro.po b/bfd/po/ro.po
new file mode 100644
index 0000000..5706e4f
--- /dev/null
+++ b/bfd/po/ro.po
@@ -0,0 +1,3026 @@
+# Mesajele în limba română pentru pachetul bfd.
+# Copyright (C) 2003 Free Software Foundation, Inc.
+# Eugen Hoanca <eugenh@urban-grafx.ro>, 2003.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: bfd 2.14rel030712\n"
+"POT-Creation-Date: 2003-07-11 13:53+0930\n"
+"PO-Revision-Date: 2003-11-25 08:39+0200\n"
+"Last-Translator: Eugen Hoanca <eugenh@urban-grafx.ro>\n"
+"Language-Team: Romanian <translation-team-ro@lists.sourceforge.net>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=ISO-8859-2\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: aout-adobe.c:204
+#, c-format
+msgid "%s: Unknown section type in a.out.adobe file: %x\n"
+msgstr "%s: Tip secțiune necunoscut în fișier adobe a.out: %x\n"
+
+#: aout-cris.c:207
+#, c-format
+msgid "%s: Invalid relocation type exported: %d"
+msgstr "%s: Tip de relocare exportat invalid: %d"
+
+#: aout-cris.c:251
+#, c-format
+msgid "%s: Invalid relocation type imported: %d"
+msgstr "%s: Tip de relocare importat invalid: %d"
+
+#: aout-cris.c:262
+#, c-format
+msgid "%s: Bad relocation record imported: %d"
+msgstr "%s: Înregistrare de relocare greșită importată: %d"
+
+#: aoutx.h:1295 aoutx.h:1716
+#, c-format
+msgid "%s: can not represent section `%s' in a.out object file format"
+msgstr "%s: nu se poate reprezenta secțiunea `%s' în format de fișier obiect a.out"
+
+#: aoutx.h:1682
+#, c-format
+msgid "%s: can not represent section for symbol `%s' in a.out object file format"
+msgstr "%s: nu se poate reprezenta secțiunea pentru simbolul `%s' în formatul de fișier obiect a.out"
+
+#: aoutx.h:1684
+msgid "*unknown*"
+msgstr "*necunoscut*"
+
+#: aoutx.h:3776
+#, c-format
+msgid "%s: relocatable link from %s to %s not supported"
+msgstr "%s: legătura relocalizabilă din %s către %s nesuportată"
+
+#: archive.c:1751
+msgid "Warning: writing archive was slow: rewriting timestamp\n"
+msgstr "Avertisment: scrierea arhivei a fost lentă: se rescrie marcajul de timp(timestamp)\n"
+
+#: archive.c:2014
+msgid "Reading archive file mod timestamp"
+msgstr "Citirea fișierului arhivă mod marcaj de timp"
+
+#: archive.c:2040
+msgid "Writing updated armap timestamp"
+msgstr "Scriere marcaj de timp armap înnoit"
+
+#: bfd.c:280
+msgid "No error"
+msgstr "Nici o eroare"
+
+#: bfd.c:281
+msgid "System call error"
+msgstr "Eroare apel sistem"
+
+#: bfd.c:282
+msgid "Invalid bfd target"
+msgstr "Țintă bfd invalidă"
+
+#: bfd.c:283
+msgid "File in wrong format"
+msgstr "Fișier în format eronat"
+
+#: bfd.c:284
+msgid "Archive object file in wrong format"
+msgstr "Fișier obiect arhivă în format eronat"
+
+#: bfd.c:285
+msgid "Invalid operation"
+msgstr "Operație invalidă"
+
+#: bfd.c:286
+msgid "Memory exhausted"
+msgstr "Memorie plină"
+
+#: bfd.c:287
+msgid "No symbols"
+msgstr "Nici un simbol"
+
+#: bfd.c:288
+msgid "Archive has no index; run ranlib to add one"
+msgstr "Arhiva nu are nici un index.; rulați ranlib pentru a adăuga unul"
+
+#: bfd.c:289
+msgid "No more archived files"
+msgstr "Nu mai există fișiere arhivate"
+
+#: bfd.c:290
+msgid "Malformed archive"
+msgstr "Arhivă malformată"
+
+#: bfd.c:291
+msgid "File format not recognized"
+msgstr "Formatul de fișier nu a fost recunoscut"
+
+#: bfd.c:292
+msgid "File format is ambiguous"
+msgstr "Formatul de fișier este ambiguu"
+
+#: bfd.c:293
+msgid "Section has no contents"
+msgstr "Secțiunea nu are conținut"
+
+#: bfd.c:294
+msgid "Nonrepresentable section on output"
+msgstr "Secțiune de output nereprezentabilă"
+
+#: bfd.c:295
+msgid "Symbol needs debug section which does not exist"
+msgstr "Simbolul necesită secțiune de debug care nu există"
+
+#: bfd.c:296
+msgid "Bad value"
+msgstr "Valoare eronată"
+
+#: bfd.c:297
+msgid "File truncated"
+msgstr "Fișier trunchiat"
+
+#: bfd.c:298
+msgid "File too big"
+msgstr "Fișier prea mare"
+
+#: bfd.c:299
+msgid "#<Invalid error code>"
+msgstr "#<Cod invalid de eroare>"
+
+#: bfd.c:687
+#, c-format
+msgid "BFD %s assertion fail %s:%d"
+msgstr "Aserțiunea BFD %s a eșuat %s:%d"
+
+#: bfd.c:703
+#, c-format
+msgid "BFD %s internal error, aborting at %s line %d in %s\n"
+msgstr "Eroare interna BFD %s, se renunță la %s linia %d în %s\n"
+
+#: bfd.c:707
+#, c-format
+msgid "BFD %s internal error, aborting at %s line %d\n"
+msgstr "Eroare internă BFD %s, se renunță la %s linia %d\n"
+
+#: bfd.c:709
+msgid "Please report this bug.\n"
+msgstr "Vă rugăm raportați acest bug.\n"
+
+#: bfdwin.c:202
+#, c-format
+msgid "not mapping: data=%lx mapped=%d\n"
+msgstr "nu se mapează: data=%lx mapat =%d\n"
+
+#: bfdwin.c:205
+msgid "not mapping: env var not set\n"
+msgstr "nu se mapează: variabila env nu este setată\n"
+
+#: binary.c:306
+#, c-format
+msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx."
+msgstr "Avertisment: Scrierea secțiunii `%s' spre offset de fișier imens (sau negativ) 0x%lx"
+
+#: coff-a29k.c:120
+msgid "Missing IHCONST"
+msgstr "IHCONST lipsă"
+
+#: coff-a29k.c:181
+msgid "Missing IHIHALF"
+msgstr "IHHALF lipsă"
+
+#: coff-a29k.c:213 coff-or32.c:236
+msgid "Unrecognized reloc"
+msgstr "Reloc necunoscut"
+
+#: coff-a29k.c:409
+msgid "missing IHCONST reloc"
+msgstr "IHCONST reloc lipsă"
+
+#: coff-a29k.c:499
+msgid "missing IHIHALF reloc"
+msgstr "IHIHALF reloc lipsă"
+
+#: coff-alpha.c:884 coff-alpha.c:921 coff-alpha.c:1992 coff-mips.c:1397
+msgid "GP relative relocation used when GP not defined"
+msgstr "Relocare relativă GP folosită când GP nu este definit"
+
+#: coff-alpha.c:1488
+msgid "using multiple gp values"
+msgstr "folosire de valori multiple gp"
+
+#: coff-arm.c:1066 elf32-arm.h:294
+#, c-format
+msgid "%s: unable to find THUMB glue '%s' for `%s'"
+msgstr "%s: nu s-a putut găsi legătura(glue) THUMB `%s' pentru `%s'"
+
+#: coff-arm.c:1096 elf32-arm.h:329
+#, c-format
+msgid "%s: unable to find ARM glue '%s' for `%s'"
+msgstr "%s: nu s-a putut găsi legătura(glue) ARM `%s' pentru `%s'"
+
+#: coff-arm.c:1394 coff-arm.c:1489 elf32-arm.h:892 elf32-arm.h:999
+#, c-format
+msgid "%s(%s): warning: interworking not enabled."
+msgstr "%s(%s): avertisment: interlucrul(interworking) nu este activat"
+
+#: coff-arm.c:1398 elf32-arm.h:1002
+#, c-format
+msgid "  first occurrence: %s: arm call to thumb"
+msgstr "  prima găsire: %s: apelare braț(arm) către deget(thumb)"
+
+#: coff-arm.c:1493 elf32-arm.h:895
+#, c-format
+msgid "  first occurrence: %s: thumb call to arm"
+msgstr "  prima găsire: %s: apelare deget(thumb) către braț(arm)"
+
+#: coff-arm.c:1496
+msgid "  consider relinking with --support-old-code enabled"
+msgstr "  luați în considerare relinkuirea cu --support-old-code activat"
+
+#: coff-arm.c:1788 coff-tic80.c:687 cofflink.c:3038
+#, c-format
+msgid "%s: bad reloc address 0x%lx in section `%s'"
+msgstr "%s: adresă eronată de relocare 0x%lx în secțiunea `%s'"
+
+#: coff-arm.c:2132
+#, c-format
+msgid "%s: illegal symbol index in reloc: %d"
+msgstr "%s: index ilegal de simbol în reloc: %d"
+
+#: coff-arm.c:2265
+#, c-format
+msgid "ERROR: %s is compiled for APCS-%d, whereas %s is compiled for APCS-%d"
+msgstr "EROARE: %s este compilat pentru APCS-%d, pe când %s e compilat pentru APCS-%d"
+
+#: coff-arm.c:2280 elf32-arm.h:2328
+#, c-format
+msgid "ERROR: %s passes floats in float registers, whereas %s passes them in integer registers"
+msgstr "EROARE: %s trimite float în regiștrii de float, pe când %s îi trimite în regiștrii de integer"
+
+#: coff-arm.c:2283 elf32-arm.h:2333
+#, c-format
+msgid "ERROR: %s passes floats in integer registers, whereas %s passes them in float registers"
+msgstr "EROARE: %s trimite integer în regiștrii de integer, pe când %s îi trimite în regiștrii de float"
+
+#: coff-arm.c:2298
+#, c-format
+msgid "ERROR: %s is compiled as position independent code, whereas target %s is absolute position"
+msgstr "EROARE: %s este compilat ca și cod independent de poziție,pe când ținta %seste poziție absolută"
+
+#: coff-arm.c:2301
+#, c-format
+msgid "ERROR: %s is compiled as absolute position code, whereas target %s is position independent"
+msgstr "EROARE: %s este compilat ca și cod poziție absolută,pe când ținta %seste independentă de poziție"
+
+#: coff-arm.c:2330 elf32-arm.h:2405
+#, c-format
+msgid "Warning: %s supports interworking, whereas %s does not"
+msgstr "Avertisment: %s suportă interlucru(interworking), pe când %s nu suportă"
+
+#: coff-arm.c:2333 elf32-arm.h:2412
+#, c-format
+msgid "Warning: %s does not support interworking, whereas %s does"
+msgstr "Avertisment: %s nu suportă interlucru(interworking), pe când %s suportă"
+
+#: coff-arm.c:2360
+#, c-format
+msgid "private flags = %x:"
+msgstr "marcaje(flags) private = %x:"
+
+#: coff-arm.c:2368 elf32-arm.h:2467
+msgid " [floats passed in float registers]"
+msgstr " [floats trecuți în regiștri de float]"
+
+#: coff-arm.c:2370
+msgid " [floats passed in integer registers]"
+msgstr " [floats trecuți în regiștrii de integer]"
+
+#: coff-arm.c:2373 elf32-arm.h:2470
+msgid " [position independent]"
+msgstr "[ independent de poziție]"
+
+#: coff-arm.c:2375
+msgid " [absolute position]"
+msgstr " [poziție absolută]"
+
+#: coff-arm.c:2379
+msgid " [interworking flag not initialised]"
+msgstr " [marcajul(flag) de interlucru(interworking) nu este inițializat]"
+
+#: coff-arm.c:2381
+msgid " [interworking supported]"
+msgstr " [interlucru(interworking) suportat]"
+
+#: coff-arm.c:2383
+msgid " [interworking not supported]"
+msgstr " [interlucru(interworking) nesuportat]"
+
+#: coff-arm.c:2431 elf32-arm.h:2150
+#, c-format
+msgid "Warning: Not setting interworking flag of %s since it has already been specified as non-interworking"
+msgstr "Avertisment: Nu se setează marcajul(flagu) de interlucru(interworking) al %s atâta timp cât a fost specificat ca non-interlucru(interworking)"
+
+#: coff-arm.c:2435 elf32-arm.h:2154
+#, c-format
+msgid "Warning: Clearing the interworking flag of %s due to outside request"
+msgstr "Avertisment: Se șterge marcajul(flag) de interlucru(interworking) al %s datorită unei cereri din afară"
+
+#: coff-h8300.c:1096
+#, c-format
+msgid "cannot handle R_MEM_INDIRECT reloc when using %s output"
+msgstr "nu am putut mainpula(handle) relocarea R_MEM_INDIRECT în folosirea ieșirii(output) %s"
+
+#: coff-i960.c:137 coff-i960.c:486
+msgid "uncertain calling convention for non-COFF symbol"
+msgstr "convenție de apelare nesigură pentru simbol non-COFF"
+
+#: coff-m68k.c:482 coff-mips.c:2394 elf32-m68k.c:2193 elf32-mips.c:1783
+msgid "unsupported reloc type"
+msgstr "tip de relocare nesuportat"
+
+#: coff-mips.c:839 elf32-mips.c:1088 elf64-mips.c:1590 elfn32-mips.c:1554
+msgid "GP relative relocation when _gp not defined"
+msgstr "Relocare relativă GP atâta timp cât _gp nu este definit"
+
+#. No other sections should appear in -membedded-pic
+#. code.
+#: coff-mips.c:2431
+msgid "reloc against unsupported section"
+msgstr "relocare pe o secțiune nesuportată"
+
+#: coff-mips.c:2439
+msgid "reloc not properly aligned"
+msgstr "relocare incorect aliniată"
+
+#: coff-rs6000.c:2790
+#, c-format
+msgid "%s: unsupported relocation type 0x%02x"
+msgstr "%s: tip de relocare nesuportat 0x%02x"
+
+#: coff-rs6000.c:2883
+#, c-format
+msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry"
+msgstr "%s: relocare TOC la 0x%x către simbolul `%s' fără nici o intrare TOC"
+
+#: coff-rs6000.c:3616 coff64-rs6000.c:2109
+#, c-format
+msgid "%s: symbol `%s' has unrecognized smclas %d"
+msgstr "%s: simbolul `%s' are un smclas necunoscut %d"
+
+#: coff-tic4x.c:170 coff-tic54x.c:288 coff-tic80.c:450
+#, c-format
+msgid "Unrecognized reloc type 0x%x"
+msgstr "Tip de relocare necunoscut 0x%x"
+
+#: coff-tic4x.c:218 coff-tic54x.c:373 coffcode.h:5045
+#, c-format
+msgid "%s: warning: illegal symbol index %ld in relocs"
+msgstr "%s: avertisment: index ilegal de simbol %ld în relocări"
+
+#: coff-w65.c:364
+#, c-format
+msgid "ignoring reloc %s\n"
+msgstr "se ignoră reloc %s\n"
+
+#: coffcode.h:1108
+#, c-format
+msgid "%s (%s): Section flag %s (0x%x) ignored"
+msgstr "%s (%s): Marcajul(flag) de secțiune %s (0x%x) ignorat"
+
+#: coffcode.h:2214
+#, c-format
+msgid "Unrecognized TI COFF target id '0x%x'"
+msgstr "Id țintă TI COFF necunoscut `0x%x'"
+
+#: coffcode.h:4437
+#, c-format
+msgid "%s: warning: illegal symbol index %ld in line numbers"
+msgstr "%s: avertisment: index ilegal de simbol %ld în numărul de linii"
+
+#: coffcode.h:4451
+#, c-format
+msgid "%s: warning: duplicate line number information for `%s'"
+msgstr "%s: avertisment: informație duplicat a numărului de linii pentru `%s'"
+
+#: coffcode.h:4805
+#, c-format
+msgid "%s: Unrecognized storage class %d for %s symbol `%s'"
+msgstr "%s: Clasă de depozitare(storage) %d necunoscută pentru %s simbolul `%s'"
+
+#: coffcode.h:4938
+#, c-format
+msgid "warning: %s: local symbol `%s' has no section"
+msgstr "avertisment: %s: simbolul local `%s' nu are secțiune"
+
+#: coffcode.h:5083
+#, c-format
+msgid "%s: illegal relocation type %d at address 0x%lx"
+msgstr "%s: tip ilegal de relocare %d la adresa 0x%lx"
+
+#: coffgen.c:1666
+#, c-format
+msgid "%s: bad string table size %lu"
+msgstr "%s: mărime tabel șiruri invalidă %lu"
+
+#: cofflink.c:538 elflink.h:1276
+#, c-format
+msgid "Warning: type of symbol `%s' changed from %d to %d in %s"
+msgstr "Avertisment: tipul de simbol `%s' schimbat de la %d la %d în %s"
+
+#: cofflink.c:2328
+#, c-format
+msgid "%s: relocs in section `%s', but it has no contents"
+msgstr "%s: relocări în secțiunea `%s', dar fără conținut"
+
+#: cofflink.c:2671 coffswap.h:890
+#, c-format
+msgid "%s: %s: reloc overflow: 0x%lx > 0xffff"
+msgstr "%s: %s: depășire(overflow) de relocări: 0x%lx > 0xffff"
+
+#: cofflink.c:2680 coffswap.h:876
+#, c-format
+msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff"
+msgstr "%s: avertisment: %s: depășire(overflow) număr de linii: 0x%lx > 0xffff"
+
+#: cpu-arm.c:196 cpu-arm.c:206
+#, c-format
+msgid "ERROR: %s is compiled for the EP9312, whereas %s is compiled for XScale"
+msgstr "EROARE: %s este compilat pentru EP9312, pe când %s e compilat pentru XScale"
+
+#: cpu-arm.c:344
+#, c-format
+msgid "warning: unable to update contents of %s section in %s"
+msgstr "avertisment: imposibil de adus la zi(update) conținutul secțiunii %s în %s"
+
+#: dwarf2.c:380
+msgid "Dwarf Error: Can't find .debug_str section."
+msgstr "Eroare Pitic(Dwarf): Nu pot găsi secțiunea debug_str"
+
+#: dwarf2.c:397
+#, c-format
+msgid "Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str size (%lu)."
+msgstr "Eroare Pitic(Dwarf): DW_FORM_strp offset (%lu) mai mare sau egală cu mărimea .debug_str (%lu)."
+
+#: dwarf2.c:541
+msgid "Dwarf Error: Can't find .debug_abbrev section."
+msgstr "Eroare Pitic(Dwarf): Nu pot găsi secțiunea debug_abbrev."
+
+#: dwarf2.c:556
+#, c-format
+msgid "Dwarf Error: Abbrev offset (%lu) greater than or equal to .debug_abbrev size (%lu)."
+msgstr "Eroare Pitic(Dwarf): Offset abbrev(%lu) mai mare sau egal cu mărimea .debug_abbrev (%lu)."
+
+#: dwarf2.c:756
+#, c-format
+msgid "Dwarf Error: Invalid or unhandled FORM value: %u."
+msgstr "Eroare Pitic(Dwarf): Valoare FORM invalidă sau nemanipulabilă: %u."
+
+#: dwarf2.c:933
+msgid "Dwarf Error: mangled line number section (bad file number)."
+msgstr "Eroare Pitic(Dwarf): secțiune număr de linii trunchiată (număr fișier eronat)"
+
+#: dwarf2.c:1032
+msgid "Dwarf Error: Can't find .debug_line section."
+msgstr "Eroare Pitic(Dwarf): Nu pot găsi secțiunea debug_line."
+
+#: dwarf2.c:1049
+#, c-format
+msgid "Dwarf Error: Line offset (%lu) greater than or equal to .debug_line size (%lu)."
+msgstr "Eroare Pitic(Dwarf): Offsetul de linie (%lu) mai mare sau egal cu mărimea .debug_line (%lu)"
+
+#: dwarf2.c:1255
+msgid "Dwarf Error: mangled line number section."
+msgstr "Eroare Pitic(Dwarf): secțiune trunchiată număr de linii"
+
+#: dwarf2.c:1470 dwarf2.c:1620
+#, c-format
+msgid "Dwarf Error: Could not find abbrev number %u."
+msgstr "Eroare Pitic(Dwarf): Nu am putut găsi numărul abbrev: %u."
+
+#: dwarf2.c:1581
+#, c-format
+msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 information."
+msgstr "Eroare Pitic(Dwarf): S-a găsit dwarf versiunea `%u', acest cititor manipulează doar informații ale versiunii 2."
+
+#: dwarf2.c:1588
+#, c-format
+msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'."
+msgstr "Eroare Pitic(Dwarf): s-a găsit adresa mărimea `%u', acest cititor nu poate manipula mărimi mai mari decât `%u'"
+
+#: dwarf2.c:1611
+#, c-format
+msgid "Dwarf Error: Bad abbrev number: %u."
+msgstr "Eroare Pitic(Dwarf): Număr invalid de abbrev: %u"
+
+#: ecoff.c:1339
+#, c-format
+msgid "Unknown basic type %d"
+msgstr "Tip de bază necunoscut %d"
+
+#: ecoff.c:1599
+#, c-format
+msgid ""
+"\n"
+"      End+1 symbol: %ld"
+msgstr ""
+"\n"
+"      Simbol Sfârșit+1: %ld"
+
+#: ecoff.c:1606 ecoff.c:1609
+#, c-format
+msgid ""
+"\n"
+"      First symbol: %ld"
+msgstr ""
+"\n"
+"      Primul simbol: %ld"
+
+#: ecoff.c:1621
+#, c-format
+msgid ""
+"\n"
+"      End+1 symbol: %-7ld   Type:  %s"
+msgstr ""
+"\n"
+"      Simbol Sfârșit+1: %-7ld   Tip:  %s"
+
+#: ecoff.c:1628
+#, c-format
+msgid ""
+"\n"
+"      Local symbol: %ld"
+msgstr ""
+"\n"
+"      Simbol local: %ld"
+
+#: ecoff.c:1636
+#, c-format
+msgid ""
+"\n"
+"      struct; End+1 symbol: %ld"
+msgstr ""
+"\n"
+"      struct; Simbol Sfârșit+1: %ld"
+
+#: ecoff.c:1641
+#, c-format
+msgid ""
+"\n"
+"      union; End+1 symbol: %ld"
+msgstr ""
+"\n"
+"      uniune; Simbol Sfârșit+1: %ld"
+
+#: ecoff.c:1646
+#, c-format
+msgid ""
+"\n"
+"      enum; End+1 symbol: %ld"
+msgstr ""
+"\n"
+"      enum; Simbol Sfârșit+1: %ld"
+
+#: ecoff.c:1652
+#, c-format
+msgid ""
+"\n"
+"      Type: %s"
+msgstr ""
+"\n"
+"      Tip: %s"
+
+#: elf-hppa.h:1458 elf-hppa.h:1491 elf-m10300.c:1628 elf64-sh64.c:1704
+#, c-format
+msgid "%s: warning: unresolvable relocation against symbol `%s' from %s section"
+msgstr "%s: avertisment: relocare nerezolvabilă pe simbolul `%s; din secțiunea `%s'"
+
+#: elf-m10200.c:442 elf-m10300.c:1695 elf32-arm.h:2088 elf32-avr.c:812
+#: elf32-cris.c:1390 elf32-d10v.c:570 elf32-fr30.c:634 elf32-frv.c:815
+#: elf32-h8300.c:528 elf32-i860.c:1028 elf32-ip2k.c:1586 elf32-iq2000.c:699
+#: elf32-m32r.c:1283 elf32-m68hc1x.c:1305 elf32-msp430.c:510
+#: elf32-openrisc.c:436 elf32-v850.c:1777 elf32-xstormy16.c:976
+#: elf64-mmix.c:1332
+msgid "internal error: out of range error"
+msgstr "eroare internă: eroare depășire de domeniu(out of range)"
+
+#: elf-m10200.c:446 elf-m10300.c:1699 elf32-arm.h:2092 elf32-avr.c:816
+#: elf32-cris.c:1394 elf32-d10v.c:574 elf32-fr30.c:638 elf32-frv.c:819
+#: elf32-h8300.c:532 elf32-i860.c:1032 elf32-iq2000.c:703 elf32-m32r.c:1287
+#: elf32-m68hc1x.c:1309 elf32-msp430.c:514 elf32-openrisc.c:440
+#: elf32-v850.c:1781 elf32-xstormy16.c:980 elf64-mmix.c:1336 elfxx-mips.c:6452
+msgid "internal error: unsupported relocation error"
+msgstr "eroare internă: eroare de relocare nesuportată"
+
+#: elf-m10200.c:450 elf-m10300.c:1703 elf32-arm.h:2096 elf32-d10v.c:578
+#: elf32-h8300.c:536 elf32-m32r.c:1291 elf32-m68hc1x.c:1313
+msgid "internal error: dangerous error"
+msgstr "eroare internă: eroare periculoasă"
+
+#: elf-m10200.c:454 elf-m10300.c:1707 elf32-arm.h:2100 elf32-avr.c:824
+#: elf32-cris.c:1402 elf32-d10v.c:582 elf32-fr30.c:646 elf32-frv.c:827
+#: elf32-h8300.c:540 elf32-i860.c:1040 elf32-ip2k.c:1601 elf32-iq2000.c:711
+#: elf32-m32r.c:1295 elf32-m68hc1x.c:1317 elf32-msp430.c:522
+#: elf32-openrisc.c:448 elf32-v850.c:1801 elf32-xstormy16.c:988
+#: elf64-mmix.c:1344
+msgid "internal error: unknown error"
+msgstr "eroare internă: eroare necunoscută"
+
+#: elf.c:372
+#, c-format
+msgid "%s: invalid string offset %u >= %lu for section `%s'"
+msgstr "%s: offset de șir invalid %u >= %lu pentru secțiunea `%s'"
+
+#: elf.c:624
+#, c-format
+msgid "%s: invalid SHT_GROUP entry"
+msgstr "%s: intrare SHT_GROUP invalidă"
+
+#: elf.c:695
+#, c-format
+msgid "%s: no group info for section %s"
+msgstr "%s nu există informații de grup pentru secțiunea %s"
+
+#: elf.c:1055
+msgid ""
+"\n"
+"Program Header:\n"
+msgstr ""
+"\n"
+"Header Program:\n"
+
+#: elf.c:1106
+msgid ""
+"\n"
+"Dynamic Section:\n"
+msgstr ""
+"\n"
+"Secțiune Dinamică:\n"
+
+#: elf.c:1235
+msgid ""
+"\n"
+"Version definitions:\n"
+msgstr ""
+"\n"
+"Definiții de versiune:\n"
+
+#: elf.c:1258
+msgid ""
+"\n"
+"Version References:\n"
+msgstr ""
+"\n"
+"Referințe Versiune:\n"
+
+#: elf.c:1263
+#, c-format
+msgid "  required from %s:\n"
+msgstr "  cerute de %s:\n"
+
+#: elf.c:1944
+#, c-format
+msgid "%s: invalid link %lu for reloc section %s (index %u)"
+msgstr "%s: link invalid %lu pentru secțiunea de relocare %s (index %u)"
+
+#: elf.c:3686
+#, c-format
+msgid "%s: Not enough room for program headers (allocated %u, need %u)"
+msgstr "%s: Memorie insuficientă pentru headerele programului (alocată %u, necesară %u)"
+
+#: elf.c:3791
+#, c-format
+msgid "%s: Not enough room for program headers, try linking with -N"
+msgstr "%s: Memorie insuficientă pentru headerele programului, încercați linkuirea cu -N"
+
+#: elf.c:3922
+#, c-format
+msgid "Error: First section in segment (%s) starts at 0x%x whereas the segment starts at 0x%x"
+msgstr "Eroare: prima secțiune în segment (%s) începe la 0x%x pe când segmentul începe la 0x%x"
+
+#: elf.c:4242
+#, c-format
+msgid "%s: warning: allocated section `%s' not in segment"
+msgstr "%s: avertisment: secțiunea alocată `%s' nu este în segment"
+
+#: elf.c:4566
+#, c-format
+msgid "%s: symbol `%s' required but not present"
+msgstr "%s: simbolul `%s' necesar, dar nu este prezent"
+
+#: elf.c:4854
+#, c-format
+msgid "%s: warning: Empty loadable segment detected, is this intentional ?\n"
+msgstr "%s: avertisment: S-a detectat segment încărcabil vid, este intenționat ?\n"
+
+#: elf.c:5485
+#, c-format
+msgid "Unable to find equivalent output section for symbol '%s' from section '%s'"
+msgstr "Nnu am putut găsi secțiunea de output echivalentă pentru simbolul '%s' din secțiunea '%s'"
+
+#: elf.c:6298
+#, c-format
+msgid "%s: unsupported relocation type %s"
+msgstr "%s: tip de relocare nesuportat: %s"
+
+#: elf32-arm.h:1228
+#, c-format
+msgid "%s: Warning: Arm BLX instruction targets Arm function '%s'."
+msgstr "%s: Avertisment: BLX Arm are ca țintă funcția Arm `%s'."
+
+#: elf32-arm.h:1424
+#, c-format
+msgid "%s: Warning: Thumb BLX instruction targets thumb function '%s'."
+msgstr "%s: Avertisment: BLX Thumb are ca țintă funcția thumb `%s'."
+
+#: elf32-arm.h:1918 elf32-sh.c:4706 elf64-sh64.c:1613
+#, c-format
+msgid "%s(%s+0x%lx): %s relocation against SEC_MERGE section"
+msgstr "%s(%s+0x%lx): %s relocare pe secțiunea SEC_MERGE"
+
+#: elf32-arm.h:2012
+#, c-format
+msgid "%s: warning: unresolvable relocation %d against symbol `%s' from %s section"
+msgstr "%s: avertisment: relocare nerezolvabilă %d pe simbolul `%s' din secțiunea %s"
+
+#: elf32-arm.h:2202
+#, c-format
+msgid "Warning: Clearing the interworking flag of %s because non-interworking code in %s has been linked with it"
+msgstr "Avertisment: Se șterge marcajul(flag) de interlucru(interworking) al %s deoarece împreună cu el a fost linkuit cod non-interlucru în %s"
+
+#: elf32-arm.h:2302
+#, c-format
+msgid "ERROR: %s is compiled for EABI version %d, whereas %s is compiled for version %d"
+msgstr "EROARE: %s este compilat pentru EABI versiunea %d, pe când %s este compilat pentru versiunea %d"
+
+#: elf32-arm.h:2316
+#, c-format
+msgid "ERROR: %s is compiled for APCS-%d, whereas target %s uses APCS-%d"
+msgstr "EROARE: %s este compilat pentru APCS-%d, pe când ținta %s folosește APCS-%d"
+
+#: elf32-arm.h:2344
+#, c-format
+msgid "ERROR: %s uses VFP instructions, whereas %s does not"
+msgstr "EROARE: %s folosește instrucțiuni VFP, pe când %s nu le folosește"
+
+#: elf32-arm.h:2349
+#, c-format
+msgid "ERROR: %s uses FPA instructions, whereas %s does not"
+msgstr "EROARE: %s folosește instrucțiuni FPA, pe când %s nu le folosește"
+
+#: elf32-arm.h:2360 elf32-arm.h:2365
+#, c-format
+msgid "ERROR: %s uses Maverick instructions, whereas %s does not"
+msgstr "EROARE: %s folosește instrucțiuni Maverick, pe când %s nu le folosește"
+
+#: elf32-arm.h:2385
+#, c-format
+msgid "ERROR: %s uses software FP, whereas %s uses hardware FP"
+msgstr "EROARE: %s folosește FP software, pe când %s folosește FP hardware"
+
+#: elf32-arm.h:2390
+#, c-format
+msgid "ERROR: %s uses hardware FP, whereas %s uses software FP"
+msgstr "EROARE: %s folosește FP hardware, pe când %s folosește FP software"
+
+#. Ignore init flag - it may not be set, despite the flags field
+#. containing valid data.
+#: elf32-arm.h:2443 elf32-cris.c:2975 elf32-m68hc1x.c:1459 elf32-m68k.c:397
+#: elf32-vax.c:546 elfxx-mips.c:9238
+#, c-format
+msgid "private flags = %lx:"
+msgstr "marcaje(flags) private = %lx:"
+
+#: elf32-arm.h:2452
+msgid " [interworking enabled]"
+msgstr " [interlucru(interworking) activat]"
+
+#: elf32-arm.h:2460
+msgid " [VFP float format]"
+msgstr " [format float VFP]"
+
+#: elf32-arm.h:2462
+msgid " [Maverick float format]"
+msgstr " [format float Maverick]"
+
+#: elf32-arm.h:2464
+msgid " [FPA float format]"
+msgstr " [format float FPA]"
+
+#: elf32-arm.h:2473
+msgid " [new ABI]"
+msgstr " [ABI nou]"
+
+#: elf32-arm.h:2476
+msgid " [old ABI]"
+msgstr " [ABI vechi]"
+
+#: elf32-arm.h:2479
+msgid " [software FP]"
+msgstr " [FP software]"
+
+#: elf32-arm.h:2488
+msgid " [Version1 EABI]"
+msgstr " [EABI Versiunea1]"
+
+#: elf32-arm.h:2491 elf32-arm.h:2502
+msgid " [sorted symbol table]"
+msgstr " [tabelă sortată de simboluri]"
+
+#: elf32-arm.h:2493 elf32-arm.h:2504
+msgid " [unsorted symbol table]"
+msgstr " [tabelă de simboluri nesortată]"
+
+#: elf32-arm.h:2499
+msgid " [Version2 EABI]"
+msgstr " [EABI Versiunea2]"
+
+#: elf32-arm.h:2507
+msgid " [dynamic symbols use segment index]"
+msgstr " [simbolurile dinamice folosesc index de segment]"
+
+#: elf32-arm.h:2510
+msgid " [mapping symbols precede others]"
+msgstr " [simbolurile de mapare le precedează pe celelalte]"
+
+#: elf32-arm.h:2517
+msgid " <EABI version unrecognised>"
+msgstr " <versiune necunoscută EABI>"
+
+#: elf32-arm.h:2524
+msgid " [relocatable executable]"
+msgstr " [executabil relocabil]"
+
+#: elf32-arm.h:2527
+msgid " [has entry point]"
+msgstr " [are punct de intrare]"
+
+#: elf32-arm.h:2532
+msgid "<Unrecognised flag bits set>"
+msgstr "<setare biți de marcaj(flag) necunoscută>"
+
+#: elf32-avr.c:820 elf32-cris.c:1398 elf32-fr30.c:642 elf32-frv.c:823
+#: elf32-i860.c:1036 elf32-ip2k.c:1597 elf32-iq2000.c:707 elf32-msp430.c:518
+#: elf32-openrisc.c:444 elf32-v850.c:1785 elf32-xstormy16.c:984
+#: elf64-mmix.c:1340
+msgid "internal error: dangerous relocation"
+msgstr "eroare internă: relocare periculoasă"
+
+#: elf32-cris.c:931
+#, c-format
+msgid "%s: unresolvable relocation %s against symbol `%s' from %s section"
+msgstr "%s: relocare nerezolvabilă %s pe simbolul `%s' din secțiunea `%s'"
+
+#: elf32-cris.c:993
+#, c-format
+msgid "%s: No PLT nor GOT for relocation %s against symbol `%s' from %s section"
+msgstr "%s:Nu există nici PLT nici GOR pentru relocarea %s pe simbolul `%s' din secțiunea %s"
+
+#: elf32-cris.c:996 elf32-cris.c:1122
+msgid "[whose name is lost]"
+msgstr "[al cărui nume s-a pierdut]"
+
+#: elf32-cris.c:1111
+#, c-format
+msgid "%s: relocation %s with non-zero addend %d against local symbol from %s section"
+msgstr "%s: relocarea %s cu adăugarea diferită de zero %d pe simbolul local din secțiunea %s"
+
+#: elf32-cris.c:1118
+#, c-format
+msgid "%s: relocation %s with non-zero addend %d against symbol `%s' from %s section"
+msgstr "%s: relocarea %s cu adăugare non-zero %d pe simbolul `%s' din secțiunea %s"
+
+#: elf32-cris.c:1143
+#, c-format
+msgid "%s: relocation %s is not allowed for global symbol: `%s' from %s section"
+msgstr "%s: relocarea %s nu este permisă pentru simbolul global `%s' din secțiunea %s"
+
+#: elf32-cris.c:1158
+#, c-format
+msgid "%s: relocation %s in section %s with no GOT created"
+msgstr "%s: relocarea %s din secțiunea %s fără GOT creat"
+
+#: elf32-cris.c:1277
+#, c-format
+msgid "%s: Internal inconsistency; no relocation section %s"
+msgstr "%s: Inconsistență internă, nu există secțiunea de relocare %s"
+
+#: elf32-cris.c:2500
+#, c-format
+msgid ""
+"%s, section %s:\n"
+"  relocation %s should not be used in a shared object; recompile with -fPIC"
+msgstr ""
+"%s, secțiunea %s:\n"
+"  relocarea %s n-ar trebui folosită într-un shared object; recompilați cu -fPIC"
+
+#: elf32-cris.c:2978
+msgid " [symbols have a _ prefix]"
+msgstr " [simbolurile au un _prefix]"
+
+#: elf32-cris.c:3017
+#, c-format
+msgid "%s: uses _-prefixed symbols, but writing file with non-prefixed symbols"
+msgstr "%s: se folosesc simbolurile _-prefixate, dar se scrie fișierul cu simboluri neprefixate"
+
+#: elf32-cris.c:3018
+#, c-format
+msgid "%s: uses non-prefixed symbols, but writing file with _-prefixed symbols"
+msgstr "%s: se folosesc simboluri neprefixate, dar se scrie fișierul cu simboluri _-prefixate"
+
+#: elf32-frv.c:1223
+#, c-format
+msgid "%s: compiled with %s and linked with modules that use non-pic relocations"
+msgstr "%s: compilat cu %s și linkuit cu module care folosesc relocații non-pic"
+
+#: elf32-frv.c:1273 elf32-iq2000.c:895
+#, c-format
+msgid "%s: compiled with %s and linked with modules compiled with %s"
+msgstr "%s: compilat cu %s și linkuit cu module compilate cu %s"
+
+#: elf32-frv.c:1285
+#, c-format
+msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)"
+msgstr "%s: folosește câmpuri marcaje e_flags (0x%lx) diferite de modulele anterioare (0x%lx)"
+
+#: elf32-frv.c:1321 elf32-iq2000.c:933
+#, c-format
+msgid "private flags = 0x%lx:"
+msgstr "marcaje(flags) private = 0x%lx"
+
+#: elf32-gen.c:83 elf64-gen.c:82
+#, c-format
+msgid "%s: Relocations in generic ELF (EM: %d)"
+msgstr "%s: Relocări în ELF generic (EM: %d)"
+
+#: elf32-hppa.c:672 elf32-m68hc1x.c:176 elf64-ppc.c:3118
+#, c-format
+msgid "%s: cannot create stub entry %s"
+msgstr "%s: nu se poate crea intrarea trunchiată %s"
+
+#: elf32-hppa.c:957 elf32-hppa.c:3538
+#, c-format
+msgid "%s(%s+0x%lx): cannot reach %s, recompile with -ffunction-sections"
+msgstr "%s(%s+0x%lx): nu se poate găsi %s, recompilați cu -ffunction-sections"
+
+#: elf32-hppa.c:1340 elf64-x86-64.c:672 elf64-x86-64.c:797
+#, c-format
+msgid "%s: relocation %s can not be used when making a shared object; recompile with -fPIC"
+msgstr "%s: relocarea %s nu poate fi utilizată când se face un shared object, recompilațicu -fPIC"
+
+#: elf32-hppa.c:1360
+#, c-format
+msgid "%s: relocation %s should not be used when making a shared object; recompile with -fPIC"
+msgstr "%s: relocarea %s nu ar trebui utilizată când se face un shared object, recompilațicu -fPIC"
+
+#: elf32-hppa.c:1553
+#, c-format
+msgid "Could not find relocation section for %s"
+msgstr "Nu se poate găsi secțiunea de relocare pentru %s"
+
+#: elf32-hppa.c:2828
+#, c-format
+msgid "%s: duplicate export stub %s"
+msgstr "%s: exportare de ciot(stub) duplicată %s"
+
+#: elf32-hppa.c:3416
+#, c-format
+msgid "%s(%s+0x%lx): fixing %s"
+msgstr "%s(%s+0x%lx): se fixează %s"
+
+#: elf32-hppa.c:4039
+#, c-format
+msgid "%s(%s+0x%lx): cannot handle %s for %s"
+msgstr "%s(%s+0x%lx): nu pot manipula %s pentru %s"
+
+#: elf32-hppa.c:4357
+msgid ".got section not immediately after .plt section"
+msgstr "secțiunea .got nu urmează imediat după secțiunea .plt"
+
+#: elf32-i386.c:326
+#, c-format
+msgid "%s: invalid relocation type %d"
+msgstr "%s: tip de relocare invalid %d"
+
+#: elf32-i386.c:841 elf32-s390.c:990 elf32-sparc.c:887 elf32-xtensa.c:637
+#: elf64-s390.c:943 elf64-x86-64.c:650
+#, c-format
+msgid "%s: bad symbol index: %d"
+msgstr "%s:index de simboluri invalid: %d"
+
+#: elf32-i386.c:949 elf32-s390.c:1168 elf32-sh.c:6426 elf32-sparc.c:1011
+#: elf64-s390.c:1129
+#, c-format
+msgid "%s: `%s' accessed both as normal and thread local symbol"
+msgstr "%s: `%s' accesate și ca simboluri locale normale și ca simboluri locale pe fire (thread)"
+
+#: elf32-i386.c:1064 elf32-s390.c:1279 elf64-ppc.c:3929 elf64-s390.c:1243
+#: elf64-x86-64.c:886
+#, c-format
+msgid "%s: bad relocation section name `%s'"
+msgstr "%s: nume secțiune relocare invalid `%s'"
+
+#: elf32-i386.c:2908 elf32-m68k.c:1757 elf32-s390.c:3022 elf32-sparc.c:2879
+#: elf32-xtensa.c:2193 elf64-s390.c:3018 elf64-sparc.c:2664
+#: elf64-x86-64.c:2452
+#, c-format
+msgid "%s(%s+0x%lx): unresolvable relocation against symbol `%s'"
+msgstr "%s(%s+0x%lx): relocare nerezolvabilă pe simbolul `%s'"
+
+#: elf32-i386.c:2947 elf32-m68k.c:1796 elf32-s390.c:3072 elf64-s390.c:3068
+#: elf64-x86-64.c:2490
+#, c-format
+msgid "%s(%s+0x%lx): reloc against `%s': error %d"
+msgstr "%s(%s+0x%lx): relocare pe `%s': eroare %d"
+
+#: elf32-ip2k.c:565 elf32-ip2k.c:571 elf32-ip2k.c:734 elf32-ip2k.c:740
+msgid "ip2k relaxer: switch table without complete matching relocation information."
+msgstr "ip2k relaxer: schimbare de tabel fără potrivirea completă a informației de relocare."
+
+#: elf32-ip2k.c:588 elf32-ip2k.c:767
+msgid "ip2k relaxer: switch table header corrupt."
+msgstr "ip2k relaxer: headerul tablelului de schimbare este corupt."
+
+#: elf32-ip2k.c:1395
+#, c-format
+msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)."
+msgstr "ip2k linker: lipsește instrucțiunea de pagină la 0x%08lx (dest = 0x%08lx)."
+
+#: elf32-ip2k.c:1409
+#, c-format
+msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)."
+msgstr "ip2k linker: instrucțiune redundantă de pagină la 0x%08lx (dest = 0x%08lx)."
+
+#. Only if it's not an unresolved symbol.
+#: elf32-ip2k.c:1593
+msgid "unsupported relocation between data/insn address spaces"
+msgstr "relocare nesuportată între dată/spațiu adresă insn"
+
+#: elf32-iq2000.c:907 elf32-m68hc1x.c:1431 elf32-ppc.c:2175 elf64-sparc.c:3072
+#: elfxx-mips.c:9195
+#, c-format
+msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"
+msgstr "%s: folosește câmpuri de marcaje e_flags (0x%lx) diferite de modulele anterioare (0x%lx)"
+
+#: elf32-m32r.c:930
+msgid "SDA relocation when _SDA_BASE_ not defined"
+msgstr "Relocare SDA când _SDA_BASE_ nu este definit"
+
+#: elf32-m32r.c:1018 elf64-alpha.c:4279 elf64-alpha.c:4407 elf32-ia64.c:3958
+#: elf64-ia64.c:3958
+#, c-format
+msgid "%s: unknown relocation type %d"
+msgstr "%s: tip necunoscut de relocare %d"
+
+#: elf32-m32r.c:1226
+#, c-format
+msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)"
+msgstr "%s: Ținta (%s) unei relocări %s este în secțiunea nepotrivită (%s)"
+
+#: elf32-m32r.c:1952
+#, c-format
+msgid "%s: Instruction set mismatch with previous modules"
+msgstr "%s: Setul de instrucțiuni nu se potrivește cu modulele anterioare"
+
+#: elf32-m32r.c:1975
+#, c-format
+msgid "private flags = %lx"
+msgstr "marcaje (flags) private = %lx"
+
+#: elf32-m32r.c:1980
+msgid ": m32r instructions"
+msgstr ": instrucțiuni m32r"
+
+#: elf32-m32r.c:1981
+msgid ": m32rx instructions"
+msgstr ": instrucțiuni m32rx"
+
+#: elf32-m68hc1x.c:1217
+#, c-format
+msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution"
+msgstr "Referința la simbolul depărtat `%s' folosind o relocare invalidă poate duce la execuție incorectă"
+
+#: elf32-m68hc1x.c:1240
+#, c-format
+msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)"
+msgstr "adresa banked [%lx:%04lx] (%lx) nu este în același bank precum adresa banked curentă [%lx:%04lx] (%lx)"
+
+#: elf32-m68hc1x.c:1259
+#, c-format
+msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx"
+msgstr "referință la adresa banked [%lx:%04lx] în spațiul normal de adresă la %04lx"
+
+#: elf32-m68hc1x.c:1396
+#, c-format
+msgid "%s: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers"
+msgstr "%s: linkuire a fișierelor compilate pentru întregi(integers)  pe 16-biți (-mshort) și a celorlalte pentru întregi(integers) pe 32-biți"
+
+#: elf32-m68hc1x.c:1404
+#, c-format
+msgid "%s: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double"
+msgstr "%s: linkuire a fișierelor compilate pentru double pe 32-biți (-fshort-double) și a celorlalte pentru double pe 64-biți"
+
+#: elf32-m68hc1x.c:1414
+#, c-format
+msgid "%s: linking files compiled for HCS12 with others compiled for HC12"
+msgstr "%s:linkuire a fișierelor compilate pentru HCS12 cu celelalte compilate pentru HC12"
+
+#: elf32-m68hc1x.c:1462
+msgid "[abi=32-bit int, "
+msgstr "[abi=32-bit int, "
+
+#: elf32-m68hc1x.c:1464
+msgid "[abi=16-bit int, "
+msgstr "[abi=16-bit int, "
+
+#: elf32-m68hc1x.c:1467
+msgid "64-bit double, "
+msgstr "double pe 64-biți, "
+
+#: elf32-m68hc1x.c:1469
+msgid "32-bit double, "
+msgstr "double pe 32-biți, "
+
+#: elf32-m68hc1x.c:1472
+msgid "cpu=HC11]"
+msgstr "cpu=HC11]"
+
+#: elf32-m68hc1x.c:1474
+msgid "cpu=HCS12]"
+msgstr "cpu=HCS12]"
+
+#: elf32-m68hc1x.c:1476
+msgid "cpu=HC12]"
+msgstr "cpu=HC12]"
+
+#: elf32-m68hc1x.c:1479
+msgid " [memory=bank-model]"
+msgstr " [memorie=mod-bank]"
+
+#: elf32-m68hc1x.c:1481
+msgid " [memory=flat]"
+msgstr " [memorie=întinsă(flat)]"
+
+#: elf32-m68k.c:400
+msgid " [cpu32]"
+msgstr " [cpu32]"
+
+#: elf32-m68k.c:403
+msgid " [m68000]"
+msgstr " [m68000]"
+
+#: elf32-mcore.c:353 elf32-mcore.c:456
+#, c-format
+msgid "%s: Relocation %s (%d) is not currently supported.\n"
+msgstr "%s: Relocarea %s (%d) nu este încă suportată.\n"
+
+#: elf32-mcore.c:441
+#, c-format
+msgid "%s: Unknown relocation type %d\n"
+msgstr "%s: Tip necunoscut de relocare %d\n"
+
+#: elf32-mips.c:1170 elf64-mips.c:1717 elfn32-mips.c:1664
+msgid "32bits gp relative relocation occurs for an external symbol"
+msgstr "relocarea relativă gp 32bits are loc pe un simbol extern"
+
+#: elf32-mips.c:1314 elf64-mips.c:1830 elfn32-mips.c:1783
+#, c-format
+msgid "Linking mips16 objects into %s format is not supported"
+msgstr "Linkuirea obiectelor mips16 în formatul %s nu este suportată"
+
+#: elf32-ppc.c:2056
+#, c-format
+msgid "generic linker can't handle %s"
+msgstr "linkerul generic nu poate manipula(handle) %s"
+
+#: elf32-ppc.c:2138
+#, c-format
+msgid "%s: compiled with -mrelocatable and linked with modules compiled normally"
+msgstr "%s: compilat cu -mrelocatable și linkuit cu module compilate normal"
+
+#: elf32-ppc.c:2147
+#, c-format
+msgid "%s: compiled normally and linked with modules compiled with -mrelocatable"
+msgstr "%s: compilat normal și linkuite cu module compilate cu -mrelocatable"
+
+#: elf32-ppc.c:3413
+#, c-format
+msgid "%s: relocation %s cannot be used when making a shared object"
+msgstr "%s: relocarea %s nu poate fi folosită când se crează un shared object"
+
+#. It does not make sense to have a procedure linkage
+#. table entry for a local symbol.
+#: elf32-ppc.c:3619
+#, c-format
+msgid "%s(%s+0x%lx): %s reloc against local symbol"
+msgstr "relocare %s(%s+0x%lx): %s pe simbol local"
+
+#: elf32-ppc.c:4862 elf64-ppc.c:7789
+#, c-format
+msgid "%s: unknown relocation type %d for symbol %s"
+msgstr "%s: tip de relocare %d necunoscut pentru simbolul %s"
+
+#: elf32-ppc.c:5113
+#, c-format
+msgid "%s(%s+0x%lx): non-zero addend on %s reloc against `%s'"
+msgstr "%s(%s+0x%lx): adăugare non-zero în relocarea %s pentru `%s'"
+
+#: elf32-ppc.c:5399 elf32-ppc.c:5425 elf32-ppc.c:5484
+#, c-format
+msgid "%s: the target (%s) of a %s relocation is in the wrong output section (%s)"
+msgstr "%s: ținta (%s) unei relocări %s este într-o secțiune invalidă de output (%s)"
+
+#: elf32-ppc.c:5539
+#, c-format
+msgid "%s: relocation %s is not yet supported for symbol %s."
+msgstr "%s: relocarea %s nu este încă suportată pentru simbolul %s."
+
+#: elf32-ppc.c:5594 elf64-ppc.c:8461
+#, c-format
+msgid "%s(%s+0x%lx): unresolvable %s relocation against symbol `%s'"
+msgstr "%s(%s+0x%lx): relocare nerezolvabilă %s pe simbolul `%s'"
+
+#: elf32-ppc.c:5644 elf64-ppc.c:8507
+#, c-format
+msgid "%s(%s+0x%lx): %s reloc against `%s': error %d"
+msgstr "%s(%s+0x%lx):relocarea %s pe `%s': eroare %d"
+
+#: elf32-ppc.c:5888
+#, c-format
+msgid "corrupt or empty %s section in %s"
+msgstr "secțiune %s coruptă sau vidă în %s"
+
+#: elf32-ppc.c:5895
+#, c-format
+msgid "unable to read in %s section from %s"
+msgstr "nu se poate citi în secțiunea %s din %s"
+
+#: elf32-ppc.c:5901
+#, c-format
+msgid "corrupt %s section in %s"
+msgstr "secțiune coruptă %s în %s"
+
+#: elf32-ppc.c:5944
+#, c-format
+msgid "warning: unable to set size of %s section in %s"
+msgstr "avertisment: nu se poate seta mărimea secțiunii %s în %s"
+
+#: elf32-ppc.c:5994
+msgid "failed to allocate space for new APUinfo section."
+msgstr "nu s-a putut aloca spațiu pentru secțiunea nouă APUinfo."
+
+#: elf32-ppc.c:6013
+msgid "failed to compute new APUinfo section."
+msgstr "nu s-a putut calcula(compute) secțiunea nouă APUinfo."
+
+#: elf32-ppc.c:6016
+msgid "failed to install new APUinfo section."
+msgstr "nu s-a putut instala secțiunea APUinfo nouă."
+
+#: elf32-s390.c:2256 elf64-s390.c:2226
+#, c-format
+msgid "%s(%s+0x%lx): invalid instruction for TLS relocation %s"
+msgstr "%s(%s+0x%lx): instrucțiune invalidă pentur relocarea TLS %s"
+
+#: elf32-sh.c:2103
+#, c-format
+msgid "%s: 0x%lx: warning: bad R_SH_USES offset"
+msgstr "%s: 0x%lx: avertisment: offset R_SH_USES invalid"
+
+#: elf32-sh.c:2115
+#, c-format
+msgid "%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x"
+msgstr "%s: 0x%lx: avertisment: R_SH_USES trimite către insn necunoscut 0x%x"
+
+#: elf32-sh.c:2132
+#, c-format
+msgid "%s: 0x%lx: warning: bad R_SH_USES load offset"
+msgstr "%s: 0x%lx: avertisment:offset de încărcare R_SH_USES invalid"
+
+#: elf32-sh.c:2147
+#, c-format
+msgid "%s: 0x%lx: warning: could not find expected reloc"
+msgstr "%s: 0x%lx: avertismetn: nu s-a putut găsi relocarea așteptată"
+
+#: elf32-sh.c:2175
+#, c-format
+msgid "%s: 0x%lx: warning: symbol in unexpected section"
+msgstr "%s: 0x%lx: avertisment: simbol în secțiune neașteptată"
+
+#: elf32-sh.c:2300
+#, c-format
+msgid "%s: 0x%lx: warning: could not find expected COUNT reloc"
+msgstr "%s: 0x%lx: avertisment: nu s-a putut găsi relocarea COUNT așteptată"
+
+#: elf32-sh.c:2309
+#, c-format
+msgid "%s: 0x%lx: warning: bad count"
+msgstr "%s: 0x%lx: avertisment: numărătoare(count) invalidă"
+
+#: elf32-sh.c:2712 elf32-sh.c:3088
+#, c-format
+msgid "%s: 0x%lx: fatal: reloc overflow while relaxing"
+msgstr "%s: 0x%lx: fatal: relocare depășită(overflow) în timpul relaxării"
+
+#: elf32-sh.c:4654 elf64-sh64.c:1585
+msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled"
+msgstr "STO_SH5_ISA32 neașteptat pe simbol local ce nu poate fi manipulat"
+
+#: elf32-sh.c:4809
+#, c-format
+msgid "%s: unresolvable relocation against symbol `%s' from %s section"
+msgstr "%s: relocare nerezolvabilă pe simbolul '%s' din secțiunea `%s'"
+
+#: elf32-sh.c:4881
+#, c-format
+msgid "%s: 0x%lx: fatal: unaligned branch target for relax-support relocation"
+msgstr "%s: 0x%lx: fatal: ramură țintă nealiniată pentru relocare cu suport de relaxare"
+
+#: elf32-sh.c:6627 elf64-alpha.c:4848
+#, c-format
+msgid "%s: TLS local exec code cannot be linked into shared objects"
+msgstr "%s: codul local executabil TLS nu poate fi linkuit în shared objects"
+
+#: elf32-sh64.c:221 elf64-sh64.c:2407
+#, c-format
+msgid "%s: compiled as 32-bit object and %s is 64-bit"
+msgstr "%s: compilat ca obiect pe 32-biți și %s este pe 64-biți"
+
+#: elf32-sh64.c:224 elf64-sh64.c:2410
+#, c-format
+msgid "%s: compiled as 64-bit object and %s is 32-bit"
+msgstr "%s: compilat ca obiect pe 64-biți și %s este pe 32-biți"
+
+#: elf32-sh64.c:226 elf64-sh64.c:2412
+#, c-format
+msgid "%s: object size does not match that of target %s"
+msgstr "%s: mărimea obiectului nu se potrivește cu cea a țintei %s"
+
+#: elf32-sh64.c:461 elf64-sh64.c:2990
+#, c-format
+msgid "%s: encountered datalabel symbol in input"
+msgstr "%s: s-a întâlnit un simbol etichetădate(datalabel) în intrare(input)"
+
+#: elf32-sh64.c:544
+msgid "PTB mismatch: a SHmedia address (bit 0 == 1)"
+msgstr "nepotrivire PTB: o adresă SHmedia (bit 0 == 1)"
+
+#: elf32-sh64.c:547
+msgid "PTA mismatch: a SHcompact address (bit 0 == 0)"
+msgstr "nepotrivire PTA: o adresă SHcompact (bit 0 == 0)"
+
+#: elf32-sh64.c:565
+#, c-format
+msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16"
+msgstr "%s: eroare GASr:  PTB insn neașteptat cu R_SH_PT_16"
+
+#: elf32-sh64.c:614 elf64-sh64.c:1748
+#, c-format
+msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n"
+msgstr "%s: eroare: tip de reloare nealiniat %d la %08x relocarea %08x\n"
+
+#: elf32-sh64.c:698
+#, c-format
+msgid "%s: could not write out added .cranges entries"
+msgstr "%s: nu am putut scrie intrările .cranges adăugate"
+
+#: elf32-sh64.c:760
+#, c-format
+msgid "%s: could not write out sorted .cranges entries"
+msgstr "%s: nu am putut scrie intrările .cranges sortate"
+
+#: elf32-sparc.c:2521 elf64-sparc.c:2314
+#, c-format
+msgid "%s: probably compiled without -fPIC?"
+msgstr "%s: probabil compilat fără -fPIC?"
+
+#: elf32-sparc.c:3348
+#, c-format
+msgid "%s: compiled for a 64 bit system and target is 32 bit"
+msgstr "%s: compilat pentru un sistem 64 biți și ținta fiind pe 32 biți"
+
+#: elf32-sparc.c:3362
+#, c-format
+msgid "%s: linking little endian files with big endian files"
+msgstr "%s: linkuire fișiere little endian files cu fișiere big endian"
+
+#: elf32-v850.c:753
+#, c-format
+msgid "Variable `%s' cannot occupy in multiple small data regions"
+msgstr "Variabila `%s' nu poate ocupa regiuni multiple de date mici"
+
+#: elf32-v850.c:756
+#, c-format
+msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions"
+msgstr "Variabila `%s' nu poate să fie în una din regiunile mici, zero sau micuțe"
+
+#: elf32-v850.c:759
+#, c-format
+msgid "Variable `%s' cannot be in both small and zero data regions simultaneously"
+msgstr "Variabila `%s' nu poate fi simultan și în regiuni de date mici și de date zero"
+
+#: elf32-v850.c:762
+#, c-format
+msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously"
+msgstr "Variabila `%s' nu poate fi simultan și în regiuni de date mici și de date micuțe"
+
+#: elf32-v850.c:765
+#, c-format
+msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously"
+msgstr "Variabila `%s' nu poate fi simultan și în regiuni de date zero și de date micuțe"
+
+#: elf32-v850.c:1144
+msgid "FAILED to find previous HI16 reloc\n"
+msgstr "EȘUARE în găsirea relocării anterioare HI16\n"
+
+#: elf32-v850.c:1789
+msgid "could not locate special linker symbol __gp"
+msgstr "nu am putut localiza simbolul special de linker __gp"
+
+#: elf32-v850.c:1793
+msgid "could not locate special linker symbol __ep"
+msgstr "nu am putut localiza simbolul special de linker __ep"
+
+#: elf32-v850.c:1797
+msgid "could not locate special linker symbol __ctbp"
+msgstr "nu am putut localiza simbolul special de linker __ctbp"
+
+#: elf32-v850.c:1963
+#, c-format
+msgid "%s: Architecture mismatch with previous modules"
+msgstr "%s: Arhitectura nu se potrivește cu modulele anterioare"
+
+#: elf32-v850.c:1983
+#, c-format
+msgid "private flags = %lx: "
+msgstr "marcaje(flags) private=- %lx: "
+
+#: elf32-v850.c:1988
+msgid "v850 architecture"
+msgstr "arhitectură v850"
+
+#: elf32-v850.c:1989
+msgid "v850e architecture"
+msgstr "arhitectură v850e"
+
+#: elf32-vax.c:549
+msgid " [nonpic]"
+msgstr " [nonpic]"
+
+#: elf32-vax.c:552
+msgid " [d-float]"
+msgstr " [d-float]"
+
+#: elf32-vax.c:555
+msgid " [g-float]"
+msgstr " [g-float]"
+
+#: elf32-vax.c:663
+#, c-format
+msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld"
+msgstr "%s: avertisment: adăugarea GOT a %ld în `%s' nu se potrivește adăugării GOT anterioare a %ld"
+
+#: elf32-vax.c:1667
+#, c-format
+msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored"
+msgstr "%s: avertisment: adăugarea PLT a %d în `%s' din secțiunea %s ignorată"
+
+#: elf32-vax.c:1802
+#, c-format
+msgid "%s: warning: %s relocation against symbol `%s' from %s section"
+msgstr "%s: avertisment: relocare %s pentru simbolul `%s' din secțiunea %s"
+
+#: elf32-vax.c:1808
+#, c-format
+msgid "%s: warning: %s relocation to 0x%x from %s section"
+msgstr "%s: avertisment: relocare %s spre 0x%x din secțiunea %s"
+
+#: elf32-xstormy16.c:462 elf32-ia64.c:2450 elf64-ia64.c:2450
+msgid "non-zero addend in @fptr reloc"
+msgstr "adăugare non-zero în relocare @fptr"
+
+#: elf64-alpha.c:1108
+msgid "GPDISP relocation did not find ldah and lda instructions"
+msgstr "relocarea GPDISP nu a găsit instrucțiuni ldah și lda"
+
+#: elf64-alpha.c:3731
+#, c-format
+msgid "%s: .got subsegment exceeds 64K (size %d)"
+msgstr "%s: .subsegmentul got depăsește 64K (size %d)"
+
+#: elf64-alpha.c:4602 elf64-alpha.c:4614
+#, c-format
+msgid "%s: gp-relative relocation against dynamic symbol %s"
+msgstr "%s: relocare relativă-gp pentru simbolul %s"
+
+#: elf64-alpha.c:4640 elf64-alpha.c:4773
+#, c-format
+msgid "%s: pc-relative relocation against dynamic symbol %s"
+msgstr "%s: relocare relativă pc pentru simbolul dinamic %s"
+
+#: elf64-alpha.c:4668
+#, c-format
+msgid "%s: change in gp: BRSGP %s"
+msgstr "%s: schimbare în gp: BRSGP %s"
+
+#: elf64-alpha.c:4693
+msgid "<unknown>"
+msgstr "<necunoscut>"
+
+#: elf64-alpha.c:4698
+#, c-format
+msgid "%s: !samegp reloc against symbol without .prologue: %s"
+msgstr "%s: !samegp reloc apentru simbol fără .prologue: %s"
+
+#: elf64-alpha.c:4749
+#, c-format
+msgid "%s: unhandled dynamic relocation against %s"
+msgstr "%s: relocare dinamică nemanipulabilă pentru %s"
+
+#: elf64-alpha.c:4832
+#, c-format
+msgid "%s: dtp-relative relocation against dynamic symbol %s"
+msgstr "%s: relocare relativă-dtp pentru simbolul dinamic %s"
+
+#: elf64-alpha.c:4855
+#, c-format
+msgid "%s: tp-relative relocation against dynamic symbol %s"
+msgstr "%s: relocare relativă-tp pentru simbolul dinamic %s"
+
+#: elf64-hppa.c:2086
+#, c-format
+msgid "stub entry for %s cannot load .plt, dp offset = %ld"
+msgstr "intrarea trunchiată pentru %s nu poate încărca .plt, offset dp = %ld"
+
+#: elf64-mmix.c:1032
+#, c-format
+msgid ""
+"%s: Internal inconsistency error for value for\n"
+" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n"
+msgstr ""
+"%s: eroare internă de inconsistență pentru valoarea\n"
+"registrului global alocat de linker: linkuit: 0x%lx%08lx != relaxat: 0x%lx%08lx\n"
+
+#: elf64-mmix.c:1416
+#, c-format
+msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s"
+msgstr "%s:relocare-offset-bază-plus pentru simbolul registru: (necunoscut) în %s"
+
+#: elf64-mmix.c:1421
+#, c-format
+msgid "%s: base-plus-offset relocation against register symbol: %s in %s"
+msgstr "%s:relocare-offset-bază-plus pentru simbolul registru: %s în %s"
+
+#: elf64-mmix.c:1465
+#, c-format
+msgid "%s: register relocation against non-register symbol: (unknown) in %s"
+msgstr "%s:relocare registru pentru simbolul non-registru: (necunoscut) în %s"
+
+#: elf64-mmix.c:1470
+#, c-format
+msgid "%s: register relocation against non-register symbol: %s in %s"
+msgstr "%s:relocare registru pentru simbolul non-registru: %s în %s"
+
+#: elf64-mmix.c:1507
+#, c-format
+msgid "%s: directive LOCAL valid only with a register or absolute value"
+msgstr "%s: directiva LOCAL este validă doar cu un registru sau o valoare absolută"
+
+#: elf64-mmix.c:1535
+#, c-format
+msgid "%s: LOCAL directive: Register $%ld is not a local register.  First global register is $%ld."
+msgstr "%s: directivă LOCAL: Registrulr $%ld nu este un registru local.  Primul registru global $%ld."
+
+#: elf64-mmix.c:1994
+#, c-format
+msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n"
+msgstr "%s: Eroare: definiții multiple ale `%s'; începutul lui %s este setat într-un fișierlinkuit anterior\n"
+
+#: elf64-mmix.c:2053
+msgid "Register section has contents\n"
+msgstr "Secțiunea registru nu are conținut\n"
+
+#: elf64-mmix.c:2216
+#, c-format
+msgid ""
+"Internal inconsistency: remaining %u != max %u.\n"
+"  Please report this bug."
+msgstr ""
+"Inconsistență internă: rămâne %u ! = max %u\n"
+"  Vă rugăm raportați acest bug."
+
+#: elf64-ppc.c:2388 libbfd.c:831
+#, c-format
+msgid "%s: compiled for a big endian system and target is little endian"
+msgstr "%s: compilat pentru un sistem big endiat iar ținta este little endian"
+
+#: elf64-ppc.c:2391 libbfd.c:833
+#, c-format
+msgid "%s: compiled for a little endian system and target is big endian"
+msgstr "%s: compilat pentru un sistem little endiat iar ținta este big endian"
+
+#: elf64-ppc.c:4857
+#, c-format
+msgid "%s: unexpected reloc type %u in .opd section"
+msgstr "%s: tip de relocare neașteptat %u în secțiune .opd"
+
+#: elf64-ppc.c:4877
+#, c-format
+msgid "%s: .opd is not a regular array of opd entries"
+msgstr "%s: .opd nu este un domeniu(array) de intrări opd"
+
+#: elf64-ppc.c:4897
+#, c-format
+msgid "%s: undefined sym `%s' in .opd section"
+msgstr "%s: sym nedefinit `%s' în secțiune .opd"
+
+#: elf64-ppc.c:6136
+#, c-format
+msgid "can't find branch stub `%s'"
+msgstr "nu pot găsi ramura trunchiată `%s'"
+
+#: elf64-ppc.c:6175 elf64-ppc.c:6250
+#, c-format
+msgid "linkage table error against `%s'"
+msgstr "eroare tabel de linkuire pentru `%s'"
+
+#: elf64-ppc.c:6340
+#, c-format
+msgid "can't build branch stub `%s'"
+msgstr "nu se poate construi ramura trunchiată `%s'"
+
+#: elf64-ppc.c:7047
+msgid ".glink and .plt too far apart"
+msgstr ".glink și .plt prea departe unul de altul"
+
+#: elf64-ppc.c:7135
+msgid "stubs don't match calculated size"
+msgstr "trunchierile(stubs) sunt în neconcordanță cu mărimea calculată"
+
+#: elf64-ppc.c:7147
+#, c-format
+msgid ""
+"linker stubs in %u groups\n"
+"  branch       %lu\n"
+"  toc adjust   %lu\n"
+"  long branch  %lu\n"
+"  long toc adj %lu\n"
+"  plt call     %lu"
+msgstr ""
+"trunchieri(stubs) de linker în grupurile %u\n"
+"  ramură       %lu\n"
+"  ajustare toc   %lu\n"
+"  ramură lungă  %lu\n"
+"  ajust. lungă toc %lu\n"
+"  apelare plt     %lu"
+
+#: elf64-ppc.c:7723
+#, c-format
+msgid "%s(%s+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc"
+msgstr "%s(%s+0x%lx): TOCuri multiple nu sunt suportateîn folosirea fișierelor voastre crt; recompilați cu  -mminimal-toc sau upgradați gcc"
+
+#: elf64-ppc.c:7731
+#, c-format
+msgid "%s(%s+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern"
+msgstr "%s(%s+0 x%lx): optimizare apelare sibling pentru `%s' nu permite automatTOCuri multiple; recompilați cu -mminimal-toc sau -fno-optimize-sibling-calls, sau faceți(make) `%s' extern"
+
+#: elf64-ppc.c:8329
+#, c-format
+msgid "%s: relocation %s is not supported for symbol %s."
+msgstr "%s: relocarea %s nu este suportată pentru simbolul %s."
+
+#: elf64-ppc.c:8408
+#, c-format
+msgid "%s: error: relocation %s not a multiple of %d"
+msgstr "%s: eroare: relocarea %s nu este multiplu de %d"
+
+#: elf64-sparc.c:1370
+#, c-format
+msgid "%s: check_relocs: unhandled reloc type %d"
+msgstr "%s: check_relocs: tip de relocare nemanipulabil %d"
+
+#: elf64-sparc.c:1407
+#, c-format
+msgid "%s: Only registers %%g[2367] can be declared using STT_REGISTER"
+msgstr "%s: Doar regiștrii %%g[2367] pot fi declarați folosind STT_REGISTER"
+
+#: elf64-sparc.c:1427
+#, c-format
+msgid "Register %%g%d used incompatibly: %s in %s, previously %s in %s"
+msgstr "Registrul %%g%d a folosit incompatibilități: %s în %s, anterior %s în %s"
+
+#: elf64-sparc.c:1450
+#, c-format
+msgid "Symbol `%s' has differing types: REGISTER in %s, previously %s in %s"
+msgstr "Simbolul `%s' are tipuri diferențiate: REGISTER în %s, anterior %s în %s"
+
+#: elf64-sparc.c:1496
+#, c-format
+msgid "Symbol `%s' has differing types: %s in %s, previously REGISTER in %s"
+msgstr "Simbolul `%s' are tipuri diferențiate: %s în %s, anterior REGISTER în %s"
+
+#: elf64-sparc.c:3053
+#, c-format
+msgid "%s: linking UltraSPARC specific with HAL specific code"
+msgstr "%s: linkuire cod specific UltraSPARC cu cod specific HAL"
+
+#: elf64-x86-64.c:739
+#, c-format
+msgid "%s: %s' accessed both as normal and thread local symbol"
+msgstr "%s: `%s' accesate și ca simboluri locale normale și ca simboluri locale pe fire (thread)"
+
+#: elfcode.h:1113
+#, c-format
+msgid "%s: version count (%ld) does not match symbol count (%ld)"
+msgstr "%s: numărul versiunii(%ld) nu se potrivește cu numărul simbolului (%ld)"
+
+#: elfcode.h:1342
+#, c-format
+msgid "%s(%s): relocation %d has invalid symbol index %ld"
+msgstr "%s(%s): relocarea %d are indexul de simbol invalid %ld"
+
+#: elflink.c:1456
+#, c-format
+msgid "%s: warning: unexpected redefinition of indirect versioned symbol `%s'"
+msgstr "%s: avertisment: redefinire neașteptată a simbolului indirect cu versiune(versioned) `%s'"
+
+#: elflink.c:1807
+#, c-format
+msgid "%s: undefined versioned symbol name %s"
+msgstr "%s: nume de simbol versiune %s nedefinit"
+
+#: elflink.c:2142
+#, c-format
+msgid "%s: relocation size mismatch in %s section %s"
+msgstr "%s: nepotrivire a mărimii de relocare în %s secțiunea %s"
+
+#: elflink.c:2434
+#, c-format
+msgid "warning: type and size of dynamic symbol `%s' are not defined"
+msgstr "avertisment: tipul și mărimea simbolului dinamic `%s' nu sunt definite"
+
+#: elflink.h:1022
+#, c-format
+msgid "%s: %s: invalid version %u (max %d)"
+msgstr "%s: %s: versiune invalidă %u (max %d)"
+
+#: elflink.h:1063
+#, c-format
+msgid "%s: %s: invalid needed version %d"
+msgstr "%s: %s: versiune necesară %d invalidă"
+
+#: elflink.h:1238
+#, c-format
+msgid "Warning: alignment %u of symbol `%s' in %s is smaller than %u in %s"
+msgstr "Avertisment: alinierea %u al simbolului `%s' din %s este mai mică decât %u în %s"
+
+#: elflink.h:1252
+#, c-format
+msgid "Warning: size of symbol `%s' changed from %lu in %s to %lu in %s"
+msgstr "Avertisment: mărimea simbolului `%s' a fost schimbată din %lu din %s în %lu din %s"
+
+#: elflink.h:2160
+#, c-format
+msgid "%s: undefined version: %s"
+msgstr "%s:versiune %s nedefinită"
+
+#: elflink.h:2226
+#, c-format
+msgid "%s: .preinit_array section is not allowed in DSO"
+msgstr "%s: secțiunea .preinit_array section nu este permisă în DSO"
+
+#: elflink.h:3078
+msgid "Not enough memory to sort relocations"
+msgstr "Nu există memorie suficientă pentru a sorta relocările"
+
+#: elflink.h:3958 elflink.h:4001
+#, c-format
+msgid "%s: could not find output section %s"
+msgstr "%s: nu s-a putut găsi secțiunea de output %s"
+
+#: elflink.h:3964
+#, c-format
+msgid "warning: %s section has zero size"
+msgstr "avertisment: secțiunea %s are mărime zero"
+
+#: elflink.h:4483
+#, c-format
+msgid "%s: %s symbol `%s' in %s is referenced by DSO"
+msgstr "%s: %s simbolul `%s' în %s este referit de DSO"
+
+#: elflink.h:4564
+#, c-format
+msgid "%s: could not find output section %s for input section %s"
+msgstr "%s: nu am putut găsi secțiunea de output %s pentru secțiunea de input %s"
+
+#: elflink.h:4666
+#, c-format
+msgid "%s: %s symbol `%s' isn't defined"
+msgstr "%s: %s simbolul `%s' nu este definit"
+
+#: elflink.h:5053 elflink.h:5095
+msgid "%T: discarded in section `%s' from %s\n"
+msgstr "%T: abandonat(discarded) în secțiunea `%s' din %s\n"
+
+#: elfxx-mips.c:887
+msgid "static procedure (no name)"
+msgstr "procedură statică (fără nume)"
+
+#: elfxx-mips.c:1897
+msgid "not enough GOT space for local GOT entries"
+msgstr "nu există destul spațiu GOT pentru intrările GOT locale"
+
+#: elfxx-mips.c:3691
+#, c-format
+msgid "%s: %s+0x%lx: jump to stub routine which is not jal"
+msgstr "%s: %s+0x%lx: salt la rutină ciot(stub) ce nu este jal"
+
+#: elfxx-mips.c:5192
+#, c-format
+msgid "%s: Malformed reloc detected for section %s"
+msgstr "%s: Relocare malformată detectată pentru secțiunea %s"
+
+#: elfxx-mips.c:5266
+#, c-format
+msgid "%s: CALL16 reloc at 0x%lx not against global symbol"
+msgstr "%s: relocarea CALL16 la 0x%lx nu este pe simbolul global"
+
+#: elfxx-mips.c:8692
+#, c-format
+msgid "%s: illegal section name `%s'"
+msgstr "%s: nume ilegal de secțiune `%s'"
+
+#: elfxx-mips.c:9025
+#, c-format
+msgid "%s: endianness incompatible with that of the selected emulation"
+msgstr "%s: endianness incompatibilă cu aceea a emulației selectate"
+
+#: elfxx-mips.c:9037
+#, c-format
+msgid "%s: ABI is incompatible with that of the selected emulation"
+msgstr "%s: ABI este incompatibil cu cel al emulației selectate"
+
+#: elfxx-mips.c:9104
+#, c-format
+msgid "%s: warning: linking PIC files with non-PIC files"
+msgstr "%s: avertisment: linkuire de fișiere PIC cu fișiere non-PIC"
+
+#: elfxx-mips.c:9121
+#, c-format
+msgid "%s: linking 32-bit code with 64-bit code"
+msgstr "%s: linkuire cod 32-biți cu cod 64-biți"
+
+#: elfxx-mips.c:9149
+#, c-format
+msgid "%s: linking %s module with previous %s modules"
+msgstr "%s: linkuire a modulului %s cu modulele%s anterioare"
+
+#: elfxx-mips.c:9172
+#, c-format
+msgid "%s: ABI mismatch: linking %s module with previous %s modules"
+msgstr "%s: nepotrivire ABI: linkuire modul %s cu module %s anterioare"
+
+#: elfxx-mips.c:9241
+msgid " [abi=O32]"
+msgstr " [abi=O32]"
+
+#: elfxx-mips.c:9243
+msgid " [abi=O64]"
+msgstr " [abi=O64]"
+
+#: elfxx-mips.c:9245
+msgid " [abi=EABI32]"
+msgstr " [abi=EABI32]"
+
+#: elfxx-mips.c:9247
+msgid " [abi=EABI64]"
+msgstr " [abi=EABI64]"
+
+#: elfxx-mips.c:9249
+msgid " [abi unknown]"
+msgstr " [abi necunoscut]"
+
+#: elfxx-mips.c:9251
+msgid " [abi=N32]"
+msgstr " [abi=N32]"
+
+#: elfxx-mips.c:9253
+msgid " [abi=64]"
+msgstr " [abi=64]"
+
+#: elfxx-mips.c:9255
+msgid " [no abi set]"
+msgstr " [abi nesetat]"
+
+#: elfxx-mips.c:9258
+msgid " [mips1]"
+msgstr " [mips1]"
+
+#: elfxx-mips.c:9260
+msgid " [mips2]"
+msgstr " [mips2]"
+
+#: elfxx-mips.c:9262
+msgid " [mips3]"
+msgstr " [mips3]"
+
+#: elfxx-mips.c:9264
+msgid " [mips4]"
+msgstr " [mips4]"
+
+#: elfxx-mips.c:9266
+msgid " [mips5]"
+msgstr " [mips5]"
+
+#: elfxx-mips.c:9268
+msgid " [mips32]"
+msgstr " [mips32]"
+
+#: elfxx-mips.c:9270
+msgid " [mips64]"
+msgstr " [mips64]"
+
+#: elfxx-mips.c:9272
+msgid " [mips32r2]"
+msgstr " [mips32r2]"
+
+#: elfxx-mips.c:9274
+msgid " [unknown ISA]"
+msgstr " [ISA necunoscut]"
+
+#: elfxx-mips.c:9277
+msgid " [mdmx]"
+msgstr " [mdmx]"
+
+#: elfxx-mips.c:9280
+msgid " [mips16]"
+msgstr " [mips16]"
+
+#: elfxx-mips.c:9283
+msgid " [32bitmode]"
+msgstr " [mod32biți]"
+
+#: elfxx-mips.c:9285
+msgid " [not 32bitmode]"
+msgstr " [non-mod32biți]"
+
+#: i386linux.c:457 m68klinux.c:461 sparclinux.c:458
+#, c-format
+msgid "Output file requires shared library `%s'\n"
+msgstr "Fișierul de output necesită biblioteca globală(shared) `%s'\n"
+
+#: i386linux.c:465 m68klinux.c:469 sparclinux.c:466
+#, c-format
+msgid "Output file requires shared library `%s.so.%s'\n"
+msgstr "Fișierul de output necesită biblioteca globală(shared) `%s'.so.`%s'\n"
+
+#: i386linux.c:654 i386linux.c:704 m68klinux.c:661 m68klinux.c:709
+#: sparclinux.c:656 sparclinux.c:706
+#, c-format
+msgid "Symbol %s not defined for fixups\n"
+msgstr "Simbolul %s nu este definit pentru acceptare(fixups)\n"
+
+#: i386linux.c:728 m68klinux.c:733 sparclinux.c:730
+msgid "Warning: fixup count mismatch\n"
+msgstr "Avertisment: nepotrivire numărători acceptare(fixup)\n"
+
+#: ieee.c:293
+#, c-format
+msgid "%s: string too long (%d chars, max 65535)"
+msgstr "%s: șir prea lung (%d caractere, max 65535)"
+
+#: ieee.c:428
+#, c-format
+msgid "%s: unrecognized symbol `%s' flags 0x%x"
+msgstr "%s: simbol necunoscut `%s' marcaje(flags) 0x%x"
+
+#: ieee.c:938
+#, c-format
+msgid "%s: unimplemented ATI record %u for symbol %u"
+msgstr "%s: înregistrare ATI neimplementată %u pe simbolul %u"
+
+#: ieee.c:963
+#, c-format
+msgid "%s: unexpected ATN type %d in external part"
+msgstr "%s: tip ATN neașteptat %d în parte externă"
+
+#: ieee.c:985
+#, c-format
+msgid "%s: unexpected type after ATN"
+msgstr "%s: tip neașteptat după ATN"
+
+#: ihex.c:264
+#, c-format
+msgid "%s:%d: unexpected character `%s' in Intel Hex file\n"
+msgstr "%s:%d: caracter neașteptat `%s' în fișier Intel Hex\n"
+
+#: ihex.c:372
+#, c-format
+msgid "%s:%u: bad checksum in Intel Hex file (expected %u, found %u)"
+msgstr "%s:%u: checksum invalid în fișier Intel Hex (se aștepta %u, s-a găsit %u)"
+
+#: ihex.c:426
+#, c-format
+msgid "%s:%u: bad extended address record length in Intel Hex file"
+msgstr "%s: %u: mărime înregistrare a adresei extinse invalidă în fișier Intel Hex"
+
+#: ihex.c:443
+#, c-format
+msgid "%s:%u: bad extended start address length in Intel Hex file"
+msgstr "%s: %u: mărime adresă de start extinsă invalidă în fișier Intel Hex"
+
+#: ihex.c:460
+#, c-format
+msgid "%s:%u: bad extended linear address record length in Intel Hex file"
+msgstr "%s: %u: mărime înregistrare a adresei lineare extinse invalidă în fișier Intel Hex"
+
+#: ihex.c:477
+#, c-format
+msgid "%s:%u: bad extended linear start address length in Intel Hex file"
+msgstr "%s: %u: mărime adresă lineară de start extinsă invalidă în fișier Intel Hex"
+
+#: ihex.c:494
+#, c-format
+msgid "%s:%u: unrecognized ihex type %u in Intel Hex file\n"
+msgstr "%s: %u: tip ihex necunoscut %u în fișier Intel Hex\n"
+
+#: ihex.c:619
+#, c-format
+msgid "%s: internal error in ihex_read_section"
+msgstr "%s: eroare internă în ihex_read_section"
+
+#: ihex.c:654
+#, c-format
+msgid "%s: bad section length in ihex_read_section"
+msgstr "%s: mărime secțiune invalidă în ihex_read_section"
+
+#: ihex.c:872
+#, c-format
+msgid "%s: address 0x%s out of range for Intel Hex file"
+msgstr "%s: adresa 0x%s este în afara domeniului(range) pentru fișierul Intel Hex"
+
+#: libbfd.c:861
+#, c-format
+msgid "Deprecated %s called at %s line %d in %s\n"
+msgstr "%s învechită apelată la %s linia %d în %s\n"
+
+#: libbfd.c:864
+#, c-format
+msgid "Deprecated %s called\n"
+msgstr "%s învechită apelată\n"
+
+#: linker.c:1829
+#, c-format
+msgid "%s: indirect symbol `%s' to `%s' is a loop"
+msgstr "%s: simbolul indirect `%s' pentru `%s' este o buclă"
+
+#: linker.c:2697
+#, c-format
+msgid "Attempt to do relocatable link with %s input and %s output"
+msgstr "Încercare de a crea un link relocabil cu input %s și output %s"
+
+#: merge.c:896
+#, c-format
+msgid "%s: access beyond end of merged section (%ld + %ld)"
+msgstr "%s: acces dincolo de sfârșitul secțiunii concatenate(merged) (%ld + %ld)"
+
+#: mmo.c:503
+#, c-format
+msgid "%s: No core to allocate section name %s\n"
+msgstr "%s:Nu există nucleu(core) pentru a aloca numele de secțiune %s\n"
+
+#: mmo.c:579
+#, c-format
+msgid "%s: No core to allocate a symbol %d bytes long\n"
+msgstr "%s: Nu există nucleu(core) pentru a aloca un simbol lung de %d octeți\n"
+
+#: mmo.c:1287
+#, c-format
+msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n"
+msgstr "%s: fișier mmo invalid: valoare de inițializare pentru $255 nu este 'Main'\n"
+
+#: mmo.c:1433
+#, c-format
+msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n"
+msgstr "%s: secvență mare(wide) de caractere 0x%02X 0x%02X nesuportată după numele de simbol care începe cu `%s'\n"
+
+#: mmo.c:1674
+#, c-format
+msgid "%s: invalid mmo file: unsupported lopcode `%d'\n"
+msgstr "%s: fișier mmo invalid: lopcode `%d' nesuportat\n"
+
+#: mmo.c:1684
+#, c-format
+msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n"
+msgstr "%s: fișier mmo invalid: pentru lop_quote se aștepta YZ = 1 s-a primit YZ= %d\n"
+
+#: mmo.c:1720
+#, c-format
+msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n"
+msgstr "%s: fișier mmo invalid: pentru lop_loc se aștepta z =1 sau z =  2 s-a primit z = %d\n"
+
+#: mmo.c:1766
+#, c-format
+msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n"
+msgstr "%s: fișier mmo invalid: pentru lop_fixo se aștepta z =1 sau z =  2 s-a primit z = %d\n"
+
+#: mmo.c:1805
+#, c-format
+msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n"
+msgstr "%s: fișier mmo invalid: pentru lop_fixrx se aștepta y =0 s-a primit y = %d\n"
+
+#: mmo.c:1814
+#, c-format
+msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n"
+msgstr "%s: fișier mmo invalid: pentru lop_fixrx se aștepta z =16 sau z = 24 s-a primit z = %d\n"
+
+#: mmo.c:1837
+#, c-format
+msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n"
+msgstr "%s: fișier mmo invalid: pentru lop_fixrx octetul de înceout al operandului word trebuie să fie 0 sau 1, s-a primit %d\n"
+
+#: mmo.c:1860
+#, c-format
+msgid "%s: cannot allocate file name for file number %d, %d bytes\n"
+msgstr "%s: nu se poate aloca nume fișier pentru fișierul numărul %d, %d octeți\n"
+
+#: mmo.c:1880
+#, c-format
+msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n"
+msgstr "%s: fișier mmo invalid: fișierul numărul %d `%s' a fost deja introdus ca `%s'\n"
+
+#: mmo.c:1893
+#, c-format
+msgid "%s: invalid mmo file: file name for number %d was not specified before use\n"
+msgstr "%s: fișier mmo invalid: numele de fișier pentru numărul %d nu a fost specificat înainte de folosire\n"
+
+#: mmo.c:1999
+#, c-format
+msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n"
+msgstr "%s: fișier mmo invalid: câmpurile y și z ale lop_stab sunt non-zero: y: %d, z: %d\n"
+
+#: mmo.c:2035
+#, c-format
+msgid "%s: invalid mmo file: lop_end not last item in file\n"
+msgstr "%s: fișier mmo invalid: lop_end nu este ultimul element în fișier\n"
+
+#: mmo.c:2048
+#, c-format
+msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n"
+msgstr "%s: fișier mmo invalid: YZ al lop_end (%ld) nu este egal cu numerele tetras ale lop_stab precedent (%ld)\n"
+
+#: mmo.c:2698
+#, c-format
+msgid "%s: invalid symbol table: duplicate symbol `%s'\n"
+msgstr "%s: tabelă de simboluri invalidă: simbol `%s' duplicat\n"
+
+#: mmo.c:2949
+#, c-format
+msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n"
+msgstr "%s: Definire invalidă de simbol: `Main' setat la %s în loc de adresa de start %s\n"
+
+#: mmo.c:3039
+#, c-format
+msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d.  Only `Main' will be emitted.\n"
+msgstr "%s: avertisment: tabela de simboluri prea mare pentru mmo, mai mare decâd 65535 cuvinte pe 32 de biți: %d.  Doar 'Main' va fi emis.\n"
+
+#: mmo.c:3084
+#, c-format
+msgid "%s: internal error, symbol table changed size from %d to %d words\n"
+msgstr "%s: eroare internă, tabela de simboluri și-a schimbat mărimea din %d în %d cuvinte\n"
+
+#: mmo.c:3139
+#, c-format
+msgid "%s: internal error, internal register section %s had contents\n"
+msgstr "%s: eroare internă, secțiunea de regiștri internă %s nu are conținut\n"
+
+#: mmo.c:3191
+#, c-format
+msgid "%s: no initialized registers; section length 0\n"
+msgstr "%s: nu există regiștri inițializați; lungime secțiune 0\n"
+
+#: mmo.c:3197
+#, c-format
+msgid "%s: too many initialized registers; section length %ld\n"
+msgstr "%s: prea mulți regiștri inițializați; lungime secțiune %ld\n"
+
+#: mmo.c:3202
+#, c-format
+msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n"
+msgstr "%s: adresă de start invalidă pentru regiștrii inițializați de lungime %ld: 0x%lx%08lx\n"
+
+#: oasys.c:1052
+#, c-format
+msgid "%s: can not represent section `%s' in oasys"
+msgstr "%s: nu se poate reprezenta secțiune `%s' în oasys"
+
+#: osf-core.c:137
+#, c-format
+msgid "Unhandled OSF/1 core file section type %d\n"
+msgstr "Tip nemanipulabil %d de fișier nucleu(core) OSF/1\n"
+
+#: pe-mips.c:659
+#, c-format
+msgid "%s: `ld -r' not supported with PE MIPS objects\n"
+msgstr "%s: `ld -r' nu este suportat cu obiecte PE MIPS\n"
+
+#. OK, at this point the following variables are set up:
+#. src = VMA of the memory we're fixing up
+#. mem = pointer to memory we're fixing up
+#. val = VMA of what we need to refer to
+#.
+#: pe-mips.c:795
+#, c-format
+msgid "%s: unimplemented %s\n"
+msgstr "%s: %s neimplementat\n"
+
+#: pe-mips.c:821
+#, c-format
+msgid "%s: jump too far away\n"
+msgstr "%s: salt prea departe(far away)\n"
+
+#: pe-mips.c:848
+#, c-format
+msgid "%s: bad pair/reflo after refhi\n"
+msgstr "%s: pair/reflo invalid după refhi\n"
+
+#. XXX code yet to be written.
+#: peicode.h:787
+#, c-format
+msgid "%s: Unhandled import type; %x"
+msgstr "%s: Tip import nemanipulabil; %x"
+
+#: peicode.h:792
+#, c-format
+msgid "%s: Unrecognised import type; %x"
+msgstr "%s: Tip import necunoscut; %x"
+
+#: peicode.h:806
+#, c-format
+msgid "%s: Unrecognised import name type; %x"
+msgstr "%s: Tip nume import necunoscut; %x"
+
+#: peicode.h:1164
+#, c-format
+msgid "%s: Unrecognised machine type (0x%x) in Import Library Format archive"
+msgstr "%s: Tip mașină necunoscut (0x%x) în arhiva Import Library Format"
+
+#: peicode.h:1176
+#, c-format
+msgid "%s: Recognised but unhandled machine type (0x%x) in Import Library Format archive"
+msgstr "%s: Tip de mașină recunoscut dar nemanipulabil (0x%x) în arhiva Import Library Format"
+
+#: peicode.h:1193
+#, c-format
+msgid "%s: size field is zero in Import Library Format header"
+msgstr "%s: mărimea câmpului din headerul Import Library Format este zero"
+
+#: peicode.h:1224
+#, c-format
+msgid "%s: string not null terminated in ILF object file."
+msgstr "%s: șirul nenul terminat în fișier obiect ILF."
+
+#: ppcboot.c:416
+msgid ""
+"\n"
+"ppcboot header:\n"
+msgstr ""
+"\n"
+"header ppcboot:\n"
+
+#: ppcboot.c:417
+#, c-format
+msgid "Entry offset        = 0x%.8lx (%ld)\n"
+msgstr "Offset intrare        = 0x%.8lx (%ld)\n"
+
+#: ppcboot.c:418
+#, c-format
+msgid "Length              = 0x%.8lx (%ld)\n"
+msgstr "Lungime              = 0x%.8lx (%ld)\n"
+
+#: ppcboot.c:421
+#, c-format
+msgid "Flag field          = 0x%.2x\n"
+msgstr "Câmp Marcaj(Flag)      = 0x%.2x\n"
+
+#: ppcboot.c:427
+#, c-format
+msgid "Partition name      = \"%s\"\n"
+msgstr "Nume Partiție      = \"%s\"\n"
+
+#: ppcboot.c:446
+#, c-format
+msgid ""
+"\n"
+"Partition[%d] start  = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n"
+msgstr ""
+"\n"
+"Start Partiție[%d]  = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n"
+
+#: ppcboot.c:452
+#, c-format
+msgid "Partition[%d] end    = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n"
+msgstr "Sfârșit Partiție[%d]    = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n"
+
+#: ppcboot.c:458
+#, c-format
+msgid "Partition[%d] sector = 0x%.8lx (%ld)\n"
+msgstr "Sector Partiție[%d] sector = 0x%.8lx (%ld)\n"
+
+#: ppcboot.c:459
+#, c-format
+msgid "Partition[%d] length = 0x%.8lx (%ld)\n"
+msgstr "Mărime Partiție[%d] = 0x%.8lx (%ld)\n"
+
+#: som.c:5422
+msgid "som_sizeof_headers unimplemented"
+msgstr "som_sizeof_headers neimplementată"
+
+#: srec.c:302
+#, c-format
+msgid "%s:%d: Unexpected character `%s' in S-record file\n"
+msgstr "%s:%d: Caracter neașteptat `%s'în fișier S-record\n"
+
+#: stabs.c:319
+#, c-format
+msgid "%s(%s+0x%lx): Stabs entry has invalid string index."
+msgstr "%s(%s+0x%lx): Intrarea bruscă(stab) are index șir invalid."
+
+#: syms.c:1019
+msgid "Unsupported .stab relocation"
+msgstr "Relocare .stab nesuportată"
+
+#: vms-gsd.c:356
+#, c-format
+msgid "bfd_make_section (%s) failed"
+msgstr "bfd_make_section (%s) eșuată"
+
+#: vms-gsd.c:371
+#, c-format
+msgid "bfd_set_section_flags (%s, %x) failed"
+msgstr "bfd_set_section_flags (%s, %x) eșuată"
+
+#: vms-gsd.c:407
+#, c-format
+msgid "Size mismatch section %s=%lx, %s=%lx"
+msgstr "Mărime nepotrivită secțiune %s=%lx, %s=%lx"
+
+#: vms-gsd.c:704
+#, c-format
+msgid "unknown gsd/egsd subtype %d"
+msgstr "subtip %d gsd/egsd necunoscut"
+
+#: vms-hdr.c:408
+msgid "Object module NOT error-free !\n"
+msgstr "Modul obiect CU erori !\n"
+
+#: vms-misc.c:541
+#, c-format
+msgid "Stack overflow (%d) in _bfd_vms_push"
+msgstr "Depășire(overflow) de stivă(%d) în bfd_vms_push"
+
+#: vms-misc.c:559
+msgid "Stack underflow in _bfd_vms_pop"
+msgstr "Subfolosire(underflow) a stivei _bfd_vms_pop"
+
+#: vms-misc.c:918
+msgid "_bfd_vms_output_counted called with zero bytes"
+msgstr "_bfd_vms_output_counted apelat cu zero octeți"
+
+#: vms-misc.c:923
+msgid "_bfd_vms_output_counted called with too many bytes"
+msgstr "_bfd_vms_output_counted apelat cu prea mulți octeți"
+
+#: vms-misc.c:1054
+#, c-format
+msgid "Symbol %s replaced by %s\n"
+msgstr "Simbolul %s înlocuit de %s\n"
+
+#: vms-misc.c:1117
+#, c-format
+msgid "failed to enter %s"
+msgstr "Eșec în introducerea %s"
+
+#: vms-tir.c:102
+msgid "No Mem !"
+msgstr "Nu mai există Mem !"
+
+#: vms-tir.c:383
+#, c-format
+msgid "bad section index in %s"
+msgstr "index de secțiune invalid în %s"
+
+#: vms-tir.c:396
+#, c-format
+msgid "unsupported STA cmd %s"
+msgstr "cmd STA %s nesuportată"
+
+#: vms-tir.c:401 vms-tir.c:1261
+#, c-format
+msgid "reserved STA cmd %d"
+msgstr "cmd STA %d rezervată"
+
+#: vms-tir.c:512 vms-tir.c:535
+#, c-format
+msgid "%s: no symbol \"%s\""
+msgstr "%s: nu există simbolul \"%s\""
+
+#. unsigned shift
+#. rotate
+#. Redefine symbol to current location.
+#. Define a literal.
+#: vms-tir.c:602 vms-tir.c:714 vms-tir.c:824 vms-tir.c:842 vms-tir.c:850
+#: vms-tir.c:859 vms-tir.c:1584
+#, c-format
+msgid "%s: not supported"
+msgstr "%s: nesuportat"
+
+#: vms-tir.c:607 vms-tir.c:1439
+#, c-format
+msgid "%s: not implemented"
+msgstr "%s: neimplementat"
+
+#: vms-tir.c:611 vms-tir.c:1443
+#, c-format
+msgid "reserved STO cmd %d"
+msgstr "cmd STO %d rezervată"
+
+#: vms-tir.c:729 vms-tir.c:1589
+#, c-format
+msgid "reserved OPR cmd %d"
+msgstr "cmd OPR %d rezervată"
+
+#: vms-tir.c:797 vms-tir.c:1653
+#, c-format
+msgid "reserved CTL cmd %d"
+msgstr "cmd CTL %d rezervată"
+
+#. stack byte from image
+#. arg: none.
+#: vms-tir.c:1169
+msgid "stack-from-image not implemented"
+msgstr "stack-from-image neimplementată"
+
+#: vms-tir.c:1187
+msgid "stack-entry-mask not fully implemented"
+msgstr "stack-entry-mask neimplementată complet"
+
+#. compare procedure argument
+#. arg: cs	symbol name
+#. by	argument index
+#. da	argument descriptor
+#.
+#. compare argument descriptor with symbol argument (ARG$V_PASSMECH)
+#. and stack TRUE (args match) or FALSE (args dont match) value.
+#: vms-tir.c:1201
+msgid "PASSMECH not fully implemented"
+msgstr "PASSMECH neimplementată complet"
+
+#: vms-tir.c:1220
+msgid "stack-local-symbol not fully implemented"
+msgstr "stack-local-symbol neimplementată complet"
+
+#: vms-tir.c:1233
+msgid "stack-literal not fully implemented"
+msgstr "stack-literal neimplementată complet"
+
+#: vms-tir.c:1254
+msgid "stack-local-symbol-entry-point-mask not fully implemented"
+msgstr "stack-local-symbol-entry-point-mask neimplementată complet"
+
+#: vms-tir.c:1531 vms-tir.c:1543 vms-tir.c:1555 vms-tir.c:1567 vms-tir.c:1632
+#: vms-tir.c:1640 vms-tir.c:1648
+#, c-format
+msgid "%s: not fully implemented"
+msgstr "%s: neimplementată complet"
+
+#: vms-tir.c:1705
+#, c-format
+msgid "obj code %d not found"
+msgstr "codul abj %d nu a fost găsit"
+
+#: vms-tir.c:2043
+#, c-format
+msgid "SEC_RELOC with no relocs in section %s"
+msgstr "SEC_RELOC fără relocări în secțiunea %s"
+
+#: vms-tir.c:2331
+#, c-format
+msgid "Unhandled relocation %s"
+msgstr "Relocare nemanipulabilă %s"
+
+#: xcofflink.c:1244
+#, c-format
+msgid "%s: `%s' has line numbers but no enclosing section"
+msgstr "%s: `%s' are numere de linii dar nici o secțiune de închidere"
+
+#: xcofflink.c:1297
+#, c-format
+msgid "%s: class %d symbol `%s' has no aux entries"
+msgstr "%s: clasa %d simbolul `%s' nu are intrări aux"
+
+#: xcofflink.c:1320
+#, c-format
+msgid "%s: symbol `%s' has unrecognized csect type %d"
+msgstr "%s: simbolul `%s' are tip necunoscut csect %d"
+
+#: xcofflink.c:1332
+#, c-format
+msgid "%s: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d"
+msgstr "%s: simbol XTY_ER invalid `%s': clasa %d scnum %d scnlen %d"
+
+#: xcofflink.c:1368
+#, c-format
+msgid "%s: XMC_TC0 symbol `%s' is class %d scnlen %d"
+msgstr "%s: simblul XMC_TC0 `%s' este clasa %d scnlen %d"
+
+#: xcofflink.c:1520
+#, c-format
+msgid "%s: csect `%s' not in enclosing section"
+msgstr "%s: csect `%s' nu este în secțiunea de închidere"
+
+#: xcofflink.c:1627
+#, c-format
+msgid "%s: misplaced XTY_LD `%s'"
+msgstr "%s:XTY_LD `%s' rătăcit"
+
+#: xcofflink.c:1958
+#, c-format
+msgid "%s: reloc %s:%d not in csect"
+msgstr "%s: relocarea %s:%d nu este în csect"
+
+#: xcofflink.c:2095
+#, c-format
+msgid "%s: XCOFF shared object when not producing XCOFF output"
+msgstr "%s: XCOFF shared object neproducând output XCOFF"
+
+#: xcofflink.c:2116
+#, c-format
+msgid "%s: dynamic object with no .loader section"
+msgstr "%s: obiect dinamic fără secțiune .loader"
+
+#: xcofflink.c:2761
+#, c-format
+msgid "%s: no such symbol"
+msgstr "%s: nu există acest simbol"
+
+#: xcofflink.c:2894
+msgid "error: undefined symbol __rtinit"
+msgstr "eroare: simbol __rtinit nedefinit"
+
+#: xcofflink.c:3455
+#, c-format
+msgid "warning: attempt to export undefined symbol `%s'"
+msgstr "avertisment: încercare de exportare a simbolului nedefinit `%s'"
+
+#: xcofflink.c:4448
+#, c-format
+msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling"
+msgstr "suprasolicitare(overflow) TOC: 0x%lx > 0x10000; încercați -mminimal-toc la compilare"
+
+#: xcofflink.c:5288 xcofflink.c:5755 xcofflink.c:5817 xcofflink.c:6119
+#, c-format
+msgid "%s: loader reloc in unrecognized section `%s'"
+msgstr "%s: relocare loader în secțiune necunoscută `%s'"
+
+#: xcofflink.c:5310 xcofflink.c:6130
+#, c-format
+msgid "%s: `%s' in loader reloc but not loader sym"
+msgstr "%s: `%s' în relocare loader dar nu în loader sym"
+
+#: xcofflink.c:5325
+#, c-format
+msgid "%s: loader reloc in read-only section %s"
+msgstr "%s: relocare loader în secțiunea doar-în-citire %s"
+
+#: elf32-ia64.c:2392 elf64-ia64.c:2392
+msgid "@pltoff reloc against local symbol"
+msgstr "relocare @pltoff pe simbol local"
+
+#: elf32-ia64.c:3804 elf64-ia64.c:3804
+#, c-format
+msgid "%s: short data segment overflowed (0x%lx >= 0x400000)"
+msgstr "%s: segment de date scurt depășit(overflowed) (0x%lx >= 0x400000)"
+
+#: elf32-ia64.c:3815 elf64-ia64.c:3815
+#, c-format
+msgid "%s: __gp does not cover short data segment"
+msgstr "%s: __gp nu acoperă segmentul de date scurte"
+
+#: elf32-ia64.c:4131 elf64-ia64.c:4131
+#, c-format
+msgid "%s: linking non-pic code in a shared library"
+msgstr "%s: linkuire cod non-pic într-o bibliotecă globală(shared)"
+
+#: elf32-ia64.c:4164 elf64-ia64.c:4164
+#, c-format
+msgid "%s: @gprel relocation against dynamic symbol %s"
+msgstr "%s: relocare @gprel pe simbolul dinamic %s"
+
+#: elf32-ia64.c:4224 elf64-ia64.c:4224
+#, c-format
+msgid "%s: linking non-pic code in a position independent executable"
+msgstr "%s: linkuire cod non-pic într-un executabil independent de poziție"
+
+#: elf32-ia64.c:4363 elf64-ia64.c:4363
+#, c-format
+msgid "%s: @internal branch to dynamic symbol %s"
+msgstr "%s: ramură @internal către simbolul dinamic %s"
+
+#: elf32-ia64.c:4365 elf64-ia64.c:4365
+#, c-format
+msgid "%s: speculation fixup to dynamic symbol %s"
+msgstr "%s: rezolvare de speculație către simbolul dinamic %s"
+
+#: elf32-ia64.c:4367 elf64-ia64.c:4367
+#, c-format
+msgid "%s: @pcrel relocation against dynamic symbol %s"
+msgstr "%s: relocare @pcrell pe simbolul dinamic %s"
+
+#: elf32-ia64.c:4579 elf64-ia64.c:4579
+msgid "unsupported reloc"
+msgstr "relocare nesuportată"
+
+#: elf32-ia64.c:4858 elf64-ia64.c:4858
+#, c-format
+msgid "%s: linking trap-on-NULL-dereference with non-trapping files"
+msgstr "%s: linkuire trap-on-NULL-dereference cu fișiere non-trapping"
+
+#: elf32-ia64.c:4867 elf64-ia64.c:4867
+#, c-format
+msgid "%s: linking big-endian files with little-endian files"
+msgstr "%s: linkuire fișiere big-endiancu fișiere little-endian"
+
+#: elf32-ia64.c:4876 elf64-ia64.c:4876
+#, c-format
+msgid "%s: linking 64-bit files with 32-bit files"
+msgstr "%s: linkuire fișiere pe 64-biți cu fișiere pe 32-biți"
+
+#: elf32-ia64.c:4885 elf64-ia64.c:4885
+#, c-format
+msgid "%s: linking constant-gp files with non-constant-gp files"
+msgstr "%s: linkuire fișiere constant-gp cu fișiere non-constant-gp"
+
+#: elf32-ia64.c:4895 elf64-ia64.c:4895
+#, c-format
+msgid "%s: linking auto-pic files with non-auto-pic files"
+msgstr "%s: linkuire fișiere auto-pic cu fișiere non-auto-pic"
+
+#: peigen.c:985 pepigen.c:985
+#, c-format
+msgid "%s: line number overflow: 0x%lx > 0xffff"
+msgstr "%s: depășire(overflow) număr linii: 0x%lx > 0xffff"
+
+#: peigen.c:1002 pepigen.c:1002
+#, c-format
+msgid "%s: reloc overflow 1: 0x%lx > 0xffff"
+msgstr "%s: depășire(overflow) relocare 1: 0x%lx > 0xffff"
+
+#: peigen.c:1016 pepigen.c:1016
+msgid "Export Directory [.edata (or where ever we found it)]"
+msgstr "Director Exportare [.edata (sau oriunde se găsește)]"
+
+#: peigen.c:1017 pepigen.c:1017
+msgid "Import Directory [parts of .idata]"
+msgstr "Director Importare [ părți ale .idata]"
+
+#: peigen.c:1018 pepigen.c:1018
+msgid "Resource Directory [.rsrc]"
+msgstr "Director Resursă [.rsrc]"
+
+#: peigen.c:1019 pepigen.c:1019
+msgid "Exception Directory [.pdata]"
+msgstr "Director Excepție [.pdata]"
+
+#: peigen.c:1020 pepigen.c:1020
+msgid "Security Directory"
+msgstr "Director Securitate"
+
+#: peigen.c:1021 pepigen.c:1021
+msgid "Base Relocation Directory [.reloc]"
+msgstr "Director Relocare de Bază [.reloc]"
+
+#: peigen.c:1022 pepigen.c:1022
+msgid "Debug Directory"
+msgstr "Director Debug"
+
+#: peigen.c:1023 pepigen.c:1023
+msgid "Description Directory"
+msgstr "Director Descriere"
+
+#: peigen.c:1024 pepigen.c:1024
+msgid "Special Directory"
+msgstr "Director Special"
+
+#: peigen.c:1025 pepigen.c:1025
+msgid "Thread Storage Directory [.tls]"
+msgstr "Director Depozitare Fire(Thread) [.tls]"
+
+#: peigen.c:1026 pepigen.c:1026
+msgid "Load Configuration Directory"
+msgstr "Director Încărcare Configurație"
+
+#: peigen.c:1027 pepigen.c:1027
+msgid "Bound Import Directory"
+msgstr "Director Importare de Graniță(Bound)"
+
+#: peigen.c:1028 pepigen.c:1028
+msgid "Import Address Table Directory"
+msgstr "Director Importare Tabelă de Adrese"
+
+#: peigen.c:1029 pepigen.c:1029
+msgid "Delay Import Directory"
+msgstr "Director Importare Întârziere"
+
+#: peigen.c:1030 peigen.c:1031 pepigen.c:1030 pepigen.c:1031
+msgid "Reserved"
+msgstr "Rezervat"
+
+#: peigen.c:1094 pepigen.c:1094
+msgid ""
+"\n"
+"There is an import table, but the section containing it could not be found\n"
+msgstr ""
+"\n"
+"Există o tabelă de importare, dar secțiunea care o conține n-a putut fi găsită\n"
+
+#: peigen.c:1099 pepigen.c:1099
+#, c-format
+msgid ""
+"\n"
+"There is an import table in %s at 0x%lx\n"
+msgstr ""
+"\n"
+"Există o tabelă de importare în %s la 0x%lx\n"
+
+#: peigen.c:1136 pepigen.c:1136
+#, c-format
+msgid ""
+"\n"
+"Function descriptor located at the start address: %04lx\n"
+msgstr ""
+"\n"
+"Descriptorul de funcție localizat la adresa de start: %04lx\n"
+
+#: peigen.c:1139 pepigen.c:1139
+#, c-format
+msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n"
+msgstr "\tcode-base %08lx toc (încărcabil/actual) %08lx/%08lx\n"
+
+#: peigen.c:1145 pepigen.c:1145
+msgid ""
+"\n"
+"No reldata section! Function descriptor not decoded.\n"
+msgstr ""
+"\n"
+"Nu există secțiune reldata! Descriptorul de funcție nu este decodat.\n"
+
+#: peigen.c:1150 pepigen.c:1150
+#, c-format
+msgid ""
+"\n"
+"The Import Tables (interpreted %s section contents)\n"
+msgstr ""
+"\n"
+"Tabelele de Importare (interpretat conținutul secțiunii %s)\n"
+
+#: peigen.c:1153 pepigen.c:1153
+msgid ""
+" vma:            Hint    Time      Forward  DLL       First\n"
+"                 Table   Stamp     Chain    Name      Thunk\n"
+msgstr ""
+" vma:          Sugestie   Timp      Înaintare  DLL     Primul\n"
+"                 Tabel   Marcaj     Lanț    Nume      Thunk\n"
+
+#: peigen.c:1204 pepigen.c:1204
+#, c-format
+msgid ""
+"\n"
+"\tDLL Name: %s\n"
+msgstr ""
+"\n"
+"\tNume DLL: %s\n"
+
+#: peigen.c:1215 pepigen.c:1215
+msgid "\tvma:  Hint/Ord Member-Name Bound-To\n"
+msgstr "\tvma:  Sugestie/Ord Membru-Nume Salt-La\n"
+
+#: peigen.c:1240 pepigen.c:1240
+msgid ""
+"\n"
+"There is a first thunk, but the section containing it could not be found\n"
+msgstr ""
+"\n"
+"Există un prim thunk, dar secțiunea care îl conține nu poate fi găsită\n"
+
+#: peigen.c:1380 pepigen.c:1380
+msgid ""
+"\n"
+"There is an export table, but the section containing it could not be found\n"
+msgstr ""
+"\n"
+"Există o tabelă de export, dar secțiunea ce o conține nu poate fi găsită\n"
+
+#: peigen.c:1385 pepigen.c:1385
+#, c-format
+msgid ""
+"\n"
+"There is an export table in %s at 0x%lx\n"
+msgstr ""
+"\n"
+"Există o tabelă de exportare în %s la 0x%lx\n"
+
+#: peigen.c:1416 pepigen.c:1416
+#, c-format
+msgid ""
+"\n"
+"The Export Tables (interpreted %s section contents)\n"
+"\n"
+msgstr ""
+"\n"
+"Tabelele de Exportare (interpretare conținut secțiune %s)\n"
+"\n"
+
+#: peigen.c:1420 pepigen.c:1420
+#, c-format
+msgid "Export Flags \t\t\t%lx\n"
+msgstr "Marcaje(Flags) Exportare \t\t\t%lx\n"
+
+#: peigen.c:1423 pepigen.c:1423
+#, c-format
+msgid "Time/Date stamp \t\t%lx\n"
+msgstr "Marcaj(stamp) Oră/Dată \t\t%lx\n"
+
+#: peigen.c:1426 pepigen.c:1426
+#, c-format
+msgid "Major/Minor \t\t\t%d/%d\n"
+msgstr "Major/Minor \t\t\t%d/%d\n"
+
+#: peigen.c:1429 pepigen.c:1429
+msgid "Name \t\t\t\t"
+msgstr "Nume \t\t\t\t"
+
+#: peigen.c:1435 pepigen.c:1435
+#, c-format
+msgid "Ordinal Base \t\t\t%ld\n"
+msgstr "Bază Ordinală \t\t\t%ld\n"
+
+#: peigen.c:1438 pepigen.c:1438
+msgid "Number in:\n"
+msgstr "Număr în:\n"
+
+#: peigen.c:1441 pepigen.c:1441
+#, c-format
+msgid "\tExport Address Table \t\t%08lx\n"
+msgstr "\t Tabelă Exportare Adrese \t\t%08lx\n"
+
+#: peigen.c:1445 pepigen.c:1445
+#, c-format
+msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n"
+msgstr "\tTabelă [Nume Pointer/Ordinal]\t%08lx\n"
+
+#: peigen.c:1448 pepigen.c:1448
+msgid "Table Addresses\n"
+msgstr "Adrese Tabelă\n"
+
+#: peigen.c:1451 pepigen.c:1451
+msgid "\tExport Address Table \t\t"
+msgstr "\tTabelă Exportare de Adrese \t\t"
+
+#: peigen.c:1456 pepigen.c:1456
+msgid "\tName Pointer Table \t\t"
+msgstr "\tNume Pointer Tabelă \t\t"
+
+#: peigen.c:1461 pepigen.c:1461
+msgid "\tOrdinal Table \t\t\t"
+msgstr "\tOrdinal Tabelă \t\t\t"
+
+#: peigen.c:1476 pepigen.c:1476
+#, c-format
+msgid ""
+"\n"
+"Export Address Table -- Ordinal Base %ld\n"
+msgstr ""
+"\n"
+"Tabelă Exportare de Adrese -- Bază Ordinală %ld\n"
+
+#: peigen.c:1495 pepigen.c:1495
+msgid "Forwarder RVA"
+msgstr "Trimițător(Forwarder) RVA"
+
+#: peigen.c:1506 pepigen.c:1506
+msgid "Export RVA"
+msgstr "Exportare RVA"
+
+#: peigen.c:1513 pepigen.c:1513
+msgid ""
+"\n"
+"[Ordinal/Name Pointer] Table\n"
+msgstr ""
+"\n"
+"[Ordinal/Nume Pointer] Tabelă\n"
+
+#: peigen.c:1568 pepigen.c:1568
+#, c-format
+msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n"
+msgstr "Avertisment, mărimea secțiunii .pdata (%ld) nu este multiplu de %d\n"
+
+#: peigen.c:1572 pepigen.c:1572
+msgid ""
+"\n"
+"The Function Table (interpreted .pdata section contents)\n"
+msgstr ""
+"\n"
+"Tabela de Funcții (interpretare conținut secțiune .pdata)\n"
+
+#: peigen.c:1575 pepigen.c:1575
+msgid " vma:\t\t\tBegin Address    End Address      Unwind Info\n"
+msgstr " vma:\t\t\tAdresă Început    Adresă Sfârșit      Info Unwind\n"
+
+#: peigen.c:1577 pepigen.c:1577
+msgid ""
+" vma:\t\tBegin    End      EH       EH       PrologEnd  Exception\n"
+"     \t\tAddress  Address  Handler  Data     Address    Mask\n"
+msgstr ""
+" vma:\t\tÎnceput    Sfârșit    EH     EH     PrologSfârșit  Excepții\n"
+"     \t\tAdresă  Adresă  Manipulant  Date   Adresă    Mască\n"
+
+#: peigen.c:1647 pepigen.c:1647
+msgid " Register save millicode"
+msgstr " Registrul salvează millicode "
+
+#: peigen.c:1650 pepigen.c:1650
+msgid " Register restore millicode"
+msgstr "Registrul reface millicode"
+
+#: peigen.c:1653 pepigen.c:1653
+msgid " Glue code sequence"
+msgstr "Secvență de cod lipită(glue)"
+
+#: peigen.c:1705 pepigen.c:1705
+msgid ""
+"\n"
+"\n"
+"PE File Base Relocations (interpreted .reloc section contents)\n"
+msgstr ""
+"\n"
+"\n"
+"Relocări Bază Fișier PE (interpretare conținut secțiune .reloc)\n"
+
+#: peigen.c:1735 pepigen.c:1735
+#, c-format
+msgid ""
+"\n"
+"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n"
+msgstr ""
+"\n"
+"Adresă Virtuală: %08lx Mărime Trunchiere %ld (0x%lx) Număr acceptări %ld\n"
+
+#: peigen.c:1748 pepigen.c:1748
+#, c-format
+msgid "\treloc %4d offset %4x [%4lx] %s"
+msgstr "\trelocarea %4d offset %4x [%4lx] %s"
+
+#. The MS dumpbin program reportedly ands with 0xff0f before
+#. printing the characteristics field.  Not sure why.  No reason to
+#. emulate it here.
+#: peigen.c:1788 pepigen.c:1788
+#, c-format
+msgid ""
+"\n"
+"Characteristics 0x%x\n"
+msgstr ""
+"\n"
+"Caracteristici 0x%x\n"
+
+#~ msgid "%s: Unknown special linker type %d"
+#~ msgstr "%s: Tip special necunoscut de linker %d"
+
+#~ msgid "v850ea architecture"
+#~ msgstr "arhitectură v850ea"
+
+#~ msgid "%s: Section %s is too large to add hole of %ld bytes"
+#~ msgstr "%s: Secțiunea %s este prea mare pentru a adăuga o gaură de %ld octeți"
+
+#~ msgid "Error: out of memory"
+#~ msgstr "Eroare: memorie plină"
+
+#~ msgid "warning: relocation against removed section; zeroing"
+#~ msgstr "avertisment: relocare pe secțiune eliminată; se umple cu zero(zeroing)"
+
+#~ msgid "warning: relocation against removed section"
+#~ msgstr "avertisment: relocare pe secțiune eliminată"
+
+#~ msgid "local symbols in discarded section %s"
+#~ msgstr "simboluri locale în secțiunea îndepărtată(discarded) %s"
+
+#~ msgid "%s: linking abicalls files with non-abicalls files"
+#~ msgstr "%s: linkuire fișiere abicalls cu fișiere non-abicalls"
+
+#~ msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)"
+#~ msgstr "%s: nepotrivire ISA (-mips%d) cu modulele anterioare (-mips%d)"
+
+#~ msgid "%s: ISA mismatch (%d) with previous modules (%d)"
+#~ msgstr "%s: nepotrivire ISA (%d) cu modulele anterioare (%d)"
+
+#~ msgid "%s: dynamic relocation against speculation fixup"
+#~ msgstr "%s: relocare dinamică pe acceptare(fixup) speculativă"
+
+#~ msgid "%s: speculation fixup against undefined weak symbol"
+#~ msgstr "%s: speculație acceptare(fixup) pe simbol ambiguu(weak) nedefinit"
diff --git a/gdb/config/arm/tm-nbsd.h b/gdb/config/arm/tm-nbsd.h
new file mode 100644
index 0000000..97bca68
--- /dev/null
+++ b/gdb/config/arm/tm-nbsd.h
@@ -0,0 +1,26 @@
+/* Macro definitions for ARM running under NetBSD.
+   Copyright 2003 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+#ifndef TM_NBSD_H
+#define TM_NBSD_H
+
+#include "solib.h"
+
+#endif /* TM_NBSD_H */
diff --git a/gdb/libunwind-frame.c b/gdb/libunwind-frame.c
new file mode 100644
index 0000000..bf0c36d
--- /dev/null
+++ b/gdb/libunwind-frame.c
@@ -0,0 +1,387 @@
+/* Frame unwinder for frames using the libunwind library.
+
+   Copyright 2003 Free Software Foundation, Inc.
+
+   Written by Jeff Johnston, contributed by Red Hat Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+#include "defs.h"
+
+#include "inferior.h"
+#include "frame.h"
+#include "frame-base.h"
+#include "frame-unwind.h"
+#include "gdbcore.h"
+#include "gdbtypes.h"
+#include "symtab.h"
+#include "objfiles.h"
+#include "regcache.h"
+
+#include <dlfcn.h>
+
+#include "gdb_assert.h"
+#include "gdb_string.h"
+
+#include "libunwind-frame.h"
+
+#include "complaints.h"
+
+static int libunwind_initialized;
+static struct gdbarch_data *libunwind_descr_handle;
+
+#ifndef LIBUNWIND_SO
+#define LIBUNWIND_SO "libunwind.so"
+#endif
+
+/* Required function pointers from libunwind.  */
+static int (*unw_get_reg_p) (unw_cursor_t *, unw_regnum_t, unw_word_t *);
+static int (*unw_get_fpreg_p) (unw_cursor_t *, unw_regnum_t, unw_fpreg_t *);
+static int (*unw_get_saveloc_p) (unw_cursor_t *, unw_regnum_t, unw_save_loc_t *);
+static int (*unw_step_p) (unw_cursor_t *);
+static int (*unw_init_remote_p) (unw_cursor_t *, unw_addr_space_t, void *);
+static unw_addr_space_t (*unw_create_addr_space_p) (unw_accessors_t *, int);
+static int (*unw_search_unwind_table_p) (unw_addr_space_t, unw_word_t, unw_dyn_info_t *,
+					 unw_proc_info_t *, int, void *);
+static unw_word_t (*unw_find_dyn_list_p) (unw_addr_space_t, unw_dyn_info_t *,
+					  void *);
+
+
+struct libunwind_frame_cache
+{
+  CORE_ADDR base;
+  CORE_ADDR func_addr;
+  unw_cursor_t cursor;
+};
+
+/* We need to qualify the function names with a platform-specific prefix to match 
+   the names used by the libunwind library.  The UNW_OBJ macro is provided by the
+   libunwind.h header file.  */
+#define STRINGIFY2(name)	#name
+#define STRINGIFY(name)		STRINGIFY2(name)
+
+static char *get_reg_name = STRINGIFY(UNW_OBJ(get_reg));
+static char *get_fpreg_name = STRINGIFY(UNW_OBJ(get_fpreg));
+static char *get_saveloc_name = STRINGIFY(UNW_OBJ(get_save_loc));
+static char *step_name = STRINGIFY(UNW_OBJ(step));
+static char *init_remote_name = STRINGIFY(UNW_OBJ(init_remote));
+static char *create_addr_space_name = STRINGIFY(UNW_OBJ(create_addr_space));
+static char *search_unwind_table_name = STRINGIFY(UNW_OBJ(search_unwind_table));
+static char *find_dyn_list_name = STRINGIFY(UNW_OBJ(find_dyn_list));
+
+static struct libunwind_descr *
+libunwind_descr (struct gdbarch *gdbarch)
+{
+  return gdbarch_data (gdbarch, libunwind_descr_handle);
+}
+
+static void *
+libunwind_descr_init (struct gdbarch *gdbarch)
+{
+  struct libunwind_descr *descr = GDBARCH_OBSTACK_ZALLOC (gdbarch,
+							  struct libunwind_descr);
+  return descr;
+}
+
+void
+libunwind_frame_set_descr (struct gdbarch *gdbarch, struct libunwind_descr *descr)
+{
+  struct libunwind_descr *arch_descr;
+
+  gdb_assert (gdbarch != NULL);
+
+  arch_descr = gdbarch_data (gdbarch, libunwind_descr_handle);
+
+  if (arch_descr == NULL)
+    {
+      /* First time here.  Must initialize data area.  */
+      arch_descr = libunwind_descr_init (gdbarch);
+      set_gdbarch_data (gdbarch, libunwind_descr_handle, arch_descr);
+    }
+
+  /* Copy new descriptor info into arch descriptor.  */
+  arch_descr->gdb2uw = descr->gdb2uw;
+  arch_descr->uw2gdb = descr->uw2gdb;
+  arch_descr->is_fpreg = descr->is_fpreg;
+  arch_descr->accessors = descr->accessors;
+}
+
+static struct libunwind_frame_cache *
+libunwind_frame_cache (struct frame_info *next_frame, void **this_cache)
+{
+  unw_accessors_t *acc;
+  unw_addr_space_t as;
+  unw_word_t fp;
+  unw_regnum_t uw_sp_regnum;
+  struct libunwind_frame_cache *cache;
+  struct libunwind_descr *descr;
+  int i, ret;
+
+  if (*this_cache)
+    return *this_cache;
+
+  /* Allocate a new cache.  */
+  cache = FRAME_OBSTACK_ZALLOC (struct libunwind_frame_cache);
+
+  cache->func_addr = frame_func_unwind (next_frame);
+
+  /* Get a libunwind cursor to the previous frame.  We do this by initializing
+     a cursor.  Libunwind treats a new cursor as the top of stack and will get
+     the current register set via the libunwind register accessor.  Now, we
+     provide the platform-specific accessors and we set up the register accessor to use
+     the frame register unwinding interfaces so that we properly get the registers for
+     the current frame rather than the top.  We then use the  unw_step function to 
+     move the libunwind cursor back one frame.  We can later use this cursor to find previous 
+     registers via the unw_get_reg interface which will invoke libunwind's special logic.  */
+  descr = libunwind_descr (get_frame_arch (next_frame));
+  acc = descr->accessors;
+  as =  unw_create_addr_space_p (acc,
+				 TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
+				 ? __BIG_ENDIAN
+				 : __LITTLE_ENDIAN);
+
+  unw_init_remote_p (&cache->cursor, as, next_frame);
+  unw_step_p (&cache->cursor);
+
+  /* To get base address, get sp from previous frame.  */
+  uw_sp_regnum = descr->gdb2uw (SP_REGNUM);
+  ret = unw_get_reg_p (&cache->cursor, uw_sp_regnum, &fp);
+  if (ret < 0)
+    error ("Can't get libunwind sp register.");
+
+  cache->base = (CORE_ADDR)fp;
+
+  *this_cache = cache;
+  return cache;
+}
+
+unw_word_t
+libunwind_find_dyn_list (unw_addr_space_t as, unw_dyn_info_t *di, void *arg)
+{
+  return unw_find_dyn_list_p (as, di, arg);
+}
+
+static const struct frame_unwind libunwind_frame_unwind =
+{
+  NORMAL_FRAME,
+  libunwind_frame_this_id,
+  libunwind_frame_prev_register
+};
+
+/* Verify if there is sufficient libunwind information for the frame to use
+   libunwind frame unwinding.  */
+const struct frame_unwind *
+libunwind_frame_sniffer (struct frame_info *next_frame)
+{
+  unw_cursor_t cursor;
+  unw_accessors_t *acc;
+  unw_addr_space_t as;
+  struct libunwind_descr *descr;
+  int i, ret;
+
+  /* To test for libunwind unwind support, initialize a cursor to the current frame and try to back
+     up.  We use this same method when setting up the frame cache (see libunwind_frame_cache()).
+     If libunwind returns success for this operation, it means that it has found sufficient
+     libunwind unwinding information to do so.  */
+
+  descr = libunwind_descr (get_frame_arch (next_frame));
+  acc = descr->accessors;
+  as =  unw_create_addr_space_p (acc,
+				 TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
+				 ? __BIG_ENDIAN
+				 : __LITTLE_ENDIAN);
+
+  ret = unw_init_remote_p (&cursor, as, next_frame);
+
+  if (ret >= 0)
+    ret = unw_step_p (&cursor);
+
+  if (ret < 0)
+    return NULL;
+
+  return &libunwind_frame_unwind;
+}
+
+void
+libunwind_frame_this_id (struct frame_info *next_frame, void **this_cache,
+		      struct frame_id *this_id)
+{
+  struct libunwind_frame_cache *cache =
+    libunwind_frame_cache (next_frame, this_cache);
+
+  (*this_id) = frame_id_build (cache->base, cache->func_addr);
+}
+
+void
+libunwind_frame_prev_register (struct frame_info *next_frame, void **this_cache,
+			       int regnum, int *optimizedp,
+			       enum lval_type *lvalp, CORE_ADDR *addrp,
+			       int *realnump, void *valuep)
+{
+  struct libunwind_frame_cache *cache =
+    libunwind_frame_cache (next_frame, this_cache);
+
+  void *ptr;
+  unw_cursor_t *c;
+  unw_save_loc_t sl;
+  int i, ret;
+  unw_word_t intval;
+  unw_fpreg_t fpval;
+  unw_regnum_t uw_regnum;
+  struct libunwind_descr *descr;
+
+  /* Convert from gdb register number to libunwind register number.  */
+  descr = libunwind_descr (get_frame_arch (next_frame));
+  uw_regnum = descr->gdb2uw (regnum);
+
+  gdb_assert (regnum >= 0);
+
+  if (!target_has_registers)
+    error ("No registers.");
+
+  *optimizedp = 0;
+  *addrp = 0;
+  *lvalp = not_lval;
+  *realnump = -1;
+
+  memset (valuep, 0, register_size (current_gdbarch, regnum));
+
+  if (uw_regnum < 0)
+    return;
+
+  /* To get the previous register, we use the libunwind register APIs with
+     the cursor we have already pushed back to the previous frame.  */
+
+  if (descr->is_fpreg (uw_regnum))
+    {
+      ret = unw_get_fpreg_p (&cache->cursor, uw_regnum, &fpval);
+      ptr = &fpval;
+    }
+  else
+    {
+      ret = unw_get_reg_p (&cache->cursor, uw_regnum, &intval);
+      ptr = &intval;
+    }
+
+  if (ret < 0)
+    return;
+
+  memcpy (valuep, ptr, register_size (current_gdbarch, regnum));
+
+  if (unw_get_saveloc_p (&cache->cursor, uw_regnum, &sl) < 0)
+    return;
+
+  switch (sl.type)
+    {
+    case UNW_SLT_NONE:
+      *optimizedp = 1;
+      break;
+
+    case UNW_SLT_MEMORY:
+      *lvalp = lval_memory;
+      *addrp = sl.u.addr;
+      break;
+
+    case UNW_SLT_REG:
+      *lvalp = lval_register;
+      *realnump = regnum;
+      break;
+    }
+} 
+
+CORE_ADDR
+libunwind_frame_base_address (struct frame_info *next_frame, void **this_cache)
+{
+  struct libunwind_frame_cache *cache =
+    libunwind_frame_cache (next_frame, this_cache);
+
+  return cache->base;
+}
+
+/* The following is a glue routine to call the libunwind unwind table
+   search function to get unwind information for a specified ip address.  */ 
+int
+libunwind_search_unwind_table (void *as, long ip, void *di,
+			       void *pi, int need_unwind_info, void *args)
+{
+  return unw_search_unwind_table_p (*(unw_addr_space_t *)as, (unw_word_t )ip, 
+				    di, pi, need_unwind_info, args);
+}
+
+static int
+libunwind_load (void)
+{
+  void *handle;
+
+  handle = dlopen (LIBUNWIND_SO, RTLD_NOW);
+  if (handle == NULL)
+    return 0;
+
+  /* Initialize pointers to the dynamic library functions we will use.  */
+
+  unw_get_reg_p = dlsym (handle, get_reg_name);
+  if (unw_get_reg_p == NULL)
+    return 0;
+
+  unw_get_fpreg_p = dlsym (handle, get_fpreg_name);
+  if (unw_get_fpreg_p == NULL)
+    return 0;
+
+  unw_get_saveloc_p = dlsym (handle, get_saveloc_name);
+  if (unw_get_saveloc_p == NULL)
+    return 0;
+
+  unw_step_p = dlsym (handle, step_name);
+  if (unw_step_p == NULL)
+    return 0;
+
+  unw_init_remote_p = dlsym (handle, init_remote_name);
+  if (unw_init_remote_p == NULL)
+    return 0;
+
+  unw_create_addr_space_p = dlsym (handle, create_addr_space_name);
+  if (unw_create_addr_space_p == NULL)
+    return 0;
+
+  unw_search_unwind_table_p = dlsym (handle, search_unwind_table_name);
+  if (unw_search_unwind_table_p == NULL)
+    return 0;
+
+  unw_find_dyn_list_p = dlsym (handle, find_dyn_list_name);
+  if (unw_find_dyn_list_p == NULL)
+    return 0;
+   
+  return 1;
+}
+
+int
+libunwind_is_initialized (void)
+{
+  return libunwind_initialized;
+}
+
+/* Provide a prototype to silence -Wmissing-prototypes.  */
+void _initialize_libunwind_frame (void);
+
+void
+_initialize_libunwind_frame (void)
+{
+  libunwind_descr_handle = register_gdbarch_data (libunwind_descr_init);
+
+  libunwind_initialized = libunwind_load ();
+}
diff --git a/gdb/libunwind-frame.h b/gdb/libunwind-frame.h
new file mode 100644
index 0000000..bacdf87
--- /dev/null
+++ b/gdb/libunwind-frame.h
@@ -0,0 +1,63 @@
+/* Frame unwinder for frames with libunwind frame information.
+
+   Copyright 2003 Free Software Foundation, Inc.
+
+   Contributed by Jeff Johnston.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+#ifdef HAVE_LIBUNWIND_H
+
+#ifndef LIBUNWIND_FRAME_H
+#define LIBUNWIND_FRAME_H 1
+
+#include "libunwind.h"
+
+struct frame_info;
+
+struct libunwind_descr
+{
+  int (*gdb2uw) (int);
+  int (*uw2gdb) (int);
+  int (*is_fpreg) (int);
+  void *accessors;
+};
+
+const struct frame_unwind *libunwind_frame_sniffer (struct frame_info *next_frame);
+
+void libunwind_frame_set_descr (struct gdbarch *arch, struct libunwind_descr *descr);
+
+void libunwind_frame_this_id (struct frame_info *next_frame, void **this_cache,
+			      struct frame_id *this_id);
+void libunwind_frame_prev_register (struct frame_info *next_frame, void **this_cache,
+				    int regnum, int *optimizedp,
+				    enum lval_type *lvalp, CORE_ADDR *addrp,
+				    int *realnump, void *valuep);
+CORE_ADDR libunwind_frame_base_address (struct frame_info *next_frame, void **this_cache);
+
+int libunwind_is_initialized (void);
+
+int libunwind_search_unwind_table (void *as, long ip, void *di,
+				   void *pi, int need_unwind_info, void *args);
+
+unw_word_t libunwind_find_dyn_list (unw_addr_space_t, unw_dyn_info_t *,
+				    void *);
+
+#endif /* libunwind-frame.h */
+
+#endif /* HAVE_LIBUNWIND_H  */
diff --git a/gdb/testsuite/gdb.arch/i386-unwind.c b/gdb/testsuite/gdb.arch/i386-unwind.c
new file mode 100644
index 0000000..6d10ecb
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/i386-unwind.c
@@ -0,0 +1,42 @@
+/* Unwinder test program.
+
+   Copyright 2003 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+void
+trap (void)
+{
+  asm ("int $0x03");
+}
+
+/* Make sure that main directly follows a function without an
+   epilogue.  */
+
+asm(".text\n"
+    "    .align 8\n"
+    "    .globl gdb1435\n"
+    "gdb1435:\n"
+    "    pushl %ebp\n"
+    "    mov   %esp, %ebp\n"
+    "    call  trap\n"
+    "    .globl main\n"
+    "main:\n"
+    "    pushl %ebp\n"
+    "    mov   %esp, %ebp\n"
+    "    call  gdb1435\n");
diff --git a/gdb/testsuite/gdb.arch/i386-unwind.exp b/gdb/testsuite/gdb.arch/i386-unwind.exp
new file mode 100644
index 0000000..9c3130f
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/i386-unwind.exp
@@ -0,0 +1,68 @@
+# Copyright 2003 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+
+# Please email any bugs, comments, and/or additions to this file to:
+# bug-gdb@gnu.org
+
+# This file is part of the gdb testsuite.
+
+if $tracelevel {
+    strace $tracelevel
+}
+
+# Test i386 unwinder.
+
+set prms_id 0
+set bug_id 0
+
+if ![istarget "i?86-*-*"] then {
+    verbose "Skipping i386 unwinder tests."
+    return
+}
+
+set testfile "i386-unwind"
+set srcfile ${testfile}.c
+set binfile ${objdir}/${subdir}/${testfile}
+if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}] != "" } {
+    gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail."
+}
+
+gdb_exit
+gdb_start
+gdb_reinitialize_dir $srcdir/$subdir
+gdb_load ${binfile}
+
+# Testcase for backtrace/1435.
+
+# We use gdb_run_cmd so this stands a chance to work for remote
+# targets too.
+gdb_run_cmd
+
+gdb_expect {
+    -re "Program received signal SIGTRAP.*$gdb_prompt $" {
+	pass "run past gdb1435"
+    }
+    -re ".*$gdb_prompt $" {
+	fail "run past gdb1435"
+    }
+    timeout {
+	fail "run past gdb1435 (timeout)"
+    }
+}
+
+gdb_test "backtrace 10" \
+	"#1\[ \t]*$hex in gdb1435.*\r\n#2\[ \t\]*$hex in main.*" \
+	"backtrace past gdb1435"
diff --git a/gdb/testsuite/gdb.asm/empty.inc b/gdb/testsuite/gdb.asm/empty.inc
new file mode 100644
index 0000000..e786488
--- /dev/null
+++ b/gdb/testsuite/gdb.asm/empty.inc
@@ -0,0 +1 @@
+	comment "empty"
diff --git a/gdb/testsuite/gdb.asm/frv.inc b/gdb/testsuite/gdb.asm/frv.inc
new file mode 100644
index 0000000..e8f3b8f
--- /dev/null
+++ b/gdb/testsuite/gdb.asm/frv.inc
@@ -0,0 +1,54 @@
+	comment "subroutine prologue"
+	.macro gdbasm_enter
+	addi sp,#-16,sp
+	sti fp, @(sp,0)
+	mov sp, fp
+	movsg lr, gr5
+	sti gr5, @(fp,8)
+	.endm
+
+	comment "subroutine epilogue"
+	.macro gdbasm_leave
+	ldi @(fp,8), gr5
+	ld @(fp,gr0), fp
+	addi sp,#16,sp
+	jmpl @(gr5,gr0)
+	.endm
+
+	.macro gdbasm_call subr
+	call \subr
+	.endm
+
+	.macro gdbasm_several_nops
+	nop
+	nop
+	nop
+	nop
+	.endm
+
+	comment "exit (0)"
+	.macro gdbasm_exit0
+	comment "Don't know how to exit, but this will certainly halt..."
+	ldi @(gr0,0), gr5
+	.endm
+
+	comment "crt0 startup"
+	.macro gdbasm_startup
+	call	.Lcall
+.Lcall:	movsg	lr, gr4
+	sethi   #gprelhi(.Lcall), gr5
+	setlo	#gprello(.Lcall), gr5
+	sub	 gr4, gr5, gr16
+
+	sethi	 #gprelhi(_stack), sp
+	setlo    #gprello(_stack), sp
+	setlos   #0, fp
+	add	 sp, gr16, sp
+	.endm
+
+	comment "Declare a data variable"
+	.macro gdbasm_datavar name value
+	.data
+\name:
+	.long	\value
+	.endm
diff --git a/gdb/testsuite/gdb.asm/netbsd.inc b/gdb/testsuite/gdb.asm/netbsd.inc
new file mode 100644
index 0000000..9446966
--- /dev/null
+++ b/gdb/testsuite/gdb.asm/netbsd.inc
@@ -0,0 +1,12 @@
+	comment "netbsd .note"
+
+.section	".note.netbsd.ident", "a"
+	.p2align	2
+
+	.long	7
+	.long	4
+	.long	1
+	.ascii	"NetBSD\0\0"
+	.long	105010000
+
+	.p2align	2
diff --git a/gdb/testsuite/gdb.base/break1.c b/gdb/testsuite/gdb.base/break1.c
new file mode 100644
index 0000000..2ed8b2a
--- /dev/null
+++ b/gdb/testsuite/gdb.base/break1.c
@@ -0,0 +1,44 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+   Copyright 1992, 1993, 1994, 1995, 1999, 2002, 2003 Free Software
+   Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+ 
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+   Please email any bugs, comments, and/or additions to this file to:
+   bug-gdb@prep.ai.mit.edu  */
+
+/* The code for this file was extracted from the gdb testsuite
+   testcase "break.c". */
+
+/* The following functions do nothing useful.  They are included
+   simply as places to try setting breakpoints at.  They are
+   explicitly "one-line functions" to verify that this case works
+   (some versions of gcc have or have had problems with this).
+  
+   These functions are in a separate source file to prevent an
+   optimizing compiler from inlining them and optimizing them away. */
+
+#ifdef PROTOTYPES
+int marker1 (void) { return (0); }	/* set breakpoint 15 here */
+int marker2 (int a) { return (1); }	/* set breakpoint 8 here */
+void marker3 (char *a, char *b) {}	/* set breakpoint 17 here */
+void marker4 (long d) {}		/* set breakpoint 14 here */
+#else
+int marker1 () { return (0); }		/* set breakpoint 16 here */
+int marker2 (a) int a; { return (1); }	/* set breakpoint 9 here */
+void marker3 (a, b) char *a, *b; {}	/* set breakpoint 18 here */
+void marker4 (d) long d; {}		/* set breakpoint 13 here */
+#endif
diff --git a/gdb/testsuite/gdb.base/freebpcmd.c b/gdb/testsuite/gdb.base/freebpcmd.c
new file mode 100644
index 0000000..52d9f30
--- /dev/null
+++ b/gdb/testsuite/gdb.base/freebpcmd.c
@@ -0,0 +1,15 @@
+int
+main (int argc, char **argv)
+{
+  int i;
+
+#ifdef usestubs
+  set_debug_traps();
+  breakpoint();
+#endif
+
+  for (i = 0; i < 100; i++)
+    printf (">>> %d\n", i); /* euphonium */
+
+  return 0;
+}
diff --git a/gdb/testsuite/gdb.base/freebpcmd.exp b/gdb/testsuite/gdb.base/freebpcmd.exp
new file mode 100644
index 0000000..f952139
--- /dev/null
+++ b/gdb/testsuite/gdb.base/freebpcmd.exp
@@ -0,0 +1,121 @@
+#   Copyright 2003 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+
+
+# This is a regression test for the following bug, as of 2003-12-12:
+#
+# Set a breakpoint which will be hit many times.  Attach a complex set
+# of commands to it, including a "continue" command.  Run the program,
+# so that the breakpoint is hit, its commands get executed, and the
+# program continues and hits the breakpoint again.  You will see
+# messages like "warning: Invalid control type in command structure.",
+# or maybe GDB will crash.
+#
+# When the breakpoint is hit, bpstat_stop_status copies the
+# breakpoint's command tree to the bpstat.  bpstat_do_actions then
+# calls execute_control_command to run the commands.  The 'continue'
+# command invokes the following chain of calls:
+#
+#   continue_command
+#     -> clear_proceed_status
+#       -> bpstat_clear
+#         -> free_command_lines
+#            -> frees the commands we are currently running.
+#
+# When control does eventually return to execute_control_command, GDB
+# continues to walk the tree of freed command nodes, resulting in the
+# error messages and / or crashes.
+#
+# Since this bug depends on storage being reused between the time that
+# we continue and the time that we fall back to bpstat_do_actions, the
+# reproduction recipe is more delicate than I would like.  I welcome
+# suggestions for improving this.
+
+set prms_id 0
+set bug_id 0
+
+set testfile "freebpcmd"
+set srcfile ${testfile}.c
+set srcfile1 ${testfile}1.c
+set binfile ${objdir}/${subdir}/${testfile}
+
+if  { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug}] != "" } {
+     gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail."
+}
+
+gdb_exit
+gdb_start
+gdb_reinitialize_dir $srcdir/$subdir
+gdb_load ${binfile}
+
+gdb_test "break [gdb_get_line_number "euphonium"]" "" "set breakpoint"
+
+# The goal of all this is to make sure that there's plenty of memory
+# churn, and different amounts of it each time the inferior stops;
+# this seems to make GDB crash more reliably.
+set lines {{if (i%2) == 0}
+           {echo "even "}
+           {print i}
+           {else}
+           {echo "odd "}
+           {print i}
+           {end}
+           {set variable $foo = 0}
+           {set variable $j = 0}
+           {while $j < i}
+           {set variable $foo += $j}
+           {set variable $j++}
+           {end}
+           {print $foo}
+           {if i != 40}
+           {c}
+           {end}
+           {end}}
+
+send_gdb "commands\n"
+for {set i 0} {$i < [llength $lines]} {incr i} {
+    gdb_expect {
+        -re ".*>" {
+            send_gdb "[lindex $lines $i]\n"
+        }
+        -re "$gdb_prompt $" {
+            set reason "got top-level prompt early"
+            break
+        }
+        timeout {
+            set reason "timeout"
+            break
+        }
+    }
+}
+if {$i >= [llength $lines]} {
+    pass "send breakpoint commands"
+} else {
+    fail "send breakpoint commands ($reason)"
+}
+
+gdb_run_cmd
+gdb_test_multiple "" "run program with breakpoint commands" {
+    -re "warning: Invalid control type in command structure" {
+        fail "run program with breakpoint commands"
+    }
+    -re "$gdb_prompt $" {
+        pass "run program with breakpoint commands"
+    }
+    eof {
+        fail "run program with breakpoint commands (GDB died)"
+    }
+}
diff --git a/gdb/testsuite/gdb.cp/class2.cc b/gdb/testsuite/gdb.cp/class2.cc
new file mode 100644
index 0000000..16cf988
--- /dev/null
+++ b/gdb/testsuite/gdb.cp/class2.cc
@@ -0,0 +1,66 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+   Copyright 2003 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+ 
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+   Please email any bugs, comments, and/or additions to this file to:
+   bug-gdb@prep.ai.mit.edu  */
+
+struct A
+{
+  virtual ~A ();
+  int a1;
+};
+
+A::~A()
+{
+  a1 = 800;
+}
+
+struct B : public A
+{
+  virtual ~B ();
+  int b1;
+  int b2;
+};
+
+B::~B()
+{
+  a1 = 900;
+  b1 = 901;
+  b2 = 902;
+}
+
+// Stop the compiler from optimizing away data.
+void refer (A *)
+{
+  ;
+}
+
+int main (void)
+{
+  A alpha, *aap, *abp;
+  B beta, *bbp;
+
+  alpha.a1 = 100;
+  beta.a1 = 200; beta.b1 = 201; beta.b2 = 202;
+
+  aap = &alpha; refer (aap);
+  abp = &beta;  refer (abp);
+  bbp = &beta;  refer (bbp);
+
+  return 0;  // marker return 0
+} // marker close brace
diff --git a/gdb/testsuite/gdb.cp/class2.exp b/gdb/testsuite/gdb.cp/class2.exp
new file mode 100644
index 0000000..9d55345
--- /dev/null
+++ b/gdb/testsuite/gdb.cp/class2.exp
@@ -0,0 +1,115 @@
+# Copyright 2003 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+
+if $tracelevel then {
+    strace $tracelevel
+    }
+
+if { [skip_cplus_tests] } { continue }
+
+set prms_id 0
+set bug_id 0
+
+set testfile "class2"
+set srcfile ${testfile}.cc
+set binfile ${objdir}/${subdir}/${testfile}
+
+# Create and source the file that provides information about the compiler
+# used to compile the test case.
+if [get_compiler_info ${binfile} "c++"] {
+    return -1
+}
+
+if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable {debug c++}] != "" } {
+    gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail."
+}
+
+gdb_exit
+gdb_start
+gdb_reinitialize_dir $srcdir/$subdir
+gdb_load ${binfile}
+
+# Start with "set print object off".
+
+gdb_test "set print object off" ""
+
+if ![runto_main] then {
+    perror "couldn't run to main"
+    continue
+}
+
+get_debug_format
+
+gdb_test "break [gdb_get_line_number "marker return 0"]" \
+    "Breakpoint.*at.* file .*" ""
+
+gdb_test "continue" "Breakpoint .* at .*" ""
+
+# Access the "A" object.
+
+gdb_test "print alpha" \
+    "= {.*a1 = 100.*}" \
+    "print alpha at marker return 0"
+
+# Access the "B" object.
+
+gdb_test "print beta" \
+    "= {.*a1 = 200.*b1 = 201.*b2 = 202}" \
+    "print beta at marker return 0"
+
+# Access the "A" object through an "A *" pointer.
+
+gdb_test_multiple "print * aap" "print * aap at marker return 0" {
+    -re "= {.*a1 = 100.*}\r\n$gdb_prompt $" {
+	# gcc 2.95.3 -gstabs+
+	# gcc 3.3.2 -gdwarf-2
+	# gcc 3.3.2 -gstabs+
+	pass "print * aap at marker return 0"
+    }
+    -re "= {.*a1 = .*}\r\n$gdb_prompt $" {
+	if { [test_compiler_info gcc-2-*] && [test_debug_format "DWARF 2"] } {
+	    # gcc 2.95.3 -gdwarf-2
+	    setup_kfail "gdb/1465" "*-*-*"
+	}
+	fail "print * aap at marker return 0"
+    }
+}
+
+# Access the "B" object through a "B *" pointer.
+
+gdb_test "print * bbp" \
+    "= {.*a1 = 200.*b1 = 201.*b2 = 202}" \
+    "print * bbp at marker return 0"
+
+# Access the "B" object through an "A *" pointer.
+# This should print using the "A" type.
+
+gdb_test_multiple "print * abp" "print * abp at marker return 0, s-p-o off" {
+    -re "= {.*a1 = 200.*b1 = .*b2 = .*}\r\n$gdb_prompt $" {
+	# This would violate the documentation for "set print object off".
+	fail "print * abp at marker return 0, s-p-o off"
+    }
+    -re "= {.*a1 = 200.*}\r\n$gdb_prompt $" {
+	pass "print * abp at marker return 0, s-p-o off"
+    }
+}
+
+# Access the "B" object through a "B *" pointer expression.
+# This should print using the "B" type.
+
+gdb_test "print * (B *) abp" \
+    "= {.*a1 = 200.*b1 = 201.*b2 = 202}" \
+    "print * (B *) abp at marker return 0"
diff --git a/sim/m32r/cpu2.c b/sim/m32r/cpu2.c
new file mode 100644
index 0000000..1749880
--- /dev/null
+++ b/sim/m32r/cpu2.c
@@ -0,0 +1,197 @@
+/* Misc. support for CPU family m32r2f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU m32r2f
+#define WANT_CPU_M32R2F
+
+#include "sim-main.h"
+#include "cgen-ops.h"
+
+/* Get the value of h-pc.  */
+
+USI
+m32r2f_h_pc_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_pc);
+}
+
+/* Set a value for h-pc.  */
+
+void
+m32r2f_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+  CPU (h_pc) = newval;
+}
+
+/* Get the value of h-gr.  */
+
+SI
+m32r2f_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return CPU (h_gr[regno]);
+}
+
+/* Set a value for h-gr.  */
+
+void
+m32r2f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  CPU (h_gr[regno]) = newval;
+}
+
+/* Get the value of h-cr.  */
+
+USI
+m32r2f_h_cr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_CR (regno);
+}
+
+/* Set a value for h-cr.  */
+
+void
+m32r2f_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+{
+  SET_H_CR (regno, newval);
+}
+
+/* Get the value of h-accum.  */
+
+DI
+m32r2f_h_accum_get (SIM_CPU *current_cpu)
+{
+  return GET_H_ACCUM ();
+}
+
+/* Set a value for h-accum.  */
+
+void
+m32r2f_h_accum_set (SIM_CPU *current_cpu, DI newval)
+{
+  SET_H_ACCUM (newval);
+}
+
+/* Get the value of h-accums.  */
+
+DI
+m32r2f_h_accums_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_ACCUMS (regno);
+}
+
+/* Set a value for h-accums.  */
+
+void
+m32r2f_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
+{
+  SET_H_ACCUMS (regno, newval);
+}
+
+/* Get the value of h-cond.  */
+
+BI
+m32r2f_h_cond_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_cond);
+}
+
+/* Set a value for h-cond.  */
+
+void
+m32r2f_h_cond_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_cond) = newval;
+}
+
+/* Get the value of h-psw.  */
+
+UQI
+m32r2f_h_psw_get (SIM_CPU *current_cpu)
+{
+  return GET_H_PSW ();
+}
+
+/* Set a value for h-psw.  */
+
+void
+m32r2f_h_psw_set (SIM_CPU *current_cpu, UQI newval)
+{
+  SET_H_PSW (newval);
+}
+
+/* Get the value of h-bpsw.  */
+
+UQI
+m32r2f_h_bpsw_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_bpsw);
+}
+
+/* Set a value for h-bpsw.  */
+
+void
+m32r2f_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_bpsw) = newval;
+}
+
+/* Get the value of h-bbpsw.  */
+
+UQI
+m32r2f_h_bbpsw_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_bbpsw);
+}
+
+/* Set a value for h-bbpsw.  */
+
+void
+m32r2f_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_bbpsw) = newval;
+}
+
+/* Get the value of h-lock.  */
+
+BI
+m32r2f_h_lock_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_lock);
+}
+
+/* Set a value for h-lock.  */
+
+void
+m32r2f_h_lock_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_lock) = newval;
+}
+
+/* Record trace results for INSN.  */
+
+void
+m32r2f_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+			    int *indices, TRACE_RECORD *tr)
+{
+}
diff --git a/sim/m32r/cpu2.h b/sim/m32r/cpu2.h
new file mode 100644
index 0000000..8ae49e4
--- /dev/null
+++ b/sim/m32r/cpu2.h
@@ -0,0 +1,1046 @@
+/* CPU family header for m32r2f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CPU_M32R2F_H
+#define CPU_M32R2F_H
+
+/* Maximum number of instructions that are fetched at a time.
+   This is for LIW type instructions sets (e.g. m32r).  */
+#define MAX_LIW_INSNS 2
+
+/* Maximum number of instructions that can be executed in parallel.  */
+#define MAX_PARALLEL_INSNS 2
+
+/* CPU state information.  */
+typedef struct {
+  /* Hardware elements.  */
+  struct {
+  /* program counter */
+  USI h_pc;
+#define GET_H_PC() CPU (h_pc)
+#define SET_H_PC(x) (CPU (h_pc) = (x))
+  /* general registers */
+  SI h_gr[16];
+#define GET_H_GR(a1) CPU (h_gr)[a1]
+#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
+  /* control registers */
+  USI h_cr[16];
+#define GET_H_CR(index) m32r2f_h_cr_get_handler (current_cpu, index)
+#define SET_H_CR(index, x) \
+do { \
+m32r2f_h_cr_set_handler (current_cpu, (index), (x));\
+;} while (0)
+  /* accumulator */
+  DI h_accum;
+#define GET_H_ACCUM() m32r2f_h_accum_get_handler (current_cpu)
+#define SET_H_ACCUM(x) \
+do { \
+m32r2f_h_accum_set_handler (current_cpu, (x));\
+;} while (0)
+  /* accumulators */
+  DI h_accums[2];
+#define GET_H_ACCUMS(index) m32r2f_h_accums_get_handler (current_cpu, index)
+#define SET_H_ACCUMS(index, x) \
+do { \
+m32r2f_h_accums_set_handler (current_cpu, (index), (x));\
+;} while (0)
+  /* condition bit */
+  BI h_cond;
+#define GET_H_COND() CPU (h_cond)
+#define SET_H_COND(x) (CPU (h_cond) = (x))
+  /* psw part of psw */
+  UQI h_psw;
+#define GET_H_PSW() m32r2f_h_psw_get_handler (current_cpu)
+#define SET_H_PSW(x) \
+do { \
+m32r2f_h_psw_set_handler (current_cpu, (x));\
+;} while (0)
+  /* backup psw */
+  UQI h_bpsw;
+#define GET_H_BPSW() CPU (h_bpsw)
+#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
+  /* backup bpsw */
+  UQI h_bbpsw;
+#define GET_H_BBPSW() CPU (h_bbpsw)
+#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
+  /* lock */
+  BI h_lock;
+#define GET_H_LOCK() CPU (h_lock)
+#define SET_H_LOCK(x) (CPU (h_lock) = (x))
+  } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+} M32R2F_CPU_DATA;
+
+/* Cover fns for register access.  */
+USI m32r2f_h_pc_get (SIM_CPU *);
+void m32r2f_h_pc_set (SIM_CPU *, USI);
+SI m32r2f_h_gr_get (SIM_CPU *, UINT);
+void m32r2f_h_gr_set (SIM_CPU *, UINT, SI);
+USI m32r2f_h_cr_get (SIM_CPU *, UINT);
+void m32r2f_h_cr_set (SIM_CPU *, UINT, USI);
+DI m32r2f_h_accum_get (SIM_CPU *);
+void m32r2f_h_accum_set (SIM_CPU *, DI);
+DI m32r2f_h_accums_get (SIM_CPU *, UINT);
+void m32r2f_h_accums_set (SIM_CPU *, UINT, DI);
+BI m32r2f_h_cond_get (SIM_CPU *);
+void m32r2f_h_cond_set (SIM_CPU *, BI);
+UQI m32r2f_h_psw_get (SIM_CPU *);
+void m32r2f_h_psw_set (SIM_CPU *, UQI);
+UQI m32r2f_h_bpsw_get (SIM_CPU *);
+void m32r2f_h_bpsw_set (SIM_CPU *, UQI);
+UQI m32r2f_h_bbpsw_get (SIM_CPU *);
+void m32r2f_h_bbpsw_set (SIM_CPU *, UQI);
+BI m32r2f_h_lock_get (SIM_CPU *);
+void m32r2f_h_lock_set (SIM_CPU *, BI);
+
+/* These must be hand-written.  */
+extern CPUREG_FETCH_FN m32r2f_fetch_register;
+extern CPUREG_STORE_FN m32r2f_store_register;
+
+typedef struct {
+  int empty;
+} MODEL_M32R2_DATA;
+
+/* Instruction argument buffer.  */
+
+union sem_fields {
+  struct { /* no operands */
+    int empty;
+  } fmt_empty;
+  struct { /*  */
+    UINT f_uimm8;
+  } sfmt_clrpsw;
+  struct { /*  */
+    UINT f_uimm4;
+  } sfmt_trap;
+  struct { /*  */
+    IADDR i_disp24;
+    unsigned char out_h_gr_SI_14;
+  } sfmt_bl24;
+  struct { /*  */
+    IADDR i_disp8;
+    unsigned char out_h_gr_SI_14;
+  } sfmt_bl8;
+  struct { /*  */
+    SI f_imm1;
+    UINT f_accd;
+    UINT f_accs;
+  } sfmt_rac_dsi;
+  struct { /*  */
+    SI* i_dr;
+    UINT f_hi16;
+    UINT f_r1;
+    unsigned char out_dr;
+  } sfmt_seth;
+  struct { /*  */
+    SI* i_src1;
+    UINT f_accs;
+    UINT f_r1;
+    unsigned char in_src1;
+  } sfmt_mvtachi_a;
+  struct { /*  */
+    SI* i_dr;
+    UINT f_accs;
+    UINT f_r1;
+    unsigned char out_dr;
+  } sfmt_mvfachi_a;
+  struct { /*  */
+    ADDR i_uimm24;
+    SI* i_dr;
+    UINT f_r1;
+    unsigned char out_dr;
+  } sfmt_ld24;
+  struct { /*  */
+    SI* i_sr;
+    UINT f_r2;
+    unsigned char in_sr;
+    unsigned char out_h_gr_SI_14;
+  } sfmt_jl;
+  struct { /*  */
+    SI* i_sr;
+    INT f_simm16;
+    UINT f_r2;
+    UINT f_uimm3;
+    unsigned char in_sr;
+  } sfmt_bset;
+  struct { /*  */
+    SI* i_dr;
+    UINT f_r1;
+    UINT f_uimm5;
+    unsigned char in_dr;
+    unsigned char out_dr;
+  } sfmt_slli;
+  struct { /*  */
+    SI* i_dr;
+    INT f_simm8;
+    UINT f_r1;
+    unsigned char in_dr;
+    unsigned char out_dr;
+  } sfmt_addi;
+  struct { /*  */
+    SI* i_src1;
+    SI* i_src2;
+    UINT f_r1;
+    UINT f_r2;
+    unsigned char in_src1;
+    unsigned char in_src2;
+    unsigned char out_src2;
+  } sfmt_st_plus;
+  struct { /*  */
+    SI* i_src1;
+    SI* i_src2;
+    INT f_simm16;
+    UINT f_r1;
+    UINT f_r2;
+    unsigned char in_src1;
+    unsigned char in_src2;
+  } sfmt_st_d;
+  struct { /*  */
+    SI* i_src1;
+    SI* i_src2;
+    UINT f_acc;
+    UINT f_r1;
+    UINT f_r2;
+    unsigned char in_src1;
+    unsigned char in_src2;
+  } sfmt_machi_a;
+  struct { /*  */
+    SI* i_dr;
+    SI* i_sr;
+    UINT f_r1;
+    UINT f_r2;
+    unsigned char in_sr;
+    unsigned char out_dr;
+    unsigned char out_sr;
+  } sfmt_ld_plus;
+  struct { /*  */
+    IADDR i_disp16;
+    SI* i_src1;
+    SI* i_src2;
+    UINT f_r1;
+    UINT f_r2;
+    unsigned char in_src1;
+    unsigned char in_src2;
+  } sfmt_beq;
+  struct { /*  */
+    SI* i_dr;
+    SI* i_sr;
+    UINT f_r1;
+    UINT f_r2;
+    UINT f_uimm16;
+    unsigned char in_sr;
+    unsigned char out_dr;
+  } sfmt_and3;
+  struct { /*  */
+    SI* i_dr;
+    SI* i_sr;
+    INT f_simm16;
+    UINT f_r1;
+    UINT f_r2;
+    unsigned char in_sr;
+    unsigned char out_dr;
+  } sfmt_add3;
+  struct { /*  */
+    SI* i_dr;
+    SI* i_sr;
+    UINT f_r1;
+    UINT f_r2;
+    unsigned char in_dr;
+    unsigned char in_sr;
+    unsigned char out_dr;
+  } sfmt_add;
+#if WITH_SCACHE_PBB
+  /* Writeback handler.  */
+  struct {
+    /* Pointer to argbuf entry for insn whose results need writing back.  */
+    const struct argbuf *abuf;
+  } write;
+  /* x-before handler */
+  struct {
+    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+    int first_p;
+  } before;
+  /* x-after handler */
+  struct {
+    int empty;
+  } after;
+  /* This entry is used to terminate each pbb.  */
+  struct {
+    /* Number of insns in pbb.  */
+    int insn_count;
+    /* Next pbb to execute.  */
+    SCACHE *next;
+    SCACHE *branch_target;
+  } chain;
+#endif
+};
+
+/* The ARGBUF struct.  */
+struct argbuf {
+  /* These are the baseclass definitions.  */
+  IADDR addr;
+  const IDESC *idesc;
+  char trace_p;
+  char profile_p;
+  /* ??? Temporary hack for skip insns.  */
+  char skip_count;
+  char unused;
+  /* cpu specific data follows */
+  union sem semantic;
+  int written;
+  union sem_fields fields;
+};
+
+/* A cached insn.
+
+   ??? SCACHE used to contain more than just argbuf.  We could delete the
+   type entirely and always just use ARGBUF, but for future concerns and as
+   a level of abstraction it is left in.  */
+
+struct scache {
+  struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+   These define and assign the local vars that contain the insn's fields.  */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+  unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+  length = 0; \
+
+#define EXTRACT_IFMT_ADD_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_IFMT_ADD_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_ADD3_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  INT f_simm16; \
+  unsigned int length;
+#define EXTRACT_IFMT_ADD3_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_AND3_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  UINT f_uimm16; \
+  unsigned int length;
+#define EXTRACT_IFMT_AND3_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_OR3_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  UINT f_uimm16; \
+  unsigned int length;
+#define EXTRACT_IFMT_OR3_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_ADDI_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  INT f_simm8; \
+  unsigned int length;
+#define EXTRACT_IFMT_ADDI_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
+
+#define EXTRACT_IFMT_ADDV3_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  INT f_simm16; \
+  unsigned int length;
+#define EXTRACT_IFMT_ADDV3_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BC8_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  SI f_disp8; \
+  unsigned int length;
+#define EXTRACT_IFMT_BC8_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+
+#define EXTRACT_IFMT_BC24_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  SI f_disp24; \
+  unsigned int length;
+#define EXTRACT_IFMT_BC24_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
+
+#define EXTRACT_IFMT_BEQ_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  SI f_disp16; \
+  unsigned int length;
+#define EXTRACT_IFMT_BEQ_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
+
+#define EXTRACT_IFMT_BEQZ_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  SI f_disp16; \
+  unsigned int length;
+#define EXTRACT_IFMT_BEQZ_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
+
+#define EXTRACT_IFMT_CMP_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMP_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_CMPI_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  INT f_simm16; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMPI_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_CMPZ_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_IFMT_CMPZ_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_DIV_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  INT f_simm16; \
+  unsigned int length;
+#define EXTRACT_IFMT_DIV_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_JC_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_IFMT_JC_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_LD24_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_uimm24; \
+  unsigned int length;
+#define EXTRACT_IFMT_LD24_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
+
+#define EXTRACT_IFMT_LDI16_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  INT f_simm16; \
+  unsigned int length;
+#define EXTRACT_IFMT_LDI16_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_MACHI_A_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_acc; \
+  UINT f_op23; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_IFMT_MACHI_A_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
+  f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_MVFACHI_A_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_accs; \
+  UINT f_op3; \
+  unsigned int length;
+#define EXTRACT_IFMT_MVFACHI_A_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
+  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
+
+#define EXTRACT_IFMT_MVFC_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_IFMT_MVFC_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_MVTACHI_A_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_accs; \
+  UINT f_op3; \
+  unsigned int length;
+#define EXTRACT_IFMT_MVTACHI_A_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
+  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
+
+#define EXTRACT_IFMT_MVTC_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_IFMT_MVTC_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_NOP_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_IFMT_NOP_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_RAC_DSI_VARS \
+  UINT f_op1; \
+  UINT f_accd; \
+  UINT f_bits67; \
+  UINT f_op2; \
+  UINT f_accs; \
+  UINT f_bit14; \
+  SI f_imm1; \
+  unsigned int length;
+#define EXTRACT_IFMT_RAC_DSI_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
+  f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
+  f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
+  f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
+
+#define EXTRACT_IFMT_SETH_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  UINT f_hi16; \
+  unsigned int length;
+#define EXTRACT_IFMT_SETH_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_SLLI_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_shift_op2; \
+  UINT f_uimm5; \
+  unsigned int length;
+#define EXTRACT_IFMT_SLLI_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
+  f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
+
+#define EXTRACT_IFMT_ST_D_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  INT f_simm16; \
+  unsigned int length;
+#define EXTRACT_IFMT_ST_D_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_TRAP_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_uimm4; \
+  unsigned int length;
+#define EXTRACT_IFMT_TRAP_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+#define EXTRACT_IFMT_SATB_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  UINT f_uimm16; \
+  unsigned int length;
+#define EXTRACT_IFMT_SATB_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_CLRPSW_VARS \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_uimm8; \
+  unsigned int length;
+#define EXTRACT_IFMT_CLRPSW_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
+
+#define EXTRACT_IFMT_BSET_VARS \
+  UINT f_op1; \
+  UINT f_bit4; \
+  UINT f_uimm3; \
+  UINT f_op2; \
+  UINT f_r2; \
+  INT f_simm16; \
+  unsigned int length;
+#define EXTRACT_IFMT_BSET_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
+  f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
+
+#define EXTRACT_IFMT_BTST_VARS \
+  UINT f_op1; \
+  UINT f_bit4; \
+  UINT f_uimm3; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_IFMT_BTST_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
+  f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
+
+/* Queued output values of an instruction.  */
+
+struct parexec {
+  union {
+    struct { /* empty sformat for unspecified field list */
+      int empty;
+    } sfmt_empty;
+    struct { /* e.g. add $dr,$sr */
+      SI dr;
+    } sfmt_add;
+    struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
+      SI dr;
+    } sfmt_add3;
+    struct { /* e.g. and3 $dr,$sr,$uimm16 */
+      SI dr;
+    } sfmt_and3;
+    struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
+      SI dr;
+    } sfmt_or3;
+    struct { /* e.g. addi $dr,$simm8 */
+      SI dr;
+    } sfmt_addi;
+    struct { /* e.g. addv $dr,$sr */
+      BI condbit;
+      SI dr;
+    } sfmt_addv;
+    struct { /* e.g. addv3 $dr,$sr,$simm16 */
+      BI condbit;
+      SI dr;
+    } sfmt_addv3;
+    struct { /* e.g. addx $dr,$sr */
+      BI condbit;
+      SI dr;
+    } sfmt_addx;
+    struct { /* e.g. bc.s $disp8 */
+      USI pc;
+    } sfmt_bc8;
+    struct { /* e.g. bc.l $disp24 */
+      USI pc;
+    } sfmt_bc24;
+    struct { /* e.g. beq $src1,$src2,$disp16 */
+      USI pc;
+    } sfmt_beq;
+    struct { /* e.g. beqz $src2,$disp16 */
+      USI pc;
+    } sfmt_beqz;
+    struct { /* e.g. bl.s $disp8 */
+      SI h_gr_SI_14;
+      USI pc;
+    } sfmt_bl8;
+    struct { /* e.g. bl.l $disp24 */
+      SI h_gr_SI_14;
+      USI pc;
+    } sfmt_bl24;
+    struct { /* e.g. bcl.s $disp8 */
+      SI h_gr_SI_14;
+      USI pc;
+    } sfmt_bcl8;
+    struct { /* e.g. bcl.l $disp24 */
+      SI h_gr_SI_14;
+      USI pc;
+    } sfmt_bcl24;
+    struct { /* e.g. bra.s $disp8 */
+      USI pc;
+    } sfmt_bra8;
+    struct { /* e.g. bra.l $disp24 */
+      USI pc;
+    } sfmt_bra24;
+    struct { /* e.g. cmp $src1,$src2 */
+      BI condbit;
+    } sfmt_cmp;
+    struct { /* e.g. cmpi $src2,$simm16 */
+      BI condbit;
+    } sfmt_cmpi;
+    struct { /* e.g. cmpz $src2 */
+      BI condbit;
+    } sfmt_cmpz;
+    struct { /* e.g. div $dr,$sr */
+      SI dr;
+    } sfmt_div;
+    struct { /* e.g. jc $sr */
+      USI pc;
+    } sfmt_jc;
+    struct { /* e.g. jl $sr */
+      SI h_gr_SI_14;
+      USI pc;
+    } sfmt_jl;
+    struct { /* e.g. jmp $sr */
+      USI pc;
+    } sfmt_jmp;
+    struct { /* e.g. ld $dr,@$sr */
+      SI dr;
+    } sfmt_ld;
+    struct { /* e.g. ld $dr,@($slo16,$sr) */
+      SI dr;
+    } sfmt_ld_d;
+    struct { /* e.g. ldb $dr,@$sr */
+      SI dr;
+    } sfmt_ldb;
+    struct { /* e.g. ldb $dr,@($slo16,$sr) */
+      SI dr;
+    } sfmt_ldb_d;
+    struct { /* e.g. ldh $dr,@$sr */
+      SI dr;
+    } sfmt_ldh;
+    struct { /* e.g. ldh $dr,@($slo16,$sr) */
+      SI dr;
+    } sfmt_ldh_d;
+    struct { /* e.g. ld $dr,@$sr+ */
+      SI dr;
+      SI sr;
+    } sfmt_ld_plus;
+    struct { /* e.g. ld24 $dr,$uimm24 */
+      SI dr;
+    } sfmt_ld24;
+    struct { /* e.g. ldi8 $dr,$simm8 */
+      SI dr;
+    } sfmt_ldi8;
+    struct { /* e.g. ldi16 $dr,$hash$slo16 */
+      SI dr;
+    } sfmt_ldi16;
+    struct { /* e.g. lock $dr,@$sr */
+      SI dr;
+      BI h_lock_BI;
+    } sfmt_lock;
+    struct { /* e.g. machi $src1,$src2,$acc */
+      DI acc;
+    } sfmt_machi_a;
+    struct { /* e.g. mulhi $src1,$src2,$acc */
+      DI acc;
+    } sfmt_mulhi_a;
+    struct { /* e.g. mv $dr,$sr */
+      SI dr;
+    } sfmt_mv;
+    struct { /* e.g. mvfachi $dr,$accs */
+      SI dr;
+    } sfmt_mvfachi_a;
+    struct { /* e.g. mvfc $dr,$scr */
+      SI dr;
+    } sfmt_mvfc;
+    struct { /* e.g. mvtachi $src1,$accs */
+      DI accs;
+    } sfmt_mvtachi_a;
+    struct { /* e.g. mvtc $sr,$dcr */
+      USI dcr;
+    } sfmt_mvtc;
+    struct { /* e.g. nop */
+      int empty;
+    } sfmt_nop;
+    struct { /* e.g. rac $accd,$accs,$imm1 */
+      DI accd;
+    } sfmt_rac_dsi;
+    struct { /* e.g. rte */
+      UQI h_bpsw_UQI;
+      USI h_cr_USI_6;
+      UQI h_psw_UQI;
+      USI pc;
+    } sfmt_rte;
+    struct { /* e.g. seth $dr,$hash$hi16 */
+      SI dr;
+    } sfmt_seth;
+    struct { /* e.g. sll3 $dr,$sr,$simm16 */
+      SI dr;
+    } sfmt_sll3;
+    struct { /* e.g. slli $dr,$uimm5 */
+      SI dr;
+    } sfmt_slli;
+    struct { /* e.g. st $src1,@$src2 */
+      SI h_memory_SI_src2;
+      USI h_memory_SI_src2_idx;
+    } sfmt_st;
+    struct { /* e.g. st $src1,@($slo16,$src2) */
+      SI h_memory_SI_add__DFLT_src2_slo16;
+      USI h_memory_SI_add__DFLT_src2_slo16_idx;
+    } sfmt_st_d;
+    struct { /* e.g. stb $src1,@$src2 */
+      QI h_memory_QI_src2;
+      USI h_memory_QI_src2_idx;
+    } sfmt_stb;
+    struct { /* e.g. stb $src1,@($slo16,$src2) */
+      QI h_memory_QI_add__DFLT_src2_slo16;
+      USI h_memory_QI_add__DFLT_src2_slo16_idx;
+    } sfmt_stb_d;
+    struct { /* e.g. sth $src1,@$src2 */
+      HI h_memory_HI_src2;
+      USI h_memory_HI_src2_idx;
+    } sfmt_sth;
+    struct { /* e.g. sth $src1,@($slo16,$src2) */
+      HI h_memory_HI_add__DFLT_src2_slo16;
+      USI h_memory_HI_add__DFLT_src2_slo16_idx;
+    } sfmt_sth_d;
+    struct { /* e.g. st $src1,@+$src2 */
+      SI h_memory_SI_new_src2;
+      USI h_memory_SI_new_src2_idx;
+      SI src2;
+    } sfmt_st_plus;
+    struct { /* e.g. sth $src1,@$src2+ */
+      HI h_memory_HI_new_src2;
+      USI h_memory_HI_new_src2_idx;
+      SI src2;
+    } sfmt_sth_plus;
+    struct { /* e.g. stb $src1,@$src2+ */
+      QI h_memory_QI_new_src2;
+      USI h_memory_QI_new_src2_idx;
+      SI src2;
+    } sfmt_stb_plus;
+    struct { /* e.g. trap $uimm4 */
+      UQI h_bbpsw_UQI;
+      UQI h_bpsw_UQI;
+      USI h_cr_USI_14;
+      USI h_cr_USI_6;
+      UQI h_psw_UQI;
+      SI pc;
+    } sfmt_trap;
+    struct { /* e.g. unlock $src1,@$src2 */
+      BI h_lock_BI;
+      SI h_memory_SI_src2;
+      USI h_memory_SI_src2_idx;
+    } sfmt_unlock;
+    struct { /* e.g. satb $dr,$sr */
+      SI dr;
+    } sfmt_satb;
+    struct { /* e.g. sat $dr,$sr */
+      SI dr;
+    } sfmt_sat;
+    struct { /* e.g. sadd */
+      DI h_accums_DI_0;
+    } sfmt_sadd;
+    struct { /* e.g. macwu1 $src1,$src2 */
+      DI h_accums_DI_1;
+    } sfmt_macwu1;
+    struct { /* e.g. msblo $src1,$src2 */
+      DI accum;
+    } sfmt_msblo;
+    struct { /* e.g. mulwu1 $src1,$src2 */
+      DI h_accums_DI_1;
+    } sfmt_mulwu1;
+    struct { /* e.g. sc */
+      int empty;
+    } sfmt_sc;
+    struct { /* e.g. clrpsw $uimm8 */
+      USI h_cr_USI_0;
+    } sfmt_clrpsw;
+    struct { /* e.g. setpsw $uimm8 */
+      USI h_cr_USI_0;
+    } sfmt_setpsw;
+    struct { /* e.g. bset $uimm3,@($slo16,$sr) */
+      QI h_memory_QI_add__DFLT_sr_slo16;
+      USI h_memory_QI_add__DFLT_sr_slo16_idx;
+    } sfmt_bset;
+    struct { /* e.g. btst $uimm3,$sr */
+      BI condbit;
+    } sfmt_btst;
+  } operands;
+  /* For conditionally written operands, bitmask of which ones were.  */
+  int written;
+};
+
+/* Collection of various things for the trace handler to use.  */
+
+typedef struct trace_record {
+  IADDR pc;
+  /* FIXME:wip */
+} TRACE_RECORD;
+
+#endif /* CPU_M32R2F_H */
diff --git a/sim/m32r/decode2.c b/sim/m32r/decode2.c
new file mode 100644
index 0000000..d98db5e
--- /dev/null
+++ b/sim/m32r/decode2.c
@@ -0,0 +1,2609 @@
+/* Simulator instruction decoder for m32r2f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU m32r2f
+#define WANT_CPU_M32R2F
+
+#include "sim-main.h"
+#include "sim-assert.h"
+
+/* Insn can't be executed in parallel.
+   Or is that "do NOt Pass to Air defense Radar"? :-) */
+#define NOPAR (-1)
+
+/* The instruction descriptor array.
+   This is computed at runtime.  Space for it is not malloc'd to save a
+   teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
+   but won't be done until necessary (we don't currently support the runtime
+   addition of instructions nor an SMP machine with different cpus).  */
+static IDESC m32r2f_insn_data[M32R2F_INSN__MAX];
+
+/* Commas between elements are contained in the macros.
+   Some of these are conditionally compiled out.  */
+
+static const struct insn_sem m32r2f_insn_sem[] =
+{
+  { VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
+  { VIRTUAL_INSN_X_AFTER, M32R2F_INSN_X_AFTER, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
+  { VIRTUAL_INSN_X_BEFORE, M32R2F_INSN_X_BEFORE, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
+  { VIRTUAL_INSN_X_CTI_CHAIN, M32R2F_INSN_X_CTI_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
+  { VIRTUAL_INSN_X_CHAIN, M32R2F_INSN_X_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
+  { VIRTUAL_INSN_X_BEGIN, M32R2F_INSN_X_BEGIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
+  { M32R_INSN_ADD, M32R2F_INSN_ADD, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_ADD, M32R2F_INSN_WRITE_ADD },
+  { M32R_INSN_ADD3, M32R2F_INSN_ADD3, M32R2F_SFMT_ADD3, NOPAR, NOPAR  },
+  { M32R_INSN_AND, M32R2F_INSN_AND, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND },
+  { M32R_INSN_AND3, M32R2F_INSN_AND3, M32R2F_SFMT_AND3, NOPAR, NOPAR  },
+  { M32R_INSN_OR, M32R2F_INSN_OR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_OR, M32R2F_INSN_WRITE_OR },
+  { M32R_INSN_OR3, M32R2F_INSN_OR3, M32R2F_SFMT_OR3, NOPAR, NOPAR  },
+  { M32R_INSN_XOR, M32R2F_INSN_XOR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_XOR, M32R2F_INSN_WRITE_XOR },
+  { M32R_INSN_XOR3, M32R2F_INSN_XOR3, M32R2F_SFMT_AND3, NOPAR, NOPAR  },
+  { M32R_INSN_ADDI, M32R2F_INSN_ADDI, M32R2F_SFMT_ADDI, M32R2F_INSN_PAR_ADDI, M32R2F_INSN_WRITE_ADDI },
+  { M32R_INSN_ADDV, M32R2F_INSN_ADDV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_ADDV, M32R2F_INSN_WRITE_ADDV },
+  { M32R_INSN_ADDV3, M32R2F_INSN_ADDV3, M32R2F_SFMT_ADDV3, NOPAR, NOPAR  },
+  { M32R_INSN_ADDX, M32R2F_INSN_ADDX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_ADDX, M32R2F_INSN_WRITE_ADDX },
+  { M32R_INSN_BC8, M32R2F_INSN_BC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BC8, M32R2F_INSN_WRITE_BC8 },
+  { M32R_INSN_BC24, M32R2F_INSN_BC24, M32R2F_SFMT_BC24, NOPAR, NOPAR  },
+  { M32R_INSN_BEQ, M32R2F_INSN_BEQ, M32R2F_SFMT_BEQ, NOPAR, NOPAR  },
+  { M32R_INSN_BEQZ, M32R2F_INSN_BEQZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR  },
+  { M32R_INSN_BGEZ, M32R2F_INSN_BGEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR  },
+  { M32R_INSN_BGTZ, M32R2F_INSN_BGTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR  },
+  { M32R_INSN_BLEZ, M32R2F_INSN_BLEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR  },
+  { M32R_INSN_BLTZ, M32R2F_INSN_BLTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR  },
+  { M32R_INSN_BNEZ, M32R2F_INSN_BNEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR  },
+  { M32R_INSN_BL8, M32R2F_INSN_BL8, M32R2F_SFMT_BL8, M32R2F_INSN_PAR_BL8, M32R2F_INSN_WRITE_BL8 },
+  { M32R_INSN_BL24, M32R2F_INSN_BL24, M32R2F_SFMT_BL24, NOPAR, NOPAR  },
+  { M32R_INSN_BCL8, M32R2F_INSN_BCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BCL8, M32R2F_INSN_WRITE_BCL8 },
+  { M32R_INSN_BCL24, M32R2F_INSN_BCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR  },
+  { M32R_INSN_BNC8, M32R2F_INSN_BNC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BNC8, M32R2F_INSN_WRITE_BNC8 },
+  { M32R_INSN_BNC24, M32R2F_INSN_BNC24, M32R2F_SFMT_BC24, NOPAR, NOPAR  },
+  { M32R_INSN_BNE, M32R2F_INSN_BNE, M32R2F_SFMT_BEQ, NOPAR, NOPAR  },
+  { M32R_INSN_BRA8, M32R2F_INSN_BRA8, M32R2F_SFMT_BRA8, M32R2F_INSN_PAR_BRA8, M32R2F_INSN_WRITE_BRA8 },
+  { M32R_INSN_BRA24, M32R2F_INSN_BRA24, M32R2F_SFMT_BRA24, NOPAR, NOPAR  },
+  { M32R_INSN_BNCL8, M32R2F_INSN_BNCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BNCL8, M32R2F_INSN_WRITE_BNCL8 },
+  { M32R_INSN_BNCL24, M32R2F_INSN_BNCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR  },
+  { M32R_INSN_CMP, M32R2F_INSN_CMP, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMP, M32R2F_INSN_WRITE_CMP },
+  { M32R_INSN_CMPI, M32R2F_INSN_CMPI, M32R2F_SFMT_CMPI, NOPAR, NOPAR  },
+  { M32R_INSN_CMPU, M32R2F_INSN_CMPU, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPU, M32R2F_INSN_WRITE_CMPU },
+  { M32R_INSN_CMPUI, M32R2F_INSN_CMPUI, M32R2F_SFMT_CMPI, NOPAR, NOPAR  },
+  { M32R_INSN_CMPEQ, M32R2F_INSN_CMPEQ, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPEQ, M32R2F_INSN_WRITE_CMPEQ },
+  { M32R_INSN_CMPZ, M32R2F_INSN_CMPZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_CMPZ, M32R2F_INSN_WRITE_CMPZ },
+  { M32R_INSN_DIV, M32R2F_INSN_DIV, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
+  { M32R_INSN_DIVU, M32R2F_INSN_DIVU, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
+  { M32R_INSN_REM, M32R2F_INSN_REM, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
+  { M32R_INSN_REMU, M32R2F_INSN_REMU, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
+  { M32R_INSN_REMH, M32R2F_INSN_REMH, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
+  { M32R_INSN_REMUH, M32R2F_INSN_REMUH, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
+  { M32R_INSN_REMB, M32R2F_INSN_REMB, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
+  { M32R_INSN_REMUB, M32R2F_INSN_REMUB, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
+  { M32R_INSN_DIVUH, M32R2F_INSN_DIVUH, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
+  { M32R_INSN_DIVB, M32R2F_INSN_DIVB, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
+  { M32R_INSN_DIVUB, M32R2F_INSN_DIVUB, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
+  { M32R_INSN_DIVH, M32R2F_INSN_DIVH, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
+  { M32R_INSN_JC, M32R2F_INSN_JC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JC, M32R2F_INSN_WRITE_JC },
+  { M32R_INSN_JNC, M32R2F_INSN_JNC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JNC, M32R2F_INSN_WRITE_JNC },
+  { M32R_INSN_JL, M32R2F_INSN_JL, M32R2F_SFMT_JL, M32R2F_INSN_PAR_JL, M32R2F_INSN_WRITE_JL },
+  { M32R_INSN_JMP, M32R2F_INSN_JMP, M32R2F_SFMT_JMP, M32R2F_INSN_PAR_JMP, M32R2F_INSN_WRITE_JMP },
+  { M32R_INSN_LD, M32R2F_INSN_LD, M32R2F_SFMT_LD, M32R2F_INSN_PAR_LD, M32R2F_INSN_WRITE_LD },
+  { M32R_INSN_LD_D, M32R2F_INSN_LD_D, M32R2F_SFMT_LD_D, NOPAR, NOPAR  },
+  { M32R_INSN_LDB, M32R2F_INSN_LDB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDB, M32R2F_INSN_WRITE_LDB },
+  { M32R_INSN_LDB_D, M32R2F_INSN_LDB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR  },
+  { M32R_INSN_LDH, M32R2F_INSN_LDH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDH, M32R2F_INSN_WRITE_LDH },
+  { M32R_INSN_LDH_D, M32R2F_INSN_LDH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR  },
+  { M32R_INSN_LDUB, M32R2F_INSN_LDUB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDUB, M32R2F_INSN_WRITE_LDUB },
+  { M32R_INSN_LDUB_D, M32R2F_INSN_LDUB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR  },
+  { M32R_INSN_LDUH, M32R2F_INSN_LDUH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDUH, M32R2F_INSN_WRITE_LDUH },
+  { M32R_INSN_LDUH_D, M32R2F_INSN_LDUH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR  },
+  { M32R_INSN_LD_PLUS, M32R2F_INSN_LD_PLUS, M32R2F_SFMT_LD_PLUS, M32R2F_INSN_PAR_LD_PLUS, M32R2F_INSN_WRITE_LD_PLUS },
+  { M32R_INSN_LD24, M32R2F_INSN_LD24, M32R2F_SFMT_LD24, NOPAR, NOPAR  },
+  { M32R_INSN_LDI8, M32R2F_INSN_LDI8, M32R2F_SFMT_LDI8, M32R2F_INSN_PAR_LDI8, M32R2F_INSN_WRITE_LDI8 },
+  { M32R_INSN_LDI16, M32R2F_INSN_LDI16, M32R2F_SFMT_LDI16, NOPAR, NOPAR  },
+  { M32R_INSN_LOCK, M32R2F_INSN_LOCK, M32R2F_SFMT_LOCK, M32R2F_INSN_PAR_LOCK, M32R2F_INSN_WRITE_LOCK },
+  { M32R_INSN_MACHI_A, M32R2F_INSN_MACHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACHI_A, M32R2F_INSN_WRITE_MACHI_A },
+  { M32R_INSN_MACLO_A, M32R2F_INSN_MACLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACLO_A, M32R2F_INSN_WRITE_MACLO_A },
+  { M32R_INSN_MACWHI_A, M32R2F_INSN_MACWHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWHI_A, M32R2F_INSN_WRITE_MACWHI_A },
+  { M32R_INSN_MACWLO_A, M32R2F_INSN_MACWLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWLO_A, M32R2F_INSN_WRITE_MACWLO_A },
+  { M32R_INSN_MUL, M32R2F_INSN_MUL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_MUL, M32R2F_INSN_WRITE_MUL },
+  { M32R_INSN_MULHI_A, M32R2F_INSN_MULHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULHI_A, M32R2F_INSN_WRITE_MULHI_A },
+  { M32R_INSN_MULLO_A, M32R2F_INSN_MULLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULLO_A, M32R2F_INSN_WRITE_MULLO_A },
+  { M32R_INSN_MULWHI_A, M32R2F_INSN_MULWHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWHI_A, M32R2F_INSN_WRITE_MULWHI_A },
+  { M32R_INSN_MULWLO_A, M32R2F_INSN_MULWLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWLO_A, M32R2F_INSN_WRITE_MULWLO_A },
+  { M32R_INSN_MV, M32R2F_INSN_MV, M32R2F_SFMT_MV, M32R2F_INSN_PAR_MV, M32R2F_INSN_WRITE_MV },
+  { M32R_INSN_MVFACHI_A, M32R2F_INSN_MVFACHI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACHI_A, M32R2F_INSN_WRITE_MVFACHI_A },
+  { M32R_INSN_MVFACLO_A, M32R2F_INSN_MVFACLO_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACLO_A, M32R2F_INSN_WRITE_MVFACLO_A },
+  { M32R_INSN_MVFACMI_A, M32R2F_INSN_MVFACMI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACMI_A, M32R2F_INSN_WRITE_MVFACMI_A },
+  { M32R_INSN_MVFC, M32R2F_INSN_MVFC, M32R2F_SFMT_MVFC, M32R2F_INSN_PAR_MVFC, M32R2F_INSN_WRITE_MVFC },
+  { M32R_INSN_MVTACHI_A, M32R2F_INSN_MVTACHI_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACHI_A, M32R2F_INSN_WRITE_MVTACHI_A },
+  { M32R_INSN_MVTACLO_A, M32R2F_INSN_MVTACLO_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACLO_A, M32R2F_INSN_WRITE_MVTACLO_A },
+  { M32R_INSN_MVTC, M32R2F_INSN_MVTC, M32R2F_SFMT_MVTC, M32R2F_INSN_PAR_MVTC, M32R2F_INSN_WRITE_MVTC },
+  { M32R_INSN_NEG, M32R2F_INSN_NEG, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NEG, M32R2F_INSN_WRITE_NEG },
+  { M32R_INSN_NOP, M32R2F_INSN_NOP, M32R2F_SFMT_NOP, M32R2F_INSN_PAR_NOP, M32R2F_INSN_WRITE_NOP },
+  { M32R_INSN_NOT, M32R2F_INSN_NOT, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NOT, M32R2F_INSN_WRITE_NOT },
+  { M32R_INSN_RAC_DSI, M32R2F_INSN_RAC_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RAC_DSI, M32R2F_INSN_WRITE_RAC_DSI },
+  { M32R_INSN_RACH_DSI, M32R2F_INSN_RACH_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RACH_DSI, M32R2F_INSN_WRITE_RACH_DSI },
+  { M32R_INSN_RTE, M32R2F_INSN_RTE, M32R2F_SFMT_RTE, M32R2F_INSN_PAR_RTE, M32R2F_INSN_WRITE_RTE },
+  { M32R_INSN_SETH, M32R2F_INSN_SETH, M32R2F_SFMT_SETH, NOPAR, NOPAR  },
+  { M32R_INSN_SLL, M32R2F_INSN_SLL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SLL, M32R2F_INSN_WRITE_SLL },
+  { M32R_INSN_SLL3, M32R2F_INSN_SLL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR  },
+  { M32R_INSN_SLLI, M32R2F_INSN_SLLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SLLI, M32R2F_INSN_WRITE_SLLI },
+  { M32R_INSN_SRA, M32R2F_INSN_SRA, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRA, M32R2F_INSN_WRITE_SRA },
+  { M32R_INSN_SRA3, M32R2F_INSN_SRA3, M32R2F_SFMT_SLL3, NOPAR, NOPAR  },
+  { M32R_INSN_SRAI, M32R2F_INSN_SRAI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRAI, M32R2F_INSN_WRITE_SRAI },
+  { M32R_INSN_SRL, M32R2F_INSN_SRL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRL, M32R2F_INSN_WRITE_SRL },
+  { M32R_INSN_SRL3, M32R2F_INSN_SRL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR  },
+  { M32R_INSN_SRLI, M32R2F_INSN_SRLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRLI, M32R2F_INSN_WRITE_SRLI },
+  { M32R_INSN_ST, M32R2F_INSN_ST, M32R2F_SFMT_ST, M32R2F_INSN_PAR_ST, M32R2F_INSN_WRITE_ST },
+  { M32R_INSN_ST_D, M32R2F_INSN_ST_D, M32R2F_SFMT_ST_D, NOPAR, NOPAR  },
+  { M32R_INSN_STB, M32R2F_INSN_STB, M32R2F_SFMT_STB, M32R2F_INSN_PAR_STB, M32R2F_INSN_WRITE_STB },
+  { M32R_INSN_STB_D, M32R2F_INSN_STB_D, M32R2F_SFMT_STB_D, NOPAR, NOPAR  },
+  { M32R_INSN_STH, M32R2F_INSN_STH, M32R2F_SFMT_STH, M32R2F_INSN_PAR_STH, M32R2F_INSN_WRITE_STH },
+  { M32R_INSN_STH_D, M32R2F_INSN_STH_D, M32R2F_SFMT_STH_D, NOPAR, NOPAR  },
+  { M32R_INSN_ST_PLUS, M32R2F_INSN_ST_PLUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_PLUS, M32R2F_INSN_WRITE_ST_PLUS },
+  { M32R_INSN_STH_PLUS, M32R2F_INSN_STH_PLUS, M32R2F_SFMT_STH_PLUS, M32R2F_INSN_PAR_STH_PLUS, M32R2F_INSN_WRITE_STH_PLUS },
+  { M32R_INSN_STB_PLUS, M32R2F_INSN_STB_PLUS, M32R2F_SFMT_STB_PLUS, M32R2F_INSN_PAR_STB_PLUS, M32R2F_INSN_WRITE_STB_PLUS },
+  { M32R_INSN_ST_MINUS, M32R2F_INSN_ST_MINUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_MINUS, M32R2F_INSN_WRITE_ST_MINUS },
+  { M32R_INSN_SUB, M32R2F_INSN_SUB, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SUB, M32R2F_INSN_WRITE_SUB },
+  { M32R_INSN_SUBV, M32R2F_INSN_SUBV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_SUBV, M32R2F_INSN_WRITE_SUBV },
+  { M32R_INSN_SUBX, M32R2F_INSN_SUBX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_SUBX, M32R2F_INSN_WRITE_SUBX },
+  { M32R_INSN_TRAP, M32R2F_INSN_TRAP, M32R2F_SFMT_TRAP, M32R2F_INSN_PAR_TRAP, M32R2F_INSN_WRITE_TRAP },
+  { M32R_INSN_UNLOCK, M32R2F_INSN_UNLOCK, M32R2F_SFMT_UNLOCK, M32R2F_INSN_PAR_UNLOCK, M32R2F_INSN_WRITE_UNLOCK },
+  { M32R_INSN_SATB, M32R2F_INSN_SATB, M32R2F_SFMT_SATB, NOPAR, NOPAR  },
+  { M32R_INSN_SATH, M32R2F_INSN_SATH, M32R2F_SFMT_SATB, NOPAR, NOPAR  },
+  { M32R_INSN_SAT, M32R2F_INSN_SAT, M32R2F_SFMT_SAT, NOPAR, NOPAR  },
+  { M32R_INSN_PCMPBZ, M32R2F_INSN_PCMPBZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_PCMPBZ, M32R2F_INSN_WRITE_PCMPBZ },
+  { M32R_INSN_SADD, M32R2F_INSN_SADD, M32R2F_SFMT_SADD, M32R2F_INSN_PAR_SADD, M32R2F_INSN_WRITE_SADD },
+  { M32R_INSN_MACWU1, M32R2F_INSN_MACWU1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACWU1, M32R2F_INSN_WRITE_MACWU1 },
+  { M32R_INSN_MSBLO, M32R2F_INSN_MSBLO, M32R2F_SFMT_MSBLO, M32R2F_INSN_PAR_MSBLO, M32R2F_INSN_WRITE_MSBLO },
+  { M32R_INSN_MULWU1, M32R2F_INSN_MULWU1, M32R2F_SFMT_MULWU1, M32R2F_INSN_PAR_MULWU1, M32R2F_INSN_WRITE_MULWU1 },
+  { M32R_INSN_MACLH1, M32R2F_INSN_MACLH1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACLH1, M32R2F_INSN_WRITE_MACLH1 },
+  { M32R_INSN_SC, M32R2F_INSN_SC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SC, M32R2F_INSN_WRITE_SC },
+  { M32R_INSN_SNC, M32R2F_INSN_SNC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SNC, M32R2F_INSN_WRITE_SNC },
+  { M32R_INSN_CLRPSW, M32R2F_INSN_CLRPSW, M32R2F_SFMT_CLRPSW, M32R2F_INSN_PAR_CLRPSW, M32R2F_INSN_WRITE_CLRPSW },
+  { M32R_INSN_SETPSW, M32R2F_INSN_SETPSW, M32R2F_SFMT_SETPSW, M32R2F_INSN_PAR_SETPSW, M32R2F_INSN_WRITE_SETPSW },
+  { M32R_INSN_BSET, M32R2F_INSN_BSET, M32R2F_SFMT_BSET, NOPAR, NOPAR  },
+  { M32R_INSN_BCLR, M32R2F_INSN_BCLR, M32R2F_SFMT_BSET, NOPAR, NOPAR  },
+  { M32R_INSN_BTST, M32R2F_INSN_BTST, M32R2F_SFMT_BTST, M32R2F_INSN_PAR_BTST, M32R2F_INSN_WRITE_BTST },
+};
+
+static const struct insn_sem m32r2f_insn_sem_invalid = {
+  VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR
+};
+
+/* Initialize an IDESC from the compile-time computable parts.  */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+  const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
+
+  id->num = t->index;
+  id->sfmt = t->sfmt;
+  if ((int) t->type <= 0)
+    id->idata = & cgen_virtual_insn_table[- (int) t->type];
+  else
+    id->idata = & insn_table[t->type];
+  id->attrs = CGEN_INSN_ATTRS (id->idata);
+  /* Oh my god, a magic number.  */
+  id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
+
+#if WITH_PROFILE_MODEL_P
+  id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+  {
+    SIM_DESC sd = CPU_STATE (cpu);
+    SIM_ASSERT (t->index == id->timing->num);
+  }
+#endif
+
+  /* Semantic pointers are initialized elsewhere.  */
+}
+
+/* Initialize the instruction descriptor table.  */
+
+void
+m32r2f_init_idesc_table (SIM_CPU *cpu)
+{
+  IDESC *id,*tabend;
+  const struct insn_sem *t,*tend;
+  int tabsize = M32R2F_INSN__MAX;
+  IDESC *table = m32r2f_insn_data;
+
+  memset (table, 0, tabsize * sizeof (IDESC));
+
+  /* First set all entries to the `invalid insn'.  */
+  t = & m32r2f_insn_sem_invalid;
+  for (id = table, tabend = table + tabsize; id < tabend; ++id)
+    init_idesc (cpu, id, t);
+
+  /* Now fill in the values for the chosen cpu.  */
+  for (t = m32r2f_insn_sem, tend = t + sizeof (m32r2f_insn_sem) / sizeof (*t);
+       t != tend; ++t)
+    {
+      init_idesc (cpu, & table[t->index], t);
+      if (t->par_index != NOPAR)
+	{
+	  init_idesc (cpu, &table[t->par_index], t);
+	  table[t->index].par_idesc = &table[t->par_index];
+	}
+      if (t->par_index != NOPAR)
+	{
+	  init_idesc (cpu, &table[t->write_index], t);
+	  table[t->par_index].par_idesc = &table[t->write_index];
+	}
+    }
+
+  /* Link the IDESC table into the cpu.  */
+  CPU_IDESC (cpu) = table;
+}
+
+/* Given an instruction, return a pointer to its IDESC entry.  */
+
+const IDESC *
+m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
+              CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
+              ARGBUF *abuf)
+{
+  /* Result of decoder.  */
+  M32R2F_INSN_TYPE itype;
+
+  {
+    CGEN_INSN_INT insn = base_insn;
+
+    {
+      unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
+      switch (val)
+      {
+      case 0 : itype = M32R2F_INSN_SUBV; goto extract_sfmt_addv;
+      case 1 : itype = M32R2F_INSN_SUBX; goto extract_sfmt_addx;
+      case 2 : itype = M32R2F_INSN_SUB; goto extract_sfmt_add;
+      case 3 : itype = M32R2F_INSN_NEG; goto extract_sfmt_mv;
+      case 4 : itype = M32R2F_INSN_CMP; goto extract_sfmt_cmp;
+      case 5 : itype = M32R2F_INSN_CMPU; goto extract_sfmt_cmp;
+      case 6 : itype = M32R2F_INSN_CMPEQ; goto extract_sfmt_cmp;
+      case 7 :
+        {
+          unsigned int val = (((insn >> 8) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = M32R2F_INSN_CMPZ; goto extract_sfmt_cmpz;
+          case 3 : itype = M32R2F_INSN_PCMPBZ; goto extract_sfmt_cmpz;
+          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 8 : itype = M32R2F_INSN_ADDV; goto extract_sfmt_addv;
+      case 9 : itype = M32R2F_INSN_ADDX; goto extract_sfmt_addx;
+      case 10 : itype = M32R2F_INSN_ADD; goto extract_sfmt_add;
+      case 11 : itype = M32R2F_INSN_NOT; goto extract_sfmt_mv;
+      case 12 : itype = M32R2F_INSN_AND; goto extract_sfmt_add;
+      case 13 : itype = M32R2F_INSN_XOR; goto extract_sfmt_add;
+      case 14 : itype = M32R2F_INSN_OR; goto extract_sfmt_add;
+      case 15 : itype = M32R2F_INSN_BTST; goto extract_sfmt_btst;
+      case 16 : itype = M32R2F_INSN_SRL; goto extract_sfmt_add;
+      case 18 : itype = M32R2F_INSN_SRA; goto extract_sfmt_add;
+      case 20 : itype = M32R2F_INSN_SLL; goto extract_sfmt_add;
+      case 22 : itype = M32R2F_INSN_MUL; goto extract_sfmt_add;
+      case 24 : itype = M32R2F_INSN_MV; goto extract_sfmt_mv;
+      case 25 : itype = M32R2F_INSN_MVFC; goto extract_sfmt_mvfc;
+      case 26 : itype = M32R2F_INSN_MVTC; goto extract_sfmt_mvtc;
+      case 28 :
+        {
+          unsigned int val = (((insn >> 8) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = M32R2F_INSN_JC; goto extract_sfmt_jc;
+          case 1 : itype = M32R2F_INSN_JNC; goto extract_sfmt_jc;
+          case 2 : itype = M32R2F_INSN_JL; goto extract_sfmt_jl;
+          case 3 : itype = M32R2F_INSN_JMP; goto extract_sfmt_jmp;
+          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 29 : itype = M32R2F_INSN_RTE; goto extract_sfmt_rte;
+      case 31 : itype = M32R2F_INSN_TRAP; goto extract_sfmt_trap;
+      case 32 : itype = M32R2F_INSN_STB; goto extract_sfmt_stb;
+      case 33 : itype = M32R2F_INSN_STB_PLUS; goto extract_sfmt_stb_plus;
+      case 34 : itype = M32R2F_INSN_STH; goto extract_sfmt_sth;
+      case 35 : itype = M32R2F_INSN_STH_PLUS; goto extract_sfmt_sth_plus;
+      case 36 : itype = M32R2F_INSN_ST; goto extract_sfmt_st;
+      case 37 : itype = M32R2F_INSN_UNLOCK; goto extract_sfmt_unlock;
+      case 38 : itype = M32R2F_INSN_ST_PLUS; goto extract_sfmt_st_plus;
+      case 39 : itype = M32R2F_INSN_ST_MINUS; goto extract_sfmt_st_plus;
+      case 40 : itype = M32R2F_INSN_LDB; goto extract_sfmt_ldb;
+      case 41 : itype = M32R2F_INSN_LDUB; goto extract_sfmt_ldb;
+      case 42 : itype = M32R2F_INSN_LDH; goto extract_sfmt_ldh;
+      case 43 : itype = M32R2F_INSN_LDUH; goto extract_sfmt_ldh;
+      case 44 : itype = M32R2F_INSN_LD; goto extract_sfmt_ld;
+      case 45 : itype = M32R2F_INSN_LOCK; goto extract_sfmt_lock;
+      case 46 : itype = M32R2F_INSN_LD_PLUS; goto extract_sfmt_ld_plus;
+      case 48 : /* fall through */
+      case 56 : itype = M32R2F_INSN_MULHI_A; goto extract_sfmt_mulhi_a;
+      case 49 : /* fall through */
+      case 57 : itype = M32R2F_INSN_MULLO_A; goto extract_sfmt_mulhi_a;
+      case 50 : /* fall through */
+      case 58 : itype = M32R2F_INSN_MULWHI_A; goto extract_sfmt_mulhi_a;
+      case 51 : /* fall through */
+      case 59 : itype = M32R2F_INSN_MULWLO_A; goto extract_sfmt_mulhi_a;
+      case 52 : /* fall through */
+      case 60 : itype = M32R2F_INSN_MACHI_A; goto extract_sfmt_machi_a;
+      case 53 : /* fall through */
+      case 61 : itype = M32R2F_INSN_MACLO_A; goto extract_sfmt_machi_a;
+      case 54 : /* fall through */
+      case 62 : itype = M32R2F_INSN_MACWHI_A; goto extract_sfmt_machi_a;
+      case 55 : /* fall through */
+      case 63 : itype = M32R2F_INSN_MACWLO_A; goto extract_sfmt_machi_a;
+      case 64 : /* fall through */
+      case 65 : /* fall through */
+      case 66 : /* fall through */
+      case 67 : /* fall through */
+      case 68 : /* fall through */
+      case 69 : /* fall through */
+      case 70 : /* fall through */
+      case 71 : /* fall through */
+      case 72 : /* fall through */
+      case 73 : /* fall through */
+      case 74 : /* fall through */
+      case 75 : /* fall through */
+      case 76 : /* fall through */
+      case 77 : /* fall through */
+      case 78 : /* fall through */
+      case 79 : itype = M32R2F_INSN_ADDI; goto extract_sfmt_addi;
+      case 80 : /* fall through */
+      case 81 : itype = M32R2F_INSN_SRLI; goto extract_sfmt_slli;
+      case 82 : /* fall through */
+      case 83 : itype = M32R2F_INSN_SRAI; goto extract_sfmt_slli;
+      case 84 : /* fall through */
+      case 85 : itype = M32R2F_INSN_SLLI; goto extract_sfmt_slli;
+      case 87 :
+        {
+          unsigned int val = (((insn >> 0) & (1 << 0)));
+          switch (val)
+          {
+          case 0 : itype = M32R2F_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a;
+          case 1 : itype = M32R2F_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a;
+          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 88 : itype = M32R2F_INSN_RACH_DSI; goto extract_sfmt_rac_dsi;
+      case 89 : itype = M32R2F_INSN_RAC_DSI; goto extract_sfmt_rac_dsi;
+      case 90 : itype = M32R2F_INSN_MULWU1; goto extract_sfmt_mulwu1;
+      case 91 : itype = M32R2F_INSN_MACWU1; goto extract_sfmt_macwu1;
+      case 92 : itype = M32R2F_INSN_MACLH1; goto extract_sfmt_macwu1;
+      case 93 : itype = M32R2F_INSN_MSBLO; goto extract_sfmt_msblo;
+      case 94 : itype = M32R2F_INSN_SADD; goto extract_sfmt_sadd;
+      case 95 :
+        {
+          unsigned int val = (((insn >> 0) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = M32R2F_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a;
+          case 1 : itype = M32R2F_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a;
+          case 2 : itype = M32R2F_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a;
+          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 96 : /* fall through */
+      case 97 : /* fall through */
+      case 98 : /* fall through */
+      case 99 : /* fall through */
+      case 100 : /* fall through */
+      case 101 : /* fall through */
+      case 102 : /* fall through */
+      case 103 : /* fall through */
+      case 104 : /* fall through */
+      case 105 : /* fall through */
+      case 106 : /* fall through */
+      case 107 : /* fall through */
+      case 108 : /* fall through */
+      case 109 : /* fall through */
+      case 110 : /* fall through */
+      case 111 : itype = M32R2F_INSN_LDI8; goto extract_sfmt_ldi8;
+      case 112 :
+        {
+          unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
+          switch (val)
+          {
+          case 0 : itype = M32R2F_INSN_NOP; goto extract_sfmt_nop;
+          case 2 : /* fall through */
+          case 3 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw;
+          case 4 : /* fall through */
+          case 5 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw;
+          case 9 : itype = M32R2F_INSN_SC; goto extract_sfmt_sc;
+          case 11 : itype = M32R2F_INSN_SNC; goto extract_sfmt_sc;
+          case 16 : /* fall through */
+          case 17 : itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8;
+          case 18 : /* fall through */
+          case 19 : itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8;
+          case 24 : /* fall through */
+          case 25 : itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8;
+          case 26 : /* fall through */
+          case 27 : itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8;
+          case 28 : /* fall through */
+          case 29 : itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8;
+          case 30 : /* fall through */
+          case 31 : itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8;
+          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 113 : /* fall through */
+      case 114 : /* fall through */
+      case 115 : /* fall through */
+      case 116 : /* fall through */
+      case 117 : /* fall through */
+      case 118 : /* fall through */
+      case 119 : /* fall through */
+      case 120 : /* fall through */
+      case 121 : /* fall through */
+      case 122 : /* fall through */
+      case 123 : /* fall through */
+      case 124 : /* fall through */
+      case 125 : /* fall through */
+      case 126 : /* fall through */
+      case 127 :
+        {
+          unsigned int val = (((insn >> 8) & (15 << 0)));
+          switch (val)
+          {
+          case 1 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw;
+          case 2 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw;
+          case 8 : itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8;
+          case 9 : itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8;
+          case 12 : itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8;
+          case 13 : itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8;
+          case 14 : itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8;
+          case 15 : itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8;
+          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 132 : itype = M32R2F_INSN_CMPI; goto extract_sfmt_cmpi;
+      case 133 : itype = M32R2F_INSN_CMPUI; goto extract_sfmt_cmpi;
+      case 134 :
+        {
+          unsigned int val = (((insn >> -8) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = M32R2F_INSN_SAT; goto extract_sfmt_sat;
+          case 2 : itype = M32R2F_INSN_SATH; goto extract_sfmt_satb;
+          case 3 : itype = M32R2F_INSN_SATB; goto extract_sfmt_satb;
+          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 136 : itype = M32R2F_INSN_ADDV3; goto extract_sfmt_addv3;
+      case 138 : itype = M32R2F_INSN_ADD3; goto extract_sfmt_add3;
+      case 140 : itype = M32R2F_INSN_AND3; goto extract_sfmt_and3;
+      case 141 : itype = M32R2F_INSN_XOR3; goto extract_sfmt_and3;
+      case 142 : itype = M32R2F_INSN_OR3; goto extract_sfmt_or3;
+      case 144 :
+        {
+          unsigned int val = (((insn >> -13) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = M32R2F_INSN_DIV; goto extract_sfmt_div;
+          case 2 : itype = M32R2F_INSN_DIVH; goto extract_sfmt_div;
+          case 3 : itype = M32R2F_INSN_DIVB; goto extract_sfmt_div;
+          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 145 :
+        {
+          unsigned int val = (((insn >> -13) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = M32R2F_INSN_DIVU; goto extract_sfmt_div;
+          case 2 : itype = M32R2F_INSN_DIVUH; goto extract_sfmt_div;
+          case 3 : itype = M32R2F_INSN_DIVUB; goto extract_sfmt_div;
+          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 146 :
+        {
+          unsigned int val = (((insn >> -13) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = M32R2F_INSN_REM; goto extract_sfmt_div;
+          case 2 : itype = M32R2F_INSN_REMH; goto extract_sfmt_div;
+          case 3 : itype = M32R2F_INSN_REMB; goto extract_sfmt_div;
+          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 147 :
+        {
+          unsigned int val = (((insn >> -13) & (3 << 0)));
+          switch (val)
+          {
+          case 0 : itype = M32R2F_INSN_REMU; goto extract_sfmt_div;
+          case 2 : itype = M32R2F_INSN_REMUH; goto extract_sfmt_div;
+          case 3 : itype = M32R2F_INSN_REMUB; goto extract_sfmt_div;
+          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      case 152 : itype = M32R2F_INSN_SRL3; goto extract_sfmt_sll3;
+      case 154 : itype = M32R2F_INSN_SRA3; goto extract_sfmt_sll3;
+      case 156 : itype = M32R2F_INSN_SLL3; goto extract_sfmt_sll3;
+      case 159 : itype = M32R2F_INSN_LDI16; goto extract_sfmt_ldi16;
+      case 160 : itype = M32R2F_INSN_STB_D; goto extract_sfmt_stb_d;
+      case 162 : itype = M32R2F_INSN_STH_D; goto extract_sfmt_sth_d;
+      case 164 : itype = M32R2F_INSN_ST_D; goto extract_sfmt_st_d;
+      case 166 : itype = M32R2F_INSN_BSET; goto extract_sfmt_bset;
+      case 167 : itype = M32R2F_INSN_BCLR; goto extract_sfmt_bset;
+      case 168 : itype = M32R2F_INSN_LDB_D; goto extract_sfmt_ldb_d;
+      case 169 : itype = M32R2F_INSN_LDUB_D; goto extract_sfmt_ldb_d;
+      case 170 : itype = M32R2F_INSN_LDH_D; goto extract_sfmt_ldh_d;
+      case 171 : itype = M32R2F_INSN_LDUH_D; goto extract_sfmt_ldh_d;
+      case 172 : itype = M32R2F_INSN_LD_D; goto extract_sfmt_ld_d;
+      case 176 : itype = M32R2F_INSN_BEQ; goto extract_sfmt_beq;
+      case 177 : itype = M32R2F_INSN_BNE; goto extract_sfmt_beq;
+      case 184 : itype = M32R2F_INSN_BEQZ; goto extract_sfmt_beqz;
+      case 185 : itype = M32R2F_INSN_BNEZ; goto extract_sfmt_beqz;
+      case 186 : itype = M32R2F_INSN_BLTZ; goto extract_sfmt_beqz;
+      case 187 : itype = M32R2F_INSN_BGEZ; goto extract_sfmt_beqz;
+      case 188 : itype = M32R2F_INSN_BLEZ; goto extract_sfmt_beqz;
+      case 189 : itype = M32R2F_INSN_BGTZ; goto extract_sfmt_beqz;
+      case 220 : itype = M32R2F_INSN_SETH; goto extract_sfmt_seth;
+      case 224 : /* fall through */
+      case 225 : /* fall through */
+      case 226 : /* fall through */
+      case 227 : /* fall through */
+      case 228 : /* fall through */
+      case 229 : /* fall through */
+      case 230 : /* fall through */
+      case 231 : /* fall through */
+      case 232 : /* fall through */
+      case 233 : /* fall through */
+      case 234 : /* fall through */
+      case 235 : /* fall through */
+      case 236 : /* fall through */
+      case 237 : /* fall through */
+      case 238 : /* fall through */
+      case 239 : itype = M32R2F_INSN_LD24; goto extract_sfmt_ld24;
+      case 240 : /* fall through */
+      case 241 : /* fall through */
+      case 242 : /* fall through */
+      case 243 : /* fall through */
+      case 244 : /* fall through */
+      case 245 : /* fall through */
+      case 246 : /* fall through */
+      case 247 : /* fall through */
+      case 248 : /* fall through */
+      case 249 : /* fall through */
+      case 250 : /* fall through */
+      case 251 : /* fall through */
+      case 252 : /* fall through */
+      case 253 : /* fall through */
+      case 254 : /* fall through */
+      case 255 :
+        {
+          unsigned int val = (((insn >> 8) & (7 << 0)));
+          switch (val)
+          {
+          case 0 : itype = M32R2F_INSN_BCL24; goto extract_sfmt_bcl24;
+          case 1 : itype = M32R2F_INSN_BNCL24; goto extract_sfmt_bcl24;
+          case 4 : itype = M32R2F_INSN_BC24; goto extract_sfmt_bc24;
+          case 5 : itype = M32R2F_INSN_BNC24; goto extract_sfmt_bc24;
+          case 6 : itype = M32R2F_INSN_BL24; goto extract_sfmt_bl24;
+          case 7 : itype = M32R2F_INSN_BRA24; goto extract_sfmt_bra24;
+          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+          }
+        }
+      default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
+      }
+    }
+  }
+
+  /* The instruction has been decoded, now extract the fields.  */
+
+ extract_sfmt_empty:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
+
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_add:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_add3:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_and3:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_and3.f
+    UINT f_r1;
+    UINT f_r2;
+    UINT f_uimm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_uimm16) = f_uimm16;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_or3:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_and3.f
+    UINT f_r1;
+    UINT f_r2;
+    UINT f_uimm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_uimm16) = f_uimm16;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_addi:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi.f
+    UINT f_r1;
+    INT f_simm8;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_simm8) = f_simm8;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_addv:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_addv3:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_addx:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bc8:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+    SI f_disp8;
+
+    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_disp8) = f_disp8;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bc24:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl24.f
+    SI f_disp24;
+
+    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_disp24) = f_disp24;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_beq:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_beq.f
+    UINT f_r1;
+    UINT f_r2;
+    SI f_disp16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_disp16) = f_disp16;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_beqz:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_beq.f
+    UINT f_r2;
+    SI f_disp16;
+
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (i_disp16) = f_disp16;
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bl8:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+    SI f_disp8;
+
+    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_disp8) = f_disp8;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_h_gr_SI_14) = 14;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bl24:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl24.f
+    SI f_disp24;
+
+    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_disp24) = f_disp24;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_h_gr_SI_14) = 14;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bcl8:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+    SI f_disp8;
+
+    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_disp8) = f_disp8;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_h_gr_SI_14) = 14;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bcl24:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl24.f
+    SI f_disp24;
+
+    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_disp24) = f_disp24;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_h_gr_SI_14) = 14;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bra8:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+    SI f_disp8;
+
+    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_disp8) = f_disp8;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bra24:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bl24.f
+    SI f_disp24;
+
+    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (i_disp24) = f_disp24;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmp:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmpi:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_d.f
+    UINT f_r2;
+    INT f_simm16;
+
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r2) = f_r2;
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_cmpz:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r2;
+
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_div:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_jc:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_jl.f
+    UINT f_r2;
+
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_jl:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_jl.f
+    UINT f_r2;
+
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_h_gr_SI_14) = 14;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_jmp:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_jl.f
+    UINT f_r2;
+
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ld:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ld_d:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldb:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldb_d:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldh:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldh_d:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ld_plus:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+      FLD (out_sr) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ld24:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld24.f
+    UINT f_r1;
+    UINT f_uimm24;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (i_uimm24) = f_uimm24;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldi8:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi.f
+    UINT f_r1;
+    INT f_simm8;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm8) = f_simm8;
+  FLD (f_r1) = f_r1;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_ldi16:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    INT f_simm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r1) = f_r1;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_lock:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_machi_a:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+    UINT f_r1;
+    UINT f_acc;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_acc) = f_acc;
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mulhi_a:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+    UINT f_r1;
+    UINT f_acc;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (f_acc) = f_acc;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mv:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mvfachi_a:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+    UINT f_r1;
+    UINT f_accs;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_accs) = f_accs;
+  FLD (f_r1) = f_r1;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mvfc:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mvtachi_a:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+    UINT f_r1;
+    UINT f_accs;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_accs) = f_accs;
+  FLD (f_r1) = f_r1;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mvtc:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_nop:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
+
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_rac_dsi:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+    UINT f_accd;
+    UINT f_accs;
+    SI f_imm1;
+
+    f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2);
+    f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
+    f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1));
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_accs) = f_accs;
+  FLD (f_imm1) = f_imm1;
+  FLD (f_accd) = f_accd;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
+
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_rte:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_seth:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_seth.f
+    UINT f_r1;
+    UINT f_hi16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_hi16) = f_hi16;
+  FLD (f_r1) = f_r1;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_sll3:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_slli:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_slli.f
+    UINT f_r1;
+    UINT f_uimm5;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_uimm5) = f_uimm5;
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_dr) = f_r1;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_st:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_st_d:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_d.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stb:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stb_d:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_d.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_sth:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_sth_d:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_d.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_st_plus:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+      FLD (out_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_sth_plus:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+      FLD (out_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_stb_plus:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+      FLD (out_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_trap:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_trap.f
+    UINT f_uimm4;
+
+    f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_uimm4) = f_uimm4;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_unlock:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_satb:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_sat:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_r1) = f_r1;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  FLD (i_dr) = & CPU (h_gr)[f_r1];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+      FLD (out_dr) = f_r1;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_sadd:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0));
+
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_macwu1:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_msblo:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_mulwu1:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
+
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r1) = f_r1;
+  FLD (f_r2) = f_r2;
+  FLD (i_src1) = & CPU (h_gr)[f_r1];
+  FLD (i_src2) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_src1) = f_r1;
+      FLD (in_src2) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_sc:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+  /* Record the fields for the semantic handler.  */
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0));
+
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_clrpsw:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_clrpsw.f
+    UINT f_uimm8;
+
+    f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_uimm8) = f_uimm8;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
+
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_setpsw:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_clrpsw.f
+    UINT f_uimm8;
+
+    f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_uimm8) = f_uimm8;
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
+
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_bset:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bset.f
+    UINT f_uimm3;
+    UINT f_r2;
+    INT f_simm16;
+
+    f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_simm16) = f_simm16;
+  FLD (f_r2) = f_r2;
+  FLD (f_uimm3) = f_uimm3;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+ extract_sfmt_btst:
+  {
+    const IDESC *idesc = &m32r2f_insn_data[itype];
+    CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bset.f
+    UINT f_uimm3;
+    UINT f_r2;
+
+    f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
+
+  /* Record the fields for the semantic handler.  */
+  FLD (f_r2) = f_r2;
+  FLD (f_uimm3) = f_uimm3;
+  FLD (i_sr) = & CPU (h_gr)[f_r2];
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+  /* Record the fields for profiling.  */
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      FLD (in_sr) = f_r2;
+    }
+#endif
+#undef FLD
+    return idesc;
+  }
+
+}
diff --git a/sim/m32r/decode2.h b/sim/m32r/decode2.h
new file mode 100644
index 0000000..280247e
--- /dev/null
+++ b/sim/m32r/decode2.h
@@ -0,0 +1,151 @@
+/* Decode header for m32r2f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef M32R2F_DECODE_H
+#define M32R2F_DECODE_H
+
+extern const IDESC *m32r2f_decode (SIM_CPU *, IADDR,
+                                  CGEN_INSN_INT, CGEN_INSN_INT,
+                                  ARGBUF *);
+extern void m32r2f_init_idesc_table (SIM_CPU *);
+extern void m32r2f_sem_init_idesc_table (SIM_CPU *);
+extern void m32r2f_semf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family m32r2f.  */
+typedef enum m32r2f_insn_type {
+  M32R2F_INSN_X_INVALID, M32R2F_INSN_X_AFTER, M32R2F_INSN_X_BEFORE, M32R2F_INSN_X_CTI_CHAIN
+ , M32R2F_INSN_X_CHAIN, M32R2F_INSN_X_BEGIN, M32R2F_INSN_ADD, M32R2F_INSN_ADD3
+ , M32R2F_INSN_AND, M32R2F_INSN_AND3, M32R2F_INSN_OR, M32R2F_INSN_OR3
+ , M32R2F_INSN_XOR, M32R2F_INSN_XOR3, M32R2F_INSN_ADDI, M32R2F_INSN_ADDV
+ , M32R2F_INSN_ADDV3, M32R2F_INSN_ADDX, M32R2F_INSN_BC8, M32R2F_INSN_BC24
+ , M32R2F_INSN_BEQ, M32R2F_INSN_BEQZ, M32R2F_INSN_BGEZ, M32R2F_INSN_BGTZ
+ , M32R2F_INSN_BLEZ, M32R2F_INSN_BLTZ, M32R2F_INSN_BNEZ, M32R2F_INSN_BL8
+ , M32R2F_INSN_BL24, M32R2F_INSN_BCL8, M32R2F_INSN_BCL24, M32R2F_INSN_BNC8
+ , M32R2F_INSN_BNC24, M32R2F_INSN_BNE, M32R2F_INSN_BRA8, M32R2F_INSN_BRA24
+ , M32R2F_INSN_BNCL8, M32R2F_INSN_BNCL24, M32R2F_INSN_CMP, M32R2F_INSN_CMPI
+ , M32R2F_INSN_CMPU, M32R2F_INSN_CMPUI, M32R2F_INSN_CMPEQ, M32R2F_INSN_CMPZ
+ , M32R2F_INSN_DIV, M32R2F_INSN_DIVU, M32R2F_INSN_REM, M32R2F_INSN_REMU
+ , M32R2F_INSN_REMH, M32R2F_INSN_REMUH, M32R2F_INSN_REMB, M32R2F_INSN_REMUB
+ , M32R2F_INSN_DIVUH, M32R2F_INSN_DIVB, M32R2F_INSN_DIVUB, M32R2F_INSN_DIVH
+ , M32R2F_INSN_JC, M32R2F_INSN_JNC, M32R2F_INSN_JL, M32R2F_INSN_JMP
+ , M32R2F_INSN_LD, M32R2F_INSN_LD_D, M32R2F_INSN_LDB, M32R2F_INSN_LDB_D
+ , M32R2F_INSN_LDH, M32R2F_INSN_LDH_D, M32R2F_INSN_LDUB, M32R2F_INSN_LDUB_D
+ , M32R2F_INSN_LDUH, M32R2F_INSN_LDUH_D, M32R2F_INSN_LD_PLUS, M32R2F_INSN_LD24
+ , M32R2F_INSN_LDI8, M32R2F_INSN_LDI16, M32R2F_INSN_LOCK, M32R2F_INSN_MACHI_A
+ , M32R2F_INSN_MACLO_A, M32R2F_INSN_MACWHI_A, M32R2F_INSN_MACWLO_A, M32R2F_INSN_MUL
+ , M32R2F_INSN_MULHI_A, M32R2F_INSN_MULLO_A, M32R2F_INSN_MULWHI_A, M32R2F_INSN_MULWLO_A
+ , M32R2F_INSN_MV, M32R2F_INSN_MVFACHI_A, M32R2F_INSN_MVFACLO_A, M32R2F_INSN_MVFACMI_A
+ , M32R2F_INSN_MVFC, M32R2F_INSN_MVTACHI_A, M32R2F_INSN_MVTACLO_A, M32R2F_INSN_MVTC
+ , M32R2F_INSN_NEG, M32R2F_INSN_NOP, M32R2F_INSN_NOT, M32R2F_INSN_RAC_DSI
+ , M32R2F_INSN_RACH_DSI, M32R2F_INSN_RTE, M32R2F_INSN_SETH, M32R2F_INSN_SLL
+ , M32R2F_INSN_SLL3, M32R2F_INSN_SLLI, M32R2F_INSN_SRA, M32R2F_INSN_SRA3
+ , M32R2F_INSN_SRAI, M32R2F_INSN_SRL, M32R2F_INSN_SRL3, M32R2F_INSN_SRLI
+ , M32R2F_INSN_ST, M32R2F_INSN_ST_D, M32R2F_INSN_STB, M32R2F_INSN_STB_D
+ , M32R2F_INSN_STH, M32R2F_INSN_STH_D, M32R2F_INSN_ST_PLUS, M32R2F_INSN_STH_PLUS
+ , M32R2F_INSN_STB_PLUS, M32R2F_INSN_ST_MINUS, M32R2F_INSN_SUB, M32R2F_INSN_SUBV
+ , M32R2F_INSN_SUBX, M32R2F_INSN_TRAP, M32R2F_INSN_UNLOCK, M32R2F_INSN_SATB
+ , M32R2F_INSN_SATH, M32R2F_INSN_SAT, M32R2F_INSN_PCMPBZ, M32R2F_INSN_SADD
+ , M32R2F_INSN_MACWU1, M32R2F_INSN_MSBLO, M32R2F_INSN_MULWU1, M32R2F_INSN_MACLH1
+ , M32R2F_INSN_SC, M32R2F_INSN_SNC, M32R2F_INSN_CLRPSW, M32R2F_INSN_SETPSW
+ , M32R2F_INSN_BSET, M32R2F_INSN_BCLR, M32R2F_INSN_BTST, M32R2F_INSN_PAR_ADD
+ , M32R2F_INSN_WRITE_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND, M32R2F_INSN_PAR_OR
+ , M32R2F_INSN_WRITE_OR, M32R2F_INSN_PAR_XOR, M32R2F_INSN_WRITE_XOR, M32R2F_INSN_PAR_ADDI
+ , M32R2F_INSN_WRITE_ADDI, M32R2F_INSN_PAR_ADDV, M32R2F_INSN_WRITE_ADDV, M32R2F_INSN_PAR_ADDX
+ , M32R2F_INSN_WRITE_ADDX, M32R2F_INSN_PAR_BC8, M32R2F_INSN_WRITE_BC8, M32R2F_INSN_PAR_BL8
+ , M32R2F_INSN_WRITE_BL8, M32R2F_INSN_PAR_BCL8, M32R2F_INSN_WRITE_BCL8, M32R2F_INSN_PAR_BNC8
+ , M32R2F_INSN_WRITE_BNC8, M32R2F_INSN_PAR_BRA8, M32R2F_INSN_WRITE_BRA8, M32R2F_INSN_PAR_BNCL8
+ , M32R2F_INSN_WRITE_BNCL8, M32R2F_INSN_PAR_CMP, M32R2F_INSN_WRITE_CMP, M32R2F_INSN_PAR_CMPU
+ , M32R2F_INSN_WRITE_CMPU, M32R2F_INSN_PAR_CMPEQ, M32R2F_INSN_WRITE_CMPEQ, M32R2F_INSN_PAR_CMPZ
+ , M32R2F_INSN_WRITE_CMPZ, M32R2F_INSN_PAR_JC, M32R2F_INSN_WRITE_JC, M32R2F_INSN_PAR_JNC
+ , M32R2F_INSN_WRITE_JNC, M32R2F_INSN_PAR_JL, M32R2F_INSN_WRITE_JL, M32R2F_INSN_PAR_JMP
+ , M32R2F_INSN_WRITE_JMP, M32R2F_INSN_PAR_LD, M32R2F_INSN_WRITE_LD, M32R2F_INSN_PAR_LDB
+ , M32R2F_INSN_WRITE_LDB, M32R2F_INSN_PAR_LDH, M32R2F_INSN_WRITE_LDH, M32R2F_INSN_PAR_LDUB
+ , M32R2F_INSN_WRITE_LDUB, M32R2F_INSN_PAR_LDUH, M32R2F_INSN_WRITE_LDUH, M32R2F_INSN_PAR_LD_PLUS
+ , M32R2F_INSN_WRITE_LD_PLUS, M32R2F_INSN_PAR_LDI8, M32R2F_INSN_WRITE_LDI8, M32R2F_INSN_PAR_LOCK
+ , M32R2F_INSN_WRITE_LOCK, M32R2F_INSN_PAR_MACHI_A, M32R2F_INSN_WRITE_MACHI_A, M32R2F_INSN_PAR_MACLO_A
+ , M32R2F_INSN_WRITE_MACLO_A, M32R2F_INSN_PAR_MACWHI_A, M32R2F_INSN_WRITE_MACWHI_A, M32R2F_INSN_PAR_MACWLO_A
+ , M32R2F_INSN_WRITE_MACWLO_A, M32R2F_INSN_PAR_MUL, M32R2F_INSN_WRITE_MUL, M32R2F_INSN_PAR_MULHI_A
+ , M32R2F_INSN_WRITE_MULHI_A, M32R2F_INSN_PAR_MULLO_A, M32R2F_INSN_WRITE_MULLO_A, M32R2F_INSN_PAR_MULWHI_A
+ , M32R2F_INSN_WRITE_MULWHI_A, M32R2F_INSN_PAR_MULWLO_A, M32R2F_INSN_WRITE_MULWLO_A, M32R2F_INSN_PAR_MV
+ , M32R2F_INSN_WRITE_MV, M32R2F_INSN_PAR_MVFACHI_A, M32R2F_INSN_WRITE_MVFACHI_A, M32R2F_INSN_PAR_MVFACLO_A
+ , M32R2F_INSN_WRITE_MVFACLO_A, M32R2F_INSN_PAR_MVFACMI_A, M32R2F_INSN_WRITE_MVFACMI_A, M32R2F_INSN_PAR_MVFC
+ , M32R2F_INSN_WRITE_MVFC, M32R2F_INSN_PAR_MVTACHI_A, M32R2F_INSN_WRITE_MVTACHI_A, M32R2F_INSN_PAR_MVTACLO_A
+ , M32R2F_INSN_WRITE_MVTACLO_A, M32R2F_INSN_PAR_MVTC, M32R2F_INSN_WRITE_MVTC, M32R2F_INSN_PAR_NEG
+ , M32R2F_INSN_WRITE_NEG, M32R2F_INSN_PAR_NOP, M32R2F_INSN_WRITE_NOP, M32R2F_INSN_PAR_NOT
+ , M32R2F_INSN_WRITE_NOT, M32R2F_INSN_PAR_RAC_DSI, M32R2F_INSN_WRITE_RAC_DSI, M32R2F_INSN_PAR_RACH_DSI
+ , M32R2F_INSN_WRITE_RACH_DSI, M32R2F_INSN_PAR_RTE, M32R2F_INSN_WRITE_RTE, M32R2F_INSN_PAR_SLL
+ , M32R2F_INSN_WRITE_SLL, M32R2F_INSN_PAR_SLLI, M32R2F_INSN_WRITE_SLLI, M32R2F_INSN_PAR_SRA
+ , M32R2F_INSN_WRITE_SRA, M32R2F_INSN_PAR_SRAI, M32R2F_INSN_WRITE_SRAI, M32R2F_INSN_PAR_SRL
+ , M32R2F_INSN_WRITE_SRL, M32R2F_INSN_PAR_SRLI, M32R2F_INSN_WRITE_SRLI, M32R2F_INSN_PAR_ST
+ , M32R2F_INSN_WRITE_ST, M32R2F_INSN_PAR_STB, M32R2F_INSN_WRITE_STB, M32R2F_INSN_PAR_STH
+ , M32R2F_INSN_WRITE_STH, M32R2F_INSN_PAR_ST_PLUS, M32R2F_INSN_WRITE_ST_PLUS, M32R2F_INSN_PAR_STH_PLUS
+ , M32R2F_INSN_WRITE_STH_PLUS, M32R2F_INSN_PAR_STB_PLUS, M32R2F_INSN_WRITE_STB_PLUS, M32R2F_INSN_PAR_ST_MINUS
+ , M32R2F_INSN_WRITE_ST_MINUS, M32R2F_INSN_PAR_SUB, M32R2F_INSN_WRITE_SUB, M32R2F_INSN_PAR_SUBV
+ , M32R2F_INSN_WRITE_SUBV, M32R2F_INSN_PAR_SUBX, M32R2F_INSN_WRITE_SUBX, M32R2F_INSN_PAR_TRAP
+ , M32R2F_INSN_WRITE_TRAP, M32R2F_INSN_PAR_UNLOCK, M32R2F_INSN_WRITE_UNLOCK, M32R2F_INSN_PAR_PCMPBZ
+ , M32R2F_INSN_WRITE_PCMPBZ, M32R2F_INSN_PAR_SADD, M32R2F_INSN_WRITE_SADD, M32R2F_INSN_PAR_MACWU1
+ , M32R2F_INSN_WRITE_MACWU1, M32R2F_INSN_PAR_MSBLO, M32R2F_INSN_WRITE_MSBLO, M32R2F_INSN_PAR_MULWU1
+ , M32R2F_INSN_WRITE_MULWU1, M32R2F_INSN_PAR_MACLH1, M32R2F_INSN_WRITE_MACLH1, M32R2F_INSN_PAR_SC
+ , M32R2F_INSN_WRITE_SC, M32R2F_INSN_PAR_SNC, M32R2F_INSN_WRITE_SNC, M32R2F_INSN_PAR_CLRPSW
+ , M32R2F_INSN_WRITE_CLRPSW, M32R2F_INSN_PAR_SETPSW, M32R2F_INSN_WRITE_SETPSW, M32R2F_INSN_PAR_BTST
+ , M32R2F_INSN_WRITE_BTST, M32R2F_INSN__MAX
+} M32R2F_INSN_TYPE;
+
+/* Enum declaration for semantic formats in cpu family m32r2f.  */
+typedef enum m32r2f_sfmt_type {
+  M32R2F_SFMT_EMPTY, M32R2F_SFMT_ADD, M32R2F_SFMT_ADD3, M32R2F_SFMT_AND3
+ , M32R2F_SFMT_OR3, M32R2F_SFMT_ADDI, M32R2F_SFMT_ADDV, M32R2F_SFMT_ADDV3
+ , M32R2F_SFMT_ADDX, M32R2F_SFMT_BC8, M32R2F_SFMT_BC24, M32R2F_SFMT_BEQ
+ , M32R2F_SFMT_BEQZ, M32R2F_SFMT_BL8, M32R2F_SFMT_BL24, M32R2F_SFMT_BCL8
+ , M32R2F_SFMT_BCL24, M32R2F_SFMT_BRA8, M32R2F_SFMT_BRA24, M32R2F_SFMT_CMP
+ , M32R2F_SFMT_CMPI, M32R2F_SFMT_CMPZ, M32R2F_SFMT_DIV, M32R2F_SFMT_JC
+ , M32R2F_SFMT_JL, M32R2F_SFMT_JMP, M32R2F_SFMT_LD, M32R2F_SFMT_LD_D
+ , M32R2F_SFMT_LDB, M32R2F_SFMT_LDB_D, M32R2F_SFMT_LDH, M32R2F_SFMT_LDH_D
+ , M32R2F_SFMT_LD_PLUS, M32R2F_SFMT_LD24, M32R2F_SFMT_LDI8, M32R2F_SFMT_LDI16
+ , M32R2F_SFMT_LOCK, M32R2F_SFMT_MACHI_A, M32R2F_SFMT_MULHI_A, M32R2F_SFMT_MV
+ , M32R2F_SFMT_MVFACHI_A, M32R2F_SFMT_MVFC, M32R2F_SFMT_MVTACHI_A, M32R2F_SFMT_MVTC
+ , M32R2F_SFMT_NOP, M32R2F_SFMT_RAC_DSI, M32R2F_SFMT_RTE, M32R2F_SFMT_SETH
+ , M32R2F_SFMT_SLL3, M32R2F_SFMT_SLLI, M32R2F_SFMT_ST, M32R2F_SFMT_ST_D
+ , M32R2F_SFMT_STB, M32R2F_SFMT_STB_D, M32R2F_SFMT_STH, M32R2F_SFMT_STH_D
+ , M32R2F_SFMT_ST_PLUS, M32R2F_SFMT_STH_PLUS, M32R2F_SFMT_STB_PLUS, M32R2F_SFMT_TRAP
+ , M32R2F_SFMT_UNLOCK, M32R2F_SFMT_SATB, M32R2F_SFMT_SAT, M32R2F_SFMT_SADD
+ , M32R2F_SFMT_MACWU1, M32R2F_SFMT_MSBLO, M32R2F_SFMT_MULWU1, M32R2F_SFMT_SC
+ , M32R2F_SFMT_CLRPSW, M32R2F_SFMT_SETPSW, M32R2F_SFMT_BSET, M32R2F_SFMT_BTST
+} M32R2F_SFMT_TYPE;
+
+/* Function unit handlers (user written).  */
+
+extern int m32r2f_model_m32r2_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
+extern int m32r2f_model_m32r2_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
+extern int m32r2f_model_m32r2_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
+extern int m32r2f_model_m32r2_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
+extern int m32r2f_model_m32r2_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
+extern int m32r2f_model_m32r2_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/, INT /*dr*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void m32r2f_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void m32r2f_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* M32R2F_DECODE_H */
diff --git a/sim/m32r/m32r2.c b/sim/m32r/m32r2.c
new file mode 100644
index 0000000..594ce8a
--- /dev/null
+++ b/sim/m32r/m32r2.c
@@ -0,0 +1,311 @@
+/* m32r2 simulator support code
+   Copyright (C) 1997, 1998, 2003 Free Software Foundation, Inc.
+   Contributed by Cygnus Support.
+
+   This file is part of GDB, the GNU debugger.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU m32r2f
+#define WANT_CPU_M32R2F
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+/* The contents of BUF are in target byte order.  */
+
+int
+m32r2f_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
+{
+  return m32rbf_fetch_register (current_cpu, rn, buf, len);
+}
+
+/* The contents of BUF are in target byte order.  */
+
+int
+m32r2f_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
+{
+  return m32rbf_store_register (current_cpu, rn, buf, len);
+}
+
+/* Cover fns to get/set the control registers.
+   FIXME: Duplicated from m32r.c.  The issue is structure offsets.  */
+
+USI
+m32r2f_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
+{
+  switch (cr)
+    {
+    case H_CR_PSW : /* PSW.  */
+      return (((CPU (h_bpsw) & 0xc1) << 8)
+	      | ((CPU (h_psw) & 0xc0) << 0)
+	      | GET_H_COND ());
+    case H_CR_BBPSW : /* Backup backup psw.  */
+      return CPU (h_bbpsw) & 0xc1;
+    case H_CR_CBR : /* Condition bit.  */
+      return GET_H_COND ();
+    case H_CR_SPI : /* Interrupt stack pointer.  */
+      if (! GET_H_SM ())
+	return CPU (h_gr[H_GR_SP]);
+      else
+	return CPU (h_cr[H_CR_SPI]);
+    case H_CR_SPU : /* User stack pointer.  */
+      if (GET_H_SM ())
+	return CPU (h_gr[H_GR_SP]);
+      else
+	return CPU (h_cr[H_CR_SPU]);
+    case H_CR_BPC : /* Backup pc.  */
+      return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
+    case H_CR_BBPC : /* Backup backup pc.  */
+      return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
+    case 4 : /* ??? unspecified, but apparently available */
+    case 5 : /* ??? unspecified, but apparently available */
+      return CPU (h_cr[cr]);
+    default :
+      return 0;
+    }
+}
+
+void
+m32r2f_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
+{
+  switch (cr)
+    {
+    case H_CR_PSW : /* psw */
+      {
+	int old_sm = (CPU (h_psw) & 0x80) != 0;
+	int new_sm = (newval & 0x80) != 0;
+	CPU (h_bpsw) = (newval >> 8) & 0xff;
+	CPU (h_psw) = newval & 0xff;
+	SET_H_COND (newval & 1);
+	/* When switching stack modes, update the registers.  */
+	if (old_sm != new_sm)
+	  {
+	    if (old_sm)
+	      {
+		/* Switching user -> system.  */
+		CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
+		CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
+	      }
+	    else
+	      {
+		/* Switching system -> user.  */
+		CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
+		CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
+	      }
+	  }
+	break;
+      }
+    case H_CR_BBPSW : /* backup backup psw */
+      CPU (h_bbpsw) = newval & 0xff;
+      break;
+    case H_CR_CBR : /* condition bit */
+      SET_H_COND (newval & 1);
+      break;
+    case H_CR_SPI : /* interrupt stack pointer */
+      if (! GET_H_SM ())
+	CPU (h_gr[H_GR_SP]) = newval;
+      else
+	CPU (h_cr[H_CR_SPI]) = newval;
+      break;
+    case H_CR_SPU : /* user stack pointer */
+      if (GET_H_SM ())
+	CPU (h_gr[H_GR_SP]) = newval;
+      else
+	CPU (h_cr[H_CR_SPU]) = newval;
+      break;
+    case H_CR_BPC : /* backup pc */
+      CPU (h_cr[H_CR_BPC]) = newval;
+      break;
+    case H_CR_BBPC : /* backup backup pc */
+      CPU (h_cr[H_CR_BBPC]) = newval;
+      break;
+    case 4 : /* ??? unspecified, but apparently available */
+    case 5 : /* ??? unspecified, but apparently available */
+      CPU (h_cr[cr]) = newval;
+      break;
+    default :
+      /* ignore */
+      break;
+    }
+}
+
+/* Cover fns to access h-psw.  */
+
+UQI
+m32r2f_h_psw_get_handler (SIM_CPU *current_cpu)
+{
+  return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
+}
+
+void
+m32r2f_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_psw) = newval;
+  CPU (h_cond) = newval & 1;
+}
+
+/* Cover fns to access h-accum.  */
+
+DI
+m32r2f_h_accum_get_handler (SIM_CPU *current_cpu)
+{
+  /* Sign extend the top 8 bits.  */
+  DI r;
+  r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
+  r = XORDI (r, MAKEDI (0x800000, 0));
+  r = SUBDI (r, MAKEDI (0x800000, 0));
+  return r;
+}
+
+void
+m32r2f_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
+{
+  CPU (h_accum) = newval;
+}
+
+/* Cover fns to access h-accums.  */
+
+DI
+m32r2f_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno)
+{
+  /* FIXME: Yes, this is just a quick hack.  */
+  DI r;
+  if (regno == 0)
+    r = CPU (h_accum);
+  else
+    r = CPU (h_accums[1]);
+  /* Sign extend the top 8 bits.  */
+  r = ANDDI (r, MAKEDI (0xffffff, 0xffffffff));
+  r = XORDI (r, MAKEDI (0x800000, 0));
+  r = SUBDI (r, MAKEDI (0x800000, 0));
+  return r;
+}
+
+void
+m32r2f_h_accums_set_handler (SIM_CPU *current_cpu, UINT regno, DI newval)
+{
+  /* FIXME: Yes, this is just a quick hack.  */
+  if (regno == 0)
+    CPU (h_accum) = newval;
+  else
+    CPU (h_accums[1]) = newval;
+}
+
+#if WITH_PROFILE_MODEL_P
+
+/* Initialize cycle counting for an insn.
+   FIRST_P is non-zero if this is the first insn in a set of parallel
+   insns.  */
+
+void
+m32r2f_model_insn_before (SIM_CPU *cpu, int first_p)
+{
+  m32rbf_model_insn_before (cpu, first_p);
+}
+
+/* Record the cycles computed for an insn.
+   LAST_P is non-zero if this is the last insn in a set of parallel insns,
+   and we update the total cycle count.
+   CYCLES is the cycle count of the insn.  */
+
+void
+m32r2f_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
+{
+  m32rbf_model_insn_after (cpu, last_p, cycles);
+}
+
+static INLINE void
+check_load_stall (SIM_CPU *cpu, int regno)
+{
+  UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
+
+  if (regno != -1
+      && (h_gr & (1 << regno)) != 0)
+    {
+      CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
+      if (TRACE_INSN_P (cpu))
+	cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
+    }
+}
+
+int
+m32r2f_model_m32r2_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT sr, INT sr2, INT dr)
+{
+  check_load_stall (cpu, sr);
+  check_load_stall (cpu, sr2);
+  return idesc->timing->units[unit_num].done;
+}
+
+int
+m32r2f_model_m32r2_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT src1, INT src2)
+{
+  check_load_stall (cpu, src1);
+  check_load_stall (cpu, src2);
+  return idesc->timing->units[unit_num].done;
+}
+
+int
+m32r2f_model_m32r2_u_mac (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT src1, INT src2)
+{
+  check_load_stall (cpu, src1);
+  check_load_stall (cpu, src2);
+  return idesc->timing->units[unit_num].done;
+}
+
+int
+m32r2f_model_m32r2_u_cti (SIM_CPU *cpu, const IDESC *idesc,
+			  int unit_num, int referenced,
+			  INT sr)
+{
+  PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
+  int taken_p = (referenced & (1 << 1)) != 0;
+
+  check_load_stall (cpu, sr);
+  if (taken_p)
+    {
+      CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
+      PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
+    }
+  else
+    PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
+  return idesc->timing->units[unit_num].done;
+}
+
+int
+m32r2f_model_m32r2_u_load (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT sr, INT dr)
+{
+  CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
+  return idesc->timing->units[unit_num].done;
+}
+
+int
+m32r2f_model_m32r2_u_store (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced,
+			    INT src1, INT src2)
+{
+  return idesc->timing->units[unit_num].done;
+}
+
+#endif /* WITH_PROFILE_MODEL_P */
diff --git a/sim/m32r/mloop2.in b/sim/m32r/mloop2.in
new file mode 100644
index 0000000..bb9b0b2
--- /dev/null
+++ b/sim/m32r/mloop2.in
@@ -0,0 +1,484 @@
+# Simulator main loop for m32r2. -*- C -*-
+# Copyright (C) 1996, 1997, 1998, 2003 Free Software Foundation, Inc.
+#
+# This file is part of GDB, the GNU debugger.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Syntax:
+# /bin/sh mainloop.in command
+#
+# Command is one of:
+#
+# init
+# support
+# extract-{simple,scache,pbb}
+# {full,fast}-exec-{simple,scache,pbb}
+#
+# A target need only provide a "full" version of one of simple,scache,pbb.
+# If the target wants it can also provide a fast version of same, or if
+# the slow (full featured) version is `simple', then the fast version can be
+# one of scache/pbb.
+# A target can't provide more than this.
+
+# ??? After a few more ports are done, revisit.
+# Will eventually need to machine generate a lot of this.
+
+case "x$1" in
+
+xsupport)
+
+cat <<EOF
+
+/* Emit insns to write back the results of insns executed in parallel.
+   SC points to a sufficient number of scache entries for the writeback
+   handlers.
+   SC1/ID1 is the first insn (left slot, lower address).
+   SC2/ID2 is the second insn (right slot, higher address).  */
+
+static INLINE void
+emit_par_finish (SIM_CPU *current_cpu, PCADDR pc, SCACHE *sc,
+		 SCACHE *sc1, const IDESC *id1, SCACHE *sc2, const IDESC *id2)
+{
+  ARGBUF *abuf;
+
+  abuf = &sc->argbuf;
+  id1 = id1->par_idesc;
+  abuf->fields.write.abuf = &sc1->argbuf;
+  @cpu@_fill_argbuf (current_cpu, abuf, id1, pc, 0);
+  /* no need to set trace_p,profile_p */
+#if 0 /* not currently needed for id2 since results written directly */
+  abuf = &sc[1].argbuf;
+  id2 = id2->par_idesc;
+  abuf->fields.write.abuf = &sc2->argbuf;
+  @cpu@_fill_argbuf (current_cpu, abuf, id2, pc + 2, 0);
+  /* no need to set trace_p,profile_p */
+#endif
+}
+
+static INLINE const IDESC *
+emit_16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
+	 SCACHE *sc, int fast_p, int parallel_p)
+{
+  ARGBUF *abuf = &sc->argbuf;
+  const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
+
+  if (parallel_p)
+    id = id->par_idesc;
+  @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+  return id;
+}
+
+static INLINE const IDESC *
+emit_full16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
+	     int trace_p, int profile_p)
+{
+  const IDESC *id;
+
+  @cpu@_emit_before (current_cpu, sc, pc, 1);
+  id = emit_16 (current_cpu, pc, insn, sc + 1, 0, 0);
+  @cpu@_emit_after (current_cpu, sc + 2, pc);
+  sc[1].argbuf.trace_p = trace_p;
+  sc[1].argbuf.profile_p = profile_p;
+  return id;
+}
+
+static INLINE const IDESC *
+emit_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
+	       SCACHE *sc, int fast_p)
+{
+  const IDESC *id,*id2;
+
+  /* Emit both insns, then emit a finisher-upper.
+     We speed things up by handling the second insn serially
+     [not parallelly].  Then the writeback only has to deal
+     with the first insn.  */
+  /* ??? Revisit to handle exceptions right.  */
+
+  /* FIXME: No need to handle this parallely if second is nop.  */
+  id = emit_16 (current_cpu, pc, insn >> 16, sc, fast_p, 1);
+
+  /* Note that this can never be a cti.  No cti's go in the S pipeline.  */
+  id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, fast_p, 0);
+
+  /* Set sc/snc insns notion of where to skip to.  */
+  if (IDESC_SKIP_P (id))
+    SEM_SKIP_COMPILE (current_cpu, sc, 1);
+
+  /* Emit code to finish executing the semantics
+     (write back the results).  */
+  emit_par_finish (current_cpu, pc, sc + 2, sc, id, sc + 1, id2);
+
+  return id;
+}
+
+static INLINE const IDESC *
+emit_full_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
+		    SCACHE *sc, int trace_p, int profile_p)
+{
+  const IDESC *id,*id2;
+
+  /* Emit both insns, then emit a finisher-upper.
+     We speed things up by handling the second insn serially
+     [not parallelly].  Then the writeback only has to deal
+     with the first insn.  */
+  /* ??? Revisit to handle exceptions right.  */
+
+  @cpu@_emit_before (current_cpu, sc, pc, 1);
+
+  /* FIXME: No need to handle this parallelly if second is nop.  */
+  id = emit_16 (current_cpu, pc, insn >> 16, sc + 1, 0, 1);
+  sc[1].argbuf.trace_p = trace_p;
+  sc[1].argbuf.profile_p = profile_p;
+
+  @cpu@_emit_before (current_cpu, sc + 2, pc, 0);
+
+  /* Note that this can never be a cti.  No cti's go in the S pipeline.  */
+  id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 3, 0, 0);
+  sc[3].argbuf.trace_p = trace_p;
+  sc[3].argbuf.profile_p = profile_p;
+
+  /* Set sc/snc insns notion of where to skip to.  */
+  if (IDESC_SKIP_P (id))
+    SEM_SKIP_COMPILE (current_cpu, sc, 4);
+
+  /* Emit code to finish executing the semantics
+     (write back the results).  */
+  emit_par_finish (current_cpu, pc, sc + 4, sc + 1, id, sc + 3, id2);
+
+  @cpu@_emit_after (current_cpu, sc + 5, pc);
+
+  return id;
+}
+
+static INLINE const IDESC *
+emit_32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
+	 SCACHE *sc, int fast_p)
+{
+  ARGBUF *abuf = &sc->argbuf;
+  const IDESC *id = @cpu@_decode (current_cpu, pc,
+				  (USI) insn >> 16, insn, abuf);
+
+  @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+  return id;
+}
+
+static INLINE const IDESC *
+emit_full32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
+	     int trace_p, int profile_p)
+{
+  const IDESC *id;
+
+  @cpu@_emit_before (current_cpu, sc, pc, 1);
+  id = emit_32 (current_cpu, pc, insn, sc + 1, 0);
+  @cpu@_emit_after (current_cpu, sc + 2, pc);
+  sc[1].argbuf.trace_p = trace_p;
+  sc[1].argbuf.profile_p = profile_p;
+  return id;
+}
+
+EOF
+
+;;
+
+xinit)
+
+# Nothing needed.
+
+;;
+
+xextract-pbb)
+
+# Inputs:  current_cpu, pc, sc, max_insns, FAST_P
+# Outputs: sc, pc
+# sc must be left pointing past the last created entry.
+# pc must be left pointing past the last created entry.
+# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
+# to record the vpc of the cti insn.
+# SET_INSN_COUNT(n) must be called to record number of real insns.
+
+cat <<EOF
+{
+  const IDESC *idesc;
+  int icount = 0;
+
+  if ((pc & 3) != 0)
+    {
+      /* This occurs when single stepping and when compiling the not-taken
+	 part of conditional branches.  */
+      UHI insn = GETIMEMUHI (current_cpu, pc);
+      int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+      int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+      SCACHE *cti_sc; /* ??? tmp hack */
+
+      /* A parallel insn isn't allowed here, but we don't mind nops.
+	 ??? We need to wait until the insn is executed before signalling
+	 the error, for situations where such signalling is wanted.  */
+#if 0
+      if ((insn & 0x8000) != 0
+	  && (insn & 0x7fff) != 0x7000) /* parallel nops are ok */
+	sim_engine_invalid_insn (current_cpu, pc, 0);
+#endif
+
+      /* Only emit before/after handlers if necessary.  */
+      if (FAST_P || (! trace_p && ! profile_p))
+	{
+	  idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, FAST_P, 0);
+	  cti_sc = sc;
+	  ++sc;
+	  --max_insns;
+	}
+      else
+	{
+	  idesc = emit_full16 (current_cpu, pc, insn & 0x7fff, sc,
+			       trace_p, profile_p);
+	  cti_sc = sc + 1;
+	  sc += 3;
+	  max_insns -= 3;
+	}
+      ++icount;
+      pc += 2;
+      if (IDESC_CTI_P (idesc))
+	{
+	  SET_CTI_VPC (cti_sc);
+	  goto Finish;
+	}
+    }
+
+  /* There are two copies of the compiler: full(!fast) and fast.
+     The "full" case emits before/after handlers for each insn.
+     Having two copies of this code is a tradeoff, having one copy
+     seemed a bit more difficult to read (due to constantly testing
+     FAST_P).  ??? On the other hand, with address ranges we'll want to
+     omit before/after handlers for unwanted insns.  Having separate loops
+     for FAST/!FAST avoids constantly doing the test in the loop, but
+     typically FAST_P is a constant and such tests will get optimized out.  */
+
+  if (FAST_P)
+    {
+      while (max_insns > 0)
+	{
+	  USI insn = GETIMEMUSI (current_cpu, pc);
+	  if ((SI) insn < 0)
+	    {
+	      /* 32 bit insn */
+	      idesc = emit_32 (current_cpu, pc, insn, sc, 1);
+	      ++sc;
+	      --max_insns;
+	      ++icount;
+	      pc += 4;
+	      if (IDESC_CTI_P (idesc))
+		{
+		  SET_CTI_VPC (sc - 1);
+		  break;
+		}
+	    }
+	  else
+	    {
+	      if ((insn & 0x8000) != 0) /* parallel? */
+		{
+		  /* Yep.  Here's the "interesting" [sic] part.  */
+		  idesc = emit_parallel (current_cpu, pc, insn, sc, 1);
+		  sc += 3;
+		  max_insns -= 3;
+		  icount += 2;
+		  pc += 4;
+		  if (IDESC_CTI_P (idesc))
+		    {
+		      SET_CTI_VPC (sc - 3);
+		      break;
+		    }
+		}
+	      else /* 2 serial 16 bit insns */
+		{
+		  idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 1, 0);
+		  ++sc;
+		  --max_insns;
+		  ++icount;
+		  pc += 2;
+		  if (IDESC_CTI_P (idesc))
+		    {
+		      SET_CTI_VPC (sc - 1);
+		      break;
+		    }
+		  /* While we're guaranteed that there's room to extract the
+		     insn, when single stepping we can't; the pbb must stop
+		     after the first insn.  */
+		  if (max_insns == 0)
+		    break;
+		  idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 1, 0);
+		  ++sc;
+		  --max_insns;
+		  ++icount;
+		  pc += 2;
+		  if (IDESC_CTI_P (idesc))
+		    {
+		      SET_CTI_VPC (sc - 1);
+		      break;
+		    }
+		}
+	    }
+	}
+    }
+  else /* ! FAST_P */
+    {
+      while (max_insns > 0)
+	{
+	  USI insn = GETIMEMUSI (current_cpu, pc);
+	  int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+	  int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+	  SCACHE *cti_sc; /* ??? tmp hack */
+	  if ((SI) insn < 0)
+	    {
+	      /* 32 bit insn
+		 Only emit before/after handlers if necessary.  */
+	      if (trace_p || profile_p)
+		{
+		  idesc = emit_full32 (current_cpu, pc, insn, sc,
+				       trace_p, profile_p);
+		  cti_sc = sc + 1;
+		  sc += 3;
+		  max_insns -= 3;
+		}
+	      else
+		{
+		  idesc = emit_32 (current_cpu, pc, insn, sc, 0);
+		  cti_sc = sc;
+		  ++sc;
+		  --max_insns;
+		}
+	      ++icount;
+	      pc += 4;
+	      if (IDESC_CTI_P (idesc))
+		{
+		  SET_CTI_VPC (cti_sc);
+		  break;
+		}
+	    }
+	  else
+	    {
+	      if ((insn & 0x8000) != 0) /* parallel? */
+		{
+		  /* Yep.  Here's the "interesting" [sic] part.
+		     Only emit before/after handlers if necessary.  */
+		  if (trace_p || profile_p)
+		    {
+		      idesc = emit_full_parallel (current_cpu, pc, insn, sc,
+						  trace_p, profile_p);
+		      cti_sc = sc + 1;
+		      sc += 6;
+		      max_insns -= 6;
+		    }
+		  else
+		    {
+		      idesc = emit_parallel (current_cpu, pc, insn, sc, 0);
+		      cti_sc = sc;
+		      sc += 3;
+		      max_insns -= 3;
+		    }
+		  icount += 2;
+		  pc += 4;
+		  if (IDESC_CTI_P (idesc))
+		    {
+		      SET_CTI_VPC (cti_sc);
+		      break;
+		    }
+		}
+	      else /* 2 serial 16 bit insns */
+		{
+		  /* Only emit before/after handlers if necessary.  */
+		  if (trace_p || profile_p)
+		    {
+		      idesc = emit_full16 (current_cpu, pc, insn >> 16, sc,
+					   trace_p, profile_p);
+		      cti_sc = sc + 1;
+		      sc += 3;
+		      max_insns -= 3;
+		    }
+		  else
+		    {
+		      idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 0, 0);
+		      cti_sc = sc;
+		      ++sc;
+		      --max_insns;
+		    }
+		  ++icount;
+		  pc += 2;
+		  if (IDESC_CTI_P (idesc))
+		    {
+		      SET_CTI_VPC (cti_sc);
+		      break;
+		    }
+		  /* While we're guaranteed that there's room to extract the
+		     insn, when single stepping we can't; the pbb must stop
+		     after the first insn.  */
+		  if (max_insns <= 0)
+		    break;
+		  /* Use the same trace/profile address for the 2nd insn.
+		     Saves us having to compute it and they come in pairs
+		     anyway (e.g. can never branch to the 2nd insn).  */
+		  if (trace_p || profile_p)
+		    {
+		      idesc = emit_full16 (current_cpu, pc, insn & 0x7fff, sc,
+					   trace_p, profile_p);
+		      cti_sc = sc + 1;
+		      sc += 3;
+		      max_insns -= 3;
+		    }
+		  else
+		    {
+		      idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 0, 0);
+		      cti_sc = sc;
+		      ++sc;
+		      --max_insns;
+		    }
+		  ++icount;
+		  pc += 2;
+		  if (IDESC_CTI_P (idesc))
+		    {
+		      SET_CTI_VPC (cti_sc);
+		      break;
+		    }
+		}
+	    }
+	}
+    }
+
+ Finish:
+  SET_INSN_COUNT (icount);
+}
+EOF
+
+;;
+
+xfull-exec-pbb)
+
+# Inputs: current_cpu, vpc, FAST_P
+# Outputs: vpc
+# vpc is the virtual program counter.
+
+cat <<EOF
+#define DEFINE_SWITCH
+#include "sem2-switch.c"
+EOF
+
+;;
+
+*)
+  echo "Invalid argument to mainloop.in: $1" >&2
+  exit 1
+  ;;
+
+esac
diff --git a/sim/m32r/model2.c b/sim/m32r/model2.c
new file mode 100644
index 0000000..7328ea4
--- /dev/null
+++ b/sim/m32r/model2.c
@@ -0,0 +1,3253 @@
+/* Simulator model support for m32r2f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU m32r2f
+#define WANT_CPU_M32R2F
+
+#include "sim-main.h"
+
+/* The profiling data is recorded here, but is accessed via the profiling
+   mechanism.  After all, this is information for profiling.  */
+
+#if WITH_PROFILE_MODEL_P
+
+/* Model handlers for each insn.  */
+
+static int
+model_m32r2_add (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_add3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_and (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_and3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_and3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_or (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_or3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_and3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_xor3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_and3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_addi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_addv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_addv3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_addx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bc8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl8.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bc24 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl24.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_beq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_beqz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bgez (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bgtz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_blez (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bltz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bnez (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bl8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl8.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bl24 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl24.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bcl8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl8.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bcl24 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl24.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl8.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl24.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bra8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl8.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bra24 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl24.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bncl8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl8.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bncl24 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bl24.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_cmp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_cmpi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_d.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_cmpu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_cmpui (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_d.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_cmpeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_cmpz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_div (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_divu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_rem (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_remu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_remh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_remuh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_remb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_remub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_divuh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_divb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_divub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_divh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_jc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    in_sr = FLD (in_sr);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_jnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    in_sr = FLD (in_sr);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_jl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    in_sr = FLD (in_sr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_jmp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jl.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    in_sr = FLD (in_sr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_ld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = 0;
+    INT out_dr = 0;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_ld_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = 0;
+    INT out_dr = 0;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_ldb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = 0;
+    INT out_dr = 0;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = 0;
+    INT out_dr = 0;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_ldh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = 0;
+    INT out_dr = 0;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = 0;
+    INT out_dr = 0;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_ldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = 0;
+    INT out_dr = 0;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = 0;
+    INT out_dr = 0;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_lduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = 0;
+    INT out_dr = 0;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = 0;
+    INT out_dr = 0;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = 0;
+    INT out_dr = 0;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_dr = FLD (in_sr);
+    out_dr = FLD (out_sr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_ld24 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld24.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_lock (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = 0;
+    INT out_dr = 0;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_machi_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_maclo_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_macwhi_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_macwlo_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_mul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_mulhi_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_mullo_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_mv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_mvfc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_src1);
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_src1);
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_mvtc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    referenced |= 1 << 0;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_neg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_nop (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_not (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_rac_dsi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_rte (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_seth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_seth.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_sll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_sll3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_slli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_slli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_sra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_sra3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_srai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_slli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_srl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_srl3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add3.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_srli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_slli.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_st (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = 0;
+    INT in_src2 = 0;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_st_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_d.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = 0;
+    INT in_src2 = 0;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_stb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = 0;
+    INT in_src2 = 0;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_stb_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_d.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = 0;
+    INT in_src2 = 0;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_sth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = 0;
+    INT in_src2 = 0;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_sth_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_d.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = 0;
+    INT in_src2 = 0;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_st_plus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = 0;
+    INT in_src2 = 0;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_dr = FLD (in_src2);
+    out_dr = FLD (out_src2);
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_sth_plus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = 0;
+    INT in_src2 = 0;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_dr = FLD (in_src2);
+    out_dr = FLD (out_src2);
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_stb_plus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = 0;
+    INT in_src2 = 0;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_dr = FLD (in_src2);
+    out_dr = FLD (out_src2);
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_st_minus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = 0;
+    INT in_src2 = 0;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_dr = FLD (in_src2);
+    out_dr = FLD (out_src2);
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_sub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_subv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_subx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    in_dr = FLD (in_dr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_trap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_trap.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_unlock (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = 0;
+    INT out_dr = 0;
+    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_satb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_sath (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_sat (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    out_dr = FLD (out_dr);
+    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+    referenced |= 1 << 2;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_sadd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_macwu1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_msblo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_mulwu1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_maclh1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_src1 = -1;
+    INT in_src2 = -1;
+    in_src1 = FLD (in_src1);
+    in_src2 = FLD (in_src2);
+    referenced |= 1 << 0;
+    referenced |= 1 << 1;
+    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_sc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_snc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_clrpsw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clrpsw.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_setpsw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clrpsw.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bset (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    referenced |= 1 << 0;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_bclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    referenced |= 1 << 0;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+static int
+model_m32r2_btst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bset.f
+  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+  const IDESC * UNUSED idesc = abuf->idesc;
+  int cycles = 0;
+  {
+    int referenced = 0;
+    int UNUSED insn_referenced = abuf->written;
+    INT in_sr = -1;
+    INT in_dr = -1;
+    INT out_dr = -1;
+    in_sr = FLD (in_sr);
+    referenced |= 1 << 0;
+    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
+  }
+  return cycles;
+#undef FLD
+}
+
+/* We assume UNIT_NONE == 0 because the tables don't always terminate
+   entries with it.  */
+
+/* Model timing data for `m32r2'.  */
+
+static const INSN_TIMING m32r2_timing[] = {
+  { M32R2F_INSN_X_INVALID, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_X_AFTER, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_X_BEFORE, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_X_CHAIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_X_BEGIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_ADD, model_m32r2_add, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_ADD3, model_m32r2_add3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_AND, model_m32r2_and, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_AND3, model_m32r2_and3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_OR, model_m32r2_or, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_OR3, model_m32r2_or3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_XOR, model_m32r2_xor, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_XOR3, model_m32r2_xor3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_ADDI, model_m32r2_addi, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_ADDV, model_m32r2_addv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_ADDV3, model_m32r2_addv3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_ADDX, model_m32r2_addx, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_BC8, model_m32r2_bc8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_BC24, model_m32r2_bc24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_BEQ, model_m32r2_beq, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
+  { M32R2F_INSN_BEQZ, model_m32r2_beqz, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
+  { M32R2F_INSN_BGEZ, model_m32r2_bgez, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
+  { M32R2F_INSN_BGTZ, model_m32r2_bgtz, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
+  { M32R2F_INSN_BLEZ, model_m32r2_blez, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
+  { M32R2F_INSN_BLTZ, model_m32r2_bltz, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
+  { M32R2F_INSN_BNEZ, model_m32r2_bnez, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
+  { M32R2F_INSN_BL8, model_m32r2_bl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_BL24, model_m32r2_bl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_BCL8, model_m32r2_bcl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_BCL24, model_m32r2_bcl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_BNC8, model_m32r2_bnc8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_BNC24, model_m32r2_bnc24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_BNE, model_m32r2_bne, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
+  { M32R2F_INSN_BRA8, model_m32r2_bra8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_BRA24, model_m32r2_bra24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_BNCL8, model_m32r2_bncl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_BNCL24, model_m32r2_bncl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_CMP, model_m32r2_cmp, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
+  { M32R2F_INSN_CMPI, model_m32r2_cmpi, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
+  { M32R2F_INSN_CMPU, model_m32r2_cmpu, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
+  { M32R2F_INSN_CMPUI, model_m32r2_cmpui, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
+  { M32R2F_INSN_CMPEQ, model_m32r2_cmpeq, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
+  { M32R2F_INSN_CMPZ, model_m32r2_cmpz, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
+  { M32R2F_INSN_DIV, model_m32r2_div, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
+  { M32R2F_INSN_DIVU, model_m32r2_divu, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
+  { M32R2F_INSN_REM, model_m32r2_rem, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
+  { M32R2F_INSN_REMU, model_m32r2_remu, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
+  { M32R2F_INSN_REMH, model_m32r2_remh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
+  { M32R2F_INSN_REMUH, model_m32r2_remuh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
+  { M32R2F_INSN_REMB, model_m32r2_remb, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
+  { M32R2F_INSN_REMUB, model_m32r2_remub, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
+  { M32R2F_INSN_DIVUH, model_m32r2_divuh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
+  { M32R2F_INSN_DIVB, model_m32r2_divb, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
+  { M32R2F_INSN_DIVUB, model_m32r2_divub, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
+  { M32R2F_INSN_DIVH, model_m32r2_divh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
+  { M32R2F_INSN_JC, model_m32r2_jc, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_JNC, model_m32r2_jnc, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_JL, model_m32r2_jl, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_JMP, model_m32r2_jmp, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
+  { M32R2F_INSN_LD, model_m32r2_ld, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
+  { M32R2F_INSN_LD_D, model_m32r2_ld_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
+  { M32R2F_INSN_LDB, model_m32r2_ldb, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
+  { M32R2F_INSN_LDB_D, model_m32r2_ldb_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
+  { M32R2F_INSN_LDH, model_m32r2_ldh, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
+  { M32R2F_INSN_LDH_D, model_m32r2_ldh_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
+  { M32R2F_INSN_LDUB, model_m32r2_ldub, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
+  { M32R2F_INSN_LDUB_D, model_m32r2_ldub_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
+  { M32R2F_INSN_LDUH, model_m32r2_lduh, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
+  { M32R2F_INSN_LDUH_D, model_m32r2_lduh_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
+  { M32R2F_INSN_LD_PLUS, model_m32r2_ld_plus, { { (int) UNIT_M32R2_U_LOAD, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
+  { M32R2F_INSN_LD24, model_m32r2_ld24, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_LDI8, model_m32r2_ldi8, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_LDI16, model_m32r2_ldi16, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_LOCK, model_m32r2_lock, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
+  { M32R2F_INSN_MACHI_A, model_m32r2_machi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
+  { M32R2F_INSN_MACLO_A, model_m32r2_maclo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
+  { M32R2F_INSN_MACWHI_A, model_m32r2_macwhi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
+  { M32R2F_INSN_MACWLO_A, model_m32r2_macwlo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
+  { M32R2F_INSN_MUL, model_m32r2_mul, { { (int) UNIT_M32R2_U_EXEC, 1, 4 } } },
+  { M32R2F_INSN_MULHI_A, model_m32r2_mulhi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
+  { M32R2F_INSN_MULLO_A, model_m32r2_mullo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
+  { M32R2F_INSN_MULWHI_A, model_m32r2_mulwhi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
+  { M32R2F_INSN_MULWLO_A, model_m32r2_mulwlo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
+  { M32R2F_INSN_MV, model_m32r2_mv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_MVFACHI_A, model_m32r2_mvfachi_a, { { (int) UNIT_M32R2_U_EXEC, 1, 2 } } },
+  { M32R2F_INSN_MVFACLO_A, model_m32r2_mvfaclo_a, { { (int) UNIT_M32R2_U_EXEC, 1, 2 } } },
+  { M32R2F_INSN_MVFACMI_A, model_m32r2_mvfacmi_a, { { (int) UNIT_M32R2_U_EXEC, 1, 2 } } },
+  { M32R2F_INSN_MVFC, model_m32r2_mvfc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_MVTACHI_A, model_m32r2_mvtachi_a, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_MVTACLO_A, model_m32r2_mvtaclo_a, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_MVTC, model_m32r2_mvtc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_NEG, model_m32r2_neg, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_NOP, model_m32r2_nop, { { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
+  { M32R2F_INSN_NOT, model_m32r2_not, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_RAC_DSI, model_m32r2_rac_dsi, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
+  { M32R2F_INSN_RACH_DSI, model_m32r2_rach_dsi, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
+  { M32R2F_INSN_RTE, model_m32r2_rte, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SETH, model_m32r2_seth, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SLL, model_m32r2_sll, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SLL3, model_m32r2_sll3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SLLI, model_m32r2_slli, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SRA, model_m32r2_sra, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SRA3, model_m32r2_sra3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SRAI, model_m32r2_srai, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SRL, model_m32r2_srl, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SRL3, model_m32r2_srl3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SRLI, model_m32r2_srli, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_ST, model_m32r2_st, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } },
+  { M32R2F_INSN_ST_D, model_m32r2_st_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 } } },
+  { M32R2F_INSN_STB, model_m32r2_stb, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } },
+  { M32R2F_INSN_STB_D, model_m32r2_stb_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 } } },
+  { M32R2F_INSN_STH, model_m32r2_sth, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } },
+  { M32R2F_INSN_STH_D, model_m32r2_sth_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 } } },
+  { M32R2F_INSN_ST_PLUS, model_m32r2_st_plus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
+  { M32R2F_INSN_STH_PLUS, model_m32r2_sth_plus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
+  { M32R2F_INSN_STB_PLUS, model_m32r2_stb_plus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
+  { M32R2F_INSN_ST_MINUS, model_m32r2_st_minus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
+  { M32R2F_INSN_SUB, model_m32r2_sub, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SUBV, model_m32r2_subv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SUBX, model_m32r2_subx, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_TRAP, model_m32r2_trap, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_UNLOCK, model_m32r2_unlock, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
+  { M32R2F_INSN_SATB, model_m32r2_satb, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SATH, model_m32r2_sath, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SAT, model_m32r2_sat, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_PCMPBZ, model_m32r2_pcmpbz, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
+  { M32R2F_INSN_SADD, model_m32r2_sadd, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
+  { M32R2F_INSN_MACWU1, model_m32r2_macwu1, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
+  { M32R2F_INSN_MSBLO, model_m32r2_msblo, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
+  { M32R2F_INSN_MULWU1, model_m32r2_mulwu1, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
+  { M32R2F_INSN_MACLH1, model_m32r2_maclh1, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
+  { M32R2F_INSN_SC, model_m32r2_sc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SNC, model_m32r2_snc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_CLRPSW, model_m32r2_clrpsw, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_SETPSW, model_m32r2_setpsw, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_BSET, model_m32r2_bset, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_BCLR, model_m32r2_bclr, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+  { M32R2F_INSN_BTST, model_m32r2_btst, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
+};
+
+#endif /* WITH_PROFILE_MODEL_P */
+
+static void
+m32r2_model_init (SIM_CPU *cpu)
+{
+  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32R2_DATA));
+}
+
+#if WITH_PROFILE_MODEL_P
+#define TIMING_DATA(td) td
+#else
+#define TIMING_DATA(td) 0
+#endif
+
+static const MODEL m32r2_models[] =
+{
+  { "m32r2", & m32r2_mach, MODEL_M32R2, TIMING_DATA (& m32r2_timing[0]), m32r2_model_init },
+  { 0 }
+};
+
+/* The properties of this cpu's implementation.  */
+
+static const MACH_IMP_PROPERTIES m32r2f_imp_properties =
+{
+  sizeof (SIM_CPU),
+#if WITH_SCACHE
+  sizeof (SCACHE)
+#else
+  0
+#endif
+};
+
+
+static void
+m32r2f_prepare_run (SIM_CPU *cpu)
+{
+  if (CPU_IDESC (cpu) == NULL)
+    m32r2f_init_idesc_table (cpu);
+}
+
+static const CGEN_INSN *
+m32r2f_get_idata (SIM_CPU *cpu, int inum)
+{
+  return CPU_IDESC (cpu) [inum].idata;
+}
+
+static void
+m32r2_init_cpu (SIM_CPU *cpu)
+{
+  CPU_REG_FETCH (cpu) = m32r2f_fetch_register;
+  CPU_REG_STORE (cpu) = m32r2f_store_register;
+  CPU_PC_FETCH (cpu) = m32r2f_h_pc_get;
+  CPU_PC_STORE (cpu) = m32r2f_h_pc_set;
+  CPU_GET_IDATA (cpu) = m32r2f_get_idata;
+  CPU_MAX_INSNS (cpu) = M32R2F_INSN__MAX;
+  CPU_INSN_NAME (cpu) = cgen_insn_name;
+  CPU_FULL_ENGINE_FN (cpu) = m32r2f_engine_run_full;
+#if WITH_FAST
+  CPU_FAST_ENGINE_FN (cpu) = m32r2f_engine_run_fast;
+#else
+  CPU_FAST_ENGINE_FN (cpu) = m32r2f_engine_run_full;
+#endif
+}
+
+const MACH m32r2_mach =
+{
+  "m32r2", "m32r2", MACH_M32R2,
+  32, 32, & m32r2_models[0], & m32r2f_imp_properties,
+  m32r2_init_cpu,
+  m32r2f_prepare_run
+};
+
diff --git a/sim/m32r/sem2-switch.c b/sim/m32r/sem2-switch.c
new file mode 100644
index 0000000..82af4cd
--- /dev/null
+++ b/sim/m32r/sem2-switch.c
@@ -0,0 +1,6822 @@
+/* Simulator instruction semantics for m32r2f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifdef DEFINE_LABELS
+
+  /* The labels have the case they have because the enum of insn types
+     is all uppercase and in the non-stdc case the insn symbol is built
+     into the enum name.  */
+
+  static struct {
+    int index;
+    void *label;
+  } labels[] = {
+    { M32R2F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
+    { M32R2F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
+    { M32R2F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
+    { M32R2F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
+    { M32R2F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
+    { M32R2F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
+    { M32R2F_INSN_ADD, && case_sem_INSN_ADD },
+    { M32R2F_INSN_ADD3, && case_sem_INSN_ADD3 },
+    { M32R2F_INSN_AND, && case_sem_INSN_AND },
+    { M32R2F_INSN_AND3, && case_sem_INSN_AND3 },
+    { M32R2F_INSN_OR, && case_sem_INSN_OR },
+    { M32R2F_INSN_OR3, && case_sem_INSN_OR3 },
+    { M32R2F_INSN_XOR, && case_sem_INSN_XOR },
+    { M32R2F_INSN_XOR3, && case_sem_INSN_XOR3 },
+    { M32R2F_INSN_ADDI, && case_sem_INSN_ADDI },
+    { M32R2F_INSN_ADDV, && case_sem_INSN_ADDV },
+    { M32R2F_INSN_ADDV3, && case_sem_INSN_ADDV3 },
+    { M32R2F_INSN_ADDX, && case_sem_INSN_ADDX },
+    { M32R2F_INSN_BC8, && case_sem_INSN_BC8 },
+    { M32R2F_INSN_BC24, && case_sem_INSN_BC24 },
+    { M32R2F_INSN_BEQ, && case_sem_INSN_BEQ },
+    { M32R2F_INSN_BEQZ, && case_sem_INSN_BEQZ },
+    { M32R2F_INSN_BGEZ, && case_sem_INSN_BGEZ },
+    { M32R2F_INSN_BGTZ, && case_sem_INSN_BGTZ },
+    { M32R2F_INSN_BLEZ, && case_sem_INSN_BLEZ },
+    { M32R2F_INSN_BLTZ, && case_sem_INSN_BLTZ },
+    { M32R2F_INSN_BNEZ, && case_sem_INSN_BNEZ },
+    { M32R2F_INSN_BL8, && case_sem_INSN_BL8 },
+    { M32R2F_INSN_BL24, && case_sem_INSN_BL24 },
+    { M32R2F_INSN_BCL8, && case_sem_INSN_BCL8 },
+    { M32R2F_INSN_BCL24, && case_sem_INSN_BCL24 },
+    { M32R2F_INSN_BNC8, && case_sem_INSN_BNC8 },
+    { M32R2F_INSN_BNC24, && case_sem_INSN_BNC24 },
+    { M32R2F_INSN_BNE, && case_sem_INSN_BNE },
+    { M32R2F_INSN_BRA8, && case_sem_INSN_BRA8 },
+    { M32R2F_INSN_BRA24, && case_sem_INSN_BRA24 },
+    { M32R2F_INSN_BNCL8, && case_sem_INSN_BNCL8 },
+    { M32R2F_INSN_BNCL24, && case_sem_INSN_BNCL24 },
+    { M32R2F_INSN_CMP, && case_sem_INSN_CMP },
+    { M32R2F_INSN_CMPI, && case_sem_INSN_CMPI },
+    { M32R2F_INSN_CMPU, && case_sem_INSN_CMPU },
+    { M32R2F_INSN_CMPUI, && case_sem_INSN_CMPUI },
+    { M32R2F_INSN_CMPEQ, && case_sem_INSN_CMPEQ },
+    { M32R2F_INSN_CMPZ, && case_sem_INSN_CMPZ },
+    { M32R2F_INSN_DIV, && case_sem_INSN_DIV },
+    { M32R2F_INSN_DIVU, && case_sem_INSN_DIVU },
+    { M32R2F_INSN_REM, && case_sem_INSN_REM },
+    { M32R2F_INSN_REMU, && case_sem_INSN_REMU },
+    { M32R2F_INSN_REMH, && case_sem_INSN_REMH },
+    { M32R2F_INSN_REMUH, && case_sem_INSN_REMUH },
+    { M32R2F_INSN_REMB, && case_sem_INSN_REMB },
+    { M32R2F_INSN_REMUB, && case_sem_INSN_REMUB },
+    { M32R2F_INSN_DIVUH, && case_sem_INSN_DIVUH },
+    { M32R2F_INSN_DIVB, && case_sem_INSN_DIVB },
+    { M32R2F_INSN_DIVUB, && case_sem_INSN_DIVUB },
+    { M32R2F_INSN_DIVH, && case_sem_INSN_DIVH },
+    { M32R2F_INSN_JC, && case_sem_INSN_JC },
+    { M32R2F_INSN_JNC, && case_sem_INSN_JNC },
+    { M32R2F_INSN_JL, && case_sem_INSN_JL },
+    { M32R2F_INSN_JMP, && case_sem_INSN_JMP },
+    { M32R2F_INSN_LD, && case_sem_INSN_LD },
+    { M32R2F_INSN_LD_D, && case_sem_INSN_LD_D },
+    { M32R2F_INSN_LDB, && case_sem_INSN_LDB },
+    { M32R2F_INSN_LDB_D, && case_sem_INSN_LDB_D },
+    { M32R2F_INSN_LDH, && case_sem_INSN_LDH },
+    { M32R2F_INSN_LDH_D, && case_sem_INSN_LDH_D },
+    { M32R2F_INSN_LDUB, && case_sem_INSN_LDUB },
+    { M32R2F_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
+    { M32R2F_INSN_LDUH, && case_sem_INSN_LDUH },
+    { M32R2F_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
+    { M32R2F_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
+    { M32R2F_INSN_LD24, && case_sem_INSN_LD24 },
+    { M32R2F_INSN_LDI8, && case_sem_INSN_LDI8 },
+    { M32R2F_INSN_LDI16, && case_sem_INSN_LDI16 },
+    { M32R2F_INSN_LOCK, && case_sem_INSN_LOCK },
+    { M32R2F_INSN_MACHI_A, && case_sem_INSN_MACHI_A },
+    { M32R2F_INSN_MACLO_A, && case_sem_INSN_MACLO_A },
+    { M32R2F_INSN_MACWHI_A, && case_sem_INSN_MACWHI_A },
+    { M32R2F_INSN_MACWLO_A, && case_sem_INSN_MACWLO_A },
+    { M32R2F_INSN_MUL, && case_sem_INSN_MUL },
+    { M32R2F_INSN_MULHI_A, && case_sem_INSN_MULHI_A },
+    { M32R2F_INSN_MULLO_A, && case_sem_INSN_MULLO_A },
+    { M32R2F_INSN_MULWHI_A, && case_sem_INSN_MULWHI_A },
+    { M32R2F_INSN_MULWLO_A, && case_sem_INSN_MULWLO_A },
+    { M32R2F_INSN_MV, && case_sem_INSN_MV },
+    { M32R2F_INSN_MVFACHI_A, && case_sem_INSN_MVFACHI_A },
+    { M32R2F_INSN_MVFACLO_A, && case_sem_INSN_MVFACLO_A },
+    { M32R2F_INSN_MVFACMI_A, && case_sem_INSN_MVFACMI_A },
+    { M32R2F_INSN_MVFC, && case_sem_INSN_MVFC },
+    { M32R2F_INSN_MVTACHI_A, && case_sem_INSN_MVTACHI_A },
+    { M32R2F_INSN_MVTACLO_A, && case_sem_INSN_MVTACLO_A },
+    { M32R2F_INSN_MVTC, && case_sem_INSN_MVTC },
+    { M32R2F_INSN_NEG, && case_sem_INSN_NEG },
+    { M32R2F_INSN_NOP, && case_sem_INSN_NOP },
+    { M32R2F_INSN_NOT, && case_sem_INSN_NOT },
+    { M32R2F_INSN_RAC_DSI, && case_sem_INSN_RAC_DSI },
+    { M32R2F_INSN_RACH_DSI, && case_sem_INSN_RACH_DSI },
+    { M32R2F_INSN_RTE, && case_sem_INSN_RTE },
+    { M32R2F_INSN_SETH, && case_sem_INSN_SETH },
+    { M32R2F_INSN_SLL, && case_sem_INSN_SLL },
+    { M32R2F_INSN_SLL3, && case_sem_INSN_SLL3 },
+    { M32R2F_INSN_SLLI, && case_sem_INSN_SLLI },
+    { M32R2F_INSN_SRA, && case_sem_INSN_SRA },
+    { M32R2F_INSN_SRA3, && case_sem_INSN_SRA3 },
+    { M32R2F_INSN_SRAI, && case_sem_INSN_SRAI },
+    { M32R2F_INSN_SRL, && case_sem_INSN_SRL },
+    { M32R2F_INSN_SRL3, && case_sem_INSN_SRL3 },
+    { M32R2F_INSN_SRLI, && case_sem_INSN_SRLI },
+    { M32R2F_INSN_ST, && case_sem_INSN_ST },
+    { M32R2F_INSN_ST_D, && case_sem_INSN_ST_D },
+    { M32R2F_INSN_STB, && case_sem_INSN_STB },
+    { M32R2F_INSN_STB_D, && case_sem_INSN_STB_D },
+    { M32R2F_INSN_STH, && case_sem_INSN_STH },
+    { M32R2F_INSN_STH_D, && case_sem_INSN_STH_D },
+    { M32R2F_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
+    { M32R2F_INSN_STH_PLUS, && case_sem_INSN_STH_PLUS },
+    { M32R2F_INSN_STB_PLUS, && case_sem_INSN_STB_PLUS },
+    { M32R2F_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
+    { M32R2F_INSN_SUB, && case_sem_INSN_SUB },
+    { M32R2F_INSN_SUBV, && case_sem_INSN_SUBV },
+    { M32R2F_INSN_SUBX, && case_sem_INSN_SUBX },
+    { M32R2F_INSN_TRAP, && case_sem_INSN_TRAP },
+    { M32R2F_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
+    { M32R2F_INSN_SATB, && case_sem_INSN_SATB },
+    { M32R2F_INSN_SATH, && case_sem_INSN_SATH },
+    { M32R2F_INSN_SAT, && case_sem_INSN_SAT },
+    { M32R2F_INSN_PCMPBZ, && case_sem_INSN_PCMPBZ },
+    { M32R2F_INSN_SADD, && case_sem_INSN_SADD },
+    { M32R2F_INSN_MACWU1, && case_sem_INSN_MACWU1 },
+    { M32R2F_INSN_MSBLO, && case_sem_INSN_MSBLO },
+    { M32R2F_INSN_MULWU1, && case_sem_INSN_MULWU1 },
+    { M32R2F_INSN_MACLH1, && case_sem_INSN_MACLH1 },
+    { M32R2F_INSN_SC, && case_sem_INSN_SC },
+    { M32R2F_INSN_SNC, && case_sem_INSN_SNC },
+    { M32R2F_INSN_CLRPSW, && case_sem_INSN_CLRPSW },
+    { M32R2F_INSN_SETPSW, && case_sem_INSN_SETPSW },
+    { M32R2F_INSN_BSET, && case_sem_INSN_BSET },
+    { M32R2F_INSN_BCLR, && case_sem_INSN_BCLR },
+    { M32R2F_INSN_BTST, && case_sem_INSN_BTST },
+    { M32R2F_INSN_PAR_ADD, && case_sem_INSN_PAR_ADD },
+    { M32R2F_INSN_WRITE_ADD, && case_sem_INSN_WRITE_ADD },
+    { M32R2F_INSN_PAR_AND, && case_sem_INSN_PAR_AND },
+    { M32R2F_INSN_WRITE_AND, && case_sem_INSN_WRITE_AND },
+    { M32R2F_INSN_PAR_OR, && case_sem_INSN_PAR_OR },
+    { M32R2F_INSN_WRITE_OR, && case_sem_INSN_WRITE_OR },
+    { M32R2F_INSN_PAR_XOR, && case_sem_INSN_PAR_XOR },
+    { M32R2F_INSN_WRITE_XOR, && case_sem_INSN_WRITE_XOR },
+    { M32R2F_INSN_PAR_ADDI, && case_sem_INSN_PAR_ADDI },
+    { M32R2F_INSN_WRITE_ADDI, && case_sem_INSN_WRITE_ADDI },
+    { M32R2F_INSN_PAR_ADDV, && case_sem_INSN_PAR_ADDV },
+    { M32R2F_INSN_WRITE_ADDV, && case_sem_INSN_WRITE_ADDV },
+    { M32R2F_INSN_PAR_ADDX, && case_sem_INSN_PAR_ADDX },
+    { M32R2F_INSN_WRITE_ADDX, && case_sem_INSN_WRITE_ADDX },
+    { M32R2F_INSN_PAR_BC8, && case_sem_INSN_PAR_BC8 },
+    { M32R2F_INSN_WRITE_BC8, && case_sem_INSN_WRITE_BC8 },
+    { M32R2F_INSN_PAR_BL8, && case_sem_INSN_PAR_BL8 },
+    { M32R2F_INSN_WRITE_BL8, && case_sem_INSN_WRITE_BL8 },
+    { M32R2F_INSN_PAR_BCL8, && case_sem_INSN_PAR_BCL8 },
+    { M32R2F_INSN_WRITE_BCL8, && case_sem_INSN_WRITE_BCL8 },
+    { M32R2F_INSN_PAR_BNC8, && case_sem_INSN_PAR_BNC8 },
+    { M32R2F_INSN_WRITE_BNC8, && case_sem_INSN_WRITE_BNC8 },
+    { M32R2F_INSN_PAR_BRA8, && case_sem_INSN_PAR_BRA8 },
+    { M32R2F_INSN_WRITE_BRA8, && case_sem_INSN_WRITE_BRA8 },
+    { M32R2F_INSN_PAR_BNCL8, && case_sem_INSN_PAR_BNCL8 },
+    { M32R2F_INSN_WRITE_BNCL8, && case_sem_INSN_WRITE_BNCL8 },
+    { M32R2F_INSN_PAR_CMP, && case_sem_INSN_PAR_CMP },
+    { M32R2F_INSN_WRITE_CMP, && case_sem_INSN_WRITE_CMP },
+    { M32R2F_INSN_PAR_CMPU, && case_sem_INSN_PAR_CMPU },
+    { M32R2F_INSN_WRITE_CMPU, && case_sem_INSN_WRITE_CMPU },
+    { M32R2F_INSN_PAR_CMPEQ, && case_sem_INSN_PAR_CMPEQ },
+    { M32R2F_INSN_WRITE_CMPEQ, && case_sem_INSN_WRITE_CMPEQ },
+    { M32R2F_INSN_PAR_CMPZ, && case_sem_INSN_PAR_CMPZ },
+    { M32R2F_INSN_WRITE_CMPZ, && case_sem_INSN_WRITE_CMPZ },
+    { M32R2F_INSN_PAR_JC, && case_sem_INSN_PAR_JC },
+    { M32R2F_INSN_WRITE_JC, && case_sem_INSN_WRITE_JC },
+    { M32R2F_INSN_PAR_JNC, && case_sem_INSN_PAR_JNC },
+    { M32R2F_INSN_WRITE_JNC, && case_sem_INSN_WRITE_JNC },
+    { M32R2F_INSN_PAR_JL, && case_sem_INSN_PAR_JL },
+    { M32R2F_INSN_WRITE_JL, && case_sem_INSN_WRITE_JL },
+    { M32R2F_INSN_PAR_JMP, && case_sem_INSN_PAR_JMP },
+    { M32R2F_INSN_WRITE_JMP, && case_sem_INSN_WRITE_JMP },
+    { M32R2F_INSN_PAR_LD, && case_sem_INSN_PAR_LD },
+    { M32R2F_INSN_WRITE_LD, && case_sem_INSN_WRITE_LD },
+    { M32R2F_INSN_PAR_LDB, && case_sem_INSN_PAR_LDB },
+    { M32R2F_INSN_WRITE_LDB, && case_sem_INSN_WRITE_LDB },
+    { M32R2F_INSN_PAR_LDH, && case_sem_INSN_PAR_LDH },
+    { M32R2F_INSN_WRITE_LDH, && case_sem_INSN_WRITE_LDH },
+    { M32R2F_INSN_PAR_LDUB, && case_sem_INSN_PAR_LDUB },
+    { M32R2F_INSN_WRITE_LDUB, && case_sem_INSN_WRITE_LDUB },
+    { M32R2F_INSN_PAR_LDUH, && case_sem_INSN_PAR_LDUH },
+    { M32R2F_INSN_WRITE_LDUH, && case_sem_INSN_WRITE_LDUH },
+    { M32R2F_INSN_PAR_LD_PLUS, && case_sem_INSN_PAR_LD_PLUS },
+    { M32R2F_INSN_WRITE_LD_PLUS, && case_sem_INSN_WRITE_LD_PLUS },
+    { M32R2F_INSN_PAR_LDI8, && case_sem_INSN_PAR_LDI8 },
+    { M32R2F_INSN_WRITE_LDI8, && case_sem_INSN_WRITE_LDI8 },
+    { M32R2F_INSN_PAR_LOCK, && case_sem_INSN_PAR_LOCK },
+    { M32R2F_INSN_WRITE_LOCK, && case_sem_INSN_WRITE_LOCK },
+    { M32R2F_INSN_PAR_MACHI_A, && case_sem_INSN_PAR_MACHI_A },
+    { M32R2F_INSN_WRITE_MACHI_A, && case_sem_INSN_WRITE_MACHI_A },
+    { M32R2F_INSN_PAR_MACLO_A, && case_sem_INSN_PAR_MACLO_A },
+    { M32R2F_INSN_WRITE_MACLO_A, && case_sem_INSN_WRITE_MACLO_A },
+    { M32R2F_INSN_PAR_MACWHI_A, && case_sem_INSN_PAR_MACWHI_A },
+    { M32R2F_INSN_WRITE_MACWHI_A, && case_sem_INSN_WRITE_MACWHI_A },
+    { M32R2F_INSN_PAR_MACWLO_A, && case_sem_INSN_PAR_MACWLO_A },
+    { M32R2F_INSN_WRITE_MACWLO_A, && case_sem_INSN_WRITE_MACWLO_A },
+    { M32R2F_INSN_PAR_MUL, && case_sem_INSN_PAR_MUL },
+    { M32R2F_INSN_WRITE_MUL, && case_sem_INSN_WRITE_MUL },
+    { M32R2F_INSN_PAR_MULHI_A, && case_sem_INSN_PAR_MULHI_A },
+    { M32R2F_INSN_WRITE_MULHI_A, && case_sem_INSN_WRITE_MULHI_A },
+    { M32R2F_INSN_PAR_MULLO_A, && case_sem_INSN_PAR_MULLO_A },
+    { M32R2F_INSN_WRITE_MULLO_A, && case_sem_INSN_WRITE_MULLO_A },
+    { M32R2F_INSN_PAR_MULWHI_A, && case_sem_INSN_PAR_MULWHI_A },
+    { M32R2F_INSN_WRITE_MULWHI_A, && case_sem_INSN_WRITE_MULWHI_A },
+    { M32R2F_INSN_PAR_MULWLO_A, && case_sem_INSN_PAR_MULWLO_A },
+    { M32R2F_INSN_WRITE_MULWLO_A, && case_sem_INSN_WRITE_MULWLO_A },
+    { M32R2F_INSN_PAR_MV, && case_sem_INSN_PAR_MV },
+    { M32R2F_INSN_WRITE_MV, && case_sem_INSN_WRITE_MV },
+    { M32R2F_INSN_PAR_MVFACHI_A, && case_sem_INSN_PAR_MVFACHI_A },
+    { M32R2F_INSN_WRITE_MVFACHI_A, && case_sem_INSN_WRITE_MVFACHI_A },
+    { M32R2F_INSN_PAR_MVFACLO_A, && case_sem_INSN_PAR_MVFACLO_A },
+    { M32R2F_INSN_WRITE_MVFACLO_A, && case_sem_INSN_WRITE_MVFACLO_A },
+    { M32R2F_INSN_PAR_MVFACMI_A, && case_sem_INSN_PAR_MVFACMI_A },
+    { M32R2F_INSN_WRITE_MVFACMI_A, && case_sem_INSN_WRITE_MVFACMI_A },
+    { M32R2F_INSN_PAR_MVFC, && case_sem_INSN_PAR_MVFC },
+    { M32R2F_INSN_WRITE_MVFC, && case_sem_INSN_WRITE_MVFC },
+    { M32R2F_INSN_PAR_MVTACHI_A, && case_sem_INSN_PAR_MVTACHI_A },
+    { M32R2F_INSN_WRITE_MVTACHI_A, && case_sem_INSN_WRITE_MVTACHI_A },
+    { M32R2F_INSN_PAR_MVTACLO_A, && case_sem_INSN_PAR_MVTACLO_A },
+    { M32R2F_INSN_WRITE_MVTACLO_A, && case_sem_INSN_WRITE_MVTACLO_A },
+    { M32R2F_INSN_PAR_MVTC, && case_sem_INSN_PAR_MVTC },
+    { M32R2F_INSN_WRITE_MVTC, && case_sem_INSN_WRITE_MVTC },
+    { M32R2F_INSN_PAR_NEG, && case_sem_INSN_PAR_NEG },
+    { M32R2F_INSN_WRITE_NEG, && case_sem_INSN_WRITE_NEG },
+    { M32R2F_INSN_PAR_NOP, && case_sem_INSN_PAR_NOP },
+    { M32R2F_INSN_WRITE_NOP, && case_sem_INSN_WRITE_NOP },
+    { M32R2F_INSN_PAR_NOT, && case_sem_INSN_PAR_NOT },
+    { M32R2F_INSN_WRITE_NOT, && case_sem_INSN_WRITE_NOT },
+    { M32R2F_INSN_PAR_RAC_DSI, && case_sem_INSN_PAR_RAC_DSI },
+    { M32R2F_INSN_WRITE_RAC_DSI, && case_sem_INSN_WRITE_RAC_DSI },
+    { M32R2F_INSN_PAR_RACH_DSI, && case_sem_INSN_PAR_RACH_DSI },
+    { M32R2F_INSN_WRITE_RACH_DSI, && case_sem_INSN_WRITE_RACH_DSI },
+    { M32R2F_INSN_PAR_RTE, && case_sem_INSN_PAR_RTE },
+    { M32R2F_INSN_WRITE_RTE, && case_sem_INSN_WRITE_RTE },
+    { M32R2F_INSN_PAR_SLL, && case_sem_INSN_PAR_SLL },
+    { M32R2F_INSN_WRITE_SLL, && case_sem_INSN_WRITE_SLL },
+    { M32R2F_INSN_PAR_SLLI, && case_sem_INSN_PAR_SLLI },
+    { M32R2F_INSN_WRITE_SLLI, && case_sem_INSN_WRITE_SLLI },
+    { M32R2F_INSN_PAR_SRA, && case_sem_INSN_PAR_SRA },
+    { M32R2F_INSN_WRITE_SRA, && case_sem_INSN_WRITE_SRA },
+    { M32R2F_INSN_PAR_SRAI, && case_sem_INSN_PAR_SRAI },
+    { M32R2F_INSN_WRITE_SRAI, && case_sem_INSN_WRITE_SRAI },
+    { M32R2F_INSN_PAR_SRL, && case_sem_INSN_PAR_SRL },
+    { M32R2F_INSN_WRITE_SRL, && case_sem_INSN_WRITE_SRL },
+    { M32R2F_INSN_PAR_SRLI, && case_sem_INSN_PAR_SRLI },
+    { M32R2F_INSN_WRITE_SRLI, && case_sem_INSN_WRITE_SRLI },
+    { M32R2F_INSN_PAR_ST, && case_sem_INSN_PAR_ST },
+    { M32R2F_INSN_WRITE_ST, && case_sem_INSN_WRITE_ST },
+    { M32R2F_INSN_PAR_STB, && case_sem_INSN_PAR_STB },
+    { M32R2F_INSN_WRITE_STB, && case_sem_INSN_WRITE_STB },
+    { M32R2F_INSN_PAR_STH, && case_sem_INSN_PAR_STH },
+    { M32R2F_INSN_WRITE_STH, && case_sem_INSN_WRITE_STH },
+    { M32R2F_INSN_PAR_ST_PLUS, && case_sem_INSN_PAR_ST_PLUS },
+    { M32R2F_INSN_WRITE_ST_PLUS, && case_sem_INSN_WRITE_ST_PLUS },
+    { M32R2F_INSN_PAR_STH_PLUS, && case_sem_INSN_PAR_STH_PLUS },
+    { M32R2F_INSN_WRITE_STH_PLUS, && case_sem_INSN_WRITE_STH_PLUS },
+    { M32R2F_INSN_PAR_STB_PLUS, && case_sem_INSN_PAR_STB_PLUS },
+    { M32R2F_INSN_WRITE_STB_PLUS, && case_sem_INSN_WRITE_STB_PLUS },
+    { M32R2F_INSN_PAR_ST_MINUS, && case_sem_INSN_PAR_ST_MINUS },
+    { M32R2F_INSN_WRITE_ST_MINUS, && case_sem_INSN_WRITE_ST_MINUS },
+    { M32R2F_INSN_PAR_SUB, && case_sem_INSN_PAR_SUB },
+    { M32R2F_INSN_WRITE_SUB, && case_sem_INSN_WRITE_SUB },
+    { M32R2F_INSN_PAR_SUBV, && case_sem_INSN_PAR_SUBV },
+    { M32R2F_INSN_WRITE_SUBV, && case_sem_INSN_WRITE_SUBV },
+    { M32R2F_INSN_PAR_SUBX, && case_sem_INSN_PAR_SUBX },
+    { M32R2F_INSN_WRITE_SUBX, && case_sem_INSN_WRITE_SUBX },
+    { M32R2F_INSN_PAR_TRAP, && case_sem_INSN_PAR_TRAP },
+    { M32R2F_INSN_WRITE_TRAP, && case_sem_INSN_WRITE_TRAP },
+    { M32R2F_INSN_PAR_UNLOCK, && case_sem_INSN_PAR_UNLOCK },
+    { M32R2F_INSN_WRITE_UNLOCK, && case_sem_INSN_WRITE_UNLOCK },
+    { M32R2F_INSN_PAR_PCMPBZ, && case_sem_INSN_PAR_PCMPBZ },
+    { M32R2F_INSN_WRITE_PCMPBZ, && case_sem_INSN_WRITE_PCMPBZ },
+    { M32R2F_INSN_PAR_SADD, && case_sem_INSN_PAR_SADD },
+    { M32R2F_INSN_WRITE_SADD, && case_sem_INSN_WRITE_SADD },
+    { M32R2F_INSN_PAR_MACWU1, && case_sem_INSN_PAR_MACWU1 },
+    { M32R2F_INSN_WRITE_MACWU1, && case_sem_INSN_WRITE_MACWU1 },
+    { M32R2F_INSN_PAR_MSBLO, && case_sem_INSN_PAR_MSBLO },
+    { M32R2F_INSN_WRITE_MSBLO, && case_sem_INSN_WRITE_MSBLO },
+    { M32R2F_INSN_PAR_MULWU1, && case_sem_INSN_PAR_MULWU1 },
+    { M32R2F_INSN_WRITE_MULWU1, && case_sem_INSN_WRITE_MULWU1 },
+    { M32R2F_INSN_PAR_MACLH1, && case_sem_INSN_PAR_MACLH1 },
+    { M32R2F_INSN_WRITE_MACLH1, && case_sem_INSN_WRITE_MACLH1 },
+    { M32R2F_INSN_PAR_SC, && case_sem_INSN_PAR_SC },
+    { M32R2F_INSN_WRITE_SC, && case_sem_INSN_WRITE_SC },
+    { M32R2F_INSN_PAR_SNC, && case_sem_INSN_PAR_SNC },
+    { M32R2F_INSN_WRITE_SNC, && case_sem_INSN_WRITE_SNC },
+    { M32R2F_INSN_PAR_CLRPSW, && case_sem_INSN_PAR_CLRPSW },
+    { M32R2F_INSN_WRITE_CLRPSW, && case_sem_INSN_WRITE_CLRPSW },
+    { M32R2F_INSN_PAR_SETPSW, && case_sem_INSN_PAR_SETPSW },
+    { M32R2F_INSN_WRITE_SETPSW, && case_sem_INSN_WRITE_SETPSW },
+    { M32R2F_INSN_PAR_BTST, && case_sem_INSN_PAR_BTST },
+    { M32R2F_INSN_WRITE_BTST, && case_sem_INSN_WRITE_BTST },
+    { 0, 0 }
+  };
+  int i;
+
+  for (i = 0; labels[i].label != 0; ++i)
+    {
+#if FAST_P
+      CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+#else
+      CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+#endif
+    }
+
+#undef DEFINE_LABELS
+#endif /* DEFINE_LABELS */
+
+#ifdef DEFINE_SWITCH
+
+/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
+   off frills like tracing and profiling.  */
+/* FIXME: A better way would be to have TRACE_RESULT check for something
+   that can cause it to be optimized out.  Another way would be to emit
+   special handlers into the instruction "stream".  */
+
+#if FAST_P
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#endif
+
+#undef GET_ATTR
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+#else
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
+#endif
+
+{
+
+#if WITH_SCACHE_PBB
+
+/* Branch to next handler without going around main loop.  */
+#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
+SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
+
+#else /* ! WITH_SCACHE_PBB */
+
+#define NEXT(vpc) BREAK (sem)
+#ifdef __GNUC__
+#if FAST_P
+  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
+#else
+  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
+#endif
+#else
+  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
+#endif
+
+#endif /* ! WITH_SCACHE_PBB */
+
+    {
+
+  CASE (sem, INSN_X_INVALID) : /* --invalid-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+    /* Update the recorded pc in the cpu state struct.
+       Only necessary for WITH_SCACHE case, but to avoid the
+       conditional compilation ....  */
+    SET_H_PC (pc);
+    /* Virtual insns have zero size.  Overwrite vpc with address of next insn
+       using the default-insn-bitsize spec.  When executing insns in parallel
+       we may want to queue the fault and continue execution.  */
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_AFTER) : /* --after-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_M32R2F
+    m32r2f_pbb_after (current_cpu, sem_arg);
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_BEFORE) : /* --before-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_M32R2F
+    m32r2f_pbb_before (current_cpu, sem_arg);
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_M32R2F
+#ifdef DEFINE_SWITCH
+    vpc = m32r2f_pbb_cti_chain (current_cpu, sem_arg,
+			       pbb_br_type, pbb_br_npc);
+    BREAK (sem);
+#else
+    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
+    vpc = m32r2f_pbb_cti_chain (current_cpu, sem_arg,
+			       CPU_PBB_BR_TYPE (current_cpu),
+			       CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_CHAIN) : /* --chain-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_M32R2F
+    vpc = m32r2f_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+    BREAK (sem);
+#endif
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_X_BEGIN) : /* --begin-- */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  {
+#if WITH_SCACHE_PBB_M32R2F
+#if defined DEFINE_SWITCH || defined FAST_P
+    /* In the switch case FAST_P is a constant, allowing several optimizations
+       in any called inline functions.  */
+    vpc = m32r2f_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
+    vpc = m32r2f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+    vpc = m32r2f_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADD) : /* add $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_AND) : /* and $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_and3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_OR) : /* or $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_and3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_XOR) : /* xor $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_and3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI temp0;BI temp1;
+  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
+  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
+  {
+    SI opval = temp0;
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+}
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  SI temp0;BI temp1;
+  temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
+  temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
+  {
+    SI opval = temp0;
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+}
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI temp0;BI temp1;
+  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  {
+    SI opval = temp0;
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+}
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BC8) : /* bc.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+  {
+    USI opval = FLD (i_disp8);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BC24) : /* bc.l $disp24 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl24.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (CPU (h_cond)) {
+  {
+    USI opval = FLD (i_disp24);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
+  {
+    USI opval = FLD (i_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQSI (* FLD (i_src2), 0)) {
+  {
+    USI opval = FLD (i_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GESI (* FLD (i_src2), 0)) {
+  {
+    USI opval = FLD (i_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GTSI (* FLD (i_src2), 0)) {
+  {
+    USI opval = FLD (i_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LESI (* FLD (i_src2), 0)) {
+  {
+    USI opval = FLD (i_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (LTSI (* FLD (i_src2), 0)) {
+  {
+    USI opval = FLD (i_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_src2), 0)) {
+  {
+    USI opval = FLD (i_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BL8) : /* bl.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  {
+    SI opval = ADDSI (ANDSI (pc, -4), 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = FLD (i_disp8);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BL24) : /* bl.l $disp24 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl24.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+  {
+    SI opval = ADDSI (pc, 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = FLD (i_disp24);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BCL8) : /* bcl.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+{
+  {
+    SI opval = ADDSI (ANDSI (pc, -4), 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = FLD (i_disp8);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BCL24) : /* bcl.l $disp24 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl24.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (CPU (h_cond)) {
+{
+  {
+    SI opval = ADDSI (pc, 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = FLD (i_disp24);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+  {
+    USI opval = FLD (i_disp8);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl24.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (CPU (h_cond))) {
+  {
+    USI opval = FLD (i_disp24);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_src1), * FLD (i_src2))) {
+  {
+    USI opval = FLD (i_disp16);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = FLD (i_disp8);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl24.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    USI opval = FLD (i_disp24);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNCL8) : /* bncl.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+{
+  {
+    SI opval = ADDSI (ANDSI (pc, -4), 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = FLD (i_disp8);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BNCL24) : /* bncl.l $disp24 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl24.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NOTBI (CPU (h_cond))) {
+{
+  {
+    SI opval = ADDSI (pc, 4);
+    CPU (h_gr[((UINT) 14)]) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = FLD (i_disp24);
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_d.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_d.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPEQ) : /* cmpeq $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = EQSI (* FLD (i_src1), * FLD (i_src2));
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CMPZ) : /* cmpz $src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = EQSI (* FLD (i_src2), 0);
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIV) : /* div $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REM) : /* rem $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REMU) : /* remu $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REMH) : /* remh $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = MODSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REMUH) : /* remuh $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REMB) : /* remb $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = MODSI (EXTBISI (TRUNCSIBI (* FLD (i_dr))), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_REMUB) : /* remub $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIVUH) : /* divuh $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIVB) : /* divb $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = DIVSI (EXTBISI (TRUNCSIBI (* FLD (i_dr))), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIVUB) : /* divub $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_DIVH) : /* divh $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NESI (* FLD (i_sr), 0)) {
+  {
+    SI opval = DIVSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_JC) : /* jc $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_jl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+  {
+    USI opval = ANDSI (* FLD (i_sr), -4);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_JNC) : /* jnc $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_jl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+  {
+    USI opval = ANDSI (* FLD (i_sr), -4);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_JL) : /* jl $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_jl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI temp0;USI temp1;
+  temp0 = ADDSI (ANDSI (pc, -4), 4);
+  temp1 = ANDSI (* FLD (i_sr), -4);
+  {
+    SI opval = temp0;
+    CPU (h_gr[((UINT) 14)]) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = temp1;
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_JMP) : /* jmp $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_jl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = ANDSI (* FLD (i_sr), -4);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD) : /* ld $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI temp0;SI temp1;
+  temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
+  temp1 = ADDSI (* FLD (i_sr), 4);
+  {
+    SI opval = temp0;
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    SI opval = temp1;
+    * FLD (i_sr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld24.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = FLD (i_uimm24);
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = FLD (f_simm8);
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = FLD (f_simm16);
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  {
+    BI opval = 1;
+    CPU (h_lock) = opval;
+    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MACHI_A) : /* machi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
+    SET_H_ACCUMS (FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MACLO_A) : /* maclo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
+    SET_H_ACCUMS (FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MACWHI_A) : /* macwhi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));
+    SET_H_ACCUMS (FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MACWLO_A) : /* macwlo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));
+    SET_H_ACCUMS (FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MUL) : /* mul $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULHI_A) : /* mulhi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
+    SET_H_ACCUMS (FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULLO_A) : /* mullo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
+    SET_H_ACCUMS (FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))));
+    SET_H_ACCUMS (FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))));
+    SET_H_ACCUMS (FLD (f_acc), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MV) : /* mv $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_sr);
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MVFACHI_A) : /* mvfachi $dr,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MVFACLO_A) : /* mvfaclo $dr,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs)));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MVFACMI_A) : /* mvfacmi $dr,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GET_H_CR (FLD (f_r2));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MVTACHI_A) : /* mvtachi $src1,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
+    SET_H_ACCUMS (FLD (f_accs), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MVTACLO_A) : /* mvtaclo $src1,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
+    SET_H_ACCUMS (FLD (f_accs), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = * FLD (i_sr);
+    SET_H_CR (FLD (f_r1), opval);
+    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NEG) : /* neg $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = NEGSI (* FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOP) : /* nop */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_NOT) : /* not $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = INVSI (* FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_RAC_DSI) : /* rac $accd,$accs,$imm1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  DI tmp_tmp1;
+  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
+  {
+    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
+    SET_H_ACCUMS (FLD (f_accd), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+}
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_RACH_DSI) : /* rach $accd,$accs,$imm1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  DI tmp_tmp1;
+  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
+  {
+    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));
+    SET_H_ACCUMS (FLD (f_accd), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+}
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_RTE) : /* rte */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  {
+    USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+  {
+    USI opval = GET_H_CR (((UINT) 14));
+    SET_H_CR (((UINT) 6), opval);
+    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+  }
+  {
+    UQI opval = CPU (h_bpsw);
+    SET_H_PSW (opval);
+    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
+  }
+  {
+    UQI opval = CPU (h_bbpsw);
+    CPU (h_bpsw) = opval;
+    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
+  }
+}
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_seth.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (FLD (f_hi16), 16);
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SLL) : /* sll $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_slli.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SRA) : /* sra $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_slli.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SRL) : /* srl $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add3.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_slli.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST) : /* st $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_d.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = * FLD (i_src1);
+    SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_d.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    QI opval = * FLD (i_src1);
+    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    HI opval = * FLD (i_src1);
+    SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_d.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    HI opval = * FLD (i_src1);
+    SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI tmp_new_src2;
+  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
+  {
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = tmp_new_src2;
+    * FLD (i_src2) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STH_PLUS) : /* sth $src1,@$src2+ */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  HI tmp_new_src2;
+  {
+    HI opval = * FLD (i_src1);
+    SETMEMHI (current_cpu, pc, tmp_new_src2, opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  tmp_new_src2 = ADDSI (* FLD (i_src2), 2);
+  {
+    SI opval = tmp_new_src2;
+    * FLD (i_src2) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_STB_PLUS) : /* stb $src1,@$src2+ */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  QI tmp_new_src2;
+  {
+    QI opval = * FLD (i_src1);
+    SETMEMQI (current_cpu, pc, tmp_new_src2, opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  tmp_new_src2 = ADDSI (* FLD (i_src2), 1);
+  {
+    SI opval = tmp_new_src2;
+    * FLD (i_src2) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI tmp_new_src2;
+  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
+  {
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = tmp_new_src2;
+    * FLD (i_src2) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SUB) : /* sub $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI temp0;BI temp1;
+  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
+  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
+  {
+    SI opval = temp0;
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+}
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI temp0;BI temp1;
+  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  {
+    SI opval = temp0;
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+}
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_TRAP) : /* trap $uimm4 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_trap.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  SEM_BRANCH_INIT
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  {
+    USI opval = GET_H_CR (((UINT) 6));
+    SET_H_CR (((UINT) 14), opval);
+    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+  }
+  {
+    USI opval = ADDSI (pc, 4);
+    SET_H_CR (((UINT) 6), opval);
+    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+  }
+  {
+    UQI opval = CPU (h_bpsw);
+    CPU (h_bbpsw) = opval;
+    TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
+  }
+  {
+    UQI opval = GET_H_PSW ();
+    CPU (h_bpsw) = opval;
+    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
+  }
+  {
+    UQI opval = ANDQI (GET_H_PSW (), 128);
+    SET_H_PSW (opval);
+    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
+  }
+  {
+    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
+    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+if (CPU (h_lock)) {
+  {
+    SI opval = * FLD (i_src1);
+    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+}
+  {
+    BI opval = 0;
+    CPU (h_lock) = opval;
+    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SATB) : /* satb $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (GESI (* FLD (i_sr), 127)) ? (127) : (LESI (* FLD (i_sr), -128)) ? (-128) : (* FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SATH) : /* sath $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = (GESI (* FLD (i_sr), 32767)) ? (32767) : (LESI (* FLD (i_sr), -32768)) ? (-32768) : (* FLD (i_sr));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SAT) : /* sat $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    SI opval = ((CPU (h_cond)) ? (((LTSI (* FLD (i_sr), 0)) ? (2147483647) : (0x80000000))) : (* FLD (i_sr)));
+    * FLD (i_dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PCMPBZ) : /* pcmpbz $src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0);
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SADD) : /* sadd */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0)));
+    SET_H_ACCUMS (((UINT) 0), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MACWU1) : /* macwu1 $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);
+    SET_H_ACCUMS (((UINT) 1), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MSBLO) : /* msblo $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8);
+    SET_H_ACCUM (opval);
+    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MULWU1) : /* mulwu1 $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16);
+    SET_H_ACCUMS (((UINT) 1), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_MACLH1) : /* maclh1 $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8);
+    SET_H_ACCUMS (((UINT) 1), opval);
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SC) : /* sc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (ZEXTBISI (CPU (h_cond)))
+  SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SNC) : /* snc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (ZEXTBISI (NOTBI (CPU (h_cond))))
+  SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_CLRPSW) : /* clrpsw $uimm8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_clrpsw.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
+    SET_H_CR (((UINT) 0), opval);
+    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_SETPSW) : /* setpsw $uimm8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_clrpsw.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = FLD (f_uimm8);
+    SET_H_CR (((UINT) 0), opval);
+    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BSET) : /* bset $uimm3,@($slo16,$sr) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3))));
+    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BCLR) : /* bclr $uimm3,@($slo16,$sr) */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+  {
+    QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3)))));
+    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_BTST) : /* btst $uimm3,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bset.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
+    CPU (h_cond) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+
+#undef FLD
+}
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_ADD) : /* add $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_ADD) : /* add $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_AND) : /* and $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_AND) : /* and $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_OR) : /* or $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_OR) : /* or $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_XOR) : /* xor $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_XOR) : /* xor $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_ADDI) : /* addi $dr,$simm8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi.f
+#define OPRND(f) par_exec->operands.sfmt_addi.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_ADDI) : /* addi $dr,$simm8 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_addi.f
+#define OPRND(f) par_exec->operands.sfmt_addi.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_ADDV) : /* addv $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addv.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI temp0;BI temp1;
+  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
+  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
+  {
+    SI opval = temp0;
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_ADDV) : /* addv $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addv.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_cond) = OPRND (condbit);
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_ADDX) : /* addx $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addx.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI temp0;BI temp1;
+  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  {
+    SI opval = temp0;
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_ADDX) : /* addx $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addx.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_cond) = OPRND (condbit);
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_BC8) : /* bc.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bc8.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+  {
+    USI opval = FLD (i_disp8);
+    OPRND (pc) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_BC8) : /* bc.s $disp8 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bc8.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    SEM_BRANCH_INIT
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  if (written & (1 << 2))
+    {
+      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+    }
+
+  SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_BL8) : /* bl.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bl8.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  {
+    SI opval = ADDSI (ANDSI (pc, -4), 4);
+    OPRND (h_gr_SI_14) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = FLD (i_disp8);
+    OPRND (pc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_BL8) : /* bl.s $disp8 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bl8.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    SEM_BRANCH_INIT
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
+  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+  SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_BCL8) : /* bcl.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bcl8.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+{
+  {
+    SI opval = ADDSI (ANDSI (pc, -4), 4);
+    OPRND (h_gr_SI_14) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = FLD (i_disp8);
+    OPRND (pc) = opval;
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_BCL8) : /* bcl.s $disp8 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bcl8.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    SEM_BRANCH_INIT
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  if (written & (1 << 3))
+    {
+      CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
+    }
+  if (written & (1 << 4))
+    {
+      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+    }
+
+  SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_BNC8) : /* bnc.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bc8.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+  {
+    USI opval = FLD (i_disp8);
+    OPRND (pc) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_BNC8) : /* bnc.s $disp8 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bc8.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    SEM_BRANCH_INIT
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  if (written & (1 << 2))
+    {
+      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+    }
+
+  SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_BRA8) : /* bra.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bra8.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = FLD (i_disp8);
+    OPRND (pc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_BRA8) : /* bra.s $disp8 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bra8.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    SEM_BRANCH_INIT
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+  SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_BNCL8) : /* bncl.s $disp8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bcl8.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+{
+  {
+    SI opval = ADDSI (ANDSI (pc, -4), 4);
+    OPRND (h_gr_SI_14) = opval;
+    written |= (1 << 3);
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = FLD (i_disp8);
+    OPRND (pc) = opval;
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+}
+
+  abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_BNCL8) : /* bncl.s $disp8 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_bl8.f
+#define OPRND(f) par_exec->operands.sfmt_bcl8.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    SEM_BRANCH_INIT
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  if (written & (1 << 3))
+    {
+      CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
+    }
+  if (written & (1 << 4))
+    {
+      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+    }
+
+  SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_CMP) : /* cmp $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_CMP) : /* cmp $src1,$src2 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmp.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_CMPU) : /* cmpu $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_CMPU) : /* cmpu $src1,$src2 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmp.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_CMPEQ) : /* cmpeq $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = EQSI (* FLD (i_src1), * FLD (i_src2));
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_CMPEQ) : /* cmpeq $src1,$src2 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmp.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_CMPZ) : /* cmpz $src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmpz.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = EQSI (* FLD (i_src2), 0);
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_CMPZ) : /* cmpz $src2 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmpz.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_JC) : /* jc $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_jl.f
+#define OPRND(f) par_exec->operands.sfmt_jc.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (CPU (h_cond)) {
+  {
+    USI opval = ANDSI (* FLD (i_sr), -4);
+    OPRND (pc) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_JC) : /* jc $sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_jl.f
+#define OPRND(f) par_exec->operands.sfmt_jc.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    SEM_BRANCH_INIT
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  if (written & (1 << 2))
+    {
+      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+    }
+
+  SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_JNC) : /* jnc $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_jl.f
+#define OPRND(f) par_exec->operands.sfmt_jc.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (CPU (h_cond))) {
+  {
+    USI opval = ANDSI (* FLD (i_sr), -4);
+    OPRND (pc) = opval;
+    written |= (1 << 2);
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_JNC) : /* jnc $sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_jl.f
+#define OPRND(f) par_exec->operands.sfmt_jc.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    SEM_BRANCH_INIT
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  if (written & (1 << 2))
+    {
+      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+    }
+
+  SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_JL) : /* jl $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_jl.f
+#define OPRND(f) par_exec->operands.sfmt_jl.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI temp0;USI temp1;
+  temp0 = ADDSI (ANDSI (pc, -4), 4);
+  temp1 = ANDSI (* FLD (i_sr), -4);
+  {
+    SI opval = temp0;
+    OPRND (h_gr_SI_14) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    USI opval = temp1;
+    OPRND (pc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_JL) : /* jl $sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_jl.f
+#define OPRND(f) par_exec->operands.sfmt_jl.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    SEM_BRANCH_INIT
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
+  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+  SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_JMP) : /* jmp $sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_jl.f
+#define OPRND(f) par_exec->operands.sfmt_jmp.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = ANDSI (* FLD (i_sr), -4);
+    OPRND (pc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_JMP) : /* jmp $sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_jl.f
+#define OPRND(f) par_exec->operands.sfmt_jmp.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    SEM_BRANCH_INIT
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+  SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LD) : /* ld $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LD) : /* ld $dr,@$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LDB) : /* ldb $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ldb.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LDB) : /* ldb $dr,@$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ldb.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LDH) : /* ldh $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ldh.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LDH) : /* ldh $dr,@$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ldh.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LDUB) : /* ldub $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ldb.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LDUB) : /* ldub $dr,@$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ldb.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LDUH) : /* lduh $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ldh.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LDUH) : /* lduh $dr,@$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ldh.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LD_PLUS) : /* ld $dr,@$sr+ */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI temp0;SI temp1;
+  temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
+  temp1 = ADDSI (* FLD (i_sr), 4);
+  {
+    SI opval = temp0;
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    SI opval = temp1;
+    OPRND (sr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LD_PLUS) : /* ld $dr,@$sr+ */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_ld_plus.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+  * FLD (i_sr) = OPRND (sr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LDI8) : /* ldi8 $dr,$simm8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi.f
+#define OPRND(f) par_exec->operands.sfmt_ldi8.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = FLD (f_simm8);
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LDI8) : /* ldi8 $dr,$simm8 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_addi.f
+#define OPRND(f) par_exec->operands.sfmt_ldi8.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_LOCK) : /* lock $dr,@$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_lock.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  {
+    BI opval = 1;
+    OPRND (h_lock_BI) = opval;
+    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
+  }
+  {
+    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_LOCK) : /* lock $dr,@$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_lock.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+  CPU (h_lock) = OPRND (h_lock_BI);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MACHI_A) : /* machi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MACHI_A) : /* machi $src1,$src2,$acc */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MACLO_A) : /* maclo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MACLO_A) : /* maclo $src1,$src2,$acc */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MACWHI_A) : /* macwhi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MACWHI_A) : /* macwhi $src1,$src2,$acc */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MACWLO_A) : /* macwlo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MACWLO_A) : /* macwlo $src1,$src2,$acc */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_machi_a.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MUL) : /* mul $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MUL) : /* mul $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MULHI_A) : /* mulhi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MULHI_A) : /* mulhi $src1,$src2,$acc */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MULLO_A) : /* mullo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MULLO_A) : /* mullo $src1,$src2,$acc */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))));
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))));
+    OPRND (acc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_machi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MV) : /* mv $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mv.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_sr);
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MV) : /* mv $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mv.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MVFACHI_A) : /* mvfachi $dr,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MVFACHI_A) : /* mvfachi $dr,$accs */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MVFACLO_A) : /* mvfaclo $dr,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs)));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MVFACLO_A) : /* mvfaclo $dr,$accs */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MVFACMI_A) : /* mvfacmi $dr,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MVFACMI_A) : /* mvfacmi $dr,$accs */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MVFC) : /* mvfc $dr,$scr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mvfc.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = GET_H_CR (FLD (f_r2));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MVFC) : /* mvfc $dr,$scr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mvfc.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MVTACHI_A) : /* mvtachi $src1,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
+    OPRND (accs) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MVTACHI_A) : /* mvtachi $src1,$accs */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (FLD (f_accs), OPRND (accs));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MVTACLO_A) : /* mvtaclo $src1,$accs */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
+    OPRND (accs) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MVTACLO_A) : /* mvtaclo $src1,$accs */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
+#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (FLD (f_accs), OPRND (accs));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MVTC) : /* mvtc $sr,$dcr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mvtc.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    USI opval = * FLD (i_sr);
+    OPRND (dcr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MVTC) : /* mvtc $sr,$dcr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mvtc.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_CR (FLD (f_r1), OPRND (dcr));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_NEG) : /* neg $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mv.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = NEGSI (* FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_NEG) : /* neg $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mv.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_NOP) : /* nop */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_nop.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_NOP) : /* nop */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_nop.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_NOT) : /* not $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mv.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = INVSI (* FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_NOT) : /* not $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mv.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_RAC_DSI) : /* rac $accd,$accs,$imm1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  DI tmp_tmp1;
+  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
+  {
+    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
+    OPRND (accd) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_RAC_DSI) : /* rac $accd,$accs,$imm1 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (FLD (f_accd), OPRND (accd));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_RACH_DSI) : /* rach $accd,$accs,$imm1 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  DI tmp_tmp1;
+  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
+  {
+    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));
+    OPRND (accd) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_RACH_DSI) : /* rach $accd,$accs,$imm1 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_rac_dsi.f
+#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (FLD (f_accd), OPRND (accd));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_RTE) : /* rte */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_rte.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  {
+    USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
+    OPRND (pc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+  {
+    USI opval = GET_H_CR (((UINT) 14));
+    OPRND (h_cr_USI_6) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+  }
+  {
+    UQI opval = CPU (h_bpsw);
+    OPRND (h_psw_UQI) = opval;
+    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
+  }
+  {
+    UQI opval = CPU (h_bbpsw);
+    OPRND (h_bpsw_UQI) = opval;
+    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_RTE) : /* rte */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_rte.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    SEM_BRANCH_INIT
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_bpsw) = OPRND (h_bpsw_UQI);
+  SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6));
+  SET_H_PSW (OPRND (h_psw_UQI));
+  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+  SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SLL) : /* sll $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SLL) : /* sll $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SLLI) : /* slli $dr,$uimm5 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_slli.f
+#define OPRND(f) par_exec->operands.sfmt_slli.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SLLI) : /* slli $dr,$uimm5 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_slli.f
+#define OPRND(f) par_exec->operands.sfmt_slli.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SRA) : /* sra $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SRA) : /* sra $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SRAI) : /* srai $dr,$uimm5 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_slli.f
+#define OPRND(f) par_exec->operands.sfmt_slli.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SRAI) : /* srai $dr,$uimm5 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_slli.f
+#define OPRND(f) par_exec->operands.sfmt_slli.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SRL) : /* srl $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SRL) : /* srl $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SRLI) : /* srli $dr,$uimm5 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_slli.f
+#define OPRND(f) par_exec->operands.sfmt_slli.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SRLI) : /* srli $dr,$uimm5 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_slli.f
+#define OPRND(f) par_exec->operands.sfmt_slli.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_ST) : /* st $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_st.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = * FLD (i_src1);
+    OPRND (h_memory_SI_src2_idx) = * FLD (i_src2);
+    OPRND (h_memory_SI_src2) = opval;
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_ST) : /* st $src1,@$src2 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_st.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_memory_SI_src2));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_STB) : /* stb $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_stb.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    QI opval = * FLD (i_src1);
+    OPRND (h_memory_QI_src2_idx) = * FLD (i_src2);
+    OPRND (h_memory_QI_src2) = opval;
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_STB) : /* stb $src1,@$src2 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_stb.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_src2_idx), OPRND (h_memory_QI_src2));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_STH) : /* sth $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_sth.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    HI opval = * FLD (i_src1);
+    OPRND (h_memory_HI_src2_idx) = * FLD (i_src2);
+    OPRND (h_memory_HI_src2) = opval;
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_STH) : /* sth $src1,@$src2 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_sth.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_src2_idx), OPRND (h_memory_HI_src2));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_ST_PLUS) : /* st $src1,@+$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI tmp_new_src2;
+  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
+  {
+    SI opval = * FLD (i_src1);
+    OPRND (h_memory_SI_new_src2_idx) = tmp_new_src2;
+    OPRND (h_memory_SI_new_src2) = opval;
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = tmp_new_src2;
+    OPRND (src2) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_ST_PLUS) : /* st $src1,@+$src2 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_st_plus.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_memory_SI_new_src2));
+  * FLD (i_src2) = OPRND (src2);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_STH_PLUS) : /* sth $src1,@$src2+ */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_sth_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  HI tmp_new_src2;
+  {
+    HI opval = * FLD (i_src1);
+    OPRND (h_memory_HI_new_src2_idx) = tmp_new_src2;
+    OPRND (h_memory_HI_new_src2) = opval;
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  tmp_new_src2 = ADDSI (* FLD (i_src2), 2);
+  {
+    SI opval = tmp_new_src2;
+    OPRND (src2) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_STH_PLUS) : /* sth $src1,@$src2+ */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_sth_plus.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_new_src2_idx), OPRND (h_memory_HI_new_src2));
+  * FLD (i_src2) = OPRND (src2);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_STB_PLUS) : /* stb $src1,@$src2+ */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_stb_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  QI tmp_new_src2;
+  {
+    QI opval = * FLD (i_src1);
+    OPRND (h_memory_QI_new_src2_idx) = tmp_new_src2;
+    OPRND (h_memory_QI_new_src2) = opval;
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  tmp_new_src2 = ADDSI (* FLD (i_src2), 1);
+  {
+    SI opval = tmp_new_src2;
+    OPRND (src2) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_STB_PLUS) : /* stb $src1,@$src2+ */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_stb_plus.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_new_src2_idx), OPRND (h_memory_QI_new_src2));
+  * FLD (i_src2) = OPRND (src2);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_ST_MINUS) : /* st $src1,@-$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_st_plus.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI tmp_new_src2;
+  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
+  {
+    SI opval = * FLD (i_src1);
+    OPRND (h_memory_SI_new_src2_idx) = tmp_new_src2;
+    OPRND (h_memory_SI_new_src2) = opval;
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+  {
+    SI opval = tmp_new_src2;
+    OPRND (src2) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_ST_MINUS) : /* st $src1,@-$src2 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_st_plus.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_memory_SI_new_src2));
+  * FLD (i_src2) = OPRND (src2);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SUB) : /* sub $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SUB) : /* sub $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_add.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SUBV) : /* subv $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addv.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI temp0;BI temp1;
+  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
+  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
+  {
+    SI opval = temp0;
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SUBV) : /* subv $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addv.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_cond) = OPRND (condbit);
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SUBX) : /* subx $dr,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addx.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  SI temp0;BI temp1;
+  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
+  {
+    SI opval = temp0;
+    OPRND (dr) = opval;
+    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+  }
+  {
+    BI opval = temp1;
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SUBX) : /* subx $dr,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_add.f
+#define OPRND(f) par_exec->operands.sfmt_addx.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_cond) = OPRND (condbit);
+  * FLD (i_dr) = OPRND (dr);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_TRAP) : /* trap $uimm4 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_trap.f
+#define OPRND(f) par_exec->operands.sfmt_trap.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+  {
+    USI opval = GET_H_CR (((UINT) 6));
+    OPRND (h_cr_USI_14) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+  }
+  {
+    USI opval = ADDSI (pc, 4);
+    OPRND (h_cr_USI_6) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+  }
+  {
+    UQI opval = CPU (h_bpsw);
+    OPRND (h_bbpsw_UQI) = opval;
+    TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
+  }
+  {
+    UQI opval = GET_H_PSW ();
+    OPRND (h_bpsw_UQI) = opval;
+    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
+  }
+  {
+    UQI opval = ANDQI (GET_H_PSW (), 128);
+    OPRND (h_psw_UQI) = opval;
+    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
+  }
+  {
+    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
+    OPRND (pc) = opval;
+    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+  }
+}
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_TRAP) : /* trap $uimm4 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_trap.f
+#define OPRND(f) par_exec->operands.sfmt_trap.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    SEM_BRANCH_INIT
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_bbpsw) = OPRND (h_bbpsw_UQI);
+  CPU (h_bpsw) = OPRND (h_bpsw_UQI);
+  SET_H_CR (((UINT) 14), OPRND (h_cr_USI_14));
+  SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6));
+  SET_H_PSW (OPRND (h_psw_UQI));
+  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
+
+  SEM_BRANCH_FINI (vpc);
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_UNLOCK) : /* unlock $src1,@$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_unlock.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+if (CPU (h_lock)) {
+  {
+    SI opval = * FLD (i_src1);
+    OPRND (h_memory_SI_src2_idx) = * FLD (i_src2);
+    OPRND (h_memory_SI_src2) = opval;
+    written |= (1 << 4);
+    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+  }
+}
+  {
+    BI opval = 0;
+    OPRND (h_lock_BI) = opval;
+    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
+  }
+}
+
+  abuf->written = written;
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_UNLOCK) : /* unlock $src1,@$src2 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_unlock.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_lock) = OPRND (h_lock_BI);
+  if (written & (1 << 4))
+    {
+      SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_memory_SI_src2));
+    }
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_PCMPBZ) : /* pcmpbz $src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmpz.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0);
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_PCMPBZ) : /* pcmpbz $src2 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_cmpz.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SADD) : /* sadd */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_sadd.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0)));
+    OPRND (h_accums_DI_0) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SADD) : /* sadd */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_sadd.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (((UINT) 0), OPRND (h_accums_DI_0));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MACWU1) : /* macwu1 $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_macwu1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);
+    OPRND (h_accums_DI_1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MACWU1) : /* macwu1 $src1,$src2 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_macwu1.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MSBLO) : /* msblo $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_msblo.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8);
+    OPRND (accum) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MSBLO) : /* msblo $src1,$src2 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_msblo.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUM (OPRND (accum));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MULWU1) : /* mulwu1 $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mulwu1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16);
+    OPRND (h_accums_DI_1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MULWU1) : /* mulwu1 $src1,$src2 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_mulwu1.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_MACLH1) : /* maclh1 $src1,$src2 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_macwu1.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8);
+    OPRND (h_accums_DI_1) = opval;
+    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_MACLH1) : /* maclh1 $src1,$src2 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+#define OPRND(f) par_exec->operands.sfmt_macwu1.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SC) : /* sc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_sc.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (ZEXTBISI (CPU (h_cond)))
+  SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SC) : /* sc */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_sc.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SNC) : /* snc */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_sc.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (ZEXTBISI (NOTBI (CPU (h_cond))))
+  SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SNC) : /* snc */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.fmt_empty.f
+#define OPRND(f) par_exec->operands.sfmt_sc.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_CLRPSW) : /* clrpsw $uimm8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_clrpsw.f
+#define OPRND(f) par_exec->operands.sfmt_clrpsw.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
+    OPRND (h_cr_USI_0) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_CLRPSW) : /* clrpsw $uimm8 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_clrpsw.f
+#define OPRND(f) par_exec->operands.sfmt_clrpsw.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_SETPSW) : /* setpsw $uimm8 */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_clrpsw.f
+#define OPRND(f) par_exec->operands.sfmt_setpsw.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    SI opval = FLD (f_uimm8);
+    OPRND (h_cr_USI_0) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_SETPSW) : /* setpsw $uimm8 */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_clrpsw.f
+#define OPRND(f) par_exec->operands.sfmt_setpsw.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0));
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+  CASE (sem, INSN_PAR_BTST) : /* btst $uimm3,$sr */
+{
+  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bset.f
+#define OPRND(f) par_exec->operands.sfmt_btst.f
+  int UNUSED written = 0;
+  IADDR UNUSED pc = abuf->addr;
+  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+  {
+    BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
+    OPRND (condbit) = opval;
+    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
+  }
+
+#undef OPRND
+#undef FLD
+}
+  NEXT (vpc);
+
+CASE (sem, INSN_WRITE_BTST) : /* btst $uimm3,$sr */
+  {
+    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
+#define FLD(f) abuf->fields.sfmt_bset.f
+#define OPRND(f) par_exec->operands.sfmt_btst.f
+    int UNUSED written = abuf->written;
+    IADDR UNUSED pc = abuf->addr;
+    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+  CPU (h_cond) = OPRND (condbit);
+
+#undef OPRND
+#undef FLD
+  }
+  NEXT (vpc);
+
+
+    }
+  ENDSWITCH (sem) /* End of semantic switch.  */
+
+  /* At this point `vpc' contains the next insn to execute.  */
+}
+
+#undef DEFINE_SWITCH
+#endif /* DEFINE_SWITCH */