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authorKevin Buettner <kevinb@redhat.com>2000-02-16 04:11:25 +0000
committerKevin Buettner <kevinb@redhat.com>2000-02-16 04:11:25 +0000
commit5e35df8e620de35759c79da38c1a3c686072d1e5 (patch)
tree369e2ff0b5d0677ff94041a7775e43d8eaefce55
parente6f9e5140d81de60665cda044c8cd006058c0ada (diff)
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Fix wording regarding Intel's IA-64 architecture.
-rw-r--r--gdb/doc/ChangeLog5
-rw-r--r--gdb/doc/agentexpr.texi2
2 files changed, 6 insertions, 1 deletions
diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog
index e2422d5..e5b6e70 100644
--- a/gdb/doc/ChangeLog
+++ b/gdb/doc/ChangeLog
@@ -1,3 +1,8 @@
+2000-02-15 Kevin Buettner <kevinb@redhat.com>
+
+ * agentexpr.texi: Fix wording regarding Intel's IA-64
+ architecture.
+
2000-01-16 Tom Tromey <tromey@cygnus.com>
* gdb.texinfo (Breakpoints): Mention breakpoint ranges.
diff --git a/gdb/doc/agentexpr.texi b/gdb/doc/agentexpr.texi
index 4b790f5..5418667 100644
--- a/gdb/doc/agentexpr.texi
+++ b/gdb/doc/agentexpr.texi
@@ -798,7 +798,7 @@ When we add side-effects, we should add this.
@item Why does the @code{reg} bytecode take a 16-bit register number?
-Intel's IA64-architecture, Merced, has 128 general-purpose registers,
+Intel's IA-64 architecture has 128 general-purpose registers,
and 128 floating-point registers, and I'm sure it has some random
control registers.