Backport ARM patches from HEAD to binutils-csl-arm-2005q1-branch.

19 files changed, 542 insertions, 15 deletions

diff --git a/ChangeLog.csl b/ChangeLog.csl
new file mode 100644
index 0000000..daecaa7
--- /dev/null
+++ b/ChangeLog.csl
@@ -0,0 +1,58 @@
+2005-03-23  Jim Blandy  <jimb@redhat.com>
+
+	* config/tc-arm.c (arm_adjust_symtab): Fetch elf_sym's binding
+	attributes properly.
+
+2005-03-21  Nick Clifton  <nickc@redhat.com>
+
+	* gas/testsuite/gas/arm/iwmmxt.s: Update instructions that use the "never" value
+	in the conditional field to use "le" instead.  This is so that the
+	disassembler will disassemble them.
+	* gas/testsuite/gas/arm/iwmmxt.d: Update expected disassemblies.
+
+2005-03-18  Julian Brown  <julian@codesourcery.com>
+
+	* ld/scripttempl/armbpapi.sc (.rel.dyn): Add .rel.init_array,
+	.rel.fini_array.
+	(.rela.dyn): Add .rela.init_array, .rela.fini_array.
+	(SECTIONS): Add .rel.other, .rela.other, .reli.other after PLT relocs.
+
+2005-03-16  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* gas/configure.tgt: Set emulation for arm-*-eabi*.
+	* gas/config/tc-arm.c (meabi_flags): Check EABI_DEFAULT.
+	* gas/config/te-armeabi.h: New file.
+	* gas/config/te-armlinuxeabi.h (EABI_DEFAULT): Define.
+	* gas/config/te-symbian.h: Include "te-armeabi.h".
+
+2005-03-15  Zack Weinberg  <zack@codesourcery.com>
+
+	* gas/config/tc-arm.c (do_mla): Rename to do_mlas, take second
+	is_mls parameter; do not diagnose Rm==Rd when is_mls.
+	(do_mla, do_mls, five_bit_unsigned_immediate, bfci_lsb_and_width)
+	(do_bfc, do_bfi, do_bfx, do_rbit, do_mov16, do_ldsttv4): New functions.
+	(insns): Add ARMv6T2 instructions:
+	bfc bfi mls movw movt rbit sbfx ubfx ldrht ldrsht ldrsbt strht.
+	(arm_archs): Add V6T2 variants.
+
+2005-03-12  Zack Weinberg  <zack@codesourcery.com>
+
+	* gas/config/tc-arm.c (tinsns): Add ARMv6K instructions sev, wfe,
+	wfi, yield.
+
+	* opcodes/arm-dis.c (thumb_opcodes): Add ARMv6K instructions nop, sev,
+	wfe, wfi, yield.
+
+	* gas/testsuite/gas/arm/thumbv6k.d, gas/arm/thumbv6k.s: New dump test.
+	* gas/testsuite/gas/arm/arm.exp: Run it.
+
+2005-03-12  Zack Weinberg  <zack@codesourcery.com>
+
+	* opcodes/arm-dis.c (arm_opcodes): Document %E and %V.
+	Add entries for v6T2 ARM instructions:
+	bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
+	(print_insn_arm): Add support for %E and %V.
+
+	* include/opcode/arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
+	Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
+	and ARM_ARCH_V6ZKT2.
diff --git a/binutils/po/fr.gmo b/binutils/po/fr.gmo
index e92b6c8..eb0d177 100644
--- a/binutils/po/fr.gmo
+++ b/binutils/po/fr.gmo
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 6976d88..19faa62 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -159,7 +159,11 @@ static int march_fpu_opt = -1;
 static int mfpu_opt = -1;
 static int mfloat_abi_opt = -1;
 #ifdef OBJ_ELF
+# ifdef EABI_DEFAULT
+static int meabi_flags = EABI_DEFAULT;
+# else
 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
+# endif
 #endif
 
 /* This array holds the chars that always start a comment.  If the
@@ -2814,7 +2818,7 @@ do_mul (char * str)
 }
 
 static void
-do_mla (char * str)
+do_mlas (char * str, bfd_boolean is_mls)
 {
   int rd, rm;
 
@@ -2846,7 +2850,9 @@ do_mla (char * str)
       return;
     }
 
-  if (rm == rd)
+  /* This restriction does not apply to mls (nor to mla in v6, but
+     that's hard to detect at present).  */
+  if (rm == rd && !is_mls)
     as_tsktsk (_("rd and rm should be different in mla"));
 
   if (skip_past_comma (&str) == FAIL
@@ -2867,6 +2873,18 @@ do_mla (char * str)
   end_of_line (str);
 }
 
+static void
+do_mla (char *str)
+{
+  do_mlas (str, FALSE);
+}
+
+static void
+do_mls (char *str)
+{
+  do_mlas (str, TRUE);
+}
+
 /* Expects *str -> the characters "acc0", possibly with leading blanks.
    Advances *str to the next non-alphanumeric.
    Returns 0, or else FAIL (in which case sets inst.error).
@@ -4512,6 +4530,286 @@ do_cpsi (char * str)
   end_of_line (str);
 }
 
+/* ARM V6T2 bitfield manipulation instructions.  */
+
+static int
+five_bit_unsigned_immediate (char **str)
+{
+  expressionS expr;
+
+  skip_whitespace (*str);
+  if (!is_immediate_prefix (**str))
+    {
+      inst.error = _("immediate expression expected");
+      return -1;
+    }
+  (*str)++;
+  if (my_get_expression (&expr, str))
+    {
+      inst.error = _("bad expression");
+      return -1;
+    }
+  if (expr.X_op != O_constant)
+    {
+      inst.error = _("constant expression expected");
+      return -1;
+    }
+  if (expr.X_add_number < 0 || expr.X_add_number > 32)
+    {
+      inst.error = _("immediate value out of range");
+      return -1;
+    }
+  
+  return expr.X_add_number;
+}
+
+static void
+bfci_lsb_and_width (char *str)
+{
+  int lsb, width;
+
+  if ((lsb = five_bit_unsigned_immediate (&str)) == -1)
+    return;
+
+  if (skip_past_comma (&str) == FAIL)
+    {
+      inst.error = BAD_ARGS;
+      return;
+    }
+  if ((width = five_bit_unsigned_immediate (&str)) == -1)
+    return;
+
+  end_of_line (str);
+
+  if (width == 0 || lsb == 32)
+    {
+      inst.error = _("immediate value out of range");
+      return;
+    }
+  else if (width + lsb > 32)
+    {
+      inst.error = _("bit-field extends past end of register");
+      return;
+    }
+
+  /* Convert to LSB/MSB and write to register.  */
+  inst.instruction |= lsb << 7;
+  inst.instruction |= (width + lsb - 1) << 16;
+}
+
+static void
+do_bfc (char *str)
+{
+  int rd;
+
+  /* Rd.  */
+  skip_whitespace (str);
+  if (((rd = reg_required_here (&str, 12)) == FAIL)
+      || (skip_past_comma (&str) == FAIL))
+    {
+      inst.error = BAD_ARGS;
+      return;
+    }
+  else if (rd == REG_PC)
+    {
+      inst.error = BAD_PC;
+      return;
+    }
+
+  bfci_lsb_and_width (str);
+}
+
+static void
+do_bfi (char *str)
+{
+  int rd, rm;
+
+  /* Rd.  */
+  skip_whitespace (str);
+  if (((rd = reg_required_here (&str, 12)) == FAIL)
+      || (skip_past_comma (&str) == FAIL))
+    {
+      inst.error = BAD_ARGS;
+      return;
+    }
+  else if (rd == REG_PC)
+    {
+      inst.error = BAD_PC;
+      return;
+    }
+
+  /* Rm.  Accept #0 in this position as an alternative syntax for bfc.  */
+  skip_whitespace (str);
+  if (is_immediate_prefix (*str))
+    {
+      expressionS expr;
+      str++;
+      if (my_get_expression (&expr, &str))
+	{
+	  inst.error = _("bad expression");
+	  return;
+	}
+      if (expr.X_op != O_constant)
+	{
+	  inst.error = _("constant expression expected");
+	  return;
+	}
+      if (expr.X_add_number != 0)
+	{
+	  inst.error = _("immediate value out of range");
+	  return;
+	}
+      inst.instruction |= 0x0000000f;  /* Rm = PC -> bfc, not bfi.  */
+    }
+  else
+    {
+      if ((rm = reg_required_here (&str, 0)) == FAIL)
+	{
+	  inst.error = BAD_ARGS;
+	  return;
+	}
+      else if (rm == REG_PC)
+	{
+	  inst.error = BAD_PC;
+	  return;
+	}
+    }
+  if (skip_past_comma (&str) == FAIL)
+    {
+      inst.error = BAD_ARGS;
+      return;
+    }
+
+  bfci_lsb_and_width (str);
+}
+
+static void
+do_bfx (char *str)
+{
+  int lsb, width;
+
+  /* Rd.  */
+  skip_whitespace (str);
+  if (reg_required_here (&str, 12) == FAIL
+      || skip_past_comma (&str) == FAIL)
+    {
+      inst.error = BAD_ARGS;
+      return;
+    }
+
+  /* Rm.  */
+  skip_whitespace (str);
+  if (reg_required_here (&str, 0) == FAIL
+      || skip_past_comma (&str) == FAIL)
+    {
+      inst.error = BAD_ARGS;
+      return;
+    }
+
+  if ((lsb = five_bit_unsigned_immediate (&str)) == -1)
+    return;
+
+  if (skip_past_comma (&str) == FAIL)
+    {
+      inst.error = BAD_ARGS;
+      return;
+    }
+  if ((width = five_bit_unsigned_immediate (&str)) == -1)
+    return;
+
+  end_of_line (str);
+
+  if (width == 0 || lsb == 32)
+    {
+      inst.error = _("immediate value out of range");
+      return;
+    }
+  else if (width + lsb > 32)
+    {
+      inst.error = _("bit-field extends past end of register");
+      return;
+    }
+
+  inst.instruction |= lsb << 7;
+  inst.instruction |= (width - 1) << 16;
+}
+
+static void
+do_rbit (char *str)
+{
+  /* Rd.  */
+  skip_whitespace (str);
+  if (reg_required_here (&str, 12) == FAIL
+      || skip_past_comma (&str) == FAIL)
+    {
+      inst.error = BAD_ARGS;
+      return;
+    }
+
+  /* Rm.  */
+  skip_whitespace (str);
+  if (reg_required_here (&str, 0) == FAIL)
+    {
+      inst.error = BAD_ARGS;
+      return;
+    }
+
+  end_of_line (str);
+}
+
+/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>.  */
+static void
+do_mov16 (char *str)
+{
+  int rd;
+  expressionS expr;
+
+  /* Rd.  */
+  skip_whitespace (str);
+  if (((rd = reg_required_here (&str, 12)) == FAIL)
+      || (skip_past_comma (&str) == FAIL))
+    {
+      inst.error = BAD_ARGS;
+      return;
+    }
+  else if (rd == REG_PC)
+    {
+      inst.error = BAD_PC;
+      return;
+    }
+
+  /* Imm16.  */
+  skip_whitespace (str);
+  if (!is_immediate_prefix (*str))
+    {
+      inst.error = _("immediate expression expected");
+      return;
+    }
+  str++;
+  if (my_get_expression (&expr, &str))
+    {
+      inst.error = _("bad expression");
+      return;
+    }
+  if (expr.X_op != O_constant)
+    {
+      inst.error = _("constant expression expected");
+      return;
+    }
+  if (expr.X_add_number < 0 || expr.X_add_number > 65535)
+    {
+      inst.error = _("immediate value out of range");
+      return;
+    }
+
+  end_of_line (str);
+
+  /* The value is in two pieces: 0:11, 16:19.  */
+  inst.instruction |= (expr.X_add_number & 0x00000fff);
+  inst.instruction |= (expr.X_add_number & 0x0000f000) << 4;
+}
+  
+
 /* THUMB V5 breakpoint instruction (argument parse)
 	BKPT <immed_8>.  */
 
@@ -6517,6 +6815,84 @@ do_ldstv4 (char * str)
   end_of_line (str);
 }
 
+static void
+do_ldsttv4 (char * str)
+{
+  int conflict_reg;
+
+  skip_whitespace (str);
+
+  if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
+    {
+      if (!inst.error)
+	inst.error = BAD_ARGS;
+      return;
+    }
+
+  if (skip_past_comma (& str) == FAIL)
+    {
+      inst.error = _("address expected");
+      return;
+    }
+
+  if (*str == '[')
+    {
+      int reg;
+
+      str++;
+
+      skip_whitespace (str);
+
+      if ((reg = reg_required_here (&str, 16)) == FAIL)
+	return;
+
+      /* ldrt/strt always use post-indexed addressing, so if the base is
+	 the same as Rd, we warn.  */
+      if (conflict_reg == reg)
+	as_warn (_("%s register same as write-back base"),
+		 ((inst.instruction & LOAD_BIT)
+		  ? _("destination") : _("source")));
+
+      skip_whitespace (str);
+
+      if (*str == ']')
+	{
+	  str ++;
+
+	  if (skip_past_comma (&str) == SUCCESS)
+	    {
+	      /* [Rn],... (post inc)  */
+	      if (ldst_extend_v4 (&str) == FAIL)
+		return;
+	    }
+	  else
+	    {
+	      /* [Rn]  */
+	      skip_whitespace (str);
+
+	      /* Skip a write-back '!'.  */
+	      if (*str == '!')
+		str++;
+
+	      inst.instruction |= (INDEX_UP|HWOFFSET_IMM);
+	    }
+	}
+      else
+	{
+	  inst.error = _("post-indexed expression expected");
+	  return;
+	}
+    }
+  else
+    {
+      inst.error = _("post-indexed expression expected");
+      return;
+    }
+
+  end_of_line (str);
+}
+
+
 static long
 reg_list (char ** strp)
 {
@@ -10014,6 +10390,21 @@ static const struct asm_opcode insns[] =
   /*  ARM V6Z.  */
   { "smi",       0xe1600070, 3,  ARM_EXT_V6Z,      do_smi},
 
+  /*  ARM V6T2.  */
+  { "bfc",       0xe7c0001f, 3,  ARM_EXT_V6T2,     do_bfc},
+  { "bfi",       0xe7c00010, 3,  ARM_EXT_V6T2,     do_bfi},
+  { "mls",       0xe0600090, 3,  ARM_EXT_V6T2,     do_mls},
+  { "movw",      0xe3000000, 4,  ARM_EXT_V6T2,     do_mov16},
+  { "movt",      0xe3400000, 4,  ARM_EXT_V6T2,     do_mov16},
+  { "rbit",      0xe3ff0f30, 4,  ARM_EXT_V6T2,     do_rbit},
+  { "sbfx",      0xe7a00050, 4,  ARM_EXT_V6T2,     do_bfx},
+  { "ubfx",      0xe7e00050, 4,  ARM_EXT_V6T2,     do_bfx},
+
+  { "ldrht",     0xe03000b0, 3,  ARM_EXT_V6T2,     do_ldsttv4},
+  { "ldrsht",    0xe03000f0, 3,  ARM_EXT_V6T2,     do_ldsttv4},
+  { "ldrsbt",    0xe03000d0, 3,  ARM_EXT_V6T2,     do_ldsttv4},
+  { "strht",     0xe02000b0, 3,  ARM_EXT_V6T2,     do_ldsttv4},
+
   /* Core FPA instruction set (V1).  */
   {"wfs",        0xee200110, 3,  FPU_FPA_EXT_V1,   do_fpa_ctrl},
   {"rfs",        0xee300110, 3,  FPU_FPA_EXT_V1,   do_fpa_ctrl},
@@ -10950,6 +11341,12 @@ static const struct thumb_opcode tinsns[] =
   {"sxtb",	0xb240,		2,	ARM_EXT_V6,  do_t_arit},
   {"uxth",	0xb280,		2,	ARM_EXT_V6,  do_t_arit},
   {"uxtb",	0xb2c0,		2,	ARM_EXT_V6,  do_t_arit},
+
+  /* ARM V6K.  */
+  {"sev",	0xbf40,		2,	ARM_EXT_V6K, do_empty},
+  {"wfe",	0xbf20,		2,	ARM_EXT_V6K, do_empty},
+  {"wfi",	0xbf30,		2,	ARM_EXT_V6K, do_empty},
+  {"yield",	0xbf10,		2,	ARM_EXT_V6K, do_empty},
 };
 
 void
@@ -12757,6 +13154,10 @@ static struct arm_arch_option_table arm_archs[] =
   {"armv6k",            ARM_ARCH_V6K,    FPU_ARCH_VFP},
   {"armv6z",            ARM_ARCH_V6Z,    FPU_ARCH_VFP},
   {"armv6zk",           ARM_ARCH_V6ZK,   FPU_ARCH_VFP},
+  {"armv6t2",		ARM_ARCH_V6T2,   FPU_ARCH_VFP},
+  {"armv6kt2",		ARM_ARCH_V6KT2,  FPU_ARCH_VFP},
+  {"armv6zt2",		ARM_ARCH_V6ZT2,  FPU_ARCH_VFP},
+  {"armv6zkt2",		ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
   {"xscale",		ARM_ARCH_XSCALE, FPU_ARCH_VFP},
   {"iwmmxt",		ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
   {NULL, 0, 0}
@@ -13302,7 +13703,7 @@ arm_adjust_symtab (void)
 	  elf_symbol_type * elf_sym;
 
 	  elf_sym = elf_symbol (symbol_get_bfdsym (sym));
-	  bind = ELF_ST_BIND (elf_sym);
+	  bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
 
 	  /* If it's a .thumb_func, declare it as so,
 	     otherwise tag label as .code 16.  */
diff --git a/gas/config/te-armlinuxeabi.h b/gas/config/te-armlinuxeabi.h
index e6abf01..b3f5f1e 100644
--- a/gas/config/te-armlinuxeabi.h
+++ b/gas/config/te-armlinuxeabi.h
@@ -2,3 +2,4 @@
 
 /* The EABI requires the use of VFP.  */
 #define FPU_DEFAULT FPU_ARCH_VFP_V2
+#define EABI_DEFAULT EF_ARM_EABI_VER4
diff --git a/gas/config/te-symbian.h b/gas/config/te-symbian.h
index 0522486..e609049 100644
--- a/gas/config/te-symbian.h
+++ b/gas/config/te-symbian.h
@@ -1,3 +1,3 @@
 #define TE_SYMBIAN 1
-#include "obj-elf.h"
 
+#include "te-armeabi.h"
diff --git a/gas/configure.tgt b/gas/configure.tgt
index 576e14e..f180b52 100644
--- a/gas/configure.tgt
+++ b/gas/configure.tgt
@@ -110,12 +110,12 @@ case ${generic_target} in
   arm-*-coff | thumb-*-coff)		fmt=coff ;;
   arm-*-rtems* | thumb-*-rtems*)	fmt=elf ;;
   arm-*-elf | thumb-*-elf)		fmt=elf ;;
-  arm-*-eabi*)				fmt=elf ;;
+  arm-*-eabi*)				fmt=elf em=armeabi ;;
   arm-*-symbianelf*)			fmt=elf em=symbian ;;
   arm-*-kaos*)				fmt=elf ;;
   arm-*-conix*)				fmt=elf ;;
   arm-*-linux*aout*)			fmt=aout em=linux ;;
-  arm-*-linux-gnueabi*)			fmt=elf  em=armlinuxeabi ;;	 
+  arm-*-linux-gnueabi*)			fmt=elf  em=armlinuxeabi ;;
   arm-*-linux-gnu*)			fmt=elf  em=linux ;;
   arm-*-uclinux*)			fmt=elf  em=linux ;;
   arm-*-netbsdelf*)                 	fmt=elf  em=nbsd ;;
diff --git a/gas/po/es.gmo b/gas/po/es.gmo
index 9497cdb..b43e80c 100644
--- a/gas/po/es.gmo
+++ b/gas/po/es.gmo
diff --git a/gas/po/tr.gmo b/gas/po/tr.gmo
index 1063539..fe95cfb 100644
--- a/gas/po/tr.gmo
+++ b/gas/po/tr.gmo
diff --git a/gas/testsuite/gas/arm/arm.exp b/gas/testsuite/gas/arm/arm.exp
index 872e62b..4ea6454 100644
--- a/gas/testsuite/gas/arm/arm.exp
+++ b/gas/testsuite/gas/arm/arm.exp
@@ -49,13 +49,16 @@ if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
     run_dump_test "reg-alias"
     run_dump_test "maverick"    
     run_dump_test "archv6"
+    run_dump_test "archv6t2"
     run_dump_test "thumbv6"
+    run_dump_test "thumbv6k"
     run_dump_test "arch6zk"
     
     run_errors_test "vfp-bad" "-mfpu=vfp" "VFP errors"
     run_errors_test "req" "-mcpu=arm7m" ".req errors"
     run_errors_test "armv1-bad" "-mcpu=arm7m" "ARM v1 errors"
     run_errors_test "r15-bad" "" "Invalid use of r15 errors"
+    run_errors_test "archv6t2-bad" "-march=armv6t2" "Invalid V6T2 instructions"
 
     if {[istarget *-*-*coff] || [istarget *-*-pe] || [istarget *-*-wince] ||
         [istarget *-*-*aout*] || [istarget *-*-netbsd] || [istarget *-*-riscix*]} then {
diff --git a/gas/testsuite/gas/arm/iwmmxt.d b/gas/testsuite/gas/arm/iwmmxt.d
index 7225a61..7ff62e4 100644
--- a/gas/testsuite/gas/arm/iwmmxt.d
+++ b/gas/testsuite/gas/arm/iwmmxt.d
@@ -46,7 +46,7 @@ Disassembly of section .text:
 0+98 <[^>]*> ee120184[ 	]+waddbus[ 	]+wr0, wr2, wr4
 0+9c <[^>]*> ee38618a[ 	]+waddbss[ 	]+wr6, wr8, wr10
 0+a0 <[^>]*> ee4ec18f[ 	]+waddh[ 	]+wr12, wr14, wr15
-0+a4 <[^>]*> fe5cd18b[ 	]+waddhusnv[ 	]+wr13, wr12, wr11
+0+a4 <[^>]*> de5cd18b[ 	]+waddhusle[ 	]+wr13, wr12, wr11
 0+a8 <[^>]*> 0e79a188[ 	]+waddhsseq[ 	]+wr10, wr9, wr8
 0+ac <[^>]*> 1e867185[ 	]+waddwne[ 	]+wr7, wr6, wr5
 0+b0 <[^>]*> ee934182[ 	]+waddwus[ 	]+wr4, wr3, wr2
@@ -87,7 +87,7 @@ Disassembly of section .text:
 0+13c <[^>]*> 5e443165[ 	]+wmaxuhpl[ 	]+wr3, wr4, wr5
 0+140 <[^>]*> 4e643165[ 	]+wmaxshmi[ 	]+wr3, wr4, wr5
 0+144 <[^>]*> ae843165[ 	]+wmaxuwge[ 	]+wr3, wr4, wr5
-0+148 <[^>]*> fea43165[ 	]+wmaxswnv[ 	]+wr3, wr4, wr5
+0+148 <[^>]*> dea43165[ 	]+wmaxswle[ 	]+wr3, wr4, wr5
 0+14c <[^>]*> 3e1c416a[ 	]+wminubcc[ 	]+wr4, wr12, wr10
 0+150 <[^>]*> ee3c416a[ 	]+wminsb[ 	]+wr4, wr12, wr10
 0+154 <[^>]*> 7e5c416a[ 	]+wminuhvc[ 	]+wr4, wr12, wr10
@@ -115,7 +115,7 @@ Disassembly of section .text:
 0+1ac <[^>]*> ee00212a[ 	]+wsadb[ 	]+wr2, wr0, wr10
 0+1b0 <[^>]*> ee40212a[ 	]+wsadh[ 	]+wr2, wr0, wr10
 0+1b4 <[^>]*> ee10212a[ 	]+wsadbz[ 	]+wr2, wr0, wr10
-0+1b8 <[^>]*> fe50212a[ 	]+wsadhznv[ 	]+wr2, wr0, wr10
+0+1b8 <[^>]*> de50212a[ 	]+wsadhzle[ 	]+wr2, wr0, wr10
 0+1bc <[^>]*> 0ef941eb[ 	]+wshufheq[ 	]+wr4, wr9, #251
 0+1c0 <[^>]*> ee592044[ 	]+wsllh[ 	]+wr2, wr9, wr4
 0+1c4 <[^>]*> ee992044[ 	]+wsllw[ 	]+wr2, wr9, wr4
diff --git a/gas/testsuite/gas/arm/iwmmxt.s b/gas/testsuite/gas/arm/iwmmxt.s
index b3e7a85..1aa433a 100644
--- a/gas/testsuite/gas/arm/iwmmxt.s
+++ b/gas/testsuite/gas/arm/iwmmxt.s
@@ -54,7 +54,7 @@ iwmmxt:
 	waddBUS		wr0,  wr2,  wr4
 	waddbssal	wr6,  wr8,  wr10
 	waddH		wr12, wr14, wr15
-	WADDHUSNV	wr13, wr12, wr11
+	WADDHUSLE	wr13, wr12, wr11
 	WADDHSSeq	wr10, wr9,  wr8
 	WADDWne		wr7,  wr6, wr5
 	waddwus		wr4,  wr3, wr2
@@ -104,7 +104,7 @@ iwmmxt:
 	wmaxuhpl	wr3, wr4, wr5
 	wmaxshmi	wr3, wr4, wr5
 	wmaxuwge	wr3, wr4, wr5
-	wmaxswnv	wr3, wr4, wr5
+	wmaxswle	wr3, wr4, wr5
 
 	wminubul	wr4, wr12, wr10
 	wminsb		wr4, wr12, wr10
@@ -139,7 +139,7 @@ iwmmxt:
 	wsadb		wr2, wr0, wr10
 	wsadhal		wr2, wr0, wr10
 	wsadbz		wr2, wr0, wr10
-	wsadhznv	wr2, wr0, wr10
+	wsadhzle	wr2, wr0, wr10
 
 	wshufheq	wr4, wr9, #251
 
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index dd90e2a..db36665 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -25,15 +25,16 @@
 #define ARM_EXT_V3	 0x00000008	/* MSR MRS.                */
 #define ARM_EXT_V3M	 0x00000010	/* Allow long multiplies.  */
 #define ARM_EXT_V4	 0x00000020	/* Allow half word loads.  */
-#define ARM_EXT_V4T	 0x00000040	/* Thumb v1.               */
+#define ARM_EXT_V4T	 0x00000040	/* Thumb.                  */
 #define ARM_EXT_V5	 0x00000080	/* Allow CLZ, etc.         */
-#define ARM_EXT_V5T	 0x00000100	/* Thumb v2.               */
+#define ARM_EXT_V5T	 0x00000100	/* Improved interworking.  */
 #define ARM_EXT_V5ExP	 0x00000200	/* DSP core set.           */
 #define ARM_EXT_V5E	 0x00000400	/* DSP Double transfers.   */
 #define ARM_EXT_V5J	 0x00000800	/* Jazelle extension.	   */
 #define ARM_EXT_V6       0x00001000     /* ARM V6.                 */
 #define ARM_EXT_V6K      0x00002000     /* ARM V6K.                */
 #define ARM_EXT_V6Z      0x00004000     /* ARM V6Z.                */
+#define ARM_EXT_V6T2	 0x00008000	/* Thumb-2.                */
 
 /* Co-processor space extensions.  */
 #define ARM_CEXT_XSCALE   0x00800000	/* Allow MIA etc.          */
@@ -65,6 +66,10 @@
 #define ARM_ARCH_V6K    (ARM_ARCH_V6    | ARM_EXT_V6K)
 #define ARM_ARCH_V6Z    (ARM_ARCH_V6    | ARM_EXT_V6Z)
 #define ARM_ARCH_V6ZK   (ARM_ARCH_V6    | ARM_EXT_V6K | ARM_EXT_V6Z)
+#define ARM_ARCH_V6T2   (ARM_ARCH_V6    | ARM_EXT_V6T2)
+#define ARM_ARCH_V6KT2  (ARM_ARCH_V6    | ARM_EXT_V6T2 | ARM_EXT_V6K)
+#define ARM_ARCH_V6ZT2  (ARM_ARCH_V6    | ARM_EXT_V6T2 | ARM_EXT_V6Z)
+#define ARM_ARCH_V6ZKT2 (ARM_ARCH_V6    | ARM_EXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z)
 
 /* Processors with specific extensions in the co-processor space.  */
 #define ARM_ARCH_XSCALE	(ARM_ARCH_V5TE	| ARM_CEXT_XSCALE)
diff --git a/ld/po/es.gmo b/ld/po/es.gmo
index 1a6a7b5..f3f1406 100644
--- a/ld/po/es.gmo
+++ b/ld/po/es.gmo
diff --git a/ld/po/fr.gmo b/ld/po/fr.gmo
index aa32a02..e67b1c1 100644
--- a/ld/po/fr.gmo
+++ b/ld/po/fr.gmo
diff --git a/ld/po/tr.gmo b/ld/po/tr.gmo
index a8b981b..96d567b 100644
--- a/ld/po/tr.gmo
+++ b/ld/po/tr.gmo
diff --git a/ld/scripttempl/armbpabi.sc b/ld/scripttempl/armbpabi.sc
index ae03504..28bac1f 100644
--- a/ld/scripttempl/armbpabi.sc
+++ b/ld/scripttempl/armbpabi.sc
@@ -392,6 +392,10 @@ eval $COMBRELOCCAT <<EOF
   ${REL_SBSS2}
   .rel.bss      0 : { *(.rel.bss${RELOCATING+ .rel.bss.* .rel.gnu.linkonce.b.*}) }
   .rela.bss     0 : { *(.rela.bss${RELOCATING+ .rela.bss.* .rela.gnu.linkonce.b.*}) }
+  .rel.init_array  0 : { *(.rel.init_array) }
+  .rela.init_array 0 : { *(.rela.init_array) }
+  .rel.fini_array  0 : { *(.rel.fini_array) }
+  .rela.fini_array 0 : { *(.rela.fini_array) }
 EOF
 if [ -n "$COMBRELOC" ]; then
 cat <<EOF
@@ -413,5 +417,8 @@ cat <<EOF
   .rel.plt      0 : { *(.rel.plt) }
   .rela.plt     0 : { *(.rela.plt) }
   ${OTHER_PLT_RELOC_SECTIONS}
+  .rel.other    0 : { *(.rel.*) }
+  .rela.other   0 : { *(.rela.*) }
+  .reli.other   0 : { *(.reli.*) }
 }
 EOF
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 5388bd1..a87bcc0 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -81,6 +81,8 @@
    %m			print register mask for ldm/stm instruction
    %C			print the PSR sub type.
    %F			print the COUNT field of a LFM/SFM instruction.
+   %E			print the LSB and WIDTH fields of a BFI or BFC instruction.
+   %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
 IWMMXT specific format options:
    %<bitfield>g         print as an iWMMXt 64-bit register
    %<bitfield>G         print as an iWMMXt general purpose or control register
@@ -118,6 +120,17 @@ static const struct arm_opcode arm_opcodes[] =
   {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
   {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
 
+  /* ARM V6T2 instructions.  */
+  {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"},
+  {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"},
+  {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+  {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "str%cht\t%12-15r, %s"},
+  {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%c%6's%5?hbt\t%12-15r, %s"},
+  {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"},
+  {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"},
+  {ARM_EXT_V6T2, 0x03ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
+  {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
+
   /* ARM V6Z instructions.  */
   {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smi%c\t%e"},
 
@@ -622,6 +635,13 @@ static const struct thumb_opcode thumb_opcodes[] =
 {
   /* Thumb instructions.  */
 
+  /* ARM V6K no-argument instructions.  */
+  {ARM_EXT_V6K, 0xbf00, 0xffff, "nop"},
+  {ARM_EXT_V6K, 0xbf10, 0xffff, "yield"},
+  {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe"},
+  {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi"},
+  {ARM_EXT_V6K, 0xbf40, 0xffff, "sev"},
+
   /* ARM V6.  */
   {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f"},
   {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f"},
@@ -929,7 +949,13 @@ print_insn_arm (pc, info, given)
 	  && info->mach != bfd_mach_arm_iWMMXt)
 	insn = insn + IWMMXT_INSN_COUNT;
 
-      if ((given & insn->mask) == insn->value)
+      if ((given & insn->mask) == insn->value
+	  /* Special case: an instruction with all bits set in the condition field
+	     (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
+	     or by the catchall at the end of the table.  */
+	  && ((given & 0xF0000000) != 0xF0000000
+	      || (insn->mask & 0xF0000000) == 0xF0000000
+	      || (insn->mask == 0 && insn->value == 0)))
 	{
 	  char * c;
 
@@ -1613,6 +1639,32 @@ print_insn_arm (pc, info, given)
 			}
 			break;
 
+		      case 'E':
+			/* LSB and WIDTH fields of BFI or BFC.  The machine-
+			   language instruction encodes LSB and MSB.  */
+			{
+			  long msb = (given & 0x001f0000) >> 16;
+			  long lsb = (given & 0x00000f80) >> 7;
+
+			  long width = msb - lsb + 1;
+			  if (width > 0)
+			    func (stream, "#%lu, #%lu", lsb, width);
+			  else
+			    func (stream, "(invalid: %lu:%lu)", lsb, msb);
+			}
+			break;
+
+		      case 'V':
+			/* 16-bit unsigned immediate from a MOVT or MOVW
+			   instruction, encoded in bits 0:11 and 15:19.  */
+			{
+			  long hi = (given & 0x000f0000) >> 4;
+			  long lo = (given & 0x00000fff);
+			  long imm16 = hi | lo;
+			  func (stream, "#%lu\t; 0x%lx", imm16, imm16);
+			}
+			break;
+
 		      default:
 			abort ();
 		      }
diff --git a/opcodes/po/es.gmo b/opcodes/po/es.gmo
index 8382c26..b4084c5 100644
--- a/opcodes/po/es.gmo
+++ b/opcodes/po/es.gmo
diff --git a/opcodes/po/fr.gmo b/opcodes/po/fr.gmo
index 20c7012..47a17c6 100644
--- a/opcodes/po/fr.gmo
+++ b/opcodes/po/fr.gmo