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| author | Maciej W. Rozycki <macro@redhat.com> | 2024-06-13 14:01:54 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@redhat.com> | 2024-06-13 14:01:54 +0100 |
| commit | 84baa5fe937543578159de698cbb8c5f2e7a57c6 (patch) | |
| tree | 372b7130ab4385544b25687a0ffcd1a3554c632e | |
| parent | 5a011d5b86bea5af144f7242192b21e18c349142 (diff) | |
| download | gdb-84baa5fe937543578159de698cbb8c5f2e7a57c6.zip gdb-84baa5fe937543578159de698cbb8c5f2e7a57c6.tar.gz gdb-84baa5fe937543578159de698cbb8c5f2e7a57c6.tar.bz2 | |
MIPS/opcodes: Update INSN_CHIP_MASK for INSN_ALLEGREX
An update has been missed with commit df18f71b565c ("Add MIPS Allegrex
CPU as a MIPS2-based CPU") for INSN_CHIP_MASK to include INSN_ALLEGREX.
Fix it.
| -rw-r--r-- | include/opcode/mips.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 230b2a0..39c20a8 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1225,7 +1225,7 @@ static const unsigned int mips_isa_table[] = { #undef ISAF /* Masks used for Chip specific instructions. */ -#define INSN_CHIP_MASK 0xc7ff4f60 +#define INSN_CHIP_MASK 0xcfff4f60 /* Cavium Networks Octeon instructions. */ #define INSN_OCTEON 0x00000800 |