s390: Simplify (dis)assembly of insn operands with const bits

Simplify assembly and disassembly of extended mnemonics with operands
with constant ORed bits:
Their instruction template already contains the respective constant
operand bits, as they are significant to distinguish the extended from
their base mnemonic. Operands are ORed into the instruction template.
Therefore it is not necessary to OR the constant bits into the operand
value during assembly in s390_insert_operand.
Additionally the constant operand bits from the instruction template
can be used to mask them from the operand value during disassembly in
s390_print_insn_with_opcode. For now do so for non-length unsigned
integer operands only.

The separate instruction formats need to be retained, as their masks
differ, which is relevant during disassembly to distinguish the base
and extended mnemonics from each other.

This affects the following extended mnemonics:
- vfaebs, vfaehs, vfaefs
- vfaezb, vfaezh, vfaezf
- vfaezbs, vfaezhs, vfaezfs
- vstrcbs, vstrchs, vstrcfs
- vstrczb, vstrczh, vstrczf
- vstrczbs, vstrczhs, vstrczfs
- wcefb, wcdgb
- wcelfb, wcdlgb
- wcfeb, wcgdb
- wclfeb, wclgdb
- wfisb, wfidb, wfixb
- wledb, wflrd, wflrx

include/
	* opcode/s390.h (S390_OPERAND_OR1, S390_OPERAND_OR2,
	S390_OPERAND_OR8): Remove.

opcodes/
	* s390-opc.c (U4_OR1_24, U4_OR2_24, U4_OR8_28): Remove.
	(INSTR_VRR_VVV0U1, INSTR_VRR_VVV0U2, INSTR_VRR_VVV0U3): Define
	as INSTR_VRR_VVV0U0 while retaining respective insn fmt mask.
	(INSTR_VRR_VV0UU8): Define as INSTR_VRR_VV0UU while retaining
	respective insn fmt mask.
	(INSTR_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB3):
	Define as INSTR_VRR_VVVU0VB while retaining respective insn fmt
	mask.
	* s390-dis.c (s390_print_insn_with_opcode): Mask constant
	operand bits set in insn template of non-length unsigned
	integer operands.

gas/
	* config/tc-s390.c (s390_insert_operand): Do not OR constant
	operand value bits.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit a3f1e7c56a60573562e8578ae8b675ec1f4448e7)

4 files changed, 17 insertions, 34 deletions

diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c
index 659c6af..75e1011 100644
--- a/gas/config/tc-s390.c
+++ b/gas/config/tc-s390.c
@@ -795,13 +795,6 @@ s390_insert_operand (unsigned char *insn,
       uval &= 0xf;
     }
 
-  if (operand->flags & S390_OPERAND_OR1)
-    uval |= 1;
-  if (operand->flags & S390_OPERAND_OR2)
-    uval |= 2;
-  if (operand->flags & S390_OPERAND_OR8)
-    uval |= 8;
-
   /* Duplicate the GPR/VR operand at bit pos 12 to 16.  */
   if (operand->flags & S390_OPERAND_CP16)
     {
diff --git a/include/opcode/s390.h b/include/opcode/s390.h
index e5dfcb2..8de0370 100644
--- a/include/opcode/s390.h
+++ b/include/opcode/s390.h
@@ -193,8 +193,4 @@ extern const struct s390_operand s390_operands[];
 
 #define S390_OPERAND_CP16 0x1000
 
-#define S390_OPERAND_OR1 0x2000
-#define S390_OPERAND_OR2 0x4000
-#define S390_OPERAND_OR8 0x8000
-
 #endif /* S390_H */
diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c
index ee2f2cb..852d2f6 100644
--- a/opcodes/s390-dis.c
+++ b/opcodes/s390-dis.c
@@ -299,12 +299,14 @@ s390_print_insn_with_opcode (bfd_vma memaddr,
 	{
 	  enum disassembler_style style;
 
-	  if (flags & S390_OPERAND_OR1)
-	    val.u &= ~1;
-	  if (flags & S390_OPERAND_OR2)
-	    val.u &= ~2;
-	  if (flags & S390_OPERAND_OR8)
-	    val.u &= ~8;
+	  if (!(flags & S390_OPERAND_LENGTH))
+	    {
+	      union operand_value insn_opval;
+
+	      /* Mask any constant operand bits set in insn template.  */
+	      insn_opval = s390_extract_operand (opcode->opcode, operand);
+	      val.u &= ~insn_opval.u;
+	    }
 
 	  if ((opcode->flags & S390_INSTR_FLAG_OPTPARM)
 	      && val.u == 0
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 10482fb..987004d 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -208,17 +208,9 @@ const struct s390_operand s390_operands[] =
   { 4, 20, 0 },
 #define U4_24       (U4_20 + 1)   /* 4 bit unsigned value starting at 24 */
   { 4, 24, 0 },
-#define U4_OR1_24   (U4_24 + 1)   /* 4 bit unsigned value ORed with 1 */
-  { 4, 24, S390_OPERAND_OR1 },	  /* starting at 24 */
-#define U4_OR2_24   (U4_OR1_24+1) /* 4 bit unsigned value ORed with 2 */
-  { 4, 24, S390_OPERAND_OR2 },    /* starting at 24 */
-#define U4_OR3_24   (U4_OR2_24+1) /* 4 bit unsigned value ORed with 3 */
-  { 4, 24, S390_OPERAND_OR1 | S390_OPERAND_OR2 }, /* starting at 24 */
-#define U4_28       (U4_OR3_24+1) /* 4 bit unsigned value starting at 28 */
+#define U4_28       (U4_24+1)     /* 4 bit unsigned value starting at 28 */
   { 4, 28, 0 },
-#define U4_OR8_28   (U4_28 + 1)   /* 4 bit unsigned value ORed with 8 */
-  { 4, 28, S390_OPERAND_OR8 },    /* starting at 28 */
-#define U4_32       (U4_OR8_28+1) /* 4 bit unsigned value starting at 32 */
+#define U4_32       (U4_28+1)     /* 4 bit unsigned value starting at 32 */
   { 4, 32, 0 },
 #define U4_36       (U4_32 + 1)   /* 4 bit unsigned value starting at 36 */
   { 4, 36, 0 },
@@ -512,23 +504,23 @@ unused_s390_operands_static_asserts (void)
 #define INSTR_VRR_VRR      6, { V_8,R_12,R_16,0,0,0 }            /* e.g. vlvgp */
 #define INSTR_VRR_VVV0U    6, { V_8,V_12,V_16,U4_32,0,0 }        /* e.g. vmrh  */
 #define INSTR_VRR_VVV0U0   6, { V_8,V_12,V_16,U4_24,0,0 }        /* e.g. vfaeb */
-#define INSTR_VRR_VVV0U1   6, { V_8,V_12,V_16,U4_OR1_24,0,0 }    /* e.g. vfaebs*/
-#define INSTR_VRR_VVV0U2   6, { V_8,V_12,V_16,U4_OR2_24,0,0 }    /* e.g. vfaezb*/
-#define INSTR_VRR_VVV0U3   6, { V_8,V_12,V_16,U4_OR3_24,0,0 }    /* e.g. vfaezbs*/
+#define INSTR_VRR_VVV0U1   INSTR_VRR_VVV0U0                      /* e.g. vfaebs*/
+#define INSTR_VRR_VVV0U2   INSTR_VRR_VVV0U0                      /* e.g. vfaezb*/
+#define INSTR_VRR_VVV0U3   INSTR_VRR_VVV0U0                      /* e.g. vfaezbs*/
 #define INSTR_VRR_VVV      6, { V_8,V_12,V_16,0,0,0 }            /* e.g. vmrhb */
 #define INSTR_VRR_VVV2     6, { V_8,V_CP16_12,0,0,0,0 }          /* e.g. vnot  */
 #define INSTR_VRR_VV0U     6, { V_8,V_12,U4_32,0,0,0 }           /* e.g. vseg  */
 #define INSTR_VRR_VV0U2    6, { V_8,V_12,U4_24,0,0,0 }           /* e.g. vistrb*/
 #define INSTR_VRR_VV0UU    6, { V_8,V_12,U4_28,U4_24,0,0 }       /* e.g. vcdgb */
 #define INSTR_VRR_VV0UU2   6, { V_8,V_12,U4_32,U4_28,0,0 }       /* e.g. wfc */
-#define INSTR_VRR_VV0UU8   6, { V_8,V_12,U4_OR8_28,U4_24,0,0 }   /* e.g. wcdgb */
+#define INSTR_VRR_VV0UU8   INSTR_VRR_VV0UU                       /* e.g. wcdgb */
 #define INSTR_VRR_VV       6, { V_8,V_12,0,0,0,0 }               /* e.g. vsegb */
 #define INSTR_VRR_VVVUU0V  6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */
 #define INSTR_VRR_VVVU0V   6, { V_8,V_12,V_16,V_32,U4_20,0 }     /* e.g. vac   */
 #define INSTR_VRR_VVVU0VB  6, { V_8,V_12,V_16,V_32,U4_24,0 }     /* e.g. vstrcb*/
-#define INSTR_VRR_VVVU0VB1 6, { V_8,V_12,V_16,V_32,U4_OR1_24,0 } /* e.g. vstrcbs*/
-#define INSTR_VRR_VVVU0VB2 6, { V_8,V_12,V_16,V_32,U4_OR2_24,0 } /* e.g. vstrczb*/
-#define INSTR_VRR_VVVU0VB3 6, { V_8,V_12,V_16,V_32,U4_OR3_24,0 } /* e.g. vstrczbs*/
+#define INSTR_VRR_VVVU0VB1 INSTR_VRR_VVVU0VB                     /* e.g. vstrcbs*/
+#define INSTR_VRR_VVVU0VB2 INSTR_VRR_VVVU0VB                     /* e.g. vstrczb*/
+#define INSTR_VRR_VVVU0VB3 INSTR_VRR_VVVU0VB                     /* e.g. vstrczbs*/
 #define INSTR_VRR_VVV0V    6, { V_8,V_12,V_16,V_32,0,0 }         /* e.g. vacq  */
 #define INSTR_VRR_VVV0U0U  6, { V_8,V_12,V_16,U4_32,U4_24,0 }    /* e.g. vfae  */
 #define INSTR_VRR_VVVV     6, { V_8,V_12,V_16,V_32,0,0 }         /* e.g. vfmadb*/