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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-06-30 23:30:58 +0200 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-07-01 07:32:20 -0600 |
| commit | 9fdc1b157b6e72f7dd98851a240c5fdb386a558e (patch) | |
| tree | 377b6bbc7d238a0325589f6029b4554ae516553a | |
| parent | d556141eb12bc75f78000facd899322096800091 (diff) | |
| download | gdb-9fdc1b157b6e72f7dd98851a240c5fdb386a558e.zip gdb-9fdc1b157b6e72f7dd98851a240c5fdb386a558e.tar.gz gdb-9fdc1b157b6e72f7dd98851a240c5fdb386a558e.tar.bz2 | |
binutils: NEWS: Announce new RISC-V vector crypto extensions
This commit adds the recently added support of the RISC-V vector crypto
extensions to the NEWS file.
binutils/ChangeLog:
* NEWS: Announce new RISC-V vector crypto extensions.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
| -rw-r--r-- | binutils/NEWS | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/binutils/NEWS b/binutils/NEWS index 2e8d51d..834e648 100644 --- a/binutils/NEWS +++ b/binutils/NEWS @@ -23,6 +23,8 @@ * The RISC-V port now supports the following new standard extensions: - Zicond (conditional zero instructions) - Zfa (additional floating-point instructions) + - Zvbb, Zvbc, Zvkg, Zvkned, Zvknh[ab], Zvksed, Zvksh, Zvkn, Zvknc, Zvkng, + Zvks, Zvksc, Zvkg, Zvkt (vector crypto instructions) * The RISC-V port now supports the following vendor-defined extensions: - XVentanaCondOps |