/* Definitions of target machine for GNU compiler, for IBM RS/6000. Copyright (C) 2002-2015 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see . */ /* IBM 128-bit floating point. IFmode and KFmode use the fractional float support in order to declare 3 128-bit floating point types. */ FRACTIONAL_FLOAT_MODE (IF, 106, 16, ibm_extended_format); /* Explicit IEEE 128-bit floating point. */ FRACTIONAL_FLOAT_MODE (KF, 113, 16, ieee_quad_format); /* 128-bit floating point. ABI_V4 uses IEEE quad, AIX/Darwin adjust this in rs6000_option_override_internal. */ FLOAT_MODE (TF, 16, ieee_quad_format); /* Add any extra modes needed to represent the condition code. For the RS/6000, we need separate modes when unsigned (logical) comparisons are being done and we need a separate mode for floating-point. We also use a mode for the case when we are comparing the results of two comparisons, as then only the EQ bit is valid in the register. */ CC_MODE (CCUNS); CC_MODE (CCFP); CC_MODE (CCEQ); /* Vector modes. */ VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */ VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ VECTOR_MODE (INT, DI, 1); VECTOR_MODE (INT, TI, 1); VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */ VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ /* Replacement for TImode that only is allowed in GPRs. We also use PTImode for quad memory atomic operations to force getting an even/odd register combination. */ PARTIAL_INT_MODE (TI, 128, PTI);