; Options for the RISC-V port of the compiler
;
; Copyright (C) 2011-2024 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
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; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3.  If not see
; <http://www.gnu.org/licenses/>.

HeaderInclude
config/riscv/riscv-opts.h

mbig-endian
Target RejectNegative Mask(BIG_ENDIAN)
Assume target CPU is configured as big endian.

mlittle-endian
Target RejectNegative InverseMask(BIG_ENDIAN)
Assume target CPU is configured as little endian.

mbranch-cost=
Target RejectNegative Joined UInteger Var(riscv_branch_cost)
-mbranch-cost=N	Set the cost of branches to roughly N instructions.

mplt
Target Alias(fplt)
This option is deprecated; use -fplt or -fno-plt instead.

mabi=
Target RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32) Negative(mabi=)
Specify integer and floating-point calling convention.

mpreferred-stack-boundary=
Target RejectNegative Joined UInteger Var(riscv_preferred_stack_boundary_arg)
Attempt to keep stack aligned to this power of 2.

Enum
Name(abi_type) Type(enum riscv_abi_type)
Supported ABIs (for use with the -mabi= option):

EnumValue
Enum(abi_type) String(ilp32) Value(ABI_ILP32)

EnumValue
Enum(abi_type) String(ilp32e) Value(ABI_ILP32E)

EnumValue
Enum(abi_type) String(ilp32f) Value(ABI_ILP32F)

EnumValue
Enum(abi_type) String(ilp32d) Value(ABI_ILP32D)

EnumValue
Enum(abi_type) String(lp64) Value(ABI_LP64)

EnumValue
Enum(abi_type) String(lp64e) Value(ABI_LP64E)

EnumValue
Enum(abi_type) String(lp64f) Value(ABI_LP64F)

EnumValue
Enum(abi_type) String(lp64d) Value(ABI_LP64D)

mfdiv
Target Mask(FDIV)
Use hardware floating-point divide and square root instructions.

mdiv
Target Mask(DIV)
Use hardware instructions for integer division.

march=
Target RejectNegative Joined Negative(march=) Var(riscv_arch_string) Save
-march=	Generate code for given RISC-V ISA (e.g. RV64IM).  ISA strings must be
lower-case.

march=help
Target RejectNegative
-march=help	Print supported -march extensions.

; -print-supported-extensions and --print-supported-extensions are added for
; clang compatibility.
print-supported-extensions
Target Undocumented RejectNegative Alias(march=help)

-print-supported-extensions
Target Undocumented RejectNegative Alias(march=help)

mtune=
Target RejectNegative Joined Var(riscv_tune_string) Save
-mtune=PROCESSOR	Optimize the output for PROCESSOR.

mcpu=
Target RejectNegative Joined Var(riscv_cpu_string) Save
-mcpu=PROCESSOR	Use architecture of and optimize the output for PROCESSOR.

msmall-data-limit=
Target Joined UInteger Var(g_switch_value) Init(8)
-msmall-data-limit=N	Put global and static data smaller than <number> bytes into a special section (on some targets).

msave-restore
Target Mask(SAVE_RESTORE)
Use smaller but slower prologue and epilogue code.

mshorten-memrefs
Target Var(riscv_mshorten_memrefs) Init(1)
Convert BASE + LARGE_OFFSET addresses to NEW_BASE + SMALL_OFFSET to allow more
memory accesses to be generated as compressed instructions.  Currently targets
32-bit integer load/stores.

mcmodel=
Target RejectNegative Joined Enum(code_model) Var(riscv_cmodel) Init(TARGET_DEFAULT_CMODEL) Save
Specify the code model.

mstrict-align
Target Mask(STRICT_ALIGN) Save
Do not generate unaligned memory accesses.

mscalar-strict-align
Target Save Alias(mstrict-align)
Do not generate unaligned scalar memory accesses.

mvector-strict-align
Target Save Var(rvv_vector_strict_align) Init(1)
Do not create element-misaligned vector memory accesses.

Enum
Name(code_model) Type(enum riscv_code_model)
Known code models (for use with the -mcmodel= option):

EnumValue
Enum(code_model) String(medlow) Value(CM_MEDLOW)

EnumValue
Enum(code_model) String(medany) Value(CM_MEDANY)

EnumValue
Enum(code_model) String(large) Value(CM_LARGE)

mexplicit-relocs
Target Mask(EXPLICIT_RELOCS)
Use %reloc() operators, rather than assembly macros, to load addresses.

mrelax
Target Var(riscv_mrelax) Init(1)
Take advantage of linker relaxations to reduce the number of instructions
required to materialize symbol addresses.

mcsr-check
Target Var(riscv_mcsr_check) Init(0)
Enable the CSR checking for the ISA-dependent CSR and the read-only CSR.
The ISA-dependent CSR are only valid when the specific ISA is set.  The
read-only CSR can not be written by the CSR instructions.

momit-leaf-frame-pointer
Target Mask(OMIT_LEAF_FRAME_POINTER) Save
Omit the frame pointer in leaf functions.

Mask(64BIT)

Mask(MUL)

Mask(ATOMIC)

Mask(HARD_FLOAT)

Mask(DOUBLE_FLOAT)

Mask(RVC)

Mask(RVE)

Mask(VECTOR)

Mask(FULL_V)

mriscv-attribute
Target Var(riscv_emit_attribute_p) Init(-1)
Emit RISC-V ELF attribute.

malign-data=
Target RejectNegative Joined Var(riscv_align_data_type) Enum(riscv_align_data) Init(riscv_align_data_type_xlen)
Use the given data alignment.

Enum
Name(riscv_align_data) Type(enum riscv_align_data)
Known data alignment choices (for use with the -malign-data= option):

EnumValue
Enum(riscv_align_data) String(xlen) Value(riscv_align_data_type_xlen)

EnumValue
Enum(riscv_align_data) String(natural) Value(riscv_align_data_type_natural)

mstack-protector-guard=
Target RejectNegative Joined Enum(stack_protector_guard) Var(riscv_stack_protector_guard) Init(SSP_GLOBAL)
Use given stack-protector guard.

Enum
Name(stack_protector_guard) Type(enum stack_protector_guard)
Valid arguments to -mstack-protector-guard=:

EnumValue
Enum(stack_protector_guard) String(tls) Value(SSP_TLS)

EnumValue
Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)

mstack-protector-guard-reg=
Target RejectNegative Joined Var(riscv_stack_protector_guard_reg_str)
Use the given base register for addressing the stack-protector guard.

TargetVariable
int riscv_stack_protector_guard_reg = 0

mstack-protector-guard-offset=
Target RejectNegative Joined Integer Var(riscv_stack_protector_guard_offset_str)
Use the given offset for addressing the stack-protector guard.

TargetVariable
long riscv_stack_protector_guard_offset = 0

TargetVariable
int riscv_zi_subext

Mask(ZICSR)       Var(riscv_zi_subext)

Mask(ZIFENCEI)    Var(riscv_zi_subext)

Mask(ZIHINTNTL)   Var(riscv_zi_subext)

Mask(ZIHINTPAUSE) Var(riscv_zi_subext)

Mask(ZICOND)      Var(riscv_zi_subext)

Mask(ZICCAMOA)    Var(riscv_zi_subext)

Mask(ZICCIF)      Var(riscv_zi_subext)

Mask(ZICCLSM)     Var(riscv_zi_subext)

Mask(ZICCRSE)     Var(riscv_zi_subext)

TargetVariable
int riscv_za_subext

Mask(ZAWRS)  Var(riscv_za_subext)

Mask(ZAAMO)  Var(riscv_za_subext)

Mask(ZALRSC) Var(riscv_za_subext)

Mask(ZABHA) Var(riscv_za_subext)

Mask(ZACAS) Var(riscv_za_subext)

Mask(ZA64RS)  Var(riscv_za_subext)

Mask(ZA128RS) Var(riscv_za_subext)

TargetVariable
int riscv_zb_subext

Mask(ZBA) Var(riscv_zb_subext)

Mask(ZBB) Var(riscv_zb_subext)

Mask(ZBC) Var(riscv_zb_subext)

Mask(ZBS) Var(riscv_zb_subext)

TargetVariable
int riscv_zinx_subext

Mask(ZFINX)    Var(riscv_zinx_subext)

Mask(ZDINX)    Var(riscv_zinx_subext)

Mask(ZHINX)    Var(riscv_zinx_subext)

Mask(ZHINXMIN) Var(riscv_zinx_subext)

TargetVariable
int riscv_zk_subext

Mask(ZBKB)  Var(riscv_zk_subext)

Mask(ZBKC)  Var(riscv_zk_subext)

Mask(ZBKX)  Var(riscv_zk_subext)

Mask(ZKNE)  Var(riscv_zk_subext)

Mask(ZKND)  Var(riscv_zk_subext)

Mask(ZKNH)  Var(riscv_zk_subext)

Mask(ZKR)   Var(riscv_zk_subext)

Mask(ZKSED) Var(riscv_zk_subext)

Mask(ZKSH)  Var(riscv_zk_subext)

Mask(ZKT)   Var(riscv_zk_subext)

TargetVariable
int riscv_vector_elen_flags

Mask(VECTOR_ELEN_32)    Var(riscv_vector_elen_flags)

Mask(VECTOR_ELEN_64)    Var(riscv_vector_elen_flags)

Mask(VECTOR_ELEN_FP_32) Var(riscv_vector_elen_flags)

Mask(VECTOR_ELEN_FP_64) Var(riscv_vector_elen_flags)

Mask(VECTOR_ELEN_FP_16) Var(riscv_vector_elen_flags)

Mask(VECTOR_ELEN_BF_16) Var(riscv_vector_elen_flags)

TargetVariable
int riscv_zvl_flags

Mask(ZVL32B)    Var(riscv_zvl_flags)

Mask(ZVL64B)    Var(riscv_zvl_flags)

Mask(ZVL128B)   Var(riscv_zvl_flags)

Mask(ZVL256B)   Var(riscv_zvl_flags)

Mask(ZVL512B)   Var(riscv_zvl_flags)

Mask(ZVL1024B)  Var(riscv_zvl_flags)

Mask(ZVL2048B)  Var(riscv_zvl_flags)

Mask(ZVL4096B)  Var(riscv_zvl_flags)

Mask(ZVL8192B)  Var(riscv_zvl_flags)

Mask(ZVL16384B) Var(riscv_zvl_flags)

Mask(ZVL32768B) Var(riscv_zvl_flags)

Mask(ZVL65536B) Var(riscv_zvl_flags)

TargetVariable
int riscv_zvb_subext

Mask(ZVBB) Var(riscv_zvb_subext)

Mask(ZVBC) Var(riscv_zvb_subext)

Mask(ZVKB) Var(riscv_zvb_subext)

TargetVariable
int riscv_zvk_subext

Mask(ZVKG)   Var(riscv_zvk_subext)

Mask(ZVKNED) Var(riscv_zvk_subext)

Mask(ZVKNHA) Var(riscv_zvk_subext)

Mask(ZVKNHB) Var(riscv_zvk_subext)

Mask(ZVKSED) Var(riscv_zvk_subext)

Mask(ZVKSH)  Var(riscv_zvk_subext)

Mask(ZVKN)   Var(riscv_zvk_subext)

Mask(ZVKNC)  Var(riscv_zvk_subext)

Mask(ZVKNG)  Var(riscv_zvk_subext)

Mask(ZVKS)   Var(riscv_zvk_subext)

Mask(ZVKSC)  Var(riscv_zvk_subext)

Mask(ZVKSG)  Var(riscv_zvk_subext)

Mask(ZVKT)   Var(riscv_zvk_subext)

TargetVariable
int riscv_zicmo_subext

Mask(ZICBOZ) Var(riscv_zicmo_subext)

Mask(ZICBOM) Var(riscv_zicmo_subext)

Mask(ZICBOP) Var(riscv_zicmo_subext)

Mask(ZIC64B) Var(riscv_zicmo_subext)

TargetVariable
int riscv_mop_subext

Mask(ZIMOP) Var(riscv_mop_subext)

Mask(ZCMOP) Var(riscv_mop_subext)

TargetVariable
int riscv_zf_subext

Mask(ZFBFMIN)  Var(riscv_zf_subext)

Mask(ZFHMIN)  Var(riscv_zf_subext)

Mask(ZFH)     Var(riscv_zf_subext)

Mask(ZVFBFMIN) Var(riscv_zf_subext)

Mask(ZVFBFWMA) Var(riscv_zf_subext)

Mask(ZVFHMIN) Var(riscv_zf_subext)

Mask(ZVFH)    Var(riscv_zf_subext)

TargetVariable
int riscv_zfa_subext

Mask(ZFA) Var(riscv_zfa_subext)

TargetVariable
int riscv_zm_subext

Mask(ZMMUL) Var(riscv_zm_subext)

TargetVariable
int riscv_zc_subext

Mask(ZCA)  Var(riscv_zc_subext)

Mask(ZCB)  Var(riscv_zc_subext)

Mask(ZCE)  Var(riscv_zc_subext)

Mask(ZCF)  Var(riscv_zc_subext)

Mask(ZCD)  Var(riscv_zc_subext)

Mask(ZCMP) Var(riscv_zc_subext)

Mask(ZCMT) Var(riscv_zc_subext)

Mask(XCVBI) Var(riscv_xcv_subext)

TargetVariable
int riscv_sv_subext

Mask(SVINVAL) Var(riscv_sv_subext)

Mask(SVNAPOT) Var(riscv_sv_subext)

Mask(SVVPTC) Var(riscv_sv_subext)

TargetVariable
int riscv_ztso_subext

Mask(ZTSO) Var(riscv_ztso_subext)

TargetVariable
int riscv_xcv_subext

Mask(XCVMAC) Var(riscv_xcv_subext)

Mask(XCVALU) Var(riscv_xcv_subext)

Mask(XCVELW) Var(riscv_xcv_subext)

Mask(XCVSIMD) Var(riscv_xcv_subext)

TargetVariable
int riscv_xthead_subext

Mask(XTHEADBA)      Var(riscv_xthead_subext)

Mask(XTHEADBB)      Var(riscv_xthead_subext)

Mask(XTHEADBS)      Var(riscv_xthead_subext)

Mask(XTHEADCMO)     Var(riscv_xthead_subext)

Mask(XTHEADCONDMOV) Var(riscv_xthead_subext)

Mask(XTHEADFMEMIDX) Var(riscv_xthead_subext)

Mask(XTHEADFMV)     Var(riscv_xthead_subext)

Mask(XTHEADINT)     Var(riscv_xthead_subext)

Mask(XTHEADMAC)     Var(riscv_xthead_subext)

Mask(XTHEADMEMIDX)  Var(riscv_xthead_subext)

Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)

Mask(XTHEADSYNC)    Var(riscv_xthead_subext)

Mask(XTHEADVECTOR)  Var(riscv_xthead_subext)

TargetVariable
int riscv_xventana_subext

Mask(XVENTANACONDOPS) Var(riscv_xventana_subext)

TargetVariable
int riscv_sifive_subext

Mask(XSFVCP) Var(riscv_sifive_subext)

Mask(XSFCEASE) Var(riscv_sifive_subext)

Mask(XSFVQMACCQOQ) Var(riscv_sifive_subext)

Mask(XSFVQMACCDOD) Var(riscv_sifive_subext)

Mask(XSFVFNRCLIPXFQF) Var(riscv_sifive_subext)

TargetVariable
int riscv_fmv_priority = 0

Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):

EnumValue
Enum(isa_spec_class) String(2.2) Value(ISA_SPEC_CLASS_2P2)

EnumValue
Enum(isa_spec_class) String(20190608) Value(ISA_SPEC_CLASS_20190608)

EnumValue
Enum(isa_spec_class) String(20191213) Value(ISA_SPEC_CLASS_20191213)

misa-spec=
Target RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) Init(TARGET_DEFAULT_ISA_SPEC)
Set the version of RISC-V ISA spec.

mmovcc
Target Var(TARGET_MOVCC)
Enable conditional moves unconditionally.

minline-atomics
Target Var(TARGET_INLINE_SUBWORD_ATOMIC) Init(1)
Always inline subword atomic operations.

minline-strcmp
Target Var(riscv_inline_strcmp) Init(1)
Inline strcmp calls if possible.

minline-strncmp
Target Var(riscv_inline_strncmp) Init(1)
Inline strncmp calls if possible.

minline-strlen
Target Var(riscv_inline_strlen) Init(1)
Inline strlen calls if possible.

-param=riscv-strcmp-inline-limit=
Target RejectNegative Joined UInteger Var(riscv_strcmp_inline_limit) Init(64)
Max number of bytes to compare as part of inlined strcmp/strncmp routines (default: 64).

Enum
Name(rvv_max_lmul) Type(enum rvv_max_lmul_enum)
The RVV possible LMUL (-mrvv-max-lmul=):

EnumValue
Enum(rvv_max_lmul) String(m1) Value(RVV_M1)

EnumValue
Enum(rvv_max_lmul) String(m2) Value(RVV_M2)

EnumValue
Enum(rvv_max_lmul) String(m4) Value(RVV_M4)

EnumValue
Enum(rvv_max_lmul) String(m8) Value(RVV_M8)

EnumValue
Enum(rvv_max_lmul) String(dynamic) Value(RVV_DYNAMIC)

mrvv-max-lmul=
Target RejectNegative Joined Enum(rvv_max_lmul) Var(rvv_max_lmul) Init(RVV_M1)
-mrvv-max-lmul=<string>	Set the RVV LMUL of auto-vectorization.

madjust-lmul-cost
Target Var(TARGET_ADJUST_LMUL_COST) Init(0)

Enum
Name(vsetvl_strategy) Type(enum vsetvl_strategy_enum)
Valid arguments to -param=vsetvl-strategy=:

EnumValue
Enum(vsetvl_strategy) String(optim) Value(VSETVL_OPT)

EnumValue
Enum(vsetvl_strategy) String(simple) Value(VSETVL_SIMPLE)

EnumValue
Enum(vsetvl_strategy) String(optim-no-fusion) Value(VSETVL_OPT_NO_FUSION)

-param=vsetvl-strategy=
Target Undocumented RejectNegative Joined Enum(vsetvl_strategy) Var(vsetvl_strategy) Init(VSETVL_OPT)
-param=vsetvl-strategy=<string>	Set the optimization level of VSETVL insert pass.

Enum
Name(stringop_strategy) Type(enum stringop_strategy_enum)
Valid arguments to -mstringop-strategy=:

EnumValue
Enum(stringop_strategy) String(auto) Value(STRATEGY_AUTO)

EnumValue
Enum(stringop_strategy) String(libcall) Value(STRATEGY_LIBCALL)

EnumValue
Enum(stringop_strategy) String(scalar) Value(STRATEGY_SCALAR)

EnumValue
Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR)

mstringop-strategy=
Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO)
Specify stringop expansion strategy.

Enum
Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum)
The possible RVV vector register lengths:

EnumValue
Enum(rvv_vector_bits) String(scalable) Value(RVV_VECTOR_BITS_SCALABLE)

EnumValue
Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL)

mrvv-vector-bits=
Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_SCALABLE)
-mrvv-vector-bits=<string>	Set the kind of bits for an RVV vector register.

Enum
Name(tls_type) Type(enum riscv_tls_type)
The possible TLS dialects:

EnumValue
Enum(tls_type) String(trad) Value(TLS_TRADITIONAL)

EnumValue
Enum(tls_type) String(desc) Value(TLS_DESCRIPTORS)

mtls-dialect=
Target RejectNegative Joined Enum(tls_type) Var(riscv_tls_dialect) Init(TLS_TRADITIONAL) Save
Specify TLS dialect.

mfence-tso
Target Var(TARGET_FENCE_TSO) Init(1)
Specifies whether the fence.tso instruction should be used.

mautovec-segment
Target Integer Var(riscv_mautovec_segment) Init(1)
Enable (default) or disable generation of vector segment load/store instructions.