; Generated by "genstr" from the template "loongarch.opt.in" ; and definitions from "loongarch-strings" and "isa-evolution.in". ; ; Please do not edit this file directly. ; It will be automatically updated during a gcc build ; if you change "loongarch.opt.in", "loongarch-strings", or ; "isa-evolution.in". ; ; Copyright (C) 2021-2024 Free Software Foundation, Inc. ; ; This file is part of GCC. ; ; GCC is free software; you can redistribute it and/or modify it under ; the terms of the GNU General Public License as published by the Free ; Software Foundation; either version 3, or (at your option) any later ; version. ; ; GCC is distributed in the hope that it will be useful, but WITHOUT ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ; License for more details. ; ; You should have received a copy of the GNU General Public License ; along with GCC; see the file COPYING3. If not see ; . ; HeaderInclude config/loongarch/loongarch-opts.h HeaderInclude config/loongarch/loongarch-str.h TargetVariable unsigned int recip_mask = 0 ; ISA related options ;; Base ISA Enum Name(isa_base) Type(int) Basic ISAs of LoongArch: EnumValue Enum(isa_base) String(la64) Value(ISA_BASE_LA64) ;; ISA extensions / adjustments Enum Name(isa_ext_fpu) Type(int) FPU types of LoongArch: EnumValue Enum(isa_ext_fpu) String(none) Value(ISA_EXT_NONE) EnumValue Enum(isa_ext_fpu) String(32) Value(ISA_EXT_FPU32) EnumValue Enum(isa_ext_fpu) String(64) Value(ISA_EXT_FPU64) mfpu= Target RejectNegative Joined ToLower Enum(isa_ext_fpu) Var(la_opt_fpu) Init(M_OPT_UNSET) Save -mfpu=FPU Generate code for the given FPU. mfpu=0 Target RejectNegative Alias(mfpu=,none) msoft-float Target Driver Defer Var(la_deferred_options) RejectNegative Negative(msingle-float) Prevent the use of all hardware floating-point instructions. msingle-float Target Driver Defer Var(la_deferred_options) RejectNegative Negative(mdouble-float) Restrict the use of hardware floating-point instructions to 32-bit operations. mdouble-float Target Driver Defer Var(la_deferred_options) RejectNegative Negative(msoft-float) Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations. Enum Name(isa_ext_simd) Type(int) SIMD extension levels of LoongArch: EnumValue Enum(isa_ext_simd) String(none) Value(ISA_EXT_NONE) EnumValue Enum(isa_ext_simd) String(lsx) Value(ISA_EXT_SIMD_LSX) EnumValue Enum(isa_ext_simd) String(lasx) Value(ISA_EXT_SIMD_LASX) msimd= Target RejectNegative Joined ToLower Enum(isa_ext_simd) Var(la_opt_simd) Init(M_OPT_UNSET) Save -msimd=SIMD Generate code for the given SIMD extension. mlsx Target Driver Defer Var(la_deferred_options) Enable LoongArch SIMD Extension (LSX, 128-bit). mlasx Target Driver Defer Var(la_deferred_options) Enable LoongArch Advanced SIMD Extension (LASX, 256-bit). ;; Base target models (implies ISA & tune parameters) Enum Name(cpu_type) Type(int) LoongArch CPU types: EnumValue Enum(cpu_type) String(native) Value(CPU_NATIVE) EnumValue Enum(cpu_type) String(abi-default) Value(CPU_ABI_DEFAULT) EnumValue Enum(cpu_type) String(loongarch64) Value(CPU_LOONGARCH64) EnumValue Enum(cpu_type) String(la464) Value(CPU_LA464) EnumValue Enum(cpu_type) String(la664) Value(CPU_LA664) march= Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) Init(M_OPT_UNSET) Save -march=PROCESSOR Generate code for the given PROCESSOR ISA. mtune= Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_tune) Init(M_OPT_UNSET) Save -mtune=PROCESSOR Generate optimized code for PROCESSOR. ; ABI related options ; (ISA constraints on ABI are handled dynamically) ;; Base ABI Enum Name(abi_base) Type(int) Base ABI types for LoongArch: EnumValue Enum(abi_base) String(lp64d) Value(ABI_BASE_LP64D) EnumValue Enum(abi_base) String(lp64f) Value(ABI_BASE_LP64F) EnumValue Enum(abi_base) String(lp64s) Value(ABI_BASE_LP64S) mabi= Target RejectNegative Joined ToLower Enum(abi_base) Var(la_opt_abi_base) Init(M_OPT_UNSET) -mabi=BASEABI Generate code that conforms to the given BASEABI. ;; ABI Extension Variable int la_opt_abi_ext = M_OPT_UNSET mbranch-cost= Target RejectNegative Joined UInteger Var(la_branch_cost) Save -mbranch-cost=COST Set the cost of branches to roughly COST instructions. mcheck-zero-division Target Mask(CHECK_ZERO_DIV) Save Trap on integer divide by zero. mcond-move-int Target Mask(COND_MOVE_INT) Save Conditional moves for integral are enabled. mcond-move-float Target Mask(COND_MOVE_FLOAT) Save Conditional moves for float are enabled. mmemcpy Target Mask(MEMCPY) Save Prevent optimizing block moves, which is also the default behavior of -Os. mstrict-align Target Mask(STRICT_ALIGN) Save Do not generate unaligned memory accesses. mmax-inline-memcpy-size= Target Joined RejectNegative UInteger Var(la_max_inline_memcpy_size) Init(1024) Save -mmax-inline-memcpy-size=SIZE Set the max size of memcpy to inline, default is 1024. Enum Name(explicit_relocs) Type(int) The code model option names for -mexplicit-relocs: EnumValue Enum(explicit_relocs) String(auto) Value(EXPLICIT_RELOCS_AUTO) EnumValue Enum(explicit_relocs) String(none) Value(EXPLICIT_RELOCS_NONE) EnumValue Enum(explicit_relocs) String(always) Value(EXPLICIT_RELOCS_ALWAYS) mexplicit-relocs= Target RejectNegative Joined Enum(explicit_relocs) Var(la_opt_explicit_relocs) Init(M_OPT_UNSET) Use %reloc() assembly operators. mexplicit-relocs Target Alias(mexplicit-relocs=, always, none) Use %reloc() assembly operators (for backward compatibility). mrecip Target RejectNegative Var(la_recip) Save Generate approximate reciprocal divide and square root for better throughput. mrecip= Target RejectNegative Joined Var(la_recip_name) Save Control generation of reciprocal estimates. ; The code model option names for -mcmodel. Enum Name(cmodel) Type(int) The code model option names for -mcmodel: EnumValue Enum(cmodel) String(normal) Value(CMODEL_NORMAL) EnumValue Enum(cmodel) String(tiny) Value(CMODEL_TINY) EnumValue Enum(cmodel) String(tiny-static) Value(CMODEL_TINY_STATIC) EnumValue Enum(cmodel) String(medium) Value(CMODEL_MEDIUM) EnumValue Enum(cmodel) String(large) Value(CMODEL_LARGE) EnumValue Enum(cmodel) String(extreme) Value(CMODEL_EXTREME) mcmodel= Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) Init(M_OPT_UNSET) Save Specify the code model. mdirect-extern-access Target Mask(DIRECT_EXTERN_ACCESS) Save Avoid using the GOT to access external symbols. mrelax Target Mask(LINKER_RELAXATION) Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. mpass-mrelax-to-as Driver Var(la_pass_mrelax_to_as) Init(HAVE_AS_MRELAX_OPTION) Pass -mrelax or -mno-relax option to the assembler. -param=loongarch-vect-unroll-limit= Target Joined UInteger Var(la_vect_unroll_limit) Init(6) IntegerRange(1, 64) Param Used to limit unroll factor which indicates how much the autovectorizer may unroll a loop. The default value is 6. -param=loongarch-vect-issue-info= Target Undocumented Joined UInteger Var(la_vect_issue_info) Init(4) IntegerRange(1, 64) Param Indicate how many non memory access vector instructions can be issued per cycle, it's used in unroll factor determination for autovectorizer. The default value is 4. ; Features added during ISA evolution. This concept is different from ISA ; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the ; explanation. These features may be implemented and enumerated with ; CPUCFG independently, so we use bit flags to specify them. TargetVariable HOST_WIDE_INT la_isa_evolution = 0 mfrecipe Target Mask(ISA_FRECIPE) Var(la_isa_evolution) Support frecipe.{s/d} and frsqrte.{s/d} instructions. mdiv32 Target Mask(ISA_DIV32) Var(la_isa_evolution) Support div.w[u] and mod.w[u] instructions with inputs not sign-extended. mlam-bh Target Mask(ISA_LAM_BH) Var(la_isa_evolution) Support am{swap/add}[_db].{b/h} instructions. mlamcas Target Mask(ISA_LAMCAS) Var(la_isa_evolution) Support amcas[_db].{b/h/w/d} instructions. mld-seq-sa Target Mask(ISA_LD_SEQ_SA) Var(la_isa_evolution) Do not need load-load barriers (dbar 0x700).