; Options for the Synopsys DesignWare ARC port of the compiler ; ; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; ; GCC is free software; you can redistribute it and/or modify it under ; the terms of the GNU General Public License as published by the Free ; Software Foundation; either version 3, or (at your option) any later ; version. ; ; GCC is distributed in the hope that it will be useful, but WITHOUT ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ; License for more details. ; ; You should have received a copy of the GNU General Public License ; along with GCC; see the file COPYING3. If not see ; . HeaderInclude config/arc/arc-opts.h mbig-endian Target RejectNegative Mask(BIG_ENDIAN) Compile code for big endian mode. mlittle-endian Target RejectNegative InverseMask(BIG_ENDIAN) Compile code for little endian mode. This is the default. mno-cond-exec Target RejectNegative Mask(NO_COND_EXEC) Disable ARCompact specific pass to generate conditional execution instructions. mA6 Target Generate ARCompact 32-bit code for ARC600 processor. mARC600 Target Same as -mA6. mARC601 Target Generate ARCompact 32-bit code for ARC601 processor. mA7 Target Generate ARCompact 32-bit code for ARC700 processor. mARC700 Target Same as -mA7. mjli-always Target Mask(JLI_ALWAYS) Force all calls to be made via a jli instruction. mmpy-option= Target RejectNegative Joined Enum(arc_mpy) Var(arc_mpy_option) Init(DEFAULT_arc_mpy_option) -mmpy-option=MPY Compile ARCv2 code with a multiplier design option. Enum Name(arc_mpy) Type(int) EnumValue Enum(arc_mpy) String(0) Value(0) EnumValue Enum(arc_mpy) String(none) Value(0) Canonical EnumValue Enum(arc_mpy) String(1) Value(1) EnumValue Enum(arc_mpy) String(w) Value(1) Canonical EnumValue Enum(arc_mpy) String(2) Value(2) EnumValue Enum(arc_mpy) String(mpy) Value(2) EnumValue Enum(arc_mpy) String(wlh1) Value(2) Canonical EnumValue Enum(arc_mpy) String(3) Value(3) EnumValue Enum(arc_mpy) String(wlh2) Value(3) Canonical EnumValue Enum(arc_mpy) String(4) Value(4) EnumValue Enum(arc_mpy) String(wlh3) Value(4) Canonical EnumValue Enum(arc_mpy) String(5) Value(5) EnumValue Enum(arc_mpy) String(wlh4) Value(5) Canonical EnumValue Enum(arc_mpy) String(6) Value(6) EnumValue Enum(arc_mpy) String(wlh5) Value(6) Canonical EnumValue Enum(arc_mpy) String(7) Value(7) EnumValue Enum(arc_mpy) String(plus_dmpy) Value(7) Canonical EnumValue Enum(arc_mpy) String(8) Value(8) EnumValue Enum(arc_mpy) String(plus_macd) Value(8) Canonical EnumValue Enum(arc_mpy) String(9) Value(9) EnumValue Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical mdiv-rem Target Mask(DIVREM) Enable DIV-REM instructions for ARCv2. mcode-density Target Mask(CODE_DENSITY) Enable code density instructions for ARCv2. mmixed-code Target Ignore Does nothing. Preserved for backward compatibility. ; We use an explict definition for the negative form because that is the ; actually interesting option, and we want that to have its own comment. mvolatile-cache Target RejectNegative Mask(VOLATILE_CACHE_SET) Use ordinarily cached memory accesses for volatile references. mno-volatile-cache Target RejectNegative InverseMask(VOLATILE_CACHE_SET) Enable cache bypass for volatile references. mbarrel-shifter Target Mask(BARREL_SHIFTER) Generate instructions supported by barrel shifter. mnorm Target Mask(NORM_SET) Generate norm instruction. mswap Target Mask(SWAP_SET) Generate swap instruction. mmul64 Target Mask(MUL64_SET) Generate mul64 and mulu64 instructions. mno-mpy Target Mask(NOMPY_SET) Warn(%qs is deprecated) Do not generate mpy instructions for ARC700. mea Target Mask(EA_SET) Generate extended arithmetic instructions, only valid for ARC700. msoft-float Target Mask(0) Dummy flag. This is the default unless FPX switches are provided explicitly. mlong-calls Target Mask(LONG_CALLS_SET) Generate call insns as register indirect calls. mno-brcc Target Mask(NO_BRCC_SET) Do no generate BRcc instructions in arc_reorg. msdata Target InverseMask(NO_SDATA_SET) Generate sdata references. This is the default, unless you compile for PIC. mmillicode Target Mask(MILLICODE_THUNK_SET) Generate millicode thunks. mspfp Target Mask(SPFP_COMPACT_SET) FPX: Generate Single Precision FPX (compact) instructions. mspfp-compact Target Mask(SPFP_COMPACT_SET) MaskExists FPX: Generate Single Precision FPX (compact) instructions. mspfp-fast Target Mask(SPFP_FAST_SET) FPX: Generate Single Precision FPX (fast) instructions. margonaut Target Mask(ARGONAUT_SET) FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions. mdpfp Target Mask(DPFP_COMPACT_SET) FPX: Generate Double Precision FPX (compact) instructions. mdpfp-compact Target Mask(DPFP_COMPACT_SET) MaskExists FPX: Generate Double Precision FPX (compact) instructions. mdpfp-fast Target Mask(DPFP_FAST_SET) FPX: Generate Double Precision FPX (fast) instructions. mno-dpfp-lrsr Target Mask(DPFP_DISABLE_LRSR) Disable LR and SR instructions from using FPX extension aux registers. msimd Target Mask(SIMD_SET) Enable generation of ARC SIMD instructions via target-specific builtins. mcpu= Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE) -mcpu=CPU Compile code for ARC variant CPU. msize-level= Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1) Size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os. misize Target PchIgnore Var(TARGET_DUMPISIZE) Annotate assembler instructions with estimated addresses. mmultcost= Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1) Cost to assume for a multiply instruction, with 4 being equal to a normal insn. mtune= Target RejectNegative ToLower Joined Var(arc_tune) Enum(arc_tune_attr) Init(ARC_TUNE_NONE) -mtune=TUNE Tune code for given ARC variant. Enum Name(arc_tune_attr) Type(int) EnumValue Enum(arc_tune_attr) String(arc600) Value(ARC_TUNE_ARC600) EnumValue Enum(arc_tune_attr) String(arc601) Value(ARC_TUNE_ARC600) EnumValue Enum(arc_tune_attr) String(arc7xx) Value(ARC_TUNE_ARC7XX) EnumValue Enum(arc_tune_attr) String(arc700) Value(ARC_TUNE_ARC700_4_2_STD) EnumValue Enum(arc_tune_attr) String(arc700-xmac) Value(ARC_TUNE_ARC700_4_2_XMAC) EnumValue Enum(arc_tune_attr) String(arc725d) Value(ARC_TUNE_ARC700_4_2_XMAC) EnumValue Enum(arc_tune_attr) String(arc750d) Value(ARC_TUNE_ARC700_4_2_XMAC) EnumValue Enum(arc_tune_attr) String(core3) Value(ARC_TUNE_CORE_3) mindexed-loads Target Var(TARGET_INDEXED_LOADS) Init(TARGET_INDEXED_LOADS_DEFAULT) Enable the use of indexed loads. mauto-modify-reg Target Var(TARGET_AUTO_MODIFY_REG) Init(TARGET_AUTO_MODIFY_REG_DEFAULT) Enable the use of pre/post modify with register displacement. mmul32x16 Target Mask(MULMAC_32BY16_SET) Generate 32x16 multiply and mac instructions. munalign-prob-threshold= Target Ignore Does nothing. Preserved for backward compatibility. mmedium-calls Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT) Don't use less than 25 bit addressing range for calls. mannotate-align Target Var(TARGET_ANNOTATE_ALIGN) Explain what alignment considerations lead to the decision to make an insn short or long. malign-call Target Ignore Does nothing. Preserved for backward compatibility. mRcq Target Var(TARGET_Rcq) Enable Rcq constraint handling - most short code generation depends on this. mRcw Target Var(TARGET_Rcw) Enable Rcw constraint handling - ccfsm condexec mostly depends on this. mearly-cbranchsi Target Var(TARGET_EARLY_CBRANCHSI) Enable pre-reload use of cbranchsi pattern. mbbit-peephole Target Var(TARGET_BBIT_PEEPHOLE) Enable bbit peephole2. mcase-vector-pcrel Target Var(TARGET_CASE_VECTOR_PC_RELATIVE) Use pc-relative switch case tables - this enables case table shortening. mcompact-casesi Target Warn(%qs is deprecated) Enable compact casesi pattern. mq-class Target Warn(%qs is deprecated) Enable 'q' instruction alternatives. mexpand-adddi Target Warn(%qs is deprecated) Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc. ; Flags used by the assembler, but for which we define preprocessor ; macro symbols as well. mcrc Target Warn(%qs is deprecated) Enable variable polynomial CRC extension. mdsp-packa Target Warn(%qs is deprecated) Enable DSP 3.1 Pack A extensions. mdvbf Target Warn(%qs is deprecated) Enable dual viterbi butterfly extension. mmac-d16 Target Undocumented Warn(%qs is deprecated) mmac-24 Target Undocumented Warn(%qs is deprecated) mtelephony Target RejectNegative Warn(%qs is deprecated) Enable Dual and Single Operand Instructions for Telephony. mxy Target Enable XY Memory extension (DSP version 3). ; ARC700 4.10 extension instructions mlock Target Enable Locked Load/Store Conditional extension. mswape Target Enable swap byte ordering extension instruction. mrtsc Target Warn(%qs is deprecated) Enable 64-bit Time-Stamp Counter extension instruction. EB Target Pass -EB option through to linker. EL Target Pass -EL option through to linker. marclinux Target Pass -marclinux option through to linker. marclinux_prof Target Pass -marclinux_prof option through to linker. ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra. mlra Target Var(arc_lra_flag) Init(1) Save Use LRA instead of reload. mlra-priority-none Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE) Don't indicate any priority with TARGET_REGISTER_PRIORITY. mlra-priority-compact Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT) Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY. mlra-priority-noncompact Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT) Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY. ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS mEA Target multcost= Target RejectNegative Joined matomic Target Mask(ATOMIC) Enable atomic instructions. mll64 Target Mask(LL64) Enable double load/store instructions for ARC HS. mfpu= Target RejectNegative Joined Enum(arc_fpu) Var(arc_fpu_build) Init(DEFAULT_arc_fpu_build) Specify the name of the target floating point configuration. Enum Name(arc_fpu) Type(int) EnumValue Enum(arc_fpu) String(fpus) Value(FPU_FPUS) EnumValue Enum(arc_fpu) String(fpud) Value(FPU_FPUD) EnumValue Enum(arc_fpu) String(fpuda) Value(FPU_FPUDA) EnumValue Enum(arc_fpu) String(fpuda_div) Value(FPU_FPUDA_DIV) EnumValue Enum(arc_fpu) String(fpuda_fma) Value(FPU_FPUDA_FMA) EnumValue Enum(arc_fpu) String(fpuda_all) Value(FPU_FPUDA_ALL) EnumValue Enum(arc_fpu) String(fpus_div) Value(FPU_FPUS_DIV) EnumValue Enum(arc_fpu) String(fpud_div) Value(FPU_FPUD_DIV) EnumValue Enum(arc_fpu) String(fpus_fma) Value(FPU_FPUS_FMA) EnumValue Enum(arc_fpu) String(fpud_fma) Value(FPU_FPUD_FMA) EnumValue Enum(arc_fpu) String(fpus_all) Value(FPU_FPUS_ALL) EnumValue Enum(arc_fpu) String(fpud_all) Value(FPU_FPUD_ALL) mtp-regno= Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(TARGET_ARC_TP_REGNO_DEFAULT) Specify thread pointer register number. mtp-regno=none Target RejectNegative Var(arc_tp_regno,-1) mbitops Target Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT) Enable use of NPS400 bit operations. mcmem Target Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT) Enable use of NPS400 xld/xst extension. munaligned-access Target Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT) Enable unaligned word and halfword accesses to packed data. mirq-ctrl-saved= Target RejectNegative Joined Var(arc_deferred_options) Defer Specifies the registers that the processor saves on an interrupt entry and exit. mrgf-banked-regs= Target RejectNegative Joined Var(arc_deferred_options) Defer Specifies the number of registers replicated in second register bank on entry to fast interrupt. mlpc-width= Target RejectNegative Joined Enum(arc_lpc) Var(arc_lpcwidth) Init(32) Sets LP_COUNT register width. Possible values are 8, 16, 20, 24, 28, and 32. Enum Name(arc_lpc) Type(int) EnumValue Enum(arc_lpc) String(8) Value(8) EnumValue Enum(arc_lpc) String(16) Value(16) EnumValue Enum(arc_lpc) String(20) Value(20) EnumValue Enum(arc_lpc) String(24) Value(24) EnumValue Enum(arc_lpc) String(28) Value(28) EnumValue Enum(arc_lpc) String(32) Value(32) mrf16 Target Mask(RF16) Enable 16-entry register file. mbranch-index Target Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX) Enable use of BI/BIH instructions when available. mcode-density-frame Target Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT) Enable ENTER_S and LEAVE_S opcodes for ARCv2.