From e8e76230ed27bb3a942c0db135089f905c43684f Mon Sep 17 00:00:00 2001 From: Andrew Haley Date: Wed, 12 Aug 2009 16:34:00 +0000 Subject: locks.h: Use atomic builtins For Linux EABI. 2009-08-12 Andrew Haley * sysdep/arm/locks.h: Use atomic builtins For Linux EABI. * configure.ac: Add ATOMICSPEC. * libgcj.spec.in: Likewise. * configure.host (arm*-linux*): Add -Wno-abi to cxxflags. (testsuite/libjava.jvmti/jvmti-interp.exp): Likewise. (testsuite/libjava.jvmti/jvmti.exp): Likewise. (testsuite/libjava.jni/jni.exp): Likewise. Set ATOMICSPEC. Set LDFLAGS to work around libtool feature. From-SVN: r150702 --- libjava/sysdep/arm/locks.h | 58 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 56 insertions(+), 2 deletions(-) (limited to 'libjava/sysdep') diff --git a/libjava/sysdep/arm/locks.h b/libjava/sysdep/arm/locks.h index 1f7763d..2a81e11 100644 --- a/libjava/sysdep/arm/locks.h +++ b/libjava/sysdep/arm/locks.h @@ -13,6 +13,59 @@ details. */ typedef size_t obj_addr_t; /* Integer type big enough for object */ /* address. */ +#if (__ARM_EABI__ && __linux) + +// Atomically replace *addr by new_val if it was initially equal to old. +// Return true if the comparison succeeded. +// Assumed to have acquire semantics, i.e. later memory operations +// cannot execute before the compare_and_swap finishes. +inline static bool +compare_and_swap(volatile obj_addr_t *addr, + obj_addr_t old, + obj_addr_t new_val) +{ + return __sync_bool_compare_and_swap(addr, old, new_val); +} + +// Set *addr to new_val with release semantics, i.e. making sure +// that prior loads and stores complete before this +// assignment. +inline static void +release_set(volatile obj_addr_t *addr, obj_addr_t new_val) +{ + __sync_synchronize(); + *(addr) = new_val; +} + +// Compare_and_swap with release semantics instead of acquire semantics. +// On many architecture, the operation makes both guarantees, so the +// implementation can be the same. +inline static bool +compare_and_swap_release(volatile obj_addr_t *addr, + obj_addr_t old, + obj_addr_t new_val) +{ + return __sync_bool_compare_and_swap(addr, old, new_val); +} + +// Ensure that subsequent instructions do not execute on stale +// data that was loaded from memory before the barrier. +// On X86, the hardware ensures that reads are properly ordered. +inline static void +read_barrier() +{ + __sync_synchronize(); +} + +// Ensure that prior stores to memory are completed with respect to other +// processors. +inline static void +write_barrier() +{ + __sync_synchronize(); +} + +#else /* Atomic compare and exchange. These sequences are not actually atomic; there is a race if *ADDR != OLD_VAL and we are preempted @@ -54,8 +107,8 @@ release_set(volatile obj_addr_t *addr, obj_addr_t new_val) inline static bool compare_and_swap_release(volatile obj_addr_t *addr, - obj_addr_t old, - obj_addr_t new_val) + obj_addr_t old, + obj_addr_t new_val) { return compare_and_swap(addr, old, new_val); } @@ -77,3 +130,4 @@ write_barrier() } #endif +#endif -- cgit v1.1