From 6a8886e45f7eb6684f4e27b9d823ea3d02df787c Mon Sep 17 00:00:00 2001
From: Michael Meissner <meissner@linux.ibm.com>
Date: Mon, 18 Jun 2018 19:10:08 +0000
Subject: re PR target/85358 (PowerPC: Using -mabi=ieeelongdouble -mcpu=power9
 breaks __ibm128)

[gcc]
2018-06-18  Michael Meissner  <meissner@linux.ibm.com>

	PR target/85358
	* config/rs6000/rs6000-modes.def (toplevel): Rework the 128-bit
	floating point modes, so that IFmode is numerically greater than
	TFmode, which is greater than KFmode using FRACTIONAL_FLOAT_MODE
	to declare the ordering.  This prevents IFmode from being
	converted to TFmode when long double is IEEE 128-bit on an ISA 3.0
	machine.  Include rs6000-modes.h to share the fractional values
	between genmodes* and the rest of the compiler.
	(IFmode): Likewise.
	(KFmode): Likewise.
	(TFmode): Likewise.
	* config/rs6000/rs6000-modes.h: New file.
	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Change the
	meaning of rs6000_long_double_size so that 126..128 selects an
	appropriate 128-bit floating point type.
	(rs6000_option_override_internal): Likewise.
	* config/rs6000/rs6000.h (toplevel): Include rs6000-modes.h.
	(TARGET_LONG_DOUBLE_128): Change the meaning of
	rs6000_long_double_size so that 126..128 selects an appropriate
	128-bit floating point type.
	(LONG_DOUBLE_TYPE_SIZE): Update comment.
	* config/rs6000/rs6000.md (trunciftf2): Correct the modes of the
	source and destination to match the standard usage.
	(truncifkf2): Likewise.
	(copysign<mode>3, IEEE iterator): Rework copysign of float128 on
	ISA 2.07 to use an explicit clobber, instead of passing in a
	temporary.
	(copysign<mode>3_soft): Likewise.

[libgcc]
2018-06-18  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/t-float128 (FP128_CFLAGS_SW): Compile float128
	support modules with -mno-gnu-attribute.
	* config/rs6000/t-float128-hw (FP128_CFLAGS_HW): Likewise.

From-SVN: r261712
---
 libgcc/ChangeLog                   | 6 ++++++
 libgcc/config/rs6000/t-float128    | 2 +-
 libgcc/config/rs6000/t-float128-hw | 2 +-
 3 files changed, 8 insertions(+), 2 deletions(-)

(limited to 'libgcc')

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index fc24d8e..65efe17 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-06-18  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/t-float128 (FP128_CFLAGS_SW): Compile float128
+	support modules with -mno-gnu-attribute.
+	* config/rs6000/t-float128-hw (FP128_CFLAGS_HW): Likewise.
+
 2018-06-07  Olivier Hainque  <hainque@adacore.com>
 
 	* config/t-vxworks (LIBGCC_INCLUDES): Add
diff --git a/libgcc/config/rs6000/t-float128 b/libgcc/config/rs6000/t-float128
index 8d52521..d541344 100644
--- a/libgcc/config/rs6000/t-float128
+++ b/libgcc/config/rs6000/t-float128
@@ -59,7 +59,7 @@ fp128_includes		= $(srcdir)/soft-fp/double.h \
 
 # Build the emulator without ISA 3.0 hardware support.
 FP128_CFLAGS_SW		 = -Wno-type-limits -mvsx -mfloat128 \
-			   -mno-float128-hardware \
+			   -mno-float128-hardware -mno-gnu-attribute \
 			   -I$(srcdir)/soft-fp \
 			   -I$(srcdir)/config/rs6000 \
 			   $(FLOAT128_HW_INSNS)
diff --git a/libgcc/config/rs6000/t-float128-hw b/libgcc/config/rs6000/t-float128-hw
index acdddb0..d64ca4d 100644
--- a/libgcc/config/rs6000/t-float128-hw
+++ b/libgcc/config/rs6000/t-float128-hw
@@ -25,7 +25,7 @@ fp128_sed_hw		= -hw
 # Build the hardware support functions with appropriate hardware support
 FP128_CFLAGS_HW		 = -Wno-type-limits -mvsx -mfloat128 \
 			   -mpower8-vector -mpower9-vector \
-			   -mfloat128-hardware \
+			   -mfloat128-hardware -mno-gnu-attribute \
 			   -I$(srcdir)/soft-fp \
 			   -I$(srcdir)/config/rs6000 \
 			   $(FLOAT128_HW_INSNS)
-- 
cgit v1.1


From 1f3fa525537199158db4373efa9d40344632f5f0 Mon Sep 17 00:00:00 2001
From: Than McIntosh <thanm@google.com>
Date: Wed, 20 Jun 2018 21:11:23 +0000
Subject: re PR libgcc/86213 (-fsplit-stack runtime may clobber SSE input param
 reg)

libgcc/:
	PR libgcc/86213
	* generic-morestack.c (allocate_segment): Move calls to getenv and
	getpagesize to __morestack_load_mmap.
	(__morestack_load_mmap) Initialize static_pagesize and
	use_guard_page here so as to avoid clobbering SSE regs during a
	__morestack call.
gcc/testsuite/:
	* gcc.dg/split-8.c: New.

From-SVN: r261823
---
 libgcc/ChangeLog           |  9 +++++++++
 libgcc/generic-morestack.c | 41 ++++++++++++++++-------------------------
 2 files changed, 25 insertions(+), 25 deletions(-)

(limited to 'libgcc')

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 65efe17..238b08f 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,12 @@
+2018-06-20  Than McIntosh  <thanm@google.com>
+
+	PR libgcc/86213
+	* generic-morestack.c (allocate_segment): Move calls to getenv and
+	getpagesize to __morestack_load_mmap.
+	(__morestack_load_mmap) Initialize static_pagesize and
+	use_guard_page here so as to avoid clobbering SSE regs during a
+	__morestack call.
+
 2018-06-18  Michael Meissner  <meissner@linux.ibm.com>
 
 	* config/rs6000/t-float128 (FP128_CFLAGS_SW): Compile float128
diff --git a/libgcc/generic-morestack.c b/libgcc/generic-morestack.c
index 80bfd7f..d70ca09 100644
--- a/libgcc/generic-morestack.c
+++ b/libgcc/generic-morestack.c
@@ -243,6 +243,12 @@ __thread struct initial_sp __morestack_initial_sp
 
 static sigset_t __morestack_fullmask;
 
+/* Page size, as returned from getpagesize(). Set on startup. */
+static unsigned int static_pagesize;
+
+/* Set on startup to non-zero value if SPLIT_STACK_GUARD env var is set. */
+static int use_guard_page;
+
 /* Convert an integer to a decimal string without using much stack
    space.  Return a pointer to the part of the buffer to use.  We this
    instead of sprintf because sprintf will require too much stack
@@ -320,8 +326,6 @@ __morestack_fail (const char *msg, size_t len, int err)
 static struct stack_segment *
 allocate_segment (size_t frame_size)
 {
-  static unsigned int static_pagesize;
-  static int use_guard_page;
   unsigned int pagesize;
   unsigned int overhead;
   unsigned int allocate;
@@ -329,27 +333,6 @@ allocate_segment (size_t frame_size)
   struct stack_segment *pss;
 
   pagesize = static_pagesize;
-  if (pagesize == 0)
-    {
-      unsigned int p;
-
-      pagesize = getpagesize ();
-
-#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
-      p = __sync_val_compare_and_swap (&static_pagesize, 0, pagesize);
-#else
-      /* Just hope this assignment is atomic.  */
-      static_pagesize = pagesize;
-      p = 0;
-#endif
-
-      use_guard_page = getenv ("SPLIT_STACK_GUARD") != 0;
-
-      /* FIXME: I'm not sure this assert should be in the released
-	 code.  */
-      assert (p == 0 || p == pagesize);
-    }
-
   overhead = sizeof (struct stack_segment);
 
   allocate = pagesize;
@@ -815,7 +798,10 @@ __generic_findstack (void *stack)
 /* This function is called at program startup time to make sure that
    mmap, munmap, and getpagesize are resolved if linking dynamically.
    We want to resolve them while we have enough stack for them, rather
-   than calling into the dynamic linker while low on stack space.  */
+   than calling into the dynamic linker while low on stack space.
+   Similarly, invoke getenv here to check for split-stack related control
+   variables, since doing do as part of the __morestack path can result
+   in unwanted use of SSE/AVX registers (see GCC PR 86213). */
 
 void
 __morestack_load_mmap (void)
@@ -825,7 +811,12 @@ __morestack_load_mmap (void)
      TLS accessor function is resolved.  */
   mmap (__morestack_current_segment, 0, PROT_READ, MAP_ANONYMOUS, -1, 0);
   mprotect (NULL, 0, 0);
-  munmap (0, getpagesize ());
+  munmap (0, static_pagesize);
+
+  /* Initialize these values here, so as to avoid dynamic linker
+     activity as part of a __morestack call. */
+  static_pagesize = getpagesize();
+  use_guard_page = getenv ("SPLIT_STACK_GUARD") != 0;
 }
 
 /* This function may be used to iterate over the stack segments.
-- 
cgit v1.1


From d1b0dd54ab096ebd088025215230c968ec6ac4f8 Mon Sep 17 00:00:00 2001
From: Christophe Lyon <christophe.lyon@linaro.org>
Date: Thu, 21 Jun 2018 11:01:05 +0000
Subject: [ARM] libgcc: Remove unsupported code for __ARM_ARCH__ < 4

2018-06-21  Christophe Lyon  <christophe.lyon@linaro.org>

	libgcc/
	* config/arm/ieee754-df.S: Remove code for __ARM_ARCH__ < 4, no
	longer supported.
	* config/arm/ieee754-sf.S: Likewise.

From-SVN: r261840
---
 libgcc/ChangeLog               |  6 ++++
 libgcc/config/arm/ieee754-df.S | 74 +-----------------------------------------
 libgcc/config/arm/ieee754-sf.S | 31 +-----------------
 3 files changed, 8 insertions(+), 103 deletions(-)

(limited to 'libgcc')

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 238b08f..22535f5 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-06-21  Christophe Lyon  <christophe.lyon@linaro.org>
+
+	* config/arm/ieee754-df.S: Remove code for __ARM_ARCH__ < 4, no
+	longer supported.
+	* config/arm/ieee754-sf.S: Likewise.
+
 2018-06-20  Than McIntosh  <thanm@google.com>
 
 	PR libgcc/86213
diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S
index 570e5f6..c6c6067 100644
--- a/libgcc/config/arm/ieee754-df.S
+++ b/libgcc/config/arm/ieee754-df.S
@@ -656,78 +656,8 @@ ARM_FUNC_ALIAS aeabi_dmul muldf3
 	orr	yh, yh, #0x00100000
 	beq	LSYM(Lml_1)
 
-#if __ARM_ARCH__ < 4
-
-	@ Put sign bit in r6, which will be restored in yl later.
-	and   r6, r6, #0x80000000
-
-	@ Well, no way to make it shorter without the umull instruction.
-	stmfd   sp!, {r6, r7, r8, r9, sl, fp}   @ sp -= 24
-	.cfi_remember_state         @ Save the current CFI state.
-	.cfi_adjust_cfa_offset 24   @ CFA is now sp + previousOffset + 24.
-	.cfi_rel_offset r6, 0       @ Registers are saved from sp to sp + 20.
-	.cfi_rel_offset r7, 4
-	.cfi_rel_offset r8, 8
-	.cfi_rel_offset r9, 12
-	.cfi_rel_offset sl, 16
-	.cfi_rel_offset fp, 20
-
-	mov	r7, xl, lsr #16
-	mov	r8, yl, lsr #16
-	mov	r9, xh, lsr #16
-	mov	sl, yh, lsr #16
-	bic	xl, xl, r7, lsl #16
-	bic	yl, yl, r8, lsl #16
-	bic	xh, xh, r9, lsl #16
-	bic	yh, yh, sl, lsl #16
-	mul	ip, xl, yl
-	mul	fp, xl, r8
-	mov	lr, #0
-	adds	ip, ip, fp, lsl #16
-	adc	lr, lr, fp, lsr #16
-	mul	fp, r7, yl
-	adds	ip, ip, fp, lsl #16
-	adc	lr, lr, fp, lsr #16
-	mul	fp, xl, sl
-	mov	r5, #0
-	adds	lr, lr, fp, lsl #16
-	adc	r5, r5, fp, lsr #16
-	mul	fp, r7, yh
-	adds	lr, lr, fp, lsl #16
-	adc	r5, r5, fp, lsr #16
-	mul	fp, xh, r8
-	adds	lr, lr, fp, lsl #16
-	adc	r5, r5, fp, lsr #16
-	mul	fp, r9, yl
-	adds	lr, lr, fp, lsl #16
-	adc	r5, r5, fp, lsr #16
-	mul	fp, xh, sl
-	mul	r6, r9, sl
-	adds	r5, r5, fp, lsl #16
-	adc	r6, r6, fp, lsr #16
-	mul	fp, r9, yh
-	adds	r5, r5, fp, lsl #16
-	adc	r6, r6, fp, lsr #16
-	mul	fp, xl, yh
-	adds	lr, lr, fp
-	mul	fp, r7, sl
-	adcs	r5, r5, fp
-	mul	fp, xh, yl
-	adc	r6, r6, #0
-	adds	lr, lr, fp
-	mul	fp, r9, r8
-	adcs	r5, r5, fp
-	mul	fp, r7, r8
-	adc	r6, r6, #0
-	adds	lr, lr, fp
-	mul	fp, xh, yh
-	adcs	r5, r5, fp
-	adc	r6, r6, #0
-	ldmfd   sp!, {yl, r7, r8, r9, sl, fp}   @ sp += 24
-	.cfi_restore_state   @ Restore the previous CFI state.
-#else
-
 	@ Here is the actual multiplication.
+	@ This code works on architecture versions > 4
 	umull	ip, lr, xl, yl
 	mov	r5, #0
 	umlal	lr, r5, xh, yl
@@ -736,8 +666,6 @@ ARM_FUNC_ALIAS aeabi_dmul muldf3
 	mov	r6, #0
 	umlal	r5, r6, xh, yh
 
-#endif
-
 	@ The LSBs in ip are only significant for the final rounding.
 	@ Fold them into lr.
 	teq	ip, #0
diff --git a/libgcc/config/arm/ieee754-sf.S b/libgcc/config/arm/ieee754-sf.S
index dac3e2e..fbef7bc 100644
--- a/libgcc/config/arm/ieee754-sf.S
+++ b/libgcc/config/arm/ieee754-sf.S
@@ -460,42 +460,13 @@ LSYM(Lml_x):
 	orr	r0, r3, r0, lsr #5
 	orr	r1, r3, r1, lsr #5
 
-#if __ARM_ARCH__ < 4
-
-	@ Put sign bit in r3, which will be restored into r0 later.
-	and	r3, ip, #0x80000000
-
-	@ Well, no way to make it shorter without the umull instruction.
-	do_push	{r3, r4, r5}       @ sp -= 12
-	.cfi_remember_state        @ Save the current CFI state
-	.cfi_adjust_cfa_offset 12  @ CFA is now sp + previousOffset + 12
-	.cfi_rel_offset r3, 0      @ Registers are saved from sp to sp + 8
-	.cfi_rel_offset r4, 4
-	.cfi_rel_offset r5, 8
-
-	mov	r4, r0, lsr #16
-	mov	r5, r1, lsr #16
-	bic	r0, r0, r4, lsl #16
-	bic	r1, r1, r5, lsl #16
-	mul	ip, r4, r5
-	mul	r3, r0, r1
-	mul	r0, r5, r0
-	mla	r0, r4, r1, r0
-	adds	r3, r3, r0, lsl #16
-	adc	r1, ip, r0, lsr #16
-	do_pop	{r0, r4, r5}       @ sp += 12
-	.cfi_restore_state         @ Restore the previous CFI state
-
-#else
-
 	@ The actual multiplication.
+	@ This code works on architecture versions > 4
 	umull	r3, r1, r0, r1
 
 	@ Put final sign in r0.
 	and	r0, ip, #0x80000000
 
-#endif
-
 	@ Adjust result upon the MSB position.
 	cmp	r1, #(1 << 23)
 	do_it	cc, tt
-- 
cgit v1.1


From 9b2e34ef6d56fae077b175d73d6f7440af8eba25 Mon Sep 17 00:00:00 2001
From: Christophe Lyon <christophe.lyon@linaro.org>
Date: Thu, 21 Jun 2018 11:05:36 +0000
Subject: [ARM] Use __ARM_ARCH and __ARM_FEATURE_LDREX instead of __ARM_ARCH__

2018-06-21  Christophe Lyon  <christophe.lyon@linaro.org>

	libatomic/
	* config/arm/arm-config.h (__ARM_ARCH__): Remove definitions, use
	__ARM_ARCH instead. Use __ARM_FEATURE_LDREX to define HAVE_STREX
	and HAVE_STREXBHD

	libgcc/
	* config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use
	__ARM_ARCH and __ARM_FEATURE_CLZ instead.
	(HAVE_ARM_CLZ): Remove definition, use __ARM_FEATURE_CLZ instead.
	* config/arm/ieee754-df.S: Use __ARM_FEATURE_CLZ instead of
	__ARM_ARCH__.
	* config/arm/ieee754-sf.S: Likewise.
	* config/arm/libunwind.S: Use __ARM_ARCH instead of __ARM_ARCH__.

From-SVN: r261841
---
 libgcc/ChangeLog               | 10 +++++
 libgcc/config/arm/ieee754-df.S |  2 +-
 libgcc/config/arm/ieee754-sf.S |  4 +-
 libgcc/config/arm/lib1funcs.S  | 96 ++++++++++--------------------------------
 libgcc/config/arm/libunwind.S  |  2 +-
 5 files changed, 37 insertions(+), 77 deletions(-)

(limited to 'libgcc')

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 22535f5..356721b 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,5 +1,15 @@
 2018-06-21  Christophe Lyon  <christophe.lyon@linaro.org>
 
+	* config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use
+	__ARM_ARCH and __ARM_FEATURE_CLZ instead.
+	(HAVE_ARM_CLZ): Remove definition, use __ARM_FEATURE_CLZ instead.
+	* config/arm/ieee754-df.S: Use __ARM_FEATURE_CLZ instead of
+	__ARM_ARCH__.
+	* config/arm/ieee754-sf.S: Likewise.
+	* config/arm/libunwind.S: Use __ARM_ARCH instead of __ARM_ARCH__.
+
+2018-06-21  Christophe Lyon  <christophe.lyon@linaro.org>
+
 	* config/arm/ieee754-df.S: Remove code for __ARM_ARCH__ < 4, no
 	longer supported.
 	* config/arm/ieee754-sf.S: Likewise.
diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S
index c6c6067..8741aa9 100644
--- a/libgcc/config/arm/ieee754-df.S
+++ b/libgcc/config/arm/ieee754-df.S
@@ -245,7 +245,7 @@ LSYM(Lad_a):
 	@ No rounding necessary since ip will always be 0 at this point.
 LSYM(Lad_l):
 
-#if __ARM_ARCH__ < 5
+#if !defined (__ARM_FEATURE_CLZ)
 
 	teq	xh, #0
 	movne	r3, #20
diff --git a/libgcc/config/arm/ieee754-sf.S b/libgcc/config/arm/ieee754-sf.S
index fbef7bc..d80d5e9 100644
--- a/libgcc/config/arm/ieee754-sf.S
+++ b/libgcc/config/arm/ieee754-sf.S
@@ -175,7 +175,7 @@ LSYM(Lad_a):
 	@ No rounding necessary since r1 will always be 0 at this point.
 LSYM(Lad_l):
 
-#if __ARM_ARCH__ < 5
+#if !defined (__ARM_FEATURE_CLZ)
 
 	movs	ip, r0, lsr #12
 	moveq	r0, r0, lsl #12
@@ -370,7 +370,7 @@ ARM_FUNC_ALIAS aeabi_l2f floatdisf
 	subeq	r3, r3, #(32 << 23)
 2:	sub	r3, r3, #(1 << 23)
 
-#if __ARM_ARCH__ < 5
+#if !defined (__ARM_FEATURE_CLZ)
 
 	mov	r2, #23
 	cmp	ip, #(1 << 16)
diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S
index 04c1b77..b9919aa 100644
--- a/libgcc/config/arm/lib1funcs.S
+++ b/libgcc/config/arm/lib1funcs.S
@@ -74,49 +74,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 
 /* Function end macros.  Variants for interworking.  */
 
-#if defined(__ARM_ARCH_2__)
-# define __ARM_ARCH__ 2
-#endif
-
-#if defined(__ARM_ARCH_3__)
-# define __ARM_ARCH__ 3
-#endif
-
-#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \
-	|| defined(__ARM_ARCH_4T__)
-/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with
-   long multiply instructions.  That includes v3M.  */
-# define __ARM_ARCH__ 4
-#endif
-	
-#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \
-	|| defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \
-	|| defined(__ARM_ARCH_5TEJ__)
-# define __ARM_ARCH__ 5
-#endif
-
-#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
-	|| defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \
-	|| defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \
-	|| defined(__ARM_ARCH_6M__)
-# define __ARM_ARCH__ 6
-#endif
-
-#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
-	|| defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
-	|| defined(__ARM_ARCH_7EM__)
-# define __ARM_ARCH__ 7
-#endif
-
-#if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \
-	|| defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__)
-# define __ARM_ARCH__ 8
-#endif
-
-#ifndef __ARM_ARCH__
-#error Unable to determine architecture.
-#endif
-
 /* There are times when we might prefer Thumb1 code even if ARM code is
    permitted, for example, the code might be smaller, or there might be
    interworking problems with switching to ARM state if interworking is
@@ -135,13 +92,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 
 /* How to return from a function call depends on the architecture variant.  */
 
-#if (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__)
+#if (__ARM_ARCH > 4) || defined(__ARM_ARCH_4T__)
 
 # define RET		bx	lr
 # define RETc(x)	bx##x	lr
 
 /* Special precautions for interworking on armv4t.  */
-# if (__ARM_ARCH__ == 4)
+# if (__ARM_ARCH == 4)
 
 /* Always use bx, not ldr pc.  */
 #  if (defined(__thumb__) || defined(__THUMB_INTERWORK__))
@@ -544,7 +501,7 @@ pc		.req	r15
 /* ------------------------------------------------------------------------ */	
 .macro ARM_DIV_BODY dividend, divisor, result, curbit
 
-#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__)
+#if defined (__ARM_FEATURE_CLZ) && ! defined (__OPTIMIZE_SIZE__)
 
 #if defined (__thumb2__)
 	clz	\curbit, \dividend
@@ -584,8 +541,8 @@ pc		.req	r15
 	.endr
 #endif
 
-#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */
-#if __ARM_ARCH__ >= 5
+#else /* !defined (__ARM_FEATURE_CLZ) || defined (__OPTIMIZE_SIZE__) */
+#if defined (__ARM_FEATURE_CLZ)
 
 	clz	\curbit, \divisor
 	clz	\result, \dividend
@@ -595,7 +552,7 @@ pc		.req	r15
 	mov	\curbit, \curbit, lsl \result
 	mov	\result, #0
 	
-#else /* __ARM_ARCH__ < 5 */
+#else /* !defined (__ARM_FEATURE_CLZ) */
 
 	@ Initially shift the divisor left 3 bits if possible,
 	@ set curbit accordingly.  This allows for curbit to be located
@@ -626,7 +583,7 @@ pc		.req	r15
 
 	mov	\result, #0
 
-#endif /* __ARM_ARCH__ < 5 */
+#endif /* !defined (__ARM_FEATURE_CLZ) */
 
 	@ Division loop
 1:	cmp	\dividend, \divisor
@@ -651,13 +608,13 @@ pc		.req	r15
 	movne	\divisor,  \divisor, lsr #4
 	bne	1b
 
-#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */
+#endif /* !defined (__ARM_FEATURE_CLZ) || defined (__OPTIMIZE_SIZE__) */
 
 .endm
 /* ------------------------------------------------------------------------ */	
 .macro ARM_DIV2_ORDER divisor, order
 
-#if __ARM_ARCH__ >= 5
+#if defined (__ARM_FEATURE_CLZ)
 
 	clz	\order, \divisor
 	rsb	\order, \order, #31
@@ -687,7 +644,7 @@ pc		.req	r15
 /* ------------------------------------------------------------------------ */
 .macro ARM_MOD_BODY dividend, divisor, order, spare
 
-#if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__)
+#if defined(__ARM_FEATURE_CLZ) && ! defined (__OPTIMIZE_SIZE__)
 
 	clz	\order, \divisor
 	clz	\spare, \dividend
@@ -702,15 +659,15 @@ pc		.req	r15
 	subcs	\dividend, \dividend, \divisor, lsl #shift
 	.endr
 
-#else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */
-#if __ARM_ARCH__ >= 5
+#else /* !defined (__ARM_FEATURE_CLZ) || defined (__OPTIMIZE_SIZE__) */
+#if defined (__ARM_FEATURE_CLZ)
 
 	clz	\order, \divisor
 	clz	\spare, \dividend
 	sub	\order, \order, \spare
 	mov	\divisor, \divisor, lsl \order
 	
-#else /* __ARM_ARCH__ < 5 */
+#else /* !defined (__ARM_FEATURE_CLZ) */
 
 	mov	\order, #0
 
@@ -732,7 +689,7 @@ pc		.req	r15
 	addlo	\order, \order, #1
 	blo	1b
 
-#endif /* __ARM_ARCH__ < 5 */
+#endif /* !defined (__ARM_FEATURE_CLZ) */
 
 	@ Perform all needed substractions to keep only the reminder.
 	@ Do comparisons in batch of 4 first.
@@ -770,7 +727,7 @@ pc		.req	r15
 	subhs	\dividend, \dividend, \divisor
 5:
 
-#endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */
+#endif /* !defined (__ARM_FEATURE_CLZ) || defined (__OPTIMIZE_SIZE__) */
 
 .endm
 /* ------------------------------------------------------------------------ */
@@ -1560,7 +1517,7 @@ LSYM(Lover12):
 @ EABI GNU/Linux call to cacheflush syscall.
 	ARM_FUNC_START clear_cache
 	do_push	{r7}
-#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6T2__)
+#if __ARM_ARCH >= 7 || defined(__ARM_ARCH_6T2__)
 	movw	r7, #2
 	movt	r7, #0xf
 #else
@@ -1699,13 +1656,6 @@ LSYM(Lover12):
 
 #endif /* __symbian__ */
 
-#if (__ARM_ARCH_ISA_THUMB == 2	\
-     || (__ARM_ARCH_ISA_ARM	\
-	 && (__ARM_ARCH__ > 5	\
-	     || (__ARM_ARCH__ == 5 && __ARM_ARCH_ISA_THUMB))))
-#define HAVE_ARM_CLZ 1
-#endif
-
 #ifdef L_clzsi2
 #ifdef NOT_ISA_TARGET_32BIT
 FUNC_START clzsi2
@@ -1736,7 +1686,7 @@ FUNC_START clzsi2
 	FUNC_END clzsi2
 #else
 ARM_FUNC_START clzsi2
-# if defined(HAVE_ARM_CLZ)
+# if defined (__ARM_FEATURE_CLZ)
 	clz	r0, r0
 	RET
 # else
@@ -1760,13 +1710,13 @@ ARM_FUNC_START clzsi2
 .align 2
 1:
 .byte 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0
-# endif /* !HAVE_ARM_CLZ */
+# endif /* !defined (__ARM_FEATURE_CLZ) */
 	FUNC_END clzsi2
 #endif
 #endif /* L_clzsi2 */
 
 #ifdef L_clzdi2
-#if !defined(HAVE_ARM_CLZ)
+#if !defined (__ARM_FEATURE_CLZ)
 
 # ifdef NOT_ISA_TARGET_32BIT
 FUNC_START clzdi2
@@ -1800,7 +1750,7 @@ ARM_FUNC_START clzdi2
 # endif
 	FUNC_END clzdi2
 
-#else /* HAVE_ARM_CLZ */
+#else /* defined (__ARM_FEATURE_CLZ) */
 
 ARM_FUNC_START clzdi2
 	cmp	xxh, #0
@@ -1848,7 +1798,7 @@ FUNC_START ctzsi2
 ARM_FUNC_START ctzsi2
 	rsb	r1, r0, #0
 	and	r0, r0, r1
-# if defined(HAVE_ARM_CLZ)
+# if defined (__ARM_FEATURE_CLZ)
 	clz	r0, r0
 	rsb	r0, r0, #31
 	RET
@@ -1873,7 +1823,7 @@ ARM_FUNC_START ctzsi2
 .align 2
 1:
 .byte	27, 28, 29, 29, 30, 30, 30, 30, 31, 31, 31, 31, 31, 31, 31, 31
-# endif /* !HAVE_ARM_CLZ */
+# endif /* !defined (__ARM_FEATURE_CLZ) */
 	FUNC_END ctzsi2
 #endif
 #endif /* L_clzsi2 */
@@ -1887,7 +1837,7 @@ ARM_FUNC_START ctzsi2
    not support Thumb instructions.  (This can be a multilib option).  */
 #if defined __ARM_ARCH_4T__ || defined __ARM_ARCH_5T__\
       || defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__ \
-      || __ARM_ARCH__ >= 6
+      || __ARM_ARCH >= 6
 
 #if defined L_call_via_rX
 
diff --git a/libgcc/config/arm/libunwind.S b/libgcc/config/arm/libunwind.S
index 3302447..50c58dc 100644
--- a/libgcc/config/arm/libunwind.S
+++ b/libgcc/config/arm/libunwind.S
@@ -46,7 +46,7 @@
 	EQUIV SYM (\name), SYM (__\name)
 .endm
 
-#if (__ARM_ARCH__ == 4)
+#if (__ARM_ARCH == 4)
 /* Some coprocessors require armv5t.  We know this code will never be run on
    other cpus.  Tell gas to allow armv5t, but only mark the objects as armv4.
  */
-- 
cgit v1.1


From 1765b0231029c0479ddcf5d54e8f4882c5feda94 Mon Sep 17 00:00:00 2001
From: Rasmus Villemoes <rv@rasmusvillemoes.dk>
Date: Wed, 27 Jun 2018 12:04:25 +0200
Subject: add support for --disable-gcov

For some targets (in my case VxWorks 5.5), libgcov does not compile due
to missing functions and macros such as getpid() and F_OK.

Incidentally, gcc/Makefile.in already contains comments such as

# Install gcov if it was compiled.

but there is no logic in place to actually allow gcov to not be
compiled.

So add an option for disabling build and install of libgcov and the
related host tools.

From-SVN: r262180
---
 libgcc/ChangeLog    |  6 ++++++
 libgcc/Makefile.in  |  8 +++++++-
 libgcc/configure    | 12 ++++++++++++
 libgcc/configure.ac |  5 +++++
 4 files changed, 30 insertions(+), 1 deletion(-)

(limited to 'libgcc')

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 356721b..cef65b5 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-06-27  Rasmus Villemoes  <rv@rasmusvillemoes.dk>
+
+	* configure.ac: Add --disable-gcov option.
+	* configure: Regenerate.
+	* Makefile.in: Honour @enable_gcov@.
+
 2018-06-21  Christophe Lyon  <christophe.lyon@linaro.org>
 
 	* config/arm/lib1funcs.S (__ARM_ARCH__): Remove definitions, use
diff --git a/libgcc/Makefile.in b/libgcc/Makefile.in
index dd8cee9..b7f2055 100644
--- a/libgcc/Makefile.in
+++ b/libgcc/Makefile.in
@@ -36,6 +36,7 @@ SHELL = @SHELL@
 
 cpu_type = @cpu_type@
 enable_shared = @enable_shared@
+enable_gcov = @enable_gcov@
 double_type_size = @double_type_size@
 long_double_type_size = @long_double_type_size@
 decimal_float = @decimal_float@
@@ -941,7 +942,10 @@ libgcc.a libgcov.a libunwind.a libgcc_eh.a:
 
 	$(RANLIB) $@
 
-all: libgcc.a libgcov.a
+all: libgcc.a
+ifeq ($(enable_gcov),yes)
+all: libgcov.a
+endif
 
 ifneq ($(LIBUNWIND),)
 all: libunwind.a
@@ -1164,9 +1168,11 @@ install-leaf: $(install-shared) $(install-libunwind)
 	$(INSTALL_DATA) libgcc.a $(DESTDIR)$(inst_libdir)/
 	chmod 644 $(DESTDIR)$(inst_libdir)/libgcc.a
 	$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc.a
+ifeq ($(enable_libgcov),yes)
 	$(INSTALL_DATA) libgcov.a $(DESTDIR)$(inst_libdir)/
 	chmod 644 $(DESTDIR)$(inst_libdir)/libgcov.a
 	$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcov.a
+endif
 
 	parts="$(INSTALL_PARTS)";				\
 	for file in $$parts; do					\
diff --git a/libgcc/configure b/libgcc/configure
index b2f3f87..7906853 100644
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -620,6 +620,7 @@ build_cpu
 build
 with_aix_soname
 enable_vtable_verify
+enable_gcov
 enable_shared
 libgcc_topdir
 target_alias
@@ -667,6 +668,7 @@ with_target_subdir
 with_cross_host
 with_ld
 enable_shared
+enable_gcov
 enable_vtable_verify
 with_aix_soname
 enable_version_specific_runtime_libs
@@ -1306,6 +1308,7 @@ Optional Features:
   --disable-FEATURE       do not include FEATURE (same as --enable-FEATURE=no)
   --enable-FEATURE[=ARG]  include FEATURE [ARG=yes]
   --disable-shared        don't provide a shared libgcc
+  --disable-gcov          don't provide libgcov and related host tools
   --enable-vtable-verify    Enable vtable verification feature
   --enable-version-specific-runtime-libs    Specify that runtime libraries should be installed in a compiler-specific directory
   --enable-maintainer-mode
@@ -2199,6 +2202,15 @@ fi
 
 
 
+# Check whether --enable-gcov was given.
+if test "${enable_gcov+set}" = set; then :
+  enableval=$enable_gcov;
+else
+  enable_gcov=yes
+fi
+
+
+
 # Check whether --enable-vtable-verify was given.
 if test "${enable_vtable_verify+set}" = set; then :
   enableval=$enable_vtable_verify; case "$enableval" in
diff --git a/libgcc/configure.ac b/libgcc/configure.ac
index b59aa74..9d0bbca 100644
--- a/libgcc/configure.ac
+++ b/libgcc/configure.ac
@@ -68,6 +68,11 @@ AC_ARG_ENABLE(shared,
 ], [enable_shared=yes])
 AC_SUBST(enable_shared)
 
+AC_ARG_ENABLE(gcov,
+[  --disable-gcov          don't provide libgcov and related host tools],
+[], [enable_gcov=yes])
+AC_SUBST(enable_gcov)
+
 AC_ARG_ENABLE(vtable-verify,
 [  --enable-vtable-verify    Enable vtable verification feature ],
 [case "$enableval" in
-- 
cgit v1.1


From b61c9b997ca38a1116cd832b876bd83de383dcea Mon Sep 17 00:00:00 2001
From: Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
Date: Wed, 27 Jun 2018 20:32:27 +0000
Subject: Fix typo in libgcc/Makefile.in

	* Makefile.in (install_leaf): Use enable_gcov instead of
	enable_libgcov.

From-SVN: r262195
---
 libgcc/ChangeLog   | 5 +++++
 libgcc/Makefile.in | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

(limited to 'libgcc')

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index cef65b5..bd75ed2 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-06-27  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+	* Makefile.in (install_leaf): Use enable_gcov instead of
+	enable_libgcov.
+
 2018-06-27  Rasmus Villemoes  <rv@rasmusvillemoes.dk>
 
 	* configure.ac: Add --disable-gcov option.
diff --git a/libgcc/Makefile.in b/libgcc/Makefile.in
index b7f2055..0c5b264 100644
--- a/libgcc/Makefile.in
+++ b/libgcc/Makefile.in
@@ -1168,7 +1168,7 @@ install-leaf: $(install-shared) $(install-libunwind)
 	$(INSTALL_DATA) libgcc.a $(DESTDIR)$(inst_libdir)/
 	chmod 644 $(DESTDIR)$(inst_libdir)/libgcc.a
 	$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc.a
-ifeq ($(enable_libgcov),yes)
+ifeq ($(enable_gcov),yes)
 	$(INSTALL_DATA) libgcov.a $(DESTDIR)$(inst_libdir)/
 	chmod 644 $(DESTDIR)$(inst_libdir)/libgcov.a
 	$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcov.a
-- 
cgit v1.1


From 1c686aa4be2781dd377c30a013638b5289ac23ee Mon Sep 17 00:00:00 2001
From: James Clarke <jrtc27@jrtc27.com>
Date: Thu, 5 Jul 2018 19:23:29 +0000
Subject: dfp.m4 (enable_decimal_float): Enable for x86_64*-*-gnu* to catch
 x86_64 kFreeBSD and Hurd.

config/
	* dfp.m4 (enable_decimal_float): Enable for x86_64*-*-gnu* to
	catch x86_64 kFreeBSD and Hurd.

gcc/
	* configure: Regenerated.

libdecnumber/
	* configure: Regenerated.

libgcc/
	* configure: Regenerated.

From-SVN: r262452
---
 libgcc/ChangeLog | 4 ++++
 libgcc/configure | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

(limited to 'libgcc')

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index bd75ed2..c13bf4c 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,7 @@
+2018-07-05  James Clarke  <jrtc27@jrtc27.com>
+
+	* configure: Regenerated.
+
 2018-06-27  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
 
 	* Makefile.in (install_leaf): Use enable_gcov instead of
diff --git a/libgcc/configure b/libgcc/configure
index 7906853..6eb111d 100644
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -4659,7 +4659,7 @@ else
 
   case $host in
     powerpc*-*-linux* | i?86*-*-linux* | x86_64*-*-linux* | s390*-*-linux* | \
-    i?86*-*-elfiamcu | i?86*-*-gnu* | \
+    i?86*-*-elfiamcu | i?86*-*-gnu* | x86_64*-*-gnu* \
     i?86*-*-mingw* | x86_64*-*-mingw* | \
     i?86*-*-cygwin* | x86_64*-*-cygwin*)
       enable_decimal_float=yes
-- 
cgit v1.1


From 1c1d2d8ca755341f69e945aa2df1a0f74d02abd8 Mon Sep 17 00:00:00 2001
From: Jeff Law <law@gcc.gnu.org>
Date: Thu, 5 Jul 2018 14:28:01 -0600
Subject: Add missing '|' as wrong patch was applied.

From-SVN: r262453
---
 libgcc/configure | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libgcc')

diff --git a/libgcc/configure b/libgcc/configure
index 6eb111d..090e548 100644
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -4659,7 +4659,7 @@ else
 
   case $host in
     powerpc*-*-linux* | i?86*-*-linux* | x86_64*-*-linux* | s390*-*-linux* | \
-    i?86*-*-elfiamcu | i?86*-*-gnu* | x86_64*-*-gnu* \
+    i?86*-*-elfiamcu | i?86*-*-gnu* | x86_64*-*-gnu* | \
     i?86*-*-mingw* | x86_64*-*-mingw* | \
     i?86*-*-cygwin* | x86_64*-*-cygwin*)
       enable_decimal_float=yes
-- 
cgit v1.1


From b72e71a39c33fac823b8f65f43aa15a8bb0ae676 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hongjiu.lu@intel.com>
Date: Fri, 27 Jul 2018 14:40:47 +0000
Subject: i386: Remove _Unwind_Frames_Increment

CET kernel has been changed to place a restore token on shadow stack for
signal handler to enhance security.  It is usually transparent to user
programs since kernel will pop the restore token when signal handler
returns.  But when an exception is thrown from a signal handler, now
we need to remove _Unwind_Frames_Increment to pop the the restore token
from shadow stack.  Otherwise, we get

FAIL: g++.dg/torture/pr85334.C   -O0  execution test
FAIL: g++.dg/torture/pr85334.C   -O1  execution test
FAIL: g++.dg/torture/pr85334.C   -O2  execution test
FAIL: g++.dg/torture/pr85334.C   -O3 -g  execution test
FAIL: g++.dg/torture/pr85334.C   -Os  execution test
FAIL: g++.dg/torture/pr85334.C   -O2 -flto -fno-use-linker-plugin -flto-partition=none  execution test

	PR libgcc/85334
	* config/i386/shadow-stack-unwind.h (_Unwind_Frames_Increment):
	Removed.

From-SVN: r263030
---
 libgcc/ChangeLog                         | 6 ++++++
 libgcc/config/i386/shadow-stack-unwind.h | 5 -----
 2 files changed, 6 insertions(+), 5 deletions(-)

(limited to 'libgcc')

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index c13bf4c..e0db8d1 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-07-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR libgcc/85334
+	* config/i386/shadow-stack-unwind.h (_Unwind_Frames_Increment):
+	Removed.
+
 2018-07-05  James Clarke  <jrtc27@jrtc27.com>
 
 	* configure: Regenerated.
diff --git a/libgcc/config/i386/shadow-stack-unwind.h b/libgcc/config/i386/shadow-stack-unwind.h
index a32f3e7..40f48df 100644
--- a/libgcc/config/i386/shadow-stack-unwind.h
+++ b/libgcc/config/i386/shadow-stack-unwind.h
@@ -49,8 +49,3 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 	}					\
     }						\
     while (0)
-
-/* Increment frame count.  Skip signal frames.  */
-#undef _Unwind_Frames_Increment
-#define _Unwind_Frames_Increment(context, frames) \
-  if (!_Unwind_IsSignalFrame (context)) frames++
-- 
cgit v1.1


From b74159752d6c1f955660e829a17e1aad1cead348 Mon Sep 17 00:00:00 2001
From: Christophe Lyon <christophe.lyon@linaro.org>
Date: Mon, 30 Jul 2018 12:51:42 +0000
Subject: [ARM] libgcc: Fix comment for code working on architectures >= 4.

2018-07-30  Christophe Lyon  <christophe.lyon@linaro.org>

	* config/arm/ieee754-df.S: Fix comment for code working on
	architectures >= 4.
	* config/arm/ieee754-sf.S: Likewise.

From-SVN: r263066
---
 libgcc/ChangeLog               | 6 ++++++
 libgcc/config/arm/ieee754-df.S | 2 +-
 libgcc/config/arm/ieee754-sf.S | 2 +-
 3 files changed, 8 insertions(+), 2 deletions(-)

(limited to 'libgcc')

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index e0db8d1..b8f85b6 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-07-30  Christophe Lyon  <christophe.lyon@linaro.org>
+
+	* config/arm/ieee754-df.S: Fix comment for code working on
+	architectures >= 4.
+	* config/arm/ieee754-sf.S: Likewise.
+
 2018-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR libgcc/85334
diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S
index 8741aa9..7f2afb2 100644
--- a/libgcc/config/arm/ieee754-df.S
+++ b/libgcc/config/arm/ieee754-df.S
@@ -657,7 +657,7 @@ ARM_FUNC_ALIAS aeabi_dmul muldf3
 	beq	LSYM(Lml_1)
 
 	@ Here is the actual multiplication.
-	@ This code works on architecture versions > 4
+	@ This code works on architecture versions >= 4
 	umull	ip, lr, xl, yl
 	mov	r5, #0
 	umlal	lr, r5, xh, yl
diff --git a/libgcc/config/arm/ieee754-sf.S b/libgcc/config/arm/ieee754-sf.S
index d80d5e9..e8ee76e 100644
--- a/libgcc/config/arm/ieee754-sf.S
+++ b/libgcc/config/arm/ieee754-sf.S
@@ -461,7 +461,7 @@ LSYM(Lml_x):
 	orr	r1, r3, r1, lsr #5
 
 	@ The actual multiplication.
-	@ This code works on architecture versions > 4
+	@ This code works on architecture versions >= 4
 	umull	r3, r1, r0, r1
 
 	@ Put final sign in r0.
-- 
cgit v1.1