From c5ed0148347beea1bd34795de146adddd2454c36 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Fri, 11 Jun 2021 15:56:37 +0100 Subject: arm: Fix the mve multilib for the broken cmse support (pr99939). The current CMSE support in the multilib build for "-march=armv8.1-m.main+mve -mfloat-abi=hard -mfpu=auto" is broken as specified in PR99939 and this patch fixes the issue. gcc/testsuite/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/99939 * gcc.target/arm/cmse/cmse-18.c: Add separate scan-assembler directives check for target is v8.1-m.main+mve or not before comparing the assembly output. * gcc.target/arm/cmse/cmse-20.c: New test. libgcc/ChangeLog: 2021-06-11 Srinath Parvathaneni PR target/99939 * config/arm/cmse_nonsecure_call.S: Add __ARM_FEATURE_MVE macro. * config/arm/t-arm: To link cmse.o and cmse_nonsecure_call.o on passing -mcmse option. --- libgcc/config/arm/cmse_nonsecure_call.S | 4 ++-- libgcc/config/arm/t-arm | 5 ++--- 2 files changed, 4 insertions(+), 5 deletions(-) (limited to 'libgcc/config/arm') diff --git a/libgcc/config/arm/cmse_nonsecure_call.S b/libgcc/config/arm/cmse_nonsecure_call.S index 146f3ed..00830ad 100644 --- a/libgcc/config/arm/cmse_nonsecure_call.S +++ b/libgcc/config/arm/cmse_nonsecure_call.S @@ -25,7 +25,7 @@ .syntax unified #ifdef __ARM_PCS_VFP -# if __ARM_FP & 0x8 +# if (__ARM_FP & 0x8) || (__ARM_FEATURE_MVE & 1) .fpu fpv5-d16 # else .fpu fpv4-sp-d16 @@ -59,7 +59,7 @@ vmov s24, s25, r5, r5 vmov s26, s27, r5, r5 vmov s28, s29, r5, r5 vmov s30, s31, r5, r5 -#elif __ARM_FP & 0x08 +#elif (__ARM_FP & 0x8) || (__ARM_FEATURE_MVE & 1) vmov.f64 d9, d8 vmov.f64 d10, d8 vmov.f64 d11, d8 diff --git a/libgcc/config/arm/t-arm b/libgcc/config/arm/t-arm index 3625a25..c1553d4 100644 --- a/libgcc/config/arm/t-arm +++ b/libgcc/config/arm/t-arm @@ -3,18 +3,17 @@ LIB1ASMFUNCS = _thumb1_case_sqi _thumb1_case_uqi _thumb1_case_shi \ _thumb1_case_uhi _thumb1_case_si _speculation_barrier HAVE_CMSE:=$(findstring __ARM_FEATURE_CMSE,$(shell $(gcc_compile_bare) -dM -E - /dev/null 2>/dev/null; echo $$?),0) CMSE_OPTS:=-mcmse endif ifdef HAVE_CMSE -ifndef HAVE_V81M + libgcc-objects += cmse.o cmse_nonsecure_call.o cmse.o: $(srcdir)/config/arm/cmse.c $(gcc_compile) -c $(CMSE_OPTS) $< + cmse_nonsecure_call.o: $(srcdir)/config/arm/cmse_nonsecure_call.S $(gcc_compile) -c $< endif -endif -- cgit v1.1 From 574e7950bd6b34e9e2cacce18c802b45505d1d0a Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 18 Jun 2021 17:16:25 +0100 Subject: arm: add erratum mitigation to __gnu_cmse_nonsecure_call [PR102035] Add the recommended erratum mitigation sequence to __gnu_cmse_nonsecure_call for use on Armv8-m.main devices. Since this is in the library code we cannot know in advance whether the core we are running on will be affected by this, so always enable it. libgcc: PR target/102035 * config/arm/cmse_nonsecure_call.S (__gnu_cmse_nonsecure_call): Add vlldm erratum work-around. --- libgcc/config/arm/cmse_nonsecure_call.S | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'libgcc/config/arm') diff --git a/libgcc/config/arm/cmse_nonsecure_call.S b/libgcc/config/arm/cmse_nonsecure_call.S index 00830ad..c8e0fbb 100644 --- a/libgcc/config/arm/cmse_nonsecure_call.S +++ b/libgcc/config/arm/cmse_nonsecure_call.S @@ -102,6 +102,11 @@ blxns r4 #ifdef __ARM_PCS_VFP vpop.f64 {d8-d15} #else +/* VLLDM erratum mitigation sequence. */ +mrs r5, control +tst r5, #8 /* CONTROL_S.SFPA */ +it ne +.inst.w 0xeeb00a40 /* vmovne s0, s0 */ vlldm sp /* Lazy restore of d0-d16 and FPSCR. */ add sp, sp, #0x88 /* Free space used to save floating point registers. */ #endif /* __ARM_PCS_VFP */ -- cgit v1.1