From f2c2a6fb1e5742d8dac7c906decb7764602d301c Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Wed, 15 May 2019 15:13:31 +0000 Subject: i386: Emulate MMX mmx_pextrw with SSE Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pextrw): Add SSE emulation. From-SVN: r271229 --- gcc/ChangeLog | 5 +++++ gcc/config/i386/mmx.md | 18 +++++++++++------- 2 files changed, 16 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 24b36d8..aa8da14 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,11 @@ 2019-05-15 H.J. Lu PR target/89021 + * config/i386/mmx.md (mmx_pextrw): Add SSE emulation. + +2019-05-15 H.J. Lu + + PR target/89021 * config/i386/sse.md (sse_cvtpi2ps): Changed to define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add SSE emulation. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index c19ee07..ca06845 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1335,16 +1335,20 @@ (set_attr "mode" "DI")]) (define_insn "mmx_pextrw" - [(set (match_operand:SI 0 "register_operand" "=r") + [(set (match_operand:SI 0 "register_operand" "=r,r") (zero_extend:SI (vec_select:HI - (match_operand:V4HI 1 "register_operand" "y") - (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))] - "TARGET_SSE || TARGET_3DNOW_A" - "pextrw\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "mmxcvt") + (match_operand:V4HI 1 "register_operand" "y,Yv") + (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")]))))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" + "@ + pextrw\t{%2, %1, %0|%0, %1, %2} + %vpextrw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64") + (set_attr "type" "mmxcvt,sselog1") (set_attr "length_immediate" "1") - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI")]) (define_expand "mmx_pshufw" [(match_operand:V4HI 0 "register_operand") -- cgit v1.1