From e55a9a6ea2a2e773b590eff00f6fa7b7400d58b3 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 3 Jan 2001 14:52:42 -0800 Subject: alpha.md (addvsi3, addvdi3): New. * config/alpha/alpha.md (addvsi3, addvdi3): New. (negvsi2, negvdi2, subvsi3, subvdi3, mulvsi3, mulvdi3): New. From-SVN: r38676 --- gcc/ChangeLog | 5 +++ gcc/config/alpha/alpha.md | 97 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3446f71..80397ce 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2001-01-03 Richard Henderson + + * config/alpha/alpha.md (addvsi3, addvdi3): New. + (negvsi2, negvdi2, subvsi3, subvdi3, mulvsi3, mulvdi3): New. + 2001-01-03 Franz Sirl * tradcpp.c (main): Make sure finclude() is called with a valid diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 01498f49a..23d9f5ae 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -582,6 +582,20 @@ operands[7] = gen_lowpart (SImode, operands[5]); }") +(define_insn "addvsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") + (match_operand:SI 2 "sext_add_operand" "rI,O"))) + (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1)) + (sign_extend:DI (match_dup 2))) + (sign_extend:DI (plus:SI (match_dup 1) + (match_dup 2)))) + (const_int 0))] + "" + "@ + addlv %r1,%2,%0 + sublv %r1,%n2,%0") + (define_expand "adddi3" [(set (match_operand:DI 0 "register_operand" "") (plus:DI (match_operand:DI 1 "register_operand" "") @@ -723,6 +737,20 @@ s%2addq %1,%3,%0 s%2subq %1,%n3,%0") +(define_insn "addvdi3" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") + (match_operand:DI 2 "sext_add_operand" "rI,O"))) + (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1)) + (sign_extend:TI (match_dup 2))) + (sign_extend:TI (plus:DI (match_dup 1) + (match_dup 2)))) + (const_int 0))] + "" + "@ + addqv %r1,%2,%0 + subqv %r1,%n2,%0") + (define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))] @@ -736,12 +764,30 @@ "" "subl $31,%1,%0") +(define_insn "negvsi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (neg:SI (match_operand:SI 1 "register_operand" "r"))) + (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1))) + (sign_extend:DI (neg:SI (match_dup 1)))) + (const_int 0))] + "" + "sublv $31,%1,%0") + (define_insn "negdi2" [(set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))] "" "subq $31,%1,%0") +(define_insn "negvdi2" + [(set (match_operand:DI 0 "register_operand" "=r") + (neg:DI (match_operand:DI 1 "register_operand" "r"))) + (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1))) + (sign_extend:TI (neg:DI (match_dup 1)))) + (const_int 0))] + "" + "subqv $31,%1,%0") + (define_expand "subsi3" [(set (match_operand:SI 0 "register_operand" "") (minus:SI (match_operand:SI 1 "reg_or_0_operand" "") @@ -780,6 +826,18 @@ "" "subl %r1,%2,%0") +(define_insn "subvsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") + (match_operand:SI 2 "reg_or_8bit_operand" "rI"))) + (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1)) + (sign_extend:DI (match_dup 2))) + (sign_extend:DI (minus:SI (match_dup 1) + (match_dup 2)))) + (const_int 0))] + "" + "sublv %r1,%2,%0") + (define_insn "subdi3" [(set (match_operand:DI 0 "register_operand" "=r") (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") @@ -812,6 +870,18 @@ "" "s%2subq %1,%3,%0") +(define_insn "subvdi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") + (match_operand:DI 2 "reg_or_8bit_operand" "rI"))) + (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1)) + (sign_extend:TI (match_dup 2))) + (sign_extend:TI (minus:DI (match_dup 1) + (match_dup 2)))) + (const_int 0))] + "" + "subqv %r1,%2,%0") + (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") @@ -831,6 +901,20 @@ [(set_attr "type" "imul") (set_attr "opsize" "si")]) +(define_insn "mulvsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") + (match_operand:SI 2 "reg_or_8bit_operand" "rI"))) + (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1)) + (sign_extend:DI (match_dup 2))) + (sign_extend:DI (mult:SI (match_dup 1) + (match_dup 2)))) + (const_int 0))] + "" + "mullv %r1,%2,%0" + [(set_attr "type" "imul") + (set_attr "opsize" "si")]) + (define_insn "muldi3" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ") @@ -839,6 +923,19 @@ "mulq %r1,%2,%0" [(set_attr "type" "imul")]) +(define_insn "mulvdi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ") + (match_operand:DI 2 "reg_or_8bit_operand" "rI"))) + (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1)) + (sign_extend:TI (match_dup 2))) + (sign_extend:TI (mult:DI (match_dup 1) + (match_dup 2)))) + (const_int 0))] + "" + "mulqv %r1,%2,%0" + [(set_attr "type" "imul")]) + (define_insn "umuldi3_highpart" [(set (match_operand:DI 0 "register_operand" "=r") (truncate:DI -- cgit v1.1